2 * Copyright 2021 Advanced Micro Devices, Inc.
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5 * copy of this software and associated documentation files (the "Software"),
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9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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24 #include "amdgpu_psp.h"
25 #include "amdgpu_ucode.h"
26 #include "soc15_common.h"
27 #include "psp_v11_0_8.h"
29 #include "mp/mp_11_0_8_offset.h"
31 static int psp_v11_0_8_ring_init(struct psp_context *psp,
32 enum psp_ring_type ring_type)
35 struct psp_ring *ring;
36 struct amdgpu_device *adev = psp->adev;
40 ring->ring_type = ring_type;
42 /* allocate 4k Page of Local Frame Buffer memory for ring */
43 ring->ring_size = 0x1000;
44 ret = amdgpu_bo_create_kernel(adev, ring->ring_size, PAGE_SIZE,
45 AMDGPU_GEM_DOMAIN_VRAM,
47 &ring->ring_mem_mc_addr,
48 (void **)&ring->ring_mem);
57 static int psp_v11_0_8_ring_stop(struct psp_context *psp,
58 enum psp_ring_type ring_type)
61 struct amdgpu_device *adev = psp->adev;
63 if (amdgpu_sriov_vf(adev)) {
64 /* Write the ring destroy command*/
65 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101,
66 GFX_CTRL_CMD_ID_DESTROY_GPCOM_RING);
67 /* there might be handshake issue with hardware which needs delay */
69 /* Wait for response flag (bit 31) */
70 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_101),
71 0x80000000, 0x80000000, false);
73 /* Write the ring destroy command*/
74 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64,
75 GFX_CTRL_CMD_ID_DESTROY_RINGS);
76 /* there might be handshake issue with hardware which needs delay */
78 /* Wait for response flag (bit 31) */
79 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
80 0x80000000, 0x80000000, false);
86 static int psp_v11_0_8_ring_create(struct psp_context *psp,
87 enum psp_ring_type ring_type)
90 unsigned int psp_ring_reg = 0;
91 struct psp_ring *ring = &psp->km_ring;
92 struct amdgpu_device *adev = psp->adev;
94 if (amdgpu_sriov_vf(adev)) {
95 ret = psp_v11_0_8_ring_stop(psp, ring_type);
97 DRM_ERROR("psp_v11_0_8_ring_stop_sriov failed!\n");
101 /* Write low address of the ring to C2PMSG_102 */
102 psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr);
103 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_102, psp_ring_reg);
104 /* Write high address of the ring to C2PMSG_103 */
105 psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr);
106 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_103, psp_ring_reg);
108 /* Write the ring initialization command to C2PMSG_101 */
109 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101,
110 GFX_CTRL_CMD_ID_INIT_GPCOM_RING);
112 /* there might be handshake issue with hardware which needs delay */
115 /* Wait for response flag (bit 31) in C2PMSG_101 */
116 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_101),
117 0x80000000, 0x8000FFFF, false);
120 /* Wait for sOS ready for ring creation */
121 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
122 0x80000000, 0x80000000, false);
124 DRM_ERROR("Failed to wait for trust OS ready for ring creation\n");
128 /* Write low address of the ring to C2PMSG_69 */
129 psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr);
130 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_69, psp_ring_reg);
131 /* Write high address of the ring to C2PMSG_70 */
132 psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr);
133 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_70, psp_ring_reg);
134 /* Write size of ring to C2PMSG_71 */
135 psp_ring_reg = ring->ring_size;
136 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_71, psp_ring_reg);
137 /* Write the ring initialization command to C2PMSG_64 */
138 psp_ring_reg = ring_type;
139 psp_ring_reg = psp_ring_reg << 16;
140 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, psp_ring_reg);
142 /* there might be handshake issue with hardware which needs delay */
145 /* Wait for response flag (bit 31) in C2PMSG_64 */
146 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
147 0x80000000, 0x8000FFFF, false);
153 static int psp_v11_0_8_ring_destroy(struct psp_context *psp,
154 enum psp_ring_type ring_type)
157 struct psp_ring *ring = &psp->km_ring;
158 struct amdgpu_device *adev = psp->adev;
160 ret = psp_v11_0_8_ring_stop(psp, ring_type);
162 DRM_ERROR("Fail to stop psp ring\n");
164 amdgpu_bo_free_kernel(&adev->firmware.rbuf,
165 &ring->ring_mem_mc_addr,
166 (void **)&ring->ring_mem);
171 static uint32_t psp_v11_0_8_ring_get_wptr(struct psp_context *psp)
174 struct amdgpu_device *adev = psp->adev;
176 if (amdgpu_sriov_vf(adev))
177 data = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_102);
179 data = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67);
184 static void psp_v11_0_8_ring_set_wptr(struct psp_context *psp, uint32_t value)
186 struct amdgpu_device *adev = psp->adev;
188 if (amdgpu_sriov_vf(adev)) {
189 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_102, value);
190 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101,
191 GFX_CTRL_CMD_ID_CONSUME_CMD);
193 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67, value);
196 static const struct psp_funcs psp_v11_0_8_funcs = {
197 .ring_init = psp_v11_0_8_ring_init,
198 .ring_create = psp_v11_0_8_ring_create,
199 .ring_stop = psp_v11_0_8_ring_stop,
200 .ring_destroy = psp_v11_0_8_ring_destroy,
201 .ring_get_wptr = psp_v11_0_8_ring_get_wptr,
202 .ring_set_wptr = psp_v11_0_8_ring_set_wptr,
205 void psp_v11_0_8_set_psp_funcs(struct psp_context *psp)
207 psp->funcs = &psp_v11_0_8_funcs;