drivers/gpu/drm/amd/amdgpu/psp_v11_0.c

   1 /*
   2  * Copyright 2018 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  */
  22
  23 #include <linux/firmware.h>
  24 #include <linux/module.h>
  25 #include <linux/vmalloc.h>
  26
  27 #include "amdgpu.h"
  28 #include "amdgpu_psp.h"
  29 #include "amdgpu_ras.h"
  30 #include "amdgpu_ucode.h"
  31 #include "soc15_common.h"
  32 #include "psp_v11_0.h"
  33
  34 #include "mp/mp_11_0_offset.h"
  35 #include "mp/mp_11_0_sh_mask.h"
  36 #include "gc/gc_9_0_offset.h"
  37 #include "sdma0/sdma0_4_0_offset.h"
  38 #include "nbio/nbio_7_4_offset.h"
  39
  40 #include "oss/osssys_4_0_offset.h"
  41 #include "oss/osssys_4_0_sh_mask.h"
  42
  43 MODULE_FIRMWARE("amdgpu/vega20_sos.bin");
  44 MODULE_FIRMWARE("amdgpu/vega20_asd.bin");
  45 MODULE_FIRMWARE("amdgpu/vega20_ta.bin");
  46 MODULE_FIRMWARE("amdgpu/navi10_sos.bin");
  47 MODULE_FIRMWARE("amdgpu/navi10_asd.bin");
  48 MODULE_FIRMWARE("amdgpu/navi10_ta.bin");
  49 MODULE_FIRMWARE("amdgpu/navi14_sos.bin");
  50 MODULE_FIRMWARE("amdgpu/navi14_asd.bin");
  51 MODULE_FIRMWARE("amdgpu/navi14_ta.bin");
  52 MODULE_FIRMWARE("amdgpu/navi12_sos.bin");
  53 MODULE_FIRMWARE("amdgpu/navi12_asd.bin");
  54 MODULE_FIRMWARE("amdgpu/navi12_ta.bin");
  55 MODULE_FIRMWARE("amdgpu/arcturus_sos.bin");
  56 MODULE_FIRMWARE("amdgpu/arcturus_asd.bin");
  57 MODULE_FIRMWARE("amdgpu/arcturus_ta.bin");
  58 MODULE_FIRMWARE("amdgpu/sienna_cichlid_sos.bin");
  59 MODULE_FIRMWARE("amdgpu/sienna_cichlid_ta.bin");
  60 MODULE_FIRMWARE("amdgpu/navy_flounder_sos.bin");
  61 MODULE_FIRMWARE("amdgpu/navy_flounder_ta.bin");
  62 MODULE_FIRMWARE("amdgpu/vangogh_asd.bin");
  63 MODULE_FIRMWARE("amdgpu/vangogh_toc.bin");
  64 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_sos.bin");
  65 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_ta.bin");
  66
  67 /* address block */
  68 #define smnMP1_FIRMWARE_FLAGS           0x3010024
  69 /* navi10 reg offset define */
  70 #define mmRLC_GPM_UCODE_ADDR_NV10       0x5b61
  71 #define mmRLC_GPM_UCODE_DATA_NV10       0x5b62
  72 #define mmSDMA0_UCODE_ADDR_NV10         0x5880
  73 #define mmSDMA0_UCODE_DATA_NV10         0x5881
  74 /* memory training timeout define */
  75 #define MEM_TRAIN_SEND_MSG_TIMEOUT_US   3000000
  76
  77 /* For large FW files the time to complete can be very long */
  78 #define USBC_PD_POLLING_LIMIT_S 240
  79
  80 static int psp_v11_0_init_microcode(struct psp_context *psp)
  81 {
  82         struct amdgpu_device *adev = psp->adev;
  83         const char *chip_name;
  84         char fw_name[PSP_FW_NAME_LEN];
  85         int err = 0;
  86         const struct ta_firmware_header_v1_0 *ta_hdr;
  87
  88         DRM_DEBUG("\n");
  89
  90         switch (adev->asic_type) {
  91         case CHIP_VEGA20:
  92                 chip_name = "vega20";
  93                 break;
  94         case CHIP_NAVI10:
  95                 chip_name = "navi10";
  96                 break;
  97         case CHIP_NAVI14:
  98                 chip_name = "navi14";
  99                 break;
 100         case CHIP_NAVI12:
 101                 chip_name = "navi12";
 102                 break;
 103         case CHIP_ARCTURUS:
 104                 chip_name = "arcturus";
 105                 break;
 106         case CHIP_SIENNA_CICHLID:
 107                 chip_name = "sienna_cichlid";
 108                 break;
 109         case CHIP_NAVY_FLOUNDER:
 110                 chip_name = "navy_flounder";
 111                 break;
 112         case CHIP_VANGOGH:
 113                 chip_name = "vangogh";
 114                 break;
 115         case CHIP_DIMGREY_CAVEFISH:
 116                 chip_name = "dimgrey_cavefish";
 117                 break;
 118         default:
 119                 BUG();
 120         }
 121
 122
 123         switch (adev->asic_type) {
 124         case CHIP_VEGA20:
 125         case CHIP_ARCTURUS:
 126                 err = psp_init_sos_microcode(psp, chip_name);
 127                 if (err)
 128                         return err;
 129                 err = psp_init_asd_microcode(psp, chip_name);
 130                 if (err)
 131                         return err;
 132                 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ta.bin", chip_name);
 133                 err = request_firmware(&adev->psp.ta_fw, fw_name, adev->dev);
 134                 if (err) {
 135                         release_firmware(adev->psp.ta_fw);
 136                         adev->psp.ta_fw = NULL;
 137                         dev_info(adev->dev,
 138                                  "psp v11.0: Failed to load firmware \"%s\"\n", fw_name);
 139                 } else {
 140                         err = amdgpu_ucode_validate(adev->psp.ta_fw);
 141                         if (err)
 142                                 goto out2;
 143
 144                         ta_hdr = (const struct ta_firmware_header_v1_0 *)adev->psp.ta_fw->data;
 145                         adev->psp.ta_xgmi_ucode_version = le32_to_cpu(ta_hdr->ta_xgmi_ucode_version);
 146                         adev->psp.ta_xgmi_ucode_size = le32_to_cpu(ta_hdr->ta_xgmi_size_bytes);
 147                         adev->psp.ta_xgmi_start_addr = (uint8_t *)ta_hdr +
 148                                 le32_to_cpu(ta_hdr->header.ucode_array_offset_bytes);
 149                         adev->psp.ta_fw_version = le32_to_cpu(ta_hdr->header.ucode_version);
 150                         adev->psp.ta_ras_ucode_version = le32_to_cpu(ta_hdr->ta_ras_ucode_version);
 151                         adev->psp.ta_ras_ucode_size = le32_to_cpu(ta_hdr->ta_ras_size_bytes);
 152                         adev->psp.ta_ras_start_addr = (uint8_t *)adev->psp.ta_xgmi_start_addr +
 153                                 le32_to_cpu(ta_hdr->ta_ras_offset_bytes);
 154                 }
 155                 break;
 156         case CHIP_NAVI10:
 157         case CHIP_NAVI14:
 158         case CHIP_NAVI12:
 159                 err = psp_init_sos_microcode(psp, chip_name);
 160                 if (err)
 161                         return err;
 162                 err = psp_init_asd_microcode(psp, chip_name);
 163                 if (err)
 164                         return err;
 165                 if (amdgpu_sriov_vf(adev))
 166                         break;
 167                 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ta.bin", chip_name);
 168                 err = request_firmware(&adev->psp.ta_fw, fw_name, adev->dev);
 169                 if (err) {
 170                         release_firmware(adev->psp.ta_fw);
 171                         adev->psp.ta_fw = NULL;
 172                         dev_info(adev->dev,
 173                                  "psp v11.0: Failed to load firmware \"%s\"\n", fw_name);
 174                 } else {
 175                         err = amdgpu_ucode_validate(adev->psp.ta_fw);
 176                         if (err)
 177                                 goto out2;
 178
 179                         ta_hdr = (const struct ta_firmware_header_v1_0 *)adev->psp.ta_fw->data;
 180                         adev->psp.ta_hdcp_ucode_version = le32_to_cpu(ta_hdr->ta_hdcp_ucode_version);
 181                         adev->psp.ta_hdcp_ucode_size = le32_to_cpu(ta_hdr->ta_hdcp_size_bytes);
 182                         adev->psp.ta_hdcp_start_addr = (uint8_t *)ta_hdr +
 183                                 le32_to_cpu(ta_hdr->header.ucode_array_offset_bytes);
 184
 185                         adev->psp.ta_fw_version = le32_to_cpu(ta_hdr->header.ucode_version);
 186
 187                         adev->psp.ta_dtm_ucode_version = le32_to_cpu(ta_hdr->ta_dtm_ucode_version);
 188                         adev->psp.ta_dtm_ucode_size = le32_to_cpu(ta_hdr->ta_dtm_size_bytes);
 189                         adev->psp.ta_dtm_start_addr = (uint8_t *)adev->psp.ta_hdcp_start_addr +
 190                                 le32_to_cpu(ta_hdr->ta_dtm_offset_bytes);
 191                 }
 192                 break;
 193         case CHIP_SIENNA_CICHLID:
 194         case CHIP_NAVY_FLOUNDER:
 195         case CHIP_DIMGREY_CAVEFISH:
 196                 err = psp_init_sos_microcode(psp, chip_name);
 197                 if (err)
 198                         return err;
 199                 err = psp_init_ta_microcode(psp, chip_name);
 200                 if (err)
 201                         return err;
 202                 break;
 203         case CHIP_VANGOGH:
 204                 err = psp_init_asd_microcode(psp, chip_name);
 205                 if (err)
 206                         return err;
 207                 err = psp_init_toc_microcode(psp, chip_name);
 208                 if (err)
 209                         return err;
 210                 break;
 211         default:
 212                 BUG();
 213         }
 214
 215         return 0;
 216
 217 out2:
 218         release_firmware(adev->psp.ta_fw);
 219         adev->psp.ta_fw = NULL;
 220         return err;
 221 }
 222
 223 static int psp_v11_0_wait_for_bootloader(struct psp_context *psp)
 224 {
 225         struct amdgpu_device *adev = psp->adev;
 226
 227         int ret;
 228         int retry_loop;
 229
 230         for (retry_loop = 0; retry_loop < 10; retry_loop++) {
 231                 /* Wait for bootloader to signify that is
 232                     ready having bit 31 of C2PMSG_35 set to 1 */
 233                 ret = psp_wait_for(psp,
 234                                    SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35),
 235                                    0x80000000,
 236                                    0x80000000,
 237                                    false);
 238
 239                 if (ret == 0)
 240                         return 0;
 241         }
 242
 243         return ret;
 244 }
 245
 246 static bool psp_v11_0_is_sos_alive(struct psp_context *psp)
 247 {
 248         struct amdgpu_device *adev = psp->adev;
 249         uint32_t sol_reg;
 250
 251         sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81);
 252
 253         return sol_reg != 0x0;
 254 }
 255
 256 static int psp_v11_0_bootloader_load_kdb(struct psp_context *psp)
 257 {
 258         int ret;
 259         uint32_t psp_gfxdrv_command_reg = 0;
 260         struct amdgpu_device *adev = psp->adev;
 261
 262         /* Check tOS sign of life register to confirm sys driver and sOS
 263          * are already been loaded.
 264          */
 265         if (psp_v11_0_is_sos_alive(psp))
 266                 return 0;
 267
 268         ret = psp_v11_0_wait_for_bootloader(psp);
 269         if (ret)
 270                 return ret;
 271
 272         memset(psp->fw_pri_buf, 0, PSP_1_MEG);
 273
 274         /* Copy PSP KDB binary to memory */
 275         memcpy(psp->fw_pri_buf, psp->kdb_start_addr, psp->kdb_bin_size);
 276
 277         /* Provide the PSP KDB to bootloader */
 278         WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36,
 279                (uint32_t)(psp->fw_pri_mc_addr >> 20));
 280         psp_gfxdrv_command_reg = PSP_BL__LOAD_KEY_DATABASE;
 281         WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35,
 282                psp_gfxdrv_command_reg);
 283
 284         ret = psp_v11_0_wait_for_bootloader(psp);
 285
 286         return ret;
 287 }
 288
 289 static int psp_v11_0_bootloader_load_spl(struct psp_context *psp)
 290 {
 291         int ret;
 292         uint32_t psp_gfxdrv_command_reg = 0;
 293         struct amdgpu_device *adev = psp->adev;
 294
 295         /* Check tOS sign of life register to confirm sys driver and sOS
 296          * are already been loaded.
 297          */
 298         if (psp_v11_0_is_sos_alive(psp))
 299                 return 0;
 300
 301         ret = psp_v11_0_wait_for_bootloader(psp);
 302         if (ret)
 303                 return ret;
 304
 305         memset(psp->fw_pri_buf, 0, PSP_1_MEG);
 306
 307         /* Copy PSP SPL binary to memory */
 308         memcpy(psp->fw_pri_buf, psp->spl_start_addr, psp->spl_bin_size);
 309
 310         /* Provide the PSP SPL to bootloader */
 311         WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36,
 312                (uint32_t)(psp->fw_pri_mc_addr >> 20));
 313         psp_gfxdrv_command_reg = PSP_BL__LOAD_TOS_SPL_TABLE;
 314         WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35,
 315                psp_gfxdrv_command_reg);
 316
 317         ret = psp_v11_0_wait_for_bootloader(psp);
 318
 319         return ret;
 320 }
 321
 322 static int psp_v11_0_bootloader_load_sysdrv(struct psp_context *psp)
 323 {
 324         int ret;
 325         uint32_t psp_gfxdrv_command_reg = 0;
 326         struct amdgpu_device *adev = psp->adev;
 327
 328         /* Check sOS sign of life register to confirm sys driver and sOS
 329          * are already been loaded.
 330          */
 331         if (psp_v11_0_is_sos_alive(psp))
 332                 return 0;
 333
 334         ret = psp_v11_0_wait_for_bootloader(psp);
 335         if (ret)
 336                 return ret;
 337
 338         memset(psp->fw_pri_buf, 0, PSP_1_MEG);
 339
 340         /* Copy PSP System Driver binary to memory */
 341         memcpy(psp->fw_pri_buf, psp->sys_start_addr, psp->sys_bin_size);
 342
 343         /* Provide the sys driver to bootloader */
 344         WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36,
 345                (uint32_t)(psp->fw_pri_mc_addr >> 20));
 346         psp_gfxdrv_command_reg = PSP_BL__LOAD_SYSDRV;
 347         WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35,
 348                psp_gfxdrv_command_reg);
 349
 350         /* there might be handshake issue with hardware which needs delay */
 351         mdelay(20);
 352
 353         ret = psp_v11_0_wait_for_bootloader(psp);
 354
 355         return ret;
 356 }
 357
 358 static int psp_v11_0_bootloader_load_sos(struct psp_context *psp)
 359 {
 360         int ret;
 361         unsigned int psp_gfxdrv_command_reg = 0;
 362         struct amdgpu_device *adev = psp->adev;
 363
 364         /* Check sOS sign of life register to confirm sys driver and sOS
 365          * are already been loaded.
 366          */
 367         if (psp_v11_0_is_sos_alive(psp))
 368                 return 0;
 369
 370         ret = psp_v11_0_wait_for_bootloader(psp);
 371         if (ret)
 372                 return ret;
 373
 374         memset(psp->fw_pri_buf, 0, PSP_1_MEG);
 375
 376         /* Copy Secure OS binary to PSP memory */
 377         memcpy(psp->fw_pri_buf, psp->sos_start_addr, psp->sos_bin_size);
 378
 379         /* Provide the PSP secure OS to bootloader */
 380         WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36,
 381                (uint32_t)(psp->fw_pri_mc_addr >> 20));
 382         psp_gfxdrv_command_reg = PSP_BL__LOAD_SOSDRV;
 383         WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35,
 384                psp_gfxdrv_command_reg);
 385
 386         /* there might be handshake issue with hardware which needs delay */
 387         mdelay(20);
 388         ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_81),
 389                            RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81),
 390                            0, true);
 391
 392         return ret;
 393 }
 394
 395 static void psp_v11_0_reroute_ih(struct psp_context *psp)
 396 {
 397         struct amdgpu_device *adev = psp->adev;
 398         uint32_t tmp;
 399
 400         /* Change IH ring for VMC */
 401         tmp = REG_SET_FIELD(0, IH_CLIENT_CFG_DATA, CREDIT_RETURN_ADDR, 0x1244b);
 402         tmp = REG_SET_FIELD(tmp, IH_CLIENT_CFG_DATA, CLIENT_TYPE, 1);
 403         tmp = REG_SET_FIELD(tmp, IH_CLIENT_CFG_DATA, RING_ID, 1);
 404
 405         WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_69, 3);
 406         WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_70, tmp);
 407         WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, GFX_CTRL_CMD_ID_GBR_IH_SET);
 408
 409         mdelay(20);
 410         psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
 411                      0x80000000, 0x8000FFFF, false);
 412
 413         /* Change IH ring for UMC */
 414         tmp = REG_SET_FIELD(0, IH_CLIENT_CFG_DATA, CREDIT_RETURN_ADDR, 0x1216b);
 415         tmp = REG_SET_FIELD(tmp, IH_CLIENT_CFG_DATA, RING_ID, 1);
 416
 417         WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_69, 4);
 418         WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_70, tmp);
 419         WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, GFX_CTRL_CMD_ID_GBR_IH_SET);
 420
 421         mdelay(20);
 422         psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
 423                      0x80000000, 0x8000FFFF, false);
 424 }
 425
 426 static int psp_v11_0_ring_init(struct psp_context *psp,
 427                               enum psp_ring_type ring_type)
 428 {
 429         int ret = 0;
 430         struct psp_ring *ring;
 431         struct amdgpu_device *adev = psp->adev;
 432
 433         if ((!amdgpu_sriov_vf(adev)) &&
 434             !(adev->asic_type >= CHIP_SIENNA_CICHLID &&
 435             adev->asic_type <= CHIP_DIMGREY_CAVEFISH))
 436                 psp_v11_0_reroute_ih(psp);
 437
 438         ring = &psp->km_ring;
 439
 440         ring->ring_type = ring_type;
 441
 442         /* allocate 4k Page of Local Frame Buffer memory for ring */
 443         ring->ring_size = 0x1000;
 444         ret = amdgpu_bo_create_kernel(adev, ring->ring_size, PAGE_SIZE,
 445                                       AMDGPU_GEM_DOMAIN_VRAM,
 446                                       &adev->firmware.rbuf,
 447                                       &ring->ring_mem_mc_addr,
 448                                       (void **)&ring->ring_mem);
 449         if (ret) {
 450                 ring->ring_size = 0;
 451                 return ret;
 452         }
 453
 454         return 0;
 455 }
 456
 457 static int psp_v11_0_ring_stop(struct psp_context *psp,
 458                               enum psp_ring_type ring_type)
 459 {
 460         int ret = 0;
 461         struct amdgpu_device *adev = psp->adev;
 462
 463         /* Write the ring destroy command*/
 464         if (amdgpu_sriov_vf(adev))
 465                 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101,
 466                                      GFX_CTRL_CMD_ID_DESTROY_GPCOM_RING);
 467         else
 468                 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64,
 469                                      GFX_CTRL_CMD_ID_DESTROY_RINGS);
 470
 471         /* there might be handshake issue with hardware which needs delay */
 472         mdelay(20);
 473
 474         /* Wait for response flag (bit 31) */
 475         if (amdgpu_sriov_vf(adev))
 476                 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_101),
 477                                    0x80000000, 0x80000000, false);
 478         else
 479                 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
 480                                    0x80000000, 0x80000000, false);
 481
 482         return ret;
 483 }
 484
 485 static int psp_v11_0_ring_create(struct psp_context *psp,
 486                                 enum psp_ring_type ring_type)
 487 {
 488         int ret = 0;
 489         unsigned int psp_ring_reg = 0;
 490         struct psp_ring *ring = &psp->km_ring;
 491         struct amdgpu_device *adev = psp->adev;
 492
 493         if (amdgpu_sriov_vf(adev)) {
 494                 ret = psp_v11_0_ring_stop(psp, ring_type);
 495                 if (ret) {
 496                         DRM_ERROR("psp_v11_0_ring_stop_sriov failed!\n");
 497                         return ret;
 498                 }
 499
 500                 /* Write low address of the ring to C2PMSG_102 */
 501                 psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr);
 502                 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_102, psp_ring_reg);
 503                 /* Write high address of the ring to C2PMSG_103 */
 504                 psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr);
 505                 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_103, psp_ring_reg);
 506
 507                 /* Write the ring initialization command to C2PMSG_101 */
 508                 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101,
 509                                              GFX_CTRL_CMD_ID_INIT_GPCOM_RING);
 510
 511                 /* there might be handshake issue with hardware which needs delay */
 512                 mdelay(20);
 513
 514                 /* Wait for response flag (bit 31) in C2PMSG_101 */
 515                 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_101),
 516                                    0x80000000, 0x8000FFFF, false);
 517
 518         } else {
 519                 /* Wait for sOS ready for ring creation */
 520                 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
 521                                    0x80000000, 0x80000000, false);
 522                 if (ret) {
 523                         DRM_ERROR("Failed to wait for sOS ready for ring creation\n");
 524                         return ret;
 525                 }
 526
 527                 /* Write low address of the ring to C2PMSG_69 */
 528                 psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr);
 529                 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_69, psp_ring_reg);
 530                 /* Write high address of the ring to C2PMSG_70 */
 531                 psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr);
 532                 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_70, psp_ring_reg);
 533                 /* Write size of ring to C2PMSG_71 */
 534                 psp_ring_reg = ring->ring_size;
 535                 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_71, psp_ring_reg);
 536                 /* Write the ring initialization command to C2PMSG_64 */
 537                 psp_ring_reg = ring_type;
 538                 psp_ring_reg = psp_ring_reg << 16;
 539                 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, psp_ring_reg);
 540
 541                 /* there might be handshake issue with hardware which needs delay */
 542                 mdelay(20);
 543
 544                 /* Wait for response flag (bit 31) in C2PMSG_64 */
 545                 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
 546                                    0x80000000, 0x8000FFFF, false);
 547         }
 548
 549         return ret;
 550 }
 551
 552
 553 static int psp_v11_0_ring_destroy(struct psp_context *psp,
 554                                  enum psp_ring_type ring_type)
 555 {
 556         int ret = 0;
 557         struct psp_ring *ring = &psp->km_ring;
 558         struct amdgpu_device *adev = psp->adev;
 559
 560         ret = psp_v11_0_ring_stop(psp, ring_type);
 561         if (ret)
 562                 DRM_ERROR("Fail to stop psp ring\n");
 563
 564         amdgpu_bo_free_kernel(&adev->firmware.rbuf,
 565                               &ring->ring_mem_mc_addr,
 566                               (void **)&ring->ring_mem);
 567
 568         return ret;
 569 }
 570
 571 static int psp_v11_0_mode1_reset(struct psp_context *psp)
 572 {
 573         int ret;
 574         uint32_t offset;
 575         struct amdgpu_device *adev = psp->adev;
 576
 577         offset = SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64);
 578
 579         ret = psp_wait_for(psp, offset, 0x80000000, 0x8000FFFF, false);
 580
 581         if (ret) {
 582                 DRM_INFO("psp is not working correctly before mode1 reset!\n");
 583                 return -EINVAL;
 584         }
 585
 586         /*send the mode 1 reset command*/
 587         WREG32(offset, GFX_CTRL_CMD_ID_MODE1_RST);
 588
 589         msleep(500);
 590
 591         offset = SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_33);
 592
 593         ret = psp_wait_for(psp, offset, 0x80000000, 0x80000000, false);
 594
 595         if (ret) {
 596                 DRM_INFO("psp mode 1 reset failed!\n");
 597                 return -EINVAL;
 598         }
 599
 600         DRM_INFO("psp mode1 reset succeed \n");
 601
 602         return 0;
 603 }
 604
 605 static int psp_v11_0_memory_training_send_msg(struct psp_context *psp, int msg)
 606 {
 607         int ret;
 608         int i;
 609         uint32_t data_32;
 610         int max_wait;
 611         struct amdgpu_device *adev = psp->adev;
 612
 613         data_32 = (psp->mem_train_ctx.c2p_train_data_offset >> 20);
 614         WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36, data_32);
 615         WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35, msg);
 616
 617         max_wait = MEM_TRAIN_SEND_MSG_TIMEOUT_US / adev->usec_timeout;
 618         for (i = 0; i < max_wait; i++) {
 619                 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35),
 620                                    0x80000000, 0x80000000, false);
 621                 if (ret == 0)
 622                         break;
 623         }
 624         if (i < max_wait)
 625                 ret = 0;
 626         else
 627                 ret = -ETIME;
 628
 629         DRM_DEBUG("training %s %s, cost %d @ %d ms\n",
 630                   (msg == PSP_BL__DRAM_SHORT_TRAIN) ? "short" : "long",
 631                   (ret == 0) ? "succeed" : "failed",
 632                   i, adev->usec_timeout/1000);
 633         return ret;
 634 }
 635
 636 /*
 637  * save and restore proces
 638  */
 639 static int psp_v11_0_memory_training(struct psp_context *psp, uint32_t ops)
 640 {
 641         struct psp_memory_training_context *ctx = &psp->mem_train_ctx;
 642         uint32_t *pcache = (uint32_t *)ctx->sys_cache;
 643         struct amdgpu_device *adev = psp->adev;
 644         uint32_t p2c_header[4];
 645         uint32_t sz;
 646         void *buf;
 647         int ret;
 648
 649         if (ctx->init == PSP_MEM_TRAIN_NOT_SUPPORT) {
 650                 DRM_DEBUG("Memory training is not supported.\n");
 651                 return 0;
 652         } else if (ctx->init != PSP_MEM_TRAIN_INIT_SUCCESS) {
 653                 DRM_ERROR("Memory training initialization failure.\n");
 654                 return -EINVAL;
 655         }
 656
 657         if (psp_v11_0_is_sos_alive(psp)) {
 658                 DRM_DEBUG("SOS is alive, skip memory training.\n");
 659                 return 0;
 660         }
 661
 662         amdgpu_device_vram_access(adev, ctx->p2c_train_data_offset, p2c_header, sizeof(p2c_header), false);
 663         DRM_DEBUG("sys_cache[%08x,%08x,%08x,%08x] p2c_header[%08x,%08x,%08x,%08x]\n",
 664                   pcache[0], pcache[1], pcache[2], pcache[3],
 665                   p2c_header[0], p2c_header[1], p2c_header[2], p2c_header[3]);
 666
 667         if (ops & PSP_MEM_TRAIN_SEND_SHORT_MSG) {
 668                 DRM_DEBUG("Short training depends on restore.\n");
 669                 ops |= PSP_MEM_TRAIN_RESTORE;
 670         }
 671
 672         if ((ops & PSP_MEM_TRAIN_RESTORE) &&
 673             pcache[0] != MEM_TRAIN_SYSTEM_SIGNATURE) {
 674                 DRM_DEBUG("sys_cache[0] is invalid, restore depends on save.\n");
 675                 ops |= PSP_MEM_TRAIN_SAVE;
 676         }
 677
 678         if (p2c_header[0] == MEM_TRAIN_SYSTEM_SIGNATURE &&
 679             !(pcache[0] == MEM_TRAIN_SYSTEM_SIGNATURE &&
 680               pcache[3] == p2c_header[3])) {
 681                 DRM_DEBUG("sys_cache is invalid or out-of-date, need save training data to sys_cache.\n");
 682                 ops |= PSP_MEM_TRAIN_SAVE;
 683         }
 684
 685         if ((ops & PSP_MEM_TRAIN_SAVE) &&
 686             p2c_header[0] != MEM_TRAIN_SYSTEM_SIGNATURE) {
 687                 DRM_DEBUG("p2c_header[0] is invalid, save depends on long training.\n");
 688                 ops |= PSP_MEM_TRAIN_SEND_LONG_MSG;
 689         }
 690
 691         if (ops & PSP_MEM_TRAIN_SEND_LONG_MSG) {
 692                 ops &= ~PSP_MEM_TRAIN_SEND_SHORT_MSG;
 693                 ops |= PSP_MEM_TRAIN_SAVE;
 694         }
 695
 696         DRM_DEBUG("Memory training ops:%x.\n", ops);
 697
 698         if (ops & PSP_MEM_TRAIN_SEND_LONG_MSG) {
 699                 /*
 700                  * Long traing will encroach certain mount of bottom VRAM,
 701                  * saving the content of this bottom VRAM to system memory
 702                  * before training, and restoring it after training to avoid
 703                  * VRAM corruption.
 704                  */
 705                 sz = GDDR6_MEM_TRAINING_ENCROACHED_SIZE;
 706
 707                 if (adev->gmc.visible_vram_size < sz || !adev->mman.aper_base_kaddr) {
 708                         DRM_ERROR("visible_vram_size %llx or aper_base_kaddr %p is not initialized.\n",
 709                                   adev->gmc.visible_vram_size,
 710                                   adev->mman.aper_base_kaddr);
 711                         return -EINVAL;
 712                 }
 713
 714                 buf = vmalloc(sz);
 715                 if (!buf) {
 716                         DRM_ERROR("failed to allocate system memory.\n");
 717                         return -ENOMEM;
 718                 }
 719
 720                 memcpy_fromio(buf, adev->mman.aper_base_kaddr, sz);
 721                 ret = psp_v11_0_memory_training_send_msg(psp, PSP_BL__DRAM_LONG_TRAIN);
 722                 if (ret) {
 723                         DRM_ERROR("Send long training msg failed.\n");
 724                         vfree(buf);
 725                         return ret;
 726                 }
 727
 728                 memcpy_toio(adev->mman.aper_base_kaddr, buf, sz);
 729                 adev->nbio.funcs->hdp_flush(adev, NULL);
 730                 vfree(buf);
 731         }
 732
 733         if (ops & PSP_MEM_TRAIN_SAVE) {
 734                 amdgpu_device_vram_access(psp->adev, ctx->p2c_train_data_offset, ctx->sys_cache, ctx->train_data_size, false);
 735         }
 736
 737         if (ops & PSP_MEM_TRAIN_RESTORE) {
 738                 amdgpu_device_vram_access(psp->adev, ctx->c2p_train_data_offset, ctx->sys_cache, ctx->train_data_size, true);
 739         }
 740
 741         if (ops & PSP_MEM_TRAIN_SEND_SHORT_MSG) {
 742                 ret = psp_v11_0_memory_training_send_msg(psp, (amdgpu_force_long_training > 0) ?
 743                                                          PSP_BL__DRAM_LONG_TRAIN : PSP_BL__DRAM_SHORT_TRAIN);
 744                 if (ret) {
 745                         DRM_ERROR("send training msg failed.\n");
 746                         return ret;
 747                 }
 748         }
 749         ctx->training_cnt++;
 750         return 0;
 751 }
 752
 753 static uint32_t psp_v11_0_ring_get_wptr(struct psp_context *psp)
 754 {
 755         uint32_t data;
 756         struct amdgpu_device *adev = psp->adev;
 757
 758         if (amdgpu_sriov_vf(adev))
 759                 data = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_102);
 760         else
 761                 data = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67);
 762
 763         return data;
 764 }
 765
 766 static void psp_v11_0_ring_set_wptr(struct psp_context *psp, uint32_t value)
 767 {
 768         struct amdgpu_device *adev = psp->adev;
 769
 770         if (amdgpu_sriov_vf(adev)) {
 771                 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_102, value);
 772                 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101, GFX_CTRL_CMD_ID_CONSUME_CMD);
 773         } else
 774                 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67, value);
 775 }
 776
 777 static int psp_v11_0_load_usbc_pd_fw(struct psp_context *psp, dma_addr_t dma_addr)
 778 {
 779         struct amdgpu_device *adev = psp->adev;
 780         uint32_t reg_status;
 781         int ret, i = 0;
 782
 783         /* Write lower 32-bit address of the PD Controller FW */
 784         WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36, lower_32_bits(dma_addr));
 785         ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35),
 786                              0x80000000, 0x80000000, false);
 787         if (ret)
 788                 return ret;
 789
 790         /* Fireup interrupt so PSP can pick up the lower address */
 791         WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35, 0x800000);
 792         ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35),
 793                              0x80000000, 0x80000000, false);
 794         if (ret)
 795                 return ret;
 796
 797         reg_status = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35);
 798
 799         if ((reg_status & 0xFFFF) != 0) {
 800                 DRM_ERROR("Lower address load failed - MP0_SMN_C2PMSG_35.Bits [15:0] = %02x...\n",
 801                                 reg_status & 0xFFFF);
 802                 return -EIO;
 803         }
 804
 805         /* Write upper 32-bit address of the PD Controller FW */
 806         WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36, upper_32_bits(dma_addr));
 807
 808         ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35),
 809                              0x80000000, 0x80000000, false);
 810         if (ret)
 811                 return ret;
 812
 813         /* Fireup interrupt so PSP can pick up the upper address */
 814         WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35, 0x4000000);
 815
 816         /* FW load takes very long time */
 817         do {
 818                 msleep(1000);
 819                 reg_status = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35);
 820
 821                 if (reg_status & 0x80000000)
 822                         goto done;
 823
 824         } while (++i < USBC_PD_POLLING_LIMIT_S);
 825
 826         return -ETIME;
 827 done:
 828
 829         if ((reg_status & 0xFFFF) != 0) {
 830                 DRM_ERROR("Upper address load failed - MP0_SMN_C2PMSG_35.Bits [15:0] = x%04x\n",
 831                                 reg_status & 0xFFFF);
 832                 return -EIO;
 833         }
 834
 835         return 0;
 836 }
 837
 838 static int psp_v11_0_read_usbc_pd_fw(struct psp_context *psp, uint32_t *fw_ver)
 839 {
 840         struct amdgpu_device *adev = psp->adev;
 841         int ret;
 842
 843         WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35, C2PMSG_CMD_GFX_USB_PD_FW_VER);
 844
 845         ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35),
 846                                      0x80000000, 0x80000000, false);
 847         if (!ret)
 848                 *fw_ver = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36);
 849
 850         return ret;
 851 }
 852
 853 static const struct psp_funcs psp_v11_0_funcs = {
 854         .init_microcode = psp_v11_0_init_microcode,
 855         .bootloader_load_kdb = psp_v11_0_bootloader_load_kdb,
 856         .bootloader_load_spl = psp_v11_0_bootloader_load_spl,
 857         .bootloader_load_sysdrv = psp_v11_0_bootloader_load_sysdrv,
 858         .bootloader_load_sos = psp_v11_0_bootloader_load_sos,
 859         .ring_init = psp_v11_0_ring_init,
 860         .ring_create = psp_v11_0_ring_create,
 861         .ring_stop = psp_v11_0_ring_stop,
 862         .ring_destroy = psp_v11_0_ring_destroy,
 863         .mode1_reset = psp_v11_0_mode1_reset,
 864         .mem_training = psp_v11_0_memory_training,
 865         .ring_get_wptr = psp_v11_0_ring_get_wptr,
 866         .ring_set_wptr = psp_v11_0_ring_set_wptr,
 867         .load_usbc_pd_fw = psp_v11_0_load_usbc_pd_fw,
 868         .read_usbc_pd_fw = psp_v11_0_read_usbc_pd_fw
 869 };
 870
 871 void psp_v11_0_set_psp_funcs(struct psp_context *psp)
 872 {
 873         psp->funcs = &psp_v11_0_funcs;
 874 }