2 * Copyright 2018 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
23 #include <linux/firmware.h>
24 #include <linux/module.h>
25 #include <linux/vmalloc.h>
28 #include "amdgpu_psp.h"
29 #include "amdgpu_ras.h"
30 #include "amdgpu_ucode.h"
31 #include "soc15_common.h"
32 #include "psp_v11_0.h"
34 #include "mp/mp_11_0_offset.h"
35 #include "mp/mp_11_0_sh_mask.h"
36 #include "gc/gc_9_0_offset.h"
37 #include "sdma0/sdma0_4_0_offset.h"
38 #include "nbio/nbio_7_4_offset.h"
40 #include "oss/osssys_4_0_offset.h"
41 #include "oss/osssys_4_0_sh_mask.h"
43 MODULE_FIRMWARE("amdgpu/vega20_sos.bin");
44 MODULE_FIRMWARE("amdgpu/vega20_asd.bin");
45 MODULE_FIRMWARE("amdgpu/vega20_ta.bin");
46 MODULE_FIRMWARE("amdgpu/navi10_sos.bin");
47 MODULE_FIRMWARE("amdgpu/navi10_asd.bin");
48 MODULE_FIRMWARE("amdgpu/navi10_ta.bin");
49 MODULE_FIRMWARE("amdgpu/navi14_sos.bin");
50 MODULE_FIRMWARE("amdgpu/navi14_asd.bin");
51 MODULE_FIRMWARE("amdgpu/navi14_ta.bin");
52 MODULE_FIRMWARE("amdgpu/navi12_sos.bin");
53 MODULE_FIRMWARE("amdgpu/navi12_asd.bin");
54 MODULE_FIRMWARE("amdgpu/navi12_ta.bin");
55 MODULE_FIRMWARE("amdgpu/arcturus_sos.bin");
56 MODULE_FIRMWARE("amdgpu/arcturus_asd.bin");
57 MODULE_FIRMWARE("amdgpu/arcturus_ta.bin");
58 MODULE_FIRMWARE("amdgpu/sienna_cichlid_sos.bin");
59 MODULE_FIRMWARE("amdgpu/sienna_cichlid_ta.bin");
60 MODULE_FIRMWARE("amdgpu/navy_flounder_sos.bin");
61 MODULE_FIRMWARE("amdgpu/navy_flounder_ta.bin");
62 MODULE_FIRMWARE("amdgpu/vangogh_asd.bin");
63 MODULE_FIRMWARE("amdgpu/vangogh_toc.bin");
64 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_sos.bin");
65 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_ta.bin");
68 #define smnMP1_FIRMWARE_FLAGS 0x3010024
69 /* navi10 reg offset define */
70 #define mmRLC_GPM_UCODE_ADDR_NV10 0x5b61
71 #define mmRLC_GPM_UCODE_DATA_NV10 0x5b62
72 #define mmSDMA0_UCODE_ADDR_NV10 0x5880
73 #define mmSDMA0_UCODE_DATA_NV10 0x5881
74 /* memory training timeout define */
75 #define MEM_TRAIN_SEND_MSG_TIMEOUT_US 3000000
77 /* For large FW files the time to complete can be very long */
78 #define USBC_PD_POLLING_LIMIT_S 240
80 static int psp_v11_0_init_microcode(struct psp_context *psp)
82 struct amdgpu_device *adev = psp->adev;
83 const char *chip_name;
84 char fw_name[PSP_FW_NAME_LEN];
86 const struct ta_firmware_header_v1_0 *ta_hdr;
90 switch (adev->asic_type) {
101 chip_name = "navi12";
104 chip_name = "arcturus";
106 case CHIP_SIENNA_CICHLID:
107 chip_name = "sienna_cichlid";
109 case CHIP_NAVY_FLOUNDER:
110 chip_name = "navy_flounder";
113 chip_name = "vangogh";
115 case CHIP_DIMGREY_CAVEFISH:
116 chip_name = "dimgrey_cavefish";
123 switch (adev->asic_type) {
126 err = psp_init_sos_microcode(psp, chip_name);
129 err = psp_init_asd_microcode(psp, chip_name);
132 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ta.bin", chip_name);
133 err = request_firmware(&adev->psp.ta_fw, fw_name, adev->dev);
135 release_firmware(adev->psp.ta_fw);
136 adev->psp.ta_fw = NULL;
138 "psp v11.0: Failed to load firmware \"%s\"\n", fw_name);
140 err = amdgpu_ucode_validate(adev->psp.ta_fw);
144 ta_hdr = (const struct ta_firmware_header_v1_0 *)adev->psp.ta_fw->data;
145 adev->psp.ta_xgmi_ucode_version = le32_to_cpu(ta_hdr->ta_xgmi_ucode_version);
146 adev->psp.ta_xgmi_ucode_size = le32_to_cpu(ta_hdr->ta_xgmi_size_bytes);
147 adev->psp.ta_xgmi_start_addr = (uint8_t *)ta_hdr +
148 le32_to_cpu(ta_hdr->header.ucode_array_offset_bytes);
149 adev->psp.ta_fw_version = le32_to_cpu(ta_hdr->header.ucode_version);
150 adev->psp.ta_ras_ucode_version = le32_to_cpu(ta_hdr->ta_ras_ucode_version);
151 adev->psp.ta_ras_ucode_size = le32_to_cpu(ta_hdr->ta_ras_size_bytes);
152 adev->psp.ta_ras_start_addr = (uint8_t *)adev->psp.ta_xgmi_start_addr +
153 le32_to_cpu(ta_hdr->ta_ras_offset_bytes);
159 err = psp_init_sos_microcode(psp, chip_name);
162 err = psp_init_asd_microcode(psp, chip_name);
165 if (amdgpu_sriov_vf(adev))
167 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ta.bin", chip_name);
168 err = request_firmware(&adev->psp.ta_fw, fw_name, adev->dev);
170 release_firmware(adev->psp.ta_fw);
171 adev->psp.ta_fw = NULL;
173 "psp v11.0: Failed to load firmware \"%s\"\n", fw_name);
175 err = amdgpu_ucode_validate(adev->psp.ta_fw);
179 ta_hdr = (const struct ta_firmware_header_v1_0 *)adev->psp.ta_fw->data;
180 adev->psp.ta_hdcp_ucode_version = le32_to_cpu(ta_hdr->ta_hdcp_ucode_version);
181 adev->psp.ta_hdcp_ucode_size = le32_to_cpu(ta_hdr->ta_hdcp_size_bytes);
182 adev->psp.ta_hdcp_start_addr = (uint8_t *)ta_hdr +
183 le32_to_cpu(ta_hdr->header.ucode_array_offset_bytes);
185 adev->psp.ta_fw_version = le32_to_cpu(ta_hdr->header.ucode_version);
187 adev->psp.ta_dtm_ucode_version = le32_to_cpu(ta_hdr->ta_dtm_ucode_version);
188 adev->psp.ta_dtm_ucode_size = le32_to_cpu(ta_hdr->ta_dtm_size_bytes);
189 adev->psp.ta_dtm_start_addr = (uint8_t *)adev->psp.ta_hdcp_start_addr +
190 le32_to_cpu(ta_hdr->ta_dtm_offset_bytes);
193 case CHIP_SIENNA_CICHLID:
194 case CHIP_NAVY_FLOUNDER:
195 case CHIP_DIMGREY_CAVEFISH:
196 err = psp_init_sos_microcode(psp, chip_name);
199 err = psp_init_ta_microcode(psp, chip_name);
204 err = psp_init_asd_microcode(psp, chip_name);
207 err = psp_init_toc_microcode(psp, chip_name);
218 release_firmware(adev->psp.ta_fw);
219 adev->psp.ta_fw = NULL;
223 static int psp_v11_0_wait_for_bootloader(struct psp_context *psp)
225 struct amdgpu_device *adev = psp->adev;
230 for (retry_loop = 0; retry_loop < 10; retry_loop++) {
231 /* Wait for bootloader to signify that is
232 ready having bit 31 of C2PMSG_35 set to 1 */
233 ret = psp_wait_for(psp,
234 SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35),
246 static bool psp_v11_0_is_sos_alive(struct psp_context *psp)
248 struct amdgpu_device *adev = psp->adev;
251 sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81);
253 return sol_reg != 0x0;
256 static int psp_v11_0_bootloader_load_kdb(struct psp_context *psp)
259 uint32_t psp_gfxdrv_command_reg = 0;
260 struct amdgpu_device *adev = psp->adev;
262 /* Check tOS sign of life register to confirm sys driver and sOS
263 * are already been loaded.
265 if (psp_v11_0_is_sos_alive(psp))
268 ret = psp_v11_0_wait_for_bootloader(psp);
272 memset(psp->fw_pri_buf, 0, PSP_1_MEG);
274 /* Copy PSP KDB binary to memory */
275 memcpy(psp->fw_pri_buf, psp->kdb_start_addr, psp->kdb_bin_size);
277 /* Provide the PSP KDB to bootloader */
278 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36,
279 (uint32_t)(psp->fw_pri_mc_addr >> 20));
280 psp_gfxdrv_command_reg = PSP_BL__LOAD_KEY_DATABASE;
281 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35,
282 psp_gfxdrv_command_reg);
284 ret = psp_v11_0_wait_for_bootloader(psp);
289 static int psp_v11_0_bootloader_load_spl(struct psp_context *psp)
292 uint32_t psp_gfxdrv_command_reg = 0;
293 struct amdgpu_device *adev = psp->adev;
295 /* Check tOS sign of life register to confirm sys driver and sOS
296 * are already been loaded.
298 if (psp_v11_0_is_sos_alive(psp))
301 ret = psp_v11_0_wait_for_bootloader(psp);
305 memset(psp->fw_pri_buf, 0, PSP_1_MEG);
307 /* Copy PSP SPL binary to memory */
308 memcpy(psp->fw_pri_buf, psp->spl_start_addr, psp->spl_bin_size);
310 /* Provide the PSP SPL to bootloader */
311 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36,
312 (uint32_t)(psp->fw_pri_mc_addr >> 20));
313 psp_gfxdrv_command_reg = PSP_BL__LOAD_TOS_SPL_TABLE;
314 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35,
315 psp_gfxdrv_command_reg);
317 ret = psp_v11_0_wait_for_bootloader(psp);
322 static int psp_v11_0_bootloader_load_sysdrv(struct psp_context *psp)
325 uint32_t psp_gfxdrv_command_reg = 0;
326 struct amdgpu_device *adev = psp->adev;
328 /* Check sOS sign of life register to confirm sys driver and sOS
329 * are already been loaded.
331 if (psp_v11_0_is_sos_alive(psp))
334 ret = psp_v11_0_wait_for_bootloader(psp);
338 memset(psp->fw_pri_buf, 0, PSP_1_MEG);
340 /* Copy PSP System Driver binary to memory */
341 memcpy(psp->fw_pri_buf, psp->sys_start_addr, psp->sys_bin_size);
343 /* Provide the sys driver to bootloader */
344 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36,
345 (uint32_t)(psp->fw_pri_mc_addr >> 20));
346 psp_gfxdrv_command_reg = PSP_BL__LOAD_SYSDRV;
347 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35,
348 psp_gfxdrv_command_reg);
350 /* there might be handshake issue with hardware which needs delay */
353 ret = psp_v11_0_wait_for_bootloader(psp);
358 static int psp_v11_0_bootloader_load_sos(struct psp_context *psp)
361 unsigned int psp_gfxdrv_command_reg = 0;
362 struct amdgpu_device *adev = psp->adev;
364 /* Check sOS sign of life register to confirm sys driver and sOS
365 * are already been loaded.
367 if (psp_v11_0_is_sos_alive(psp))
370 ret = psp_v11_0_wait_for_bootloader(psp);
374 memset(psp->fw_pri_buf, 0, PSP_1_MEG);
376 /* Copy Secure OS binary to PSP memory */
377 memcpy(psp->fw_pri_buf, psp->sos_start_addr, psp->sos_bin_size);
379 /* Provide the PSP secure OS to bootloader */
380 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36,
381 (uint32_t)(psp->fw_pri_mc_addr >> 20));
382 psp_gfxdrv_command_reg = PSP_BL__LOAD_SOSDRV;
383 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35,
384 psp_gfxdrv_command_reg);
386 /* there might be handshake issue with hardware which needs delay */
388 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_81),
389 RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81),
395 static void psp_v11_0_reroute_ih(struct psp_context *psp)
397 struct amdgpu_device *adev = psp->adev;
400 /* Change IH ring for VMC */
401 tmp = REG_SET_FIELD(0, IH_CLIENT_CFG_DATA, CREDIT_RETURN_ADDR, 0x1244b);
402 tmp = REG_SET_FIELD(tmp, IH_CLIENT_CFG_DATA, CLIENT_TYPE, 1);
403 tmp = REG_SET_FIELD(tmp, IH_CLIENT_CFG_DATA, RING_ID, 1);
405 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_69, 3);
406 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_70, tmp);
407 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, GFX_CTRL_CMD_ID_GBR_IH_SET);
410 psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
411 0x80000000, 0x8000FFFF, false);
413 /* Change IH ring for UMC */
414 tmp = REG_SET_FIELD(0, IH_CLIENT_CFG_DATA, CREDIT_RETURN_ADDR, 0x1216b);
415 tmp = REG_SET_FIELD(tmp, IH_CLIENT_CFG_DATA, RING_ID, 1);
417 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_69, 4);
418 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_70, tmp);
419 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, GFX_CTRL_CMD_ID_GBR_IH_SET);
422 psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
423 0x80000000, 0x8000FFFF, false);
426 static int psp_v11_0_ring_init(struct psp_context *psp,
427 enum psp_ring_type ring_type)
430 struct psp_ring *ring;
431 struct amdgpu_device *adev = psp->adev;
433 if ((!amdgpu_sriov_vf(adev)) &&
434 !(adev->asic_type >= CHIP_SIENNA_CICHLID &&
435 adev->asic_type <= CHIP_DIMGREY_CAVEFISH))
436 psp_v11_0_reroute_ih(psp);
438 ring = &psp->km_ring;
440 ring->ring_type = ring_type;
442 /* allocate 4k Page of Local Frame Buffer memory for ring */
443 ring->ring_size = 0x1000;
444 ret = amdgpu_bo_create_kernel(adev, ring->ring_size, PAGE_SIZE,
445 AMDGPU_GEM_DOMAIN_VRAM,
446 &adev->firmware.rbuf,
447 &ring->ring_mem_mc_addr,
448 (void **)&ring->ring_mem);
457 static int psp_v11_0_ring_stop(struct psp_context *psp,
458 enum psp_ring_type ring_type)
461 struct amdgpu_device *adev = psp->adev;
463 /* Write the ring destroy command*/
464 if (amdgpu_sriov_vf(adev))
465 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101,
466 GFX_CTRL_CMD_ID_DESTROY_GPCOM_RING);
468 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64,
469 GFX_CTRL_CMD_ID_DESTROY_RINGS);
471 /* there might be handshake issue with hardware which needs delay */
474 /* Wait for response flag (bit 31) */
475 if (amdgpu_sriov_vf(adev))
476 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_101),
477 0x80000000, 0x80000000, false);
479 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
480 0x80000000, 0x80000000, false);
485 static int psp_v11_0_ring_create(struct psp_context *psp,
486 enum psp_ring_type ring_type)
489 unsigned int psp_ring_reg = 0;
490 struct psp_ring *ring = &psp->km_ring;
491 struct amdgpu_device *adev = psp->adev;
493 if (amdgpu_sriov_vf(adev)) {
494 ret = psp_v11_0_ring_stop(psp, ring_type);
496 DRM_ERROR("psp_v11_0_ring_stop_sriov failed!\n");
500 /* Write low address of the ring to C2PMSG_102 */
501 psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr);
502 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_102, psp_ring_reg);
503 /* Write high address of the ring to C2PMSG_103 */
504 psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr);
505 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_103, psp_ring_reg);
507 /* Write the ring initialization command to C2PMSG_101 */
508 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101,
509 GFX_CTRL_CMD_ID_INIT_GPCOM_RING);
511 /* there might be handshake issue with hardware which needs delay */
514 /* Wait for response flag (bit 31) in C2PMSG_101 */
515 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_101),
516 0x80000000, 0x8000FFFF, false);
519 /* Wait for sOS ready for ring creation */
520 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
521 0x80000000, 0x80000000, false);
523 DRM_ERROR("Failed to wait for sOS ready for ring creation\n");
527 /* Write low address of the ring to C2PMSG_69 */
528 psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr);
529 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_69, psp_ring_reg);
530 /* Write high address of the ring to C2PMSG_70 */
531 psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr);
532 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_70, psp_ring_reg);
533 /* Write size of ring to C2PMSG_71 */
534 psp_ring_reg = ring->ring_size;
535 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_71, psp_ring_reg);
536 /* Write the ring initialization command to C2PMSG_64 */
537 psp_ring_reg = ring_type;
538 psp_ring_reg = psp_ring_reg << 16;
539 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, psp_ring_reg);
541 /* there might be handshake issue with hardware which needs delay */
544 /* Wait for response flag (bit 31) in C2PMSG_64 */
545 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
546 0x80000000, 0x8000FFFF, false);
553 static int psp_v11_0_ring_destroy(struct psp_context *psp,
554 enum psp_ring_type ring_type)
557 struct psp_ring *ring = &psp->km_ring;
558 struct amdgpu_device *adev = psp->adev;
560 ret = psp_v11_0_ring_stop(psp, ring_type);
562 DRM_ERROR("Fail to stop psp ring\n");
564 amdgpu_bo_free_kernel(&adev->firmware.rbuf,
565 &ring->ring_mem_mc_addr,
566 (void **)&ring->ring_mem);
571 static int psp_v11_0_mode1_reset(struct psp_context *psp)
575 struct amdgpu_device *adev = psp->adev;
577 offset = SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64);
579 ret = psp_wait_for(psp, offset, 0x80000000, 0x8000FFFF, false);
582 DRM_INFO("psp is not working correctly before mode1 reset!\n");
586 /*send the mode 1 reset command*/
587 WREG32(offset, GFX_CTRL_CMD_ID_MODE1_RST);
591 offset = SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_33);
593 ret = psp_wait_for(psp, offset, 0x80000000, 0x80000000, false);
596 DRM_INFO("psp mode 1 reset failed!\n");
600 DRM_INFO("psp mode1 reset succeed \n");
605 static int psp_v11_0_memory_training_send_msg(struct psp_context *psp, int msg)
611 struct amdgpu_device *adev = psp->adev;
613 data_32 = (psp->mem_train_ctx.c2p_train_data_offset >> 20);
614 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36, data_32);
615 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35, msg);
617 max_wait = MEM_TRAIN_SEND_MSG_TIMEOUT_US / adev->usec_timeout;
618 for (i = 0; i < max_wait; i++) {
619 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35),
620 0x80000000, 0x80000000, false);
629 DRM_DEBUG("training %s %s, cost %d @ %d ms\n",
630 (msg == PSP_BL__DRAM_SHORT_TRAIN) ? "short" : "long",
631 (ret == 0) ? "succeed" : "failed",
632 i, adev->usec_timeout/1000);
637 * save and restore proces
639 static int psp_v11_0_memory_training(struct psp_context *psp, uint32_t ops)
641 struct psp_memory_training_context *ctx = &psp->mem_train_ctx;
642 uint32_t *pcache = (uint32_t *)ctx->sys_cache;
643 struct amdgpu_device *adev = psp->adev;
644 uint32_t p2c_header[4];
649 if (ctx->init == PSP_MEM_TRAIN_NOT_SUPPORT) {
650 DRM_DEBUG("Memory training is not supported.\n");
652 } else if (ctx->init != PSP_MEM_TRAIN_INIT_SUCCESS) {
653 DRM_ERROR("Memory training initialization failure.\n");
657 if (psp_v11_0_is_sos_alive(psp)) {
658 DRM_DEBUG("SOS is alive, skip memory training.\n");
662 amdgpu_device_vram_access(adev, ctx->p2c_train_data_offset, p2c_header, sizeof(p2c_header), false);
663 DRM_DEBUG("sys_cache[%08x,%08x,%08x,%08x] p2c_header[%08x,%08x,%08x,%08x]\n",
664 pcache[0], pcache[1], pcache[2], pcache[3],
665 p2c_header[0], p2c_header[1], p2c_header[2], p2c_header[3]);
667 if (ops & PSP_MEM_TRAIN_SEND_SHORT_MSG) {
668 DRM_DEBUG("Short training depends on restore.\n");
669 ops |= PSP_MEM_TRAIN_RESTORE;
672 if ((ops & PSP_MEM_TRAIN_RESTORE) &&
673 pcache[0] != MEM_TRAIN_SYSTEM_SIGNATURE) {
674 DRM_DEBUG("sys_cache[0] is invalid, restore depends on save.\n");
675 ops |= PSP_MEM_TRAIN_SAVE;
678 if (p2c_header[0] == MEM_TRAIN_SYSTEM_SIGNATURE &&
679 !(pcache[0] == MEM_TRAIN_SYSTEM_SIGNATURE &&
680 pcache[3] == p2c_header[3])) {
681 DRM_DEBUG("sys_cache is invalid or out-of-date, need save training data to sys_cache.\n");
682 ops |= PSP_MEM_TRAIN_SAVE;
685 if ((ops & PSP_MEM_TRAIN_SAVE) &&
686 p2c_header[0] != MEM_TRAIN_SYSTEM_SIGNATURE) {
687 DRM_DEBUG("p2c_header[0] is invalid, save depends on long training.\n");
688 ops |= PSP_MEM_TRAIN_SEND_LONG_MSG;
691 if (ops & PSP_MEM_TRAIN_SEND_LONG_MSG) {
692 ops &= ~PSP_MEM_TRAIN_SEND_SHORT_MSG;
693 ops |= PSP_MEM_TRAIN_SAVE;
696 DRM_DEBUG("Memory training ops:%x.\n", ops);
698 if (ops & PSP_MEM_TRAIN_SEND_LONG_MSG) {
700 * Long traing will encroach certain mount of bottom VRAM,
701 * saving the content of this bottom VRAM to system memory
702 * before training, and restoring it after training to avoid
705 sz = GDDR6_MEM_TRAINING_ENCROACHED_SIZE;
707 if (adev->gmc.visible_vram_size < sz || !adev->mman.aper_base_kaddr) {
708 DRM_ERROR("visible_vram_size %llx or aper_base_kaddr %p is not initialized.\n",
709 adev->gmc.visible_vram_size,
710 adev->mman.aper_base_kaddr);
716 DRM_ERROR("failed to allocate system memory.\n");
720 memcpy_fromio(buf, adev->mman.aper_base_kaddr, sz);
721 ret = psp_v11_0_memory_training_send_msg(psp, PSP_BL__DRAM_LONG_TRAIN);
723 DRM_ERROR("Send long training msg failed.\n");
728 memcpy_toio(adev->mman.aper_base_kaddr, buf, sz);
729 adev->nbio.funcs->hdp_flush(adev, NULL);
733 if (ops & PSP_MEM_TRAIN_SAVE) {
734 amdgpu_device_vram_access(psp->adev, ctx->p2c_train_data_offset, ctx->sys_cache, ctx->train_data_size, false);
737 if (ops & PSP_MEM_TRAIN_RESTORE) {
738 amdgpu_device_vram_access(psp->adev, ctx->c2p_train_data_offset, ctx->sys_cache, ctx->train_data_size, true);
741 if (ops & PSP_MEM_TRAIN_SEND_SHORT_MSG) {
742 ret = psp_v11_0_memory_training_send_msg(psp, (amdgpu_force_long_training > 0) ?
743 PSP_BL__DRAM_LONG_TRAIN : PSP_BL__DRAM_SHORT_TRAIN);
745 DRM_ERROR("send training msg failed.\n");
753 static uint32_t psp_v11_0_ring_get_wptr(struct psp_context *psp)
756 struct amdgpu_device *adev = psp->adev;
758 if (amdgpu_sriov_vf(adev))
759 data = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_102);
761 data = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67);
766 static void psp_v11_0_ring_set_wptr(struct psp_context *psp, uint32_t value)
768 struct amdgpu_device *adev = psp->adev;
770 if (amdgpu_sriov_vf(adev)) {
771 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_102, value);
772 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101, GFX_CTRL_CMD_ID_CONSUME_CMD);
774 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67, value);
777 static int psp_v11_0_load_usbc_pd_fw(struct psp_context *psp, dma_addr_t dma_addr)
779 struct amdgpu_device *adev = psp->adev;
783 /* Write lower 32-bit address of the PD Controller FW */
784 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36, lower_32_bits(dma_addr));
785 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35),
786 0x80000000, 0x80000000, false);
790 /* Fireup interrupt so PSP can pick up the lower address */
791 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35, 0x800000);
792 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35),
793 0x80000000, 0x80000000, false);
797 reg_status = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35);
799 if ((reg_status & 0xFFFF) != 0) {
800 DRM_ERROR("Lower address load failed - MP0_SMN_C2PMSG_35.Bits [15:0] = %02x...\n",
801 reg_status & 0xFFFF);
805 /* Write upper 32-bit address of the PD Controller FW */
806 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36, upper_32_bits(dma_addr));
808 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35),
809 0x80000000, 0x80000000, false);
813 /* Fireup interrupt so PSP can pick up the upper address */
814 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35, 0x4000000);
816 /* FW load takes very long time */
819 reg_status = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35);
821 if (reg_status & 0x80000000)
824 } while (++i < USBC_PD_POLLING_LIMIT_S);
829 if ((reg_status & 0xFFFF) != 0) {
830 DRM_ERROR("Upper address load failed - MP0_SMN_C2PMSG_35.Bits [15:0] = x%04x\n",
831 reg_status & 0xFFFF);
838 static int psp_v11_0_read_usbc_pd_fw(struct psp_context *psp, uint32_t *fw_ver)
840 struct amdgpu_device *adev = psp->adev;
843 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35, C2PMSG_CMD_GFX_USB_PD_FW_VER);
845 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35),
846 0x80000000, 0x80000000, false);
848 *fw_ver = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36);
853 static const struct psp_funcs psp_v11_0_funcs = {
854 .init_microcode = psp_v11_0_init_microcode,
855 .bootloader_load_kdb = psp_v11_0_bootloader_load_kdb,
856 .bootloader_load_spl = psp_v11_0_bootloader_load_spl,
857 .bootloader_load_sysdrv = psp_v11_0_bootloader_load_sysdrv,
858 .bootloader_load_sos = psp_v11_0_bootloader_load_sos,
859 .ring_init = psp_v11_0_ring_init,
860 .ring_create = psp_v11_0_ring_create,
861 .ring_stop = psp_v11_0_ring_stop,
862 .ring_destroy = psp_v11_0_ring_destroy,
863 .mode1_reset = psp_v11_0_mode1_reset,
864 .mem_training = psp_v11_0_memory_training,
865 .ring_get_wptr = psp_v11_0_ring_get_wptr,
866 .ring_set_wptr = psp_v11_0_ring_set_wptr,
867 .load_usbc_pd_fw = psp_v11_0_load_usbc_pd_fw,
868 .read_usbc_pd_fw = psp_v11_0_read_usbc_pd_fw
871 void psp_v11_0_set_psp_funcs(struct psp_context *psp)
873 psp->funcs = &psp_v11_0_funcs;