drivers/gpu/drm/amd/amdgpu/psp_v11_0.c

   1 /*
   2  * Copyright 2018 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  */
  22
  23 #include <linux/firmware.h>
  24 #include <linux/module.h>
  25
  26 #include "amdgpu.h"
  27 #include "amdgpu_psp.h"
  28 #include "amdgpu_ucode.h"
  29 #include "soc15_common.h"
  30 #include "psp_v11_0.h"
  31
  32 #include "mp/mp_11_0_offset.h"
  33 #include "mp/mp_11_0_sh_mask.h"
  34 #include "gc/gc_9_0_offset.h"
  35 #include "sdma0/sdma0_4_0_offset.h"
  36 #include "nbio/nbio_7_4_offset.h"
  37
  38 #include "oss/osssys_4_0_offset.h"
  39 #include "oss/osssys_4_0_sh_mask.h"
  40
  41 MODULE_FIRMWARE("amdgpu/vega20_sos.bin");
  42 MODULE_FIRMWARE("amdgpu/vega20_asd.bin");
  43 MODULE_FIRMWARE("amdgpu/vega20_ta.bin");
  44 MODULE_FIRMWARE("amdgpu/navi10_sos.bin");
  45 MODULE_FIRMWARE("amdgpu/navi10_asd.bin");
  46
  47 /* address block */
  48 #define smnMP1_FIRMWARE_FLAGS           0x3010024
  49 /* navi10 reg offset define */
  50 #define mmRLC_GPM_UCODE_ADDR_NV10       0x5b61
  51 #define mmRLC_GPM_UCODE_DATA_NV10       0x5b62
  52 #define mmSDMA0_UCODE_ADDR_NV10         0x5880
  53 #define mmSDMA0_UCODE_DATA_NV10         0x5881
  54
  55 static int psp_v11_0_init_microcode(struct psp_context *psp)
  56 {
  57         struct amdgpu_device *adev = psp->adev;
  58         const char *chip_name;
  59         char fw_name[30];
  60         int err = 0;
  61         const struct psp_firmware_header_v1_0 *sos_hdr;
  62         const struct psp_firmware_header_v1_1 *sos_hdr_v1_1;
  63         const struct psp_firmware_header_v1_0 *asd_hdr;
  64         const struct ta_firmware_header_v1_0 *ta_hdr;
  65
  66         DRM_DEBUG("\n");
  67
  68         switch (adev->asic_type) {
  69         case CHIP_VEGA20:
  70                 chip_name = "vega20";
  71                 break;
  72         case CHIP_NAVI10:
  73                 chip_name = "navi10";
  74                 break;
  75         default:
  76                 BUG();
  77         }
  78
  79         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sos.bin", chip_name);
  80         err = request_firmware(&adev->psp.sos_fw, fw_name, adev->dev);
  81         if (err)
  82                 goto out;
  83
  84         err = amdgpu_ucode_validate(adev->psp.sos_fw);
  85         if (err)
  86                 goto out;
  87
  88         sos_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.sos_fw->data;
  89         amdgpu_ucode_print_psp_hdr(&sos_hdr->header);
  90
  91         switch (sos_hdr->header.header_version_major) {
  92         case 1:
  93                 adev->psp.sos_fw_version = le32_to_cpu(sos_hdr->header.ucode_version);
  94                 adev->psp.sos_feature_version = le32_to_cpu(sos_hdr->ucode_feature_version);
  95                 adev->psp.sos_bin_size = le32_to_cpu(sos_hdr->sos_size_bytes);
  96                 adev->psp.sys_bin_size = le32_to_cpu(sos_hdr->sos_offset_bytes);
  97                 adev->psp.sys_start_addr = (uint8_t *)sos_hdr +
  98                                 le32_to_cpu(sos_hdr->header.ucode_array_offset_bytes);
  99                 adev->psp.sos_start_addr = (uint8_t *)adev->psp.sys_start_addr +
 100                                 le32_to_cpu(sos_hdr->sos_offset_bytes);
 101                 if (sos_hdr->header.header_version_minor == 1) {
 102                         sos_hdr_v1_1 = (const struct psp_firmware_header_v1_1 *)adev->psp.sos_fw->data;
 103                         adev->psp.toc_bin_size = le32_to_cpu(sos_hdr_v1_1->toc_size_bytes);
 104                         adev->psp.toc_start_addr = (uint8_t *)adev->psp.sys_start_addr +
 105                                         le32_to_cpu(sos_hdr_v1_1->toc_offset_bytes);
 106                         adev->psp.kdb_bin_size = le32_to_cpu(sos_hdr_v1_1->kdb_size_bytes);
 107                         adev->psp.kdb_start_addr = (uint8_t *)adev->psp.sys_start_addr +
 108                                         le32_to_cpu(sos_hdr_v1_1->kdb_offset_bytes);
 109                 }
 110                 break;
 111         default:
 112                 dev_err(adev->dev,
 113                         "Unsupported psp sos firmware\n");
 114                 err = -EINVAL;
 115                 goto out;
 116         }
 117
 118         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_asd.bin", chip_name);
 119         err = request_firmware(&adev->psp.asd_fw, fw_name, adev->dev);
 120         if (err)
 121                 goto out1;
 122
 123         err = amdgpu_ucode_validate(adev->psp.asd_fw);
 124         if (err)
 125                 goto out1;
 126
 127         asd_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.asd_fw->data;
 128         adev->psp.asd_fw_version = le32_to_cpu(asd_hdr->header.ucode_version);
 129         adev->psp.asd_feature_version = le32_to_cpu(asd_hdr->ucode_feature_version);
 130         adev->psp.asd_ucode_size = le32_to_cpu(asd_hdr->header.ucode_size_bytes);
 131         adev->psp.asd_start_addr = (uint8_t *)asd_hdr +
 132                                 le32_to_cpu(asd_hdr->header.ucode_array_offset_bytes);
 133
 134         switch (adev->asic_type) {
 135         case CHIP_VEGA20:
 136                 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ta.bin", chip_name);
 137                 err = request_firmware(&adev->psp.ta_fw, fw_name, adev->dev);
 138                 if (err) {
 139                         release_firmware(adev->psp.ta_fw);
 140                         adev->psp.ta_fw = NULL;
 141                         dev_info(adev->dev,
 142                                  "psp v11.0: Failed to load firmware \"%s\"\n", fw_name);
 143                 } else {
 144                         err = amdgpu_ucode_validate(adev->psp.ta_fw);
 145                         if (err)
 146                                 goto out2;
 147
 148                         ta_hdr = (const struct ta_firmware_header_v1_0 *)adev->psp.ta_fw->data;
 149                         adev->psp.ta_xgmi_ucode_version = le32_to_cpu(ta_hdr->ta_xgmi_ucode_version);
 150                         adev->psp.ta_xgmi_ucode_size = le32_to_cpu(ta_hdr->ta_xgmi_size_bytes);
 151                         adev->psp.ta_xgmi_start_addr = (uint8_t *)ta_hdr +
 152                                 le32_to_cpu(ta_hdr->header.ucode_array_offset_bytes);
 153                         adev->psp.ta_fw_version = le32_to_cpu(ta_hdr->header.ucode_version);
 154                         adev->psp.ta_ras_ucode_version = le32_to_cpu(ta_hdr->ta_ras_ucode_version);
 155                         adev->psp.ta_ras_ucode_size = le32_to_cpu(ta_hdr->ta_ras_size_bytes);
 156                         adev->psp.ta_ras_start_addr = (uint8_t *)adev->psp.ta_xgmi_start_addr +
 157                                 le32_to_cpu(ta_hdr->ta_ras_offset_bytes);
 158                 }
 159                 break;
 160         case CHIP_NAVI10:
 161                 break;
 162         default:
 163                 BUG();
 164         }
 165
 166         return 0;
 167
 168 out2:
 169         release_firmware(adev->psp.ta_fw);
 170         adev->psp.ta_fw = NULL;
 171 out1:
 172         release_firmware(adev->psp.asd_fw);
 173         adev->psp.asd_fw = NULL;
 174 out:
 175         dev_err(adev->dev,
 176                 "psp v11.0: Failed to load firmware \"%s\"\n", fw_name);
 177         release_firmware(adev->psp.sos_fw);
 178         adev->psp.sos_fw = NULL;
 179
 180         return err;
 181 }
 182
 183 static int psp_v11_0_bootloader_load_kdb(struct psp_context *psp)
 184 {
 185         int ret;
 186         uint32_t psp_gfxdrv_command_reg = 0;
 187         struct amdgpu_device *adev = psp->adev;
 188         uint32_t sol_reg;
 189
 190         /* Check tOS sign of life register to confirm sys driver and sOS
 191          * are already been loaded.
 192          */
 193         sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81);
 194         if (sol_reg) {
 195                 psp->sos_fw_version = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_58);
 196                 dev_info(adev->dev, "sos fw version = 0x%x.\n", psp->sos_fw_version);
 197                 return 0;
 198         }
 199
 200         /* Wait for bootloader to signify that is ready having bit 31 of C2PMSG_35 set to 1 */
 201         ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35),
 202                            0x80000000, 0x80000000, false);
 203         if (ret)
 204                 return ret;
 205
 206         memset(psp->fw_pri_buf, 0, PSP_1_MEG);
 207
 208         /* Copy PSP KDB binary to memory */
 209         memcpy(psp->fw_pri_buf, psp->kdb_start_addr, psp->kdb_bin_size);
 210
 211         /* Provide the sys driver to bootloader */
 212         WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36,
 213                (uint32_t)(psp->fw_pri_mc_addr >> 20));
 214         psp_gfxdrv_command_reg = PSP_BL__LOAD_KEY_DATABASE;
 215         WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35,
 216                psp_gfxdrv_command_reg);
 217
 218         /* Wait for bootloader to signify that is ready having  bit 31 of C2PMSG_35 set to 1*/
 219         ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35),
 220                            0x80000000, 0x80000000, false);
 221
 222         return ret;
 223 }
 224
 225 static int psp_v11_0_bootloader_load_sysdrv(struct psp_context *psp)
 226 {
 227         int ret;
 228         uint32_t psp_gfxdrv_command_reg = 0;
 229         struct amdgpu_device *adev = psp->adev;
 230         uint32_t sol_reg;
 231
 232         /* Check sOS sign of life register to confirm sys driver and sOS
 233          * are already been loaded.
 234          */
 235         sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81);
 236         if (sol_reg) {
 237                 psp->sos_fw_version = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_58);
 238                 dev_info(adev->dev, "sos fw version = 0x%x.\n", psp->sos_fw_version);
 239                 return 0;
 240         }
 241
 242         /* Wait for bootloader to signify that is ready having bit 31 of C2PMSG_35 set to 1 */
 243         ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35),
 244                            0x80000000, 0x80000000, false);
 245         if (ret)
 246                 return ret;
 247
 248         memset(psp->fw_pri_buf, 0, PSP_1_MEG);
 249
 250         /* Copy PSP System Driver binary to memory */
 251         memcpy(psp->fw_pri_buf, psp->sys_start_addr, psp->sys_bin_size);
 252
 253         /* Provide the sys driver to bootloader */
 254         WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36,
 255                (uint32_t)(psp->fw_pri_mc_addr >> 20));
 256         psp_gfxdrv_command_reg = PSP_BL__LOAD_SYSDRV;
 257         WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35,
 258                psp_gfxdrv_command_reg);
 259
 260         /* there might be handshake issue with hardware which needs delay */
 261         mdelay(20);
 262
 263         ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35),
 264                            0x80000000, 0x80000000, false);
 265
 266         return ret;
 267 }
 268
 269 static int psp_v11_0_bootloader_load_sos(struct psp_context *psp)
 270 {
 271         int ret;
 272         unsigned int psp_gfxdrv_command_reg = 0;
 273         struct amdgpu_device *adev = psp->adev;
 274         uint32_t sol_reg;
 275
 276         /* Check sOS sign of life register to confirm sys driver and sOS
 277          * are already been loaded.
 278          */
 279         sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81);
 280         if (sol_reg)
 281                 return 0;
 282
 283         /* Wait for bootloader to signify that is ready having bit 31 of C2PMSG_35 set to 1 */
 284         ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35),
 285                            0x80000000, 0x80000000, false);
 286         if (ret)
 287                 return ret;
 288
 289         memset(psp->fw_pri_buf, 0, PSP_1_MEG);
 290
 291         /* Copy Secure OS binary to PSP memory */
 292         memcpy(psp->fw_pri_buf, psp->sos_start_addr, psp->sos_bin_size);
 293
 294         /* Provide the PSP secure OS to bootloader */
 295         WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36,
 296                (uint32_t)(psp->fw_pri_mc_addr >> 20));
 297         psp_gfxdrv_command_reg = PSP_BL__LOAD_SOSDRV;
 298         WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35,
 299                psp_gfxdrv_command_reg);
 300
 301         /* there might be handshake issue with hardware which needs delay */
 302         mdelay(20);
 303         ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_81),
 304                            RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81),
 305                            0, true);
 306
 307         return ret;
 308 }
 309
 310 static void psp_v11_0_reroute_ih(struct psp_context *psp)
 311 {
 312         struct amdgpu_device *adev = psp->adev;
 313         uint32_t tmp;
 314
 315         /* Change IH ring for VMC */
 316         tmp = REG_SET_FIELD(0, IH_CLIENT_CFG_DATA, CREDIT_RETURN_ADDR, 0x1244b);
 317         tmp = REG_SET_FIELD(tmp, IH_CLIENT_CFG_DATA, CLIENT_TYPE, 1);
 318         tmp = REG_SET_FIELD(tmp, IH_CLIENT_CFG_DATA, RING_ID, 1);
 319
 320         WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_69, 3);
 321         WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_70, tmp);
 322         WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, GFX_CTRL_CMD_ID_GBR_IH_SET);
 323
 324         mdelay(20);
 325         psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
 326                      0x80000000, 0x8000FFFF, false);
 327
 328         /* Change IH ring for UMC */
 329         tmp = REG_SET_FIELD(0, IH_CLIENT_CFG_DATA, CREDIT_RETURN_ADDR, 0x1216b);
 330         tmp = REG_SET_FIELD(tmp, IH_CLIENT_CFG_DATA, RING_ID, 1);
 331
 332         WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_69, 4);
 333         WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_70, tmp);
 334         WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, GFX_CTRL_CMD_ID_GBR_IH_SET);
 335
 336         mdelay(20);
 337         psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
 338                      0x80000000, 0x8000FFFF, false);
 339 }
 340
 341 static int psp_v11_0_ring_init(struct psp_context *psp,
 342                               enum psp_ring_type ring_type)
 343 {
 344         int ret = 0;
 345         struct psp_ring *ring;
 346         struct amdgpu_device *adev = psp->adev;
 347
 348         psp_v11_0_reroute_ih(psp);
 349
 350         ring = &psp->km_ring;
 351
 352         ring->ring_type = ring_type;
 353
 354         /* allocate 4k Page of Local Frame Buffer memory for ring */
 355         ring->ring_size = 0x1000;
 356         ret = amdgpu_bo_create_kernel(adev, ring->ring_size, PAGE_SIZE,
 357                                       AMDGPU_GEM_DOMAIN_VRAM,
 358                                       &adev->firmware.rbuf,
 359                                       &ring->ring_mem_mc_addr,
 360                                       (void **)&ring->ring_mem);
 361         if (ret) {
 362                 ring->ring_size = 0;
 363                 return ret;
 364         }
 365
 366         return 0;
 367 }
 368
 369 static bool psp_v11_0_support_vmr_ring(struct psp_context *psp)
 370 {
 371         if (amdgpu_sriov_vf(psp->adev) && psp->sos_fw_version > 0x80045)
 372                 return true;
 373         return false;
 374 }
 375
 376 static int psp_v11_0_ring_create(struct psp_context *psp,
 377                                 enum psp_ring_type ring_type)
 378 {
 379         int ret = 0;
 380         unsigned int psp_ring_reg = 0;
 381         struct psp_ring *ring = &psp->km_ring;
 382         struct amdgpu_device *adev = psp->adev;
 383
 384         if (psp_v11_0_support_vmr_ring(psp)) {
 385                 /* Write low address of the ring to C2PMSG_102 */
 386                 psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr);
 387                 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_102, psp_ring_reg);
 388                 /* Write high address of the ring to C2PMSG_103 */
 389                 psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr);
 390                 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_103, psp_ring_reg);
 391
 392                 /* Write the ring initialization command to C2PMSG_101 */
 393                 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101,
 394                                              GFX_CTRL_CMD_ID_INIT_GPCOM_RING);
 395
 396                 /* there might be handshake issue with hardware which needs delay */
 397                 mdelay(20);
 398
 399                 /* Wait for response flag (bit 31) in C2PMSG_101 */
 400                 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_101),
 401                                    0x80000000, 0x8000FFFF, false);
 402
 403         } else {
 404                 /* Write low address of the ring to C2PMSG_69 */
 405                 psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr);
 406                 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_69, psp_ring_reg);
 407                 /* Write high address of the ring to C2PMSG_70 */
 408                 psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr);
 409                 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_70, psp_ring_reg);
 410                 /* Write size of ring to C2PMSG_71 */
 411                 psp_ring_reg = ring->ring_size;
 412                 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_71, psp_ring_reg);
 413                 /* Write the ring initialization command to C2PMSG_64 */
 414                 psp_ring_reg = ring_type;
 415                 psp_ring_reg = psp_ring_reg << 16;
 416                 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, psp_ring_reg);
 417
 418                 /* there might be handshake issue with hardware which needs delay */
 419                 mdelay(20);
 420
 421                 /* Wait for response flag (bit 31) in C2PMSG_64 */
 422                 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
 423                                    0x80000000, 0x8000FFFF, false);
 424         }
 425
 426         return ret;
 427 }
 428
 429 static int psp_v11_0_ring_stop(struct psp_context *psp,
 430                               enum psp_ring_type ring_type)
 431 {
 432         int ret = 0;
 433         struct amdgpu_device *adev = psp->adev;
 434
 435         /* Write the ring destroy command*/
 436         if (psp_v11_0_support_vmr_ring(psp))
 437                 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101,
 438                                      GFX_CTRL_CMD_ID_DESTROY_GPCOM_RING);
 439         else
 440                 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64,
 441                                      GFX_CTRL_CMD_ID_DESTROY_RINGS);
 442
 443         /* there might be handshake issue with hardware which needs delay */
 444         mdelay(20);
 445
 446         /* Wait for response flag (bit 31) */
 447         if (psp_v11_0_support_vmr_ring(psp))
 448                 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_101),
 449                                    0x80000000, 0x80000000, false);
 450         else
 451                 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
 452                                    0x80000000, 0x80000000, false);
 453
 454         return ret;
 455 }
 456
 457 static int psp_v11_0_ring_destroy(struct psp_context *psp,
 458                                  enum psp_ring_type ring_type)
 459 {
 460         int ret = 0;
 461         struct psp_ring *ring = &psp->km_ring;
 462         struct amdgpu_device *adev = psp->adev;
 463
 464         ret = psp_v11_0_ring_stop(psp, ring_type);
 465         if (ret)
 466                 DRM_ERROR("Fail to stop psp ring\n");
 467
 468         amdgpu_bo_free_kernel(&adev->firmware.rbuf,
 469                               &ring->ring_mem_mc_addr,
 470                               (void **)&ring->ring_mem);
 471
 472         return ret;
 473 }
 474
 475 static int psp_v11_0_cmd_submit(struct psp_context *psp,
 476                                struct amdgpu_firmware_info *ucode,
 477                                uint64_t cmd_buf_mc_addr, uint64_t fence_mc_addr,
 478                                int index)
 479 {
 480         unsigned int psp_write_ptr_reg = 0;
 481         struct psp_gfx_rb_frame *write_frame = psp->km_ring.ring_mem;
 482         struct psp_ring *ring = &psp->km_ring;
 483         struct psp_gfx_rb_frame *ring_buffer_start = ring->ring_mem;
 484         struct psp_gfx_rb_frame *ring_buffer_end = ring_buffer_start +
 485                 ring->ring_size / sizeof(struct psp_gfx_rb_frame) - 1;
 486         struct amdgpu_device *adev = psp->adev;
 487         uint32_t ring_size_dw = ring->ring_size / 4;
 488         uint32_t rb_frame_size_dw = sizeof(struct psp_gfx_rb_frame) / 4;
 489
 490         /* KM (GPCOM) prepare write pointer */
 491         if (psp_v11_0_support_vmr_ring(psp))
 492                 psp_write_ptr_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_102);
 493         else
 494                 psp_write_ptr_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67);
 495
 496         /* Update KM RB frame pointer to new frame */
 497         /* write_frame ptr increments by size of rb_frame in bytes */
 498         /* psp_write_ptr_reg increments by size of rb_frame in DWORDs */
 499         if ((psp_write_ptr_reg % ring_size_dw) == 0)
 500                 write_frame = ring_buffer_start;
 501         else
 502                 write_frame = ring_buffer_start + (psp_write_ptr_reg / rb_frame_size_dw);
 503         /* Check invalid write_frame ptr address */
 504         if ((write_frame < ring_buffer_start) || (ring_buffer_end < write_frame)) {
 505                 DRM_ERROR("ring_buffer_start = %p; ring_buffer_end = %p; write_frame = %p\n",
 506                           ring_buffer_start, ring_buffer_end, write_frame);
 507                 DRM_ERROR("write_frame is pointing to address out of bounds\n");
 508                 return -EINVAL;
 509         }
 510
 511         /* Initialize KM RB frame */
 512         memset(write_frame, 0, sizeof(struct psp_gfx_rb_frame));
 513
 514         /* Update KM RB frame */
 515         write_frame->cmd_buf_addr_hi = upper_32_bits(cmd_buf_mc_addr);
 516         write_frame->cmd_buf_addr_lo = lower_32_bits(cmd_buf_mc_addr);
 517         write_frame->fence_addr_hi = upper_32_bits(fence_mc_addr);
 518         write_frame->fence_addr_lo = lower_32_bits(fence_mc_addr);
 519         write_frame->fence_value = index;
 520
 521         /* Update the write Pointer in DWORDs */
 522         psp_write_ptr_reg = (psp_write_ptr_reg + rb_frame_size_dw) % ring_size_dw;
 523         if (psp_v11_0_support_vmr_ring(psp)) {
 524                 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_102, psp_write_ptr_reg);
 525                 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101, GFX_CTRL_CMD_ID_CONSUME_CMD);
 526         } else
 527                 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67, psp_write_ptr_reg);
 528
 529         return 0;
 530 }
 531
 532 static int
 533 psp_v11_0_sram_map(struct amdgpu_device *adev,
 534                   unsigned int *sram_offset, unsigned int *sram_addr_reg_offset,
 535                   unsigned int *sram_data_reg_offset,
 536                   enum AMDGPU_UCODE_ID ucode_id)
 537 {
 538         int ret = 0;
 539
 540         switch (ucode_id) {
 541 /* TODO: needs to confirm */
 542 #if 0
 543         case AMDGPU_UCODE_ID_SMC:
 544                 *sram_offset = 0;
 545                 *sram_addr_reg_offset = 0;
 546                 *sram_data_reg_offset = 0;
 547                 break;
 548 #endif
 549
 550         case AMDGPU_UCODE_ID_CP_CE:
 551                 *sram_offset = 0x0;
 552                 *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_CE_UCODE_ADDR);
 553                 *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_CE_UCODE_DATA);
 554                 break;
 555
 556         case AMDGPU_UCODE_ID_CP_PFP:
 557                 *sram_offset = 0x0;
 558                 *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_PFP_UCODE_ADDR);
 559                 *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_PFP_UCODE_DATA);
 560                 break;
 561
 562         case AMDGPU_UCODE_ID_CP_ME:
 563                 *sram_offset = 0x0;
 564                 *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_ME_UCODE_ADDR);
 565                 *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_ME_UCODE_DATA);
 566                 break;
 567
 568         case AMDGPU_UCODE_ID_CP_MEC1:
 569                 *sram_offset = 0x10000;
 570                 *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_MEC_ME1_UCODE_ADDR);
 571                 *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_MEC_ME1_UCODE_DATA);
 572                 break;
 573
 574         case AMDGPU_UCODE_ID_CP_MEC2:
 575                 *sram_offset = 0x10000;
 576                 *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_MEC2_UCODE_ADDR);
 577                 *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_MEC2_UCODE_DATA);
 578                 break;
 579
 580         case AMDGPU_UCODE_ID_RLC_G:
 581                 *sram_offset = 0x2000;
 582                 if (adev->asic_type < CHIP_NAVI10) {
 583                         *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_UCODE_ADDR);
 584                         *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_UCODE_DATA);
 585                 } else {
 586                         *sram_addr_reg_offset = adev->reg_offset[GC_HWIP][0][1] + mmRLC_GPM_UCODE_ADDR_NV10;
 587                         *sram_data_reg_offset = adev->reg_offset[GC_HWIP][0][1] + mmRLC_GPM_UCODE_DATA_NV10;
 588                 }
 589                 break;
 590
 591         case AMDGPU_UCODE_ID_SDMA0:
 592                 *sram_offset = 0x0;
 593                 if (adev->asic_type < CHIP_NAVI10) {
 594                         *sram_addr_reg_offset = SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_UCODE_ADDR);
 595                         *sram_data_reg_offset = SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_UCODE_DATA);
 596                 } else {
 597                         *sram_addr_reg_offset = adev->reg_offset[GC_HWIP][0][1] + mmSDMA0_UCODE_ADDR_NV10;
 598                         *sram_data_reg_offset = adev->reg_offset[GC_HWIP][0][1] + mmSDMA0_UCODE_DATA_NV10;
 599                 }
 600                 break;
 601
 602 /* TODO: needs to confirm */
 603 #if 0
 604         case AMDGPU_UCODE_ID_SDMA1:
 605                 *sram_offset = ;
 606                 *sram_addr_reg_offset = ;
 607                 break;
 608
 609         case AMDGPU_UCODE_ID_UVD:
 610                 *sram_offset = ;
 611                 *sram_addr_reg_offset = ;
 612                 break;
 613
 614         case AMDGPU_UCODE_ID_VCE:
 615                 *sram_offset = ;
 616                 *sram_addr_reg_offset = ;
 617                 break;
 618 #endif
 619
 620         case AMDGPU_UCODE_ID_MAXIMUM:
 621         default:
 622                 ret = -EINVAL;
 623                 break;
 624         }
 625
 626         return ret;
 627 }
 628
 629 static bool psp_v11_0_compare_sram_data(struct psp_context *psp,
 630                                        struct amdgpu_firmware_info *ucode,
 631                                        enum AMDGPU_UCODE_ID ucode_type)
 632 {
 633         int err = 0;
 634         unsigned int fw_sram_reg_val = 0;
 635         unsigned int fw_sram_addr_reg_offset = 0;
 636         unsigned int fw_sram_data_reg_offset = 0;
 637         unsigned int ucode_size;
 638         uint32_t *ucode_mem = NULL;
 639         struct amdgpu_device *adev = psp->adev;
 640
 641         err = psp_v11_0_sram_map(adev, &fw_sram_reg_val, &fw_sram_addr_reg_offset,
 642                                 &fw_sram_data_reg_offset, ucode_type);
 643         if (err)
 644                 return false;
 645
 646         WREG32(fw_sram_addr_reg_offset, fw_sram_reg_val);
 647
 648         ucode_size = ucode->ucode_size;
 649         ucode_mem = (uint32_t *)ucode->kaddr;
 650         while (ucode_size) {
 651                 fw_sram_reg_val = RREG32(fw_sram_data_reg_offset);
 652
 653                 if (*ucode_mem != fw_sram_reg_val)
 654                         return false;
 655
 656                 ucode_mem++;
 657                 /* 4 bytes */
 658                 ucode_size -= 4;
 659         }
 660
 661         return true;
 662 }
 663
 664 static int psp_v11_0_mode1_reset(struct psp_context *psp)
 665 {
 666         int ret;
 667         uint32_t offset;
 668         struct amdgpu_device *adev = psp->adev;
 669
 670         offset = SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64);
 671
 672         ret = psp_wait_for(psp, offset, 0x80000000, 0x8000FFFF, false);
 673
 674         if (ret) {
 675                 DRM_INFO("psp is not working correctly before mode1 reset!\n");
 676                 return -EINVAL;
 677         }
 678
 679         /*send the mode 1 reset command*/
 680         WREG32(offset, GFX_CTRL_CMD_ID_MODE1_RST);
 681
 682         msleep(500);
 683
 684         offset = SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_33);
 685
 686         ret = psp_wait_for(psp, offset, 0x80000000, 0x80000000, false);
 687
 688         if (ret) {
 689                 DRM_INFO("psp mode 1 reset failed!\n");
 690                 return -EINVAL;
 691         }
 692
 693         DRM_INFO("psp mode1 reset succeed \n");
 694
 695         return 0;
 696 }
 697
 698 /* TODO: Fill in follow functions once PSP firmware interface for XGMI is ready.
 699  * For now, return success and hack the hive_id so high level code can
 700  * start testing
 701  */
 702 static int psp_v11_0_xgmi_get_topology_info(struct psp_context *psp,
 703         int number_devices, struct psp_xgmi_topology_info *topology)
 704 {
 705         struct ta_xgmi_shared_memory *xgmi_cmd;
 706         struct ta_xgmi_cmd_get_topology_info_input *topology_info_input;
 707         struct ta_xgmi_cmd_get_topology_info_output *topology_info_output;
 708         int i;
 709         int ret;
 710
 711         if (!topology || topology->num_nodes > TA_XGMI__MAX_CONNECTED_NODES)
 712                 return -EINVAL;
 713
 714         xgmi_cmd = (struct ta_xgmi_shared_memory*)psp->xgmi_context.xgmi_shared_buf;
 715         memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory));
 716
 717         /* Fill in the shared memory with topology information as input */
 718         topology_info_input = &xgmi_cmd->xgmi_in_message.get_topology_info;
 719         xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_GET_TOPOLOGY_INFO;
 720         topology_info_input->num_nodes = number_devices;
 721
 722         for (i = 0; i < topology_info_input->num_nodes; i++) {
 723                 topology_info_input->nodes[i].node_id = topology->nodes[i].node_id;
 724                 topology_info_input->nodes[i].num_hops = topology->nodes[i].num_hops;
 725                 topology_info_input->nodes[i].is_sharing_enabled = topology->nodes[i].is_sharing_enabled;
 726                 topology_info_input->nodes[i].sdma_engine = topology->nodes[i].sdma_engine;
 727         }
 728
 729         /* Invoke xgmi ta to get the topology information */
 730         ret = psp_xgmi_invoke(psp, TA_COMMAND_XGMI__GET_GET_TOPOLOGY_INFO);
 731         if (ret)
 732                 return ret;
 733
 734         /* Read the output topology information from the shared memory */
 735         topology_info_output = &xgmi_cmd->xgmi_out_message.get_topology_info;
 736         topology->num_nodes = xgmi_cmd->xgmi_out_message.get_topology_info.num_nodes;
 737         for (i = 0; i < topology->num_nodes; i++) {
 738                 topology->nodes[i].node_id = topology_info_output->nodes[i].node_id;
 739                 topology->nodes[i].num_hops = topology_info_output->nodes[i].num_hops;
 740                 topology->nodes[i].is_sharing_enabled = topology_info_output->nodes[i].is_sharing_enabled;
 741                 topology->nodes[i].sdma_engine = topology_info_output->nodes[i].sdma_engine;
 742         }
 743
 744         return 0;
 745 }
 746
 747 static int psp_v11_0_xgmi_set_topology_info(struct psp_context *psp,
 748         int number_devices, struct psp_xgmi_topology_info *topology)
 749 {
 750         struct ta_xgmi_shared_memory *xgmi_cmd;
 751         struct ta_xgmi_cmd_get_topology_info_input *topology_info_input;
 752         int i;
 753
 754         if (!topology || topology->num_nodes > TA_XGMI__MAX_CONNECTED_NODES)
 755                 return -EINVAL;
 756
 757         xgmi_cmd = (struct ta_xgmi_shared_memory*)psp->xgmi_context.xgmi_shared_buf;
 758         memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory));
 759
 760         topology_info_input = &xgmi_cmd->xgmi_in_message.get_topology_info;
 761         xgmi_cmd->cmd_id = TA_COMMAND_XGMI__SET_TOPOLOGY_INFO;
 762         topology_info_input->num_nodes = number_devices;
 763
 764         for (i = 0; i < topology_info_input->num_nodes; i++) {
 765                 topology_info_input->nodes[i].node_id = topology->nodes[i].node_id;
 766                 topology_info_input->nodes[i].num_hops = topology->nodes[i].num_hops;
 767                 topology_info_input->nodes[i].is_sharing_enabled = 1;
 768                 topology_info_input->nodes[i].sdma_engine = topology->nodes[i].sdma_engine;
 769         }
 770
 771         /* Invoke xgmi ta to set topology information */
 772         return psp_xgmi_invoke(psp, TA_COMMAND_XGMI__SET_TOPOLOGY_INFO);
 773 }
 774
 775 static int psp_v11_0_xgmi_get_hive_id(struct psp_context *psp, uint64_t *hive_id)
 776 {
 777         struct ta_xgmi_shared_memory *xgmi_cmd;
 778         int ret;
 779
 780         xgmi_cmd = (struct ta_xgmi_shared_memory*)psp->xgmi_context.xgmi_shared_buf;
 781         memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory));
 782
 783         xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_HIVE_ID;
 784
 785         /* Invoke xgmi ta to get hive id */
 786         ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id);
 787         if (ret)
 788                 return ret;
 789
 790         *hive_id = xgmi_cmd->xgmi_out_message.get_hive_id.hive_id;
 791
 792         return 0;
 793 }
 794
 795 static int psp_v11_0_xgmi_get_node_id(struct psp_context *psp, uint64_t *node_id)
 796 {
 797         struct ta_xgmi_shared_memory *xgmi_cmd;
 798         int ret;
 799
 800         xgmi_cmd = (struct ta_xgmi_shared_memory*)psp->xgmi_context.xgmi_shared_buf;
 801         memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory));
 802
 803         xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_NODE_ID;
 804
 805         /* Invoke xgmi ta to get the node id */
 806         ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id);
 807         if (ret)
 808                 return ret;
 809
 810         *node_id = xgmi_cmd->xgmi_out_message.get_node_id.node_id;
 811
 812         return 0;
 813 }
 814
 815 static int psp_v11_0_ras_trigger_error(struct psp_context *psp,
 816                 struct ta_ras_trigger_error_input *info)
 817 {
 818         struct ta_ras_shared_memory *ras_cmd;
 819         int ret;
 820
 821         if (!psp->ras.ras_initialized)
 822                 return -EINVAL;
 823
 824         ras_cmd = (struct ta_ras_shared_memory *)psp->ras.ras_shared_buf;
 825         memset(ras_cmd, 0, sizeof(struct ta_ras_shared_memory));
 826
 827         ras_cmd->cmd_id = TA_RAS_COMMAND__TRIGGER_ERROR;
 828         ras_cmd->ras_in_message.trigger_error = *info;
 829
 830         ret = psp_ras_invoke(psp, ras_cmd->cmd_id);
 831         if (ret)
 832                 return -EINVAL;
 833
 834         return ras_cmd->ras_status;
 835 }
 836
 837 static int psp_v11_0_ras_cure_posion(struct psp_context *psp, uint64_t *mode_ptr)
 838 {
 839 #if 0
 840         // not support yet.
 841         struct ta_ras_shared_memory *ras_cmd;
 842         int ret;
 843
 844         if (!psp->ras.ras_initialized)
 845                 return -EINVAL;
 846
 847         ras_cmd = (struct ta_ras_shared_memory *)psp->ras.ras_shared_buf;
 848         memset(ras_cmd, 0, sizeof(struct ta_ras_shared_memory));
 849
 850         ras_cmd->cmd_id = TA_RAS_COMMAND__CURE_POISON;
 851         ras_cmd->ras_in_message.cure_poison.mode_ptr = mode_ptr;
 852
 853         ret = psp_ras_invoke(psp, ras_cmd->cmd_id);
 854         if (ret)
 855                 return -EINVAL;
 856
 857         return ras_cmd->ras_status;
 858 #else
 859         return -EINVAL;
 860 #endif
 861 }
 862
 863 static int psp_v11_0_rlc_autoload_start(struct psp_context *psp)
 864 {
 865         return psp_rlc_autoload_start(psp);
 866 }
 867
 868 static const struct psp_funcs psp_v11_0_funcs = {
 869         .init_microcode = psp_v11_0_init_microcode,
 870         .bootloader_load_kdb = psp_v11_0_bootloader_load_kdb,
 871         .bootloader_load_sysdrv = psp_v11_0_bootloader_load_sysdrv,
 872         .bootloader_load_sos = psp_v11_0_bootloader_load_sos,
 873         .ring_init = psp_v11_0_ring_init,
 874         .ring_create = psp_v11_0_ring_create,
 875         .ring_stop = psp_v11_0_ring_stop,
 876         .ring_destroy = psp_v11_0_ring_destroy,
 877         .cmd_submit = psp_v11_0_cmd_submit,
 878         .compare_sram_data = psp_v11_0_compare_sram_data,
 879         .mode1_reset = psp_v11_0_mode1_reset,
 880         .xgmi_get_topology_info = psp_v11_0_xgmi_get_topology_info,
 881         .xgmi_set_topology_info = psp_v11_0_xgmi_set_topology_info,
 882         .xgmi_get_hive_id = psp_v11_0_xgmi_get_hive_id,
 883         .xgmi_get_node_id = psp_v11_0_xgmi_get_node_id,
 884         .support_vmr_ring = psp_v11_0_support_vmr_ring,
 885         .ras_trigger_error = psp_v11_0_ras_trigger_error,
 886         .ras_cure_posion = psp_v11_0_ras_cure_posion,
 887         .rlc_autoload_start = psp_v11_0_rlc_autoload_start,
 888 };
 889
 890 void psp_v11_0_set_psp_funcs(struct psp_context *psp)
 891 {
 892         psp->funcs = &psp_v11_0_funcs;
 893 }