2 * Copyright 2016 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
26 #include <linux/firmware.h>
27 #include <linux/module.h>
28 #include <linux/pci.h>
31 #include "amdgpu_psp.h"
32 #include "amdgpu_ucode.h"
33 #include "soc15_common.h"
34 #include "psp_v10_0.h"
36 #include "mp/mp_10_0_offset.h"
37 #include "gc/gc_9_1_offset.h"
38 #include "sdma0/sdma0_4_1_offset.h"
40 MODULE_FIRMWARE("amdgpu/raven_asd.bin");
41 MODULE_FIRMWARE("amdgpu/picasso_asd.bin");
42 MODULE_FIRMWARE("amdgpu/raven2_asd.bin");
43 MODULE_FIRMWARE("amdgpu/picasso_ta.bin");
44 MODULE_FIRMWARE("amdgpu/raven2_ta.bin");
45 MODULE_FIRMWARE("amdgpu/raven_ta.bin");
47 static int psp_v10_0_init_microcode(struct psp_context *psp)
49 struct amdgpu_device *adev = psp->adev;
50 const char *chip_name;
53 const struct ta_firmware_header_v1_0 *ta_hdr;
56 switch (adev->asic_type) {
58 if (adev->rev_id >= 0x8)
60 else if (adev->pdev->device == 0x15d8)
61 chip_name = "picasso";
68 err = psp_init_asd_microcode(psp, chip_name);
72 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ta.bin", chip_name);
73 err = request_firmware(&adev->psp.ta_fw, fw_name, adev->dev);
75 release_firmware(adev->psp.ta_fw);
76 adev->psp.ta_fw = NULL;
78 "psp v10.0: Failed to load firmware \"%s\"\n",
81 err = amdgpu_ucode_validate(adev->psp.ta_fw);
85 ta_hdr = (const struct ta_firmware_header_v1_0 *)
86 adev->psp.ta_fw->data;
87 adev->psp.ta_hdcp_ucode_version =
88 le32_to_cpu(ta_hdr->ta_hdcp_ucode_version);
89 adev->psp.ta_hdcp_ucode_size =
90 le32_to_cpu(ta_hdr->ta_hdcp_size_bytes);
91 adev->psp.ta_hdcp_start_addr =
93 le32_to_cpu(ta_hdr->header.ucode_array_offset_bytes);
95 adev->psp.ta_fw_version = le32_to_cpu(ta_hdr->header.ucode_version);
97 adev->psp.ta_dtm_ucode_version =
98 le32_to_cpu(ta_hdr->ta_dtm_ucode_version);
99 adev->psp.ta_dtm_ucode_size =
100 le32_to_cpu(ta_hdr->ta_dtm_size_bytes);
101 adev->psp.ta_dtm_start_addr =
102 (uint8_t *)adev->psp.ta_hdcp_start_addr +
103 le32_to_cpu(ta_hdr->ta_dtm_offset_bytes);
109 release_firmware(adev->psp.ta_fw);
110 adev->psp.ta_fw = NULL;
114 "psp v10.0: Failed to load firmware \"%s\"\n",
121 static int psp_v10_0_ring_init(struct psp_context *psp,
122 enum psp_ring_type ring_type)
125 struct psp_ring *ring;
126 struct amdgpu_device *adev = psp->adev;
128 ring = &psp->km_ring;
130 ring->ring_type = ring_type;
132 /* allocate 4k Page of Local Frame Buffer memory for ring */
133 ring->ring_size = 0x1000;
134 ret = amdgpu_bo_create_kernel(adev, ring->ring_size, PAGE_SIZE,
135 AMDGPU_GEM_DOMAIN_VRAM,
136 &adev->firmware.rbuf,
137 &ring->ring_mem_mc_addr,
138 (void **)&ring->ring_mem);
147 static int psp_v10_0_ring_create(struct psp_context *psp,
148 enum psp_ring_type ring_type)
151 unsigned int psp_ring_reg = 0;
152 struct psp_ring *ring = &psp->km_ring;
153 struct amdgpu_device *adev = psp->adev;
155 /* Write low address of the ring to C2PMSG_69 */
156 psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr);
157 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_69, psp_ring_reg);
158 /* Write high address of the ring to C2PMSG_70 */
159 psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr);
160 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_70, psp_ring_reg);
161 /* Write size of ring to C2PMSG_71 */
162 psp_ring_reg = ring->ring_size;
163 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_71, psp_ring_reg);
164 /* Write the ring initialization command to C2PMSG_64 */
165 psp_ring_reg = ring_type;
166 psp_ring_reg = psp_ring_reg << 16;
167 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, psp_ring_reg);
169 /* There might be handshake issue with hardware which needs delay */
172 /* Wait for response flag (bit 31) in C2PMSG_64 */
173 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
174 0x80000000, 0x8000FFFF, false);
179 static int psp_v10_0_ring_stop(struct psp_context *psp,
180 enum psp_ring_type ring_type)
183 unsigned int psp_ring_reg = 0;
184 struct amdgpu_device *adev = psp->adev;
186 /* Write the ring destroy command to C2PMSG_64 */
187 psp_ring_reg = 3 << 16;
188 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, psp_ring_reg);
190 /* There might be handshake issue with hardware which needs delay */
193 /* Wait for response flag (bit 31) in C2PMSG_64 */
194 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
195 0x80000000, 0x80000000, false);
200 static int psp_v10_0_ring_destroy(struct psp_context *psp,
201 enum psp_ring_type ring_type)
204 struct psp_ring *ring = &psp->km_ring;
205 struct amdgpu_device *adev = psp->adev;
207 ret = psp_v10_0_ring_stop(psp, ring_type);
209 DRM_ERROR("Fail to stop psp ring\n");
211 amdgpu_bo_free_kernel(&adev->firmware.rbuf,
212 &ring->ring_mem_mc_addr,
213 (void **)&ring->ring_mem);
218 static int psp_v10_0_mode1_reset(struct psp_context *psp)
220 DRM_INFO("psp mode 1 reset not supported now! \n");
224 static uint32_t psp_v10_0_ring_get_wptr(struct psp_context *psp)
226 struct amdgpu_device *adev = psp->adev;
228 return RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67);
231 static void psp_v10_0_ring_set_wptr(struct psp_context *psp, uint32_t value)
233 struct amdgpu_device *adev = psp->adev;
235 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67, value);
238 static const struct psp_funcs psp_v10_0_funcs = {
239 .init_microcode = psp_v10_0_init_microcode,
240 .ring_init = psp_v10_0_ring_init,
241 .ring_create = psp_v10_0_ring_create,
242 .ring_stop = psp_v10_0_ring_stop,
243 .ring_destroy = psp_v10_0_ring_destroy,
244 .mode1_reset = psp_v10_0_mode1_reset,
245 .ring_get_wptr = psp_v10_0_ring_get_wptr,
246 .ring_set_wptr = psp_v10_0_ring_set_wptr,
249 void psp_v10_0_set_psp_funcs(struct psp_context *psp)
251 psp->funcs = &psp_v10_0_funcs;