2 * Copyright 2019 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
23 #include <linux/firmware.h>
24 #include <linux/slab.h>
25 #include <linux/module.h>
26 #include <linux/pci.h>
28 #include <drm/amdgpu_drm.h>
31 #include "amdgpu_atombios.h"
32 #include "amdgpu_ih.h"
33 #include "amdgpu_uvd.h"
34 #include "amdgpu_vce.h"
35 #include "amdgpu_ucode.h"
36 #include "amdgpu_psp.h"
40 #include "gc/gc_10_1_0_offset.h"
41 #include "gc/gc_10_1_0_sh_mask.h"
42 #include "mp/mp_11_0_offset.h"
45 #include "soc15_common.h"
46 #include "gmc_v10_0.h"
47 #include "gfxhub_v2_0.h"
48 #include "mmhub_v2_0.h"
49 #include "nbio_v2_3.h"
50 #include "nbio_v7_2.h"
53 #include "navi10_ih.h"
54 #include "gfx_v10_0.h"
55 #include "sdma_v5_0.h"
56 #include "sdma_v5_2.h"
58 #include "jpeg_v2_0.h"
60 #include "jpeg_v3_0.h"
61 #include "dce_virtual.h"
62 #include "mes_v10_1.h"
64 #include "smuio_v11_0.h"
65 #include "smuio_v11_0_6.h"
67 #define codec_info_build(type, width, height, level) \
70 .max_height = height,\
71 .max_pixels_per_frame = height * width,\
74 static const struct amd_ip_funcs nv_common_ip_funcs;
77 static const struct amdgpu_video_codec_info nv_video_codecs_encode_array[] =
80 .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC,
83 .max_pixels_per_frame = 4096 * 2304,
87 .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC,
90 .max_pixels_per_frame = 4096 * 2304,
95 static const struct amdgpu_video_codecs nv_video_codecs_encode =
97 .codec_count = ARRAY_SIZE(nv_video_codecs_encode_array),
98 .codec_array = nv_video_codecs_encode_array,
102 static const struct amdgpu_video_codec_info nv_video_codecs_decode_array[] =
105 .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2,
108 .max_pixels_per_frame = 4096 * 4096,
112 .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4,
115 .max_pixels_per_frame = 4096 * 4096,
119 .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC,
122 .max_pixels_per_frame = 4096 * 4096,
126 .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1,
129 .max_pixels_per_frame = 4096 * 4096,
133 .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC,
136 .max_pixels_per_frame = 8192 * 4352,
140 .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG,
143 .max_pixels_per_frame = 4096 * 4096,
147 .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9,
150 .max_pixels_per_frame = 8192 * 4352,
155 static const struct amdgpu_video_codecs nv_video_codecs_decode =
157 .codec_count = ARRAY_SIZE(nv_video_codecs_decode_array),
158 .codec_array = nv_video_codecs_decode_array,
162 static const struct amdgpu_video_codec_info sc_video_codecs_decode_array[] =
165 .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2,
168 .max_pixels_per_frame = 4096 * 4096,
172 .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4,
175 .max_pixels_per_frame = 4096 * 4096,
179 .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC,
182 .max_pixels_per_frame = 4096 * 4096,
186 .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1,
189 .max_pixels_per_frame = 4096 * 4096,
193 .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC,
196 .max_pixels_per_frame = 8192 * 4352,
200 .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG,
203 .max_pixels_per_frame = 4096 * 4096,
207 .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9,
210 .max_pixels_per_frame = 8192 * 4352,
214 .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1,
217 .max_pixels_per_frame = 8192 * 4352,
222 static const struct amdgpu_video_codecs sc_video_codecs_decode =
224 .codec_count = ARRAY_SIZE(sc_video_codecs_decode_array),
225 .codec_array = sc_video_codecs_decode_array,
228 /* SRIOV Sienna Cichlid, not const since data is controlled by host */
229 static struct amdgpu_video_codec_info sriov_sc_video_codecs_encode_array[] =
232 .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC,
235 .max_pixels_per_frame = 4096 * 2304,
239 .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC,
242 .max_pixels_per_frame = 4096 * 2304,
247 static struct amdgpu_video_codec_info sriov_sc_video_codecs_decode_array[] =
250 .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2,
253 .max_pixels_per_frame = 4096 * 4096,
257 .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4,
260 .max_pixels_per_frame = 4096 * 4096,
264 .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC,
267 .max_pixels_per_frame = 4096 * 4096,
271 .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1,
274 .max_pixels_per_frame = 4096 * 4096,
278 .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC,
281 .max_pixels_per_frame = 8192 * 4352,
285 .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG,
288 .max_pixels_per_frame = 4096 * 4096,
292 .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9,
295 .max_pixels_per_frame = 8192 * 4352,
299 .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1,
302 .max_pixels_per_frame = 8192 * 4352,
307 static struct amdgpu_video_codecs sriov_sc_video_codecs_encode =
309 .codec_count = ARRAY_SIZE(sriov_sc_video_codecs_encode_array),
310 .codec_array = sriov_sc_video_codecs_encode_array,
313 static struct amdgpu_video_codecs sriov_sc_video_codecs_decode =
315 .codec_count = ARRAY_SIZE(sriov_sc_video_codecs_decode_array),
316 .codec_array = sriov_sc_video_codecs_decode_array,
320 static const struct amdgpu_video_codec_info bg_video_codecs_decode_array[] = {
321 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4906, 52)},
322 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)},
323 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)},
326 static const struct amdgpu_video_codecs bg_video_codecs_decode = {
327 .codec_count = ARRAY_SIZE(bg_video_codecs_decode_array),
328 .codec_array = bg_video_codecs_decode_array,
331 static const struct amdgpu_video_codecs bg_video_codecs_encode = {
336 static int nv_query_video_codecs(struct amdgpu_device *adev, bool encode,
337 const struct amdgpu_video_codecs **codecs)
339 switch (adev->asic_type) {
340 case CHIP_SIENNA_CICHLID:
341 if (amdgpu_sriov_vf(adev)) {
343 *codecs = &sriov_sc_video_codecs_encode;
345 *codecs = &sriov_sc_video_codecs_decode;
348 *codecs = &nv_video_codecs_encode;
350 *codecs = &sc_video_codecs_decode;
353 case CHIP_NAVY_FLOUNDER:
354 case CHIP_DIMGREY_CAVEFISH:
356 case CHIP_YELLOW_CARP:
358 *codecs = &nv_video_codecs_encode;
360 *codecs = &sc_video_codecs_decode;
362 case CHIP_BEIGE_GOBY:
364 *codecs = &bg_video_codecs_encode;
366 *codecs = &bg_video_codecs_decode;
372 *codecs = &nv_video_codecs_encode;
374 *codecs = &nv_video_codecs_decode;
382 * Indirect registers accessor
384 static u32 nv_pcie_rreg(struct amdgpu_device *adev, u32 reg)
386 unsigned long address, data;
387 address = adev->nbio.funcs->get_pcie_index_offset(adev);
388 data = adev->nbio.funcs->get_pcie_data_offset(adev);
390 return amdgpu_device_indirect_rreg(adev, address, data, reg);
393 static void nv_pcie_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
395 unsigned long address, data;
397 address = adev->nbio.funcs->get_pcie_index_offset(adev);
398 data = adev->nbio.funcs->get_pcie_data_offset(adev);
400 amdgpu_device_indirect_wreg(adev, address, data, reg, v);
403 static u64 nv_pcie_rreg64(struct amdgpu_device *adev, u32 reg)
405 unsigned long address, data;
406 address = adev->nbio.funcs->get_pcie_index_offset(adev);
407 data = adev->nbio.funcs->get_pcie_data_offset(adev);
409 return amdgpu_device_indirect_rreg64(adev, address, data, reg);
412 static u32 nv_pcie_port_rreg(struct amdgpu_device *adev, u32 reg)
414 unsigned long flags, address, data;
416 address = adev->nbio.funcs->get_pcie_port_index_offset(adev);
417 data = adev->nbio.funcs->get_pcie_port_data_offset(adev);
419 spin_lock_irqsave(&adev->pcie_idx_lock, flags);
420 WREG32(address, reg * 4);
421 (void)RREG32(address);
423 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
427 static void nv_pcie_wreg64(struct amdgpu_device *adev, u32 reg, u64 v)
429 unsigned long address, data;
431 address = adev->nbio.funcs->get_pcie_index_offset(adev);
432 data = adev->nbio.funcs->get_pcie_data_offset(adev);
434 amdgpu_device_indirect_wreg64(adev, address, data, reg, v);
437 static void nv_pcie_port_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
439 unsigned long flags, address, data;
441 address = adev->nbio.funcs->get_pcie_port_index_offset(adev);
442 data = adev->nbio.funcs->get_pcie_port_data_offset(adev);
444 spin_lock_irqsave(&adev->pcie_idx_lock, flags);
445 WREG32(address, reg * 4);
446 (void)RREG32(address);
449 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
452 static u32 nv_didt_rreg(struct amdgpu_device *adev, u32 reg)
454 unsigned long flags, address, data;
457 address = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_INDEX);
458 data = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_DATA);
460 spin_lock_irqsave(&adev->didt_idx_lock, flags);
461 WREG32(address, (reg));
463 spin_unlock_irqrestore(&adev->didt_idx_lock, flags);
467 static void nv_didt_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
469 unsigned long flags, address, data;
471 address = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_INDEX);
472 data = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_DATA);
474 spin_lock_irqsave(&adev->didt_idx_lock, flags);
475 WREG32(address, (reg));
477 spin_unlock_irqrestore(&adev->didt_idx_lock, flags);
480 static u32 nv_get_config_memsize(struct amdgpu_device *adev)
482 return adev->nbio.funcs->get_memsize(adev);
485 static u32 nv_get_xclk(struct amdgpu_device *adev)
487 return adev->clock.spll.reference_freq;
491 void nv_grbm_select(struct amdgpu_device *adev,
492 u32 me, u32 pipe, u32 queue, u32 vmid)
494 u32 grbm_gfx_cntl = 0;
495 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, PIPEID, pipe);
496 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, MEID, me);
497 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, VMID, vmid);
498 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, QUEUEID, queue);
500 WREG32_SOC15(GC, 0, mmGRBM_GFX_CNTL, grbm_gfx_cntl);
503 static void nv_vga_set_state(struct amdgpu_device *adev, bool state)
508 static bool nv_read_disabled_bios(struct amdgpu_device *adev)
514 static bool nv_read_bios_from_rom(struct amdgpu_device *adev,
515 u8 *bios, u32 length_bytes)
519 u32 rom_index_offset, rom_data_offset;
523 if (length_bytes == 0)
525 /* APU vbios image is part of sbios image */
526 if (adev->flags & AMD_IS_APU)
529 dw_ptr = (u32 *)bios;
530 length_dw = ALIGN(length_bytes, 4) / 4;
533 adev->smuio.funcs->get_rom_index_offset(adev);
535 adev->smuio.funcs->get_rom_data_offset(adev);
537 /* set rom index to 0 */
538 WREG32(rom_index_offset, 0);
539 /* read out the rom data */
540 for (i = 0; i < length_dw; i++)
541 dw_ptr[i] = RREG32(rom_data_offset);
546 static struct soc15_allowed_register_entry nv_allowed_read_registers[] = {
547 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS)},
548 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS2)},
549 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE0)},
550 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE1)},
551 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE2)},
552 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE3)},
553 { SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_STATUS_REG)},
554 { SOC15_REG_ENTRY(SDMA1, 0, mmSDMA1_STATUS_REG)},
555 { SOC15_REG_ENTRY(GC, 0, mmCP_STAT)},
556 { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT1)},
557 { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT2)},
558 { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT3)},
559 { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_BUSY_STAT)},
560 { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_STALLED_STAT1)},
561 { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_STATUS)},
562 { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_BUSY_STAT)},
563 { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_STALLED_STAT1)},
564 { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_STATUS)},
565 { SOC15_REG_ENTRY(GC, 0, mmGB_ADDR_CONFIG)},
568 static uint32_t nv_read_indexed_register(struct amdgpu_device *adev, u32 se_num,
569 u32 sh_num, u32 reg_offset)
573 mutex_lock(&adev->grbm_idx_mutex);
574 if (se_num != 0xffffffff || sh_num != 0xffffffff)
575 amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff);
577 val = RREG32(reg_offset);
579 if (se_num != 0xffffffff || sh_num != 0xffffffff)
580 amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
581 mutex_unlock(&adev->grbm_idx_mutex);
585 static uint32_t nv_get_register_value(struct amdgpu_device *adev,
586 bool indexed, u32 se_num,
587 u32 sh_num, u32 reg_offset)
590 return nv_read_indexed_register(adev, se_num, sh_num, reg_offset);
592 if (reg_offset == SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG))
593 return adev->gfx.config.gb_addr_config;
594 return RREG32(reg_offset);
598 static int nv_read_register(struct amdgpu_device *adev, u32 se_num,
599 u32 sh_num, u32 reg_offset, u32 *value)
602 struct soc15_allowed_register_entry *en;
605 for (i = 0; i < ARRAY_SIZE(nv_allowed_read_registers); i++) {
606 en = &nv_allowed_read_registers[i];
607 if ((i == 7 && (adev->sdma.num_instances == 1)) || /* some asics don't have SDMA1 */
609 (adev->reg_offset[en->hwip][en->inst][en->seg] + en->reg_offset))
612 *value = nv_get_register_value(adev,
613 nv_allowed_read_registers[i].grbm_indexed,
614 se_num, sh_num, reg_offset);
620 static int nv_asic_mode2_reset(struct amdgpu_device *adev)
625 amdgpu_atombios_scratch_regs_engine_hung(adev, true);
628 pci_clear_master(adev->pdev);
630 amdgpu_device_cache_pci_state(adev->pdev);
632 ret = amdgpu_dpm_mode2_reset(adev);
634 dev_err(adev->dev, "GPU mode2 reset failed\n");
636 amdgpu_device_load_pci_state(adev->pdev);
638 /* wait for asic to come out of reset */
639 for (i = 0; i < adev->usec_timeout; i++) {
640 u32 memsize = adev->nbio.funcs->get_memsize(adev);
642 if (memsize != 0xffffffff)
647 amdgpu_atombios_scratch_regs_engine_hung(adev, false);
652 static enum amd_reset_method
653 nv_asic_reset_method(struct amdgpu_device *adev)
655 if (amdgpu_reset_method == AMD_RESET_METHOD_MODE1 ||
656 amdgpu_reset_method == AMD_RESET_METHOD_MODE2 ||
657 amdgpu_reset_method == AMD_RESET_METHOD_BACO ||
658 amdgpu_reset_method == AMD_RESET_METHOD_PCI)
659 return amdgpu_reset_method;
661 if (amdgpu_reset_method != -1)
662 dev_warn(adev->dev, "Specified reset method:%d isn't supported, using AUTO instead.\n",
663 amdgpu_reset_method);
665 switch (adev->asic_type) {
667 case CHIP_YELLOW_CARP:
668 return AMD_RESET_METHOD_MODE2;
669 case CHIP_SIENNA_CICHLID:
670 case CHIP_NAVY_FLOUNDER:
671 case CHIP_DIMGREY_CAVEFISH:
672 case CHIP_BEIGE_GOBY:
673 return AMD_RESET_METHOD_MODE1;
675 if (amdgpu_dpm_is_baco_supported(adev))
676 return AMD_RESET_METHOD_BACO;
678 return AMD_RESET_METHOD_MODE1;
682 static int nv_asic_reset(struct amdgpu_device *adev)
686 switch (nv_asic_reset_method(adev)) {
687 case AMD_RESET_METHOD_PCI:
688 dev_info(adev->dev, "PCI reset\n");
689 ret = amdgpu_device_pci_reset(adev);
691 case AMD_RESET_METHOD_BACO:
692 dev_info(adev->dev, "BACO reset\n");
693 ret = amdgpu_dpm_baco_reset(adev);
695 case AMD_RESET_METHOD_MODE2:
696 dev_info(adev->dev, "MODE2 reset\n");
697 ret = nv_asic_mode2_reset(adev);
700 dev_info(adev->dev, "MODE1 reset\n");
701 ret = amdgpu_device_mode1_reset(adev);
708 static int nv_set_uvd_clocks(struct amdgpu_device *adev, u32 vclk, u32 dclk)
714 static int nv_set_vce_clocks(struct amdgpu_device *adev, u32 evclk, u32 ecclk)
720 static void nv_pcie_gen3_enable(struct amdgpu_device *adev)
722 if (pci_is_root_bus(adev->pdev->bus))
725 if (amdgpu_pcie_gen2 == 0)
728 if (!(adev->pm.pcie_gen_mask & (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 |
729 CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3)))
735 static void nv_program_aspm(struct amdgpu_device *adev)
740 if (!(adev->flags & AMD_IS_APU) &&
741 (adev->nbio.funcs->program_aspm))
742 adev->nbio.funcs->program_aspm(adev);
746 static void nv_enable_doorbell_aperture(struct amdgpu_device *adev,
749 adev->nbio.funcs->enable_doorbell_aperture(adev, enable);
750 adev->nbio.funcs->enable_doorbell_selfring_aperture(adev, enable);
753 static const struct amdgpu_ip_block_version nv_common_ip_block =
755 .type = AMD_IP_BLOCK_TYPE_COMMON,
759 .funcs = &nv_common_ip_funcs,
762 static bool nv_is_headless_sku(struct pci_dev *pdev)
764 if ((pdev->device == 0x731E &&
765 (pdev->revision == 0xC6 || pdev->revision == 0xC7)) ||
766 (pdev->device == 0x7340 && pdev->revision == 0xC9) ||
767 (pdev->device == 0x7360 && pdev->revision == 0xC7))
772 static int nv_reg_base_init(struct amdgpu_device *adev)
776 if (amdgpu_discovery) {
777 r = amdgpu_discovery_reg_base_init(adev);
779 DRM_WARN("failed to init reg base from ip discovery table, "
780 "fallback to legacy init method\n");
784 amdgpu_discovery_harvest_ip(adev);
785 if (nv_is_headless_sku(adev->pdev)) {
786 adev->harvest_ip_mask |= AMD_HARVEST_IP_VCN_MASK;
787 adev->harvest_ip_mask |= AMD_HARVEST_IP_JPEG_MASK;
794 switch (adev->asic_type) {
796 navi10_reg_base_init(adev);
799 navi14_reg_base_init(adev);
802 navi12_reg_base_init(adev);
804 case CHIP_SIENNA_CICHLID:
805 case CHIP_NAVY_FLOUNDER:
806 sienna_cichlid_reg_base_init(adev);
809 vangogh_reg_base_init(adev);
811 case CHIP_DIMGREY_CAVEFISH:
812 dimgrey_cavefish_reg_base_init(adev);
814 case CHIP_BEIGE_GOBY:
815 beige_goby_reg_base_init(adev);
817 case CHIP_YELLOW_CARP:
818 yellow_carp_reg_base_init(adev);
827 void nv_set_virt_ops(struct amdgpu_device *adev)
829 adev->virt.ops = &xgpu_nv_virt_ops;
832 int nv_set_ip_blocks(struct amdgpu_device *adev)
836 if (adev->flags & AMD_IS_APU) {
837 adev->nbio.funcs = &nbio_v7_2_funcs;
838 adev->nbio.hdp_flush_reg = &nbio_v7_2_hdp_flush_reg;
840 adev->nbio.funcs = &nbio_v2_3_funcs;
841 adev->nbio.hdp_flush_reg = &nbio_v2_3_hdp_flush_reg;
843 adev->hdp.funcs = &hdp_v5_0_funcs;
845 if (adev->asic_type >= CHIP_SIENNA_CICHLID)
846 adev->smuio.funcs = &smuio_v11_0_6_funcs;
848 adev->smuio.funcs = &smuio_v11_0_funcs;
850 if (adev->asic_type == CHIP_SIENNA_CICHLID)
851 adev->gmc.xgmi.supported = true;
853 /* Set IP register base before any HW register access */
854 r = nv_reg_base_init(adev);
858 switch (adev->asic_type) {
861 amdgpu_device_ip_block_add(adev, &nv_common_ip_block);
862 amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block);
863 amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block);
864 amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block);
865 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP &&
866 !amdgpu_sriov_vf(adev))
867 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);
868 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))
869 amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
870 #if defined(CONFIG_DRM_AMD_DC)
871 else if (amdgpu_device_has_dc_support(adev))
872 amdgpu_device_ip_block_add(adev, &dm_ip_block);
874 amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block);
875 amdgpu_device_ip_block_add(adev, &sdma_v5_0_ip_block);
876 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT &&
877 !amdgpu_sriov_vf(adev))
878 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);
879 amdgpu_device_ip_block_add(adev, &vcn_v2_0_ip_block);
880 amdgpu_device_ip_block_add(adev, &jpeg_v2_0_ip_block);
881 if (adev->enable_mes)
882 amdgpu_device_ip_block_add(adev, &mes_v10_1_ip_block);
885 amdgpu_device_ip_block_add(adev, &nv_common_ip_block);
886 amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block);
887 if (!amdgpu_sriov_vf(adev)) {
888 amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block);
889 amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block);
891 amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block);
892 amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block);
894 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)
895 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);
896 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))
897 amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
898 #if defined(CONFIG_DRM_AMD_DC)
899 else if (amdgpu_device_has_dc_support(adev))
900 amdgpu_device_ip_block_add(adev, &dm_ip_block);
902 amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block);
903 amdgpu_device_ip_block_add(adev, &sdma_v5_0_ip_block);
904 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT &&
905 !amdgpu_sriov_vf(adev))
906 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);
907 amdgpu_device_ip_block_add(adev, &vcn_v2_0_ip_block);
908 if (!amdgpu_sriov_vf(adev))
909 amdgpu_device_ip_block_add(adev, &jpeg_v2_0_ip_block);
911 case CHIP_SIENNA_CICHLID:
912 amdgpu_device_ip_block_add(adev, &nv_common_ip_block);
913 amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block);
914 if (!amdgpu_sriov_vf(adev)) {
915 amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block);
916 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP))
917 amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block);
919 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP))
920 amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block);
921 amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block);
923 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP &&
924 is_support_sw_smu(adev))
925 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);
926 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))
927 amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
928 #if defined(CONFIG_DRM_AMD_DC)
929 else if (amdgpu_device_has_dc_support(adev))
930 amdgpu_device_ip_block_add(adev, &dm_ip_block);
932 amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block);
933 amdgpu_device_ip_block_add(adev, &sdma_v5_2_ip_block);
934 amdgpu_device_ip_block_add(adev, &vcn_v3_0_ip_block);
935 if (!amdgpu_sriov_vf(adev))
936 amdgpu_device_ip_block_add(adev, &jpeg_v3_0_ip_block);
937 if (adev->enable_mes)
938 amdgpu_device_ip_block_add(adev, &mes_v10_1_ip_block);
940 case CHIP_NAVY_FLOUNDER:
941 amdgpu_device_ip_block_add(adev, &nv_common_ip_block);
942 amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block);
943 amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block);
944 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP))
945 amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block);
946 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP &&
947 is_support_sw_smu(adev))
948 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);
949 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))
950 amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
951 #if defined(CONFIG_DRM_AMD_DC)
952 else if (amdgpu_device_has_dc_support(adev))
953 amdgpu_device_ip_block_add(adev, &dm_ip_block);
955 amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block);
956 amdgpu_device_ip_block_add(adev, &sdma_v5_2_ip_block);
957 amdgpu_device_ip_block_add(adev, &vcn_v3_0_ip_block);
958 amdgpu_device_ip_block_add(adev, &jpeg_v3_0_ip_block);
959 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT &&
960 is_support_sw_smu(adev))
961 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);
964 amdgpu_device_ip_block_add(adev, &nv_common_ip_block);
965 amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block);
966 amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block);
967 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP))
968 amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block);
969 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);
970 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))
971 amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
972 #if defined(CONFIG_DRM_AMD_DC)
973 else if (amdgpu_device_has_dc_support(adev))
974 amdgpu_device_ip_block_add(adev, &dm_ip_block);
976 amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block);
977 amdgpu_device_ip_block_add(adev, &sdma_v5_2_ip_block);
978 amdgpu_device_ip_block_add(adev, &vcn_v3_0_ip_block);
979 amdgpu_device_ip_block_add(adev, &jpeg_v3_0_ip_block);
981 case CHIP_DIMGREY_CAVEFISH:
982 amdgpu_device_ip_block_add(adev, &nv_common_ip_block);
983 amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block);
984 amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block);
985 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP))
986 amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block);
987 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP &&
988 is_support_sw_smu(adev))
989 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);
990 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))
991 amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
992 #if defined(CONFIG_DRM_AMD_DC)
993 else if (amdgpu_device_has_dc_support(adev))
994 amdgpu_device_ip_block_add(adev, &dm_ip_block);
996 amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block);
997 amdgpu_device_ip_block_add(adev, &sdma_v5_2_ip_block);
998 amdgpu_device_ip_block_add(adev, &vcn_v3_0_ip_block);
999 amdgpu_device_ip_block_add(adev, &jpeg_v3_0_ip_block);
1001 case CHIP_BEIGE_GOBY:
1002 amdgpu_device_ip_block_add(adev, &nv_common_ip_block);
1003 amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block);
1004 amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block);
1005 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP))
1006 amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block);
1007 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP &&
1008 is_support_sw_smu(adev))
1009 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);
1010 amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block);
1011 amdgpu_device_ip_block_add(adev, &sdma_v5_2_ip_block);
1012 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))
1013 amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
1014 #if defined(CONFIG_DRM_AMD_DC)
1015 else if (amdgpu_device_has_dc_support(adev))
1016 amdgpu_device_ip_block_add(adev, &dm_ip_block);
1018 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT &&
1019 is_support_sw_smu(adev))
1020 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);
1021 amdgpu_device_ip_block_add(adev, &vcn_v3_0_ip_block);
1023 case CHIP_YELLOW_CARP:
1024 amdgpu_device_ip_block_add(adev, &nv_common_ip_block);
1025 amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block);
1026 amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block);
1027 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP))
1028 amdgpu_device_ip_block_add(adev, &psp_v13_0_ip_block);
1029 amdgpu_device_ip_block_add(adev, &smu_v13_0_ip_block);
1030 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))
1031 amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
1032 amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block);
1033 amdgpu_device_ip_block_add(adev, &sdma_v5_2_ip_block);
1034 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))
1035 amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
1036 #if defined(CONFIG_DRM_AMD_DC)
1037 else if (amdgpu_device_has_dc_support(adev))
1038 amdgpu_device_ip_block_add(adev, &dm_ip_block);
1040 amdgpu_device_ip_block_add(adev, &vcn_v3_0_ip_block);
1041 amdgpu_device_ip_block_add(adev, &jpeg_v3_0_ip_block);
1050 static uint32_t nv_get_rev_id(struct amdgpu_device *adev)
1052 return adev->nbio.funcs->get_rev_id(adev);
1055 static bool nv_need_full_reset(struct amdgpu_device *adev)
1060 static bool nv_need_reset_on_init(struct amdgpu_device *adev)
1064 if (adev->flags & AMD_IS_APU)
1067 /* Check sOS sign of life register to confirm sys driver and sOS
1068 * are already been loaded.
1070 sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81);
1077 static uint64_t nv_get_pcie_replay_count(struct amdgpu_device *adev)
1081 * dummy implement for pcie_replay_count sysfs interface
1087 static void nv_init_doorbell_index(struct amdgpu_device *adev)
1089 adev->doorbell_index.kiq = AMDGPU_NAVI10_DOORBELL_KIQ;
1090 adev->doorbell_index.mec_ring0 = AMDGPU_NAVI10_DOORBELL_MEC_RING0;
1091 adev->doorbell_index.mec_ring1 = AMDGPU_NAVI10_DOORBELL_MEC_RING1;
1092 adev->doorbell_index.mec_ring2 = AMDGPU_NAVI10_DOORBELL_MEC_RING2;
1093 adev->doorbell_index.mec_ring3 = AMDGPU_NAVI10_DOORBELL_MEC_RING3;
1094 adev->doorbell_index.mec_ring4 = AMDGPU_NAVI10_DOORBELL_MEC_RING4;
1095 adev->doorbell_index.mec_ring5 = AMDGPU_NAVI10_DOORBELL_MEC_RING5;
1096 adev->doorbell_index.mec_ring6 = AMDGPU_NAVI10_DOORBELL_MEC_RING6;
1097 adev->doorbell_index.mec_ring7 = AMDGPU_NAVI10_DOORBELL_MEC_RING7;
1098 adev->doorbell_index.userqueue_start = AMDGPU_NAVI10_DOORBELL_USERQUEUE_START;
1099 adev->doorbell_index.userqueue_end = AMDGPU_NAVI10_DOORBELL_USERQUEUE_END;
1100 adev->doorbell_index.gfx_ring0 = AMDGPU_NAVI10_DOORBELL_GFX_RING0;
1101 adev->doorbell_index.gfx_ring1 = AMDGPU_NAVI10_DOORBELL_GFX_RING1;
1102 adev->doorbell_index.mes_ring = AMDGPU_NAVI10_DOORBELL_MES_RING;
1103 adev->doorbell_index.sdma_engine[0] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE0;
1104 adev->doorbell_index.sdma_engine[1] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE1;
1105 adev->doorbell_index.sdma_engine[2] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE2;
1106 adev->doorbell_index.sdma_engine[3] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE3;
1107 adev->doorbell_index.ih = AMDGPU_NAVI10_DOORBELL_IH;
1108 adev->doorbell_index.vcn.vcn_ring0_1 = AMDGPU_NAVI10_DOORBELL64_VCN0_1;
1109 adev->doorbell_index.vcn.vcn_ring2_3 = AMDGPU_NAVI10_DOORBELL64_VCN2_3;
1110 adev->doorbell_index.vcn.vcn_ring4_5 = AMDGPU_NAVI10_DOORBELL64_VCN4_5;
1111 adev->doorbell_index.vcn.vcn_ring6_7 = AMDGPU_NAVI10_DOORBELL64_VCN6_7;
1112 adev->doorbell_index.first_non_cp = AMDGPU_NAVI10_DOORBELL64_FIRST_NON_CP;
1113 adev->doorbell_index.last_non_cp = AMDGPU_NAVI10_DOORBELL64_LAST_NON_CP;
1115 adev->doorbell_index.max_assignment = AMDGPU_NAVI10_DOORBELL_MAX_ASSIGNMENT << 1;
1116 adev->doorbell_index.sdma_doorbell_range = 20;
1119 static void nv_pre_asic_init(struct amdgpu_device *adev)
1123 static int nv_update_umd_stable_pstate(struct amdgpu_device *adev,
1127 amdgpu_gfx_rlc_enter_safe_mode(adev);
1129 amdgpu_gfx_rlc_exit_safe_mode(adev);
1131 if (adev->gfx.funcs->update_perfmon_mgcg)
1132 adev->gfx.funcs->update_perfmon_mgcg(adev, !enter);
1134 if (!(adev->flags & AMD_IS_APU) &&
1135 (adev->nbio.funcs->enable_aspm))
1136 adev->nbio.funcs->enable_aspm(adev, !enter);
1141 static const struct amdgpu_asic_funcs nv_asic_funcs =
1143 .read_disabled_bios = &nv_read_disabled_bios,
1144 .read_bios_from_rom = &nv_read_bios_from_rom,
1145 .read_register = &nv_read_register,
1146 .reset = &nv_asic_reset,
1147 .reset_method = &nv_asic_reset_method,
1148 .set_vga_state = &nv_vga_set_state,
1149 .get_xclk = &nv_get_xclk,
1150 .set_uvd_clocks = &nv_set_uvd_clocks,
1151 .set_vce_clocks = &nv_set_vce_clocks,
1152 .get_config_memsize = &nv_get_config_memsize,
1153 .init_doorbell_index = &nv_init_doorbell_index,
1154 .need_full_reset = &nv_need_full_reset,
1155 .need_reset_on_init = &nv_need_reset_on_init,
1156 .get_pcie_replay_count = &nv_get_pcie_replay_count,
1157 .supports_baco = &amdgpu_dpm_is_baco_supported,
1158 .pre_asic_init = &nv_pre_asic_init,
1159 .update_umd_stable_pstate = &nv_update_umd_stable_pstate,
1160 .query_video_codecs = &nv_query_video_codecs,
1163 static int nv_common_early_init(void *handle)
1165 #define MMIO_REG_HOLE_OFFSET (0x80000 - PAGE_SIZE)
1166 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1168 adev->rmmio_remap.reg_offset = MMIO_REG_HOLE_OFFSET;
1169 adev->rmmio_remap.bus_addr = adev->rmmio_base + MMIO_REG_HOLE_OFFSET;
1170 adev->smc_rreg = NULL;
1171 adev->smc_wreg = NULL;
1172 adev->pcie_rreg = &nv_pcie_rreg;
1173 adev->pcie_wreg = &nv_pcie_wreg;
1174 adev->pcie_rreg64 = &nv_pcie_rreg64;
1175 adev->pcie_wreg64 = &nv_pcie_wreg64;
1176 adev->pciep_rreg = &nv_pcie_port_rreg;
1177 adev->pciep_wreg = &nv_pcie_port_wreg;
1179 /* TODO: will add them during VCN v2 implementation */
1180 adev->uvd_ctx_rreg = NULL;
1181 adev->uvd_ctx_wreg = NULL;
1183 adev->didt_rreg = &nv_didt_rreg;
1184 adev->didt_wreg = &nv_didt_wreg;
1186 adev->asic_funcs = &nv_asic_funcs;
1188 adev->rev_id = nv_get_rev_id(adev);
1189 adev->external_rev_id = 0xff;
1190 switch (adev->asic_type) {
1192 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
1193 AMD_CG_SUPPORT_GFX_CGCG |
1194 AMD_CG_SUPPORT_IH_CG |
1195 AMD_CG_SUPPORT_HDP_MGCG |
1196 AMD_CG_SUPPORT_HDP_LS |
1197 AMD_CG_SUPPORT_SDMA_MGCG |
1198 AMD_CG_SUPPORT_SDMA_LS |
1199 AMD_CG_SUPPORT_MC_MGCG |
1200 AMD_CG_SUPPORT_MC_LS |
1201 AMD_CG_SUPPORT_ATHUB_MGCG |
1202 AMD_CG_SUPPORT_ATHUB_LS |
1203 AMD_CG_SUPPORT_VCN_MGCG |
1204 AMD_CG_SUPPORT_JPEG_MGCG |
1205 AMD_CG_SUPPORT_BIF_MGCG |
1206 AMD_CG_SUPPORT_BIF_LS;
1207 adev->pg_flags = AMD_PG_SUPPORT_VCN |
1208 AMD_PG_SUPPORT_VCN_DPG |
1209 AMD_PG_SUPPORT_JPEG |
1210 AMD_PG_SUPPORT_ATHUB;
1211 adev->external_rev_id = adev->rev_id + 0x1;
1214 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
1215 AMD_CG_SUPPORT_GFX_CGCG |
1216 AMD_CG_SUPPORT_IH_CG |
1217 AMD_CG_SUPPORT_HDP_MGCG |
1218 AMD_CG_SUPPORT_HDP_LS |
1219 AMD_CG_SUPPORT_SDMA_MGCG |
1220 AMD_CG_SUPPORT_SDMA_LS |
1221 AMD_CG_SUPPORT_MC_MGCG |
1222 AMD_CG_SUPPORT_MC_LS |
1223 AMD_CG_SUPPORT_ATHUB_MGCG |
1224 AMD_CG_SUPPORT_ATHUB_LS |
1225 AMD_CG_SUPPORT_VCN_MGCG |
1226 AMD_CG_SUPPORT_JPEG_MGCG |
1227 AMD_CG_SUPPORT_BIF_MGCG |
1228 AMD_CG_SUPPORT_BIF_LS;
1229 adev->pg_flags = AMD_PG_SUPPORT_VCN |
1230 AMD_PG_SUPPORT_JPEG |
1231 AMD_PG_SUPPORT_VCN_DPG;
1232 adev->external_rev_id = adev->rev_id + 20;
1235 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
1236 AMD_CG_SUPPORT_GFX_MGLS |
1237 AMD_CG_SUPPORT_GFX_CGCG |
1238 AMD_CG_SUPPORT_GFX_CP_LS |
1239 AMD_CG_SUPPORT_GFX_RLC_LS |
1240 AMD_CG_SUPPORT_IH_CG |
1241 AMD_CG_SUPPORT_HDP_MGCG |
1242 AMD_CG_SUPPORT_HDP_LS |
1243 AMD_CG_SUPPORT_SDMA_MGCG |
1244 AMD_CG_SUPPORT_SDMA_LS |
1245 AMD_CG_SUPPORT_MC_MGCG |
1246 AMD_CG_SUPPORT_MC_LS |
1247 AMD_CG_SUPPORT_ATHUB_MGCG |
1248 AMD_CG_SUPPORT_ATHUB_LS |
1249 AMD_CG_SUPPORT_VCN_MGCG |
1250 AMD_CG_SUPPORT_JPEG_MGCG;
1251 adev->pg_flags = AMD_PG_SUPPORT_VCN |
1252 AMD_PG_SUPPORT_VCN_DPG |
1253 AMD_PG_SUPPORT_JPEG |
1254 AMD_PG_SUPPORT_ATHUB;
1255 /* guest vm gets 0xffffffff when reading RCC_DEV0_EPF0_STRAP0,
1256 * as a consequence, the rev_id and external_rev_id are wrong.
1257 * workaround it by hardcoding rev_id to 0 (default value).
1259 if (amdgpu_sriov_vf(adev))
1261 adev->external_rev_id = adev->rev_id + 0xa;
1263 case CHIP_SIENNA_CICHLID:
1264 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
1265 AMD_CG_SUPPORT_GFX_CGCG |
1266 AMD_CG_SUPPORT_GFX_CGLS |
1267 AMD_CG_SUPPORT_GFX_3D_CGCG |
1268 AMD_CG_SUPPORT_MC_MGCG |
1269 AMD_CG_SUPPORT_VCN_MGCG |
1270 AMD_CG_SUPPORT_JPEG_MGCG |
1271 AMD_CG_SUPPORT_HDP_MGCG |
1272 AMD_CG_SUPPORT_HDP_LS |
1273 AMD_CG_SUPPORT_IH_CG |
1274 AMD_CG_SUPPORT_MC_LS;
1275 adev->pg_flags = AMD_PG_SUPPORT_VCN |
1276 AMD_PG_SUPPORT_VCN_DPG |
1277 AMD_PG_SUPPORT_JPEG |
1278 AMD_PG_SUPPORT_ATHUB |
1279 AMD_PG_SUPPORT_MMHUB;
1280 if (amdgpu_sriov_vf(adev)) {
1281 /* hypervisor control CG and PG enablement */
1285 adev->external_rev_id = adev->rev_id + 0x28;
1287 case CHIP_NAVY_FLOUNDER:
1288 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
1289 AMD_CG_SUPPORT_GFX_CGCG |
1290 AMD_CG_SUPPORT_GFX_CGLS |
1291 AMD_CG_SUPPORT_GFX_3D_CGCG |
1292 AMD_CG_SUPPORT_VCN_MGCG |
1293 AMD_CG_SUPPORT_JPEG_MGCG |
1294 AMD_CG_SUPPORT_MC_MGCG |
1295 AMD_CG_SUPPORT_MC_LS |
1296 AMD_CG_SUPPORT_HDP_MGCG |
1297 AMD_CG_SUPPORT_HDP_LS |
1298 AMD_CG_SUPPORT_IH_CG;
1299 adev->pg_flags = AMD_PG_SUPPORT_VCN |
1300 AMD_PG_SUPPORT_VCN_DPG |
1301 AMD_PG_SUPPORT_JPEG |
1302 AMD_PG_SUPPORT_ATHUB |
1303 AMD_PG_SUPPORT_MMHUB;
1304 adev->external_rev_id = adev->rev_id + 0x32;
1308 adev->apu_flags |= AMD_APU_IS_VANGOGH;
1309 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
1310 AMD_CG_SUPPORT_GFX_MGLS |
1311 AMD_CG_SUPPORT_GFX_CP_LS |
1312 AMD_CG_SUPPORT_GFX_RLC_LS |
1313 AMD_CG_SUPPORT_GFX_CGCG |
1314 AMD_CG_SUPPORT_GFX_CGLS |
1315 AMD_CG_SUPPORT_GFX_3D_CGCG |
1316 AMD_CG_SUPPORT_GFX_3D_CGLS |
1317 AMD_CG_SUPPORT_MC_MGCG |
1318 AMD_CG_SUPPORT_MC_LS |
1319 AMD_CG_SUPPORT_GFX_FGCG |
1320 AMD_CG_SUPPORT_VCN_MGCG |
1321 AMD_CG_SUPPORT_SDMA_MGCG |
1322 AMD_CG_SUPPORT_SDMA_LS |
1323 AMD_CG_SUPPORT_JPEG_MGCG;
1324 adev->pg_flags = AMD_PG_SUPPORT_GFX_PG |
1325 AMD_PG_SUPPORT_VCN |
1326 AMD_PG_SUPPORT_VCN_DPG |
1327 AMD_PG_SUPPORT_JPEG;
1328 if (adev->apu_flags & AMD_APU_IS_VANGOGH)
1329 adev->external_rev_id = adev->rev_id + 0x01;
1331 case CHIP_DIMGREY_CAVEFISH:
1332 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
1333 AMD_CG_SUPPORT_GFX_CGCG |
1334 AMD_CG_SUPPORT_GFX_CGLS |
1335 AMD_CG_SUPPORT_GFX_3D_CGCG |
1336 AMD_CG_SUPPORT_VCN_MGCG |
1337 AMD_CG_SUPPORT_JPEG_MGCG |
1338 AMD_CG_SUPPORT_MC_MGCG |
1339 AMD_CG_SUPPORT_MC_LS |
1340 AMD_CG_SUPPORT_HDP_MGCG |
1341 AMD_CG_SUPPORT_HDP_LS |
1342 AMD_CG_SUPPORT_IH_CG;
1343 adev->pg_flags = AMD_PG_SUPPORT_VCN |
1344 AMD_PG_SUPPORT_VCN_DPG |
1345 AMD_PG_SUPPORT_JPEG |
1346 AMD_PG_SUPPORT_ATHUB |
1347 AMD_PG_SUPPORT_MMHUB;
1348 adev->external_rev_id = adev->rev_id + 0x3c;
1350 case CHIP_BEIGE_GOBY:
1351 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
1352 AMD_CG_SUPPORT_GFX_CGCG |
1353 AMD_CG_SUPPORT_GFX_CGLS |
1354 AMD_CG_SUPPORT_GFX_3D_CGCG |
1355 AMD_CG_SUPPORT_MC_MGCG |
1356 AMD_CG_SUPPORT_MC_LS |
1357 AMD_CG_SUPPORT_HDP_MGCG |
1358 AMD_CG_SUPPORT_HDP_LS |
1359 AMD_CG_SUPPORT_IH_CG |
1360 AMD_CG_SUPPORT_VCN_MGCG;
1361 adev->pg_flags = AMD_PG_SUPPORT_VCN |
1362 AMD_PG_SUPPORT_VCN_DPG |
1363 AMD_PG_SUPPORT_ATHUB |
1364 AMD_PG_SUPPORT_MMHUB;
1365 adev->external_rev_id = adev->rev_id + 0x46;
1367 case CHIP_YELLOW_CARP:
1368 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
1369 AMD_CG_SUPPORT_GFX_MGLS |
1370 AMD_CG_SUPPORT_GFX_CGCG |
1371 AMD_CG_SUPPORT_GFX_CGLS |
1372 AMD_CG_SUPPORT_GFX_3D_CGCG |
1373 AMD_CG_SUPPORT_GFX_3D_CGLS |
1374 AMD_CG_SUPPORT_GFX_RLC_LS |
1375 AMD_CG_SUPPORT_GFX_CP_LS |
1376 AMD_CG_SUPPORT_GFX_FGCG |
1377 AMD_CG_SUPPORT_MC_MGCG |
1378 AMD_CG_SUPPORT_MC_LS |
1379 AMD_CG_SUPPORT_SDMA_LS |
1380 AMD_CG_SUPPORT_HDP_MGCG |
1381 AMD_CG_SUPPORT_HDP_LS |
1382 AMD_CG_SUPPORT_ATHUB_MGCG |
1383 AMD_CG_SUPPORT_ATHUB_LS |
1384 AMD_CG_SUPPORT_IH_CG |
1385 AMD_CG_SUPPORT_VCN_MGCG |
1386 AMD_CG_SUPPORT_JPEG_MGCG;
1387 adev->pg_flags = AMD_PG_SUPPORT_GFX_PG |
1388 AMD_PG_SUPPORT_VCN |
1389 AMD_PG_SUPPORT_VCN_DPG |
1390 AMD_PG_SUPPORT_JPEG;
1391 adev->external_rev_id = adev->rev_id + 0x01;
1394 /* FIXME: not supported yet */
1398 if (adev->harvest_ip_mask & AMD_HARVEST_IP_VCN_MASK)
1399 adev->pg_flags &= ~(AMD_PG_SUPPORT_VCN |
1400 AMD_PG_SUPPORT_VCN_DPG |
1401 AMD_PG_SUPPORT_JPEG);
1403 if (amdgpu_sriov_vf(adev)) {
1404 amdgpu_virt_init_setting(adev);
1405 xgpu_nv_mailbox_set_irq_funcs(adev);
1411 static int nv_common_late_init(void *handle)
1413 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1415 if (amdgpu_sriov_vf(adev)) {
1416 xgpu_nv_mailbox_get_irq(adev);
1417 amdgpu_virt_update_sriov_video_codec(adev,
1418 sriov_sc_video_codecs_encode_array, ARRAY_SIZE(sriov_sc_video_codecs_encode_array),
1419 sriov_sc_video_codecs_decode_array, ARRAY_SIZE(sriov_sc_video_codecs_decode_array));
1425 static int nv_common_sw_init(void *handle)
1427 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1429 if (amdgpu_sriov_vf(adev))
1430 xgpu_nv_mailbox_add_irq_id(adev);
1435 static int nv_common_sw_fini(void *handle)
1440 static int nv_common_hw_init(void *handle)
1442 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1444 if (adev->nbio.funcs->apply_lc_spc_mode_wa)
1445 adev->nbio.funcs->apply_lc_spc_mode_wa(adev);
1447 if (adev->nbio.funcs->apply_l1_link_width_reconfig_wa)
1448 adev->nbio.funcs->apply_l1_link_width_reconfig_wa(adev);
1450 /* enable pcie gen2/3 link */
1451 nv_pcie_gen3_enable(adev);
1453 nv_program_aspm(adev);
1454 /* setup nbio registers */
1455 adev->nbio.funcs->init_registers(adev);
1456 /* remap HDP registers to a hole in mmio space,
1457 * for the purpose of expose those registers
1460 if (adev->nbio.funcs->remap_hdp_registers)
1461 adev->nbio.funcs->remap_hdp_registers(adev);
1462 /* enable the doorbell aperture */
1463 nv_enable_doorbell_aperture(adev, true);
1468 static int nv_common_hw_fini(void *handle)
1470 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1472 /* disable the doorbell aperture */
1473 nv_enable_doorbell_aperture(adev, false);
1478 static int nv_common_suspend(void *handle)
1480 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1482 return nv_common_hw_fini(adev);
1485 static int nv_common_resume(void *handle)
1487 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1489 return nv_common_hw_init(adev);
1492 static bool nv_common_is_idle(void *handle)
1497 static int nv_common_wait_for_idle(void *handle)
1502 static int nv_common_soft_reset(void *handle)
1507 static int nv_common_set_clockgating_state(void *handle,
1508 enum amd_clockgating_state state)
1510 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1512 if (amdgpu_sriov_vf(adev))
1515 switch (adev->asic_type) {
1519 case CHIP_SIENNA_CICHLID:
1520 case CHIP_NAVY_FLOUNDER:
1521 case CHIP_DIMGREY_CAVEFISH:
1522 case CHIP_BEIGE_GOBY:
1523 adev->nbio.funcs->update_medium_grain_clock_gating(adev,
1524 state == AMD_CG_STATE_GATE);
1525 adev->nbio.funcs->update_medium_grain_light_sleep(adev,
1526 state == AMD_CG_STATE_GATE);
1527 adev->hdp.funcs->update_clock_gating(adev,
1528 state == AMD_CG_STATE_GATE);
1529 adev->smuio.funcs->update_rom_clock_gating(adev,
1530 state == AMD_CG_STATE_GATE);
1538 static int nv_common_set_powergating_state(void *handle,
1539 enum amd_powergating_state state)
1545 static void nv_common_get_clockgating_state(void *handle, u32 *flags)
1547 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1549 if (amdgpu_sriov_vf(adev))
1552 adev->nbio.funcs->get_clockgating_state(adev, flags);
1554 adev->hdp.funcs->get_clock_gating_state(adev, flags);
1556 adev->smuio.funcs->get_clock_gating_state(adev, flags);
1561 static const struct amd_ip_funcs nv_common_ip_funcs = {
1562 .name = "nv_common",
1563 .early_init = nv_common_early_init,
1564 .late_init = nv_common_late_init,
1565 .sw_init = nv_common_sw_init,
1566 .sw_fini = nv_common_sw_fini,
1567 .hw_init = nv_common_hw_init,
1568 .hw_fini = nv_common_hw_fini,
1569 .suspend = nv_common_suspend,
1570 .resume = nv_common_resume,
1571 .is_idle = nv_common_is_idle,
1572 .wait_for_idle = nv_common_wait_for_idle,
1573 .soft_reset = nv_common_soft_reset,
1574 .set_clockgating_state = nv_common_set_clockgating_state,
1575 .set_powergating_state = nv_common_set_powergating_state,
1576 .get_clockgating_state = nv_common_get_clockgating_state,