drivers/gpu/drm/amd/amdgpu/nv.c

   1 /*
   2  * Copyright 2019 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23 #include <linux/firmware.h>
  24 #include <linux/slab.h>
  25 #include <linux/module.h>
  26 #include <linux/pci.h>
  27
  28 #include "amdgpu.h"
  29 #include "amdgpu_atombios.h"
  30 #include "amdgpu_ih.h"
  31 #include "amdgpu_uvd.h"
  32 #include "amdgpu_vce.h"
  33 #include "amdgpu_ucode.h"
  34 #include "amdgpu_psp.h"
  35 #include "amdgpu_smu.h"
  36 #include "atom.h"
  37 #include "amd_pcie.h"
  38
  39 #include "gc/gc_10_1_0_offset.h"
  40 #include "gc/gc_10_1_0_sh_mask.h"
  41 #include "hdp/hdp_5_0_0_offset.h"
  42 #include "hdp/hdp_5_0_0_sh_mask.h"
  43 #include "smuio/smuio_11_0_0_offset.h"
  44 #include "mp/mp_11_0_offset.h"
  45
  46 #include "soc15.h"
  47 #include "soc15_common.h"
  48 #include "gmc_v10_0.h"
  49 #include "gfxhub_v2_0.h"
  50 #include "mmhub_v2_0.h"
  51 #include "nbio_v2_3.h"
  52 #include "nv.h"
  53 #include "navi10_ih.h"
  54 #include "gfx_v10_0.h"
  55 #include "sdma_v5_0.h"
  56 #include "sdma_v5_2.h"
  57 #include "vcn_v2_0.h"
  58 #include "jpeg_v2_0.h"
  59 #include "vcn_v3_0.h"
  60 #include "jpeg_v3_0.h"
  61 #include "dce_virtual.h"
  62 #include "mes_v10_1.h"
  63 #include "mxgpu_nv.h"
  64
  65 static const struct amd_ip_funcs nv_common_ip_funcs;
  66
  67 /*
  68  * Indirect registers accessor
  69  */
  70 static u32 nv_pcie_rreg(struct amdgpu_device *adev, u32 reg)
  71 {
  72         unsigned long address, data;
  73         address = adev->nbio.funcs->get_pcie_index_offset(adev);
  74         data = adev->nbio.funcs->get_pcie_data_offset(adev);
  75
  76         return amdgpu_device_indirect_rreg(adev, address, data, reg);
  77 }
  78
  79 static void nv_pcie_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
  80 {
  81         unsigned long address, data;
  82
  83         address = adev->nbio.funcs->get_pcie_index_offset(adev);
  84         data = adev->nbio.funcs->get_pcie_data_offset(adev);
  85
  86         amdgpu_device_indirect_wreg(adev, address, data, reg, v);
  87 }
  88
  89 static u64 nv_pcie_rreg64(struct amdgpu_device *adev, u32 reg)
  90 {
  91         unsigned long address, data;
  92         address = adev->nbio.funcs->get_pcie_index_offset(adev);
  93         data = adev->nbio.funcs->get_pcie_data_offset(adev);
  94
  95         return amdgpu_device_indirect_rreg64(adev, address, data, reg);
  96 }
  97
  98 static void nv_pcie_wreg64(struct amdgpu_device *adev, u32 reg, u64 v)
  99 {
 100         unsigned long address, data;
 101
 102         address = adev->nbio.funcs->get_pcie_index_offset(adev);
 103         data = adev->nbio.funcs->get_pcie_data_offset(adev);
 104
 105         amdgpu_device_indirect_wreg64(adev, address, data, reg, v);
 106 }
 107
 108 static u32 nv_didt_rreg(struct amdgpu_device *adev, u32 reg)
 109 {
 110         unsigned long flags, address, data;
 111         u32 r;
 112
 113         address = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_INDEX);
 114         data = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_DATA);
 115
 116         spin_lock_irqsave(&adev->didt_idx_lock, flags);
 117         WREG32(address, (reg));
 118         r = RREG32(data);
 119         spin_unlock_irqrestore(&adev->didt_idx_lock, flags);
 120         return r;
 121 }
 122
 123 static void nv_didt_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
 124 {
 125         unsigned long flags, address, data;
 126
 127         address = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_INDEX);
 128         data = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_DATA);
 129
 130         spin_lock_irqsave(&adev->didt_idx_lock, flags);
 131         WREG32(address, (reg));
 132         WREG32(data, (v));
 133         spin_unlock_irqrestore(&adev->didt_idx_lock, flags);
 134 }
 135
 136 static u32 nv_get_config_memsize(struct amdgpu_device *adev)
 137 {
 138         return adev->nbio.funcs->get_memsize(adev);
 139 }
 140
 141 static u32 nv_get_xclk(struct amdgpu_device *adev)
 142 {
 143         return adev->clock.spll.reference_freq;
 144 }
 145
 146
 147 void nv_grbm_select(struct amdgpu_device *adev,
 148                      u32 me, u32 pipe, u32 queue, u32 vmid)
 149 {
 150         u32 grbm_gfx_cntl = 0;
 151         grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, PIPEID, pipe);
 152         grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, MEID, me);
 153         grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, VMID, vmid);
 154         grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, QUEUEID, queue);
 155
 156         WREG32(SOC15_REG_OFFSET(GC, 0, mmGRBM_GFX_CNTL), grbm_gfx_cntl);
 157 }
 158
 159 static void nv_vga_set_state(struct amdgpu_device *adev, bool state)
 160 {
 161         /* todo */
 162 }
 163
 164 static bool nv_read_disabled_bios(struct amdgpu_device *adev)
 165 {
 166         /* todo */
 167         return false;
 168 }
 169
 170 static bool nv_read_bios_from_rom(struct amdgpu_device *adev,
 171                                   u8 *bios, u32 length_bytes)
 172 {
 173         u32 *dw_ptr;
 174         u32 i, length_dw;
 175
 176         if (bios == NULL)
 177                 return false;
 178         if (length_bytes == 0)
 179                 return false;
 180         /* APU vbios image is part of sbios image */
 181         if (adev->flags & AMD_IS_APU)
 182                 return false;
 183
 184         dw_ptr = (u32 *)bios;
 185         length_dw = ALIGN(length_bytes, 4) / 4;
 186
 187         /* set rom index to 0 */
 188         WREG32(SOC15_REG_OFFSET(SMUIO, 0, mmROM_INDEX), 0);
 189         /* read out the rom data */
 190         for (i = 0; i < length_dw; i++)
 191                 dw_ptr[i] = RREG32(SOC15_REG_OFFSET(SMUIO, 0, mmROM_DATA));
 192
 193         return true;
 194 }
 195
 196 static struct soc15_allowed_register_entry nv_allowed_read_registers[] = {
 197         { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS)},
 198         { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS2)},
 199         { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE0)},
 200         { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE1)},
 201         { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE2)},
 202         { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE3)},
 203         { SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_STATUS_REG)},
 204         { SOC15_REG_ENTRY(SDMA1, 0, mmSDMA1_STATUS_REG)},
 205         { SOC15_REG_ENTRY(GC, 0, mmCP_STAT)},
 206         { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT1)},
 207         { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT2)},
 208         { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT3)},
 209         { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_BUSY_STAT)},
 210         { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_STALLED_STAT1)},
 211         { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_STATUS)},
 212         { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_BUSY_STAT)},
 213         { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_STALLED_STAT1)},
 214         { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_STATUS)},
 215         { SOC15_REG_ENTRY(GC, 0, mmGB_ADDR_CONFIG)},
 216 };
 217
 218 static uint32_t nv_read_indexed_register(struct amdgpu_device *adev, u32 se_num,
 219                                          u32 sh_num, u32 reg_offset)
 220 {
 221         uint32_t val;
 222
 223         mutex_lock(&adev->grbm_idx_mutex);
 224         if (se_num != 0xffffffff || sh_num != 0xffffffff)
 225                 amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff);
 226
 227         val = RREG32(reg_offset);
 228
 229         if (se_num != 0xffffffff || sh_num != 0xffffffff)
 230                 amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
 231         mutex_unlock(&adev->grbm_idx_mutex);
 232         return val;
 233 }
 234
 235 static uint32_t nv_get_register_value(struct amdgpu_device *adev,
 236                                       bool indexed, u32 se_num,
 237                                       u32 sh_num, u32 reg_offset)
 238 {
 239         if (indexed) {
 240                 return nv_read_indexed_register(adev, se_num, sh_num, reg_offset);
 241         } else {
 242                 if (reg_offset == SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG))
 243                         return adev->gfx.config.gb_addr_config;
 244                 return RREG32(reg_offset);
 245         }
 246 }
 247
 248 static int nv_read_register(struct amdgpu_device *adev, u32 se_num,
 249                             u32 sh_num, u32 reg_offset, u32 *value)
 250 {
 251         uint32_t i;
 252         struct soc15_allowed_register_entry  *en;
 253
 254         *value = 0;
 255         for (i = 0; i < ARRAY_SIZE(nv_allowed_read_registers); i++) {
 256                 en = &nv_allowed_read_registers[i];
 257                 if (reg_offset !=
 258                     (adev->reg_offset[en->hwip][en->inst][en->seg] + en->reg_offset))
 259                         continue;
 260
 261                 *value = nv_get_register_value(adev,
 262                                                nv_allowed_read_registers[i].grbm_indexed,
 263                                                se_num, sh_num, reg_offset);
 264                 return 0;
 265         }
 266         return -EINVAL;
 267 }
 268
 269 static int nv_asic_mode1_reset(struct amdgpu_device *adev)
 270 {
 271         u32 i;
 272         int ret = 0;
 273
 274         amdgpu_atombios_scratch_regs_engine_hung(adev, true);
 275
 276         /* disable BM */
 277         pci_clear_master(adev->pdev);
 278
 279         amdgpu_device_cache_pci_state(adev->pdev);
 280
 281         if (amdgpu_dpm_is_mode1_reset_supported(adev)) {
 282                 dev_info(adev->dev, "GPU smu mode1 reset\n");
 283                 ret = amdgpu_dpm_mode1_reset(adev);
 284         } else {
 285                 dev_info(adev->dev, "GPU psp mode1 reset\n");
 286                 ret = psp_gpu_reset(adev);
 287         }
 288
 289         if (ret)
 290                 dev_err(adev->dev, "GPU mode1 reset failed\n");
 291         amdgpu_device_load_pci_state(adev->pdev);
 292
 293         /* wait for asic to come out of reset */
 294         for (i = 0; i < adev->usec_timeout; i++) {
 295                 u32 memsize = adev->nbio.funcs->get_memsize(adev);
 296
 297                 if (memsize != 0xffffffff)
 298                         break;
 299                 udelay(1);
 300         }
 301
 302         amdgpu_atombios_scratch_regs_engine_hung(adev, false);
 303
 304         return ret;
 305 }
 306
 307 static bool nv_asic_supports_baco(struct amdgpu_device *adev)
 308 {
 309         struct smu_context *smu = &adev->smu;
 310
 311         if (smu_baco_is_support(smu))
 312                 return true;
 313         else
 314                 return false;
 315 }
 316
 317 static enum amd_reset_method
 318 nv_asic_reset_method(struct amdgpu_device *adev)
 319 {
 320         struct smu_context *smu = &adev->smu;
 321
 322         if (amdgpu_reset_method == AMD_RESET_METHOD_MODE1 ||
 323             amdgpu_reset_method == AMD_RESET_METHOD_BACO)
 324                 return amdgpu_reset_method;
 325
 326         if (amdgpu_reset_method != -1)
 327                 dev_warn(adev->dev, "Specified reset method:%d isn't supported, using AUTO instead.\n",
 328                                   amdgpu_reset_method);
 329
 330         switch (adev->asic_type) {
 331         case CHIP_SIENNA_CICHLID:
 332         case CHIP_NAVY_FLOUNDER:
 333                 return AMD_RESET_METHOD_MODE1;
 334         default:
 335                 if (smu_baco_is_support(smu))
 336                         return AMD_RESET_METHOD_BACO;
 337                 else
 338                         return AMD_RESET_METHOD_MODE1;
 339         }
 340 }
 341
 342 static int nv_asic_reset(struct amdgpu_device *adev)
 343 {
 344         int ret = 0;
 345         struct smu_context *smu = &adev->smu;
 346
 347         if (nv_asic_reset_method(adev) == AMD_RESET_METHOD_BACO) {
 348                 dev_info(adev->dev, "BACO reset\n");
 349
 350                 ret = smu_baco_enter(smu);
 351                 if (ret)
 352                         return ret;
 353                 ret = smu_baco_exit(smu);
 354                 if (ret)
 355                         return ret;
 356         } else {
 357                 dev_info(adev->dev, "MODE1 reset\n");
 358                 ret = nv_asic_mode1_reset(adev);
 359         }
 360
 361         return ret;
 362 }
 363
 364 static int nv_set_uvd_clocks(struct amdgpu_device *adev, u32 vclk, u32 dclk)
 365 {
 366         /* todo */
 367         return 0;
 368 }
 369
 370 static int nv_set_vce_clocks(struct amdgpu_device *adev, u32 evclk, u32 ecclk)
 371 {
 372         /* todo */
 373         return 0;
 374 }
 375
 376 static void nv_pcie_gen3_enable(struct amdgpu_device *adev)
 377 {
 378         if (pci_is_root_bus(adev->pdev->bus))
 379                 return;
 380
 381         if (amdgpu_pcie_gen2 == 0)
 382                 return;
 383
 384         if (!(adev->pm.pcie_gen_mask & (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 |
 385                                         CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3)))
 386                 return;
 387
 388         /* todo */
 389 }
 390
 391 static void nv_program_aspm(struct amdgpu_device *adev)
 392 {
 393
 394         if (amdgpu_aspm == 0)
 395                 return;
 396
 397         /* todo */
 398 }
 399
 400 static void nv_enable_doorbell_aperture(struct amdgpu_device *adev,
 401                                         bool enable)
 402 {
 403         adev->nbio.funcs->enable_doorbell_aperture(adev, enable);
 404         adev->nbio.funcs->enable_doorbell_selfring_aperture(adev, enable);
 405 }
 406
 407 static const struct amdgpu_ip_block_version nv_common_ip_block =
 408 {
 409         .type = AMD_IP_BLOCK_TYPE_COMMON,
 410         .major = 1,
 411         .minor = 0,
 412         .rev = 0,
 413         .funcs = &nv_common_ip_funcs,
 414 };
 415
 416 static int nv_reg_base_init(struct amdgpu_device *adev)
 417 {
 418         int r;
 419
 420         if (amdgpu_discovery) {
 421                 r = amdgpu_discovery_reg_base_init(adev);
 422                 if (r) {
 423                         DRM_WARN("failed to init reg base from ip discovery table, "
 424                                         "fallback to legacy init method\n");
 425                         goto legacy_init;
 426                 }
 427
 428                 return 0;
 429         }
 430
 431 legacy_init:
 432         switch (adev->asic_type) {
 433         case CHIP_NAVI10:
 434                 navi10_reg_base_init(adev);
 435                 break;
 436         case CHIP_NAVI14:
 437                 navi14_reg_base_init(adev);
 438                 break;
 439         case CHIP_NAVI12:
 440                 navi12_reg_base_init(adev);
 441                 break;
 442         case CHIP_SIENNA_CICHLID:
 443         case CHIP_NAVY_FLOUNDER:
 444                 sienna_cichlid_reg_base_init(adev);
 445                 break;
 446         default:
 447                 return -EINVAL;
 448         }
 449
 450         return 0;
 451 }
 452
 453 void nv_set_virt_ops(struct amdgpu_device *adev)
 454 {
 455         adev->virt.ops = &xgpu_nv_virt_ops;
 456 }
 457
 458 static bool nv_is_headless_sku(struct pci_dev *pdev)
 459 {
 460         if ((pdev->device == 0x731E &&
 461             (pdev->revision == 0xC6 || pdev->revision == 0xC7)) ||
 462             (pdev->device == 0x7340 && pdev->revision == 0xC9))
 463                 return true;
 464         return false;
 465 }
 466
 467 int nv_set_ip_blocks(struct amdgpu_device *adev)
 468 {
 469         int r;
 470
 471         adev->nbio.funcs = &nbio_v2_3_funcs;
 472         adev->nbio.hdp_flush_reg = &nbio_v2_3_hdp_flush_reg;
 473
 474         if (adev->asic_type == CHIP_SIENNA_CICHLID)
 475                 adev->gmc.xgmi.supported = true;
 476
 477         /* Set IP register base before any HW register access */
 478         r = nv_reg_base_init(adev);
 479         if (r)
 480                 return r;
 481
 482         switch (adev->asic_type) {
 483         case CHIP_NAVI10:
 484         case CHIP_NAVI14:
 485                 amdgpu_device_ip_block_add(adev, &nv_common_ip_block);
 486                 amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block);
 487                 amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block);
 488                 amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block);
 489                 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP &&
 490                     !amdgpu_sriov_vf(adev))
 491                         amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);
 492                 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))
 493                         amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
 494 #if defined(CONFIG_DRM_AMD_DC)
 495                 else if (amdgpu_device_has_dc_support(adev))
 496                         amdgpu_device_ip_block_add(adev, &dm_ip_block);
 497 #endif
 498                 amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block);
 499                 amdgpu_device_ip_block_add(adev, &sdma_v5_0_ip_block);
 500                 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT &&
 501                     !amdgpu_sriov_vf(adev))
 502                         amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);
 503                 if (!nv_is_headless_sku(adev->pdev))
 504                         amdgpu_device_ip_block_add(adev, &vcn_v2_0_ip_block);
 505                 amdgpu_device_ip_block_add(adev, &jpeg_v2_0_ip_block);
 506                 if (adev->enable_mes)
 507                         amdgpu_device_ip_block_add(adev, &mes_v10_1_ip_block);
 508                 break;
 509         case CHIP_NAVI12:
 510                 amdgpu_device_ip_block_add(adev, &nv_common_ip_block);
 511                 amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block);
 512                 amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block);
 513                 amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block);
 514                 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)
 515                         amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);
 516                 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))
 517                         amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
 518 #if defined(CONFIG_DRM_AMD_DC)
 519                 else if (amdgpu_device_has_dc_support(adev))
 520                         amdgpu_device_ip_block_add(adev, &dm_ip_block);
 521 #endif
 522                 amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block);
 523                 amdgpu_device_ip_block_add(adev, &sdma_v5_0_ip_block);
 524                 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT &&
 525                     !amdgpu_sriov_vf(adev))
 526                         amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);
 527                 amdgpu_device_ip_block_add(adev, &vcn_v2_0_ip_block);
 528                 if (!amdgpu_sriov_vf(adev))
 529                         amdgpu_device_ip_block_add(adev, &jpeg_v2_0_ip_block);
 530                 break;
 531         case CHIP_SIENNA_CICHLID:
 532                 amdgpu_device_ip_block_add(adev, &nv_common_ip_block);
 533                 amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block);
 534                 amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block);
 535                 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP))
 536                         amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block);
 537                 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP &&
 538                     is_support_sw_smu(adev) && !amdgpu_sriov_vf(adev))
 539                         amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);
 540                 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))
 541                         amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
 542 #if defined(CONFIG_DRM_AMD_DC)
 543                 else if (amdgpu_device_has_dc_support(adev))
 544                         amdgpu_device_ip_block_add(adev, &dm_ip_block);
 545 #endif
 546                 amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block);
 547                 amdgpu_device_ip_block_add(adev, &sdma_v5_2_ip_block);
 548                 amdgpu_device_ip_block_add(adev, &vcn_v3_0_ip_block);
 549                 if (!amdgpu_sriov_vf(adev))
 550                         amdgpu_device_ip_block_add(adev, &jpeg_v3_0_ip_block);
 551
 552                 if (adev->enable_mes)
 553                         amdgpu_device_ip_block_add(adev, &mes_v10_1_ip_block);
 554                 break;
 555         case CHIP_NAVY_FLOUNDER:
 556                 amdgpu_device_ip_block_add(adev, &nv_common_ip_block);
 557                 amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block);
 558                 amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block);
 559                 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP))
 560                         amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block);
 561                 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP &&
 562                     is_support_sw_smu(adev))
 563                         amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);
 564                 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))
 565                         amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
 566 #if defined(CONFIG_DRM_AMD_DC)
 567                 else if (amdgpu_device_has_dc_support(adev))
 568                         amdgpu_device_ip_block_add(adev, &dm_ip_block);
 569 #endif
 570                 amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block);
 571                 amdgpu_device_ip_block_add(adev, &sdma_v5_2_ip_block);
 572                 amdgpu_device_ip_block_add(adev, &vcn_v3_0_ip_block);
 573                 amdgpu_device_ip_block_add(adev, &jpeg_v3_0_ip_block);
 574                 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT &&
 575                     is_support_sw_smu(adev))
 576                         amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);
 577                 break;
 578         default:
 579                 return -EINVAL;
 580         }
 581
 582         return 0;
 583 }
 584
 585 static uint32_t nv_get_rev_id(struct amdgpu_device *adev)
 586 {
 587         return adev->nbio.funcs->get_rev_id(adev);
 588 }
 589
 590 static void nv_flush_hdp(struct amdgpu_device *adev, struct amdgpu_ring *ring)
 591 {
 592         adev->nbio.funcs->hdp_flush(adev, ring);
 593 }
 594
 595 static void nv_invalidate_hdp(struct amdgpu_device *adev,
 596                                 struct amdgpu_ring *ring)
 597 {
 598         if (!ring || !ring->funcs->emit_wreg) {
 599                 WREG32_SOC15_NO_KIQ(HDP, 0, mmHDP_READ_CACHE_INVALIDATE, 1);
 600         } else {
 601                 amdgpu_ring_emit_wreg(ring, SOC15_REG_OFFSET(
 602                                         HDP, 0, mmHDP_READ_CACHE_INVALIDATE), 1);
 603         }
 604 }
 605
 606 static bool nv_need_full_reset(struct amdgpu_device *adev)
 607 {
 608         return true;
 609 }
 610
 611 static bool nv_need_reset_on_init(struct amdgpu_device *adev)
 612 {
 613         u32 sol_reg;
 614
 615         if (adev->flags & AMD_IS_APU)
 616                 return false;
 617
 618         /* Check sOS sign of life register to confirm sys driver and sOS
 619          * are already been loaded.
 620          */
 621         sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81);
 622         if (sol_reg)
 623                 return true;
 624
 625         return false;
 626 }
 627
 628 static uint64_t nv_get_pcie_replay_count(struct amdgpu_device *adev)
 629 {
 630
 631         /* TODO
 632          * dummy implement for pcie_replay_count sysfs interface
 633          * */
 634
 635         return 0;
 636 }
 637
 638 static void nv_init_doorbell_index(struct amdgpu_device *adev)
 639 {
 640         adev->doorbell_index.kiq = AMDGPU_NAVI10_DOORBELL_KIQ;
 641         adev->doorbell_index.mec_ring0 = AMDGPU_NAVI10_DOORBELL_MEC_RING0;
 642         adev->doorbell_index.mec_ring1 = AMDGPU_NAVI10_DOORBELL_MEC_RING1;
 643         adev->doorbell_index.mec_ring2 = AMDGPU_NAVI10_DOORBELL_MEC_RING2;
 644         adev->doorbell_index.mec_ring3 = AMDGPU_NAVI10_DOORBELL_MEC_RING3;
 645         adev->doorbell_index.mec_ring4 = AMDGPU_NAVI10_DOORBELL_MEC_RING4;
 646         adev->doorbell_index.mec_ring5 = AMDGPU_NAVI10_DOORBELL_MEC_RING5;
 647         adev->doorbell_index.mec_ring6 = AMDGPU_NAVI10_DOORBELL_MEC_RING6;
 648         adev->doorbell_index.mec_ring7 = AMDGPU_NAVI10_DOORBELL_MEC_RING7;
 649         adev->doorbell_index.userqueue_start = AMDGPU_NAVI10_DOORBELL_USERQUEUE_START;
 650         adev->doorbell_index.userqueue_end = AMDGPU_NAVI10_DOORBELL_USERQUEUE_END;
 651         adev->doorbell_index.gfx_ring0 = AMDGPU_NAVI10_DOORBELL_GFX_RING0;
 652         adev->doorbell_index.gfx_ring1 = AMDGPU_NAVI10_DOORBELL_GFX_RING1;
 653         adev->doorbell_index.mes_ring = AMDGPU_NAVI10_DOORBELL_MES_RING;
 654         adev->doorbell_index.sdma_engine[0] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE0;
 655         adev->doorbell_index.sdma_engine[1] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE1;
 656         adev->doorbell_index.sdma_engine[2] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE2;
 657         adev->doorbell_index.sdma_engine[3] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE3;
 658         adev->doorbell_index.ih = AMDGPU_NAVI10_DOORBELL_IH;
 659         adev->doorbell_index.vcn.vcn_ring0_1 = AMDGPU_NAVI10_DOORBELL64_VCN0_1;
 660         adev->doorbell_index.vcn.vcn_ring2_3 = AMDGPU_NAVI10_DOORBELL64_VCN2_3;
 661         adev->doorbell_index.vcn.vcn_ring4_5 = AMDGPU_NAVI10_DOORBELL64_VCN4_5;
 662         adev->doorbell_index.vcn.vcn_ring6_7 = AMDGPU_NAVI10_DOORBELL64_VCN6_7;
 663         adev->doorbell_index.first_non_cp = AMDGPU_NAVI10_DOORBELL64_FIRST_NON_CP;
 664         adev->doorbell_index.last_non_cp = AMDGPU_NAVI10_DOORBELL64_LAST_NON_CP;
 665
 666         adev->doorbell_index.max_assignment = AMDGPU_NAVI10_DOORBELL_MAX_ASSIGNMENT << 1;
 667         adev->doorbell_index.sdma_doorbell_range = 20;
 668 }
 669
 670 static void nv_pre_asic_init(struct amdgpu_device *adev)
 671 {
 672 }
 673
 674 static const struct amdgpu_asic_funcs nv_asic_funcs =
 675 {
 676         .read_disabled_bios = &nv_read_disabled_bios,
 677         .read_bios_from_rom = &nv_read_bios_from_rom,
 678         .read_register = &nv_read_register,
 679         .reset = &nv_asic_reset,
 680         .reset_method = &nv_asic_reset_method,
 681         .set_vga_state = &nv_vga_set_state,
 682         .get_xclk = &nv_get_xclk,
 683         .set_uvd_clocks = &nv_set_uvd_clocks,
 684         .set_vce_clocks = &nv_set_vce_clocks,
 685         .get_config_memsize = &nv_get_config_memsize,
 686         .flush_hdp = &nv_flush_hdp,
 687         .invalidate_hdp = &nv_invalidate_hdp,
 688         .init_doorbell_index = &nv_init_doorbell_index,
 689         .need_full_reset = &nv_need_full_reset,
 690         .need_reset_on_init = &nv_need_reset_on_init,
 691         .get_pcie_replay_count = &nv_get_pcie_replay_count,
 692         .supports_baco = &nv_asic_supports_baco,
 693         .pre_asic_init = &nv_pre_asic_init,
 694 };
 695
 696 static int nv_common_early_init(void *handle)
 697 {
 698 #define MMIO_REG_HOLE_OFFSET (0x80000 - PAGE_SIZE)
 699         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 700
 701         adev->rmmio_remap.reg_offset = MMIO_REG_HOLE_OFFSET;
 702         adev->rmmio_remap.bus_addr = adev->rmmio_base + MMIO_REG_HOLE_OFFSET;
 703         adev->smc_rreg = NULL;
 704         adev->smc_wreg = NULL;
 705         adev->pcie_rreg = &nv_pcie_rreg;
 706         adev->pcie_wreg = &nv_pcie_wreg;
 707         adev->pcie_rreg64 = &nv_pcie_rreg64;
 708         adev->pcie_wreg64 = &nv_pcie_wreg64;
 709
 710         /* TODO: will add them during VCN v2 implementation */
 711         adev->uvd_ctx_rreg = NULL;
 712         adev->uvd_ctx_wreg = NULL;
 713
 714         adev->didt_rreg = &nv_didt_rreg;
 715         adev->didt_wreg = &nv_didt_wreg;
 716
 717         adev->asic_funcs = &nv_asic_funcs;
 718
 719         adev->rev_id = nv_get_rev_id(adev);
 720         adev->external_rev_id = 0xff;
 721         switch (adev->asic_type) {
 722         case CHIP_NAVI10:
 723                 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
 724                         AMD_CG_SUPPORT_GFX_CGCG |
 725                         AMD_CG_SUPPORT_IH_CG |
 726                         AMD_CG_SUPPORT_HDP_MGCG |
 727                         AMD_CG_SUPPORT_HDP_LS |
 728                         AMD_CG_SUPPORT_SDMA_MGCG |
 729                         AMD_CG_SUPPORT_SDMA_LS |
 730                         AMD_CG_SUPPORT_MC_MGCG |
 731                         AMD_CG_SUPPORT_MC_LS |
 732                         AMD_CG_SUPPORT_ATHUB_MGCG |
 733                         AMD_CG_SUPPORT_ATHUB_LS |
 734                         AMD_CG_SUPPORT_VCN_MGCG |
 735                         AMD_CG_SUPPORT_JPEG_MGCG |
 736                         AMD_CG_SUPPORT_BIF_MGCG |
 737                         AMD_CG_SUPPORT_BIF_LS;
 738                 adev->pg_flags = AMD_PG_SUPPORT_VCN |
 739                         AMD_PG_SUPPORT_VCN_DPG |
 740                         AMD_PG_SUPPORT_JPEG |
 741                         AMD_PG_SUPPORT_ATHUB;
 742                 adev->external_rev_id = adev->rev_id + 0x1;
 743                 break;
 744         case CHIP_NAVI14:
 745                 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
 746                         AMD_CG_SUPPORT_GFX_CGCG |
 747                         AMD_CG_SUPPORT_IH_CG |
 748                         AMD_CG_SUPPORT_HDP_MGCG |
 749                         AMD_CG_SUPPORT_HDP_LS |
 750                         AMD_CG_SUPPORT_SDMA_MGCG |
 751                         AMD_CG_SUPPORT_SDMA_LS |
 752                         AMD_CG_SUPPORT_MC_MGCG |
 753                         AMD_CG_SUPPORT_MC_LS |
 754                         AMD_CG_SUPPORT_ATHUB_MGCG |
 755                         AMD_CG_SUPPORT_ATHUB_LS |
 756                         AMD_CG_SUPPORT_VCN_MGCG |
 757                         AMD_CG_SUPPORT_JPEG_MGCG |
 758                         AMD_CG_SUPPORT_BIF_MGCG |
 759                         AMD_CG_SUPPORT_BIF_LS;
 760                 adev->pg_flags = AMD_PG_SUPPORT_VCN |
 761                         AMD_PG_SUPPORT_JPEG |
 762                         AMD_PG_SUPPORT_VCN_DPG;
 763                 adev->external_rev_id = adev->rev_id + 20;
 764                 break;
 765         case CHIP_NAVI12:
 766                 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
 767                         AMD_CG_SUPPORT_GFX_MGLS |
 768                         AMD_CG_SUPPORT_GFX_CGCG |
 769                         AMD_CG_SUPPORT_GFX_CP_LS |
 770                         AMD_CG_SUPPORT_GFX_RLC_LS |
 771                         AMD_CG_SUPPORT_IH_CG |
 772                         AMD_CG_SUPPORT_HDP_MGCG |
 773                         AMD_CG_SUPPORT_HDP_LS |
 774                         AMD_CG_SUPPORT_SDMA_MGCG |
 775                         AMD_CG_SUPPORT_SDMA_LS |
 776                         AMD_CG_SUPPORT_MC_MGCG |
 777                         AMD_CG_SUPPORT_MC_LS |
 778                         AMD_CG_SUPPORT_ATHUB_MGCG |
 779                         AMD_CG_SUPPORT_ATHUB_LS |
 780                         AMD_CG_SUPPORT_VCN_MGCG |
 781                         AMD_CG_SUPPORT_JPEG_MGCG;
 782                 adev->pg_flags = AMD_PG_SUPPORT_VCN |
 783                         AMD_PG_SUPPORT_VCN_DPG |
 784                         AMD_PG_SUPPORT_JPEG |
 785                         AMD_PG_SUPPORT_ATHUB;
 786                 /* guest vm gets 0xffffffff when reading RCC_DEV0_EPF0_STRAP0,
 787                  * as a consequence, the rev_id and external_rev_id are wrong.
 788                  * workaround it by hardcoding rev_id to 0 (default value).
 789                  */
 790                 if (amdgpu_sriov_vf(adev))
 791                         adev->rev_id = 0;
 792                 adev->external_rev_id = adev->rev_id + 0xa;
 793                 break;
 794         case CHIP_SIENNA_CICHLID:
 795                 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
 796                         AMD_CG_SUPPORT_GFX_CGCG |
 797                         AMD_CG_SUPPORT_GFX_3D_CGCG |
 798                         AMD_CG_SUPPORT_MC_MGCG |
 799                         AMD_CG_SUPPORT_VCN_MGCG |
 800                         AMD_CG_SUPPORT_JPEG_MGCG |
 801                         AMD_CG_SUPPORT_HDP_MGCG |
 802                         AMD_CG_SUPPORT_HDP_LS |
 803                         AMD_CG_SUPPORT_IH_CG |
 804                         AMD_CG_SUPPORT_MC_LS;
 805                 adev->pg_flags = AMD_PG_SUPPORT_VCN |
 806                         AMD_PG_SUPPORT_VCN_DPG |
 807                         AMD_PG_SUPPORT_JPEG |
 808                         AMD_PG_SUPPORT_ATHUB |
 809                         AMD_PG_SUPPORT_MMHUB;
 810                 if (amdgpu_sriov_vf(adev)) {
 811                         /* hypervisor control CG and PG enablement */
 812                         adev->cg_flags = 0;
 813                         adev->pg_flags = 0;
 814                 }
 815                 adev->external_rev_id = adev->rev_id + 0x28;
 816                 break;
 817         case CHIP_NAVY_FLOUNDER:
 818                 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
 819                         AMD_CG_SUPPORT_GFX_CGCG |
 820                         AMD_CG_SUPPORT_GFX_3D_CGCG |
 821                         AMD_CG_SUPPORT_VCN_MGCG |
 822                         AMD_CG_SUPPORT_JPEG_MGCG |
 823                         AMD_CG_SUPPORT_MC_MGCG |
 824                         AMD_CG_SUPPORT_MC_LS |
 825                         AMD_CG_SUPPORT_HDP_MGCG |
 826                         AMD_CG_SUPPORT_HDP_LS |
 827                         AMD_CG_SUPPORT_IH_CG;
 828                 adev->pg_flags = AMD_PG_SUPPORT_VCN |
 829                         AMD_PG_SUPPORT_VCN_DPG |
 830                         AMD_PG_SUPPORT_JPEG |
 831                         AMD_PG_SUPPORT_ATHUB |
 832                         AMD_PG_SUPPORT_MMHUB;
 833                 adev->external_rev_id = adev->rev_id + 0x32;
 834                 break;
 835
 836         default:
 837                 /* FIXME: not supported yet */
 838                 return -EINVAL;
 839         }
 840
 841         if (amdgpu_sriov_vf(adev)) {
 842                 amdgpu_virt_init_setting(adev);
 843                 xgpu_nv_mailbox_set_irq_funcs(adev);
 844         }
 845
 846         return 0;
 847 }
 848
 849 static int nv_common_late_init(void *handle)
 850 {
 851         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 852
 853         if (amdgpu_sriov_vf(adev))
 854                 xgpu_nv_mailbox_get_irq(adev);
 855
 856         return 0;
 857 }
 858
 859 static int nv_common_sw_init(void *handle)
 860 {
 861         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 862
 863         if (amdgpu_sriov_vf(adev))
 864                 xgpu_nv_mailbox_add_irq_id(adev);
 865
 866         return 0;
 867 }
 868
 869 static int nv_common_sw_fini(void *handle)
 870 {
 871         return 0;
 872 }
 873
 874 static int nv_common_hw_init(void *handle)
 875 {
 876         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 877
 878         /* enable pcie gen2/3 link */
 879         nv_pcie_gen3_enable(adev);
 880         /* enable aspm */
 881         nv_program_aspm(adev);
 882         /* setup nbio registers */
 883         adev->nbio.funcs->init_registers(adev);
 884         /* remap HDP registers to a hole in mmio space,
 885          * for the purpose of expose those registers
 886          * to process space
 887          */
 888         if (adev->nbio.funcs->remap_hdp_registers)
 889                 adev->nbio.funcs->remap_hdp_registers(adev);
 890         /* enable the doorbell aperture */
 891         nv_enable_doorbell_aperture(adev, true);
 892
 893         return 0;
 894 }
 895
 896 static int nv_common_hw_fini(void *handle)
 897 {
 898         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 899
 900         /* disable the doorbell aperture */
 901         nv_enable_doorbell_aperture(adev, false);
 902
 903         return 0;
 904 }
 905
 906 static int nv_common_suspend(void *handle)
 907 {
 908         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 909
 910         return nv_common_hw_fini(adev);
 911 }
 912
 913 static int nv_common_resume(void *handle)
 914 {
 915         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 916
 917         return nv_common_hw_init(adev);
 918 }
 919
 920 static bool nv_common_is_idle(void *handle)
 921 {
 922         return true;
 923 }
 924
 925 static int nv_common_wait_for_idle(void *handle)
 926 {
 927         return 0;
 928 }
 929
 930 static int nv_common_soft_reset(void *handle)
 931 {
 932         return 0;
 933 }
 934
 935 static void nv_update_hdp_mem_power_gating(struct amdgpu_device *adev,
 936                                            bool enable)
 937 {
 938         uint32_t hdp_clk_cntl, hdp_clk_cntl1;
 939         uint32_t hdp_mem_pwr_cntl;
 940
 941         if (!(adev->cg_flags & (AMD_CG_SUPPORT_HDP_LS |
 942                                 AMD_CG_SUPPORT_HDP_DS |
 943                                 AMD_CG_SUPPORT_HDP_SD)))
 944                 return;
 945
 946         hdp_clk_cntl = hdp_clk_cntl1 = RREG32_SOC15(HDP, 0, mmHDP_CLK_CNTL);
 947         hdp_mem_pwr_cntl = RREG32_SOC15(HDP, 0, mmHDP_MEM_POWER_CTRL);
 948
 949         /* Before doing clock/power mode switch,
 950          * forced on IPH & RC clock */
 951         hdp_clk_cntl = REG_SET_FIELD(hdp_clk_cntl, HDP_CLK_CNTL,
 952                                      IPH_MEM_CLK_SOFT_OVERRIDE, 1);
 953         hdp_clk_cntl = REG_SET_FIELD(hdp_clk_cntl, HDP_CLK_CNTL,
 954                                      RC_MEM_CLK_SOFT_OVERRIDE, 1);
 955         WREG32_SOC15(HDP, 0, mmHDP_CLK_CNTL, hdp_clk_cntl);
 956
 957         /* HDP 5.0 doesn't support dynamic power mode switch,
 958          * disable clock and power gating before any changing */
 959         hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,
 960                                          IPH_MEM_POWER_CTRL_EN, 0);
 961         hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,
 962                                          IPH_MEM_POWER_LS_EN, 0);
 963         hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,
 964                                          IPH_MEM_POWER_DS_EN, 0);
 965         hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,
 966                                          IPH_MEM_POWER_SD_EN, 0);
 967         hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,
 968                                          RC_MEM_POWER_CTRL_EN, 0);
 969         hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,
 970                                          RC_MEM_POWER_LS_EN, 0);
 971         hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,
 972                                          RC_MEM_POWER_DS_EN, 0);
 973         hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,
 974                                          RC_MEM_POWER_SD_EN, 0);
 975         WREG32_SOC15(HDP, 0, mmHDP_MEM_POWER_CTRL, hdp_mem_pwr_cntl);
 976
 977         /* only one clock gating mode (LS/DS/SD) can be enabled */
 978         if (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS) {
 979                 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl,
 980                                                  HDP_MEM_POWER_CTRL,
 981                                                  IPH_MEM_POWER_LS_EN, enable);
 982                 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl,
 983                                                  HDP_MEM_POWER_CTRL,
 984                                                  RC_MEM_POWER_LS_EN, enable);
 985         } else if (adev->cg_flags & AMD_CG_SUPPORT_HDP_DS) {
 986                 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl,
 987                                                  HDP_MEM_POWER_CTRL,
 988                                                  IPH_MEM_POWER_DS_EN, enable);
 989                 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl,
 990                                                  HDP_MEM_POWER_CTRL,
 991                                                  RC_MEM_POWER_DS_EN, enable);
 992         } else if (adev->cg_flags & AMD_CG_SUPPORT_HDP_SD) {
 993                 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl,
 994                                                  HDP_MEM_POWER_CTRL,
 995                                                  IPH_MEM_POWER_SD_EN, enable);
 996                 /* RC should not use shut down mode, fallback to ds */
 997                 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl,
 998                                                  HDP_MEM_POWER_CTRL,
 999                                                  RC_MEM_POWER_DS_EN, enable);
1000         }
1001
1002         /* confirmed that IPH_MEM_POWER_CTRL_EN and RC_MEM_POWER_CTRL_EN have to
1003          * be set for SRAM LS/DS/SD */
1004         if (adev->cg_flags & (AMD_CG_SUPPORT_HDP_LS | AMD_CG_SUPPORT_HDP_DS |
1005                                                         AMD_CG_SUPPORT_HDP_SD)) {
1006                 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,
1007                                                 IPH_MEM_POWER_CTRL_EN, 1);
1008                 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,
1009                                                 RC_MEM_POWER_CTRL_EN, 1);
1010         }
1011
1012         WREG32_SOC15(HDP, 0, mmHDP_MEM_POWER_CTRL, hdp_mem_pwr_cntl);
1013
1014         /* restore IPH & RC clock override after clock/power mode changing */
1015         WREG32_SOC15(HDP, 0, mmHDP_CLK_CNTL, hdp_clk_cntl1);
1016 }
1017
1018 static void nv_update_hdp_clock_gating(struct amdgpu_device *adev,
1019                                        bool enable)
1020 {
1021         uint32_t hdp_clk_cntl;
1022
1023         if (!(adev->cg_flags & AMD_CG_SUPPORT_HDP_MGCG))
1024                 return;
1025
1026         hdp_clk_cntl = RREG32_SOC15(HDP, 0, mmHDP_CLK_CNTL);
1027
1028         if (enable) {
1029                 hdp_clk_cntl &=
1030                         ~(uint32_t)
1031                           (HDP_CLK_CNTL__IPH_MEM_CLK_SOFT_OVERRIDE_MASK |
1032                            HDP_CLK_CNTL__RC_MEM_CLK_SOFT_OVERRIDE_MASK |
1033                            HDP_CLK_CNTL__DBUS_CLK_SOFT_OVERRIDE_MASK |
1034                            HDP_CLK_CNTL__DYN_CLK_SOFT_OVERRIDE_MASK |
1035                            HDP_CLK_CNTL__XDP_REG_CLK_SOFT_OVERRIDE_MASK |
1036                            HDP_CLK_CNTL__HDP_REG_CLK_SOFT_OVERRIDE_MASK);
1037         } else {
1038                 hdp_clk_cntl |= HDP_CLK_CNTL__IPH_MEM_CLK_SOFT_OVERRIDE_MASK |
1039                         HDP_CLK_CNTL__RC_MEM_CLK_SOFT_OVERRIDE_MASK |
1040                         HDP_CLK_CNTL__DBUS_CLK_SOFT_OVERRIDE_MASK |
1041                         HDP_CLK_CNTL__DYN_CLK_SOFT_OVERRIDE_MASK |
1042                         HDP_CLK_CNTL__XDP_REG_CLK_SOFT_OVERRIDE_MASK |
1043                         HDP_CLK_CNTL__HDP_REG_CLK_SOFT_OVERRIDE_MASK;
1044         }
1045
1046         WREG32_SOC15(HDP, 0, mmHDP_CLK_CNTL, hdp_clk_cntl);
1047 }
1048
1049 static int nv_common_set_clockgating_state(void *handle,
1050                                            enum amd_clockgating_state state)
1051 {
1052         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1053
1054         if (amdgpu_sriov_vf(adev))
1055                 return 0;
1056
1057         switch (adev->asic_type) {
1058         case CHIP_NAVI10:
1059         case CHIP_NAVI14:
1060         case CHIP_NAVI12:
1061         case CHIP_SIENNA_CICHLID:
1062         case CHIP_NAVY_FLOUNDER:
1063                 adev->nbio.funcs->update_medium_grain_clock_gating(adev,
1064                                 state == AMD_CG_STATE_GATE);
1065                 adev->nbio.funcs->update_medium_grain_light_sleep(adev,
1066                                 state == AMD_CG_STATE_GATE);
1067                 nv_update_hdp_mem_power_gating(adev,
1068                                    state == AMD_CG_STATE_GATE);
1069                 nv_update_hdp_clock_gating(adev,
1070                                 state == AMD_CG_STATE_GATE);
1071                 break;
1072         default:
1073                 break;
1074         }
1075         return 0;
1076 }
1077
1078 static int nv_common_set_powergating_state(void *handle,
1079                                            enum amd_powergating_state state)
1080 {
1081         /* TODO */
1082         return 0;
1083 }
1084
1085 static void nv_common_get_clockgating_state(void *handle, u32 *flags)
1086 {
1087         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1088         uint32_t tmp;
1089
1090         if (amdgpu_sriov_vf(adev))
1091                 *flags = 0;
1092
1093         adev->nbio.funcs->get_clockgating_state(adev, flags);
1094
1095         /* AMD_CG_SUPPORT_HDP_MGCG */
1096         tmp = RREG32_SOC15(HDP, 0, mmHDP_CLK_CNTL);
1097         if (!(tmp & (HDP_CLK_CNTL__IPH_MEM_CLK_SOFT_OVERRIDE_MASK |
1098                      HDP_CLK_CNTL__RC_MEM_CLK_SOFT_OVERRIDE_MASK |
1099                      HDP_CLK_CNTL__DBUS_CLK_SOFT_OVERRIDE_MASK |
1100                      HDP_CLK_CNTL__DYN_CLK_SOFT_OVERRIDE_MASK |
1101                      HDP_CLK_CNTL__XDP_REG_CLK_SOFT_OVERRIDE_MASK |
1102                      HDP_CLK_CNTL__HDP_REG_CLK_SOFT_OVERRIDE_MASK)))
1103                 *flags |= AMD_CG_SUPPORT_HDP_MGCG;
1104
1105         /* AMD_CG_SUPPORT_HDP_LS/DS/SD */
1106         tmp = RREG32_SOC15(HDP, 0, mmHDP_MEM_POWER_CTRL);
1107         if (tmp & HDP_MEM_POWER_CTRL__IPH_MEM_POWER_LS_EN_MASK)
1108                 *flags |= AMD_CG_SUPPORT_HDP_LS;
1109         else if (tmp & HDP_MEM_POWER_CTRL__IPH_MEM_POWER_DS_EN_MASK)
1110                 *flags |= AMD_CG_SUPPORT_HDP_DS;
1111         else if (tmp & HDP_MEM_POWER_CTRL__IPH_MEM_POWER_SD_EN_MASK)
1112                 *flags |= AMD_CG_SUPPORT_HDP_SD;
1113
1114         return;
1115 }
1116
1117 static const struct amd_ip_funcs nv_common_ip_funcs = {
1118         .name = "nv_common",
1119         .early_init = nv_common_early_init,
1120         .late_init = nv_common_late_init,
1121         .sw_init = nv_common_sw_init,
1122         .sw_fini = nv_common_sw_fini,
1123         .hw_init = nv_common_hw_init,
1124         .hw_fini = nv_common_hw_fini,
1125         .suspend = nv_common_suspend,
1126         .resume = nv_common_resume,
1127         .is_idle = nv_common_is_idle,
1128         .wait_for_idle = nv_common_wait_for_idle,
1129         .soft_reset = nv_common_soft_reset,
1130         .set_clockgating_state = nv_common_set_clockgating_state,
1131         .set_powergating_state = nv_common_set_powergating_state,
1132         .get_clockgating_state = nv_common_get_clockgating_state,
1133 };