drivers/gpu/drm/amd/amdgpu/nv.c

   1 /*
   2  * Copyright 2019 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23 #include <linux/firmware.h>
  24 #include <linux/slab.h>
  25 #include <linux/module.h>
  26 #include <linux/pci.h>
  27
  28 #include <drm/amdgpu_drm.h>
  29
  30 #include "amdgpu.h"
  31 #include "amdgpu_atombios.h"
  32 #include "amdgpu_ih.h"
  33 #include "amdgpu_uvd.h"
  34 #include "amdgpu_vce.h"
  35 #include "amdgpu_ucode.h"
  36 #include "amdgpu_psp.h"
  37 #include "atom.h"
  38 #include "amd_pcie.h"
  39
  40 #include "gc/gc_10_1_0_offset.h"
  41 #include "gc/gc_10_1_0_sh_mask.h"
  42 #include "mp/mp_11_0_offset.h"
  43
  44 #include "soc15.h"
  45 #include "soc15_common.h"
  46 #include "gmc_v10_0.h"
  47 #include "gfxhub_v2_0.h"
  48 #include "mmhub_v2_0.h"
  49 #include "nbio_v2_3.h"
  50 #include "nbio_v7_2.h"
  51 #include "hdp_v5_0.h"
  52 #include "nv.h"
  53 #include "navi10_ih.h"
  54 #include "gfx_v10_0.h"
  55 #include "sdma_v5_0.h"
  56 #include "sdma_v5_2.h"
  57 #include "vcn_v2_0.h"
  58 #include "jpeg_v2_0.h"
  59 #include "vcn_v3_0.h"
  60 #include "jpeg_v3_0.h"
  61 #include "dce_virtual.h"
  62 #include "mes_v10_1.h"
  63 #include "mxgpu_nv.h"
  64 #include "smuio_v11_0.h"
  65 #include "smuio_v11_0_6.h"
  66
  67 static const struct amd_ip_funcs nv_common_ip_funcs;
  68
  69 /* Navi */
  70 static const struct amdgpu_video_codec_info nv_video_codecs_encode_array[] =
  71 {
  72         {
  73                 .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC,
  74                 .max_width = 4096,
  75                 .max_height = 2304,
  76                 .max_pixels_per_frame = 4096 * 2304,
  77                 .max_level = 0,
  78         },
  79         {
  80                 .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC,
  81                 .max_width = 4096,
  82                 .max_height = 2304,
  83                 .max_pixels_per_frame = 4096 * 2304,
  84                 .max_level = 0,
  85         },
  86 };
  87
  88 static const struct amdgpu_video_codecs nv_video_codecs_encode =
  89 {
  90         .codec_count = ARRAY_SIZE(nv_video_codecs_encode_array),
  91         .codec_array = nv_video_codecs_encode_array,
  92 };
  93
  94 /* Navi1x */
  95 static const struct amdgpu_video_codec_info nv_video_codecs_decode_array[] =
  96 {
  97         {
  98                 .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2,
  99                 .max_width = 4096,
 100                 .max_height = 4096,
 101                 .max_pixels_per_frame = 4096 * 4096,
 102                 .max_level = 3,
 103         },
 104         {
 105                 .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4,
 106                 .max_width = 4096,
 107                 .max_height = 4096,
 108                 .max_pixels_per_frame = 4096 * 4096,
 109                 .max_level = 5,
 110         },
 111         {
 112                 .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC,
 113                 .max_width = 4096,
 114                 .max_height = 4096,
 115                 .max_pixels_per_frame = 4096 * 4096,
 116                 .max_level = 52,
 117         },
 118         {
 119                 .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1,
 120                 .max_width = 4096,
 121                 .max_height = 4096,
 122                 .max_pixels_per_frame = 4096 * 4096,
 123                 .max_level = 4,
 124         },
 125         {
 126                 .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC,
 127                 .max_width = 8192,
 128                 .max_height = 4352,
 129                 .max_pixels_per_frame = 8192 * 4352,
 130                 .max_level = 186,
 131         },
 132         {
 133                 .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG,
 134                 .max_width = 4096,
 135                 .max_height = 4096,
 136                 .max_pixels_per_frame = 4096 * 4096,
 137                 .max_level = 0,
 138         },
 139         {
 140                 .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9,
 141                 .max_width = 8192,
 142                 .max_height = 4352,
 143                 .max_pixels_per_frame = 8192 * 4352,
 144                 .max_level = 0,
 145         },
 146 };
 147
 148 static const struct amdgpu_video_codecs nv_video_codecs_decode =
 149 {
 150         .codec_count = ARRAY_SIZE(nv_video_codecs_decode_array),
 151         .codec_array = nv_video_codecs_decode_array,
 152 };
 153
 154 /* Sienna Cichlid */
 155 static const struct amdgpu_video_codec_info sc_video_codecs_decode_array[] =
 156 {
 157         {
 158                 .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2,
 159                 .max_width = 4096,
 160                 .max_height = 4096,
 161                 .max_pixels_per_frame = 4096 * 4096,
 162                 .max_level = 3,
 163         },
 164         {
 165                 .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4,
 166                 .max_width = 4096,
 167                 .max_height = 4096,
 168                 .max_pixels_per_frame = 4096 * 4096,
 169                 .max_level = 5,
 170         },
 171         {
 172                 .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC,
 173                 .max_width = 4096,
 174                 .max_height = 4096,
 175                 .max_pixels_per_frame = 4096 * 4096,
 176                 .max_level = 52,
 177         },
 178         {
 179                 .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1,
 180                 .max_width = 4096,
 181                 .max_height = 4096,
 182                 .max_pixels_per_frame = 4096 * 4096,
 183                 .max_level = 4,
 184         },
 185         {
 186                 .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC,
 187                 .max_width = 8192,
 188                 .max_height = 4352,
 189                 .max_pixels_per_frame = 8192 * 4352,
 190                 .max_level = 186,
 191         },
 192         {
 193                 .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG,
 194                 .max_width = 4096,
 195                 .max_height = 4096,
 196                 .max_pixels_per_frame = 4096 * 4096,
 197                 .max_level = 0,
 198         },
 199         {
 200                 .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9,
 201                 .max_width = 8192,
 202                 .max_height = 4352,
 203                 .max_pixels_per_frame = 8192 * 4352,
 204                 .max_level = 0,
 205         },
 206         {
 207                 .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1,
 208                 .max_width = 8192,
 209                 .max_height = 4352,
 210                 .max_pixels_per_frame = 8192 * 4352,
 211                 .max_level = 0,
 212         },
 213 };
 214
 215 static const struct amdgpu_video_codecs sc_video_codecs_decode =
 216 {
 217         .codec_count = ARRAY_SIZE(sc_video_codecs_decode_array),
 218         .codec_array = sc_video_codecs_decode_array,
 219 };
 220
 221 /* SRIOV Sienna Cichlid, not const since data is controlled by host */
 222 static struct amdgpu_video_codec_info sriov_sc_video_codecs_encode_array[] =
 223 {
 224         {
 225                 .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC,
 226                 .max_width = 4096,
 227                 .max_height = 2304,
 228                 .max_pixels_per_frame = 4096 * 2304,
 229                 .max_level = 0,
 230         },
 231         {
 232                 .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC,
 233                 .max_width = 4096,
 234                 .max_height = 2304,
 235                 .max_pixels_per_frame = 4096 * 2304,
 236                 .max_level = 0,
 237         },
 238 };
 239
 240 static struct amdgpu_video_codec_info sriov_sc_video_codecs_decode_array[] =
 241 {
 242         {
 243                 .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2,
 244                 .max_width = 4096,
 245                 .max_height = 4096,
 246                 .max_pixels_per_frame = 4096 * 4096,
 247                 .max_level = 3,
 248         },
 249         {
 250                 .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4,
 251                 .max_width = 4096,
 252                 .max_height = 4096,
 253                 .max_pixels_per_frame = 4096 * 4096,
 254                 .max_level = 5,
 255         },
 256         {
 257                 .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC,
 258                 .max_width = 4096,
 259                 .max_height = 4096,
 260                 .max_pixels_per_frame = 4096 * 4096,
 261                 .max_level = 52,
 262         },
 263         {
 264                 .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1,
 265                 .max_width = 4096,
 266                 .max_height = 4096,
 267                 .max_pixels_per_frame = 4096 * 4096,
 268                 .max_level = 4,
 269         },
 270         {
 271                 .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC,
 272                 .max_width = 8192,
 273                 .max_height = 4352,
 274                 .max_pixels_per_frame = 8192 * 4352,
 275                 .max_level = 186,
 276         },
 277         {
 278                 .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG,
 279                 .max_width = 4096,
 280                 .max_height = 4096,
 281                 .max_pixels_per_frame = 4096 * 4096,
 282                 .max_level = 0,
 283         },
 284         {
 285                 .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9,
 286                 .max_width = 8192,
 287                 .max_height = 4352,
 288                 .max_pixels_per_frame = 8192 * 4352,
 289                 .max_level = 0,
 290         },
 291         {
 292                 .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1,
 293                 .max_width = 8192,
 294                 .max_height = 4352,
 295                 .max_pixels_per_frame = 8192 * 4352,
 296                 .max_level = 0,
 297         },
 298 };
 299
 300 static struct amdgpu_video_codecs sriov_sc_video_codecs_encode =
 301 {
 302         .codec_count = ARRAY_SIZE(sriov_sc_video_codecs_encode_array),
 303         .codec_array = sriov_sc_video_codecs_encode_array,
 304 };
 305
 306 static struct amdgpu_video_codecs sriov_sc_video_codecs_decode =
 307 {
 308         .codec_count = ARRAY_SIZE(sriov_sc_video_codecs_decode_array),
 309         .codec_array = sriov_sc_video_codecs_decode_array,
 310 };
 311
 312 static int nv_query_video_codecs(struct amdgpu_device *adev, bool encode,
 313                                  const struct amdgpu_video_codecs **codecs)
 314 {
 315         switch (adev->asic_type) {
 316         case CHIP_SIENNA_CICHLID:
 317                 if (amdgpu_sriov_vf(adev)) {
 318                         if (encode)
 319                                 *codecs = &sriov_sc_video_codecs_encode;
 320                         else
 321                                 *codecs = &sriov_sc_video_codecs_decode;
 322                 } else {
 323                         if (encode)
 324                                 *codecs = &nv_video_codecs_encode;
 325                         else
 326                                 *codecs = &sc_video_codecs_decode;
 327                 }
 328                 return 0;
 329         case CHIP_NAVY_FLOUNDER:
 330         case CHIP_DIMGREY_CAVEFISH:
 331         case CHIP_VANGOGH:
 332                 if (encode)
 333                         *codecs = &nv_video_codecs_encode;
 334                 else
 335                         *codecs = &sc_video_codecs_decode;
 336                 return 0;
 337         case CHIP_NAVI10:
 338         case CHIP_NAVI14:
 339         case CHIP_NAVI12:
 340                 if (encode)
 341                         *codecs = &nv_video_codecs_encode;
 342                 else
 343                         *codecs = &nv_video_codecs_decode;
 344                 return 0;
 345         default:
 346                 return -EINVAL;
 347         }
 348 }
 349
 350 /*
 351  * Indirect registers accessor
 352  */
 353 static u32 nv_pcie_rreg(struct amdgpu_device *adev, u32 reg)
 354 {
 355         unsigned long address, data;
 356         address = adev->nbio.funcs->get_pcie_index_offset(adev);
 357         data = adev->nbio.funcs->get_pcie_data_offset(adev);
 358
 359         return amdgpu_device_indirect_rreg(adev, address, data, reg);
 360 }
 361
 362 static void nv_pcie_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
 363 {
 364         unsigned long address, data;
 365
 366         address = adev->nbio.funcs->get_pcie_index_offset(adev);
 367         data = adev->nbio.funcs->get_pcie_data_offset(adev);
 368
 369         amdgpu_device_indirect_wreg(adev, address, data, reg, v);
 370 }
 371
 372 static u64 nv_pcie_rreg64(struct amdgpu_device *adev, u32 reg)
 373 {
 374         unsigned long address, data;
 375         address = adev->nbio.funcs->get_pcie_index_offset(adev);
 376         data = adev->nbio.funcs->get_pcie_data_offset(adev);
 377
 378         return amdgpu_device_indirect_rreg64(adev, address, data, reg);
 379 }
 380
 381 static u32 nv_pcie_port_rreg(struct amdgpu_device *adev, u32 reg)
 382 {
 383         unsigned long flags, address, data;
 384         u32 r;
 385         address = adev->nbio.funcs->get_pcie_port_index_offset(adev);
 386         data = adev->nbio.funcs->get_pcie_port_data_offset(adev);
 387
 388         spin_lock_irqsave(&adev->pcie_idx_lock, flags);
 389         WREG32(address, reg * 4);
 390         (void)RREG32(address);
 391         r = RREG32(data);
 392         spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
 393         return r;
 394 }
 395
 396 static void nv_pcie_wreg64(struct amdgpu_device *adev, u32 reg, u64 v)
 397 {
 398         unsigned long address, data;
 399
 400         address = adev->nbio.funcs->get_pcie_index_offset(adev);
 401         data = adev->nbio.funcs->get_pcie_data_offset(adev);
 402
 403         amdgpu_device_indirect_wreg64(adev, address, data, reg, v);
 404 }
 405
 406 static void nv_pcie_port_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
 407 {
 408         unsigned long flags, address, data;
 409
 410         address = adev->nbio.funcs->get_pcie_port_index_offset(adev);
 411         data = adev->nbio.funcs->get_pcie_port_data_offset(adev);
 412
 413         spin_lock_irqsave(&adev->pcie_idx_lock, flags);
 414         WREG32(address, reg * 4);
 415         (void)RREG32(address);
 416         WREG32(data, v);
 417         (void)RREG32(data);
 418         spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
 419 }
 420
 421 static u32 nv_didt_rreg(struct amdgpu_device *adev, u32 reg)
 422 {
 423         unsigned long flags, address, data;
 424         u32 r;
 425
 426         address = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_INDEX);
 427         data = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_DATA);
 428
 429         spin_lock_irqsave(&adev->didt_idx_lock, flags);
 430         WREG32(address, (reg));
 431         r = RREG32(data);
 432         spin_unlock_irqrestore(&adev->didt_idx_lock, flags);
 433         return r;
 434 }
 435
 436 static void nv_didt_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
 437 {
 438         unsigned long flags, address, data;
 439
 440         address = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_INDEX);
 441         data = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_DATA);
 442
 443         spin_lock_irqsave(&adev->didt_idx_lock, flags);
 444         WREG32(address, (reg));
 445         WREG32(data, (v));
 446         spin_unlock_irqrestore(&adev->didt_idx_lock, flags);
 447 }
 448
 449 static u32 nv_get_config_memsize(struct amdgpu_device *adev)
 450 {
 451         return adev->nbio.funcs->get_memsize(adev);
 452 }
 453
 454 static u32 nv_get_xclk(struct amdgpu_device *adev)
 455 {
 456         return adev->clock.spll.reference_freq;
 457 }
 458
 459
 460 void nv_grbm_select(struct amdgpu_device *adev,
 461                      u32 me, u32 pipe, u32 queue, u32 vmid)
 462 {
 463         u32 grbm_gfx_cntl = 0;
 464         grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, PIPEID, pipe);
 465         grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, MEID, me);
 466         grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, VMID, vmid);
 467         grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, QUEUEID, queue);
 468
 469         WREG32(SOC15_REG_OFFSET(GC, 0, mmGRBM_GFX_CNTL), grbm_gfx_cntl);
 470 }
 471
 472 static void nv_vga_set_state(struct amdgpu_device *adev, bool state)
 473 {
 474         /* todo */
 475 }
 476
 477 static bool nv_read_disabled_bios(struct amdgpu_device *adev)
 478 {
 479         /* todo */
 480         return false;
 481 }
 482
 483 static bool nv_read_bios_from_rom(struct amdgpu_device *adev,
 484                                   u8 *bios, u32 length_bytes)
 485 {
 486         u32 *dw_ptr;
 487         u32 i, length_dw;
 488         u32 rom_index_offset, rom_data_offset;
 489
 490         if (bios == NULL)
 491                 return false;
 492         if (length_bytes == 0)
 493                 return false;
 494         /* APU vbios image is part of sbios image */
 495         if (adev->flags & AMD_IS_APU)
 496                 return false;
 497
 498         dw_ptr = (u32 *)bios;
 499         length_dw = ALIGN(length_bytes, 4) / 4;
 500
 501         rom_index_offset =
 502                 adev->smuio.funcs->get_rom_index_offset(adev);
 503         rom_data_offset =
 504                 adev->smuio.funcs->get_rom_data_offset(adev);
 505
 506         /* set rom index to 0 */
 507         WREG32(rom_index_offset, 0);
 508         /* read out the rom data */
 509         for (i = 0; i < length_dw; i++)
 510                 dw_ptr[i] = RREG32(rom_data_offset);
 511
 512         return true;
 513 }
 514
 515 static struct soc15_allowed_register_entry nv_allowed_read_registers[] = {
 516         { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS)},
 517         { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS2)},
 518         { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE0)},
 519         { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE1)},
 520         { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE2)},
 521         { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE3)},
 522         { SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_STATUS_REG)},
 523         { SOC15_REG_ENTRY(SDMA1, 0, mmSDMA1_STATUS_REG)},
 524         { SOC15_REG_ENTRY(GC, 0, mmCP_STAT)},
 525         { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT1)},
 526         { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT2)},
 527         { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT3)},
 528         { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_BUSY_STAT)},
 529         { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_STALLED_STAT1)},
 530         { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_STATUS)},
 531         { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_BUSY_STAT)},
 532         { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_STALLED_STAT1)},
 533         { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_STATUS)},
 534         { SOC15_REG_ENTRY(GC, 0, mmGB_ADDR_CONFIG)},
 535 };
 536
 537 static uint32_t nv_read_indexed_register(struct amdgpu_device *adev, u32 se_num,
 538                                          u32 sh_num, u32 reg_offset)
 539 {
 540         uint32_t val;
 541
 542         mutex_lock(&adev->grbm_idx_mutex);
 543         if (se_num != 0xffffffff || sh_num != 0xffffffff)
 544                 amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff);
 545
 546         val = RREG32(reg_offset);
 547
 548         if (se_num != 0xffffffff || sh_num != 0xffffffff)
 549                 amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
 550         mutex_unlock(&adev->grbm_idx_mutex);
 551         return val;
 552 }
 553
 554 static uint32_t nv_get_register_value(struct amdgpu_device *adev,
 555                                       bool indexed, u32 se_num,
 556                                       u32 sh_num, u32 reg_offset)
 557 {
 558         if (indexed) {
 559                 return nv_read_indexed_register(adev, se_num, sh_num, reg_offset);
 560         } else {
 561                 if (reg_offset == SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG))
 562                         return adev->gfx.config.gb_addr_config;
 563                 return RREG32(reg_offset);
 564         }
 565 }
 566
 567 static int nv_read_register(struct amdgpu_device *adev, u32 se_num,
 568                             u32 sh_num, u32 reg_offset, u32 *value)
 569 {
 570         uint32_t i;
 571         struct soc15_allowed_register_entry  *en;
 572
 573         *value = 0;
 574         for (i = 0; i < ARRAY_SIZE(nv_allowed_read_registers); i++) {
 575                 en = &nv_allowed_read_registers[i];
 576                 if ((i == 7 && (adev->sdma.num_instances == 1)) || /* some asics don't have SDMA1 */
 577                     reg_offset !=
 578                     (adev->reg_offset[en->hwip][en->inst][en->seg] + en->reg_offset))
 579                         continue;
 580
 581                 *value = nv_get_register_value(adev,
 582                                                nv_allowed_read_registers[i].grbm_indexed,
 583                                                se_num, sh_num, reg_offset);
 584                 return 0;
 585         }
 586         return -EINVAL;
 587 }
 588
 589 static int nv_asic_mode2_reset(struct amdgpu_device *adev)
 590 {
 591         u32 i;
 592         int ret = 0;
 593
 594         amdgpu_atombios_scratch_regs_engine_hung(adev, true);
 595
 596         /* disable BM */
 597         pci_clear_master(adev->pdev);
 598
 599         amdgpu_device_cache_pci_state(adev->pdev);
 600
 601         ret = amdgpu_dpm_mode2_reset(adev);
 602         if (ret)
 603                 dev_err(adev->dev, "GPU mode2 reset failed\n");
 604
 605         amdgpu_device_load_pci_state(adev->pdev);
 606
 607         /* wait for asic to come out of reset */
 608         for (i = 0; i < adev->usec_timeout; i++) {
 609                 u32 memsize = adev->nbio.funcs->get_memsize(adev);
 610
 611                 if (memsize != 0xffffffff)
 612                         break;
 613                 udelay(1);
 614         }
 615
 616         amdgpu_atombios_scratch_regs_engine_hung(adev, false);
 617
 618         return ret;
 619 }
 620
 621 static enum amd_reset_method
 622 nv_asic_reset_method(struct amdgpu_device *adev)
 623 {
 624         if (amdgpu_reset_method == AMD_RESET_METHOD_MODE1 ||
 625             amdgpu_reset_method == AMD_RESET_METHOD_MODE2 ||
 626             amdgpu_reset_method == AMD_RESET_METHOD_BACO ||
 627             amdgpu_reset_method == AMD_RESET_METHOD_PCI)
 628                 return amdgpu_reset_method;
 629
 630         if (amdgpu_reset_method != -1)
 631                 dev_warn(adev->dev, "Specified reset method:%d isn't supported, using AUTO instead.\n",
 632                                   amdgpu_reset_method);
 633
 634         switch (adev->asic_type) {
 635         case CHIP_VANGOGH:
 636                 return AMD_RESET_METHOD_MODE2;
 637         case CHIP_SIENNA_CICHLID:
 638         case CHIP_NAVY_FLOUNDER:
 639         case CHIP_DIMGREY_CAVEFISH:
 640         case CHIP_BEIGE_GOBY:
 641                 return AMD_RESET_METHOD_MODE1;
 642         default:
 643                 if (amdgpu_dpm_is_baco_supported(adev))
 644                         return AMD_RESET_METHOD_BACO;
 645                 else
 646                         return AMD_RESET_METHOD_MODE1;
 647         }
 648 }
 649
 650 static int nv_asic_reset(struct amdgpu_device *adev)
 651 {
 652         int ret = 0;
 653
 654         switch (nv_asic_reset_method(adev)) {
 655         case AMD_RESET_METHOD_PCI:
 656                 dev_info(adev->dev, "PCI reset\n");
 657                 ret = amdgpu_device_pci_reset(adev);
 658                 break;
 659         case AMD_RESET_METHOD_BACO:
 660                 dev_info(adev->dev, "BACO reset\n");
 661                 ret = amdgpu_dpm_baco_reset(adev);
 662                 break;
 663         case AMD_RESET_METHOD_MODE2:
 664                 dev_info(adev->dev, "MODE2 reset\n");
 665                 ret = nv_asic_mode2_reset(adev);
 666                 break;
 667         default:
 668                 dev_info(adev->dev, "MODE1 reset\n");
 669                 ret = amdgpu_device_mode1_reset(adev);
 670                 break;
 671         }
 672
 673         return ret;
 674 }
 675
 676 static int nv_set_uvd_clocks(struct amdgpu_device *adev, u32 vclk, u32 dclk)
 677 {
 678         /* todo */
 679         return 0;
 680 }
 681
 682 static int nv_set_vce_clocks(struct amdgpu_device *adev, u32 evclk, u32 ecclk)
 683 {
 684         /* todo */
 685         return 0;
 686 }
 687
 688 static void nv_pcie_gen3_enable(struct amdgpu_device *adev)
 689 {
 690         if (pci_is_root_bus(adev->pdev->bus))
 691                 return;
 692
 693         if (amdgpu_pcie_gen2 == 0)
 694                 return;
 695
 696         if (!(adev->pm.pcie_gen_mask & (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 |
 697                                         CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3)))
 698                 return;
 699
 700         /* todo */
 701 }
 702
 703 static void nv_program_aspm(struct amdgpu_device *adev)
 704 {
 705         if (!amdgpu_aspm)
 706                 return;
 707
 708         if (!(adev->flags & AMD_IS_APU) &&
 709             (adev->nbio.funcs->program_aspm))
 710                 adev->nbio.funcs->program_aspm(adev);
 711
 712 }
 713
 714 static void nv_enable_doorbell_aperture(struct amdgpu_device *adev,
 715                                         bool enable)
 716 {
 717         adev->nbio.funcs->enable_doorbell_aperture(adev, enable);
 718         adev->nbio.funcs->enable_doorbell_selfring_aperture(adev, enable);
 719 }
 720
 721 static const struct amdgpu_ip_block_version nv_common_ip_block =
 722 {
 723         .type = AMD_IP_BLOCK_TYPE_COMMON,
 724         .major = 1,
 725         .minor = 0,
 726         .rev = 0,
 727         .funcs = &nv_common_ip_funcs,
 728 };
 729
 730 static bool nv_is_headless_sku(struct pci_dev *pdev)
 731 {
 732         if ((pdev->device == 0x731E &&
 733             (pdev->revision == 0xC6 || pdev->revision == 0xC7)) ||
 734             (pdev->device == 0x7340 && pdev->revision == 0xC9)  ||
 735             (pdev->device == 0x7360 && pdev->revision == 0xC7))
 736                 return true;
 737         return false;
 738 }
 739
 740 static int nv_reg_base_init(struct amdgpu_device *adev)
 741 {
 742         int r;
 743
 744         if (amdgpu_discovery) {
 745                 r = amdgpu_discovery_reg_base_init(adev);
 746                 if (r) {
 747                         DRM_WARN("failed to init reg base from ip discovery table, "
 748                                         "fallback to legacy init method\n");
 749                         goto legacy_init;
 750                 }
 751
 752                 amdgpu_discovery_harvest_ip(adev);
 753                 if (nv_is_headless_sku(adev->pdev)) {
 754                         adev->harvest_ip_mask |= AMD_HARVEST_IP_VCN_MASK;
 755                         adev->harvest_ip_mask |= AMD_HARVEST_IP_JPEG_MASK;
 756                 }
 757
 758                 return 0;
 759         }
 760
 761 legacy_init:
 762         switch (adev->asic_type) {
 763         case CHIP_NAVI10:
 764                 navi10_reg_base_init(adev);
 765                 break;
 766         case CHIP_NAVI14:
 767                 navi14_reg_base_init(adev);
 768                 break;
 769         case CHIP_NAVI12:
 770                 navi12_reg_base_init(adev);
 771                 break;
 772         case CHIP_SIENNA_CICHLID:
 773         case CHIP_NAVY_FLOUNDER:
 774                 sienna_cichlid_reg_base_init(adev);
 775                 break;
 776         case CHIP_VANGOGH:
 777                 vangogh_reg_base_init(adev);
 778                 break;
 779         case CHIP_DIMGREY_CAVEFISH:
 780                 dimgrey_cavefish_reg_base_init(adev);
 781                 break;
 782         case CHIP_BEIGE_GOBY:
 783                 beige_goby_reg_base_init(adev);
 784                 break;
 785         default:
 786                 return -EINVAL;
 787         }
 788
 789         return 0;
 790 }
 791
 792 void nv_set_virt_ops(struct amdgpu_device *adev)
 793 {
 794         adev->virt.ops = &xgpu_nv_virt_ops;
 795 }
 796
 797 int nv_set_ip_blocks(struct amdgpu_device *adev)
 798 {
 799         int r;
 800
 801         if (adev->flags & AMD_IS_APU) {
 802                 adev->nbio.funcs = &nbio_v7_2_funcs;
 803                 adev->nbio.hdp_flush_reg = &nbio_v7_2_hdp_flush_reg;
 804         } else {
 805                 adev->nbio.funcs = &nbio_v2_3_funcs;
 806                 adev->nbio.hdp_flush_reg = &nbio_v2_3_hdp_flush_reg;
 807         }
 808         adev->hdp.funcs = &hdp_v5_0_funcs;
 809
 810         if (adev->asic_type >= CHIP_SIENNA_CICHLID)
 811                 adev->smuio.funcs = &smuio_v11_0_6_funcs;
 812         else
 813                 adev->smuio.funcs = &smuio_v11_0_funcs;
 814
 815         if (adev->asic_type == CHIP_SIENNA_CICHLID)
 816                 adev->gmc.xgmi.supported = true;
 817
 818         /* Set IP register base before any HW register access */
 819         r = nv_reg_base_init(adev);
 820         if (r)
 821                 return r;
 822
 823         switch (adev->asic_type) {
 824         case CHIP_NAVI10:
 825         case CHIP_NAVI14:
 826                 amdgpu_device_ip_block_add(adev, &nv_common_ip_block);
 827                 amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block);
 828                 amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block);
 829                 amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block);
 830                 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP &&
 831                     !amdgpu_sriov_vf(adev))
 832                         amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);
 833                 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))
 834                         amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
 835 #if defined(CONFIG_DRM_AMD_DC)
 836                 else if (amdgpu_device_has_dc_support(adev))
 837                         amdgpu_device_ip_block_add(adev, &dm_ip_block);
 838 #endif
 839                 amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block);
 840                 amdgpu_device_ip_block_add(adev, &sdma_v5_0_ip_block);
 841                 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT &&
 842                     !amdgpu_sriov_vf(adev))
 843                         amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);
 844                 amdgpu_device_ip_block_add(adev, &vcn_v2_0_ip_block);
 845                 amdgpu_device_ip_block_add(adev, &jpeg_v2_0_ip_block);
 846                 if (adev->enable_mes)
 847                         amdgpu_device_ip_block_add(adev, &mes_v10_1_ip_block);
 848                 break;
 849         case CHIP_NAVI12:
 850                 amdgpu_device_ip_block_add(adev, &nv_common_ip_block);
 851                 amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block);
 852                 amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block);
 853                 amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block);
 854                 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)
 855                         amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);
 856                 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))
 857                         amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
 858 #if defined(CONFIG_DRM_AMD_DC)
 859                 else if (amdgpu_device_has_dc_support(adev))
 860                         amdgpu_device_ip_block_add(adev, &dm_ip_block);
 861 #endif
 862                 amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block);
 863                 amdgpu_device_ip_block_add(adev, &sdma_v5_0_ip_block);
 864                 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT &&
 865                     !amdgpu_sriov_vf(adev))
 866                         amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);
 867                 amdgpu_device_ip_block_add(adev, &vcn_v2_0_ip_block);
 868                 if (!amdgpu_sriov_vf(adev))
 869                         amdgpu_device_ip_block_add(adev, &jpeg_v2_0_ip_block);
 870                 break;
 871         case CHIP_SIENNA_CICHLID:
 872                 amdgpu_device_ip_block_add(adev, &nv_common_ip_block);
 873                 amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block);
 874                 amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block);
 875                 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP))
 876                         amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block);
 877                 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP &&
 878                     is_support_sw_smu(adev))
 879                         amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);
 880                 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))
 881                         amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
 882 #if defined(CONFIG_DRM_AMD_DC)
 883                 else if (amdgpu_device_has_dc_support(adev))
 884                         amdgpu_device_ip_block_add(adev, &dm_ip_block);
 885 #endif
 886                 amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block);
 887                 amdgpu_device_ip_block_add(adev, &sdma_v5_2_ip_block);
 888                 amdgpu_device_ip_block_add(adev, &vcn_v3_0_ip_block);
 889                 if (!amdgpu_sriov_vf(adev))
 890                         amdgpu_device_ip_block_add(adev, &jpeg_v3_0_ip_block);
 891                 if (adev->enable_mes)
 892                         amdgpu_device_ip_block_add(adev, &mes_v10_1_ip_block);
 893                 break;
 894         case CHIP_NAVY_FLOUNDER:
 895                 amdgpu_device_ip_block_add(adev, &nv_common_ip_block);
 896                 amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block);
 897                 amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block);
 898                 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP))
 899                         amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block);
 900                 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP &&
 901                     is_support_sw_smu(adev))
 902                         amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);
 903                 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))
 904                         amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
 905 #if defined(CONFIG_DRM_AMD_DC)
 906                 else if (amdgpu_device_has_dc_support(adev))
 907                         amdgpu_device_ip_block_add(adev, &dm_ip_block);
 908 #endif
 909                 amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block);
 910                 amdgpu_device_ip_block_add(adev, &sdma_v5_2_ip_block);
 911                 amdgpu_device_ip_block_add(adev, &vcn_v3_0_ip_block);
 912                 amdgpu_device_ip_block_add(adev, &jpeg_v3_0_ip_block);
 913                 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT &&
 914                     is_support_sw_smu(adev))
 915                         amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);
 916                 break;
 917         case CHIP_VANGOGH:
 918                 amdgpu_device_ip_block_add(adev, &nv_common_ip_block);
 919                 amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block);
 920                 amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block);
 921                 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP))
 922                         amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block);
 923                 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);
 924                 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))
 925                         amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
 926 #if defined(CONFIG_DRM_AMD_DC)
 927                 else if (amdgpu_device_has_dc_support(adev))
 928                         amdgpu_device_ip_block_add(adev, &dm_ip_block);
 929 #endif
 930                 amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block);
 931                 amdgpu_device_ip_block_add(adev, &sdma_v5_2_ip_block);
 932                 amdgpu_device_ip_block_add(adev, &vcn_v3_0_ip_block);
 933                 amdgpu_device_ip_block_add(adev, &jpeg_v3_0_ip_block);
 934                 break;
 935         case CHIP_DIMGREY_CAVEFISH:
 936                 amdgpu_device_ip_block_add(adev, &nv_common_ip_block);
 937                 amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block);
 938                 amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block);
 939                 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP))
 940                         amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block);
 941                 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP &&
 942                     is_support_sw_smu(adev))
 943                         amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);
 944                 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))
 945                         amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
 946 #if defined(CONFIG_DRM_AMD_DC)
 947                 else if (amdgpu_device_has_dc_support(adev))
 948                         amdgpu_device_ip_block_add(adev, &dm_ip_block);
 949 #endif
 950                 amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block);
 951                 amdgpu_device_ip_block_add(adev, &sdma_v5_2_ip_block);
 952                 amdgpu_device_ip_block_add(adev, &vcn_v3_0_ip_block);
 953                 amdgpu_device_ip_block_add(adev, &jpeg_v3_0_ip_block);
 954                 break;
 955         case CHIP_BEIGE_GOBY:
 956                 amdgpu_device_ip_block_add(adev, &nv_common_ip_block);
 957                 amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block);
 958                 amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block);
 959                 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP))
 960                         amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block);
 961                 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP &&
 962                     is_support_sw_smu(adev))
 963                         amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);
 964                 amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block);
 965                 amdgpu_device_ip_block_add(adev, &sdma_v5_2_ip_block);
 966                 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))
 967                         amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
 968                 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT &&
 969                     is_support_sw_smu(adev))
 970                         amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);
 971                 amdgpu_device_ip_block_add(adev, &vcn_v3_0_ip_block);
 972                 break;
 973         default:
 974                 return -EINVAL;
 975         }
 976
 977         return 0;
 978 }
 979
 980 static uint32_t nv_get_rev_id(struct amdgpu_device *adev)
 981 {
 982         return adev->nbio.funcs->get_rev_id(adev);
 983 }
 984
 985 static bool nv_need_full_reset(struct amdgpu_device *adev)
 986 {
 987         return true;
 988 }
 989
 990 static bool nv_need_reset_on_init(struct amdgpu_device *adev)
 991 {
 992         u32 sol_reg;
 993
 994         if (adev->flags & AMD_IS_APU)
 995                 return false;
 996
 997         /* Check sOS sign of life register to confirm sys driver and sOS
 998          * are already been loaded.
 999          */
1000         sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81);
1001         if (sol_reg)
1002                 return true;
1003
1004         return false;
1005 }
1006
1007 static uint64_t nv_get_pcie_replay_count(struct amdgpu_device *adev)
1008 {
1009
1010         /* TODO
1011          * dummy implement for pcie_replay_count sysfs interface
1012          * */
1013
1014         return 0;
1015 }
1016
1017 static void nv_init_doorbell_index(struct amdgpu_device *adev)
1018 {
1019         adev->doorbell_index.kiq = AMDGPU_NAVI10_DOORBELL_KIQ;
1020         adev->doorbell_index.mec_ring0 = AMDGPU_NAVI10_DOORBELL_MEC_RING0;
1021         adev->doorbell_index.mec_ring1 = AMDGPU_NAVI10_DOORBELL_MEC_RING1;
1022         adev->doorbell_index.mec_ring2 = AMDGPU_NAVI10_DOORBELL_MEC_RING2;
1023         adev->doorbell_index.mec_ring3 = AMDGPU_NAVI10_DOORBELL_MEC_RING3;
1024         adev->doorbell_index.mec_ring4 = AMDGPU_NAVI10_DOORBELL_MEC_RING4;
1025         adev->doorbell_index.mec_ring5 = AMDGPU_NAVI10_DOORBELL_MEC_RING5;
1026         adev->doorbell_index.mec_ring6 = AMDGPU_NAVI10_DOORBELL_MEC_RING6;
1027         adev->doorbell_index.mec_ring7 = AMDGPU_NAVI10_DOORBELL_MEC_RING7;
1028         adev->doorbell_index.userqueue_start = AMDGPU_NAVI10_DOORBELL_USERQUEUE_START;
1029         adev->doorbell_index.userqueue_end = AMDGPU_NAVI10_DOORBELL_USERQUEUE_END;
1030         adev->doorbell_index.gfx_ring0 = AMDGPU_NAVI10_DOORBELL_GFX_RING0;
1031         adev->doorbell_index.gfx_ring1 = AMDGPU_NAVI10_DOORBELL_GFX_RING1;
1032         adev->doorbell_index.mes_ring = AMDGPU_NAVI10_DOORBELL_MES_RING;
1033         adev->doorbell_index.sdma_engine[0] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE0;
1034         adev->doorbell_index.sdma_engine[1] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE1;
1035         adev->doorbell_index.sdma_engine[2] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE2;
1036         adev->doorbell_index.sdma_engine[3] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE3;
1037         adev->doorbell_index.ih = AMDGPU_NAVI10_DOORBELL_IH;
1038         adev->doorbell_index.vcn.vcn_ring0_1 = AMDGPU_NAVI10_DOORBELL64_VCN0_1;
1039         adev->doorbell_index.vcn.vcn_ring2_3 = AMDGPU_NAVI10_DOORBELL64_VCN2_3;
1040         adev->doorbell_index.vcn.vcn_ring4_5 = AMDGPU_NAVI10_DOORBELL64_VCN4_5;
1041         adev->doorbell_index.vcn.vcn_ring6_7 = AMDGPU_NAVI10_DOORBELL64_VCN6_7;
1042         adev->doorbell_index.first_non_cp = AMDGPU_NAVI10_DOORBELL64_FIRST_NON_CP;
1043         adev->doorbell_index.last_non_cp = AMDGPU_NAVI10_DOORBELL64_LAST_NON_CP;
1044
1045         adev->doorbell_index.max_assignment = AMDGPU_NAVI10_DOORBELL_MAX_ASSIGNMENT << 1;
1046         adev->doorbell_index.sdma_doorbell_range = 20;
1047 }
1048
1049 static void nv_pre_asic_init(struct amdgpu_device *adev)
1050 {
1051 }
1052
1053 static int nv_update_umd_stable_pstate(struct amdgpu_device *adev,
1054                                        bool enter)
1055 {
1056         if (enter)
1057                 amdgpu_gfx_rlc_enter_safe_mode(adev);
1058         else
1059                 amdgpu_gfx_rlc_exit_safe_mode(adev);
1060
1061         if (adev->gfx.funcs->update_perfmon_mgcg)
1062                 adev->gfx.funcs->update_perfmon_mgcg(adev, !enter);
1063
1064         if (!(adev->flags & AMD_IS_APU) &&
1065             (adev->nbio.funcs->enable_aspm))
1066                 adev->nbio.funcs->enable_aspm(adev, !enter);
1067
1068         return 0;
1069 }
1070
1071 static const struct amdgpu_asic_funcs nv_asic_funcs =
1072 {
1073         .read_disabled_bios = &nv_read_disabled_bios,
1074         .read_bios_from_rom = &nv_read_bios_from_rom,
1075         .read_register = &nv_read_register,
1076         .reset = &nv_asic_reset,
1077         .reset_method = &nv_asic_reset_method,
1078         .set_vga_state = &nv_vga_set_state,
1079         .get_xclk = &nv_get_xclk,
1080         .set_uvd_clocks = &nv_set_uvd_clocks,
1081         .set_vce_clocks = &nv_set_vce_clocks,
1082         .get_config_memsize = &nv_get_config_memsize,
1083         .init_doorbell_index = &nv_init_doorbell_index,
1084         .need_full_reset = &nv_need_full_reset,
1085         .need_reset_on_init = &nv_need_reset_on_init,
1086         .get_pcie_replay_count = &nv_get_pcie_replay_count,
1087         .supports_baco = &amdgpu_dpm_is_baco_supported,
1088         .pre_asic_init = &nv_pre_asic_init,
1089         .update_umd_stable_pstate = &nv_update_umd_stable_pstate,
1090         .query_video_codecs = &nv_query_video_codecs,
1091 };
1092
1093 static int nv_common_early_init(void *handle)
1094 {
1095 #define MMIO_REG_HOLE_OFFSET (0x80000 - PAGE_SIZE)
1096         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1097
1098         adev->rmmio_remap.reg_offset = MMIO_REG_HOLE_OFFSET;
1099         adev->rmmio_remap.bus_addr = adev->rmmio_base + MMIO_REG_HOLE_OFFSET;
1100         adev->smc_rreg = NULL;
1101         adev->smc_wreg = NULL;
1102         adev->pcie_rreg = &nv_pcie_rreg;
1103         adev->pcie_wreg = &nv_pcie_wreg;
1104         adev->pcie_rreg64 = &nv_pcie_rreg64;
1105         adev->pcie_wreg64 = &nv_pcie_wreg64;
1106         adev->pciep_rreg = &nv_pcie_port_rreg;
1107         adev->pciep_wreg = &nv_pcie_port_wreg;
1108
1109         /* TODO: will add them during VCN v2 implementation */
1110         adev->uvd_ctx_rreg = NULL;
1111         adev->uvd_ctx_wreg = NULL;
1112
1113         adev->didt_rreg = &nv_didt_rreg;
1114         adev->didt_wreg = &nv_didt_wreg;
1115
1116         adev->asic_funcs = &nv_asic_funcs;
1117
1118         adev->rev_id = nv_get_rev_id(adev);
1119         adev->external_rev_id = 0xff;
1120         switch (adev->asic_type) {
1121         case CHIP_NAVI10:
1122                 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
1123                         AMD_CG_SUPPORT_GFX_CGCG |
1124                         AMD_CG_SUPPORT_IH_CG |
1125                         AMD_CG_SUPPORT_HDP_MGCG |
1126                         AMD_CG_SUPPORT_HDP_LS |
1127                         AMD_CG_SUPPORT_SDMA_MGCG |
1128                         AMD_CG_SUPPORT_SDMA_LS |
1129                         AMD_CG_SUPPORT_MC_MGCG |
1130                         AMD_CG_SUPPORT_MC_LS |
1131                         AMD_CG_SUPPORT_ATHUB_MGCG |
1132                         AMD_CG_SUPPORT_ATHUB_LS |
1133                         AMD_CG_SUPPORT_VCN_MGCG |
1134                         AMD_CG_SUPPORT_JPEG_MGCG |
1135                         AMD_CG_SUPPORT_BIF_MGCG |
1136                         AMD_CG_SUPPORT_BIF_LS;
1137                 adev->pg_flags = AMD_PG_SUPPORT_VCN |
1138                         AMD_PG_SUPPORT_VCN_DPG |
1139                         AMD_PG_SUPPORT_JPEG |
1140                         AMD_PG_SUPPORT_ATHUB;
1141                 adev->external_rev_id = adev->rev_id + 0x1;
1142                 break;
1143         case CHIP_NAVI14:
1144                 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
1145                         AMD_CG_SUPPORT_GFX_CGCG |
1146                         AMD_CG_SUPPORT_IH_CG |
1147                         AMD_CG_SUPPORT_HDP_MGCG |
1148                         AMD_CG_SUPPORT_HDP_LS |
1149                         AMD_CG_SUPPORT_SDMA_MGCG |
1150                         AMD_CG_SUPPORT_SDMA_LS |
1151                         AMD_CG_SUPPORT_MC_MGCG |
1152                         AMD_CG_SUPPORT_MC_LS |
1153                         AMD_CG_SUPPORT_ATHUB_MGCG |
1154                         AMD_CG_SUPPORT_ATHUB_LS |
1155                         AMD_CG_SUPPORT_VCN_MGCG |
1156                         AMD_CG_SUPPORT_JPEG_MGCG |
1157                         AMD_CG_SUPPORT_BIF_MGCG |
1158                         AMD_CG_SUPPORT_BIF_LS;
1159                 adev->pg_flags = AMD_PG_SUPPORT_VCN |
1160                         AMD_PG_SUPPORT_JPEG |
1161                         AMD_PG_SUPPORT_VCN_DPG;
1162                 adev->external_rev_id = adev->rev_id + 20;
1163                 break;
1164         case CHIP_NAVI12:
1165                 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
1166                         AMD_CG_SUPPORT_GFX_MGLS |
1167                         AMD_CG_SUPPORT_GFX_CGCG |
1168                         AMD_CG_SUPPORT_GFX_CP_LS |
1169                         AMD_CG_SUPPORT_GFX_RLC_LS |
1170                         AMD_CG_SUPPORT_IH_CG |
1171                         AMD_CG_SUPPORT_HDP_MGCG |
1172                         AMD_CG_SUPPORT_HDP_LS |
1173                         AMD_CG_SUPPORT_SDMA_MGCG |
1174                         AMD_CG_SUPPORT_SDMA_LS |
1175                         AMD_CG_SUPPORT_MC_MGCG |
1176                         AMD_CG_SUPPORT_MC_LS |
1177                         AMD_CG_SUPPORT_ATHUB_MGCG |
1178                         AMD_CG_SUPPORT_ATHUB_LS |
1179                         AMD_CG_SUPPORT_VCN_MGCG |
1180                         AMD_CG_SUPPORT_JPEG_MGCG;
1181                 adev->pg_flags = AMD_PG_SUPPORT_VCN |
1182                         AMD_PG_SUPPORT_VCN_DPG |
1183                         AMD_PG_SUPPORT_JPEG |
1184                         AMD_PG_SUPPORT_ATHUB;
1185                 /* guest vm gets 0xffffffff when reading RCC_DEV0_EPF0_STRAP0,
1186                  * as a consequence, the rev_id and external_rev_id are wrong.
1187                  * workaround it by hardcoding rev_id to 0 (default value).
1188                  */
1189                 if (amdgpu_sriov_vf(adev))
1190                         adev->rev_id = 0;
1191                 adev->external_rev_id = adev->rev_id + 0xa;
1192                 break;
1193         case CHIP_SIENNA_CICHLID:
1194                 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
1195                         AMD_CG_SUPPORT_GFX_CGCG |
1196                         AMD_CG_SUPPORT_GFX_CGLS |
1197                         AMD_CG_SUPPORT_GFX_3D_CGCG |
1198                         AMD_CG_SUPPORT_MC_MGCG |
1199                         AMD_CG_SUPPORT_VCN_MGCG |
1200                         AMD_CG_SUPPORT_JPEG_MGCG |
1201                         AMD_CG_SUPPORT_HDP_MGCG |
1202                         AMD_CG_SUPPORT_HDP_LS |
1203                         AMD_CG_SUPPORT_IH_CG |
1204                         AMD_CG_SUPPORT_MC_LS;
1205                 adev->pg_flags = AMD_PG_SUPPORT_VCN |
1206                         AMD_PG_SUPPORT_VCN_DPG |
1207                         AMD_PG_SUPPORT_JPEG |
1208                         AMD_PG_SUPPORT_ATHUB |
1209                         AMD_PG_SUPPORT_MMHUB;
1210                 if (amdgpu_sriov_vf(adev)) {
1211                         /* hypervisor control CG and PG enablement */
1212                         adev->cg_flags = 0;
1213                         adev->pg_flags = 0;
1214                 }
1215                 adev->external_rev_id = adev->rev_id + 0x28;
1216                 break;
1217         case CHIP_NAVY_FLOUNDER:
1218                 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
1219                         AMD_CG_SUPPORT_GFX_CGCG |
1220                         AMD_CG_SUPPORT_GFX_CGLS |
1221                         AMD_CG_SUPPORT_GFX_3D_CGCG |
1222                         AMD_CG_SUPPORT_VCN_MGCG |
1223                         AMD_CG_SUPPORT_JPEG_MGCG |
1224                         AMD_CG_SUPPORT_MC_MGCG |
1225                         AMD_CG_SUPPORT_MC_LS |
1226                         AMD_CG_SUPPORT_HDP_MGCG |
1227                         AMD_CG_SUPPORT_HDP_LS |
1228                         AMD_CG_SUPPORT_IH_CG;
1229                 adev->pg_flags = AMD_PG_SUPPORT_VCN |
1230                         AMD_PG_SUPPORT_VCN_DPG |
1231                         AMD_PG_SUPPORT_JPEG |
1232                         AMD_PG_SUPPORT_ATHUB |
1233                         AMD_PG_SUPPORT_MMHUB;
1234                 adev->external_rev_id = adev->rev_id + 0x32;
1235                 break;
1236
1237         case CHIP_VANGOGH:
1238                 adev->apu_flags |= AMD_APU_IS_VANGOGH;
1239                 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
1240                         AMD_CG_SUPPORT_GFX_MGLS |
1241                         AMD_CG_SUPPORT_GFX_CP_LS |
1242                         AMD_CG_SUPPORT_GFX_RLC_LS |
1243                         AMD_CG_SUPPORT_GFX_CGCG |
1244                         AMD_CG_SUPPORT_GFX_CGLS |
1245                         AMD_CG_SUPPORT_GFX_3D_CGCG |
1246                         AMD_CG_SUPPORT_GFX_3D_CGLS |
1247                         AMD_CG_SUPPORT_MC_MGCG |
1248                         AMD_CG_SUPPORT_MC_LS |
1249                         AMD_CG_SUPPORT_GFX_FGCG |
1250                         AMD_CG_SUPPORT_VCN_MGCG |
1251                         AMD_CG_SUPPORT_SDMA_MGCG |
1252                         AMD_CG_SUPPORT_SDMA_LS |
1253                         AMD_CG_SUPPORT_JPEG_MGCG;
1254                 adev->pg_flags = AMD_PG_SUPPORT_GFX_PG |
1255                         AMD_PG_SUPPORT_VCN |
1256                         AMD_PG_SUPPORT_VCN_DPG |
1257                         AMD_PG_SUPPORT_JPEG;
1258                 if (adev->apu_flags & AMD_APU_IS_VANGOGH)
1259                         adev->external_rev_id = adev->rev_id + 0x01;
1260                 break;
1261         case CHIP_DIMGREY_CAVEFISH:
1262                 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
1263                         AMD_CG_SUPPORT_GFX_CGCG |
1264                         AMD_CG_SUPPORT_GFX_CGLS |
1265                         AMD_CG_SUPPORT_GFX_3D_CGCG |
1266                         AMD_CG_SUPPORT_VCN_MGCG |
1267                         AMD_CG_SUPPORT_JPEG_MGCG |
1268                         AMD_CG_SUPPORT_MC_MGCG |
1269                         AMD_CG_SUPPORT_MC_LS |
1270                         AMD_CG_SUPPORT_HDP_MGCG |
1271                         AMD_CG_SUPPORT_HDP_LS |
1272                         AMD_CG_SUPPORT_IH_CG;
1273                 adev->pg_flags = AMD_PG_SUPPORT_VCN |
1274                         AMD_PG_SUPPORT_VCN_DPG |
1275                         AMD_PG_SUPPORT_JPEG |
1276                         AMD_PG_SUPPORT_ATHUB |
1277                         AMD_PG_SUPPORT_MMHUB;
1278                 adev->external_rev_id = adev->rev_id + 0x3c;
1279                 break;
1280         case CHIP_BEIGE_GOBY:
1281                 adev->cg_flags = 0;
1282                 adev->pg_flags = AMD_PG_SUPPORT_VCN |
1283                         AMD_PG_SUPPORT_VCN_DPG;
1284                 adev->external_rev_id = adev->rev_id + 0x46;
1285                 break;
1286         default:
1287                 /* FIXME: not supported yet */
1288                 return -EINVAL;
1289         }
1290
1291         if (adev->harvest_ip_mask & AMD_HARVEST_IP_VCN_MASK)
1292                 adev->pg_flags &= ~(AMD_PG_SUPPORT_VCN |
1293                                     AMD_PG_SUPPORT_VCN_DPG |
1294                                     AMD_PG_SUPPORT_JPEG);
1295
1296         if (amdgpu_sriov_vf(adev)) {
1297                 amdgpu_virt_init_setting(adev);
1298                 xgpu_nv_mailbox_set_irq_funcs(adev);
1299         }
1300
1301         return 0;
1302 }
1303
1304 static int nv_common_late_init(void *handle)
1305 {
1306         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1307
1308         if (amdgpu_sriov_vf(adev)) {
1309                 xgpu_nv_mailbox_get_irq(adev);
1310                 amdgpu_virt_update_sriov_video_codec(adev,
1311                                 sriov_sc_video_codecs_encode_array, ARRAY_SIZE(sriov_sc_video_codecs_encode_array),
1312                                 sriov_sc_video_codecs_decode_array, ARRAY_SIZE(sriov_sc_video_codecs_decode_array));
1313         }
1314
1315         return 0;
1316 }
1317
1318 static int nv_common_sw_init(void *handle)
1319 {
1320         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1321
1322         if (amdgpu_sriov_vf(adev))
1323                 xgpu_nv_mailbox_add_irq_id(adev);
1324
1325         return 0;
1326 }
1327
1328 static int nv_common_sw_fini(void *handle)
1329 {
1330         return 0;
1331 }
1332
1333 static int nv_common_hw_init(void *handle)
1334 {
1335         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1336
1337         /* enable pcie gen2/3 link */
1338         nv_pcie_gen3_enable(adev);
1339         /* enable aspm */
1340         nv_program_aspm(adev);
1341         /* setup nbio registers */
1342         adev->nbio.funcs->init_registers(adev);
1343         /* remap HDP registers to a hole in mmio space,
1344          * for the purpose of expose those registers
1345          * to process space
1346          */
1347         if (adev->nbio.funcs->remap_hdp_registers)
1348                 adev->nbio.funcs->remap_hdp_registers(adev);
1349         /* enable the doorbell aperture */
1350         nv_enable_doorbell_aperture(adev, true);
1351
1352         return 0;
1353 }
1354
1355 static int nv_common_hw_fini(void *handle)
1356 {
1357         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1358
1359         /* disable the doorbell aperture */
1360         nv_enable_doorbell_aperture(adev, false);
1361
1362         return 0;
1363 }
1364
1365 static int nv_common_suspend(void *handle)
1366 {
1367         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1368
1369         return nv_common_hw_fini(adev);
1370 }
1371
1372 static int nv_common_resume(void *handle)
1373 {
1374         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1375
1376         return nv_common_hw_init(adev);
1377 }
1378
1379 static bool nv_common_is_idle(void *handle)
1380 {
1381         return true;
1382 }
1383
1384 static int nv_common_wait_for_idle(void *handle)
1385 {
1386         return 0;
1387 }
1388
1389 static int nv_common_soft_reset(void *handle)
1390 {
1391         return 0;
1392 }
1393
1394 static int nv_common_set_clockgating_state(void *handle,
1395                                            enum amd_clockgating_state state)
1396 {
1397         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1398
1399         if (amdgpu_sriov_vf(adev))
1400                 return 0;
1401
1402         switch (adev->asic_type) {
1403         case CHIP_NAVI10:
1404         case CHIP_NAVI14:
1405         case CHIP_NAVI12:
1406         case CHIP_SIENNA_CICHLID:
1407         case CHIP_NAVY_FLOUNDER:
1408         case CHIP_DIMGREY_CAVEFISH:
1409         case CHIP_BEIGE_GOBY:
1410                 adev->nbio.funcs->update_medium_grain_clock_gating(adev,
1411                                 state == AMD_CG_STATE_GATE);
1412                 adev->nbio.funcs->update_medium_grain_light_sleep(adev,
1413                                 state == AMD_CG_STATE_GATE);
1414                 adev->hdp.funcs->update_clock_gating(adev,
1415                                 state == AMD_CG_STATE_GATE);
1416                 adev->smuio.funcs->update_rom_clock_gating(adev,
1417                                 state == AMD_CG_STATE_GATE);
1418                 break;
1419         default:
1420                 break;
1421         }
1422         return 0;
1423 }
1424
1425 static int nv_common_set_powergating_state(void *handle,
1426                                            enum amd_powergating_state state)
1427 {
1428         /* TODO */
1429         return 0;
1430 }
1431
1432 static void nv_common_get_clockgating_state(void *handle, u32 *flags)
1433 {
1434         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1435
1436         if (amdgpu_sriov_vf(adev))
1437                 *flags = 0;
1438
1439         adev->nbio.funcs->get_clockgating_state(adev, flags);
1440
1441         adev->hdp.funcs->get_clock_gating_state(adev, flags);
1442
1443         adev->smuio.funcs->get_clock_gating_state(adev, flags);
1444
1445         return;
1446 }
1447
1448 static const struct amd_ip_funcs nv_common_ip_funcs = {
1449         .name = "nv_common",
1450         .early_init = nv_common_early_init,
1451         .late_init = nv_common_late_init,
1452         .sw_init = nv_common_sw_init,
1453         .sw_fini = nv_common_sw_fini,
1454         .hw_init = nv_common_hw_init,
1455         .hw_fini = nv_common_hw_fini,
1456         .suspend = nv_common_suspend,
1457         .resume = nv_common_resume,
1458         .is_idle = nv_common_is_idle,
1459         .wait_for_idle = nv_common_wait_for_idle,
1460         .soft_reset = nv_common_soft_reset,
1461         .set_clockgating_state = nv_common_set_clockgating_state,
1462         .set_powergating_state = nv_common_set_powergating_state,
1463         .get_clockgating_state = nv_common_get_clockgating_state,
1464 };