2 * Copyright 2019 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
23 #include <linux/firmware.h>
24 #include <linux/slab.h>
25 #include <linux/module.h>
26 #include <linux/pci.h>
28 #include <drm/amdgpu_drm.h>
31 #include "amdgpu_atombios.h"
32 #include "amdgpu_ih.h"
33 #include "amdgpu_uvd.h"
34 #include "amdgpu_vce.h"
35 #include "amdgpu_ucode.h"
36 #include "amdgpu_psp.h"
40 #include "gc/gc_10_1_0_offset.h"
41 #include "gc/gc_10_1_0_sh_mask.h"
42 #include "mp/mp_11_0_offset.h"
45 #include "soc15_common.h"
46 #include "gmc_v10_0.h"
47 #include "gfxhub_v2_0.h"
48 #include "mmhub_v2_0.h"
49 #include "nbio_v2_3.h"
50 #include "nbio_v7_2.h"
53 #include "navi10_ih.h"
54 #include "gfx_v10_0.h"
55 #include "sdma_v5_0.h"
56 #include "sdma_v5_2.h"
58 #include "jpeg_v2_0.h"
60 #include "jpeg_v3_0.h"
61 #include "dce_virtual.h"
62 #include "mes_v10_1.h"
64 #include "smuio_v11_0.h"
65 #include "smuio_v11_0_6.h"
67 static const struct amd_ip_funcs nv_common_ip_funcs;
70 static const struct amdgpu_video_codec_info nv_video_codecs_encode_array[] =
73 .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC,
76 .max_pixels_per_frame = 4096 * 2304,
80 .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC,
83 .max_pixels_per_frame = 4096 * 2304,
88 static const struct amdgpu_video_codecs nv_video_codecs_encode =
90 .codec_count = ARRAY_SIZE(nv_video_codecs_encode_array),
91 .codec_array = nv_video_codecs_encode_array,
95 static const struct amdgpu_video_codec_info nv_video_codecs_decode_array[] =
98 .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2,
101 .max_pixels_per_frame = 4096 * 4096,
105 .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4,
108 .max_pixels_per_frame = 4096 * 4096,
112 .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC,
115 .max_pixels_per_frame = 4096 * 4096,
119 .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1,
122 .max_pixels_per_frame = 4096 * 4096,
126 .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC,
129 .max_pixels_per_frame = 8192 * 4352,
133 .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG,
136 .max_pixels_per_frame = 4096 * 4096,
140 .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9,
143 .max_pixels_per_frame = 8192 * 4352,
148 static const struct amdgpu_video_codecs nv_video_codecs_decode =
150 .codec_count = ARRAY_SIZE(nv_video_codecs_decode_array),
151 .codec_array = nv_video_codecs_decode_array,
155 static const struct amdgpu_video_codec_info sc_video_codecs_decode_array[] =
158 .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2,
161 .max_pixels_per_frame = 4096 * 4096,
165 .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4,
168 .max_pixels_per_frame = 4096 * 4096,
172 .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC,
175 .max_pixels_per_frame = 4096 * 4096,
179 .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1,
182 .max_pixels_per_frame = 4096 * 4096,
186 .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC,
189 .max_pixels_per_frame = 8192 * 4352,
193 .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG,
196 .max_pixels_per_frame = 4096 * 4096,
200 .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9,
203 .max_pixels_per_frame = 8192 * 4352,
207 .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1,
210 .max_pixels_per_frame = 8192 * 4352,
215 static const struct amdgpu_video_codecs sc_video_codecs_decode =
217 .codec_count = ARRAY_SIZE(sc_video_codecs_decode_array),
218 .codec_array = sc_video_codecs_decode_array,
221 /* SRIOV Sienna Cichlid, not const since data is controlled by host */
222 static struct amdgpu_video_codec_info sriov_sc_video_codecs_encode_array[] =
225 .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC,
228 .max_pixels_per_frame = 4096 * 2304,
232 .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC,
235 .max_pixels_per_frame = 4096 * 2304,
240 static struct amdgpu_video_codec_info sriov_sc_video_codecs_decode_array[] =
243 .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2,
246 .max_pixels_per_frame = 4096 * 4096,
250 .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4,
253 .max_pixels_per_frame = 4096 * 4096,
257 .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC,
260 .max_pixels_per_frame = 4096 * 4096,
264 .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1,
267 .max_pixels_per_frame = 4096 * 4096,
271 .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC,
274 .max_pixels_per_frame = 8192 * 4352,
278 .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG,
281 .max_pixels_per_frame = 4096 * 4096,
285 .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9,
288 .max_pixels_per_frame = 8192 * 4352,
292 .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1,
295 .max_pixels_per_frame = 8192 * 4352,
300 static struct amdgpu_video_codecs sriov_sc_video_codecs_encode =
302 .codec_count = ARRAY_SIZE(sriov_sc_video_codecs_encode_array),
303 .codec_array = sriov_sc_video_codecs_encode_array,
306 static struct amdgpu_video_codecs sriov_sc_video_codecs_decode =
308 .codec_count = ARRAY_SIZE(sriov_sc_video_codecs_decode_array),
309 .codec_array = sriov_sc_video_codecs_decode_array,
312 static int nv_query_video_codecs(struct amdgpu_device *adev, bool encode,
313 const struct amdgpu_video_codecs **codecs)
315 switch (adev->asic_type) {
316 case CHIP_SIENNA_CICHLID:
317 if (amdgpu_sriov_vf(adev)) {
319 *codecs = &sriov_sc_video_codecs_encode;
321 *codecs = &sriov_sc_video_codecs_decode;
324 *codecs = &nv_video_codecs_encode;
326 *codecs = &sc_video_codecs_decode;
329 case CHIP_NAVY_FLOUNDER:
330 case CHIP_DIMGREY_CAVEFISH:
333 *codecs = &nv_video_codecs_encode;
335 *codecs = &sc_video_codecs_decode;
341 *codecs = &nv_video_codecs_encode;
343 *codecs = &nv_video_codecs_decode;
351 * Indirect registers accessor
353 static u32 nv_pcie_rreg(struct amdgpu_device *adev, u32 reg)
355 unsigned long address, data;
356 address = adev->nbio.funcs->get_pcie_index_offset(adev);
357 data = adev->nbio.funcs->get_pcie_data_offset(adev);
359 return amdgpu_device_indirect_rreg(adev, address, data, reg);
362 static void nv_pcie_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
364 unsigned long address, data;
366 address = adev->nbio.funcs->get_pcie_index_offset(adev);
367 data = adev->nbio.funcs->get_pcie_data_offset(adev);
369 amdgpu_device_indirect_wreg(adev, address, data, reg, v);
372 static u64 nv_pcie_rreg64(struct amdgpu_device *adev, u32 reg)
374 unsigned long address, data;
375 address = adev->nbio.funcs->get_pcie_index_offset(adev);
376 data = adev->nbio.funcs->get_pcie_data_offset(adev);
378 return amdgpu_device_indirect_rreg64(adev, address, data, reg);
381 static u32 nv_pcie_port_rreg(struct amdgpu_device *adev, u32 reg)
383 unsigned long flags, address, data;
385 address = adev->nbio.funcs->get_pcie_port_index_offset(adev);
386 data = adev->nbio.funcs->get_pcie_port_data_offset(adev);
388 spin_lock_irqsave(&adev->pcie_idx_lock, flags);
389 WREG32(address, reg * 4);
390 (void)RREG32(address);
392 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
396 static void nv_pcie_wreg64(struct amdgpu_device *adev, u32 reg, u64 v)
398 unsigned long address, data;
400 address = adev->nbio.funcs->get_pcie_index_offset(adev);
401 data = adev->nbio.funcs->get_pcie_data_offset(adev);
403 amdgpu_device_indirect_wreg64(adev, address, data, reg, v);
406 static void nv_pcie_port_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
408 unsigned long flags, address, data;
410 address = adev->nbio.funcs->get_pcie_port_index_offset(adev);
411 data = adev->nbio.funcs->get_pcie_port_data_offset(adev);
413 spin_lock_irqsave(&adev->pcie_idx_lock, flags);
414 WREG32(address, reg * 4);
415 (void)RREG32(address);
418 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
421 static u32 nv_didt_rreg(struct amdgpu_device *adev, u32 reg)
423 unsigned long flags, address, data;
426 address = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_INDEX);
427 data = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_DATA);
429 spin_lock_irqsave(&adev->didt_idx_lock, flags);
430 WREG32(address, (reg));
432 spin_unlock_irqrestore(&adev->didt_idx_lock, flags);
436 static void nv_didt_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
438 unsigned long flags, address, data;
440 address = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_INDEX);
441 data = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_DATA);
443 spin_lock_irqsave(&adev->didt_idx_lock, flags);
444 WREG32(address, (reg));
446 spin_unlock_irqrestore(&adev->didt_idx_lock, flags);
449 static u32 nv_get_config_memsize(struct amdgpu_device *adev)
451 return adev->nbio.funcs->get_memsize(adev);
454 static u32 nv_get_xclk(struct amdgpu_device *adev)
456 return adev->clock.spll.reference_freq;
460 void nv_grbm_select(struct amdgpu_device *adev,
461 u32 me, u32 pipe, u32 queue, u32 vmid)
463 u32 grbm_gfx_cntl = 0;
464 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, PIPEID, pipe);
465 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, MEID, me);
466 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, VMID, vmid);
467 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, QUEUEID, queue);
469 WREG32(SOC15_REG_OFFSET(GC, 0, mmGRBM_GFX_CNTL), grbm_gfx_cntl);
472 static void nv_vga_set_state(struct amdgpu_device *adev, bool state)
477 static bool nv_read_disabled_bios(struct amdgpu_device *adev)
483 static bool nv_read_bios_from_rom(struct amdgpu_device *adev,
484 u8 *bios, u32 length_bytes)
488 u32 rom_index_offset, rom_data_offset;
492 if (length_bytes == 0)
494 /* APU vbios image is part of sbios image */
495 if (adev->flags & AMD_IS_APU)
498 dw_ptr = (u32 *)bios;
499 length_dw = ALIGN(length_bytes, 4) / 4;
502 adev->smuio.funcs->get_rom_index_offset(adev);
504 adev->smuio.funcs->get_rom_data_offset(adev);
506 /* set rom index to 0 */
507 WREG32(rom_index_offset, 0);
508 /* read out the rom data */
509 for (i = 0; i < length_dw; i++)
510 dw_ptr[i] = RREG32(rom_data_offset);
515 static struct soc15_allowed_register_entry nv_allowed_read_registers[] = {
516 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS)},
517 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS2)},
518 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE0)},
519 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE1)},
520 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE2)},
521 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE3)},
522 { SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_STATUS_REG)},
523 { SOC15_REG_ENTRY(SDMA1, 0, mmSDMA1_STATUS_REG)},
524 { SOC15_REG_ENTRY(GC, 0, mmCP_STAT)},
525 { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT1)},
526 { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT2)},
527 { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT3)},
528 { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_BUSY_STAT)},
529 { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_STALLED_STAT1)},
530 { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_STATUS)},
531 { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_BUSY_STAT)},
532 { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_STALLED_STAT1)},
533 { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_STATUS)},
534 { SOC15_REG_ENTRY(GC, 0, mmGB_ADDR_CONFIG)},
537 static uint32_t nv_read_indexed_register(struct amdgpu_device *adev, u32 se_num,
538 u32 sh_num, u32 reg_offset)
542 mutex_lock(&adev->grbm_idx_mutex);
543 if (se_num != 0xffffffff || sh_num != 0xffffffff)
544 amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff);
546 val = RREG32(reg_offset);
548 if (se_num != 0xffffffff || sh_num != 0xffffffff)
549 amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
550 mutex_unlock(&adev->grbm_idx_mutex);
554 static uint32_t nv_get_register_value(struct amdgpu_device *adev,
555 bool indexed, u32 se_num,
556 u32 sh_num, u32 reg_offset)
559 return nv_read_indexed_register(adev, se_num, sh_num, reg_offset);
561 if (reg_offset == SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG))
562 return adev->gfx.config.gb_addr_config;
563 return RREG32(reg_offset);
567 static int nv_read_register(struct amdgpu_device *adev, u32 se_num,
568 u32 sh_num, u32 reg_offset, u32 *value)
571 struct soc15_allowed_register_entry *en;
574 for (i = 0; i < ARRAY_SIZE(nv_allowed_read_registers); i++) {
575 en = &nv_allowed_read_registers[i];
576 if ((i == 7 && (adev->sdma.num_instances == 1)) || /* some asics don't have SDMA1 */
578 (adev->reg_offset[en->hwip][en->inst][en->seg] + en->reg_offset))
581 *value = nv_get_register_value(adev,
582 nv_allowed_read_registers[i].grbm_indexed,
583 se_num, sh_num, reg_offset);
589 static int nv_asic_mode2_reset(struct amdgpu_device *adev)
594 amdgpu_atombios_scratch_regs_engine_hung(adev, true);
597 pci_clear_master(adev->pdev);
599 amdgpu_device_cache_pci_state(adev->pdev);
601 ret = amdgpu_dpm_mode2_reset(adev);
603 dev_err(adev->dev, "GPU mode2 reset failed\n");
605 amdgpu_device_load_pci_state(adev->pdev);
607 /* wait for asic to come out of reset */
608 for (i = 0; i < adev->usec_timeout; i++) {
609 u32 memsize = adev->nbio.funcs->get_memsize(adev);
611 if (memsize != 0xffffffff)
616 amdgpu_atombios_scratch_regs_engine_hung(adev, false);
621 static enum amd_reset_method
622 nv_asic_reset_method(struct amdgpu_device *adev)
624 if (amdgpu_reset_method == AMD_RESET_METHOD_MODE1 ||
625 amdgpu_reset_method == AMD_RESET_METHOD_MODE2 ||
626 amdgpu_reset_method == AMD_RESET_METHOD_BACO ||
627 amdgpu_reset_method == AMD_RESET_METHOD_PCI)
628 return amdgpu_reset_method;
630 if (amdgpu_reset_method != -1)
631 dev_warn(adev->dev, "Specified reset method:%d isn't supported, using AUTO instead.\n",
632 amdgpu_reset_method);
634 switch (adev->asic_type) {
636 return AMD_RESET_METHOD_MODE2;
637 case CHIP_SIENNA_CICHLID:
638 case CHIP_NAVY_FLOUNDER:
639 case CHIP_DIMGREY_CAVEFISH:
640 return AMD_RESET_METHOD_MODE1;
642 if (amdgpu_dpm_is_baco_supported(adev))
643 return AMD_RESET_METHOD_BACO;
645 return AMD_RESET_METHOD_MODE1;
649 static int nv_asic_reset(struct amdgpu_device *adev)
653 switch (nv_asic_reset_method(adev)) {
654 case AMD_RESET_METHOD_PCI:
655 dev_info(adev->dev, "PCI reset\n");
656 ret = amdgpu_device_pci_reset(adev);
658 case AMD_RESET_METHOD_BACO:
659 dev_info(adev->dev, "BACO reset\n");
660 ret = amdgpu_dpm_baco_reset(adev);
662 case AMD_RESET_METHOD_MODE2:
663 dev_info(adev->dev, "MODE2 reset\n");
664 ret = nv_asic_mode2_reset(adev);
667 dev_info(adev->dev, "MODE1 reset\n");
668 ret = amdgpu_device_mode1_reset(adev);
675 static int nv_set_uvd_clocks(struct amdgpu_device *adev, u32 vclk, u32 dclk)
681 static int nv_set_vce_clocks(struct amdgpu_device *adev, u32 evclk, u32 ecclk)
687 static void nv_pcie_gen3_enable(struct amdgpu_device *adev)
689 if (pci_is_root_bus(adev->pdev->bus))
692 if (amdgpu_pcie_gen2 == 0)
695 if (!(adev->pm.pcie_gen_mask & (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 |
696 CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3)))
702 static void nv_program_aspm(struct amdgpu_device *adev)
707 if (!(adev->flags & AMD_IS_APU) &&
708 (adev->nbio.funcs->program_aspm))
709 adev->nbio.funcs->program_aspm(adev);
713 static void nv_enable_doorbell_aperture(struct amdgpu_device *adev,
716 adev->nbio.funcs->enable_doorbell_aperture(adev, enable);
717 adev->nbio.funcs->enable_doorbell_selfring_aperture(adev, enable);
720 static const struct amdgpu_ip_block_version nv_common_ip_block =
722 .type = AMD_IP_BLOCK_TYPE_COMMON,
726 .funcs = &nv_common_ip_funcs,
729 static bool nv_is_headless_sku(struct pci_dev *pdev)
731 if ((pdev->device == 0x731E &&
732 (pdev->revision == 0xC6 || pdev->revision == 0xC7)) ||
733 (pdev->device == 0x7340 && pdev->revision == 0xC9) ||
734 (pdev->device == 0x7360 && pdev->revision == 0xC7))
739 static int nv_reg_base_init(struct amdgpu_device *adev)
743 if (amdgpu_discovery) {
744 r = amdgpu_discovery_reg_base_init(adev);
746 DRM_WARN("failed to init reg base from ip discovery table, "
747 "fallback to legacy init method\n");
751 amdgpu_discovery_harvest_ip(adev);
752 if (nv_is_headless_sku(adev->pdev)) {
753 adev->harvest_ip_mask |= AMD_HARVEST_IP_VCN_MASK;
754 adev->harvest_ip_mask |= AMD_HARVEST_IP_JPEG_MASK;
761 switch (adev->asic_type) {
763 navi10_reg_base_init(adev);
766 navi14_reg_base_init(adev);
769 navi12_reg_base_init(adev);
771 case CHIP_SIENNA_CICHLID:
772 case CHIP_NAVY_FLOUNDER:
773 sienna_cichlid_reg_base_init(adev);
776 vangogh_reg_base_init(adev);
778 case CHIP_DIMGREY_CAVEFISH:
779 dimgrey_cavefish_reg_base_init(adev);
781 case CHIP_BEIGE_GOBY:
782 beige_goby_reg_base_init(adev);
791 void nv_set_virt_ops(struct amdgpu_device *adev)
793 adev->virt.ops = &xgpu_nv_virt_ops;
796 int nv_set_ip_blocks(struct amdgpu_device *adev)
800 if (adev->flags & AMD_IS_APU) {
801 adev->nbio.funcs = &nbio_v7_2_funcs;
802 adev->nbio.hdp_flush_reg = &nbio_v7_2_hdp_flush_reg;
804 adev->nbio.funcs = &nbio_v2_3_funcs;
805 adev->nbio.hdp_flush_reg = &nbio_v2_3_hdp_flush_reg;
807 adev->hdp.funcs = &hdp_v5_0_funcs;
809 if (adev->asic_type >= CHIP_SIENNA_CICHLID)
810 adev->smuio.funcs = &smuio_v11_0_6_funcs;
812 adev->smuio.funcs = &smuio_v11_0_funcs;
814 if (adev->asic_type == CHIP_SIENNA_CICHLID)
815 adev->gmc.xgmi.supported = true;
817 /* Set IP register base before any HW register access */
818 r = nv_reg_base_init(adev);
822 switch (adev->asic_type) {
825 amdgpu_device_ip_block_add(adev, &nv_common_ip_block);
826 amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block);
827 amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block);
828 amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block);
829 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP &&
830 !amdgpu_sriov_vf(adev))
831 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);
832 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))
833 amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
834 #if defined(CONFIG_DRM_AMD_DC)
835 else if (amdgpu_device_has_dc_support(adev))
836 amdgpu_device_ip_block_add(adev, &dm_ip_block);
838 amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block);
839 amdgpu_device_ip_block_add(adev, &sdma_v5_0_ip_block);
840 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT &&
841 !amdgpu_sriov_vf(adev))
842 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);
843 amdgpu_device_ip_block_add(adev, &vcn_v2_0_ip_block);
844 amdgpu_device_ip_block_add(adev, &jpeg_v2_0_ip_block);
845 if (adev->enable_mes)
846 amdgpu_device_ip_block_add(adev, &mes_v10_1_ip_block);
849 amdgpu_device_ip_block_add(adev, &nv_common_ip_block);
850 amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block);
851 amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block);
852 amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block);
853 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)
854 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);
855 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))
856 amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
857 #if defined(CONFIG_DRM_AMD_DC)
858 else if (amdgpu_device_has_dc_support(adev))
859 amdgpu_device_ip_block_add(adev, &dm_ip_block);
861 amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block);
862 amdgpu_device_ip_block_add(adev, &sdma_v5_0_ip_block);
863 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT &&
864 !amdgpu_sriov_vf(adev))
865 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);
866 amdgpu_device_ip_block_add(adev, &vcn_v2_0_ip_block);
867 if (!amdgpu_sriov_vf(adev))
868 amdgpu_device_ip_block_add(adev, &jpeg_v2_0_ip_block);
870 case CHIP_SIENNA_CICHLID:
871 amdgpu_device_ip_block_add(adev, &nv_common_ip_block);
872 amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block);
873 amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block);
874 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP))
875 amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block);
876 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP &&
877 is_support_sw_smu(adev))
878 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);
879 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))
880 amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
881 #if defined(CONFIG_DRM_AMD_DC)
882 else if (amdgpu_device_has_dc_support(adev))
883 amdgpu_device_ip_block_add(adev, &dm_ip_block);
885 amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block);
886 amdgpu_device_ip_block_add(adev, &sdma_v5_2_ip_block);
887 amdgpu_device_ip_block_add(adev, &vcn_v3_0_ip_block);
888 if (!amdgpu_sriov_vf(adev))
889 amdgpu_device_ip_block_add(adev, &jpeg_v3_0_ip_block);
890 if (adev->enable_mes)
891 amdgpu_device_ip_block_add(adev, &mes_v10_1_ip_block);
893 case CHIP_NAVY_FLOUNDER:
894 amdgpu_device_ip_block_add(adev, &nv_common_ip_block);
895 amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block);
896 amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block);
897 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP))
898 amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block);
899 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP &&
900 is_support_sw_smu(adev))
901 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);
902 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))
903 amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
904 #if defined(CONFIG_DRM_AMD_DC)
905 else if (amdgpu_device_has_dc_support(adev))
906 amdgpu_device_ip_block_add(adev, &dm_ip_block);
908 amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block);
909 amdgpu_device_ip_block_add(adev, &sdma_v5_2_ip_block);
910 amdgpu_device_ip_block_add(adev, &vcn_v3_0_ip_block);
911 amdgpu_device_ip_block_add(adev, &jpeg_v3_0_ip_block);
912 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT &&
913 is_support_sw_smu(adev))
914 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);
917 amdgpu_device_ip_block_add(adev, &nv_common_ip_block);
918 amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block);
919 amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block);
920 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP))
921 amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block);
922 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);
923 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))
924 amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
925 #if defined(CONFIG_DRM_AMD_DC)
926 else if (amdgpu_device_has_dc_support(adev))
927 amdgpu_device_ip_block_add(adev, &dm_ip_block);
929 amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block);
930 amdgpu_device_ip_block_add(adev, &sdma_v5_2_ip_block);
931 amdgpu_device_ip_block_add(adev, &vcn_v3_0_ip_block);
932 amdgpu_device_ip_block_add(adev, &jpeg_v3_0_ip_block);
934 case CHIP_DIMGREY_CAVEFISH:
935 amdgpu_device_ip_block_add(adev, &nv_common_ip_block);
936 amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block);
937 amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block);
938 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP))
939 amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block);
940 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP &&
941 is_support_sw_smu(adev))
942 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);
943 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))
944 amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
945 #if defined(CONFIG_DRM_AMD_DC)
946 else if (amdgpu_device_has_dc_support(adev))
947 amdgpu_device_ip_block_add(adev, &dm_ip_block);
949 amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block);
950 amdgpu_device_ip_block_add(adev, &sdma_v5_2_ip_block);
951 amdgpu_device_ip_block_add(adev, &vcn_v3_0_ip_block);
952 amdgpu_device_ip_block_add(adev, &jpeg_v3_0_ip_block);
954 case CHIP_BEIGE_GOBY:
955 amdgpu_device_ip_block_add(adev, &nv_common_ip_block);
956 amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block);
957 amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block);
966 static uint32_t nv_get_rev_id(struct amdgpu_device *adev)
968 return adev->nbio.funcs->get_rev_id(adev);
971 static bool nv_need_full_reset(struct amdgpu_device *adev)
976 static bool nv_need_reset_on_init(struct amdgpu_device *adev)
980 if (adev->flags & AMD_IS_APU)
983 /* Check sOS sign of life register to confirm sys driver and sOS
984 * are already been loaded.
986 sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81);
993 static uint64_t nv_get_pcie_replay_count(struct amdgpu_device *adev)
997 * dummy implement for pcie_replay_count sysfs interface
1003 static void nv_init_doorbell_index(struct amdgpu_device *adev)
1005 adev->doorbell_index.kiq = AMDGPU_NAVI10_DOORBELL_KIQ;
1006 adev->doorbell_index.mec_ring0 = AMDGPU_NAVI10_DOORBELL_MEC_RING0;
1007 adev->doorbell_index.mec_ring1 = AMDGPU_NAVI10_DOORBELL_MEC_RING1;
1008 adev->doorbell_index.mec_ring2 = AMDGPU_NAVI10_DOORBELL_MEC_RING2;
1009 adev->doorbell_index.mec_ring3 = AMDGPU_NAVI10_DOORBELL_MEC_RING3;
1010 adev->doorbell_index.mec_ring4 = AMDGPU_NAVI10_DOORBELL_MEC_RING4;
1011 adev->doorbell_index.mec_ring5 = AMDGPU_NAVI10_DOORBELL_MEC_RING5;
1012 adev->doorbell_index.mec_ring6 = AMDGPU_NAVI10_DOORBELL_MEC_RING6;
1013 adev->doorbell_index.mec_ring7 = AMDGPU_NAVI10_DOORBELL_MEC_RING7;
1014 adev->doorbell_index.userqueue_start = AMDGPU_NAVI10_DOORBELL_USERQUEUE_START;
1015 adev->doorbell_index.userqueue_end = AMDGPU_NAVI10_DOORBELL_USERQUEUE_END;
1016 adev->doorbell_index.gfx_ring0 = AMDGPU_NAVI10_DOORBELL_GFX_RING0;
1017 adev->doorbell_index.gfx_ring1 = AMDGPU_NAVI10_DOORBELL_GFX_RING1;
1018 adev->doorbell_index.mes_ring = AMDGPU_NAVI10_DOORBELL_MES_RING;
1019 adev->doorbell_index.sdma_engine[0] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE0;
1020 adev->doorbell_index.sdma_engine[1] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE1;
1021 adev->doorbell_index.sdma_engine[2] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE2;
1022 adev->doorbell_index.sdma_engine[3] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE3;
1023 adev->doorbell_index.ih = AMDGPU_NAVI10_DOORBELL_IH;
1024 adev->doorbell_index.vcn.vcn_ring0_1 = AMDGPU_NAVI10_DOORBELL64_VCN0_1;
1025 adev->doorbell_index.vcn.vcn_ring2_3 = AMDGPU_NAVI10_DOORBELL64_VCN2_3;
1026 adev->doorbell_index.vcn.vcn_ring4_5 = AMDGPU_NAVI10_DOORBELL64_VCN4_5;
1027 adev->doorbell_index.vcn.vcn_ring6_7 = AMDGPU_NAVI10_DOORBELL64_VCN6_7;
1028 adev->doorbell_index.first_non_cp = AMDGPU_NAVI10_DOORBELL64_FIRST_NON_CP;
1029 adev->doorbell_index.last_non_cp = AMDGPU_NAVI10_DOORBELL64_LAST_NON_CP;
1031 adev->doorbell_index.max_assignment = AMDGPU_NAVI10_DOORBELL_MAX_ASSIGNMENT << 1;
1032 adev->doorbell_index.sdma_doorbell_range = 20;
1035 static void nv_pre_asic_init(struct amdgpu_device *adev)
1039 static int nv_update_umd_stable_pstate(struct amdgpu_device *adev,
1043 amdgpu_gfx_rlc_enter_safe_mode(adev);
1045 amdgpu_gfx_rlc_exit_safe_mode(adev);
1047 if (adev->gfx.funcs->update_perfmon_mgcg)
1048 adev->gfx.funcs->update_perfmon_mgcg(adev, !enter);
1050 if (!(adev->flags & AMD_IS_APU) &&
1051 (adev->nbio.funcs->enable_aspm))
1052 adev->nbio.funcs->enable_aspm(adev, !enter);
1057 static const struct amdgpu_asic_funcs nv_asic_funcs =
1059 .read_disabled_bios = &nv_read_disabled_bios,
1060 .read_bios_from_rom = &nv_read_bios_from_rom,
1061 .read_register = &nv_read_register,
1062 .reset = &nv_asic_reset,
1063 .reset_method = &nv_asic_reset_method,
1064 .set_vga_state = &nv_vga_set_state,
1065 .get_xclk = &nv_get_xclk,
1066 .set_uvd_clocks = &nv_set_uvd_clocks,
1067 .set_vce_clocks = &nv_set_vce_clocks,
1068 .get_config_memsize = &nv_get_config_memsize,
1069 .init_doorbell_index = &nv_init_doorbell_index,
1070 .need_full_reset = &nv_need_full_reset,
1071 .need_reset_on_init = &nv_need_reset_on_init,
1072 .get_pcie_replay_count = &nv_get_pcie_replay_count,
1073 .supports_baco = &amdgpu_dpm_is_baco_supported,
1074 .pre_asic_init = &nv_pre_asic_init,
1075 .update_umd_stable_pstate = &nv_update_umd_stable_pstate,
1076 .query_video_codecs = &nv_query_video_codecs,
1079 static int nv_common_early_init(void *handle)
1081 #define MMIO_REG_HOLE_OFFSET (0x80000 - PAGE_SIZE)
1082 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1084 adev->rmmio_remap.reg_offset = MMIO_REG_HOLE_OFFSET;
1085 adev->rmmio_remap.bus_addr = adev->rmmio_base + MMIO_REG_HOLE_OFFSET;
1086 adev->smc_rreg = NULL;
1087 adev->smc_wreg = NULL;
1088 adev->pcie_rreg = &nv_pcie_rreg;
1089 adev->pcie_wreg = &nv_pcie_wreg;
1090 adev->pcie_rreg64 = &nv_pcie_rreg64;
1091 adev->pcie_wreg64 = &nv_pcie_wreg64;
1092 adev->pciep_rreg = &nv_pcie_port_rreg;
1093 adev->pciep_wreg = &nv_pcie_port_wreg;
1095 /* TODO: will add them during VCN v2 implementation */
1096 adev->uvd_ctx_rreg = NULL;
1097 adev->uvd_ctx_wreg = NULL;
1099 adev->didt_rreg = &nv_didt_rreg;
1100 adev->didt_wreg = &nv_didt_wreg;
1102 adev->asic_funcs = &nv_asic_funcs;
1104 adev->rev_id = nv_get_rev_id(adev);
1105 adev->external_rev_id = 0xff;
1106 switch (adev->asic_type) {
1108 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
1109 AMD_CG_SUPPORT_GFX_CGCG |
1110 AMD_CG_SUPPORT_IH_CG |
1111 AMD_CG_SUPPORT_HDP_MGCG |
1112 AMD_CG_SUPPORT_HDP_LS |
1113 AMD_CG_SUPPORT_SDMA_MGCG |
1114 AMD_CG_SUPPORT_SDMA_LS |
1115 AMD_CG_SUPPORT_MC_MGCG |
1116 AMD_CG_SUPPORT_MC_LS |
1117 AMD_CG_SUPPORT_ATHUB_MGCG |
1118 AMD_CG_SUPPORT_ATHUB_LS |
1119 AMD_CG_SUPPORT_VCN_MGCG |
1120 AMD_CG_SUPPORT_JPEG_MGCG |
1121 AMD_CG_SUPPORT_BIF_MGCG |
1122 AMD_CG_SUPPORT_BIF_LS;
1123 adev->pg_flags = AMD_PG_SUPPORT_VCN |
1124 AMD_PG_SUPPORT_VCN_DPG |
1125 AMD_PG_SUPPORT_JPEG |
1126 AMD_PG_SUPPORT_ATHUB;
1127 adev->external_rev_id = adev->rev_id + 0x1;
1130 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
1131 AMD_CG_SUPPORT_GFX_CGCG |
1132 AMD_CG_SUPPORT_IH_CG |
1133 AMD_CG_SUPPORT_HDP_MGCG |
1134 AMD_CG_SUPPORT_HDP_LS |
1135 AMD_CG_SUPPORT_SDMA_MGCG |
1136 AMD_CG_SUPPORT_SDMA_LS |
1137 AMD_CG_SUPPORT_MC_MGCG |
1138 AMD_CG_SUPPORT_MC_LS |
1139 AMD_CG_SUPPORT_ATHUB_MGCG |
1140 AMD_CG_SUPPORT_ATHUB_LS |
1141 AMD_CG_SUPPORT_VCN_MGCG |
1142 AMD_CG_SUPPORT_JPEG_MGCG |
1143 AMD_CG_SUPPORT_BIF_MGCG |
1144 AMD_CG_SUPPORT_BIF_LS;
1145 adev->pg_flags = AMD_PG_SUPPORT_VCN |
1146 AMD_PG_SUPPORT_JPEG |
1147 AMD_PG_SUPPORT_VCN_DPG;
1148 adev->external_rev_id = adev->rev_id + 20;
1151 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
1152 AMD_CG_SUPPORT_GFX_MGLS |
1153 AMD_CG_SUPPORT_GFX_CGCG |
1154 AMD_CG_SUPPORT_GFX_CP_LS |
1155 AMD_CG_SUPPORT_GFX_RLC_LS |
1156 AMD_CG_SUPPORT_IH_CG |
1157 AMD_CG_SUPPORT_HDP_MGCG |
1158 AMD_CG_SUPPORT_HDP_LS |
1159 AMD_CG_SUPPORT_SDMA_MGCG |
1160 AMD_CG_SUPPORT_SDMA_LS |
1161 AMD_CG_SUPPORT_MC_MGCG |
1162 AMD_CG_SUPPORT_MC_LS |
1163 AMD_CG_SUPPORT_ATHUB_MGCG |
1164 AMD_CG_SUPPORT_ATHUB_LS |
1165 AMD_CG_SUPPORT_VCN_MGCG |
1166 AMD_CG_SUPPORT_JPEG_MGCG;
1167 adev->pg_flags = AMD_PG_SUPPORT_VCN |
1168 AMD_PG_SUPPORT_VCN_DPG |
1169 AMD_PG_SUPPORT_JPEG |
1170 AMD_PG_SUPPORT_ATHUB;
1171 /* guest vm gets 0xffffffff when reading RCC_DEV0_EPF0_STRAP0,
1172 * as a consequence, the rev_id and external_rev_id are wrong.
1173 * workaround it by hardcoding rev_id to 0 (default value).
1175 if (amdgpu_sriov_vf(adev))
1177 adev->external_rev_id = adev->rev_id + 0xa;
1179 case CHIP_SIENNA_CICHLID:
1180 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
1181 AMD_CG_SUPPORT_GFX_CGCG |
1182 AMD_CG_SUPPORT_GFX_CGLS |
1183 AMD_CG_SUPPORT_GFX_3D_CGCG |
1184 AMD_CG_SUPPORT_MC_MGCG |
1185 AMD_CG_SUPPORT_VCN_MGCG |
1186 AMD_CG_SUPPORT_JPEG_MGCG |
1187 AMD_CG_SUPPORT_HDP_MGCG |
1188 AMD_CG_SUPPORT_HDP_LS |
1189 AMD_CG_SUPPORT_IH_CG |
1190 AMD_CG_SUPPORT_MC_LS;
1191 adev->pg_flags = AMD_PG_SUPPORT_VCN |
1192 AMD_PG_SUPPORT_VCN_DPG |
1193 AMD_PG_SUPPORT_JPEG |
1194 AMD_PG_SUPPORT_ATHUB |
1195 AMD_PG_SUPPORT_MMHUB;
1196 if (amdgpu_sriov_vf(adev)) {
1197 /* hypervisor control CG and PG enablement */
1201 adev->external_rev_id = adev->rev_id + 0x28;
1203 case CHIP_NAVY_FLOUNDER:
1204 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
1205 AMD_CG_SUPPORT_GFX_CGCG |
1206 AMD_CG_SUPPORT_GFX_CGLS |
1207 AMD_CG_SUPPORT_GFX_3D_CGCG |
1208 AMD_CG_SUPPORT_VCN_MGCG |
1209 AMD_CG_SUPPORT_JPEG_MGCG |
1210 AMD_CG_SUPPORT_MC_MGCG |
1211 AMD_CG_SUPPORT_MC_LS |
1212 AMD_CG_SUPPORT_HDP_MGCG |
1213 AMD_CG_SUPPORT_HDP_LS |
1214 AMD_CG_SUPPORT_IH_CG;
1215 adev->pg_flags = AMD_PG_SUPPORT_VCN |
1216 AMD_PG_SUPPORT_VCN_DPG |
1217 AMD_PG_SUPPORT_JPEG |
1218 AMD_PG_SUPPORT_ATHUB |
1219 AMD_PG_SUPPORT_MMHUB;
1220 adev->external_rev_id = adev->rev_id + 0x32;
1224 adev->apu_flags |= AMD_APU_IS_VANGOGH;
1225 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
1226 AMD_CG_SUPPORT_GFX_MGLS |
1227 AMD_CG_SUPPORT_GFX_CP_LS |
1228 AMD_CG_SUPPORT_GFX_RLC_LS |
1229 AMD_CG_SUPPORT_GFX_CGCG |
1230 AMD_CG_SUPPORT_GFX_CGLS |
1231 AMD_CG_SUPPORT_GFX_3D_CGCG |
1232 AMD_CG_SUPPORT_GFX_3D_CGLS |
1233 AMD_CG_SUPPORT_MC_MGCG |
1234 AMD_CG_SUPPORT_MC_LS |
1235 AMD_CG_SUPPORT_GFX_FGCG |
1236 AMD_CG_SUPPORT_VCN_MGCG |
1237 AMD_CG_SUPPORT_SDMA_MGCG |
1238 AMD_CG_SUPPORT_SDMA_LS |
1239 AMD_CG_SUPPORT_JPEG_MGCG;
1240 adev->pg_flags = AMD_PG_SUPPORT_GFX_PG |
1241 AMD_PG_SUPPORT_VCN |
1242 AMD_PG_SUPPORT_VCN_DPG |
1243 AMD_PG_SUPPORT_JPEG;
1244 if (adev->apu_flags & AMD_APU_IS_VANGOGH)
1245 adev->external_rev_id = adev->rev_id + 0x01;
1247 case CHIP_DIMGREY_CAVEFISH:
1248 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
1249 AMD_CG_SUPPORT_GFX_CGCG |
1250 AMD_CG_SUPPORT_GFX_CGLS |
1251 AMD_CG_SUPPORT_GFX_3D_CGCG |
1252 AMD_CG_SUPPORT_VCN_MGCG |
1253 AMD_CG_SUPPORT_JPEG_MGCG |
1254 AMD_CG_SUPPORT_MC_MGCG |
1255 AMD_CG_SUPPORT_MC_LS |
1256 AMD_CG_SUPPORT_HDP_MGCG |
1257 AMD_CG_SUPPORT_HDP_LS |
1258 AMD_CG_SUPPORT_IH_CG;
1259 adev->pg_flags = AMD_PG_SUPPORT_VCN |
1260 AMD_PG_SUPPORT_VCN_DPG |
1261 AMD_PG_SUPPORT_JPEG |
1262 AMD_PG_SUPPORT_ATHUB |
1263 AMD_PG_SUPPORT_MMHUB;
1264 adev->external_rev_id = adev->rev_id + 0x3c;
1266 case CHIP_BEIGE_GOBY:
1269 adev->external_rev_id = adev->rev_id + 0x46;
1272 /* FIXME: not supported yet */
1276 if (adev->harvest_ip_mask & AMD_HARVEST_IP_VCN_MASK)
1277 adev->pg_flags &= ~(AMD_PG_SUPPORT_VCN |
1278 AMD_PG_SUPPORT_VCN_DPG |
1279 AMD_PG_SUPPORT_JPEG);
1281 if (amdgpu_sriov_vf(adev)) {
1282 amdgpu_virt_init_setting(adev);
1283 xgpu_nv_mailbox_set_irq_funcs(adev);
1289 static int nv_common_late_init(void *handle)
1291 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1293 if (amdgpu_sriov_vf(adev)) {
1294 xgpu_nv_mailbox_get_irq(adev);
1295 amdgpu_virt_update_sriov_video_codec(adev,
1296 sriov_sc_video_codecs_encode_array, ARRAY_SIZE(sriov_sc_video_codecs_encode_array),
1297 sriov_sc_video_codecs_decode_array, ARRAY_SIZE(sriov_sc_video_codecs_decode_array));
1303 static int nv_common_sw_init(void *handle)
1305 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1307 if (amdgpu_sriov_vf(adev))
1308 xgpu_nv_mailbox_add_irq_id(adev);
1313 static int nv_common_sw_fini(void *handle)
1318 static int nv_common_hw_init(void *handle)
1320 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1322 /* enable pcie gen2/3 link */
1323 nv_pcie_gen3_enable(adev);
1325 nv_program_aspm(adev);
1326 /* setup nbio registers */
1327 adev->nbio.funcs->init_registers(adev);
1328 /* remap HDP registers to a hole in mmio space,
1329 * for the purpose of expose those registers
1332 if (adev->nbio.funcs->remap_hdp_registers)
1333 adev->nbio.funcs->remap_hdp_registers(adev);
1334 /* enable the doorbell aperture */
1335 nv_enable_doorbell_aperture(adev, true);
1340 static int nv_common_hw_fini(void *handle)
1342 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1344 /* disable the doorbell aperture */
1345 nv_enable_doorbell_aperture(adev, false);
1350 static int nv_common_suspend(void *handle)
1352 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1354 return nv_common_hw_fini(adev);
1357 static int nv_common_resume(void *handle)
1359 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1361 return nv_common_hw_init(adev);
1364 static bool nv_common_is_idle(void *handle)
1369 static int nv_common_wait_for_idle(void *handle)
1374 static int nv_common_soft_reset(void *handle)
1379 static int nv_common_set_clockgating_state(void *handle,
1380 enum amd_clockgating_state state)
1382 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1384 if (amdgpu_sriov_vf(adev))
1387 switch (adev->asic_type) {
1391 case CHIP_SIENNA_CICHLID:
1392 case CHIP_NAVY_FLOUNDER:
1393 case CHIP_DIMGREY_CAVEFISH:
1394 case CHIP_BEIGE_GOBY:
1395 adev->nbio.funcs->update_medium_grain_clock_gating(adev,
1396 state == AMD_CG_STATE_GATE);
1397 adev->nbio.funcs->update_medium_grain_light_sleep(adev,
1398 state == AMD_CG_STATE_GATE);
1399 adev->hdp.funcs->update_clock_gating(adev,
1400 state == AMD_CG_STATE_GATE);
1401 adev->smuio.funcs->update_rom_clock_gating(adev,
1402 state == AMD_CG_STATE_GATE);
1410 static int nv_common_set_powergating_state(void *handle,
1411 enum amd_powergating_state state)
1417 static void nv_common_get_clockgating_state(void *handle, u32 *flags)
1419 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1421 if (amdgpu_sriov_vf(adev))
1424 adev->nbio.funcs->get_clockgating_state(adev, flags);
1426 adev->hdp.funcs->get_clock_gating_state(adev, flags);
1428 adev->smuio.funcs->get_clock_gating_state(adev, flags);
1433 static const struct amd_ip_funcs nv_common_ip_funcs = {
1434 .name = "nv_common",
1435 .early_init = nv_common_early_init,
1436 .late_init = nv_common_late_init,
1437 .sw_init = nv_common_sw_init,
1438 .sw_fini = nv_common_sw_fini,
1439 .hw_init = nv_common_hw_init,
1440 .hw_fini = nv_common_hw_fini,
1441 .suspend = nv_common_suspend,
1442 .resume = nv_common_resume,
1443 .is_idle = nv_common_is_idle,
1444 .wait_for_idle = nv_common_wait_for_idle,
1445 .soft_reset = nv_common_soft_reset,
1446 .set_clockgating_state = nv_common_set_clockgating_state,
1447 .set_powergating_state = nv_common_set_powergating_state,
1448 .get_clockgating_state = nv_common_get_clockgating_state,