drivers/gpu/drm/amd/amdgpu/nv.c

   1 /*
   2  * Copyright 2019 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23 #include <linux/firmware.h>
  24 #include <linux/slab.h>
  25 #include <linux/module.h>
  26 #include <linux/pci.h>
  27
  28 #include "amdgpu.h"
  29 #include "amdgpu_atombios.h"
  30 #include "amdgpu_ih.h"
  31 #include "amdgpu_uvd.h"
  32 #include "amdgpu_vce.h"
  33 #include "amdgpu_ucode.h"
  34 #include "amdgpu_psp.h"
  35 #include "amdgpu_smu.h"
  36 #include "atom.h"
  37 #include "amd_pcie.h"
  38
  39 #include "gc/gc_10_1_0_offset.h"
  40 #include "gc/gc_10_1_0_sh_mask.h"
  41 #include "hdp/hdp_5_0_0_offset.h"
  42 #include "hdp/hdp_5_0_0_sh_mask.h"
  43 #include "smuio/smuio_11_0_0_offset.h"
  44 #include "mp/mp_11_0_offset.h"
  45
  46 #include "soc15.h"
  47 #include "soc15_common.h"
  48 #include "gmc_v10_0.h"
  49 #include "gfxhub_v2_0.h"
  50 #include "mmhub_v2_0.h"
  51 #include "nbio_v2_3.h"
  52 #include "nbio_v7_2.h"
  53 #include "nv.h"
  54 #include "navi10_ih.h"
  55 #include "gfx_v10_0.h"
  56 #include "sdma_v5_0.h"
  57 #include "sdma_v5_2.h"
  58 #include "vcn_v2_0.h"
  59 #include "jpeg_v2_0.h"
  60 #include "vcn_v3_0.h"
  61 #include "jpeg_v3_0.h"
  62 #include "dce_virtual.h"
  63 #include "mes_v10_1.h"
  64 #include "mxgpu_nv.h"
  65
  66 static const struct amd_ip_funcs nv_common_ip_funcs;
  67
  68 /*
  69  * Indirect registers accessor
  70  */
  71 static u32 nv_pcie_rreg(struct amdgpu_device *adev, u32 reg)
  72 {
  73         unsigned long address, data;
  74         address = adev->nbio.funcs->get_pcie_index_offset(adev);
  75         data = adev->nbio.funcs->get_pcie_data_offset(adev);
  76
  77         return amdgpu_device_indirect_rreg(adev, address, data, reg);
  78 }
  79
  80 static void nv_pcie_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
  81 {
  82         unsigned long address, data;
  83
  84         address = adev->nbio.funcs->get_pcie_index_offset(adev);
  85         data = adev->nbio.funcs->get_pcie_data_offset(adev);
  86
  87         amdgpu_device_indirect_wreg(adev, address, data, reg, v);
  88 }
  89
  90 static u64 nv_pcie_rreg64(struct amdgpu_device *adev, u32 reg)
  91 {
  92         unsigned long address, data;
  93         address = adev->nbio.funcs->get_pcie_index_offset(adev);
  94         data = adev->nbio.funcs->get_pcie_data_offset(adev);
  95
  96         return amdgpu_device_indirect_rreg64(adev, address, data, reg);
  97 }
  98
  99 static u32 nv_pcie_port_rreg(struct amdgpu_device *adev, u32 reg)
 100 {
 101         unsigned long flags, address, data;
 102         u32 r;
 103         address = adev->nbio.funcs->get_pcie_port_index_offset(adev);
 104         data = adev->nbio.funcs->get_pcie_port_data_offset(adev);
 105
 106         spin_lock_irqsave(&adev->pcie_idx_lock, flags);
 107         WREG32(address, reg * 4);
 108         (void)RREG32(address);
 109         r = RREG32(data);
 110         spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
 111         return r;
 112 }
 113
 114 static void nv_pcie_wreg64(struct amdgpu_device *adev, u32 reg, u64 v)
 115 {
 116         unsigned long address, data;
 117
 118         address = adev->nbio.funcs->get_pcie_index_offset(adev);
 119         data = adev->nbio.funcs->get_pcie_data_offset(adev);
 120
 121         amdgpu_device_indirect_wreg64(adev, address, data, reg, v);
 122 }
 123
 124 static void nv_pcie_port_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
 125 {
 126         unsigned long flags, address, data;
 127
 128         address = adev->nbio.funcs->get_pcie_port_index_offset(adev);
 129         data = adev->nbio.funcs->get_pcie_port_data_offset(adev);
 130
 131         spin_lock_irqsave(&adev->pcie_idx_lock, flags);
 132         WREG32(address, reg * 4);
 133         (void)RREG32(address);
 134         WREG32(data, v);
 135         (void)RREG32(data);
 136         spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
 137 }
 138
 139 static u32 nv_didt_rreg(struct amdgpu_device *adev, u32 reg)
 140 {
 141         unsigned long flags, address, data;
 142         u32 r;
 143
 144         address = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_INDEX);
 145         data = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_DATA);
 146
 147         spin_lock_irqsave(&adev->didt_idx_lock, flags);
 148         WREG32(address, (reg));
 149         r = RREG32(data);
 150         spin_unlock_irqrestore(&adev->didt_idx_lock, flags);
 151         return r;
 152 }
 153
 154 static void nv_didt_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
 155 {
 156         unsigned long flags, address, data;
 157
 158         address = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_INDEX);
 159         data = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_DATA);
 160
 161         spin_lock_irqsave(&adev->didt_idx_lock, flags);
 162         WREG32(address, (reg));
 163         WREG32(data, (v));
 164         spin_unlock_irqrestore(&adev->didt_idx_lock, flags);
 165 }
 166
 167 static u32 nv_get_config_memsize(struct amdgpu_device *adev)
 168 {
 169         return adev->nbio.funcs->get_memsize(adev);
 170 }
 171
 172 static u32 nv_get_xclk(struct amdgpu_device *adev)
 173 {
 174         return adev->clock.spll.reference_freq;
 175 }
 176
 177
 178 void nv_grbm_select(struct amdgpu_device *adev,
 179                      u32 me, u32 pipe, u32 queue, u32 vmid)
 180 {
 181         u32 grbm_gfx_cntl = 0;
 182         grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, PIPEID, pipe);
 183         grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, MEID, me);
 184         grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, VMID, vmid);
 185         grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, QUEUEID, queue);
 186
 187         WREG32(SOC15_REG_OFFSET(GC, 0, mmGRBM_GFX_CNTL), grbm_gfx_cntl);
 188 }
 189
 190 static void nv_vga_set_state(struct amdgpu_device *adev, bool state)
 191 {
 192         /* todo */
 193 }
 194
 195 static bool nv_read_disabled_bios(struct amdgpu_device *adev)
 196 {
 197         /* todo */
 198         return false;
 199 }
 200
 201 static bool nv_read_bios_from_rom(struct amdgpu_device *adev,
 202                                   u8 *bios, u32 length_bytes)
 203 {
 204         u32 *dw_ptr;
 205         u32 i, length_dw;
 206
 207         if (bios == NULL)
 208                 return false;
 209         if (length_bytes == 0)
 210                 return false;
 211         /* APU vbios image is part of sbios image */
 212         if (adev->flags & AMD_IS_APU)
 213                 return false;
 214
 215         dw_ptr = (u32 *)bios;
 216         length_dw = ALIGN(length_bytes, 4) / 4;
 217
 218         /* set rom index to 0 */
 219         WREG32(SOC15_REG_OFFSET(SMUIO, 0, mmROM_INDEX), 0);
 220         /* read out the rom data */
 221         for (i = 0; i < length_dw; i++)
 222                 dw_ptr[i] = RREG32(SOC15_REG_OFFSET(SMUIO, 0, mmROM_DATA));
 223
 224         return true;
 225 }
 226
 227 static struct soc15_allowed_register_entry nv_allowed_read_registers[] = {
 228         { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS)},
 229         { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS2)},
 230         { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE0)},
 231         { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE1)},
 232         { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE2)},
 233         { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE3)},
 234         { SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_STATUS_REG)},
 235         { SOC15_REG_ENTRY(SDMA1, 0, mmSDMA1_STATUS_REG)},
 236         { SOC15_REG_ENTRY(GC, 0, mmCP_STAT)},
 237         { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT1)},
 238         { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT2)},
 239         { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT3)},
 240         { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_BUSY_STAT)},
 241         { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_STALLED_STAT1)},
 242         { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_STATUS)},
 243         { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_BUSY_STAT)},
 244         { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_STALLED_STAT1)},
 245         { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_STATUS)},
 246         { SOC15_REG_ENTRY(GC, 0, mmGB_ADDR_CONFIG)},
 247 };
 248
 249 static uint32_t nv_read_indexed_register(struct amdgpu_device *adev, u32 se_num,
 250                                          u32 sh_num, u32 reg_offset)
 251 {
 252         uint32_t val;
 253
 254         mutex_lock(&adev->grbm_idx_mutex);
 255         if (se_num != 0xffffffff || sh_num != 0xffffffff)
 256                 amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff);
 257
 258         val = RREG32(reg_offset);
 259
 260         if (se_num != 0xffffffff || sh_num != 0xffffffff)
 261                 amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
 262         mutex_unlock(&adev->grbm_idx_mutex);
 263         return val;
 264 }
 265
 266 static uint32_t nv_get_register_value(struct amdgpu_device *adev,
 267                                       bool indexed, u32 se_num,
 268                                       u32 sh_num, u32 reg_offset)
 269 {
 270         if (indexed) {
 271                 return nv_read_indexed_register(adev, se_num, sh_num, reg_offset);
 272         } else {
 273                 if (reg_offset == SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG))
 274                         return adev->gfx.config.gb_addr_config;
 275                 return RREG32(reg_offset);
 276         }
 277 }
 278
 279 static int nv_read_register(struct amdgpu_device *adev, u32 se_num,
 280                             u32 sh_num, u32 reg_offset, u32 *value)
 281 {
 282         uint32_t i;
 283         struct soc15_allowed_register_entry  *en;
 284
 285         *value = 0;
 286         for (i = 0; i < ARRAY_SIZE(nv_allowed_read_registers); i++) {
 287                 en = &nv_allowed_read_registers[i];
 288                 if ((i == 7 && (adev->sdma.num_instances == 1)) || /* some asics don't have SDMA1 */
 289                     reg_offset !=
 290                     (adev->reg_offset[en->hwip][en->inst][en->seg] + en->reg_offset))
 291                         continue;
 292
 293                 *value = nv_get_register_value(adev,
 294                                                nv_allowed_read_registers[i].grbm_indexed,
 295                                                se_num, sh_num, reg_offset);
 296                 return 0;
 297         }
 298         return -EINVAL;
 299 }
 300
 301 static int nv_asic_mode1_reset(struct amdgpu_device *adev)
 302 {
 303         u32 i;
 304         int ret = 0;
 305
 306         amdgpu_atombios_scratch_regs_engine_hung(adev, true);
 307
 308         /* disable BM */
 309         pci_clear_master(adev->pdev);
 310
 311         amdgpu_device_cache_pci_state(adev->pdev);
 312
 313         if (amdgpu_dpm_is_mode1_reset_supported(adev)) {
 314                 dev_info(adev->dev, "GPU smu mode1 reset\n");
 315                 ret = amdgpu_dpm_mode1_reset(adev);
 316         } else {
 317                 dev_info(adev->dev, "GPU psp mode1 reset\n");
 318                 ret = psp_gpu_reset(adev);
 319         }
 320
 321         if (ret)
 322                 dev_err(adev->dev, "GPU mode1 reset failed\n");
 323         amdgpu_device_load_pci_state(adev->pdev);
 324
 325         /* wait for asic to come out of reset */
 326         for (i = 0; i < adev->usec_timeout; i++) {
 327                 u32 memsize = adev->nbio.funcs->get_memsize(adev);
 328
 329                 if (memsize != 0xffffffff)
 330                         break;
 331                 udelay(1);
 332         }
 333
 334         amdgpu_atombios_scratch_regs_engine_hung(adev, false);
 335
 336         return ret;
 337 }
 338
 339 static bool nv_asic_supports_baco(struct amdgpu_device *adev)
 340 {
 341         struct smu_context *smu = &adev->smu;
 342
 343         if (smu_baco_is_support(smu))
 344                 return true;
 345         else
 346                 return false;
 347 }
 348
 349 static enum amd_reset_method
 350 nv_asic_reset_method(struct amdgpu_device *adev)
 351 {
 352         struct smu_context *smu = &adev->smu;
 353
 354         if (amdgpu_reset_method == AMD_RESET_METHOD_MODE1 ||
 355             amdgpu_reset_method == AMD_RESET_METHOD_BACO)
 356                 return amdgpu_reset_method;
 357
 358         if (amdgpu_reset_method != -1)
 359                 dev_warn(adev->dev, "Specified reset method:%d isn't supported, using AUTO instead.\n",
 360                                   amdgpu_reset_method);
 361
 362         switch (adev->asic_type) {
 363         case CHIP_SIENNA_CICHLID:
 364         case CHIP_NAVY_FLOUNDER:
 365                 return AMD_RESET_METHOD_MODE1;
 366         default:
 367                 if (smu_baco_is_support(smu))
 368                         return AMD_RESET_METHOD_BACO;
 369                 else
 370                         return AMD_RESET_METHOD_MODE1;
 371         }
 372 }
 373
 374 static int nv_asic_reset(struct amdgpu_device *adev)
 375 {
 376         int ret = 0;
 377         struct smu_context *smu = &adev->smu;
 378
 379         if (nv_asic_reset_method(adev) == AMD_RESET_METHOD_BACO) {
 380                 dev_info(adev->dev, "BACO reset\n");
 381
 382                 ret = smu_baco_enter(smu);
 383                 if (ret)
 384                         return ret;
 385                 ret = smu_baco_exit(smu);
 386                 if (ret)
 387                         return ret;
 388         } else {
 389                 dev_info(adev->dev, "MODE1 reset\n");
 390                 ret = nv_asic_mode1_reset(adev);
 391         }
 392
 393         return ret;
 394 }
 395
 396 static int nv_set_uvd_clocks(struct amdgpu_device *adev, u32 vclk, u32 dclk)
 397 {
 398         /* todo */
 399         return 0;
 400 }
 401
 402 static int nv_set_vce_clocks(struct amdgpu_device *adev, u32 evclk, u32 ecclk)
 403 {
 404         /* todo */
 405         return 0;
 406 }
 407
 408 static void nv_pcie_gen3_enable(struct amdgpu_device *adev)
 409 {
 410         if (pci_is_root_bus(adev->pdev->bus))
 411                 return;
 412
 413         if (amdgpu_pcie_gen2 == 0)
 414                 return;
 415
 416         if (!(adev->pm.pcie_gen_mask & (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 |
 417                                         CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3)))
 418                 return;
 419
 420         /* todo */
 421 }
 422
 423 static void nv_program_aspm(struct amdgpu_device *adev)
 424 {
 425
 426         if (amdgpu_aspm == 0)
 427                 return;
 428
 429         /* todo */
 430 }
 431
 432 static void nv_enable_doorbell_aperture(struct amdgpu_device *adev,
 433                                         bool enable)
 434 {
 435         adev->nbio.funcs->enable_doorbell_aperture(adev, enable);
 436         adev->nbio.funcs->enable_doorbell_selfring_aperture(adev, enable);
 437 }
 438
 439 static const struct amdgpu_ip_block_version nv_common_ip_block =
 440 {
 441         .type = AMD_IP_BLOCK_TYPE_COMMON,
 442         .major = 1,
 443         .minor = 0,
 444         .rev = 0,
 445         .funcs = &nv_common_ip_funcs,
 446 };
 447
 448 static int nv_reg_base_init(struct amdgpu_device *adev)
 449 {
 450         int r;
 451
 452         /* IP discovery table is not available yet */
 453         if (adev->asic_type == CHIP_VANGOGH)
 454                 goto legacy_init;
 455
 456         if (amdgpu_discovery) {
 457                 r = amdgpu_discovery_reg_base_init(adev);
 458                 if (r) {
 459                         DRM_WARN("failed to init reg base from ip discovery table, "
 460                                         "fallback to legacy init method\n");
 461                         goto legacy_init;
 462                 }
 463
 464                 return 0;
 465         }
 466
 467 legacy_init:
 468         switch (adev->asic_type) {
 469         case CHIP_NAVI10:
 470                 navi10_reg_base_init(adev);
 471                 break;
 472         case CHIP_NAVI14:
 473                 navi14_reg_base_init(adev);
 474                 break;
 475         case CHIP_NAVI12:
 476                 navi12_reg_base_init(adev);
 477                 break;
 478         case CHIP_SIENNA_CICHLID:
 479         case CHIP_NAVY_FLOUNDER:
 480                 sienna_cichlid_reg_base_init(adev);
 481                 break;
 482         case CHIP_VANGOGH:
 483                 vangogh_reg_base_init(adev);
 484                 break;
 485         case CHIP_DIMGREY_CAVEFISH:
 486                 dimgrey_cavefish_reg_base_init(adev);
 487                 break;
 488         default:
 489                 return -EINVAL;
 490         }
 491
 492         return 0;
 493 }
 494
 495 void nv_set_virt_ops(struct amdgpu_device *adev)
 496 {
 497         adev->virt.ops = &xgpu_nv_virt_ops;
 498 }
 499
 500 int nv_set_ip_blocks(struct amdgpu_device *adev)
 501 {
 502         int r;
 503
 504         if (adev->flags & AMD_IS_APU) {
 505                 adev->nbio.funcs = &nbio_v7_2_funcs;
 506                 adev->nbio.hdp_flush_reg = &nbio_v7_2_hdp_flush_reg;
 507         } else {
 508                 adev->nbio.funcs = &nbio_v2_3_funcs;
 509                 adev->nbio.hdp_flush_reg = &nbio_v2_3_hdp_flush_reg;
 510         }
 511
 512         if (adev->asic_type == CHIP_SIENNA_CICHLID)
 513                 adev->gmc.xgmi.supported = true;
 514
 515         /* Set IP register base before any HW register access */
 516         r = nv_reg_base_init(adev);
 517         if (r)
 518                 return r;
 519
 520         switch (adev->asic_type) {
 521         case CHIP_NAVI10:
 522         case CHIP_NAVI14:
 523                 amdgpu_device_ip_block_add(adev, &nv_common_ip_block);
 524                 amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block);
 525                 amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block);
 526                 amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block);
 527                 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP &&
 528                     !amdgpu_sriov_vf(adev))
 529                         amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);
 530                 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))
 531                         amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
 532 #if defined(CONFIG_DRM_AMD_DC)
 533                 else if (amdgpu_device_has_dc_support(adev))
 534                         amdgpu_device_ip_block_add(adev, &dm_ip_block);
 535 #endif
 536                 amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block);
 537                 amdgpu_device_ip_block_add(adev, &sdma_v5_0_ip_block);
 538                 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT &&
 539                     !amdgpu_sriov_vf(adev))
 540                         amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);
 541                 amdgpu_device_ip_block_add(adev, &vcn_v2_0_ip_block);
 542                 amdgpu_device_ip_block_add(adev, &jpeg_v2_0_ip_block);
 543                 if (adev->enable_mes)
 544                         amdgpu_device_ip_block_add(adev, &mes_v10_1_ip_block);
 545                 break;
 546         case CHIP_NAVI12:
 547                 amdgpu_device_ip_block_add(adev, &nv_common_ip_block);
 548                 amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block);
 549                 amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block);
 550                 amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block);
 551                 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)
 552                         amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);
 553                 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))
 554                         amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
 555 #if defined(CONFIG_DRM_AMD_DC)
 556                 else if (amdgpu_device_has_dc_support(adev))
 557                         amdgpu_device_ip_block_add(adev, &dm_ip_block);
 558 #endif
 559                 amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block);
 560                 amdgpu_device_ip_block_add(adev, &sdma_v5_0_ip_block);
 561                 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT &&
 562                     !amdgpu_sriov_vf(adev))
 563                         amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);
 564                 amdgpu_device_ip_block_add(adev, &vcn_v2_0_ip_block);
 565                 if (!amdgpu_sriov_vf(adev))
 566                         amdgpu_device_ip_block_add(adev, &jpeg_v2_0_ip_block);
 567                 break;
 568         case CHIP_SIENNA_CICHLID:
 569                 amdgpu_device_ip_block_add(adev, &nv_common_ip_block);
 570                 amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block);
 571                 amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block);
 572                 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP))
 573                         amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block);
 574                 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP &&
 575                     is_support_sw_smu(adev) && !amdgpu_sriov_vf(adev))
 576                         amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);
 577                 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))
 578                         amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
 579 #if defined(CONFIG_DRM_AMD_DC)
 580                 else if (amdgpu_device_has_dc_support(adev))
 581                         amdgpu_device_ip_block_add(adev, &dm_ip_block);
 582 #endif
 583                 amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block);
 584                 amdgpu_device_ip_block_add(adev, &sdma_v5_2_ip_block);
 585                 amdgpu_device_ip_block_add(adev, &vcn_v3_0_ip_block);
 586                 if (!amdgpu_sriov_vf(adev))
 587                         amdgpu_device_ip_block_add(adev, &jpeg_v3_0_ip_block);
 588
 589                 if (adev->enable_mes)
 590                         amdgpu_device_ip_block_add(adev, &mes_v10_1_ip_block);
 591                 break;
 592         case CHIP_NAVY_FLOUNDER:
 593                 amdgpu_device_ip_block_add(adev, &nv_common_ip_block);
 594                 amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block);
 595                 amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block);
 596                 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP))
 597                         amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block);
 598                 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP &&
 599                     is_support_sw_smu(adev))
 600                         amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);
 601                 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))
 602                         amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
 603 #if defined(CONFIG_DRM_AMD_DC)
 604                 else if (amdgpu_device_has_dc_support(adev))
 605                         amdgpu_device_ip_block_add(adev, &dm_ip_block);
 606 #endif
 607                 amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block);
 608                 amdgpu_device_ip_block_add(adev, &sdma_v5_2_ip_block);
 609                 amdgpu_device_ip_block_add(adev, &vcn_v3_0_ip_block);
 610                 amdgpu_device_ip_block_add(adev, &jpeg_v3_0_ip_block);
 611                 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT &&
 612                     is_support_sw_smu(adev))
 613                         amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);
 614                 break;
 615         case CHIP_VANGOGH:
 616                 amdgpu_device_ip_block_add(adev, &nv_common_ip_block);
 617                 amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block);
 618                 amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block);
 619                 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP))
 620                         amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block);
 621                 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);
 622                 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))
 623                         amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
 624 #if defined(CONFIG_DRM_AMD_DC)
 625                 else if (amdgpu_device_has_dc_support(adev))
 626                         amdgpu_device_ip_block_add(adev, &dm_ip_block);
 627 #endif
 628                 amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block);
 629                 amdgpu_device_ip_block_add(adev, &sdma_v5_2_ip_block);
 630                 amdgpu_device_ip_block_add(adev, &vcn_v3_0_ip_block);
 631                 amdgpu_device_ip_block_add(adev, &jpeg_v3_0_ip_block);
 632                 break;
 633         case CHIP_DIMGREY_CAVEFISH:
 634                 amdgpu_device_ip_block_add(adev, &nv_common_ip_block);
 635                 amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block);
 636                 amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block);
 637                 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP))
 638                         amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block);
 639                 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP &&
 640                     is_support_sw_smu(adev))
 641                         amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);
 642                 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))
 643                         amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
 644 #if defined(CONFIG_DRM_AMD_DC)
 645                 else if (amdgpu_device_has_dc_support(adev))
 646                         amdgpu_device_ip_block_add(adev, &dm_ip_block);
 647 #endif
 648                 amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block);
 649                 amdgpu_device_ip_block_add(adev, &sdma_v5_2_ip_block);
 650                 amdgpu_device_ip_block_add(adev, &vcn_v3_0_ip_block);
 651                 amdgpu_device_ip_block_add(adev, &jpeg_v3_0_ip_block);
 652                 break;
 653         default:
 654                 return -EINVAL;
 655         }
 656
 657         return 0;
 658 }
 659
 660 static uint32_t nv_get_rev_id(struct amdgpu_device *adev)
 661 {
 662         return adev->nbio.funcs->get_rev_id(adev);
 663 }
 664
 665 static void nv_flush_hdp(struct amdgpu_device *adev, struct amdgpu_ring *ring)
 666 {
 667         adev->nbio.funcs->hdp_flush(adev, ring);
 668 }
 669
 670 static void nv_invalidate_hdp(struct amdgpu_device *adev,
 671                                 struct amdgpu_ring *ring)
 672 {
 673         if (!ring || !ring->funcs->emit_wreg) {
 674                 WREG32_SOC15_NO_KIQ(HDP, 0, mmHDP_READ_CACHE_INVALIDATE, 1);
 675         } else {
 676                 amdgpu_ring_emit_wreg(ring, SOC15_REG_OFFSET(
 677                                         HDP, 0, mmHDP_READ_CACHE_INVALIDATE), 1);
 678         }
 679 }
 680
 681 static bool nv_need_full_reset(struct amdgpu_device *adev)
 682 {
 683         return true;
 684 }
 685
 686 static bool nv_need_reset_on_init(struct amdgpu_device *adev)
 687 {
 688         u32 sol_reg;
 689
 690         if (adev->flags & AMD_IS_APU)
 691                 return false;
 692
 693         /* Check sOS sign of life register to confirm sys driver and sOS
 694          * are already been loaded.
 695          */
 696         sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81);
 697         if (sol_reg)
 698                 return true;
 699
 700         return false;
 701 }
 702
 703 static uint64_t nv_get_pcie_replay_count(struct amdgpu_device *adev)
 704 {
 705
 706         /* TODO
 707          * dummy implement for pcie_replay_count sysfs interface
 708          * */
 709
 710         return 0;
 711 }
 712
 713 static void nv_init_doorbell_index(struct amdgpu_device *adev)
 714 {
 715         adev->doorbell_index.kiq = AMDGPU_NAVI10_DOORBELL_KIQ;
 716         adev->doorbell_index.mec_ring0 = AMDGPU_NAVI10_DOORBELL_MEC_RING0;
 717         adev->doorbell_index.mec_ring1 = AMDGPU_NAVI10_DOORBELL_MEC_RING1;
 718         adev->doorbell_index.mec_ring2 = AMDGPU_NAVI10_DOORBELL_MEC_RING2;
 719         adev->doorbell_index.mec_ring3 = AMDGPU_NAVI10_DOORBELL_MEC_RING3;
 720         adev->doorbell_index.mec_ring4 = AMDGPU_NAVI10_DOORBELL_MEC_RING4;
 721         adev->doorbell_index.mec_ring5 = AMDGPU_NAVI10_DOORBELL_MEC_RING5;
 722         adev->doorbell_index.mec_ring6 = AMDGPU_NAVI10_DOORBELL_MEC_RING6;
 723         adev->doorbell_index.mec_ring7 = AMDGPU_NAVI10_DOORBELL_MEC_RING7;
 724         adev->doorbell_index.userqueue_start = AMDGPU_NAVI10_DOORBELL_USERQUEUE_START;
 725         adev->doorbell_index.userqueue_end = AMDGPU_NAVI10_DOORBELL_USERQUEUE_END;
 726         adev->doorbell_index.gfx_ring0 = AMDGPU_NAVI10_DOORBELL_GFX_RING0;
 727         adev->doorbell_index.gfx_ring1 = AMDGPU_NAVI10_DOORBELL_GFX_RING1;
 728         adev->doorbell_index.mes_ring = AMDGPU_NAVI10_DOORBELL_MES_RING;
 729         adev->doorbell_index.sdma_engine[0] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE0;
 730         adev->doorbell_index.sdma_engine[1] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE1;
 731         adev->doorbell_index.sdma_engine[2] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE2;
 732         adev->doorbell_index.sdma_engine[3] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE3;
 733         adev->doorbell_index.ih = AMDGPU_NAVI10_DOORBELL_IH;
 734         adev->doorbell_index.vcn.vcn_ring0_1 = AMDGPU_NAVI10_DOORBELL64_VCN0_1;
 735         adev->doorbell_index.vcn.vcn_ring2_3 = AMDGPU_NAVI10_DOORBELL64_VCN2_3;
 736         adev->doorbell_index.vcn.vcn_ring4_5 = AMDGPU_NAVI10_DOORBELL64_VCN4_5;
 737         adev->doorbell_index.vcn.vcn_ring6_7 = AMDGPU_NAVI10_DOORBELL64_VCN6_7;
 738         adev->doorbell_index.first_non_cp = AMDGPU_NAVI10_DOORBELL64_FIRST_NON_CP;
 739         adev->doorbell_index.last_non_cp = AMDGPU_NAVI10_DOORBELL64_LAST_NON_CP;
 740
 741         adev->doorbell_index.max_assignment = AMDGPU_NAVI10_DOORBELL_MAX_ASSIGNMENT << 1;
 742         adev->doorbell_index.sdma_doorbell_range = 20;
 743 }
 744
 745 static void nv_pre_asic_init(struct amdgpu_device *adev)
 746 {
 747 }
 748
 749 static int nv_update_umd_stable_pstate(struct amdgpu_device *adev,
 750                                        bool enter)
 751 {
 752         if (enter)
 753                 amdgpu_gfx_rlc_enter_safe_mode(adev);
 754         else
 755                 amdgpu_gfx_rlc_exit_safe_mode(adev);
 756
 757         if (adev->gfx.funcs->update_perfmon_mgcg)
 758                 adev->gfx.funcs->update_perfmon_mgcg(adev, !enter);
 759
 760         /*
 761          * The ASPM function is not fully enabled and verified on
 762          * Navi yet. Temporarily skip this until ASPM enabled.
 763          */
 764 #if 0
 765         if (adev->nbio.funcs->enable_aspm)
 766                 adev->nbio.funcs->enable_aspm(adev, !enter);
 767 #endif
 768
 769         return 0;
 770 }
 771
 772 static const struct amdgpu_asic_funcs nv_asic_funcs =
 773 {
 774         .read_disabled_bios = &nv_read_disabled_bios,
 775         .read_bios_from_rom = &nv_read_bios_from_rom,
 776         .read_register = &nv_read_register,
 777         .reset = &nv_asic_reset,
 778         .reset_method = &nv_asic_reset_method,
 779         .set_vga_state = &nv_vga_set_state,
 780         .get_xclk = &nv_get_xclk,
 781         .set_uvd_clocks = &nv_set_uvd_clocks,
 782         .set_vce_clocks = &nv_set_vce_clocks,
 783         .get_config_memsize = &nv_get_config_memsize,
 784         .flush_hdp = &nv_flush_hdp,
 785         .invalidate_hdp = &nv_invalidate_hdp,
 786         .init_doorbell_index = &nv_init_doorbell_index,
 787         .need_full_reset = &nv_need_full_reset,
 788         .need_reset_on_init = &nv_need_reset_on_init,
 789         .get_pcie_replay_count = &nv_get_pcie_replay_count,
 790         .supports_baco = &nv_asic_supports_baco,
 791         .pre_asic_init = &nv_pre_asic_init,
 792         .update_umd_stable_pstate = &nv_update_umd_stable_pstate,
 793 };
 794
 795 static int nv_common_early_init(void *handle)
 796 {
 797 #define MMIO_REG_HOLE_OFFSET (0x80000 - PAGE_SIZE)
 798         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 799
 800         adev->rmmio_remap.reg_offset = MMIO_REG_HOLE_OFFSET;
 801         adev->rmmio_remap.bus_addr = adev->rmmio_base + MMIO_REG_HOLE_OFFSET;
 802         adev->smc_rreg = NULL;
 803         adev->smc_wreg = NULL;
 804         adev->pcie_rreg = &nv_pcie_rreg;
 805         adev->pcie_wreg = &nv_pcie_wreg;
 806         adev->pcie_rreg64 = &nv_pcie_rreg64;
 807         adev->pcie_wreg64 = &nv_pcie_wreg64;
 808         adev->pciep_rreg = &nv_pcie_port_rreg;
 809         adev->pciep_wreg = &nv_pcie_port_wreg;
 810
 811         /* TODO: will add them during VCN v2 implementation */
 812         adev->uvd_ctx_rreg = NULL;
 813         adev->uvd_ctx_wreg = NULL;
 814
 815         adev->didt_rreg = &nv_didt_rreg;
 816         adev->didt_wreg = &nv_didt_wreg;
 817
 818         adev->asic_funcs = &nv_asic_funcs;
 819
 820         adev->rev_id = nv_get_rev_id(adev);
 821         adev->external_rev_id = 0xff;
 822         switch (adev->asic_type) {
 823         case CHIP_NAVI10:
 824                 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
 825                         AMD_CG_SUPPORT_GFX_CGCG |
 826                         AMD_CG_SUPPORT_IH_CG |
 827                         AMD_CG_SUPPORT_HDP_MGCG |
 828                         AMD_CG_SUPPORT_HDP_LS |
 829                         AMD_CG_SUPPORT_SDMA_MGCG |
 830                         AMD_CG_SUPPORT_SDMA_LS |
 831                         AMD_CG_SUPPORT_MC_MGCG |
 832                         AMD_CG_SUPPORT_MC_LS |
 833                         AMD_CG_SUPPORT_ATHUB_MGCG |
 834                         AMD_CG_SUPPORT_ATHUB_LS |
 835                         AMD_CG_SUPPORT_VCN_MGCG |
 836                         AMD_CG_SUPPORT_JPEG_MGCG |
 837                         AMD_CG_SUPPORT_BIF_MGCG |
 838                         AMD_CG_SUPPORT_BIF_LS;
 839                 adev->pg_flags = AMD_PG_SUPPORT_VCN |
 840                         AMD_PG_SUPPORT_VCN_DPG |
 841                         AMD_PG_SUPPORT_JPEG |
 842                         AMD_PG_SUPPORT_ATHUB;
 843                 adev->external_rev_id = adev->rev_id + 0x1;
 844                 break;
 845         case CHIP_NAVI14:
 846                 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
 847                         AMD_CG_SUPPORT_GFX_CGCG |
 848                         AMD_CG_SUPPORT_IH_CG |
 849                         AMD_CG_SUPPORT_HDP_MGCG |
 850                         AMD_CG_SUPPORT_HDP_LS |
 851                         AMD_CG_SUPPORT_SDMA_MGCG |
 852                         AMD_CG_SUPPORT_SDMA_LS |
 853                         AMD_CG_SUPPORT_MC_MGCG |
 854                         AMD_CG_SUPPORT_MC_LS |
 855                         AMD_CG_SUPPORT_ATHUB_MGCG |
 856                         AMD_CG_SUPPORT_ATHUB_LS |
 857                         AMD_CG_SUPPORT_VCN_MGCG |
 858                         AMD_CG_SUPPORT_JPEG_MGCG |
 859                         AMD_CG_SUPPORT_BIF_MGCG |
 860                         AMD_CG_SUPPORT_BIF_LS;
 861                 adev->pg_flags = AMD_PG_SUPPORT_VCN |
 862                         AMD_PG_SUPPORT_JPEG |
 863                         AMD_PG_SUPPORT_VCN_DPG;
 864                 adev->external_rev_id = adev->rev_id + 20;
 865                 break;
 866         case CHIP_NAVI12:
 867                 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
 868                         AMD_CG_SUPPORT_GFX_MGLS |
 869                         AMD_CG_SUPPORT_GFX_CGCG |
 870                         AMD_CG_SUPPORT_GFX_CP_LS |
 871                         AMD_CG_SUPPORT_GFX_RLC_LS |
 872                         AMD_CG_SUPPORT_IH_CG |
 873                         AMD_CG_SUPPORT_HDP_MGCG |
 874                         AMD_CG_SUPPORT_HDP_LS |
 875                         AMD_CG_SUPPORT_SDMA_MGCG |
 876                         AMD_CG_SUPPORT_SDMA_LS |
 877                         AMD_CG_SUPPORT_MC_MGCG |
 878                         AMD_CG_SUPPORT_MC_LS |
 879                         AMD_CG_SUPPORT_ATHUB_MGCG |
 880                         AMD_CG_SUPPORT_ATHUB_LS |
 881                         AMD_CG_SUPPORT_VCN_MGCG |
 882                         AMD_CG_SUPPORT_JPEG_MGCG;
 883                 adev->pg_flags = AMD_PG_SUPPORT_VCN |
 884                         AMD_PG_SUPPORT_VCN_DPG |
 885                         AMD_PG_SUPPORT_JPEG |
 886                         AMD_PG_SUPPORT_ATHUB;
 887                 /* guest vm gets 0xffffffff when reading RCC_DEV0_EPF0_STRAP0,
 888                  * as a consequence, the rev_id and external_rev_id are wrong.
 889                  * workaround it by hardcoding rev_id to 0 (default value).
 890                  */
 891                 if (amdgpu_sriov_vf(adev))
 892                         adev->rev_id = 0;
 893                 adev->external_rev_id = adev->rev_id + 0xa;
 894                 break;
 895         case CHIP_SIENNA_CICHLID:
 896                 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
 897                         AMD_CG_SUPPORT_GFX_CGCG |
 898                         AMD_CG_SUPPORT_GFX_3D_CGCG |
 899                         AMD_CG_SUPPORT_MC_MGCG |
 900                         AMD_CG_SUPPORT_VCN_MGCG |
 901                         AMD_CG_SUPPORT_JPEG_MGCG |
 902                         AMD_CG_SUPPORT_HDP_MGCG |
 903                         AMD_CG_SUPPORT_HDP_LS |
 904                         AMD_CG_SUPPORT_IH_CG |
 905                         AMD_CG_SUPPORT_MC_LS;
 906                 adev->pg_flags = AMD_PG_SUPPORT_VCN |
 907                         AMD_PG_SUPPORT_VCN_DPG |
 908                         AMD_PG_SUPPORT_JPEG |
 909                         AMD_PG_SUPPORT_ATHUB |
 910                         AMD_PG_SUPPORT_MMHUB;
 911                 if (amdgpu_sriov_vf(adev)) {
 912                         /* hypervisor control CG and PG enablement */
 913                         adev->cg_flags = 0;
 914                         adev->pg_flags = 0;
 915                 }
 916                 adev->external_rev_id = adev->rev_id + 0x28;
 917                 break;
 918         case CHIP_NAVY_FLOUNDER:
 919                 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
 920                         AMD_CG_SUPPORT_GFX_CGCG |
 921                         AMD_CG_SUPPORT_GFX_3D_CGCG |
 922                         AMD_CG_SUPPORT_VCN_MGCG |
 923                         AMD_CG_SUPPORT_JPEG_MGCG |
 924                         AMD_CG_SUPPORT_MC_MGCG |
 925                         AMD_CG_SUPPORT_MC_LS |
 926                         AMD_CG_SUPPORT_HDP_MGCG |
 927                         AMD_CG_SUPPORT_HDP_LS |
 928                         AMD_CG_SUPPORT_IH_CG;
 929                 adev->pg_flags = AMD_PG_SUPPORT_VCN |
 930                         AMD_PG_SUPPORT_VCN_DPG |
 931                         AMD_PG_SUPPORT_JPEG |
 932                         AMD_PG_SUPPORT_ATHUB |
 933                         AMD_PG_SUPPORT_MMHUB;
 934                 adev->external_rev_id = adev->rev_id + 0x32;
 935                 break;
 936
 937         case CHIP_VANGOGH:
 938                 adev->cg_flags = AMD_CG_SUPPORT_GFX_CGCG |
 939                         AMD_CG_SUPPORT_GFX_CGLS |
 940                         AMD_CG_SUPPORT_GFX_3D_CGCG |
 941                         AMD_CG_SUPPORT_GFX_3D_CGLS;
 942                 adev->pg_flags = AMD_PG_SUPPORT_GFX_PG;
 943                 adev->external_rev_id = adev->rev_id + 0x01;
 944                 break;
 945         case CHIP_DIMGREY_CAVEFISH:
 946                 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
 947                         AMD_CG_SUPPORT_GFX_CGCG |
 948                         AMD_CG_SUPPORT_GFX_3D_CGCG |
 949                         AMD_CG_SUPPORT_VCN_MGCG |
 950                         AMD_CG_SUPPORT_JPEG_MGCG |
 951                         AMD_CG_SUPPORT_MC_MGCG |
 952                         AMD_CG_SUPPORT_MC_LS |
 953                         AMD_CG_SUPPORT_HDP_MGCG |
 954                         AMD_CG_SUPPORT_HDP_LS |
 955                         AMD_CG_SUPPORT_IH_CG;
 956                 adev->pg_flags = AMD_PG_SUPPORT_VCN |
 957                         AMD_PG_SUPPORT_VCN_DPG |
 958                         AMD_PG_SUPPORT_JPEG |
 959                         AMD_PG_SUPPORT_ATHUB |
 960                         AMD_PG_SUPPORT_MMHUB;
 961                 adev->external_rev_id = adev->rev_id + 0x3c;
 962                 break;
 963         default:
 964                 /* FIXME: not supported yet */
 965                 return -EINVAL;
 966         }
 967
 968         if (amdgpu_sriov_vf(adev)) {
 969                 amdgpu_virt_init_setting(adev);
 970                 xgpu_nv_mailbox_set_irq_funcs(adev);
 971         }
 972
 973         return 0;
 974 }
 975
 976 static int nv_common_late_init(void *handle)
 977 {
 978         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 979
 980         if (amdgpu_sriov_vf(adev))
 981                 xgpu_nv_mailbox_get_irq(adev);
 982
 983         return 0;
 984 }
 985
 986 static int nv_common_sw_init(void *handle)
 987 {
 988         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 989
 990         if (amdgpu_sriov_vf(adev))
 991                 xgpu_nv_mailbox_add_irq_id(adev);
 992
 993         return 0;
 994 }
 995
 996 static int nv_common_sw_fini(void *handle)
 997 {
 998         return 0;
 999 }
1000
1001 static int nv_common_hw_init(void *handle)
1002 {
1003         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1004
1005         /* enable pcie gen2/3 link */
1006         nv_pcie_gen3_enable(adev);
1007         /* enable aspm */
1008         nv_program_aspm(adev);
1009         /* setup nbio registers */
1010         adev->nbio.funcs->init_registers(adev);
1011         /* remap HDP registers to a hole in mmio space,
1012          * for the purpose of expose those registers
1013          * to process space
1014          */
1015         if (adev->nbio.funcs->remap_hdp_registers)
1016                 adev->nbio.funcs->remap_hdp_registers(adev);
1017         /* enable the doorbell aperture */
1018         nv_enable_doorbell_aperture(adev, true);
1019
1020         return 0;
1021 }
1022
1023 static int nv_common_hw_fini(void *handle)
1024 {
1025         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1026
1027         /* disable the doorbell aperture */
1028         nv_enable_doorbell_aperture(adev, false);
1029
1030         return 0;
1031 }
1032
1033 static int nv_common_suspend(void *handle)
1034 {
1035         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1036
1037         return nv_common_hw_fini(adev);
1038 }
1039
1040 static int nv_common_resume(void *handle)
1041 {
1042         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1043
1044         return nv_common_hw_init(adev);
1045 }
1046
1047 static bool nv_common_is_idle(void *handle)
1048 {
1049         return true;
1050 }
1051
1052 static int nv_common_wait_for_idle(void *handle)
1053 {
1054         return 0;
1055 }
1056
1057 static int nv_common_soft_reset(void *handle)
1058 {
1059         return 0;
1060 }
1061
1062 static void nv_update_hdp_mem_power_gating(struct amdgpu_device *adev,
1063                                            bool enable)
1064 {
1065         uint32_t hdp_clk_cntl, hdp_clk_cntl1;
1066         uint32_t hdp_mem_pwr_cntl;
1067
1068         if (!(adev->cg_flags & (AMD_CG_SUPPORT_HDP_LS |
1069                                 AMD_CG_SUPPORT_HDP_DS |
1070                                 AMD_CG_SUPPORT_HDP_SD)))
1071                 return;
1072
1073         hdp_clk_cntl = hdp_clk_cntl1 = RREG32_SOC15(HDP, 0, mmHDP_CLK_CNTL);
1074         hdp_mem_pwr_cntl = RREG32_SOC15(HDP, 0, mmHDP_MEM_POWER_CTRL);
1075
1076         /* Before doing clock/power mode switch,
1077          * forced on IPH & RC clock */
1078         hdp_clk_cntl = REG_SET_FIELD(hdp_clk_cntl, HDP_CLK_CNTL,
1079                                      IPH_MEM_CLK_SOFT_OVERRIDE, 1);
1080         hdp_clk_cntl = REG_SET_FIELD(hdp_clk_cntl, HDP_CLK_CNTL,
1081                                      RC_MEM_CLK_SOFT_OVERRIDE, 1);
1082         WREG32_SOC15(HDP, 0, mmHDP_CLK_CNTL, hdp_clk_cntl);
1083
1084         /* HDP 5.0 doesn't support dynamic power mode switch,
1085          * disable clock and power gating before any changing */
1086         hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,
1087                                          IPH_MEM_POWER_CTRL_EN, 0);
1088         hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,
1089                                          IPH_MEM_POWER_LS_EN, 0);
1090         hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,
1091                                          IPH_MEM_POWER_DS_EN, 0);
1092         hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,
1093                                          IPH_MEM_POWER_SD_EN, 0);
1094         hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,
1095                                          RC_MEM_POWER_CTRL_EN, 0);
1096         hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,
1097                                          RC_MEM_POWER_LS_EN, 0);
1098         hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,
1099                                          RC_MEM_POWER_DS_EN, 0);
1100         hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,
1101                                          RC_MEM_POWER_SD_EN, 0);
1102         WREG32_SOC15(HDP, 0, mmHDP_MEM_POWER_CTRL, hdp_mem_pwr_cntl);
1103
1104         /* only one clock gating mode (LS/DS/SD) can be enabled */
1105         if (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS) {
1106                 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl,
1107                                                  HDP_MEM_POWER_CTRL,
1108                                                  IPH_MEM_POWER_LS_EN, enable);
1109                 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl,
1110                                                  HDP_MEM_POWER_CTRL,
1111                                                  RC_MEM_POWER_LS_EN, enable);
1112         } else if (adev->cg_flags & AMD_CG_SUPPORT_HDP_DS) {
1113                 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl,
1114                                                  HDP_MEM_POWER_CTRL,
1115                                                  IPH_MEM_POWER_DS_EN, enable);
1116                 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl,
1117                                                  HDP_MEM_POWER_CTRL,
1118                                                  RC_MEM_POWER_DS_EN, enable);
1119         } else if (adev->cg_flags & AMD_CG_SUPPORT_HDP_SD) {
1120                 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl,
1121                                                  HDP_MEM_POWER_CTRL,
1122                                                  IPH_MEM_POWER_SD_EN, enable);
1123                 /* RC should not use shut down mode, fallback to ds */
1124                 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl,
1125                                                  HDP_MEM_POWER_CTRL,
1126                                                  RC_MEM_POWER_DS_EN, enable);
1127         }
1128
1129         /* confirmed that IPH_MEM_POWER_CTRL_EN and RC_MEM_POWER_CTRL_EN have to
1130          * be set for SRAM LS/DS/SD */
1131         if (adev->cg_flags & (AMD_CG_SUPPORT_HDP_LS | AMD_CG_SUPPORT_HDP_DS |
1132                                                         AMD_CG_SUPPORT_HDP_SD)) {
1133                 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,
1134                                                 IPH_MEM_POWER_CTRL_EN, 1);
1135                 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,
1136                                                 RC_MEM_POWER_CTRL_EN, 1);
1137         }
1138
1139         WREG32_SOC15(HDP, 0, mmHDP_MEM_POWER_CTRL, hdp_mem_pwr_cntl);
1140
1141         /* restore IPH & RC clock override after clock/power mode changing */
1142         WREG32_SOC15(HDP, 0, mmHDP_CLK_CNTL, hdp_clk_cntl1);
1143 }
1144
1145 static void nv_update_hdp_clock_gating(struct amdgpu_device *adev,
1146                                        bool enable)
1147 {
1148         uint32_t hdp_clk_cntl;
1149
1150         if (!(adev->cg_flags & AMD_CG_SUPPORT_HDP_MGCG))
1151                 return;
1152
1153         hdp_clk_cntl = RREG32_SOC15(HDP, 0, mmHDP_CLK_CNTL);
1154
1155         if (enable) {
1156                 hdp_clk_cntl &=
1157                         ~(uint32_t)
1158                           (HDP_CLK_CNTL__IPH_MEM_CLK_SOFT_OVERRIDE_MASK |
1159                            HDP_CLK_CNTL__RC_MEM_CLK_SOFT_OVERRIDE_MASK |
1160                            HDP_CLK_CNTL__DBUS_CLK_SOFT_OVERRIDE_MASK |
1161                            HDP_CLK_CNTL__DYN_CLK_SOFT_OVERRIDE_MASK |
1162                            HDP_CLK_CNTL__XDP_REG_CLK_SOFT_OVERRIDE_MASK |
1163                            HDP_CLK_CNTL__HDP_REG_CLK_SOFT_OVERRIDE_MASK);
1164         } else {
1165                 hdp_clk_cntl |= HDP_CLK_CNTL__IPH_MEM_CLK_SOFT_OVERRIDE_MASK |
1166                         HDP_CLK_CNTL__RC_MEM_CLK_SOFT_OVERRIDE_MASK |
1167                         HDP_CLK_CNTL__DBUS_CLK_SOFT_OVERRIDE_MASK |
1168                         HDP_CLK_CNTL__DYN_CLK_SOFT_OVERRIDE_MASK |
1169                         HDP_CLK_CNTL__XDP_REG_CLK_SOFT_OVERRIDE_MASK |
1170                         HDP_CLK_CNTL__HDP_REG_CLK_SOFT_OVERRIDE_MASK;
1171         }
1172
1173         WREG32_SOC15(HDP, 0, mmHDP_CLK_CNTL, hdp_clk_cntl);
1174 }
1175
1176 static int nv_common_set_clockgating_state(void *handle,
1177                                            enum amd_clockgating_state state)
1178 {
1179         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1180
1181         if (amdgpu_sriov_vf(adev))
1182                 return 0;
1183
1184         switch (adev->asic_type) {
1185         case CHIP_NAVI10:
1186         case CHIP_NAVI14:
1187         case CHIP_NAVI12:
1188         case CHIP_SIENNA_CICHLID:
1189         case CHIP_NAVY_FLOUNDER:
1190         case CHIP_DIMGREY_CAVEFISH:
1191                 adev->nbio.funcs->update_medium_grain_clock_gating(adev,
1192                                 state == AMD_CG_STATE_GATE);
1193                 adev->nbio.funcs->update_medium_grain_light_sleep(adev,
1194                                 state == AMD_CG_STATE_GATE);
1195                 nv_update_hdp_mem_power_gating(adev,
1196                                    state == AMD_CG_STATE_GATE);
1197                 nv_update_hdp_clock_gating(adev,
1198                                 state == AMD_CG_STATE_GATE);
1199                 break;
1200         default:
1201                 break;
1202         }
1203         return 0;
1204 }
1205
1206 static int nv_common_set_powergating_state(void *handle,
1207                                            enum amd_powergating_state state)
1208 {
1209         /* TODO */
1210         return 0;
1211 }
1212
1213 static void nv_common_get_clockgating_state(void *handle, u32 *flags)
1214 {
1215         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1216         uint32_t tmp;
1217
1218         if (amdgpu_sriov_vf(adev))
1219                 *flags = 0;
1220
1221         adev->nbio.funcs->get_clockgating_state(adev, flags);
1222
1223         /* AMD_CG_SUPPORT_HDP_MGCG */
1224         tmp = RREG32_SOC15(HDP, 0, mmHDP_CLK_CNTL);
1225         if (!(tmp & (HDP_CLK_CNTL__IPH_MEM_CLK_SOFT_OVERRIDE_MASK |
1226                      HDP_CLK_CNTL__RC_MEM_CLK_SOFT_OVERRIDE_MASK |
1227                      HDP_CLK_CNTL__DBUS_CLK_SOFT_OVERRIDE_MASK |
1228                      HDP_CLK_CNTL__DYN_CLK_SOFT_OVERRIDE_MASK |
1229                      HDP_CLK_CNTL__XDP_REG_CLK_SOFT_OVERRIDE_MASK |
1230                      HDP_CLK_CNTL__HDP_REG_CLK_SOFT_OVERRIDE_MASK)))
1231                 *flags |= AMD_CG_SUPPORT_HDP_MGCG;
1232
1233         /* AMD_CG_SUPPORT_HDP_LS/DS/SD */
1234         tmp = RREG32_SOC15(HDP, 0, mmHDP_MEM_POWER_CTRL);
1235         if (tmp & HDP_MEM_POWER_CTRL__IPH_MEM_POWER_LS_EN_MASK)
1236                 *flags |= AMD_CG_SUPPORT_HDP_LS;
1237         else if (tmp & HDP_MEM_POWER_CTRL__IPH_MEM_POWER_DS_EN_MASK)
1238                 *flags |= AMD_CG_SUPPORT_HDP_DS;
1239         else if (tmp & HDP_MEM_POWER_CTRL__IPH_MEM_POWER_SD_EN_MASK)
1240                 *flags |= AMD_CG_SUPPORT_HDP_SD;
1241
1242         return;
1243 }
1244
1245 static const struct amd_ip_funcs nv_common_ip_funcs = {
1246         .name = "nv_common",
1247         .early_init = nv_common_early_init,
1248         .late_init = nv_common_late_init,
1249         .sw_init = nv_common_sw_init,
1250         .sw_fini = nv_common_sw_fini,
1251         .hw_init = nv_common_hw_init,
1252         .hw_fini = nv_common_hw_fini,
1253         .suspend = nv_common_suspend,
1254         .resume = nv_common_resume,
1255         .is_idle = nv_common_is_idle,
1256         .wait_for_idle = nv_common_wait_for_idle,
1257         .soft_reset = nv_common_soft_reset,
1258         .set_clockgating_state = nv_common_set_clockgating_state,
1259         .set_powergating_state = nv_common_set_powergating_state,
1260         .get_clockgating_state = nv_common_get_clockgating_state,
1261 };