drivers/gpu/drm/amd/amdgpu/nbio_v7_7.c

   1 /*
   2  * Copyright 2021 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23 #include "amdgpu.h"
  24 #include "amdgpu_atombios.h"
  25 #include "nbio_v7_7.h"
  26
  27 #include "nbio/nbio_7_7_0_offset.h"
  28 #include "nbio/nbio_7_7_0_sh_mask.h"
  29 #include <uapi/linux/kfd_ioctl.h>
  30
  31 static u32 nbio_v7_7_get_rev_id(struct amdgpu_device *adev)
  32 {
  33         u32 tmp;
  34
  35         tmp = RREG32_SOC15(NBIO, 0, regRCC_STRAP0_RCC_DEV0_EPF0_STRAP0);
  36         tmp &= RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0_MASK;
  37         tmp >>= RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0__SHIFT;
  38
  39         return tmp;
  40 }
  41
  42 static void nbio_v7_7_mc_access_enable(struct amdgpu_device *adev, bool enable)
  43 {
  44         if (enable)
  45                 WREG32_SOC15(NBIO, 0, regBIF_BX1_BIF_FB_EN,
  46                         BIF_BX1_BIF_FB_EN__FB_READ_EN_MASK |
  47                         BIF_BX1_BIF_FB_EN__FB_WRITE_EN_MASK);
  48         else
  49                 WREG32_SOC15(NBIO, 0, regBIF_BX1_BIF_FB_EN, 0);
  50 }
  51
  52 static u32 nbio_v7_7_get_memsize(struct amdgpu_device *adev)
  53 {
  54         return RREG32_SOC15(NBIO, 0, regRCC_DEV0_EPF0_0_RCC_CONFIG_MEMSIZE);
  55 }
  56
  57 static void nbio_v7_7_sdma_doorbell_range(struct amdgpu_device *adev, int instance,
  58                                           bool use_doorbell, int doorbell_index,
  59                                           int doorbell_size)
  60 {
  61         u32 reg = SOC15_REG_OFFSET(NBIO, 0, regGDC0_BIF_CSDMA_DOORBELL_RANGE);
  62         u32 doorbell_range = RREG32_PCIE_PORT(reg);
  63
  64         if (use_doorbell) {
  65                 doorbell_range = REG_SET_FIELD(doorbell_range,
  66                                                GDC0_BIF_CSDMA_DOORBELL_RANGE,
  67                                                OFFSET, doorbell_index);
  68                 doorbell_range = REG_SET_FIELD(doorbell_range,
  69                                                GDC0_BIF_CSDMA_DOORBELL_RANGE,
  70                                                SIZE, doorbell_size);
  71                 doorbell_range = REG_SET_FIELD(doorbell_range,
  72                                                GDC0_BIF_SDMA0_DOORBELL_RANGE,
  73                                                OFFSET, doorbell_index);
  74                 doorbell_range = REG_SET_FIELD(doorbell_range,
  75                                                GDC0_BIF_SDMA0_DOORBELL_RANGE,
  76                                                SIZE, doorbell_size);
  77         } else {
  78                 doorbell_range = REG_SET_FIELD(doorbell_range,
  79                                                GDC0_BIF_SDMA0_DOORBELL_RANGE,
  80                                                SIZE, 0);
  81         }
  82
  83         WREG32_PCIE_PORT(reg, doorbell_range);
  84 }
  85
  86 static void nbio_v7_7_enable_doorbell_aperture(struct amdgpu_device *adev,
  87                                                bool enable)
  88 {
  89         u32 reg;
  90
  91         reg = RREG32_SOC15(NBIO, 0, regRCC_DEV0_EPF0_0_RCC_DOORBELL_APER_EN);
  92         reg = REG_SET_FIELD(reg, RCC_DEV0_EPF0_0_RCC_DOORBELL_APER_EN,
  93                             BIF_DOORBELL_APER_EN, enable ? 1 : 0);
  94
  95         WREG32_SOC15(NBIO, 0, regRCC_DEV0_EPF0_0_RCC_DOORBELL_APER_EN, reg);
  96 }
  97
  98 static void nbio_v7_7_enable_doorbell_selfring_aperture(struct amdgpu_device *adev,
  99                                                         bool enable)
 100 {
 101         u32 tmp = 0;
 102
 103         if (enable) {
 104                 tmp = REG_SET_FIELD(tmp, BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL,
 105                                 DOORBELL_SELFRING_GPA_APER_EN, 1) |
 106                         REG_SET_FIELD(tmp, BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL,
 107                                 DOORBELL_SELFRING_GPA_APER_MODE, 1) |
 108                         REG_SET_FIELD(tmp, BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL,
 109                                 DOORBELL_SELFRING_GPA_APER_SIZE, 0);
 110
 111                 WREG32_SOC15(NBIO, 0,
 112                         regBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_LOW,
 113                         lower_32_bits(adev->doorbell.base));
 114                 WREG32_SOC15(NBIO, 0,
 115                         regBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH,
 116                         upper_32_bits(adev->doorbell.base));
 117         }
 118
 119         WREG32_SOC15(NBIO, 0, regBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL,
 120                 tmp);
 121 }
 122
 123
 124 static void nbio_v7_7_ih_doorbell_range(struct amdgpu_device *adev,
 125                                         bool use_doorbell, int doorbell_index)
 126 {
 127         u32 ih_doorbell_range = RREG32_SOC15(NBIO, 0,
 128                                                                 regGDC0_BIF_IH_DOORBELL_RANGE);
 129
 130         if (use_doorbell) {
 131                 ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range,
 132                                                   GDC0_BIF_IH_DOORBELL_RANGE, OFFSET,
 133                                                   doorbell_index);
 134                 ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range,
 135                                                   GDC0_BIF_IH_DOORBELL_RANGE, SIZE,
 136                                                   2);
 137         } else {
 138                 ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range,
 139                                                   GDC0_BIF_IH_DOORBELL_RANGE, SIZE,
 140                                                   0);
 141         }
 142
 143         WREG32_SOC15(NBIO, 0, regGDC0_BIF_IH_DOORBELL_RANGE,
 144                          ih_doorbell_range);
 145 }
 146
 147 static void nbio_v7_7_ih_control(struct amdgpu_device *adev)
 148 {
 149         u32 interrupt_cntl;
 150
 151         /* setup interrupt control */
 152         WREG32_SOC15(NBIO, 0, regBIF_BX1_INTERRUPT_CNTL2,
 153                      adev->dummy_page_addr >> 8);
 154
 155         interrupt_cntl = RREG32_SOC15(NBIO, 0, regBIF_BX1_INTERRUPT_CNTL);
 156         /*
 157          * INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK=0 - dummy read disabled with msi, enabled without msi
 158          * INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK=1 - dummy read controlled by IH_DUMMY_RD_EN
 159          */
 160         interrupt_cntl = REG_SET_FIELD(interrupt_cntl, BIF_BX1_INTERRUPT_CNTL,
 161                                        IH_DUMMY_RD_OVERRIDE, 0);
 162
 163         /* INTERRUPT_CNTL__IH_REQ_NONSNOOP_EN_MASK=1 if ring is in non-cacheable memory, e.g., vram */
 164         interrupt_cntl = REG_SET_FIELD(interrupt_cntl, BIF_BX1_INTERRUPT_CNTL,
 165                                        IH_REQ_NONSNOOP_EN, 0);
 166
 167         WREG32_SOC15(NBIO, 0, regBIF_BX1_INTERRUPT_CNTL, interrupt_cntl);
 168 }
 169
 170 static u32 nbio_v7_7_get_hdp_flush_req_offset(struct amdgpu_device *adev)
 171 {
 172         return SOC15_REG_OFFSET(NBIO, 0, regBIF_BX_PF0_GPU_HDP_FLUSH_REQ);
 173 }
 174
 175 static u32 nbio_v7_7_get_hdp_flush_done_offset(struct amdgpu_device *adev)
 176 {
 177         return SOC15_REG_OFFSET(NBIO, 0, regBIF_BX_PF0_GPU_HDP_FLUSH_DONE);
 178 }
 179
 180 static u32 nbio_v7_7_get_pcie_index_offset(struct amdgpu_device *adev)
 181 {
 182         return SOC15_REG_OFFSET(NBIO, 0, regBIF_BX0_PCIE_INDEX2);
 183 }
 184
 185 static u32 nbio_v7_7_get_pcie_data_offset(struct amdgpu_device *adev)
 186 {
 187         return SOC15_REG_OFFSET(NBIO, 0, regBIF_BX0_PCIE_DATA2);
 188 }
 189
 190 static u32 nbio_v7_7_get_pcie_port_index_offset(struct amdgpu_device *adev)
 191 {
 192         return SOC15_REG_OFFSET(NBIO, 0, regBIF_BX_PF0_RSMU_INDEX);
 193 }
 194
 195 static u32 nbio_v7_7_get_pcie_port_data_offset(struct amdgpu_device *adev)
 196 {
 197         return SOC15_REG_OFFSET(NBIO, 0, regBIF_BX_PF0_RSMU_DATA);
 198 }
 199
 200 const struct nbio_hdp_flush_reg nbio_v7_7_hdp_flush_reg = {
 201         .ref_and_mask_cp0 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP0_MASK,
 202         .ref_and_mask_cp1 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP1_MASK,
 203         .ref_and_mask_cp2 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP2_MASK,
 204         .ref_and_mask_cp3 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP3_MASK,
 205         .ref_and_mask_cp4 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP4_MASK,
 206         .ref_and_mask_cp5 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP5_MASK,
 207         .ref_and_mask_cp6 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP6_MASK,
 208         .ref_and_mask_cp7 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP7_MASK,
 209         .ref_and_mask_cp8 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP8_MASK,
 210         .ref_and_mask_cp9 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP9_MASK,
 211         .ref_and_mask_sdma0 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__SDMA0_MASK,
 212         .ref_and_mask_sdma1 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__SDMA1_MASK,
 213 };
 214
 215 static void nbio_v7_7_init_registers(struct amdgpu_device *adev)
 216 {
 217         uint32_t def, data;
 218
 219         def = data = RREG32_SOC15(NBIO, 0, regBIF0_PCIE_MST_CTRL_3);
 220         data = REG_SET_FIELD(data, BIF0_PCIE_MST_CTRL_3,
 221                              CI_SWUS_MAX_READ_REQUEST_SIZE_MODE, 1);
 222         data = REG_SET_FIELD(data, BIF0_PCIE_MST_CTRL_3,
 223                              CI_SWUS_MAX_READ_REQUEST_SIZE_PRIV, 1);
 224
 225         if (def != data)
 226                 WREG32_SOC15(NBIO, 0, regBIF0_PCIE_MST_CTRL_3, data);
 227
 228 }
 229
 230 const struct amdgpu_nbio_funcs nbio_v7_7_funcs = {
 231         .get_hdp_flush_req_offset = nbio_v7_7_get_hdp_flush_req_offset,
 232         .get_hdp_flush_done_offset = nbio_v7_7_get_hdp_flush_done_offset,
 233         .get_pcie_index_offset = nbio_v7_7_get_pcie_index_offset,
 234         .get_pcie_data_offset = nbio_v7_7_get_pcie_data_offset,
 235         .get_pcie_port_index_offset = nbio_v7_7_get_pcie_port_index_offset,
 236         .get_pcie_port_data_offset = nbio_v7_7_get_pcie_port_data_offset,
 237         .get_rev_id = nbio_v7_7_get_rev_id,
 238         .mc_access_enable = nbio_v7_7_mc_access_enable,
 239         .get_memsize = nbio_v7_7_get_memsize,
 240         .sdma_doorbell_range = nbio_v7_7_sdma_doorbell_range,
 241         .enable_doorbell_aperture = nbio_v7_7_enable_doorbell_aperture,
 242         .enable_doorbell_selfring_aperture = nbio_v7_7_enable_doorbell_selfring_aperture,
 243         .ih_doorbell_range = nbio_v7_7_ih_doorbell_range,
 244         .ih_control = nbio_v7_7_ih_control,
 245         .init_registers = nbio_v7_7_init_registers,
 246 };