2 * Copyright 2018 Advanced Micro Devices, Inc.
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5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
24 #include "amdgpu_atombios.h"
25 #include "nbio_v7_4.h"
27 #include "nbio/nbio_7_4_offset.h"
28 #include "nbio/nbio_7_4_sh_mask.h"
30 #define smnNBIF_MGCG_CTRL_LCLK 0x1013a21c
32 #define smnCPM_CONTROL 0x11180460
33 #define smnPCIE_CNTL2 0x11180070
35 static u32 nbio_v7_4_get_rev_id(struct amdgpu_device *adev)
37 u32 tmp = RREG32_SOC15(NBIO, 0, mmRCC_DEV0_EPF0_STRAP0);
39 tmp &= RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0_MASK;
40 tmp >>= RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0__SHIFT;
45 static void nbio_v7_4_mc_access_enable(struct amdgpu_device *adev, bool enable)
48 WREG32_SOC15(NBIO, 0, mmBIF_FB_EN,
49 BIF_FB_EN__FB_READ_EN_MASK | BIF_FB_EN__FB_WRITE_EN_MASK);
51 WREG32_SOC15(NBIO, 0, mmBIF_FB_EN, 0);
54 static void nbio_v7_4_hdp_flush(struct amdgpu_device *adev,
55 struct amdgpu_ring *ring)
57 if (!ring || !ring->funcs->emit_wreg)
58 WREG32_SOC15_NO_KIQ(NBIO, 0, mmHDP_MEM_COHERENCY_FLUSH_CNTL, 0);
60 amdgpu_ring_emit_wreg(ring, SOC15_REG_OFFSET(
61 NBIO, 0, mmHDP_MEM_COHERENCY_FLUSH_CNTL), 0);
64 static u32 nbio_v7_4_get_memsize(struct amdgpu_device *adev)
66 return RREG32_SOC15(NBIO, 0, mmRCC_CONFIG_MEMSIZE);
69 static void nbio_v7_4_sdma_doorbell_range(struct amdgpu_device *adev, int instance,
70 bool use_doorbell, int doorbell_index)
72 u32 reg = instance == 0 ? SOC15_REG_OFFSET(NBIO, 0, mmBIF_SDMA0_DOORBELL_RANGE) :
73 SOC15_REG_OFFSET(NBIO, 0, mmBIF_SDMA1_DOORBELL_RANGE);
75 u32 doorbell_range = RREG32(reg);
78 doorbell_range = REG_SET_FIELD(doorbell_range, BIF_SDMA0_DOORBELL_RANGE, OFFSET, doorbell_index);
79 doorbell_range = REG_SET_FIELD(doorbell_range, BIF_SDMA0_DOORBELL_RANGE, SIZE, 2);
81 doorbell_range = REG_SET_FIELD(doorbell_range, BIF_SDMA0_DOORBELL_RANGE, SIZE, 0);
83 WREG32(reg, doorbell_range);
86 static void nbio_v7_4_enable_doorbell_aperture(struct amdgpu_device *adev,
89 WREG32_FIELD15(NBIO, 0, RCC_DOORBELL_APER_EN, BIF_DOORBELL_APER_EN, enable ? 1 : 0);
92 static void nbio_v7_4_enable_doorbell_selfring_aperture(struct amdgpu_device *adev,
98 static void nbio_v7_4_ih_doorbell_range(struct amdgpu_device *adev,
99 bool use_doorbell, int doorbell_index)
101 u32 ih_doorbell_range = RREG32_SOC15(NBIO, 0 , mmBIF_IH_DOORBELL_RANGE);
104 ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range, BIF_IH_DOORBELL_RANGE, OFFSET, doorbell_index);
105 ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range, BIF_IH_DOORBELL_RANGE, SIZE, 2);
107 ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range, BIF_IH_DOORBELL_RANGE, SIZE, 0);
109 WREG32_SOC15(NBIO, 0, mmBIF_IH_DOORBELL_RANGE, ih_doorbell_range);
113 static void nbio_v7_4_update_medium_grain_clock_gating(struct amdgpu_device *adev,
116 //TODO: Add support for v7.4
119 static void nbio_v7_4_update_medium_grain_light_sleep(struct amdgpu_device *adev,
124 def = data = RREG32_PCIE(smnPCIE_CNTL2);
125 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_BIF_LS)) {
126 data |= (PCIE_CNTL2__SLV_MEM_LS_EN_MASK |
127 PCIE_CNTL2__MST_MEM_LS_EN_MASK |
128 PCIE_CNTL2__REPLAY_MEM_LS_EN_MASK);
130 data &= ~(PCIE_CNTL2__SLV_MEM_LS_EN_MASK |
131 PCIE_CNTL2__MST_MEM_LS_EN_MASK |
132 PCIE_CNTL2__REPLAY_MEM_LS_EN_MASK);
136 WREG32_PCIE(smnPCIE_CNTL2, data);
139 static void nbio_v7_4_get_clockgating_state(struct amdgpu_device *adev,
144 /* AMD_CG_SUPPORT_BIF_MGCG */
145 data = RREG32_PCIE(smnCPM_CONTROL);
146 if (data & CPM_CONTROL__LCLK_DYN_GATE_ENABLE_MASK)
147 *flags |= AMD_CG_SUPPORT_BIF_MGCG;
149 /* AMD_CG_SUPPORT_BIF_LS */
150 data = RREG32_PCIE(smnPCIE_CNTL2);
151 if (data & PCIE_CNTL2__SLV_MEM_LS_EN_MASK)
152 *flags |= AMD_CG_SUPPORT_BIF_LS;
155 static void nbio_v7_4_ih_control(struct amdgpu_device *adev)
159 /* setup interrupt control */
160 WREG32_SOC15(NBIO, 0, mmINTERRUPT_CNTL2, adev->dummy_page_addr >> 8);
161 interrupt_cntl = RREG32_SOC15(NBIO, 0, mmINTERRUPT_CNTL);
162 /* INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK=0 - dummy read disabled with msi, enabled without msi
163 * INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK=1 - dummy read controlled by IH_DUMMY_RD_EN
165 interrupt_cntl = REG_SET_FIELD(interrupt_cntl, INTERRUPT_CNTL, IH_DUMMY_RD_OVERRIDE, 0);
166 /* INTERRUPT_CNTL__IH_REQ_NONSNOOP_EN_MASK=1 if ring is in non-cacheable memory, e.g., vram */
167 interrupt_cntl = REG_SET_FIELD(interrupt_cntl, INTERRUPT_CNTL, IH_REQ_NONSNOOP_EN, 0);
168 WREG32_SOC15(NBIO, 0, mmINTERRUPT_CNTL, interrupt_cntl);
171 static u32 nbio_v7_4_get_hdp_flush_req_offset(struct amdgpu_device *adev)
173 return SOC15_REG_OFFSET(NBIO, 0, mmGPU_HDP_FLUSH_REQ);
176 static u32 nbio_v7_4_get_hdp_flush_done_offset(struct amdgpu_device *adev)
178 return SOC15_REG_OFFSET(NBIO, 0, mmGPU_HDP_FLUSH_DONE);
181 static u32 nbio_v7_4_get_pcie_index_offset(struct amdgpu_device *adev)
183 return SOC15_REG_OFFSET(NBIO, 0, mmPCIE_INDEX2);
186 static u32 nbio_v7_4_get_pcie_data_offset(struct amdgpu_device *adev)
188 return SOC15_REG_OFFSET(NBIO, 0, mmPCIE_DATA2);
191 static const struct nbio_hdp_flush_reg nbio_v7_4_hdp_flush_reg = {
192 .ref_and_mask_cp0 = GPU_HDP_FLUSH_DONE__CP0_MASK,
193 .ref_and_mask_cp1 = GPU_HDP_FLUSH_DONE__CP1_MASK,
194 .ref_and_mask_cp2 = GPU_HDP_FLUSH_DONE__CP2_MASK,
195 .ref_and_mask_cp3 = GPU_HDP_FLUSH_DONE__CP3_MASK,
196 .ref_and_mask_cp4 = GPU_HDP_FLUSH_DONE__CP4_MASK,
197 .ref_and_mask_cp5 = GPU_HDP_FLUSH_DONE__CP5_MASK,
198 .ref_and_mask_cp6 = GPU_HDP_FLUSH_DONE__CP6_MASK,
199 .ref_and_mask_cp7 = GPU_HDP_FLUSH_DONE__CP7_MASK,
200 .ref_and_mask_cp8 = GPU_HDP_FLUSH_DONE__CP8_MASK,
201 .ref_and_mask_cp9 = GPU_HDP_FLUSH_DONE__CP9_MASK,
202 .ref_and_mask_sdma0 = GPU_HDP_FLUSH_DONE__SDMA0_MASK,
203 .ref_and_mask_sdma1 = GPU_HDP_FLUSH_DONE__SDMA1_MASK,
206 static void nbio_v7_4_detect_hw_virt(struct amdgpu_device *adev)
210 reg = RREG32_SOC15(NBIO, 0, mmRCC_IOV_FUNC_IDENTIFIER);
212 adev->virt.caps |= AMDGPU_SRIOV_CAPS_IS_VF;
214 if (reg & 0x80000000)
215 adev->virt.caps |= AMDGPU_SRIOV_CAPS_ENABLE_IOV;
218 if (is_virtual_machine()) /* passthrough mode exclus sriov mod */
219 adev->virt.caps |= AMDGPU_PASSTHROUGH_MODE;
223 static void nbio_v7_4_init_registers(struct amdgpu_device *adev)
228 const struct amdgpu_nbio_funcs nbio_v7_4_funcs = {
229 .hdp_flush_reg = &nbio_v7_4_hdp_flush_reg,
230 .get_hdp_flush_req_offset = nbio_v7_4_get_hdp_flush_req_offset,
231 .get_hdp_flush_done_offset = nbio_v7_4_get_hdp_flush_done_offset,
232 .get_pcie_index_offset = nbio_v7_4_get_pcie_index_offset,
233 .get_pcie_data_offset = nbio_v7_4_get_pcie_data_offset,
234 .get_rev_id = nbio_v7_4_get_rev_id,
235 .mc_access_enable = nbio_v7_4_mc_access_enable,
236 .hdp_flush = nbio_v7_4_hdp_flush,
237 .get_memsize = nbio_v7_4_get_memsize,
238 .sdma_doorbell_range = nbio_v7_4_sdma_doorbell_range,
239 .enable_doorbell_aperture = nbio_v7_4_enable_doorbell_aperture,
240 .enable_doorbell_selfring_aperture = nbio_v7_4_enable_doorbell_selfring_aperture,
241 .ih_doorbell_range = nbio_v7_4_ih_doorbell_range,
242 .update_medium_grain_clock_gating = nbio_v7_4_update_medium_grain_clock_gating,
243 .update_medium_grain_light_sleep = nbio_v7_4_update_medium_grain_light_sleep,
244 .get_clockgating_state = nbio_v7_4_get_clockgating_state,
245 .ih_control = nbio_v7_4_ih_control,
246 .init_registers = nbio_v7_4_init_registers,
247 .detect_hw_virt = nbio_v7_4_detect_hw_virt,