2 * Copyright 2018 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
24 #include "amdgpu_atombios.h"
25 #include "nbio_v7_4.h"
26 #include "amdgpu_ras.h"
28 #include "nbio/nbio_7_4_offset.h"
29 #include "nbio/nbio_7_4_sh_mask.h"
30 #include "nbio/nbio_7_4_0_smn.h"
31 #include "ivsrcid/nbio/irqsrcs_nbif_7_4.h"
32 #include <uapi/linux/kfd_ioctl.h>
34 #define smnPCIE_LC_CNTL 0x11140280
35 #define smnPCIE_LC_CNTL3 0x111402d4
36 #define smnPCIE_LC_CNTL6 0x111402ec
37 #define smnPCIE_LC_CNTL7 0x111402f0
38 #define smnNBIF_MGCG_CTRL_LCLK 0x1013a21c
39 #define smnRCC_BIF_STRAP3 0x1012348c
40 #define RCC_BIF_STRAP3__STRAP_VLINK_ASPM_IDLE_TIMER_MASK 0x0000FFFFL
41 #define RCC_BIF_STRAP3__STRAP_VLINK_PM_L1_ENTRY_TIMER_MASK 0xFFFF0000L
42 #define smnRCC_BIF_STRAP5 0x10123494
43 #define RCC_BIF_STRAP5__STRAP_VLINK_LDN_ENTRY_TIMER_MASK 0x0000FFFFL
44 #define smnBIF_CFG_DEV0_EPF0_DEVICE_CNTL2 0x1014008c
45 #define BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__LTR_EN_MASK 0x0400L
46 #define smnBIF_CFG_DEV0_EPF0_PCIE_LTR_CAP 0x10140324
47 #define smnPSWUSP0_PCIE_LC_CNTL2 0x111402c4
48 #define smnRCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL 0x10123538
49 #define smnRCC_BIF_STRAP2 0x10123488
50 #define RCC_BIF_STRAP2__STRAP_LTR_IN_ASPML1_DIS_MASK 0x00004000L
51 #define RCC_BIF_STRAP3__STRAP_VLINK_ASPM_IDLE_TIMER__SHIFT 0x0
52 #define RCC_BIF_STRAP3__STRAP_VLINK_PM_L1_ENTRY_TIMER__SHIFT 0x10
53 #define RCC_BIF_STRAP5__STRAP_VLINK_LDN_ENTRY_TIMER__SHIFT 0x0
56 * These are nbio v7_4_1 registers mask. Temporarily define these here since
57 * nbio v7_4_1 header is incomplete.
59 #define GPU_HDP_FLUSH_DONE__RSVD_ENG0_MASK 0x00001000L
60 #define GPU_HDP_FLUSH_DONE__RSVD_ENG1_MASK 0x00002000L
61 #define GPU_HDP_FLUSH_DONE__RSVD_ENG2_MASK 0x00004000L
62 #define GPU_HDP_FLUSH_DONE__RSVD_ENG3_MASK 0x00008000L
63 #define GPU_HDP_FLUSH_DONE__RSVD_ENG4_MASK 0x00010000L
64 #define GPU_HDP_FLUSH_DONE__RSVD_ENG5_MASK 0x00020000L
66 #define mmBIF_MMSCH1_DOORBELL_RANGE 0x01dc
67 #define mmBIF_MMSCH1_DOORBELL_RANGE_BASE_IDX 2
68 //BIF_MMSCH1_DOORBELL_RANGE
69 #define BIF_MMSCH1_DOORBELL_RANGE__OFFSET__SHIFT 0x2
70 #define BIF_MMSCH1_DOORBELL_RANGE__SIZE__SHIFT 0x10
71 #define BIF_MMSCH1_DOORBELL_RANGE__OFFSET_MASK 0x00000FFCL
72 #define BIF_MMSCH1_DOORBELL_RANGE__SIZE_MASK 0x001F0000L
74 #define BIF_MMSCH1_DOORBELL_RANGE__OFFSET_MASK 0x00000FFCL
75 #define BIF_MMSCH1_DOORBELL_RANGE__SIZE_MASK 0x001F0000L
77 #define mmBIF_MMSCH1_DOORBELL_RANGE_ALDE 0x01d8
78 #define mmBIF_MMSCH1_DOORBELL_RANGE_ALDE_BASE_IDX 2
79 //BIF_MMSCH1_DOORBELL_ALDE_RANGE
80 #define BIF_MMSCH1_DOORBELL_RANGE_ALDE__OFFSET__SHIFT 0x2
81 #define BIF_MMSCH1_DOORBELL_RANGE_ALDE__SIZE__SHIFT 0x10
82 #define BIF_MMSCH1_DOORBELL_RANGE_ALDE__OFFSET_MASK 0x00000FFCL
83 #define BIF_MMSCH1_DOORBELL_RANGE_ALDE__SIZE_MASK 0x001F0000L
85 #define mmRCC_DEV0_EPF0_STRAP0_ALDE 0x0015
86 #define mmRCC_DEV0_EPF0_STRAP0_ALDE_BASE_IDX 2
88 #define mmBIF_DOORBELL_INT_CNTL_ALDE 0x3878
89 #define mmBIF_DOORBELL_INT_CNTL_ALDE_BASE_IDX 2
90 #define BIF_DOORBELL_INT_CNTL_ALDE__DOORBELL_INTERRUPT_DISABLE__SHIFT 0x18
91 #define BIF_DOORBELL_INT_CNTL_ALDE__DOORBELL_INTERRUPT_DISABLE_MASK 0x01000000L
93 static void nbio_v7_4_query_ras_error_count(struct amdgpu_device *adev,
94 void *ras_error_status);
96 static void nbio_v7_4_remap_hdp_registers(struct amdgpu_device *adev)
98 WREG32_SOC15(NBIO, 0, mmREMAP_HDP_MEM_FLUSH_CNTL,
99 adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL);
100 WREG32_SOC15(NBIO, 0, mmREMAP_HDP_REG_FLUSH_CNTL,
101 adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_REG_FLUSH_CNTL);
104 static u32 nbio_v7_4_get_rev_id(struct amdgpu_device *adev)
108 if (adev->asic_type == CHIP_ALDEBARAN)
109 tmp = RREG32_SOC15(NBIO, 0, mmRCC_DEV0_EPF0_STRAP0_ALDE);
111 tmp = RREG32_SOC15(NBIO, 0, mmRCC_DEV0_EPF0_STRAP0);
113 tmp &= RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0_MASK;
114 tmp >>= RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0__SHIFT;
119 static void nbio_v7_4_mc_access_enable(struct amdgpu_device *adev, bool enable)
122 WREG32_SOC15(NBIO, 0, mmBIF_FB_EN,
123 BIF_FB_EN__FB_READ_EN_MASK | BIF_FB_EN__FB_WRITE_EN_MASK);
125 WREG32_SOC15(NBIO, 0, mmBIF_FB_EN, 0);
128 static u32 nbio_v7_4_get_memsize(struct amdgpu_device *adev)
130 return RREG32_SOC15(NBIO, 0, mmRCC_CONFIG_MEMSIZE);
133 static void nbio_v7_4_sdma_doorbell_range(struct amdgpu_device *adev, int instance,
134 bool use_doorbell, int doorbell_index, int doorbell_size)
136 u32 reg, doorbell_range;
140 SOC15_REG_OFFSET(NBIO, 0, mmBIF_SDMA0_DOORBELL_RANGE);
143 * These registers address of SDMA2~7 is not consecutive
144 * from SDMA0~1. Need plus 4 dwords offset.
146 * BIF_SDMA0_DOORBELL_RANGE: 0x3bc0
147 * BIF_SDMA1_DOORBELL_RANGE: 0x3bc4
148 * BIF_SDMA2_DOORBELL_RANGE: 0x3bd8
149 + * BIF_SDMA4_DOORBELL_RANGE:
151 + * ALDEBARAN: 0x3be4
153 if (adev->asic_type == CHIP_ALDEBARAN && instance == 4)
154 reg = instance + 0x4 + 0x1 +
155 SOC15_REG_OFFSET(NBIO, 0,
156 mmBIF_SDMA0_DOORBELL_RANGE);
158 reg = instance + 0x4 +
159 SOC15_REG_OFFSET(NBIO, 0,
160 mmBIF_SDMA0_DOORBELL_RANGE);
163 doorbell_range = RREG32(reg);
166 doorbell_range = REG_SET_FIELD(doorbell_range, BIF_SDMA0_DOORBELL_RANGE, OFFSET, doorbell_index);
167 doorbell_range = REG_SET_FIELD(doorbell_range, BIF_SDMA0_DOORBELL_RANGE, SIZE, doorbell_size);
169 doorbell_range = REG_SET_FIELD(doorbell_range, BIF_SDMA0_DOORBELL_RANGE, SIZE, 0);
171 WREG32(reg, doorbell_range);
174 static void nbio_v7_4_vcn_doorbell_range(struct amdgpu_device *adev, bool use_doorbell,
175 int doorbell_index, int instance)
181 if (adev->asic_type == CHIP_ALDEBARAN)
182 reg = SOC15_REG_OFFSET(NBIO, 0, mmBIF_MMSCH1_DOORBELL_RANGE_ALDE);
184 reg = SOC15_REG_OFFSET(NBIO, 0, mmBIF_MMSCH1_DOORBELL_RANGE);
186 reg = SOC15_REG_OFFSET(NBIO, 0, mmBIF_MMSCH0_DOORBELL_RANGE);
188 doorbell_range = RREG32(reg);
191 doorbell_range = REG_SET_FIELD(doorbell_range,
192 BIF_MMSCH0_DOORBELL_RANGE, OFFSET,
194 doorbell_range = REG_SET_FIELD(doorbell_range,
195 BIF_MMSCH0_DOORBELL_RANGE, SIZE, 8);
197 doorbell_range = REG_SET_FIELD(doorbell_range,
198 BIF_MMSCH0_DOORBELL_RANGE, SIZE, 0);
200 WREG32(reg, doorbell_range);
203 static void nbio_v7_4_enable_doorbell_aperture(struct amdgpu_device *adev,
206 WREG32_FIELD15(NBIO, 0, RCC_DOORBELL_APER_EN, BIF_DOORBELL_APER_EN, enable ? 1 : 0);
209 static void nbio_v7_4_enable_doorbell_selfring_aperture(struct amdgpu_device *adev,
215 tmp = REG_SET_FIELD(tmp, DOORBELL_SELFRING_GPA_APER_CNTL, DOORBELL_SELFRING_GPA_APER_EN, 1) |
216 REG_SET_FIELD(tmp, DOORBELL_SELFRING_GPA_APER_CNTL, DOORBELL_SELFRING_GPA_APER_MODE, 1) |
217 REG_SET_FIELD(tmp, DOORBELL_SELFRING_GPA_APER_CNTL, DOORBELL_SELFRING_GPA_APER_SIZE, 0);
219 WREG32_SOC15(NBIO, 0, mmDOORBELL_SELFRING_GPA_APER_BASE_LOW,
220 lower_32_bits(adev->doorbell.base));
221 WREG32_SOC15(NBIO, 0, mmDOORBELL_SELFRING_GPA_APER_BASE_HIGH,
222 upper_32_bits(adev->doorbell.base));
225 WREG32_SOC15(NBIO, 0, mmDOORBELL_SELFRING_GPA_APER_CNTL, tmp);
228 static void nbio_v7_4_ih_doorbell_range(struct amdgpu_device *adev,
229 bool use_doorbell, int doorbell_index)
231 u32 ih_doorbell_range = RREG32_SOC15(NBIO, 0 , mmBIF_IH_DOORBELL_RANGE);
234 ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range, BIF_IH_DOORBELL_RANGE, OFFSET, doorbell_index);
235 ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range, BIF_IH_DOORBELL_RANGE, SIZE, 4);
237 ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range, BIF_IH_DOORBELL_RANGE, SIZE, 0);
239 WREG32_SOC15(NBIO, 0, mmBIF_IH_DOORBELL_RANGE, ih_doorbell_range);
243 static void nbio_v7_4_update_medium_grain_clock_gating(struct amdgpu_device *adev,
246 //TODO: Add support for v7.4
249 static void nbio_v7_4_update_medium_grain_light_sleep(struct amdgpu_device *adev,
254 def = data = RREG32_PCIE(smnPCIE_CNTL2);
255 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_BIF_LS)) {
256 data |= (PCIE_CNTL2__SLV_MEM_LS_EN_MASK |
257 PCIE_CNTL2__MST_MEM_LS_EN_MASK |
258 PCIE_CNTL2__REPLAY_MEM_LS_EN_MASK);
260 data &= ~(PCIE_CNTL2__SLV_MEM_LS_EN_MASK |
261 PCIE_CNTL2__MST_MEM_LS_EN_MASK |
262 PCIE_CNTL2__REPLAY_MEM_LS_EN_MASK);
266 WREG32_PCIE(smnPCIE_CNTL2, data);
269 static void nbio_v7_4_get_clockgating_state(struct amdgpu_device *adev,
274 /* AMD_CG_SUPPORT_BIF_MGCG */
275 data = RREG32_PCIE(smnCPM_CONTROL);
276 if (data & CPM_CONTROL__LCLK_DYN_GATE_ENABLE_MASK)
277 *flags |= AMD_CG_SUPPORT_BIF_MGCG;
279 /* AMD_CG_SUPPORT_BIF_LS */
280 data = RREG32_PCIE(smnPCIE_CNTL2);
281 if (data & PCIE_CNTL2__SLV_MEM_LS_EN_MASK)
282 *flags |= AMD_CG_SUPPORT_BIF_LS;
285 static void nbio_v7_4_ih_control(struct amdgpu_device *adev)
289 /* setup interrupt control */
290 WREG32_SOC15(NBIO, 0, mmINTERRUPT_CNTL2, adev->dummy_page_addr >> 8);
291 interrupt_cntl = RREG32_SOC15(NBIO, 0, mmINTERRUPT_CNTL);
292 /* INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK=0 - dummy read disabled with msi, enabled without msi
293 * INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK=1 - dummy read controlled by IH_DUMMY_RD_EN
295 interrupt_cntl = REG_SET_FIELD(interrupt_cntl, INTERRUPT_CNTL, IH_DUMMY_RD_OVERRIDE, 0);
296 /* INTERRUPT_CNTL__IH_REQ_NONSNOOP_EN_MASK=1 if ring is in non-cacheable memory, e.g., vram */
297 interrupt_cntl = REG_SET_FIELD(interrupt_cntl, INTERRUPT_CNTL, IH_REQ_NONSNOOP_EN, 0);
298 WREG32_SOC15(NBIO, 0, mmINTERRUPT_CNTL, interrupt_cntl);
301 static u32 nbio_v7_4_get_hdp_flush_req_offset(struct amdgpu_device *adev)
303 return SOC15_REG_OFFSET(NBIO, 0, mmGPU_HDP_FLUSH_REQ);
306 static u32 nbio_v7_4_get_hdp_flush_done_offset(struct amdgpu_device *adev)
308 return SOC15_REG_OFFSET(NBIO, 0, mmGPU_HDP_FLUSH_DONE);
311 static u32 nbio_v7_4_get_pcie_index_offset(struct amdgpu_device *adev)
313 return SOC15_REG_OFFSET(NBIO, 0, mmPCIE_INDEX2);
316 static u32 nbio_v7_4_get_pcie_data_offset(struct amdgpu_device *adev)
318 return SOC15_REG_OFFSET(NBIO, 0, mmPCIE_DATA2);
321 const struct nbio_hdp_flush_reg nbio_v7_4_hdp_flush_reg = {
322 .ref_and_mask_cp0 = GPU_HDP_FLUSH_DONE__CP0_MASK,
323 .ref_and_mask_cp1 = GPU_HDP_FLUSH_DONE__CP1_MASK,
324 .ref_and_mask_cp2 = GPU_HDP_FLUSH_DONE__CP2_MASK,
325 .ref_and_mask_cp3 = GPU_HDP_FLUSH_DONE__CP3_MASK,
326 .ref_and_mask_cp4 = GPU_HDP_FLUSH_DONE__CP4_MASK,
327 .ref_and_mask_cp5 = GPU_HDP_FLUSH_DONE__CP5_MASK,
328 .ref_and_mask_cp6 = GPU_HDP_FLUSH_DONE__CP6_MASK,
329 .ref_and_mask_cp7 = GPU_HDP_FLUSH_DONE__CP7_MASK,
330 .ref_and_mask_cp8 = GPU_HDP_FLUSH_DONE__CP8_MASK,
331 .ref_and_mask_cp9 = GPU_HDP_FLUSH_DONE__CP9_MASK,
332 .ref_and_mask_sdma0 = GPU_HDP_FLUSH_DONE__SDMA0_MASK,
333 .ref_and_mask_sdma1 = GPU_HDP_FLUSH_DONE__SDMA1_MASK,
334 .ref_and_mask_sdma2 = GPU_HDP_FLUSH_DONE__RSVD_ENG0_MASK,
335 .ref_and_mask_sdma3 = GPU_HDP_FLUSH_DONE__RSVD_ENG1_MASK,
336 .ref_and_mask_sdma4 = GPU_HDP_FLUSH_DONE__RSVD_ENG2_MASK,
337 .ref_and_mask_sdma5 = GPU_HDP_FLUSH_DONE__RSVD_ENG3_MASK,
338 .ref_and_mask_sdma6 = GPU_HDP_FLUSH_DONE__RSVD_ENG4_MASK,
339 .ref_and_mask_sdma7 = GPU_HDP_FLUSH_DONE__RSVD_ENG5_MASK,
342 static void nbio_v7_4_init_registers(struct amdgpu_device *adev)
347 static void nbio_v7_4_handle_ras_controller_intr_no_bifring(struct amdgpu_device *adev)
349 uint32_t bif_doorbell_intr_cntl;
350 struct ras_manager *obj = amdgpu_ras_find_obj(adev, adev->nbio.ras_if);
351 struct ras_err_data err_data = {0, 0, 0, NULL};
352 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
354 if (adev->asic_type == CHIP_ALDEBARAN)
355 bif_doorbell_intr_cntl = RREG32_SOC15(NBIO, 0, mmBIF_DOORBELL_INT_CNTL_ALDE);
357 bif_doorbell_intr_cntl = RREG32_SOC15(NBIO, 0, mmBIF_DOORBELL_INT_CNTL);
359 if (REG_GET_FIELD(bif_doorbell_intr_cntl,
360 BIF_DOORBELL_INT_CNTL, RAS_CNTLR_INTERRUPT_STATUS)) {
361 /* driver has to clear the interrupt status when bif ring is disabled */
362 bif_doorbell_intr_cntl = REG_SET_FIELD(bif_doorbell_intr_cntl,
363 BIF_DOORBELL_INT_CNTL,
364 RAS_CNTLR_INTERRUPT_CLEAR, 1);
365 if (adev->asic_type == CHIP_ALDEBARAN)
366 WREG32_SOC15(NBIO, 0, mmBIF_DOORBELL_INT_CNTL_ALDE, bif_doorbell_intr_cntl);
368 WREG32_SOC15(NBIO, 0, mmBIF_DOORBELL_INT_CNTL, bif_doorbell_intr_cntl);
370 if (!ras->disable_ras_err_cnt_harvest) {
372 * clear error status after ras_controller_intr
373 * according to hw team and count ue number
376 nbio_v7_4_query_ras_error_count(adev, &err_data);
378 /* logging on error cnt and printing for awareness */
379 obj->err_data.ue_count += err_data.ue_count;
380 obj->err_data.ce_count += err_data.ce_count;
382 if (err_data.ce_count)
383 dev_info(adev->dev, "%ld correctable hardware "
384 "errors detected in %s block, "
385 "no user action is needed.\n",
386 obj->err_data.ce_count,
387 ras_block_str(adev->nbio.ras_if->block));
389 if (err_data.ue_count)
390 dev_info(adev->dev, "%ld uncorrectable hardware "
391 "errors detected in %s block\n",
392 obj->err_data.ue_count,
393 ras_block_str(adev->nbio.ras_if->block));
396 dev_info(adev->dev, "RAS controller interrupt triggered "
399 /* ras_controller_int is dedicated for nbif ras error,
400 * not the global interrupt for sync flood
402 amdgpu_ras_reset_gpu(adev);
406 static void nbio_v7_4_handle_ras_err_event_athub_intr_no_bifring(struct amdgpu_device *adev)
408 uint32_t bif_doorbell_intr_cntl;
410 if (adev->asic_type == CHIP_ALDEBARAN)
411 bif_doorbell_intr_cntl = RREG32_SOC15(NBIO, 0, mmBIF_DOORBELL_INT_CNTL_ALDE);
413 bif_doorbell_intr_cntl = RREG32_SOC15(NBIO, 0, mmBIF_DOORBELL_INT_CNTL);
415 if (REG_GET_FIELD(bif_doorbell_intr_cntl,
416 BIF_DOORBELL_INT_CNTL, RAS_ATHUB_ERR_EVENT_INTERRUPT_STATUS)) {
417 /* driver has to clear the interrupt status when bif ring is disabled */
418 bif_doorbell_intr_cntl = REG_SET_FIELD(bif_doorbell_intr_cntl,
419 BIF_DOORBELL_INT_CNTL,
420 RAS_ATHUB_ERR_EVENT_INTERRUPT_CLEAR, 1);
422 if (adev->asic_type == CHIP_ALDEBARAN)
423 WREG32_SOC15(NBIO, 0, mmBIF_DOORBELL_INT_CNTL_ALDE, bif_doorbell_intr_cntl);
425 WREG32_SOC15(NBIO, 0, mmBIF_DOORBELL_INT_CNTL, bif_doorbell_intr_cntl);
427 amdgpu_ras_global_ras_isr(adev);
432 static int nbio_v7_4_set_ras_controller_irq_state(struct amdgpu_device *adev,
433 struct amdgpu_irq_src *src,
435 enum amdgpu_interrupt_state state)
437 /* The ras_controller_irq enablement should be done in psp bl when it
438 * tries to enable ras feature. Driver only need to set the correct interrupt
439 * vector for bare-metal and sriov use case respectively
441 uint32_t bif_intr_cntl;
443 bif_intr_cntl = RREG32_SOC15(NBIO, 0, mmBIF_INTR_CNTL);
444 if (state == AMDGPU_IRQ_STATE_ENABLE) {
445 /* set interrupt vector select bit to 0 to select
446 * vetcor 1 for bare metal case */
447 bif_intr_cntl = REG_SET_FIELD(bif_intr_cntl,
449 RAS_INTR_VEC_SEL, 0);
450 WREG32_SOC15(NBIO, 0, mmBIF_INTR_CNTL, bif_intr_cntl);
456 static int nbio_v7_4_process_ras_controller_irq(struct amdgpu_device *adev,
457 struct amdgpu_irq_src *source,
458 struct amdgpu_iv_entry *entry)
460 /* By design, the ih cookie for ras_controller_irq should be written
461 * to BIFring instead of general iv ring. However, due to known bif ring
462 * hw bug, it has to be disabled. There is no chance the process function
463 * will be involked. Just left it as a dummy one.
468 static int nbio_v7_4_set_ras_err_event_athub_irq_state(struct amdgpu_device *adev,
469 struct amdgpu_irq_src *src,
471 enum amdgpu_interrupt_state state)
473 /* The ras_controller_irq enablement should be done in psp bl when it
474 * tries to enable ras feature. Driver only need to set the correct interrupt
475 * vector for bare-metal and sriov use case respectively
477 uint32_t bif_intr_cntl;
479 bif_intr_cntl = RREG32_SOC15(NBIO, 0, mmBIF_INTR_CNTL);
480 if (state == AMDGPU_IRQ_STATE_ENABLE) {
481 /* set interrupt vector select bit to 0 to select
482 * vetcor 1 for bare metal case */
483 bif_intr_cntl = REG_SET_FIELD(bif_intr_cntl,
485 RAS_INTR_VEC_SEL, 0);
486 WREG32_SOC15(NBIO, 0, mmBIF_INTR_CNTL, bif_intr_cntl);
492 static int nbio_v7_4_process_err_event_athub_irq(struct amdgpu_device *adev,
493 struct amdgpu_irq_src *source,
494 struct amdgpu_iv_entry *entry)
496 /* By design, the ih cookie for err_event_athub_irq should be written
497 * to BIFring instead of general iv ring. However, due to known bif ring
498 * hw bug, it has to be disabled. There is no chance the process function
499 * will be involked. Just left it as a dummy one.
504 static const struct amdgpu_irq_src_funcs nbio_v7_4_ras_controller_irq_funcs = {
505 .set = nbio_v7_4_set_ras_controller_irq_state,
506 .process = nbio_v7_4_process_ras_controller_irq,
509 static const struct amdgpu_irq_src_funcs nbio_v7_4_ras_err_event_athub_irq_funcs = {
510 .set = nbio_v7_4_set_ras_err_event_athub_irq_state,
511 .process = nbio_v7_4_process_err_event_athub_irq,
514 static int nbio_v7_4_init_ras_controller_interrupt (struct amdgpu_device *adev)
518 /* init the irq funcs */
519 adev->nbio.ras_controller_irq.funcs =
520 &nbio_v7_4_ras_controller_irq_funcs;
521 adev->nbio.ras_controller_irq.num_types = 1;
523 /* register ras controller interrupt */
524 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_BIF,
525 NBIF_7_4__SRCID__RAS_CONTROLLER_INTERRUPT,
526 &adev->nbio.ras_controller_irq);
531 static int nbio_v7_4_init_ras_err_event_athub_interrupt (struct amdgpu_device *adev)
536 /* init the irq funcs */
537 adev->nbio.ras_err_event_athub_irq.funcs =
538 &nbio_v7_4_ras_err_event_athub_irq_funcs;
539 adev->nbio.ras_err_event_athub_irq.num_types = 1;
541 /* register ras err event athub interrupt */
542 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_BIF,
543 NBIF_7_4__SRCID__ERREVENT_ATHUB_INTERRUPT,
544 &adev->nbio.ras_err_event_athub_irq);
549 #define smnPARITY_ERROR_STATUS_UNCORR_GRP2 0x13a20030
551 static void nbio_v7_4_query_ras_error_count(struct amdgpu_device *adev,
552 void *ras_error_status)
554 uint32_t global_sts, central_sts, int_eoi, parity_sts;
555 uint32_t corr, fatal, non_fatal;
556 struct ras_err_data *err_data = (struct ras_err_data *)ras_error_status;
558 global_sts = RREG32_PCIE(smnRAS_GLOBAL_STATUS_LO);
559 corr = REG_GET_FIELD(global_sts, RAS_GLOBAL_STATUS_LO, ParityErrCorr);
560 fatal = REG_GET_FIELD(global_sts, RAS_GLOBAL_STATUS_LO, ParityErrFatal);
561 non_fatal = REG_GET_FIELD(global_sts, RAS_GLOBAL_STATUS_LO,
563 parity_sts = RREG32_PCIE(smnPARITY_ERROR_STATUS_UNCORR_GRP2);
566 err_data->ce_count++;
568 err_data->ue_count++;
570 if (corr || fatal || non_fatal) {
571 central_sts = RREG32_PCIE(smnBIFL_RAS_CENTRAL_STATUS);
572 /* clear error status register */
573 WREG32_PCIE(smnRAS_GLOBAL_STATUS_LO, global_sts);
576 /* clear parity fatal error indication field */
577 WREG32_PCIE(smnPARITY_ERROR_STATUS_UNCORR_GRP2,
580 if (REG_GET_FIELD(central_sts, BIFL_RAS_CENTRAL_STATUS,
581 BIFL_RasContller_Intr_Recv)) {
582 /* clear interrupt status register */
583 WREG32_PCIE(smnBIFL_RAS_CENTRAL_STATUS, central_sts);
584 int_eoi = RREG32_PCIE(smnIOHC_INTERRUPT_EOI);
585 int_eoi = REG_SET_FIELD(int_eoi,
586 IOHC_INTERRUPT_EOI, SMI_EOI, 1);
587 WREG32_PCIE(smnIOHC_INTERRUPT_EOI, int_eoi);
592 static void nbio_v7_4_enable_doorbell_interrupt(struct amdgpu_device *adev,
595 if (adev->asic_type == CHIP_ALDEBARAN)
596 WREG32_FIELD15(NBIO, 0, BIF_DOORBELL_INT_CNTL_ALDE,
597 DOORBELL_INTERRUPT_DISABLE, enable ? 0 : 1);
599 WREG32_FIELD15(NBIO, 0, BIF_DOORBELL_INT_CNTL,
600 DOORBELL_INTERRUPT_DISABLE, enable ? 0 : 1);
603 const struct amdgpu_nbio_ras_funcs nbio_v7_4_ras_funcs = {
604 .handle_ras_controller_intr_no_bifring = nbio_v7_4_handle_ras_controller_intr_no_bifring,
605 .handle_ras_err_event_athub_intr_no_bifring = nbio_v7_4_handle_ras_err_event_athub_intr_no_bifring,
606 .init_ras_controller_interrupt = nbio_v7_4_init_ras_controller_interrupt,
607 .init_ras_err_event_athub_interrupt = nbio_v7_4_init_ras_err_event_athub_interrupt,
608 .query_ras_error_count = nbio_v7_4_query_ras_error_count,
609 .ras_late_init = amdgpu_nbio_ras_late_init,
610 .ras_fini = amdgpu_nbio_ras_fini,
613 static void nbio_v7_4_program_ltr(struct amdgpu_device *adev)
617 WREG32_PCIE(smnRCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL, 0x75EB);
619 def = data = RREG32_PCIE(smnRCC_BIF_STRAP2);
620 data &= ~RCC_BIF_STRAP2__STRAP_LTR_IN_ASPML1_DIS_MASK;
622 WREG32_PCIE(smnRCC_BIF_STRAP2, data);
624 def = data = RREG32_PCIE(smnRCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL);
625 data &= ~EP_PCIE_TX_LTR_CNTL__LTR_PRIV_MSG_DIS_IN_PM_NON_D0_MASK;
627 WREG32_PCIE(smnRCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL, data);
629 def = data = RREG32_PCIE(smnBIF_CFG_DEV0_EPF0_DEVICE_CNTL2);
630 data |= BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__LTR_EN_MASK;
632 WREG32_PCIE(smnBIF_CFG_DEV0_EPF0_DEVICE_CNTL2, data);
635 static void nbio_v7_4_program_aspm(struct amdgpu_device *adev)
639 def = data = RREG32_PCIE(smnPCIE_LC_CNTL);
640 data &= ~PCIE_LC_CNTL__LC_L1_INACTIVITY_MASK;
641 data &= ~PCIE_LC_CNTL__LC_L0S_INACTIVITY_MASK;
642 data |= PCIE_LC_CNTL__LC_PMI_TO_L1_DIS_MASK;
644 WREG32_PCIE(smnPCIE_LC_CNTL, data);
646 def = data = RREG32_PCIE(smnPCIE_LC_CNTL7);
647 data |= PCIE_LC_CNTL7__LC_NBIF_ASPM_INPUT_EN_MASK;
649 WREG32_PCIE(smnPCIE_LC_CNTL7, data);
651 def = data = RREG32_PCIE(smnNBIF_MGCG_CTRL_LCLK);
652 data |= NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_REG_DIS_LCLK_MASK;
654 WREG32_PCIE(smnNBIF_MGCG_CTRL_LCLK, data);
656 def = data = RREG32_PCIE(smnPCIE_LC_CNTL3);
657 data |= PCIE_LC_CNTL3__LC_DSC_DONT_ENTER_L23_AFTER_PME_ACK_MASK;
659 WREG32_PCIE(smnPCIE_LC_CNTL3, data);
661 def = data = RREG32_PCIE(smnRCC_BIF_STRAP3);
662 data &= ~RCC_BIF_STRAP3__STRAP_VLINK_ASPM_IDLE_TIMER_MASK;
663 data &= ~RCC_BIF_STRAP3__STRAP_VLINK_PM_L1_ENTRY_TIMER_MASK;
665 WREG32_PCIE(smnRCC_BIF_STRAP3, data);
667 def = data = RREG32_PCIE(smnRCC_BIF_STRAP5);
668 data &= ~RCC_BIF_STRAP5__STRAP_VLINK_LDN_ENTRY_TIMER_MASK;
670 WREG32_PCIE(smnRCC_BIF_STRAP5, data);
672 def = data = RREG32_PCIE(smnBIF_CFG_DEV0_EPF0_DEVICE_CNTL2);
673 data &= ~BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__LTR_EN_MASK;
675 WREG32_PCIE(smnBIF_CFG_DEV0_EPF0_DEVICE_CNTL2, data);
677 WREG32_PCIE(smnBIF_CFG_DEV0_EPF0_PCIE_LTR_CAP, 0x10011001);
679 def = data = RREG32_PCIE(smnPSWUSP0_PCIE_LC_CNTL2);
680 data |= PSWUSP0_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L1_MASK |
681 PSWUSP0_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L23_MASK;
682 data &= ~PSWUSP0_PCIE_LC_CNTL2__LC_RCV_L0_TO_RCV_L0S_DIS_MASK;
684 WREG32_PCIE(smnPSWUSP0_PCIE_LC_CNTL2, data);
686 def = data = RREG32_PCIE(smnPCIE_LC_CNTL6);
687 data |= PCIE_LC_CNTL6__LC_L1_POWERDOWN_MASK |
688 PCIE_LC_CNTL6__LC_RX_L0S_STANDBY_EN_MASK;
690 WREG32_PCIE(smnPCIE_LC_CNTL6, data);
692 nbio_v7_4_program_ltr(adev);
694 def = data = RREG32_PCIE(smnRCC_BIF_STRAP3);
695 data |= 0x5DE0 << RCC_BIF_STRAP3__STRAP_VLINK_ASPM_IDLE_TIMER__SHIFT;
696 data |= 0x0010 << RCC_BIF_STRAP3__STRAP_VLINK_PM_L1_ENTRY_TIMER__SHIFT;
698 WREG32_PCIE(smnRCC_BIF_STRAP3, data);
700 def = data = RREG32_PCIE(smnRCC_BIF_STRAP5);
701 data |= 0x0010 << RCC_BIF_STRAP5__STRAP_VLINK_LDN_ENTRY_TIMER__SHIFT;
703 WREG32_PCIE(smnRCC_BIF_STRAP5, data);
705 def = data = RREG32_PCIE(smnPCIE_LC_CNTL);
706 data &= ~PCIE_LC_CNTL__LC_L0S_INACTIVITY_MASK;
707 data |= 0x9 << PCIE_LC_CNTL__LC_L1_INACTIVITY__SHIFT;
708 data |= 0x1 << PCIE_LC_CNTL__LC_PMI_TO_L1_DIS__SHIFT;
710 WREG32_PCIE(smnPCIE_LC_CNTL, data);
712 def = data = RREG32_PCIE(smnPCIE_LC_CNTL3);
713 data &= ~PCIE_LC_CNTL3__LC_DSC_DONT_ENTER_L23_AFTER_PME_ACK_MASK;
715 WREG32_PCIE(smnPCIE_LC_CNTL3, data);
718 const struct amdgpu_nbio_funcs nbio_v7_4_funcs = {
719 .get_hdp_flush_req_offset = nbio_v7_4_get_hdp_flush_req_offset,
720 .get_hdp_flush_done_offset = nbio_v7_4_get_hdp_flush_done_offset,
721 .get_pcie_index_offset = nbio_v7_4_get_pcie_index_offset,
722 .get_pcie_data_offset = nbio_v7_4_get_pcie_data_offset,
723 .get_rev_id = nbio_v7_4_get_rev_id,
724 .mc_access_enable = nbio_v7_4_mc_access_enable,
725 .get_memsize = nbio_v7_4_get_memsize,
726 .sdma_doorbell_range = nbio_v7_4_sdma_doorbell_range,
727 .vcn_doorbell_range = nbio_v7_4_vcn_doorbell_range,
728 .enable_doorbell_aperture = nbio_v7_4_enable_doorbell_aperture,
729 .enable_doorbell_selfring_aperture = nbio_v7_4_enable_doorbell_selfring_aperture,
730 .ih_doorbell_range = nbio_v7_4_ih_doorbell_range,
731 .enable_doorbell_interrupt = nbio_v7_4_enable_doorbell_interrupt,
732 .update_medium_grain_clock_gating = nbio_v7_4_update_medium_grain_clock_gating,
733 .update_medium_grain_light_sleep = nbio_v7_4_update_medium_grain_light_sleep,
734 .get_clockgating_state = nbio_v7_4_get_clockgating_state,
735 .ih_control = nbio_v7_4_ih_control,
736 .init_registers = nbio_v7_4_init_registers,
737 .remap_hdp_registers = nbio_v7_4_remap_hdp_registers,
738 .program_aspm = nbio_v7_4_program_aspm,