2 * Copyright 2020 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
24 #include "amdgpu_atombios.h"
25 #include "nbio_v7_2.h"
27 #include "nbio/nbio_7_2_0_offset.h"
28 #include "nbio/nbio_7_2_0_sh_mask.h"
29 #include <uapi/linux/kfd_ioctl.h>
31 static void nbio_v7_2_remap_hdp_registers(struct amdgpu_device *adev)
33 WREG32_SOC15(NBIO, 0, regBIF_BX0_REMAP_HDP_MEM_FLUSH_CNTL,
34 adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL);
35 WREG32_SOC15(NBIO, 0, regBIF_BX0_REMAP_HDP_REG_FLUSH_CNTL,
36 adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_REG_FLUSH_CNTL);
39 static u32 nbio_v7_2_get_rev_id(struct amdgpu_device *adev)
41 u32 tmp = RREG32_SOC15(NBIO, 0, regRCC_STRAP0_RCC_DEV0_EPF0_STRAP0);
43 tmp &= RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0_MASK;
44 tmp >>= RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0__SHIFT;
49 static void nbio_v7_2_mc_access_enable(struct amdgpu_device *adev, bool enable)
52 WREG32_SOC15(NBIO, 0, regBIF_BX0_BIF_FB_EN,
53 BIF_BX0_BIF_FB_EN__FB_READ_EN_MASK |
54 BIF_BX0_BIF_FB_EN__FB_WRITE_EN_MASK);
56 WREG32_SOC15(NBIO, 0, regBIF_BX0_BIF_FB_EN, 0);
59 static void nbio_v7_2_hdp_flush(struct amdgpu_device *adev,
60 struct amdgpu_ring *ring)
62 if (!ring || !ring->funcs->emit_wreg)
63 WREG32_NO_KIQ((adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >> 2, 0);
65 amdgpu_ring_emit_wreg(ring, (adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >> 2, 0);
68 static u32 nbio_v7_2_get_memsize(struct amdgpu_device *adev)
70 return RREG32_SOC15(NBIO, 0, regRCC_DEV0_EPF0_0_RCC_CONFIG_MEMSIZE);
73 static void nbio_v7_2_sdma_doorbell_range(struct amdgpu_device *adev, int instance,
74 bool use_doorbell, int doorbell_index,
77 u32 reg = SOC15_REG_OFFSET(NBIO, 0, regGDC0_BIF_SDMA0_DOORBELL_RANGE);
78 u32 doorbell_range = RREG32_PCIE_PORT(reg);
81 doorbell_range = REG_SET_FIELD(doorbell_range,
82 GDC0_BIF_SDMA0_DOORBELL_RANGE,
83 OFFSET, doorbell_index);
84 doorbell_range = REG_SET_FIELD(doorbell_range,
85 GDC0_BIF_SDMA0_DOORBELL_RANGE,
88 doorbell_range = REG_SET_FIELD(doorbell_range,
89 GDC0_BIF_SDMA0_DOORBELL_RANGE,
93 WREG32_PCIE_PORT(reg, doorbell_range);
96 static void nbio_v7_2_vcn_doorbell_range(struct amdgpu_device *adev, bool use_doorbell,
97 int doorbell_index, int instance)
99 u32 reg = SOC15_REG_OFFSET(NBIO, 0, regGDC0_BIF_VCN0_DOORBELL_RANGE);
100 u32 doorbell_range = RREG32_PCIE_PORT(reg);
103 doorbell_range = REG_SET_FIELD(doorbell_range,
104 GDC0_BIF_VCN0_DOORBELL_RANGE, OFFSET,
106 doorbell_range = REG_SET_FIELD(doorbell_range,
107 GDC0_BIF_VCN0_DOORBELL_RANGE, SIZE, 8);
109 doorbell_range = REG_SET_FIELD(doorbell_range,
110 GDC0_BIF_VCN0_DOORBELL_RANGE, SIZE, 0);
113 WREG32_PCIE_PORT(reg, doorbell_range);
116 static void nbio_v7_2_enable_doorbell_aperture(struct amdgpu_device *adev,
121 reg = RREG32_SOC15(NBIO, 0, regRCC_DEV0_EPF0_0_RCC_DOORBELL_APER_EN);
122 reg = REG_SET_FIELD(reg, RCC_DEV0_EPF0_0_RCC_DOORBELL_APER_EN,
123 BIF_DOORBELL_APER_EN, enable ? 1 : 0);
125 WREG32_SOC15(NBIO, 0, regRCC_DEV0_EPF0_0_RCC_DOORBELL_APER_EN, reg);
128 static void nbio_v7_2_enable_doorbell_selfring_aperture(struct amdgpu_device *adev,
134 tmp = REG_SET_FIELD(tmp, BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL,
135 DOORBELL_SELFRING_GPA_APER_EN, 1) |
136 REG_SET_FIELD(tmp, BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL,
137 DOORBELL_SELFRING_GPA_APER_MODE, 1) |
138 REG_SET_FIELD(tmp, BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL,
139 DOORBELL_SELFRING_GPA_APER_SIZE, 0);
141 WREG32_SOC15(NBIO, 0,
142 regBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_LOW,
143 lower_32_bits(adev->doorbell.base));
144 WREG32_SOC15(NBIO, 0,
145 regBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH,
146 upper_32_bits(adev->doorbell.base));
149 WREG32_SOC15(NBIO, 0, regBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL,
154 static void nbio_v7_2_ih_doorbell_range(struct amdgpu_device *adev,
155 bool use_doorbell, int doorbell_index)
157 u32 ih_doorbell_range = RREG32_PCIE_PORT(SOC15_REG_OFFSET(NBIO, 0, regGDC0_BIF_IH_DOORBELL_RANGE));
160 ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range,
161 GDC0_BIF_IH_DOORBELL_RANGE, OFFSET,
163 ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range,
164 GDC0_BIF_IH_DOORBELL_RANGE, SIZE,
167 ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range,
168 GDC0_BIF_IH_DOORBELL_RANGE, SIZE,
172 WREG32_PCIE_PORT(SOC15_REG_OFFSET(NBIO, 0, regGDC0_BIF_IH_DOORBELL_RANGE),
176 static void nbio_v7_2_ih_control(struct amdgpu_device *adev)
180 /* setup interrupt control */
181 WREG32_SOC15(NBIO, 0, regBIF_BX0_INTERRUPT_CNTL2,
182 adev->dummy_page_addr >> 8);
184 interrupt_cntl = RREG32_SOC15(NBIO, 0, regBIF_BX0_INTERRUPT_CNTL);
186 * INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK=0 - dummy read disabled with msi, enabled without msi
187 * INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK=1 - dummy read controlled by IH_DUMMY_RD_EN
189 interrupt_cntl = REG_SET_FIELD(interrupt_cntl, BIF_BX0_INTERRUPT_CNTL,
190 IH_DUMMY_RD_OVERRIDE, 0);
192 /* INTERRUPT_CNTL__IH_REQ_NONSNOOP_EN_MASK=1 if ring is in non-cacheable memory, e.g., vram */
193 interrupt_cntl = REG_SET_FIELD(interrupt_cntl, BIF_BX0_INTERRUPT_CNTL,
194 IH_REQ_NONSNOOP_EN, 0);
196 WREG32_SOC15(NBIO, 0, regBIF_BX0_INTERRUPT_CNTL, interrupt_cntl);
199 static void nbio_v7_2_update_medium_grain_clock_gating(struct amdgpu_device *adev,
204 def = data = RREG32_PCIE_PORT(SOC15_REG_OFFSET(NBIO, 0, regCPM_CONTROL));
205 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_BIF_MGCG)) {
206 data |= (CPM_CONTROL__LCLK_DYN_GATE_ENABLE_MASK |
207 CPM_CONTROL__TXCLK_DYN_GATE_ENABLE_MASK |
208 CPM_CONTROL__TXCLK_LCNT_GATE_ENABLE_MASK |
209 CPM_CONTROL__TXCLK_REGS_GATE_ENABLE_MASK |
210 CPM_CONTROL__TXCLK_PRBS_GATE_ENABLE_MASK |
211 CPM_CONTROL__REFCLK_REGS_GATE_ENABLE_MASK);
213 data &= ~(CPM_CONTROL__LCLK_DYN_GATE_ENABLE_MASK |
214 CPM_CONTROL__TXCLK_DYN_GATE_ENABLE_MASK |
215 CPM_CONTROL__TXCLK_LCNT_GATE_ENABLE_MASK |
216 CPM_CONTROL__TXCLK_REGS_GATE_ENABLE_MASK |
217 CPM_CONTROL__TXCLK_PRBS_GATE_ENABLE_MASK |
218 CPM_CONTROL__REFCLK_REGS_GATE_ENABLE_MASK);
222 WREG32_PCIE_PORT(SOC15_REG_OFFSET(NBIO, 0, regCPM_CONTROL), data);
225 static void nbio_v7_2_update_medium_grain_light_sleep(struct amdgpu_device *adev,
230 def = data = RREG32_PCIE_PORT(SOC15_REG_OFFSET(NBIO, 0, regPCIE_CNTL2));
231 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_BIF_LS)) {
232 data |= (PCIE_CNTL2__SLV_MEM_LS_EN_MASK |
233 PCIE_CNTL2__MST_MEM_LS_EN_MASK |
234 PCIE_CNTL2__REPLAY_MEM_LS_EN_MASK);
236 data &= ~(PCIE_CNTL2__SLV_MEM_LS_EN_MASK |
237 PCIE_CNTL2__MST_MEM_LS_EN_MASK |
238 PCIE_CNTL2__REPLAY_MEM_LS_EN_MASK);
242 WREG32_PCIE_PORT(SOC15_REG_OFFSET(NBIO, 0, regPCIE_CNTL2), data);
245 static void nbio_v7_2_get_clockgating_state(struct amdgpu_device *adev,
250 /* AMD_CG_SUPPORT_BIF_MGCG */
251 data = RREG32_PCIE_PORT(SOC15_REG_OFFSET(NBIO, 0, regCPM_CONTROL));
252 if (data & CPM_CONTROL__LCLK_DYN_GATE_ENABLE_MASK)
253 *flags |= AMD_CG_SUPPORT_BIF_MGCG;
255 /* AMD_CG_SUPPORT_BIF_LS */
256 data = RREG32_PCIE_PORT(SOC15_REG_OFFSET(NBIO, 0, regPCIE_CNTL2));
257 if (data & PCIE_CNTL2__SLV_MEM_LS_EN_MASK)
258 *flags |= AMD_CG_SUPPORT_BIF_LS;
261 static u32 nbio_v7_2_get_hdp_flush_req_offset(struct amdgpu_device *adev)
263 return SOC15_REG_OFFSET(NBIO, 0, regBIF_BX_PF0_GPU_HDP_FLUSH_REQ);
266 static u32 nbio_v7_2_get_hdp_flush_done_offset(struct amdgpu_device *adev)
268 return SOC15_REG_OFFSET(NBIO, 0, regBIF_BX_PF0_GPU_HDP_FLUSH_DONE);
271 static u32 nbio_v7_2_get_pcie_index_offset(struct amdgpu_device *adev)
273 return SOC15_REG_OFFSET(NBIO, 0, regBIF_BX0_PCIE_INDEX2);
276 static u32 nbio_v7_2_get_pcie_data_offset(struct amdgpu_device *adev)
278 return SOC15_REG_OFFSET(NBIO, 0, regBIF_BX0_PCIE_DATA2);
281 static u32 nbio_v7_2_get_pcie_port_index_offset(struct amdgpu_device *adev)
283 return SOC15_REG_OFFSET(NBIO, 0, regBIF_BX_PF0_RSMU_INDEX);
286 static u32 nbio_v7_2_get_pcie_port_data_offset(struct amdgpu_device *adev)
288 return SOC15_REG_OFFSET(NBIO, 0, regBIF_BX_PF0_RSMU_DATA);
291 const struct nbio_hdp_flush_reg nbio_v7_2_hdp_flush_reg = {
292 .ref_and_mask_cp0 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP0_MASK,
293 .ref_and_mask_cp1 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP1_MASK,
294 .ref_and_mask_cp2 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP2_MASK,
295 .ref_and_mask_cp3 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP3_MASK,
296 .ref_and_mask_cp4 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP4_MASK,
297 .ref_and_mask_cp5 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP5_MASK,
298 .ref_and_mask_cp6 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP6_MASK,
299 .ref_and_mask_cp7 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP7_MASK,
300 .ref_and_mask_cp8 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP8_MASK,
301 .ref_and_mask_cp9 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP9_MASK,
302 .ref_and_mask_sdma0 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__SDMA0_MASK,
303 .ref_and_mask_sdma1 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__SDMA1_MASK,
306 static void nbio_v7_2_init_registers(struct amdgpu_device *adev)
310 def = data = RREG32_PCIE_PORT(SOC15_REG_OFFSET(NBIO, 0, regPCIE_CONFIG_CNTL));
311 data = REG_SET_FIELD(data, PCIE_CONFIG_CNTL, CI_SWUS_MAX_READ_REQUEST_SIZE_MODE, 1);
312 data = REG_SET_FIELD(data, PCIE_CONFIG_CNTL, CI_SWUS_MAX_READ_REQUEST_SIZE_PRIV, 1);
315 WREG32_PCIE_PORT(SOC15_REG_OFFSET(NBIO, 0, regPCIE_CONFIG_CNTL),
319 const struct amdgpu_nbio_funcs nbio_v7_2_funcs = {
320 .get_hdp_flush_req_offset = nbio_v7_2_get_hdp_flush_req_offset,
321 .get_hdp_flush_done_offset = nbio_v7_2_get_hdp_flush_done_offset,
322 .get_pcie_index_offset = nbio_v7_2_get_pcie_index_offset,
323 .get_pcie_data_offset = nbio_v7_2_get_pcie_data_offset,
324 .get_pcie_port_index_offset = nbio_v7_2_get_pcie_port_index_offset,
325 .get_pcie_port_data_offset = nbio_v7_2_get_pcie_port_data_offset,
326 .get_rev_id = nbio_v7_2_get_rev_id,
327 .mc_access_enable = nbio_v7_2_mc_access_enable,
328 .hdp_flush = nbio_v7_2_hdp_flush,
329 .get_memsize = nbio_v7_2_get_memsize,
330 .sdma_doorbell_range = nbio_v7_2_sdma_doorbell_range,
331 .vcn_doorbell_range = nbio_v7_2_vcn_doorbell_range,
332 .enable_doorbell_aperture = nbio_v7_2_enable_doorbell_aperture,
333 .enable_doorbell_selfring_aperture = nbio_v7_2_enable_doorbell_selfring_aperture,
334 .ih_doorbell_range = nbio_v7_2_ih_doorbell_range,
335 .update_medium_grain_clock_gating = nbio_v7_2_update_medium_grain_clock_gating,
336 .update_medium_grain_light_sleep = nbio_v7_2_update_medium_grain_light_sleep,
337 .get_clockgating_state = nbio_v7_2_get_clockgating_state,
338 .ih_control = nbio_v7_2_ih_control,
339 .init_registers = nbio_v7_2_init_registers,
340 .remap_hdp_registers = nbio_v7_2_remap_hdp_registers,