2 * Copyright 2020 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
24 #include "amdgpu_atombios.h"
25 #include "nbio_v7_2.h"
27 #include "nbio/nbio_7_2_0_offset.h"
28 #include "nbio/nbio_7_2_0_sh_mask.h"
29 #include <uapi/linux/kfd_ioctl.h>
31 static void nbio_v7_2_remap_hdp_registers(struct amdgpu_device *adev)
33 WREG32_SOC15(NBIO, 0, regBIF_BX0_REMAP_HDP_MEM_FLUSH_CNTL,
34 adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL);
35 WREG32_SOC15(NBIO, 0, regBIF_BX0_REMAP_HDP_REG_FLUSH_CNTL,
36 adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_REG_FLUSH_CNTL);
39 static u32 nbio_v7_2_get_rev_id(struct amdgpu_device *adev)
41 u32 tmp = RREG32_SOC15(NBIO, 0, regRCC_STRAP0_RCC_DEV0_EPF0_STRAP0);
43 tmp &= RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0_MASK;
44 tmp >>= RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0__SHIFT;
49 static void nbio_v7_2_mc_access_enable(struct amdgpu_device *adev, bool enable)
52 WREG32_SOC15(NBIO, 0, regBIF_BX0_BIF_FB_EN,
53 BIF_BX0_BIF_FB_EN__FB_READ_EN_MASK |
54 BIF_BX0_BIF_FB_EN__FB_WRITE_EN_MASK);
56 WREG32_SOC15(NBIO, 0, regBIF_BX0_BIF_FB_EN, 0);
59 static u32 nbio_v7_2_get_memsize(struct amdgpu_device *adev)
61 return RREG32_SOC15(NBIO, 0, regRCC_DEV0_EPF0_0_RCC_CONFIG_MEMSIZE);
64 static void nbio_v7_2_sdma_doorbell_range(struct amdgpu_device *adev, int instance,
65 bool use_doorbell, int doorbell_index,
68 u32 reg = SOC15_REG_OFFSET(NBIO, 0, regGDC0_BIF_SDMA0_DOORBELL_RANGE);
69 u32 doorbell_range = RREG32_PCIE_PORT(reg);
72 doorbell_range = REG_SET_FIELD(doorbell_range,
73 GDC0_BIF_SDMA0_DOORBELL_RANGE,
74 OFFSET, doorbell_index);
75 doorbell_range = REG_SET_FIELD(doorbell_range,
76 GDC0_BIF_SDMA0_DOORBELL_RANGE,
79 doorbell_range = REG_SET_FIELD(doorbell_range,
80 GDC0_BIF_SDMA0_DOORBELL_RANGE,
84 WREG32_PCIE_PORT(reg, doorbell_range);
87 static void nbio_v7_2_vcn_doorbell_range(struct amdgpu_device *adev, bool use_doorbell,
88 int doorbell_index, int instance)
90 u32 reg = SOC15_REG_OFFSET(NBIO, 0, regGDC0_BIF_VCN0_DOORBELL_RANGE);
91 u32 doorbell_range = RREG32_PCIE_PORT(reg);
94 doorbell_range = REG_SET_FIELD(doorbell_range,
95 GDC0_BIF_VCN0_DOORBELL_RANGE, OFFSET,
97 doorbell_range = REG_SET_FIELD(doorbell_range,
98 GDC0_BIF_VCN0_DOORBELL_RANGE, SIZE, 8);
100 doorbell_range = REG_SET_FIELD(doorbell_range,
101 GDC0_BIF_VCN0_DOORBELL_RANGE, SIZE, 0);
104 WREG32_PCIE_PORT(reg, doorbell_range);
107 static void nbio_v7_2_enable_doorbell_aperture(struct amdgpu_device *adev,
112 reg = RREG32_SOC15(NBIO, 0, regRCC_DEV0_EPF0_0_RCC_DOORBELL_APER_EN);
113 reg = REG_SET_FIELD(reg, RCC_DEV0_EPF0_0_RCC_DOORBELL_APER_EN,
114 BIF_DOORBELL_APER_EN, enable ? 1 : 0);
116 WREG32_SOC15(NBIO, 0, regRCC_DEV0_EPF0_0_RCC_DOORBELL_APER_EN, reg);
119 static void nbio_v7_2_enable_doorbell_selfring_aperture(struct amdgpu_device *adev,
125 tmp = REG_SET_FIELD(tmp, BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL,
126 DOORBELL_SELFRING_GPA_APER_EN, 1) |
127 REG_SET_FIELD(tmp, BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL,
128 DOORBELL_SELFRING_GPA_APER_MODE, 1) |
129 REG_SET_FIELD(tmp, BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL,
130 DOORBELL_SELFRING_GPA_APER_SIZE, 0);
132 WREG32_SOC15(NBIO, 0,
133 regBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_LOW,
134 lower_32_bits(adev->doorbell.base));
135 WREG32_SOC15(NBIO, 0,
136 regBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH,
137 upper_32_bits(adev->doorbell.base));
140 WREG32_SOC15(NBIO, 0, regBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL,
145 static void nbio_v7_2_ih_doorbell_range(struct amdgpu_device *adev,
146 bool use_doorbell, int doorbell_index)
148 u32 ih_doorbell_range = RREG32_PCIE_PORT(SOC15_REG_OFFSET(NBIO, 0, regGDC0_BIF_IH_DOORBELL_RANGE));
151 ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range,
152 GDC0_BIF_IH_DOORBELL_RANGE, OFFSET,
154 ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range,
155 GDC0_BIF_IH_DOORBELL_RANGE, SIZE,
158 ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range,
159 GDC0_BIF_IH_DOORBELL_RANGE, SIZE,
163 WREG32_PCIE_PORT(SOC15_REG_OFFSET(NBIO, 0, regGDC0_BIF_IH_DOORBELL_RANGE),
167 static void nbio_v7_2_ih_control(struct amdgpu_device *adev)
171 /* setup interrupt control */
172 WREG32_SOC15(NBIO, 0, regBIF_BX0_INTERRUPT_CNTL2,
173 adev->dummy_page_addr >> 8);
175 interrupt_cntl = RREG32_SOC15(NBIO, 0, regBIF_BX0_INTERRUPT_CNTL);
177 * INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK=0 - dummy read disabled with msi, enabled without msi
178 * INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK=1 - dummy read controlled by IH_DUMMY_RD_EN
180 interrupt_cntl = REG_SET_FIELD(interrupt_cntl, BIF_BX0_INTERRUPT_CNTL,
181 IH_DUMMY_RD_OVERRIDE, 0);
183 /* INTERRUPT_CNTL__IH_REQ_NONSNOOP_EN_MASK=1 if ring is in non-cacheable memory, e.g., vram */
184 interrupt_cntl = REG_SET_FIELD(interrupt_cntl, BIF_BX0_INTERRUPT_CNTL,
185 IH_REQ_NONSNOOP_EN, 0);
187 WREG32_SOC15(NBIO, 0, regBIF_BX0_INTERRUPT_CNTL, interrupt_cntl);
190 static void nbio_v7_2_update_medium_grain_clock_gating(struct amdgpu_device *adev,
195 def = data = RREG32_PCIE_PORT(SOC15_REG_OFFSET(NBIO, 0, regCPM_CONTROL));
196 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_BIF_MGCG)) {
197 data |= (CPM_CONTROL__LCLK_DYN_GATE_ENABLE_MASK |
198 CPM_CONTROL__TXCLK_DYN_GATE_ENABLE_MASK |
199 CPM_CONTROL__TXCLK_LCNT_GATE_ENABLE_MASK |
200 CPM_CONTROL__TXCLK_REGS_GATE_ENABLE_MASK |
201 CPM_CONTROL__TXCLK_PRBS_GATE_ENABLE_MASK |
202 CPM_CONTROL__REFCLK_REGS_GATE_ENABLE_MASK);
204 data &= ~(CPM_CONTROL__LCLK_DYN_GATE_ENABLE_MASK |
205 CPM_CONTROL__TXCLK_DYN_GATE_ENABLE_MASK |
206 CPM_CONTROL__TXCLK_LCNT_GATE_ENABLE_MASK |
207 CPM_CONTROL__TXCLK_REGS_GATE_ENABLE_MASK |
208 CPM_CONTROL__TXCLK_PRBS_GATE_ENABLE_MASK |
209 CPM_CONTROL__REFCLK_REGS_GATE_ENABLE_MASK);
213 WREG32_PCIE_PORT(SOC15_REG_OFFSET(NBIO, 0, regCPM_CONTROL), data);
216 static void nbio_v7_2_update_medium_grain_light_sleep(struct amdgpu_device *adev,
221 def = data = RREG32_PCIE_PORT(SOC15_REG_OFFSET(NBIO, 0, regPCIE_CNTL2));
222 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_BIF_LS)) {
223 data |= (PCIE_CNTL2__SLV_MEM_LS_EN_MASK |
224 PCIE_CNTL2__MST_MEM_LS_EN_MASK |
225 PCIE_CNTL2__REPLAY_MEM_LS_EN_MASK);
227 data &= ~(PCIE_CNTL2__SLV_MEM_LS_EN_MASK |
228 PCIE_CNTL2__MST_MEM_LS_EN_MASK |
229 PCIE_CNTL2__REPLAY_MEM_LS_EN_MASK);
233 WREG32_PCIE_PORT(SOC15_REG_OFFSET(NBIO, 0, regPCIE_CNTL2), data);
236 static void nbio_v7_2_get_clockgating_state(struct amdgpu_device *adev,
241 /* AMD_CG_SUPPORT_BIF_MGCG */
242 data = RREG32_PCIE_PORT(SOC15_REG_OFFSET(NBIO, 0, regCPM_CONTROL));
243 if (data & CPM_CONTROL__LCLK_DYN_GATE_ENABLE_MASK)
244 *flags |= AMD_CG_SUPPORT_BIF_MGCG;
246 /* AMD_CG_SUPPORT_BIF_LS */
247 data = RREG32_PCIE_PORT(SOC15_REG_OFFSET(NBIO, 0, regPCIE_CNTL2));
248 if (data & PCIE_CNTL2__SLV_MEM_LS_EN_MASK)
249 *flags |= AMD_CG_SUPPORT_BIF_LS;
252 static u32 nbio_v7_2_get_hdp_flush_req_offset(struct amdgpu_device *adev)
254 return SOC15_REG_OFFSET(NBIO, 0, regBIF_BX_PF0_GPU_HDP_FLUSH_REQ);
257 static u32 nbio_v7_2_get_hdp_flush_done_offset(struct amdgpu_device *adev)
259 return SOC15_REG_OFFSET(NBIO, 0, regBIF_BX_PF0_GPU_HDP_FLUSH_DONE);
262 static u32 nbio_v7_2_get_pcie_index_offset(struct amdgpu_device *adev)
264 return SOC15_REG_OFFSET(NBIO, 0, regBIF_BX0_PCIE_INDEX2);
267 static u32 nbio_v7_2_get_pcie_data_offset(struct amdgpu_device *adev)
269 return SOC15_REG_OFFSET(NBIO, 0, regBIF_BX0_PCIE_DATA2);
272 static u32 nbio_v7_2_get_pcie_port_index_offset(struct amdgpu_device *adev)
274 return SOC15_REG_OFFSET(NBIO, 0, regBIF_BX_PF0_RSMU_INDEX);
277 static u32 nbio_v7_2_get_pcie_port_data_offset(struct amdgpu_device *adev)
279 return SOC15_REG_OFFSET(NBIO, 0, regBIF_BX_PF0_RSMU_DATA);
282 const struct nbio_hdp_flush_reg nbio_v7_2_hdp_flush_reg = {
283 .ref_and_mask_cp0 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP0_MASK,
284 .ref_and_mask_cp1 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP1_MASK,
285 .ref_and_mask_cp2 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP2_MASK,
286 .ref_and_mask_cp3 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP3_MASK,
287 .ref_and_mask_cp4 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP4_MASK,
288 .ref_and_mask_cp5 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP5_MASK,
289 .ref_and_mask_cp6 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP6_MASK,
290 .ref_and_mask_cp7 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP7_MASK,
291 .ref_and_mask_cp8 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP8_MASK,
292 .ref_and_mask_cp9 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP9_MASK,
293 .ref_and_mask_sdma0 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__SDMA0_MASK,
294 .ref_and_mask_sdma1 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__SDMA1_MASK,
297 static void nbio_v7_2_init_registers(struct amdgpu_device *adev)
301 def = data = RREG32_PCIE_PORT(SOC15_REG_OFFSET(NBIO, 0, regPCIE_CONFIG_CNTL));
302 data = REG_SET_FIELD(data, PCIE_CONFIG_CNTL, CI_SWUS_MAX_READ_REQUEST_SIZE_MODE, 1);
303 data = REG_SET_FIELD(data, PCIE_CONFIG_CNTL, CI_SWUS_MAX_READ_REQUEST_SIZE_PRIV, 1);
306 WREG32_PCIE_PORT(SOC15_REG_OFFSET(NBIO, 0, regPCIE_CONFIG_CNTL),
310 const struct amdgpu_nbio_funcs nbio_v7_2_funcs = {
311 .get_hdp_flush_req_offset = nbio_v7_2_get_hdp_flush_req_offset,
312 .get_hdp_flush_done_offset = nbio_v7_2_get_hdp_flush_done_offset,
313 .get_pcie_index_offset = nbio_v7_2_get_pcie_index_offset,
314 .get_pcie_data_offset = nbio_v7_2_get_pcie_data_offset,
315 .get_pcie_port_index_offset = nbio_v7_2_get_pcie_port_index_offset,
316 .get_pcie_port_data_offset = nbio_v7_2_get_pcie_port_data_offset,
317 .get_rev_id = nbio_v7_2_get_rev_id,
318 .mc_access_enable = nbio_v7_2_mc_access_enable,
319 .get_memsize = nbio_v7_2_get_memsize,
320 .sdma_doorbell_range = nbio_v7_2_sdma_doorbell_range,
321 .vcn_doorbell_range = nbio_v7_2_vcn_doorbell_range,
322 .enable_doorbell_aperture = nbio_v7_2_enable_doorbell_aperture,
323 .enable_doorbell_selfring_aperture = nbio_v7_2_enable_doorbell_selfring_aperture,
324 .ih_doorbell_range = nbio_v7_2_ih_doorbell_range,
325 .update_medium_grain_clock_gating = nbio_v7_2_update_medium_grain_clock_gating,
326 .update_medium_grain_light_sleep = nbio_v7_2_update_medium_grain_light_sleep,
327 .get_clockgating_state = nbio_v7_2_get_clockgating_state,
328 .ih_control = nbio_v7_2_ih_control,
329 .init_registers = nbio_v7_2_init_registers,
330 .remap_hdp_registers = nbio_v7_2_remap_hdp_registers,