2 * Copyright 2016 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
24 #include "amdgpu_atombios.h"
25 #include "nbio_v7_0.h"
27 #include "nbio/nbio_7_0_default.h"
28 #include "nbio/nbio_7_0_offset.h"
29 #include "nbio/nbio_7_0_sh_mask.h"
30 #include "vega10_enum.h"
32 #define smnNBIF_MGCG_CTRL_LCLK 0x1013a05c
34 #define smnCPM_CONTROL 0x11180460
35 #define smnPCIE_CNTL2 0x11180070
37 static u32 nbio_v7_0_get_rev_id(struct amdgpu_device *adev)
39 u32 tmp = RREG32_SOC15(NBIO, 0, mmRCC_DEV0_EPF0_STRAP0);
41 tmp &= RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0_MASK;
42 tmp >>= RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0__SHIFT;
47 static void nbio_v7_0_mc_access_enable(struct amdgpu_device *adev, bool enable)
50 WREG32_SOC15(NBIO, 0, mmBIF_FB_EN,
51 BIF_FB_EN__FB_READ_EN_MASK | BIF_FB_EN__FB_WRITE_EN_MASK);
53 WREG32_SOC15(NBIO, 0, mmBIF_FB_EN, 0);
56 static void nbio_v7_0_hdp_flush(struct amdgpu_device *adev,
57 struct amdgpu_ring *ring)
59 if (!ring || !ring->funcs->emit_wreg)
60 WREG32_SOC15_NO_KIQ(NBIO, 0, mmHDP_MEM_COHERENCY_FLUSH_CNTL, 0);
62 amdgpu_ring_emit_wreg(ring, SOC15_REG_OFFSET(
63 NBIO, 0, mmHDP_MEM_COHERENCY_FLUSH_CNTL), 0);
66 static u32 nbio_v7_0_get_memsize(struct amdgpu_device *adev)
68 return RREG32_SOC15(NBIO, 0, mmRCC_CONFIG_MEMSIZE);
71 static void nbio_v7_0_sdma_doorbell_range(struct amdgpu_device *adev, int instance,
72 bool use_doorbell, int doorbell_index)
74 u32 reg = instance == 0 ? SOC15_REG_OFFSET(NBIO, 0, mmBIF_SDMA0_DOORBELL_RANGE) :
75 SOC15_REG_OFFSET(NBIO, 0, mmBIF_SDMA1_DOORBELL_RANGE);
77 u32 doorbell_range = RREG32(reg);
80 doorbell_range = REG_SET_FIELD(doorbell_range, BIF_SDMA0_DOORBELL_RANGE, OFFSET, doorbell_index);
81 doorbell_range = REG_SET_FIELD(doorbell_range, BIF_SDMA0_DOORBELL_RANGE, SIZE, 2);
83 doorbell_range = REG_SET_FIELD(doorbell_range, BIF_SDMA0_DOORBELL_RANGE, SIZE, 0);
85 WREG32(reg, doorbell_range);
88 static void nbio_v7_0_enable_doorbell_aperture(struct amdgpu_device *adev,
91 WREG32_FIELD15(NBIO, 0, RCC_DOORBELL_APER_EN, BIF_DOORBELL_APER_EN, enable ? 1 : 0);
94 static void nbio_v7_0_enable_doorbell_selfring_aperture(struct amdgpu_device *adev,
100 static void nbio_v7_0_ih_doorbell_range(struct amdgpu_device *adev,
101 bool use_doorbell, int doorbell_index)
103 u32 ih_doorbell_range = RREG32_SOC15(NBIO, 0 , mmBIF_IH_DOORBELL_RANGE);
106 ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range, BIF_IH_DOORBELL_RANGE, OFFSET, doorbell_index);
107 ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range, BIF_IH_DOORBELL_RANGE, SIZE, 2);
109 ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range, BIF_IH_DOORBELL_RANGE, SIZE, 0);
111 WREG32_SOC15(NBIO, 0, mmBIF_IH_DOORBELL_RANGE, ih_doorbell_range);
114 static uint32_t nbio_7_0_read_syshub_ind_mmr(struct amdgpu_device *adev, uint32_t offset)
118 WREG32_SOC15(NBIO, 0, mmSYSHUB_INDEX, offset);
119 data = RREG32_SOC15(NBIO, 0, mmSYSHUB_DATA);
124 static void nbio_7_0_write_syshub_ind_mmr(struct amdgpu_device *adev, uint32_t offset,
127 WREG32_SOC15(NBIO, 0, mmSYSHUB_INDEX, offset);
128 WREG32_SOC15(NBIO, 0, mmSYSHUB_DATA, data);
131 static void nbio_v7_0_update_medium_grain_clock_gating(struct amdgpu_device *adev,
136 /* NBIF_MGCG_CTRL_LCLK */
137 def = data = RREG32_PCIE(smnNBIF_MGCG_CTRL_LCLK);
139 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_BIF_MGCG))
140 data |= NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_EN_LCLK_MASK;
142 data &= ~NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_EN_LCLK_MASK;
145 WREG32_PCIE(smnNBIF_MGCG_CTRL_LCLK, data);
147 /* SYSHUB_MGCG_CTRL_SOCCLK */
148 def = data = nbio_7_0_read_syshub_ind_mmr(adev, ixSYSHUB_MMREG_IND_SYSHUB_MGCG_CTRL_SOCCLK);
150 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_BIF_MGCG))
151 data |= SYSHUB_MMREG_DIRECT_SYSHUB_MGCG_CTRL_SOCCLK__SYSHUB_MGCG_EN_SOCCLK_MASK;
153 data &= ~SYSHUB_MMREG_DIRECT_SYSHUB_MGCG_CTRL_SOCCLK__SYSHUB_MGCG_EN_SOCCLK_MASK;
156 nbio_7_0_write_syshub_ind_mmr(adev, ixSYSHUB_MMREG_IND_SYSHUB_MGCG_CTRL_SOCCLK, data);
158 /* SYSHUB_MGCG_CTRL_SHUBCLK */
159 def = data = nbio_7_0_read_syshub_ind_mmr(adev, ixSYSHUB_MMREG_IND_SYSHUB_MGCG_CTRL_SHUBCLK);
161 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_BIF_MGCG))
162 data |= SYSHUB_MMREG_DIRECT_SYSHUB_MGCG_CTRL_SHUBCLK__SYSHUB_MGCG_EN_SHUBCLK_MASK;
164 data &= ~SYSHUB_MMREG_DIRECT_SYSHUB_MGCG_CTRL_SHUBCLK__SYSHUB_MGCG_EN_SHUBCLK_MASK;
167 nbio_7_0_write_syshub_ind_mmr(adev, ixSYSHUB_MMREG_IND_SYSHUB_MGCG_CTRL_SHUBCLK, data);
170 static void nbio_v7_0_update_medium_grain_light_sleep(struct amdgpu_device *adev,
175 def = data = RREG32_PCIE(smnPCIE_CNTL2);
176 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_BIF_LS)) {
177 data |= (PCIE_CNTL2__SLV_MEM_LS_EN_MASK |
178 PCIE_CNTL2__MST_MEM_LS_EN_MASK |
179 PCIE_CNTL2__REPLAY_MEM_LS_EN_MASK);
181 data &= ~(PCIE_CNTL2__SLV_MEM_LS_EN_MASK |
182 PCIE_CNTL2__MST_MEM_LS_EN_MASK |
183 PCIE_CNTL2__REPLAY_MEM_LS_EN_MASK);
187 WREG32_PCIE(smnPCIE_CNTL2, data);
190 static void nbio_v7_0_get_clockgating_state(struct amdgpu_device *adev,
195 /* AMD_CG_SUPPORT_BIF_MGCG */
196 data = RREG32_PCIE(smnCPM_CONTROL);
197 if (data & CPM_CONTROL__LCLK_DYN_GATE_ENABLE_MASK)
198 *flags |= AMD_CG_SUPPORT_BIF_MGCG;
200 /* AMD_CG_SUPPORT_BIF_LS */
201 data = RREG32_PCIE(smnPCIE_CNTL2);
202 if (data & PCIE_CNTL2__SLV_MEM_LS_EN_MASK)
203 *flags |= AMD_CG_SUPPORT_BIF_LS;
206 static void nbio_v7_0_ih_control(struct amdgpu_device *adev)
210 /* setup interrupt control */
211 WREG32_SOC15(NBIO, 0, mmINTERRUPT_CNTL2, adev->dummy_page_addr >> 8);
212 interrupt_cntl = RREG32_SOC15(NBIO, 0, mmINTERRUPT_CNTL);
213 /* INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK=0 - dummy read disabled with msi, enabled without msi
214 * INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK=1 - dummy read controlled by IH_DUMMY_RD_EN
216 interrupt_cntl = REG_SET_FIELD(interrupt_cntl, INTERRUPT_CNTL, IH_DUMMY_RD_OVERRIDE, 0);
217 /* INTERRUPT_CNTL__IH_REQ_NONSNOOP_EN_MASK=1 if ring is in non-cacheable memory, e.g., vram */
218 interrupt_cntl = REG_SET_FIELD(interrupt_cntl, INTERRUPT_CNTL, IH_REQ_NONSNOOP_EN, 0);
219 WREG32_SOC15(NBIO, 0, mmINTERRUPT_CNTL, interrupt_cntl);
222 static u32 nbio_v7_0_get_hdp_flush_req_offset(struct amdgpu_device *adev)
224 return SOC15_REG_OFFSET(NBIO, 0, mmGPU_HDP_FLUSH_REQ);
227 static u32 nbio_v7_0_get_hdp_flush_done_offset(struct amdgpu_device *adev)
229 return SOC15_REG_OFFSET(NBIO, 0, mmGPU_HDP_FLUSH_DONE);
232 static u32 nbio_v7_0_get_pcie_index_offset(struct amdgpu_device *adev)
234 return SOC15_REG_OFFSET(NBIO, 0, mmPCIE_INDEX2);
237 static u32 nbio_v7_0_get_pcie_data_offset(struct amdgpu_device *adev)
239 return SOC15_REG_OFFSET(NBIO, 0, mmPCIE_DATA2);
242 const struct nbio_hdp_flush_reg nbio_v7_0_hdp_flush_reg = {
243 .ref_and_mask_cp0 = GPU_HDP_FLUSH_DONE__CP0_MASK,
244 .ref_and_mask_cp1 = GPU_HDP_FLUSH_DONE__CP1_MASK,
245 .ref_and_mask_cp2 = GPU_HDP_FLUSH_DONE__CP2_MASK,
246 .ref_and_mask_cp3 = GPU_HDP_FLUSH_DONE__CP3_MASK,
247 .ref_and_mask_cp4 = GPU_HDP_FLUSH_DONE__CP4_MASK,
248 .ref_and_mask_cp5 = GPU_HDP_FLUSH_DONE__CP5_MASK,
249 .ref_and_mask_cp6 = GPU_HDP_FLUSH_DONE__CP6_MASK,
250 .ref_and_mask_cp7 = GPU_HDP_FLUSH_DONE__CP7_MASK,
251 .ref_and_mask_cp8 = GPU_HDP_FLUSH_DONE__CP8_MASK,
252 .ref_and_mask_cp9 = GPU_HDP_FLUSH_DONE__CP9_MASK,
253 .ref_and_mask_sdma0 = GPU_HDP_FLUSH_DONE__SDMA0_MASK,
254 .ref_and_mask_sdma1 = GPU_HDP_FLUSH_DONE__SDMA1_MASK,
257 static void nbio_v7_0_detect_hw_virt(struct amdgpu_device *adev)
259 if (is_virtual_machine()) /* passthrough mode exclus sriov mod */
260 adev->virt.caps |= AMDGPU_PASSTHROUGH_MODE;
263 static void nbio_v7_0_init_registers(struct amdgpu_device *adev)
268 const struct amdgpu_nbio_funcs nbio_v7_0_funcs = {
269 .hdp_flush_reg = &nbio_v7_0_hdp_flush_reg,
270 .get_hdp_flush_req_offset = nbio_v7_0_get_hdp_flush_req_offset,
271 .get_hdp_flush_done_offset = nbio_v7_0_get_hdp_flush_done_offset,
272 .get_pcie_index_offset = nbio_v7_0_get_pcie_index_offset,
273 .get_pcie_data_offset = nbio_v7_0_get_pcie_data_offset,
274 .get_rev_id = nbio_v7_0_get_rev_id,
275 .mc_access_enable = nbio_v7_0_mc_access_enable,
276 .hdp_flush = nbio_v7_0_hdp_flush,
277 .get_memsize = nbio_v7_0_get_memsize,
278 .sdma_doorbell_range = nbio_v7_0_sdma_doorbell_range,
279 .enable_doorbell_aperture = nbio_v7_0_enable_doorbell_aperture,
280 .enable_doorbell_selfring_aperture = nbio_v7_0_enable_doorbell_selfring_aperture,
281 .ih_doorbell_range = nbio_v7_0_ih_doorbell_range,
282 .update_medium_grain_clock_gating = nbio_v7_0_update_medium_grain_clock_gating,
283 .update_medium_grain_light_sleep = nbio_v7_0_update_medium_grain_light_sleep,
284 .get_clockgating_state = nbio_v7_0_get_clockgating_state,
285 .ih_control = nbio_v7_0_ih_control,
286 .init_registers = nbio_v7_0_init_registers,
287 .detect_hw_virt = nbio_v7_0_detect_hw_virt,