drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c

   1 /*
   2  * Copyright 2016 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23 #include "amdgpu.h"
  24 #include "amdgpu_atombios.h"
  25 #include "nbio_v7_0.h"
  26
  27 #include "nbio/nbio_7_0_default.h"
  28 #include "nbio/nbio_7_0_offset.h"
  29 #include "nbio/nbio_7_0_sh_mask.h"
  30 #include "vega10_enum.h"
  31
  32 #define smnNBIF_MGCG_CTRL_LCLK  0x1013a05c
  33
  34 #define smnCPM_CONTROL                                                                                  0x11180460
  35 #define smnPCIE_CNTL2                                                                                   0x11180070
  36
  37 static u32 nbio_v7_0_get_rev_id(struct amdgpu_device *adev)
  38 {
  39         u32 tmp = RREG32_SOC15(NBIO, 0, mmRCC_DEV0_EPF0_STRAP0);
  40
  41         tmp &= RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0_MASK;
  42         tmp >>= RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0__SHIFT;
  43
  44         return tmp;
  45 }
  46
  47 static void nbio_v7_0_mc_access_enable(struct amdgpu_device *adev, bool enable)
  48 {
  49         if (enable)
  50                 WREG32_SOC15(NBIO, 0, mmBIF_FB_EN,
  51                         BIF_FB_EN__FB_READ_EN_MASK | BIF_FB_EN__FB_WRITE_EN_MASK);
  52         else
  53                 WREG32_SOC15(NBIO, 0, mmBIF_FB_EN, 0);
  54 }
  55
  56 static void nbio_v7_0_hdp_flush(struct amdgpu_device *adev,
  57                                 struct amdgpu_ring *ring)
  58 {
  59         if (!ring || !ring->funcs->emit_wreg)
  60                 WREG32_SOC15_NO_KIQ(NBIO, 0, mmHDP_MEM_COHERENCY_FLUSH_CNTL, 0);
  61         else
  62                 amdgpu_ring_emit_wreg(ring, SOC15_REG_OFFSET(
  63                         NBIO, 0, mmHDP_MEM_COHERENCY_FLUSH_CNTL), 0);
  64 }
  65
  66 static u32 nbio_v7_0_get_memsize(struct amdgpu_device *adev)
  67 {
  68         return RREG32_SOC15(NBIO, 0, mmRCC_CONFIG_MEMSIZE);
  69 }
  70
  71 static void nbio_v7_0_sdma_doorbell_range(struct amdgpu_device *adev, int instance,
  72                                           bool use_doorbell, int doorbell_index)
  73 {
  74         u32 reg = instance == 0 ? SOC15_REG_OFFSET(NBIO, 0, mmBIF_SDMA0_DOORBELL_RANGE) :
  75                         SOC15_REG_OFFSET(NBIO, 0, mmBIF_SDMA1_DOORBELL_RANGE);
  76
  77         u32 doorbell_range = RREG32(reg);
  78
  79         if (use_doorbell) {
  80                 doorbell_range = REG_SET_FIELD(doorbell_range, BIF_SDMA0_DOORBELL_RANGE, OFFSET, doorbell_index);
  81                 doorbell_range = REG_SET_FIELD(doorbell_range, BIF_SDMA0_DOORBELL_RANGE, SIZE, 2);
  82         } else
  83                 doorbell_range = REG_SET_FIELD(doorbell_range, BIF_SDMA0_DOORBELL_RANGE, SIZE, 0);
  84
  85         WREG32(reg, doorbell_range);
  86 }
  87
  88 static void nbio_v7_0_enable_doorbell_aperture(struct amdgpu_device *adev,
  89                                                bool enable)
  90 {
  91         WREG32_FIELD15(NBIO, 0, RCC_DOORBELL_APER_EN, BIF_DOORBELL_APER_EN, enable ? 1 : 0);
  92 }
  93
  94 static void nbio_v7_0_enable_doorbell_selfring_aperture(struct amdgpu_device *adev,
  95                                                         bool enable)
  96 {
  97
  98 }
  99
 100 static void nbio_v7_0_ih_doorbell_range(struct amdgpu_device *adev,
 101                                         bool use_doorbell, int doorbell_index)
 102 {
 103         u32 ih_doorbell_range = RREG32_SOC15(NBIO, 0 , mmBIF_IH_DOORBELL_RANGE);
 104
 105         if (use_doorbell) {
 106                 ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range, BIF_IH_DOORBELL_RANGE, OFFSET, doorbell_index);
 107                 ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range, BIF_IH_DOORBELL_RANGE, SIZE, 2);
 108         } else
 109                 ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range, BIF_IH_DOORBELL_RANGE, SIZE, 0);
 110
 111         WREG32_SOC15(NBIO, 0, mmBIF_IH_DOORBELL_RANGE, ih_doorbell_range);
 112 }
 113
 114 static uint32_t nbio_7_0_read_syshub_ind_mmr(struct amdgpu_device *adev, uint32_t offset)
 115 {
 116         uint32_t data;
 117
 118         WREG32_SOC15(NBIO, 0, mmSYSHUB_INDEX, offset);
 119         data = RREG32_SOC15(NBIO, 0, mmSYSHUB_DATA);
 120
 121         return data;
 122 }
 123
 124 static void nbio_7_0_write_syshub_ind_mmr(struct amdgpu_device *adev, uint32_t offset,
 125                                        uint32_t data)
 126 {
 127         WREG32_SOC15(NBIO, 0, mmSYSHUB_INDEX, offset);
 128         WREG32_SOC15(NBIO, 0, mmSYSHUB_DATA, data);
 129 }
 130
 131 static void nbio_v7_0_update_medium_grain_clock_gating(struct amdgpu_device *adev,
 132                                                        bool enable)
 133 {
 134         uint32_t def, data;
 135
 136         /* NBIF_MGCG_CTRL_LCLK */
 137         def = data = RREG32_PCIE(smnNBIF_MGCG_CTRL_LCLK);
 138
 139         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_BIF_MGCG))
 140                 data |= NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_EN_LCLK_MASK;
 141         else
 142                 data &= ~NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_EN_LCLK_MASK;
 143
 144         if (def != data)
 145                 WREG32_PCIE(smnNBIF_MGCG_CTRL_LCLK, data);
 146
 147         /* SYSHUB_MGCG_CTRL_SOCCLK */
 148         def = data = nbio_7_0_read_syshub_ind_mmr(adev, ixSYSHUB_MMREG_IND_SYSHUB_MGCG_CTRL_SOCCLK);
 149
 150         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_BIF_MGCG))
 151                 data |= SYSHUB_MMREG_DIRECT_SYSHUB_MGCG_CTRL_SOCCLK__SYSHUB_MGCG_EN_SOCCLK_MASK;
 152         else
 153                 data &= ~SYSHUB_MMREG_DIRECT_SYSHUB_MGCG_CTRL_SOCCLK__SYSHUB_MGCG_EN_SOCCLK_MASK;
 154
 155         if (def != data)
 156                 nbio_7_0_write_syshub_ind_mmr(adev, ixSYSHUB_MMREG_IND_SYSHUB_MGCG_CTRL_SOCCLK, data);
 157
 158         /* SYSHUB_MGCG_CTRL_SHUBCLK */
 159         def = data = nbio_7_0_read_syshub_ind_mmr(adev, ixSYSHUB_MMREG_IND_SYSHUB_MGCG_CTRL_SHUBCLK);
 160
 161         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_BIF_MGCG))
 162                 data |= SYSHUB_MMREG_DIRECT_SYSHUB_MGCG_CTRL_SHUBCLK__SYSHUB_MGCG_EN_SHUBCLK_MASK;
 163         else
 164                 data &= ~SYSHUB_MMREG_DIRECT_SYSHUB_MGCG_CTRL_SHUBCLK__SYSHUB_MGCG_EN_SHUBCLK_MASK;
 165
 166         if (def != data)
 167                 nbio_7_0_write_syshub_ind_mmr(adev, ixSYSHUB_MMREG_IND_SYSHUB_MGCG_CTRL_SHUBCLK, data);
 168 }
 169
 170 static void nbio_v7_0_update_medium_grain_light_sleep(struct amdgpu_device *adev,
 171                                                       bool enable)
 172 {
 173         uint32_t def, data;
 174
 175         def = data = RREG32_PCIE(smnPCIE_CNTL2);
 176         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_BIF_LS)) {
 177                 data |= (PCIE_CNTL2__SLV_MEM_LS_EN_MASK |
 178                          PCIE_CNTL2__MST_MEM_LS_EN_MASK |
 179                          PCIE_CNTL2__REPLAY_MEM_LS_EN_MASK);
 180         } else {
 181                 data &= ~(PCIE_CNTL2__SLV_MEM_LS_EN_MASK |
 182                           PCIE_CNTL2__MST_MEM_LS_EN_MASK |
 183                           PCIE_CNTL2__REPLAY_MEM_LS_EN_MASK);
 184         }
 185
 186         if (def != data)
 187                 WREG32_PCIE(smnPCIE_CNTL2, data);
 188 }
 189
 190 static void nbio_v7_0_get_clockgating_state(struct amdgpu_device *adev,
 191                                             u32 *flags)
 192 {
 193         int data;
 194
 195         /* AMD_CG_SUPPORT_BIF_MGCG */
 196         data = RREG32_PCIE(smnCPM_CONTROL);
 197         if (data & CPM_CONTROL__LCLK_DYN_GATE_ENABLE_MASK)
 198                 *flags |= AMD_CG_SUPPORT_BIF_MGCG;
 199
 200         /* AMD_CG_SUPPORT_BIF_LS */
 201         data = RREG32_PCIE(smnPCIE_CNTL2);
 202         if (data & PCIE_CNTL2__SLV_MEM_LS_EN_MASK)
 203                 *flags |= AMD_CG_SUPPORT_BIF_LS;
 204 }
 205
 206 static void nbio_v7_0_ih_control(struct amdgpu_device *adev)
 207 {
 208         u32 interrupt_cntl;
 209
 210         /* setup interrupt control */
 211         WREG32_SOC15(NBIO, 0, mmINTERRUPT_CNTL2, adev->dummy_page_addr >> 8);
 212         interrupt_cntl = RREG32_SOC15(NBIO, 0, mmINTERRUPT_CNTL);
 213         /* INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK=0 - dummy read disabled with msi, enabled without msi
 214          * INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK=1 - dummy read controlled by IH_DUMMY_RD_EN
 215          */
 216         interrupt_cntl = REG_SET_FIELD(interrupt_cntl, INTERRUPT_CNTL, IH_DUMMY_RD_OVERRIDE, 0);
 217         /* INTERRUPT_CNTL__IH_REQ_NONSNOOP_EN_MASK=1 if ring is in non-cacheable memory, e.g., vram */
 218         interrupt_cntl = REG_SET_FIELD(interrupt_cntl, INTERRUPT_CNTL, IH_REQ_NONSNOOP_EN, 0);
 219         WREG32_SOC15(NBIO, 0, mmINTERRUPT_CNTL, interrupt_cntl);
 220 }
 221
 222 static u32 nbio_v7_0_get_hdp_flush_req_offset(struct amdgpu_device *adev)
 223 {
 224         return SOC15_REG_OFFSET(NBIO, 0, mmGPU_HDP_FLUSH_REQ);
 225 }
 226
 227 static u32 nbio_v7_0_get_hdp_flush_done_offset(struct amdgpu_device *adev)
 228 {
 229         return SOC15_REG_OFFSET(NBIO, 0, mmGPU_HDP_FLUSH_DONE);
 230 }
 231
 232 static u32 nbio_v7_0_get_pcie_index_offset(struct amdgpu_device *adev)
 233 {
 234         return SOC15_REG_OFFSET(NBIO, 0, mmPCIE_INDEX2);
 235 }
 236
 237 static u32 nbio_v7_0_get_pcie_data_offset(struct amdgpu_device *adev)
 238 {
 239         return SOC15_REG_OFFSET(NBIO, 0, mmPCIE_DATA2);
 240 }
 241
 242 const struct nbio_hdp_flush_reg nbio_v7_0_hdp_flush_reg = {
 243         .ref_and_mask_cp0 = GPU_HDP_FLUSH_DONE__CP0_MASK,
 244         .ref_and_mask_cp1 = GPU_HDP_FLUSH_DONE__CP1_MASK,
 245         .ref_and_mask_cp2 = GPU_HDP_FLUSH_DONE__CP2_MASK,
 246         .ref_and_mask_cp3 = GPU_HDP_FLUSH_DONE__CP3_MASK,
 247         .ref_and_mask_cp4 = GPU_HDP_FLUSH_DONE__CP4_MASK,
 248         .ref_and_mask_cp5 = GPU_HDP_FLUSH_DONE__CP5_MASK,
 249         .ref_and_mask_cp6 = GPU_HDP_FLUSH_DONE__CP6_MASK,
 250         .ref_and_mask_cp7 = GPU_HDP_FLUSH_DONE__CP7_MASK,
 251         .ref_and_mask_cp8 = GPU_HDP_FLUSH_DONE__CP8_MASK,
 252         .ref_and_mask_cp9 = GPU_HDP_FLUSH_DONE__CP9_MASK,
 253         .ref_and_mask_sdma0 = GPU_HDP_FLUSH_DONE__SDMA0_MASK,
 254         .ref_and_mask_sdma1 = GPU_HDP_FLUSH_DONE__SDMA1_MASK,
 255 };
 256
 257 static void nbio_v7_0_detect_hw_virt(struct amdgpu_device *adev)
 258 {
 259         if (is_virtual_machine())       /* passthrough mode exclus sriov mod */
 260                 adev->virt.caps |= AMDGPU_PASSTHROUGH_MODE;
 261 }
 262
 263 static void nbio_v7_0_init_registers(struct amdgpu_device *adev)
 264 {
 265
 266 }
 267
 268 const struct amdgpu_nbio_funcs nbio_v7_0_funcs = {
 269         .hdp_flush_reg = &nbio_v7_0_hdp_flush_reg,
 270         .get_hdp_flush_req_offset = nbio_v7_0_get_hdp_flush_req_offset,
 271         .get_hdp_flush_done_offset = nbio_v7_0_get_hdp_flush_done_offset,
 272         .get_pcie_index_offset = nbio_v7_0_get_pcie_index_offset,
 273         .get_pcie_data_offset = nbio_v7_0_get_pcie_data_offset,
 274         .get_rev_id = nbio_v7_0_get_rev_id,
 275         .mc_access_enable = nbio_v7_0_mc_access_enable,
 276         .hdp_flush = nbio_v7_0_hdp_flush,
 277         .get_memsize = nbio_v7_0_get_memsize,
 278         .sdma_doorbell_range = nbio_v7_0_sdma_doorbell_range,
 279         .enable_doorbell_aperture = nbio_v7_0_enable_doorbell_aperture,
 280         .enable_doorbell_selfring_aperture = nbio_v7_0_enable_doorbell_selfring_aperture,
 281         .ih_doorbell_range = nbio_v7_0_ih_doorbell_range,
 282         .update_medium_grain_clock_gating = nbio_v7_0_update_medium_grain_clock_gating,
 283         .update_medium_grain_light_sleep = nbio_v7_0_update_medium_grain_light_sleep,
 284         .get_clockgating_state = nbio_v7_0_get_clockgating_state,
 285         .ih_control = nbio_v7_0_ih_control,
 286         .init_registers = nbio_v7_0_init_registers,
 287         .detect_hw_virt = nbio_v7_0_detect_hw_virt,
 288 };