drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c

   1 /*
   2  * Copyright 2016 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23 #include "amdgpu.h"
  24 #include "amdgpu_atombios.h"
  25 #include "nbio_v7_0.h"
  26
  27 #include "nbio/nbio_7_0_default.h"
  28 #include "nbio/nbio_7_0_offset.h"
  29 #include "nbio/nbio_7_0_sh_mask.h"
  30 #include "nbio/nbio_7_0_smn.h"
  31 #include "vega10_enum.h"
  32
  33 #define smnNBIF_MGCG_CTRL_LCLK  0x1013a05c
  34
  35 static u32 nbio_v7_0_get_rev_id(struct amdgpu_device *adev)
  36 {
  37         u32 tmp = RREG32_SOC15(NBIO, 0, mmRCC_DEV0_EPF0_STRAP0);
  38
  39         tmp &= RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0_MASK;
  40         tmp >>= RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0__SHIFT;
  41
  42         return tmp;
  43 }
  44
  45 static void nbio_v7_0_mc_access_enable(struct amdgpu_device *adev, bool enable)
  46 {
  47         if (enable)
  48                 WREG32_SOC15(NBIO, 0, mmBIF_FB_EN,
  49                         BIF_FB_EN__FB_READ_EN_MASK | BIF_FB_EN__FB_WRITE_EN_MASK);
  50         else
  51                 WREG32_SOC15(NBIO, 0, mmBIF_FB_EN, 0);
  52 }
  53
  54 static void nbio_v7_0_hdp_flush(struct amdgpu_device *adev,
  55                                 struct amdgpu_ring *ring)
  56 {
  57         if (!ring || !ring->funcs->emit_wreg)
  58                 WREG32_SOC15_NO_KIQ(NBIO, 0, mmHDP_MEM_COHERENCY_FLUSH_CNTL, 0);
  59         else
  60                 amdgpu_ring_emit_wreg(ring, SOC15_REG_OFFSET(
  61                         NBIO, 0, mmHDP_MEM_COHERENCY_FLUSH_CNTL), 0);
  62 }
  63
  64 static u32 nbio_v7_0_get_memsize(struct amdgpu_device *adev)
  65 {
  66         return RREG32_SOC15(NBIO, 0, mmRCC_CONFIG_MEMSIZE);
  67 }
  68
  69 static void nbio_v7_0_sdma_doorbell_range(struct amdgpu_device *adev, int instance,
  70                         bool use_doorbell, int doorbell_index, int doorbell_size)
  71 {
  72         u32 reg = instance == 0 ? SOC15_REG_OFFSET(NBIO, 0, mmBIF_SDMA0_DOORBELL_RANGE) :
  73                         SOC15_REG_OFFSET(NBIO, 0, mmBIF_SDMA1_DOORBELL_RANGE);
  74
  75         u32 doorbell_range = RREG32(reg);
  76
  77         if (use_doorbell) {
  78                 doorbell_range = REG_SET_FIELD(doorbell_range, BIF_SDMA0_DOORBELL_RANGE, OFFSET, doorbell_index);
  79                 doorbell_range = REG_SET_FIELD(doorbell_range, BIF_SDMA0_DOORBELL_RANGE, SIZE, doorbell_size);
  80         } else
  81                 doorbell_range = REG_SET_FIELD(doorbell_range, BIF_SDMA0_DOORBELL_RANGE, SIZE, 0);
  82
  83         WREG32(reg, doorbell_range);
  84 }
  85
  86 static void nbio_v7_0_enable_doorbell_aperture(struct amdgpu_device *adev,
  87                                                bool enable)
  88 {
  89         WREG32_FIELD15(NBIO, 0, RCC_DOORBELL_APER_EN, BIF_DOORBELL_APER_EN, enable ? 1 : 0);
  90 }
  91
  92 static void nbio_v7_0_enable_doorbell_selfring_aperture(struct amdgpu_device *adev,
  93                                                         bool enable)
  94 {
  95
  96 }
  97
  98 static void nbio_v7_0_ih_doorbell_range(struct amdgpu_device *adev,
  99                                         bool use_doorbell, int doorbell_index)
 100 {
 101         u32 ih_doorbell_range = RREG32_SOC15(NBIO, 0 , mmBIF_IH_DOORBELL_RANGE);
 102
 103         if (use_doorbell) {
 104                 ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range, BIF_IH_DOORBELL_RANGE, OFFSET, doorbell_index);
 105                 ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range, BIF_IH_DOORBELL_RANGE, SIZE, 2);
 106         } else
 107                 ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range, BIF_IH_DOORBELL_RANGE, SIZE, 0);
 108
 109         WREG32_SOC15(NBIO, 0, mmBIF_IH_DOORBELL_RANGE, ih_doorbell_range);
 110 }
 111
 112 static uint32_t nbio_7_0_read_syshub_ind_mmr(struct amdgpu_device *adev, uint32_t offset)
 113 {
 114         uint32_t data;
 115
 116         WREG32_SOC15(NBIO, 0, mmSYSHUB_INDEX, offset);
 117         data = RREG32_SOC15(NBIO, 0, mmSYSHUB_DATA);
 118
 119         return data;
 120 }
 121
 122 static void nbio_7_0_write_syshub_ind_mmr(struct amdgpu_device *adev, uint32_t offset,
 123                                        uint32_t data)
 124 {
 125         WREG32_SOC15(NBIO, 0, mmSYSHUB_INDEX, offset);
 126         WREG32_SOC15(NBIO, 0, mmSYSHUB_DATA, data);
 127 }
 128
 129 static void nbio_v7_0_update_medium_grain_clock_gating(struct amdgpu_device *adev,
 130                                                        bool enable)
 131 {
 132         uint32_t def, data;
 133
 134         /* NBIF_MGCG_CTRL_LCLK */
 135         def = data = RREG32_PCIE(smnNBIF_MGCG_CTRL_LCLK);
 136
 137         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_BIF_MGCG))
 138                 data |= NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_EN_LCLK_MASK;
 139         else
 140                 data &= ~NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_EN_LCLK_MASK;
 141
 142         if (def != data)
 143                 WREG32_PCIE(smnNBIF_MGCG_CTRL_LCLK, data);
 144
 145         /* SYSHUB_MGCG_CTRL_SOCCLK */
 146         def = data = nbio_7_0_read_syshub_ind_mmr(adev, ixSYSHUB_MMREG_IND_SYSHUB_MGCG_CTRL_SOCCLK);
 147
 148         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_BIF_MGCG))
 149                 data |= SYSHUB_MMREG_DIRECT_SYSHUB_MGCG_CTRL_SOCCLK__SYSHUB_MGCG_EN_SOCCLK_MASK;
 150         else
 151                 data &= ~SYSHUB_MMREG_DIRECT_SYSHUB_MGCG_CTRL_SOCCLK__SYSHUB_MGCG_EN_SOCCLK_MASK;
 152
 153         if (def != data)
 154                 nbio_7_0_write_syshub_ind_mmr(adev, ixSYSHUB_MMREG_IND_SYSHUB_MGCG_CTRL_SOCCLK, data);
 155
 156         /* SYSHUB_MGCG_CTRL_SHUBCLK */
 157         def = data = nbio_7_0_read_syshub_ind_mmr(adev, ixSYSHUB_MMREG_IND_SYSHUB_MGCG_CTRL_SHUBCLK);
 158
 159         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_BIF_MGCG))
 160                 data |= SYSHUB_MMREG_DIRECT_SYSHUB_MGCG_CTRL_SHUBCLK__SYSHUB_MGCG_EN_SHUBCLK_MASK;
 161         else
 162                 data &= ~SYSHUB_MMREG_DIRECT_SYSHUB_MGCG_CTRL_SHUBCLK__SYSHUB_MGCG_EN_SHUBCLK_MASK;
 163
 164         if (def != data)
 165                 nbio_7_0_write_syshub_ind_mmr(adev, ixSYSHUB_MMREG_IND_SYSHUB_MGCG_CTRL_SHUBCLK, data);
 166 }
 167
 168 static void nbio_v7_0_update_medium_grain_light_sleep(struct amdgpu_device *adev,
 169                                                       bool enable)
 170 {
 171         uint32_t def, data;
 172
 173         def = data = RREG32_PCIE(smnPCIE_CNTL2);
 174         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_BIF_LS)) {
 175                 data |= (PCIE_CNTL2__SLV_MEM_LS_EN_MASK |
 176                          PCIE_CNTL2__MST_MEM_LS_EN_MASK |
 177                          PCIE_CNTL2__REPLAY_MEM_LS_EN_MASK);
 178         } else {
 179                 data &= ~(PCIE_CNTL2__SLV_MEM_LS_EN_MASK |
 180                           PCIE_CNTL2__MST_MEM_LS_EN_MASK |
 181                           PCIE_CNTL2__REPLAY_MEM_LS_EN_MASK);
 182         }
 183
 184         if (def != data)
 185                 WREG32_PCIE(smnPCIE_CNTL2, data);
 186 }
 187
 188 static void nbio_v7_0_get_clockgating_state(struct amdgpu_device *adev,
 189                                             u32 *flags)
 190 {
 191         int data;
 192
 193         /* AMD_CG_SUPPORT_BIF_MGCG */
 194         data = RREG32_PCIE(smnCPM_CONTROL);
 195         if (data & CPM_CONTROL__LCLK_DYN_GATE_ENABLE_MASK)
 196                 *flags |= AMD_CG_SUPPORT_BIF_MGCG;
 197
 198         /* AMD_CG_SUPPORT_BIF_LS */
 199         data = RREG32_PCIE(smnPCIE_CNTL2);
 200         if (data & PCIE_CNTL2__SLV_MEM_LS_EN_MASK)
 201                 *flags |= AMD_CG_SUPPORT_BIF_LS;
 202 }
 203
 204 static void nbio_v7_0_ih_control(struct amdgpu_device *adev)
 205 {
 206         u32 interrupt_cntl;
 207
 208         /* setup interrupt control */
 209         WREG32_SOC15(NBIO, 0, mmINTERRUPT_CNTL2, adev->dummy_page_addr >> 8);
 210         interrupt_cntl = RREG32_SOC15(NBIO, 0, mmINTERRUPT_CNTL);
 211         /* INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK=0 - dummy read disabled with msi, enabled without msi
 212          * INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK=1 - dummy read controlled by IH_DUMMY_RD_EN
 213          */
 214         interrupt_cntl = REG_SET_FIELD(interrupt_cntl, INTERRUPT_CNTL, IH_DUMMY_RD_OVERRIDE, 0);
 215         /* INTERRUPT_CNTL__IH_REQ_NONSNOOP_EN_MASK=1 if ring is in non-cacheable memory, e.g., vram */
 216         interrupt_cntl = REG_SET_FIELD(interrupt_cntl, INTERRUPT_CNTL, IH_REQ_NONSNOOP_EN, 0);
 217         WREG32_SOC15(NBIO, 0, mmINTERRUPT_CNTL, interrupt_cntl);
 218 }
 219
 220 static u32 nbio_v7_0_get_hdp_flush_req_offset(struct amdgpu_device *adev)
 221 {
 222         return SOC15_REG_OFFSET(NBIO, 0, mmGPU_HDP_FLUSH_REQ);
 223 }
 224
 225 static u32 nbio_v7_0_get_hdp_flush_done_offset(struct amdgpu_device *adev)
 226 {
 227         return SOC15_REG_OFFSET(NBIO, 0, mmGPU_HDP_FLUSH_DONE);
 228 }
 229
 230 static u32 nbio_v7_0_get_pcie_index_offset(struct amdgpu_device *adev)
 231 {
 232         return SOC15_REG_OFFSET(NBIO, 0, mmPCIE_INDEX2);
 233 }
 234
 235 static u32 nbio_v7_0_get_pcie_data_offset(struct amdgpu_device *adev)
 236 {
 237         return SOC15_REG_OFFSET(NBIO, 0, mmPCIE_DATA2);
 238 }
 239
 240 const struct nbio_hdp_flush_reg nbio_v7_0_hdp_flush_reg = {
 241         .ref_and_mask_cp0 = GPU_HDP_FLUSH_DONE__CP0_MASK,
 242         .ref_and_mask_cp1 = GPU_HDP_FLUSH_DONE__CP1_MASK,
 243         .ref_and_mask_cp2 = GPU_HDP_FLUSH_DONE__CP2_MASK,
 244         .ref_and_mask_cp3 = GPU_HDP_FLUSH_DONE__CP3_MASK,
 245         .ref_and_mask_cp4 = GPU_HDP_FLUSH_DONE__CP4_MASK,
 246         .ref_and_mask_cp5 = GPU_HDP_FLUSH_DONE__CP5_MASK,
 247         .ref_and_mask_cp6 = GPU_HDP_FLUSH_DONE__CP6_MASK,
 248         .ref_and_mask_cp7 = GPU_HDP_FLUSH_DONE__CP7_MASK,
 249         .ref_and_mask_cp8 = GPU_HDP_FLUSH_DONE__CP8_MASK,
 250         .ref_and_mask_cp9 = GPU_HDP_FLUSH_DONE__CP9_MASK,
 251         .ref_and_mask_sdma0 = GPU_HDP_FLUSH_DONE__SDMA0_MASK,
 252         .ref_and_mask_sdma1 = GPU_HDP_FLUSH_DONE__SDMA1_MASK,
 253 };
 254
 255 static void nbio_v7_0_detect_hw_virt(struct amdgpu_device *adev)
 256 {
 257         if (is_virtual_machine())       /* passthrough mode exclus sriov mod */
 258                 adev->virt.caps |= AMDGPU_PASSTHROUGH_MODE;
 259 }
 260
 261 static void nbio_v7_0_init_registers(struct amdgpu_device *adev)
 262 {
 263
 264 }
 265
 266 const struct amdgpu_nbio_funcs nbio_v7_0_funcs = {
 267         .hdp_flush_reg = &nbio_v7_0_hdp_flush_reg,
 268         .get_hdp_flush_req_offset = nbio_v7_0_get_hdp_flush_req_offset,
 269         .get_hdp_flush_done_offset = nbio_v7_0_get_hdp_flush_done_offset,
 270         .get_pcie_index_offset = nbio_v7_0_get_pcie_index_offset,
 271         .get_pcie_data_offset = nbio_v7_0_get_pcie_data_offset,
 272         .get_rev_id = nbio_v7_0_get_rev_id,
 273         .mc_access_enable = nbio_v7_0_mc_access_enable,
 274         .hdp_flush = nbio_v7_0_hdp_flush,
 275         .get_memsize = nbio_v7_0_get_memsize,
 276         .sdma_doorbell_range = nbio_v7_0_sdma_doorbell_range,
 277         .enable_doorbell_aperture = nbio_v7_0_enable_doorbell_aperture,
 278         .enable_doorbell_selfring_aperture = nbio_v7_0_enable_doorbell_selfring_aperture,
 279         .ih_doorbell_range = nbio_v7_0_ih_doorbell_range,
 280         .update_medium_grain_clock_gating = nbio_v7_0_update_medium_grain_clock_gating,
 281         .update_medium_grain_light_sleep = nbio_v7_0_update_medium_grain_light_sleep,
 282         .get_clockgating_state = nbio_v7_0_get_clockgating_state,
 283         .ih_control = nbio_v7_0_ih_control,
 284         .init_registers = nbio_v7_0_init_registers,
 285         .detect_hw_virt = nbio_v7_0_detect_hw_virt,
 286 };