drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c

   1 /*
   2  * Copyright 2014 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #include "amdgpu.h"
  25 #include "nbio/nbio_6_1_offset.h"
  26 #include "nbio/nbio_6_1_sh_mask.h"
  27 #include "gc/gc_9_0_offset.h"
  28 #include "gc/gc_9_0_sh_mask.h"
  29 #include "soc15.h"
  30 #include "vega10_ih.h"
  31 #include "soc15_common.h"
  32 #include "mxgpu_ai.h"
  33
  34 static void xgpu_ai_mailbox_send_ack(struct amdgpu_device *adev)
  35 {
  36         WREG8(AI_MAIBOX_CONTROL_RCV_OFFSET_BYTE, 2);
  37 }
  38
  39 static void xgpu_ai_mailbox_set_valid(struct amdgpu_device *adev, bool val)
  40 {
  41         WREG8(AI_MAIBOX_CONTROL_TRN_OFFSET_BYTE, val ? 1 : 0);
  42 }
  43
  44 /*
  45  * this peek_msg could *only* be called in IRQ routine becuase in IRQ routine
  46  * RCV_MSG_VALID filed of BIF_BX_PF0_MAILBOX_CONTROL must already be set to 1
  47  * by host.
  48  *
  49  * if called no in IRQ routine, this peek_msg cannot guaranteed to return the
  50  * correct value since it doesn't return the RCV_DW0 under the case that
  51  * RCV_MSG_VALID is set by host.
  52  */
  53 static enum idh_event xgpu_ai_mailbox_peek_msg(struct amdgpu_device *adev)
  54 {
  55         return RREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0,
  56                                 mmBIF_BX_PF0_MAILBOX_MSGBUF_RCV_DW0));
  57 }
  58
  59
  60 static int xgpu_ai_mailbox_rcv_msg(struct amdgpu_device *adev,
  61                                    enum idh_event event)
  62 {
  63         u32 reg;
  64
  65         reg = RREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0,
  66                                              mmBIF_BX_PF0_MAILBOX_MSGBUF_RCV_DW0));
  67         if (reg != event)
  68                 return -ENOENT;
  69
  70         xgpu_ai_mailbox_send_ack(adev);
  71
  72         return 0;
  73 }
  74
  75 static uint8_t xgpu_ai_peek_ack(struct amdgpu_device *adev) {
  76         return RREG8(AI_MAIBOX_CONTROL_TRN_OFFSET_BYTE) & 2;
  77 }
  78
  79 static int xgpu_ai_poll_ack(struct amdgpu_device *adev)
  80 {
  81         int timeout  = AI_MAILBOX_POLL_ACK_TIMEDOUT;
  82         u8 reg;
  83
  84         do {
  85                 reg = RREG8(AI_MAIBOX_CONTROL_TRN_OFFSET_BYTE);
  86                 if (reg & 2)
  87                         return 0;
  88
  89                 mdelay(5);
  90                 timeout -= 5;
  91         } while (timeout > 1);
  92
  93         pr_err("Doesn't get TRN_MSG_ACK from pf in %d msec\n", AI_MAILBOX_POLL_ACK_TIMEDOUT);
  94
  95         return -ETIME;
  96 }
  97
  98 static int xgpu_ai_poll_msg(struct amdgpu_device *adev, enum idh_event event)
  99 {
 100         int r, timeout = AI_MAILBOX_POLL_MSG_TIMEDOUT;
 101
 102         do {
 103                 r = xgpu_ai_mailbox_rcv_msg(adev, event);
 104                 if (!r)
 105                         return 0;
 106
 107                 msleep(10);
 108                 timeout -= 10;
 109         } while (timeout > 1);
 110
 111         pr_err("Doesn't get msg:%d from pf, error=%d\n", event, r);
 112
 113         return -ETIME;
 114 }
 115
 116 static void xgpu_ai_mailbox_trans_msg (struct amdgpu_device *adev,
 117               enum idh_request req, u32 data1, u32 data2, u32 data3) {
 118         u32 reg;
 119         int r;
 120         uint8_t trn;
 121
 122         /* IMPORTANT:
 123          * clear TRN_MSG_VALID valid to clear host's RCV_MSG_ACK
 124          * and with host's RCV_MSG_ACK cleared hw automatically clear host's RCV_MSG_ACK
 125          * which lead to VF's TRN_MSG_ACK cleared, otherwise below xgpu_ai_poll_ack()
 126          * will return immediatly
 127          */
 128         do {
 129                 xgpu_ai_mailbox_set_valid(adev, false);
 130                 trn = xgpu_ai_peek_ack(adev);
 131                 if (trn) {
 132                         pr_err("trn=%x ACK should not assert! wait again !\n", trn);
 133                         msleep(1);
 134                 }
 135         } while(trn);
 136
 137         reg = RREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0,
 138                                              mmBIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW0));
 139         reg = REG_SET_FIELD(reg, BIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW0,
 140                             MSGBUF_DATA, req);
 141         WREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW0),
 142                       reg);
 143         WREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW1),
 144                                 data1);
 145         WREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW2),
 146                                 data2);
 147         WREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW3),
 148                                 data3);
 149
 150         xgpu_ai_mailbox_set_valid(adev, true);
 151
 152         /* start to poll ack */
 153         r = xgpu_ai_poll_ack(adev);
 154         if (r)
 155                 pr_err("Doesn't get ack from pf, continue\n");
 156
 157         xgpu_ai_mailbox_set_valid(adev, false);
 158 }
 159
 160 static int xgpu_ai_send_access_requests(struct amdgpu_device *adev,
 161                                         enum idh_request req)
 162 {
 163         int r;
 164
 165         xgpu_ai_mailbox_trans_msg(adev, req, 0, 0, 0);
 166
 167         /* start to check msg if request is idh_req_gpu_init_access */
 168         if (req == IDH_REQ_GPU_INIT_ACCESS ||
 169                 req == IDH_REQ_GPU_FINI_ACCESS ||
 170                 req == IDH_REQ_GPU_RESET_ACCESS) {
 171                 r = xgpu_ai_poll_msg(adev, IDH_READY_TO_ACCESS_GPU);
 172                 if (r) {
 173                         pr_err("Doesn't get READY_TO_ACCESS_GPU from pf, give up\n");
 174                         return r;
 175                 }
 176                 /* Retrieve checksum from mailbox2 */
 177                 if (req == IDH_REQ_GPU_INIT_ACCESS) {
 178                         adev->virt.fw_reserve.checksum_key =
 179                                 RREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0,
 180                                         mmBIF_BX_PF0_MAILBOX_MSGBUF_RCV_DW2));
 181                 }
 182         }
 183
 184         return 0;
 185 }
 186
 187 static int xgpu_ai_request_reset(struct amdgpu_device *adev)
 188 {
 189         return xgpu_ai_send_access_requests(adev, IDH_REQ_GPU_RESET_ACCESS);
 190 }
 191
 192 static int xgpu_ai_request_full_gpu_access(struct amdgpu_device *adev,
 193                                            bool init)
 194 {
 195         enum idh_request req;
 196
 197         req = init ? IDH_REQ_GPU_INIT_ACCESS : IDH_REQ_GPU_FINI_ACCESS;
 198         return xgpu_ai_send_access_requests(adev, req);
 199 }
 200
 201 static int xgpu_ai_release_full_gpu_access(struct amdgpu_device *adev,
 202                                            bool init)
 203 {
 204         enum idh_request req;
 205         int r = 0;
 206
 207         req = init ? IDH_REL_GPU_INIT_ACCESS : IDH_REL_GPU_FINI_ACCESS;
 208         r = xgpu_ai_send_access_requests(adev, req);
 209
 210         return r;
 211 }
 212
 213 static int xgpu_ai_mailbox_ack_irq(struct amdgpu_device *adev,
 214                                         struct amdgpu_irq_src *source,
 215                                         struct amdgpu_iv_entry *entry)
 216 {
 217         DRM_DEBUG("get ack intr and do nothing.\n");
 218         return 0;
 219 }
 220
 221 static int xgpu_ai_set_mailbox_ack_irq(struct amdgpu_device *adev,
 222                                         struct amdgpu_irq_src *source,
 223                                         unsigned type,
 224                                         enum amdgpu_interrupt_state state)
 225 {
 226         u32 tmp = RREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF0_MAILBOX_INT_CNTL));
 227
 228         tmp = REG_SET_FIELD(tmp, BIF_BX_PF0_MAILBOX_INT_CNTL, ACK_INT_EN,
 229                                 (state == AMDGPU_IRQ_STATE_ENABLE) ? 1 : 0);
 230         WREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF0_MAILBOX_INT_CNTL), tmp);
 231
 232         return 0;
 233 }
 234
 235 static void xgpu_ai_mailbox_flr_work(struct work_struct *work)
 236 {
 237         struct amdgpu_virt *virt = container_of(work, struct amdgpu_virt, flr_work);
 238         struct amdgpu_device *adev = container_of(virt, struct amdgpu_device, virt);
 239         int timeout = AI_MAILBOX_POLL_FLR_TIMEDOUT;
 240         int locked;
 241
 242         /* block amdgpu_gpu_recover till msg FLR COMPLETE received,
 243          * otherwise the mailbox msg will be ruined/reseted by
 244          * the VF FLR.
 245          *
 246          * we can unlock the lock_reset to allow "amdgpu_job_timedout"
 247          * to run gpu_recover() after FLR_NOTIFICATION_CMPL received
 248          * which means host side had finished this VF's FLR.
 249          */
 250         locked = mutex_trylock(&adev->lock_reset);
 251         if (locked)
 252                 adev->in_gpu_reset = 1;
 253
 254         do {
 255                 if (xgpu_ai_mailbox_peek_msg(adev) == IDH_FLR_NOTIFICATION_CMPL)
 256                         goto flr_done;
 257
 258                 msleep(10);
 259                 timeout -= 10;
 260         } while (timeout > 1);
 261
 262 flr_done:
 263         if (locked)
 264                 mutex_unlock(&adev->lock_reset);
 265
 266         /* Trigger recovery for world switch failure if no TDR */
 267         if (amdgpu_lockup_timeout == 0)
 268                 amdgpu_device_gpu_recover(adev, NULL, true);
 269 }
 270
 271 static int xgpu_ai_set_mailbox_rcv_irq(struct amdgpu_device *adev,
 272                                        struct amdgpu_irq_src *src,
 273                                        unsigned type,
 274                                        enum amdgpu_interrupt_state state)
 275 {
 276         u32 tmp = RREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF0_MAILBOX_INT_CNTL));
 277
 278         tmp = REG_SET_FIELD(tmp, BIF_BX_PF0_MAILBOX_INT_CNTL, VALID_INT_EN,
 279                             (state == AMDGPU_IRQ_STATE_ENABLE) ? 1 : 0);
 280         WREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF0_MAILBOX_INT_CNTL), tmp);
 281
 282         return 0;
 283 }
 284
 285 static int xgpu_ai_mailbox_rcv_irq(struct amdgpu_device *adev,
 286                                    struct amdgpu_irq_src *source,
 287                                    struct amdgpu_iv_entry *entry)
 288 {
 289         enum idh_event event = xgpu_ai_mailbox_peek_msg(adev);
 290
 291         switch (event) {
 292                 case IDH_FLR_NOTIFICATION:
 293                 if (amdgpu_sriov_runtime(adev))
 294                         schedule_work(&adev->virt.flr_work);
 295                 break;
 296                 /* READY_TO_ACCESS_GPU is fetched by kernel polling, IRQ can ignore
 297                  * it byfar since that polling thread will handle it,
 298                  * other msg like flr complete is not handled here.
 299                  */
 300                 case IDH_CLR_MSG_BUF:
 301                 case IDH_FLR_NOTIFICATION_CMPL:
 302                 case IDH_READY_TO_ACCESS_GPU:
 303                 default:
 304                 break;
 305         }
 306
 307         return 0;
 308 }
 309
 310 static const struct amdgpu_irq_src_funcs xgpu_ai_mailbox_ack_irq_funcs = {
 311         .set = xgpu_ai_set_mailbox_ack_irq,
 312         .process = xgpu_ai_mailbox_ack_irq,
 313 };
 314
 315 static const struct amdgpu_irq_src_funcs xgpu_ai_mailbox_rcv_irq_funcs = {
 316         .set = xgpu_ai_set_mailbox_rcv_irq,
 317         .process = xgpu_ai_mailbox_rcv_irq,
 318 };
 319
 320 void xgpu_ai_mailbox_set_irq_funcs(struct amdgpu_device *adev)
 321 {
 322         adev->virt.ack_irq.num_types = 1;
 323         adev->virt.ack_irq.funcs = &xgpu_ai_mailbox_ack_irq_funcs;
 324         adev->virt.rcv_irq.num_types = 1;
 325         adev->virt.rcv_irq.funcs = &xgpu_ai_mailbox_rcv_irq_funcs;
 326 }
 327
 328 int xgpu_ai_mailbox_add_irq_id(struct amdgpu_device *adev)
 329 {
 330         int r;
 331
 332         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_BIF, 135, &adev->virt.rcv_irq);
 333         if (r)
 334                 return r;
 335
 336         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_BIF, 138, &adev->virt.ack_irq);
 337         if (r) {
 338                 amdgpu_irq_put(adev, &adev->virt.rcv_irq, 0);
 339                 return r;
 340         }
 341
 342         return 0;
 343 }
 344
 345 int xgpu_ai_mailbox_get_irq(struct amdgpu_device *adev)
 346 {
 347         int r;
 348
 349         r = amdgpu_irq_get(adev, &adev->virt.rcv_irq, 0);
 350         if (r)
 351                 return r;
 352         r = amdgpu_irq_get(adev, &adev->virt.ack_irq, 0);
 353         if (r) {
 354                 amdgpu_irq_put(adev, &adev->virt.rcv_irq, 0);
 355                 return r;
 356         }
 357
 358         INIT_WORK(&adev->virt.flr_work, xgpu_ai_mailbox_flr_work);
 359
 360         return 0;
 361 }
 362
 363 void xgpu_ai_mailbox_put_irq(struct amdgpu_device *adev)
 364 {
 365         amdgpu_irq_put(adev, &adev->virt.ack_irq, 0);
 366         amdgpu_irq_put(adev, &adev->virt.rcv_irq, 0);
 367 }
 368
 369 const struct amdgpu_virt_ops xgpu_ai_virt_ops = {
 370         .req_full_gpu   = xgpu_ai_request_full_gpu_access,
 371         .rel_full_gpu   = xgpu_ai_release_full_gpu_access,
 372         .reset_gpu = xgpu_ai_request_reset,
 373         .wait_reset = NULL,
 374         .trans_msg = xgpu_ai_mailbox_trans_msg,
 375 };