2 * Copyright 2020 Advanced Micro Devices, Inc.
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5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
24 #ifndef __MMSCH_V3_0_H__
25 #define __MMSCH_V3_0_H__
27 #include "amdgpu_vcn.h"
29 #define MMSCH_VERSION_MAJOR 3
30 #define MMSCH_VERSION_MINOR 0
31 #define MMSCH_VERSION (MMSCH_VERSION_MAJOR << 16 | MMSCH_VERSION_MINOR)
33 enum mmsch_v3_0_command_type {
34 MMSCH_COMMAND__DIRECT_REG_WRITE = 0,
35 MMSCH_COMMAND__DIRECT_REG_POLLING = 2,
36 MMSCH_COMMAND__DIRECT_REG_READ_MODIFY_WRITE = 3,
37 MMSCH_COMMAND__INDIRECT_REG_WRITE = 8,
38 MMSCH_COMMAND__END = 0xf
41 struct mmsch_v3_0_table_info {
43 uint32_t table_offset;
47 struct mmsch_v3_0_init_header {
50 struct mmsch_v3_0_table_info inst[AMDGPU_MAX_VCN_INSTANCES];
53 struct mmsch_v3_0_cmd_direct_reg_header {
54 uint32_t reg_offset : 28;
55 uint32_t command_type : 4;
58 struct mmsch_v3_0_cmd_indirect_reg_header {
59 uint32_t reg_offset : 20;
60 uint32_t reg_idx_space : 8;
61 uint32_t command_type : 4;
64 struct mmsch_v3_0_cmd_direct_write {
65 struct mmsch_v3_0_cmd_direct_reg_header cmd_header;
69 struct mmsch_v3_0_cmd_direct_read_modify_write {
70 struct mmsch_v3_0_cmd_direct_reg_header cmd_header;
75 struct mmsch_v3_0_cmd_direct_polling {
76 struct mmsch_v3_0_cmd_direct_reg_header cmd_header;
81 struct mmsch_v3_0_cmd_end {
82 struct mmsch_v3_0_cmd_direct_reg_header cmd_header;
85 struct mmsch_v3_0_cmd_indirect_write {
86 struct mmsch_v3_0_cmd_indirect_reg_header cmd_header;
90 #define MMSCH_V3_0_INSERT_DIRECT_RD_MOD_WT(reg, mask, data) { \
91 size = sizeof(struct mmsch_v3_0_cmd_direct_read_modify_write); \
93 direct_rd_mod_wt.cmd_header.reg_offset = reg; \
94 direct_rd_mod_wt.mask_value = mask; \
95 direct_rd_mod_wt.write_data = data; \
96 memcpy((void *)table_loc, &direct_rd_mod_wt, size); \
97 table_loc += size_dw; \
98 table_size += size_dw; \
101 #define MMSCH_V3_0_INSERT_DIRECT_WT(reg, value) { \
102 size = sizeof(struct mmsch_v3_0_cmd_direct_write); \
103 size_dw = size / 4; \
104 direct_wt.cmd_header.reg_offset = reg; \
105 direct_wt.reg_value = value; \
106 memcpy((void *)table_loc, &direct_wt, size); \
107 table_loc += size_dw; \
108 table_size += size_dw; \
111 #define MMSCH_V3_0_INSERT_DIRECT_POLL(reg, mask, wait) { \
112 size = sizeof(struct mmsch_v3_0_cmd_direct_polling); \
113 size_dw = size / 4; \
114 direct_poll.cmd_header.reg_offset = reg; \
115 direct_poll.mask_value = mask; \
116 direct_poll.wait_value = wait; \
117 memcpy((void *)table_loc, &direct_poll, size); \
118 table_loc += size_dw; \
119 table_size += size_dw; \
122 #define MMSCH_V3_0_INSERT_END() { \
123 size = sizeof(struct mmsch_v3_0_cmd_end); \
124 size_dw = size / 4; \
125 memcpy((void *)table_loc, &end, size); \
126 table_loc += size_dw; \
127 table_size += size_dw; \