drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c

   1 /*
   2  * Copyright 2018 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23 #include "amdgpu.h"
  24 #include "amdgpu_ras.h"
  25 #include "mmhub_v9_4.h"
  26
  27 #include "mmhub/mmhub_9_4_1_offset.h"
  28 #include "mmhub/mmhub_9_4_1_sh_mask.h"
  29 #include "mmhub/mmhub_9_4_1_default.h"
  30 #include "athub/athub_1_0_offset.h"
  31 #include "athub/athub_1_0_sh_mask.h"
  32 #include "vega10_enum.h"
  33 #include "soc15.h"
  34 #include "soc15_common.h"
  35
  36 #define MMHUB_NUM_INSTANCES                     2
  37 #define MMHUB_INSTANCE_REGISTER_OFFSET          0x3000
  38
  39 static u64 mmhub_v9_4_get_fb_location(struct amdgpu_device *adev)
  40 {
  41         /* The base should be same b/t 2 mmhubs on Acrturus. Read one here. */
  42         u64 base = RREG32_SOC15(MMHUB, 0, mmVMSHAREDVC0_MC_VM_FB_LOCATION_BASE);
  43         u64 top = RREG32_SOC15(MMHUB, 0, mmVMSHAREDVC0_MC_VM_FB_LOCATION_TOP);
  44
  45         base &= VMSHAREDVC0_MC_VM_FB_LOCATION_BASE__FB_BASE_MASK;
  46         base <<= 24;
  47
  48         top &= VMSHAREDVC0_MC_VM_FB_LOCATION_TOP__FB_TOP_MASK;
  49         top <<= 24;
  50
  51         adev->gmc.fb_start = base;
  52         adev->gmc.fb_end = top;
  53
  54         return base;
  55 }
  56
  57 static void mmhub_v9_4_setup_hubid_vm_pt_regs(struct amdgpu_device *adev, int hubid,
  58                                 uint32_t vmid, uint64_t value)
  59 {
  60         struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB_0];
  61
  62         WREG32_SOC15_OFFSET(MMHUB, 0,
  63                             mmVML2VC0_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32,
  64                             hub->ctx_addr_distance * vmid + hubid * MMHUB_INSTANCE_REGISTER_OFFSET,
  65                             lower_32_bits(value));
  66
  67         WREG32_SOC15_OFFSET(MMHUB, 0,
  68                             mmVML2VC0_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32,
  69                             hub->ctx_addr_distance * vmid + hubid * MMHUB_INSTANCE_REGISTER_OFFSET,
  70                             upper_32_bits(value));
  71
  72 }
  73
  74 static void mmhub_v9_4_init_gart_aperture_regs(struct amdgpu_device *adev,
  75                                                int hubid)
  76 {
  77         uint64_t pt_base = amdgpu_gmc_pd_addr(adev->gart.bo);
  78
  79         mmhub_v9_4_setup_hubid_vm_pt_regs(adev, hubid, 0, pt_base);
  80
  81         WREG32_SOC15_OFFSET(MMHUB, 0,
  82                             mmVML2VC0_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32,
  83                             hubid * MMHUB_INSTANCE_REGISTER_OFFSET,
  84                             (u32)(adev->gmc.gart_start >> 12));
  85         WREG32_SOC15_OFFSET(MMHUB, 0,
  86                             mmVML2VC0_VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32,
  87                             hubid * MMHUB_INSTANCE_REGISTER_OFFSET,
  88                             (u32)(adev->gmc.gart_start >> 44));
  89
  90         WREG32_SOC15_OFFSET(MMHUB, 0,
  91                             mmVML2VC0_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32,
  92                             hubid * MMHUB_INSTANCE_REGISTER_OFFSET,
  93                             (u32)(adev->gmc.gart_end >> 12));
  94         WREG32_SOC15_OFFSET(MMHUB, 0,
  95                             mmVML2VC0_VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32,
  96                             hubid * MMHUB_INSTANCE_REGISTER_OFFSET,
  97                             (u32)(adev->gmc.gart_end >> 44));
  98 }
  99
 100 static void mmhub_v9_4_setup_vm_pt_regs(struct amdgpu_device *adev, uint32_t vmid,
 101                                 uint64_t page_table_base)
 102 {
 103         int i;
 104
 105         for (i = 0; i < MMHUB_NUM_INSTANCES; i++)
 106                 mmhub_v9_4_setup_hubid_vm_pt_regs(adev, i, vmid,
 107                                 page_table_base);
 108 }
 109
 110 static void mmhub_v9_4_init_system_aperture_regs(struct amdgpu_device *adev,
 111                                                  int hubid)
 112 {
 113         uint64_t value;
 114         uint32_t tmp;
 115
 116         /* Program the AGP BAR */
 117         WREG32_SOC15_OFFSET(MMHUB, 0, mmVMSHAREDVC0_MC_VM_AGP_BASE,
 118                             hubid * MMHUB_INSTANCE_REGISTER_OFFSET,
 119                             0);
 120         WREG32_SOC15_OFFSET(MMHUB, 0, mmVMSHAREDVC0_MC_VM_AGP_TOP,
 121                             hubid * MMHUB_INSTANCE_REGISTER_OFFSET,
 122                             adev->gmc.agp_end >> 24);
 123         WREG32_SOC15_OFFSET(MMHUB, 0, mmVMSHAREDVC0_MC_VM_AGP_BOT,
 124                             hubid * MMHUB_INSTANCE_REGISTER_OFFSET,
 125                             adev->gmc.agp_start >> 24);
 126
 127         if (!amdgpu_sriov_vf(adev)) {
 128                 /* Program the system aperture low logical page number. */
 129                 WREG32_SOC15_OFFSET(
 130                         MMHUB, 0, mmVMSHAREDVC0_MC_VM_SYSTEM_APERTURE_LOW_ADDR,
 131                         hubid * MMHUB_INSTANCE_REGISTER_OFFSET,
 132                         min(adev->gmc.fb_start, adev->gmc.agp_start) >> 18);
 133                 WREG32_SOC15_OFFSET(
 134                         MMHUB, 0, mmVMSHAREDVC0_MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
 135                         hubid * MMHUB_INSTANCE_REGISTER_OFFSET,
 136                         max(adev->gmc.fb_end, adev->gmc.agp_end) >> 18);
 137
 138                 /* Set default page address. */
 139                 value = amdgpu_gmc_vram_mc2pa(adev, adev->vram_scratch.gpu_addr);
 140                 WREG32_SOC15_OFFSET(
 141                         MMHUB, 0,
 142                         mmVMSHAREDPF0_MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB,
 143                         hubid * MMHUB_INSTANCE_REGISTER_OFFSET,
 144                         (u32)(value >> 12));
 145                 WREG32_SOC15_OFFSET(
 146                         MMHUB, 0,
 147                         mmVMSHAREDPF0_MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB,
 148                         hubid * MMHUB_INSTANCE_REGISTER_OFFSET,
 149                         (u32)(value >> 44));
 150
 151                 /* Program "protection fault". */
 152                 WREG32_SOC15_OFFSET(
 153                         MMHUB, 0,
 154                         mmVML2PF0_VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32,
 155                         hubid * MMHUB_INSTANCE_REGISTER_OFFSET,
 156                         (u32)(adev->dummy_page_addr >> 12));
 157                 WREG32_SOC15_OFFSET(
 158                         MMHUB, 0,
 159                         mmVML2PF0_VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32,
 160                         hubid * MMHUB_INSTANCE_REGISTER_OFFSET,
 161                         (u32)((u64)adev->dummy_page_addr >> 44));
 162
 163                 tmp = RREG32_SOC15_OFFSET(
 164                         MMHUB, 0, mmVML2PF0_VM_L2_PROTECTION_FAULT_CNTL2,
 165                         hubid * MMHUB_INSTANCE_REGISTER_OFFSET);
 166                 tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_PROTECTION_FAULT_CNTL2,
 167                                     ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY, 1);
 168                 WREG32_SOC15_OFFSET(MMHUB, 0,
 169                                     mmVML2PF0_VM_L2_PROTECTION_FAULT_CNTL2,
 170                                     hubid * MMHUB_INSTANCE_REGISTER_OFFSET,
 171                                     tmp);
 172         }
 173 }
 174
 175 static void mmhub_v9_4_init_tlb_regs(struct amdgpu_device *adev, int hubid)
 176 {
 177         uint32_t tmp;
 178
 179         /* Setup TLB control */
 180         tmp = RREG32_SOC15_OFFSET(MMHUB, 0,
 181                            mmVMSHAREDVC0_MC_VM_MX_L1_TLB_CNTL,
 182                            hubid * MMHUB_INSTANCE_REGISTER_OFFSET);
 183
 184         tmp = REG_SET_FIELD(tmp, VMSHAREDVC0_MC_VM_MX_L1_TLB_CNTL,
 185                             ENABLE_L1_TLB, 1);
 186         tmp = REG_SET_FIELD(tmp, VMSHAREDVC0_MC_VM_MX_L1_TLB_CNTL,
 187                             SYSTEM_ACCESS_MODE, 3);
 188         tmp = REG_SET_FIELD(tmp, VMSHAREDVC0_MC_VM_MX_L1_TLB_CNTL,
 189                             ENABLE_ADVANCED_DRIVER_MODEL, 1);
 190         tmp = REG_SET_FIELD(tmp, VMSHAREDVC0_MC_VM_MX_L1_TLB_CNTL,
 191                             SYSTEM_APERTURE_UNMAPPED_ACCESS, 0);
 192         tmp = REG_SET_FIELD(tmp, VMSHAREDVC0_MC_VM_MX_L1_TLB_CNTL,
 193                             ECO_BITS, 0);
 194         tmp = REG_SET_FIELD(tmp, VMSHAREDVC0_MC_VM_MX_L1_TLB_CNTL,
 195                             MTYPE, MTYPE_UC);/* XXX for emulation. */
 196         tmp = REG_SET_FIELD(tmp, VMSHAREDVC0_MC_VM_MX_L1_TLB_CNTL,
 197                             ATC_EN, 1);
 198
 199         WREG32_SOC15_OFFSET(MMHUB, 0, mmVMSHAREDVC0_MC_VM_MX_L1_TLB_CNTL,
 200                             hubid * MMHUB_INSTANCE_REGISTER_OFFSET, tmp);
 201 }
 202
 203 static void mmhub_v9_4_init_cache_regs(struct amdgpu_device *adev, int hubid)
 204 {
 205         uint32_t tmp;
 206
 207         /* Setup L2 cache */
 208         tmp = RREG32_SOC15_OFFSET(MMHUB, 0, mmVML2PF0_VM_L2_CNTL,
 209                                   hubid * MMHUB_INSTANCE_REGISTER_OFFSET);
 210         tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_CNTL,
 211                             ENABLE_L2_CACHE, 1);
 212         tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_CNTL,
 213                             ENABLE_L2_FRAGMENT_PROCESSING, 1);
 214         /* XXX for emulation, Refer to closed source code.*/
 215         tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_CNTL,
 216                             L2_PDE0_CACHE_TAG_GENERATION_MODE, 0);
 217         tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_CNTL,
 218                             PDE_FAULT_CLASSIFICATION, 0);
 219         tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_CNTL,
 220                             CONTEXT1_IDENTITY_ACCESS_MODE, 1);
 221         tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_CNTL,
 222                             IDENTITY_MODE_FRAGMENT_SIZE, 0);
 223         WREG32_SOC15_OFFSET(MMHUB, 0, mmVML2PF0_VM_L2_CNTL,
 224                      hubid * MMHUB_INSTANCE_REGISTER_OFFSET, tmp);
 225
 226         tmp = RREG32_SOC15_OFFSET(MMHUB, 0, mmVML2PF0_VM_L2_CNTL2,
 227                                   hubid * MMHUB_INSTANCE_REGISTER_OFFSET);
 228         tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_CNTL2,
 229                             INVALIDATE_ALL_L1_TLBS, 1);
 230         tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_CNTL2,
 231                             INVALIDATE_L2_CACHE, 1);
 232         WREG32_SOC15_OFFSET(MMHUB, 0, mmVML2PF0_VM_L2_CNTL2,
 233                             hubid * MMHUB_INSTANCE_REGISTER_OFFSET, tmp);
 234
 235         tmp = mmVML2PF0_VM_L2_CNTL3_DEFAULT;
 236         if (adev->gmc.translate_further) {
 237                 tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_CNTL3, BANK_SELECT, 12);
 238                 tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_CNTL3,
 239                                     L2_CACHE_BIGK_FRAGMENT_SIZE, 9);
 240         } else {
 241                 tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_CNTL3, BANK_SELECT, 9);
 242                 tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_CNTL3,
 243                                     L2_CACHE_BIGK_FRAGMENT_SIZE, 6);
 244         }
 245         WREG32_SOC15_OFFSET(MMHUB, 0, mmVML2PF0_VM_L2_CNTL3,
 246                             hubid * MMHUB_INSTANCE_REGISTER_OFFSET, tmp);
 247
 248         tmp = mmVML2PF0_VM_L2_CNTL4_DEFAULT;
 249         tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_CNTL4,
 250                             VMC_TAP_PDE_REQUEST_PHYSICAL, 0);
 251         tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_CNTL4,
 252                             VMC_TAP_PTE_REQUEST_PHYSICAL, 0);
 253         WREG32_SOC15_OFFSET(MMHUB, 0, mmVML2PF0_VM_L2_CNTL4,
 254                             hubid * MMHUB_INSTANCE_REGISTER_OFFSET, tmp);
 255 }
 256
 257 static void mmhub_v9_4_enable_system_domain(struct amdgpu_device *adev,
 258                                             int hubid)
 259 {
 260         uint32_t tmp;
 261
 262         tmp = RREG32_SOC15_OFFSET(MMHUB, 0, mmVML2VC0_VM_CONTEXT0_CNTL,
 263                                   hubid * MMHUB_INSTANCE_REGISTER_OFFSET);
 264         tmp = REG_SET_FIELD(tmp, VML2VC0_VM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1);
 265         tmp = REG_SET_FIELD(tmp, VML2VC0_VM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0);
 266         tmp = REG_SET_FIELD(tmp, VML2VC0_VM_CONTEXT0_CNTL,
 267                             RETRY_PERMISSION_OR_INVALID_PAGE_FAULT, 0);
 268         WREG32_SOC15_OFFSET(MMHUB, 0, mmVML2VC0_VM_CONTEXT0_CNTL,
 269                             hubid * MMHUB_INSTANCE_REGISTER_OFFSET, tmp);
 270 }
 271
 272 static void mmhub_v9_4_disable_identity_aperture(struct amdgpu_device *adev,
 273                                                  int hubid)
 274 {
 275         WREG32_SOC15_OFFSET(MMHUB, 0,
 276                     mmVML2PF0_VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32,
 277                     hubid * MMHUB_INSTANCE_REGISTER_OFFSET, 0XFFFFFFFF);
 278         WREG32_SOC15_OFFSET(MMHUB, 0,
 279                     mmVML2PF0_VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32,
 280                     hubid * MMHUB_INSTANCE_REGISTER_OFFSET, 0x0000000F);
 281
 282         WREG32_SOC15_OFFSET(MMHUB, 0,
 283                     mmVML2PF0_VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32,
 284                     hubid * MMHUB_INSTANCE_REGISTER_OFFSET, 0);
 285         WREG32_SOC15_OFFSET(MMHUB, 0,
 286                     mmVML2PF0_VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32,
 287                     hubid * MMHUB_INSTANCE_REGISTER_OFFSET, 0);
 288
 289         WREG32_SOC15_OFFSET(MMHUB, 0,
 290                     mmVML2PF0_VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32,
 291                     hubid * MMHUB_INSTANCE_REGISTER_OFFSET, 0);
 292         WREG32_SOC15_OFFSET(MMHUB, 0,
 293                     mmVML2PF0_VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32,
 294                     hubid * MMHUB_INSTANCE_REGISTER_OFFSET, 0);
 295 }
 296
 297 static void mmhub_v9_4_setup_vmid_config(struct amdgpu_device *adev, int hubid)
 298 {
 299         struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB_0];
 300         uint32_t tmp;
 301         int i;
 302
 303         for (i = 0; i <= 14; i++) {
 304                 tmp = RREG32_SOC15_OFFSET(MMHUB, 0, mmVML2VC0_VM_CONTEXT1_CNTL,
 305                                 hubid * MMHUB_INSTANCE_REGISTER_OFFSET + i);
 306                 tmp = REG_SET_FIELD(tmp, VML2VC0_VM_CONTEXT1_CNTL,
 307                                     ENABLE_CONTEXT, 1);
 308                 tmp = REG_SET_FIELD(tmp, VML2VC0_VM_CONTEXT1_CNTL,
 309                                     PAGE_TABLE_DEPTH,
 310                                     adev->vm_manager.num_level);
 311                 tmp = REG_SET_FIELD(tmp, VML2VC0_VM_CONTEXT1_CNTL,
 312                                     RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 313                 tmp = REG_SET_FIELD(tmp, VML2VC0_VM_CONTEXT1_CNTL,
 314                                     DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT,
 315                                     1);
 316                 tmp = REG_SET_FIELD(tmp, VML2VC0_VM_CONTEXT1_CNTL,
 317                                     PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 318                 tmp = REG_SET_FIELD(tmp, VML2VC0_VM_CONTEXT1_CNTL,
 319                                     VALID_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 320                 tmp = REG_SET_FIELD(tmp, VML2VC0_VM_CONTEXT1_CNTL,
 321                                     READ_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 322                 tmp = REG_SET_FIELD(tmp, VML2VC0_VM_CONTEXT1_CNTL,
 323                                     WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 324                 tmp = REG_SET_FIELD(tmp, VML2VC0_VM_CONTEXT1_CNTL,
 325                                     EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 326                 tmp = REG_SET_FIELD(tmp, VML2VC0_VM_CONTEXT1_CNTL,
 327                                     PAGE_TABLE_BLOCK_SIZE,
 328                                     adev->vm_manager.block_size - 9);
 329                 /* Send no-retry XNACK on fault to suppress VM fault storm. */
 330                 tmp = REG_SET_FIELD(tmp, VML2VC0_VM_CONTEXT1_CNTL,
 331                                     RETRY_PERMISSION_OR_INVALID_PAGE_FAULT,
 332                                     !adev->gmc.noretry);
 333                 WREG32_SOC15_OFFSET(MMHUB, 0, mmVML2VC0_VM_CONTEXT1_CNTL,
 334                                     hubid * MMHUB_INSTANCE_REGISTER_OFFSET +
 335                                     i * hub->ctx_distance, tmp);
 336                 WREG32_SOC15_OFFSET(MMHUB, 0,
 337                             mmVML2VC0_VM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32,
 338                             hubid * MMHUB_INSTANCE_REGISTER_OFFSET +
 339                             i * hub->ctx_addr_distance, 0);
 340                 WREG32_SOC15_OFFSET(MMHUB, 0,
 341                             mmVML2VC0_VM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32,
 342                             hubid * MMHUB_INSTANCE_REGISTER_OFFSET +
 343                             i * hub->ctx_addr_distance, 0);
 344                 WREG32_SOC15_OFFSET(MMHUB, 0,
 345                                 mmVML2VC0_VM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32,
 346                                 hubid * MMHUB_INSTANCE_REGISTER_OFFSET +
 347                                 i * hub->ctx_addr_distance,
 348                                 lower_32_bits(adev->vm_manager.max_pfn - 1));
 349                 WREG32_SOC15_OFFSET(MMHUB, 0,
 350                                 mmVML2VC0_VM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32,
 351                                 hubid * MMHUB_INSTANCE_REGISTER_OFFSET +
 352                                 i * hub->ctx_addr_distance,
 353                                 upper_32_bits(adev->vm_manager.max_pfn - 1));
 354         }
 355 }
 356
 357 static void mmhub_v9_4_program_invalidation(struct amdgpu_device *adev,
 358                                             int hubid)
 359 {
 360         struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB_0];
 361         unsigned i;
 362
 363         for (i = 0; i < 18; ++i) {
 364                 WREG32_SOC15_OFFSET(MMHUB, 0,
 365                                 mmVML2VC0_VM_INVALIDATE_ENG0_ADDR_RANGE_LO32,
 366                                 hubid * MMHUB_INSTANCE_REGISTER_OFFSET +
 367                                 i * hub->eng_addr_distance,
 368                                 0xffffffff);
 369                 WREG32_SOC15_OFFSET(MMHUB, 0,
 370                                 mmVML2VC0_VM_INVALIDATE_ENG0_ADDR_RANGE_HI32,
 371                                 hubid * MMHUB_INSTANCE_REGISTER_OFFSET +
 372                                 i * hub->eng_addr_distance,
 373                                 0x1f);
 374         }
 375 }
 376
 377 static int mmhub_v9_4_gart_enable(struct amdgpu_device *adev)
 378 {
 379         int i;
 380
 381         for (i = 0; i < MMHUB_NUM_INSTANCES; i++) {
 382                 /* GART Enable. */
 383                 mmhub_v9_4_init_gart_aperture_regs(adev, i);
 384                 mmhub_v9_4_init_system_aperture_regs(adev, i);
 385                 mmhub_v9_4_init_tlb_regs(adev, i);
 386                 if (!amdgpu_sriov_vf(adev))
 387                         mmhub_v9_4_init_cache_regs(adev, i);
 388
 389                 mmhub_v9_4_enable_system_domain(adev, i);
 390                 if (!amdgpu_sriov_vf(adev))
 391                         mmhub_v9_4_disable_identity_aperture(adev, i);
 392                 mmhub_v9_4_setup_vmid_config(adev, i);
 393                 mmhub_v9_4_program_invalidation(adev, i);
 394         }
 395
 396         return 0;
 397 }
 398
 399 static void mmhub_v9_4_gart_disable(struct amdgpu_device *adev)
 400 {
 401         struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB_0];
 402         u32 tmp;
 403         u32 i, j;
 404
 405         for (j = 0; j < MMHUB_NUM_INSTANCES; j++) {
 406                 /* Disable all tables */
 407                 for (i = 0; i < AMDGPU_NUM_VMID; i++)
 408                         WREG32_SOC15_OFFSET(MMHUB, 0,
 409                                             mmVML2VC0_VM_CONTEXT0_CNTL,
 410                                             j * MMHUB_INSTANCE_REGISTER_OFFSET +
 411                                             i * hub->ctx_distance, 0);
 412
 413                 /* Setup TLB control */
 414                 tmp = RREG32_SOC15_OFFSET(MMHUB, 0,
 415                                    mmVMSHAREDVC0_MC_VM_MX_L1_TLB_CNTL,
 416                                    j * MMHUB_INSTANCE_REGISTER_OFFSET);
 417                 tmp = REG_SET_FIELD(tmp, VMSHAREDVC0_MC_VM_MX_L1_TLB_CNTL,
 418                                     ENABLE_L1_TLB, 0);
 419                 tmp = REG_SET_FIELD(tmp,
 420                                     VMSHAREDVC0_MC_VM_MX_L1_TLB_CNTL,
 421                                     ENABLE_ADVANCED_DRIVER_MODEL, 0);
 422                 WREG32_SOC15_OFFSET(MMHUB, 0,
 423                                     mmVMSHAREDVC0_MC_VM_MX_L1_TLB_CNTL,
 424                                     j * MMHUB_INSTANCE_REGISTER_OFFSET, tmp);
 425
 426                 /* Setup L2 cache */
 427                 tmp = RREG32_SOC15_OFFSET(MMHUB, 0, mmVML2PF0_VM_L2_CNTL,
 428                                           j * MMHUB_INSTANCE_REGISTER_OFFSET);
 429                 tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_CNTL,
 430                                     ENABLE_L2_CACHE, 0);
 431                 WREG32_SOC15_OFFSET(MMHUB, 0, mmVML2PF0_VM_L2_CNTL,
 432                                     j * MMHUB_INSTANCE_REGISTER_OFFSET, tmp);
 433                 WREG32_SOC15_OFFSET(MMHUB, 0, mmVML2PF0_VM_L2_CNTL3,
 434                                     j * MMHUB_INSTANCE_REGISTER_OFFSET, 0);
 435         }
 436 }
 437
 438 /**
 439  * mmhub_v1_0_set_fault_enable_default - update GART/VM fault handling
 440  *
 441  * @adev: amdgpu_device pointer
 442  * @value: true redirects VM faults to the default page
 443  */
 444 static void mmhub_v9_4_set_fault_enable_default(struct amdgpu_device *adev, bool value)
 445 {
 446         u32 tmp;
 447         int i;
 448
 449         for (i = 0; i < MMHUB_NUM_INSTANCES; i++) {
 450                 tmp = RREG32_SOC15_OFFSET(MMHUB, 0,
 451                                           mmVML2PF0_VM_L2_PROTECTION_FAULT_CNTL,
 452                                           i * MMHUB_INSTANCE_REGISTER_OFFSET);
 453                 tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_PROTECTION_FAULT_CNTL,
 454                                     RANGE_PROTECTION_FAULT_ENABLE_DEFAULT,
 455                                     value);
 456                 tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_PROTECTION_FAULT_CNTL,
 457                                     PDE0_PROTECTION_FAULT_ENABLE_DEFAULT,
 458                                     value);
 459                 tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_PROTECTION_FAULT_CNTL,
 460                                     PDE1_PROTECTION_FAULT_ENABLE_DEFAULT,
 461                                     value);
 462                 tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_PROTECTION_FAULT_CNTL,
 463                                     PDE2_PROTECTION_FAULT_ENABLE_DEFAULT,
 464                                     value);
 465                 tmp = REG_SET_FIELD(tmp,
 466                             VML2PF0_VM_L2_PROTECTION_FAULT_CNTL,
 467                             TRANSLATE_FURTHER_PROTECTION_FAULT_ENABLE_DEFAULT,
 468                             value);
 469                 tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_PROTECTION_FAULT_CNTL,
 470                                     NACK_PROTECTION_FAULT_ENABLE_DEFAULT,
 471                                     value);
 472                 tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_PROTECTION_FAULT_CNTL,
 473                                     DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT,
 474                                     value);
 475                 tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_PROTECTION_FAULT_CNTL,
 476                                     VALID_PROTECTION_FAULT_ENABLE_DEFAULT,
 477                                     value);
 478                 tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_PROTECTION_FAULT_CNTL,
 479                                     READ_PROTECTION_FAULT_ENABLE_DEFAULT,
 480                                     value);
 481                 tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_PROTECTION_FAULT_CNTL,
 482                                     WRITE_PROTECTION_FAULT_ENABLE_DEFAULT,
 483                                     value);
 484                 tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_PROTECTION_FAULT_CNTL,
 485                                     EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT,
 486                                     value);
 487                 if (!value) {
 488                         tmp = REG_SET_FIELD(tmp,
 489                                             VML2PF0_VM_L2_PROTECTION_FAULT_CNTL,
 490                                             CRASH_ON_NO_RETRY_FAULT, 1);
 491                         tmp = REG_SET_FIELD(tmp,
 492                                             VML2PF0_VM_L2_PROTECTION_FAULT_CNTL,
 493                                             CRASH_ON_RETRY_FAULT, 1);
 494                 }
 495
 496                 WREG32_SOC15_OFFSET(MMHUB, 0,
 497                                     mmVML2PF0_VM_L2_PROTECTION_FAULT_CNTL,
 498                                     i * MMHUB_INSTANCE_REGISTER_OFFSET, tmp);
 499         }
 500 }
 501
 502 static void mmhub_v9_4_init(struct amdgpu_device *adev)
 503 {
 504         struct amdgpu_vmhub *hub[MMHUB_NUM_INSTANCES] =
 505                 {&adev->vmhub[AMDGPU_MMHUB_0], &adev->vmhub[AMDGPU_MMHUB_1]};
 506         int i;
 507
 508         for (i = 0; i < MMHUB_NUM_INSTANCES; i++) {
 509                 hub[i]->ctx0_ptb_addr_lo32 =
 510                         SOC15_REG_OFFSET(MMHUB, 0,
 511                             mmVML2VC0_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32) +
 512                             i * MMHUB_INSTANCE_REGISTER_OFFSET;
 513                 hub[i]->ctx0_ptb_addr_hi32 =
 514                         SOC15_REG_OFFSET(MMHUB, 0,
 515                             mmVML2VC0_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32) +
 516                             i * MMHUB_INSTANCE_REGISTER_OFFSET;
 517                 hub[i]->vm_inv_eng0_sem =
 518                         SOC15_REG_OFFSET(MMHUB, 0,
 519                                          mmVML2VC0_VM_INVALIDATE_ENG0_SEM) +
 520                                          i * MMHUB_INSTANCE_REGISTER_OFFSET;
 521                 hub[i]->vm_inv_eng0_req =
 522                         SOC15_REG_OFFSET(MMHUB, 0,
 523                                          mmVML2VC0_VM_INVALIDATE_ENG0_REQ) +
 524                                          i * MMHUB_INSTANCE_REGISTER_OFFSET;
 525                 hub[i]->vm_inv_eng0_ack =
 526                         SOC15_REG_OFFSET(MMHUB, 0,
 527                                          mmVML2VC0_VM_INVALIDATE_ENG0_ACK) +
 528                                          i * MMHUB_INSTANCE_REGISTER_OFFSET;
 529                 hub[i]->vm_context0_cntl =
 530                         SOC15_REG_OFFSET(MMHUB, 0,
 531                                          mmVML2VC0_VM_CONTEXT0_CNTL) +
 532                                          i * MMHUB_INSTANCE_REGISTER_OFFSET;
 533                 hub[i]->vm_l2_pro_fault_status =
 534                         SOC15_REG_OFFSET(MMHUB, 0,
 535                                     mmVML2PF0_VM_L2_PROTECTION_FAULT_STATUS) +
 536                                     i * MMHUB_INSTANCE_REGISTER_OFFSET;
 537                 hub[i]->vm_l2_pro_fault_cntl =
 538                         SOC15_REG_OFFSET(MMHUB, 0,
 539                                     mmVML2PF0_VM_L2_PROTECTION_FAULT_CNTL) +
 540                                     i * MMHUB_INSTANCE_REGISTER_OFFSET;
 541
 542                 hub[i]->ctx_distance = mmVML2VC0_VM_CONTEXT1_CNTL -
 543                         mmVML2VC0_VM_CONTEXT0_CNTL;
 544                 hub[i]->ctx_addr_distance = mmVML2VC0_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32 -
 545                         mmVML2VC0_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32;
 546                 hub[i]->eng_distance = mmVML2VC0_VM_INVALIDATE_ENG1_REQ -
 547                         mmVML2VC0_VM_INVALIDATE_ENG0_REQ;
 548                 hub[i]->eng_addr_distance = mmVML2VC0_VM_INVALIDATE_ENG1_ADDR_RANGE_LO32 -
 549                         mmVML2VC0_VM_INVALIDATE_ENG0_ADDR_RANGE_LO32;
 550         }
 551 }
 552
 553 static void mmhub_v9_4_update_medium_grain_clock_gating(struct amdgpu_device *adev,
 554                                                         bool enable)
 555 {
 556         uint32_t def, data, def1, data1;
 557         int i, j;
 558         int dist = mmDAGB1_CNTL_MISC2 - mmDAGB0_CNTL_MISC2;
 559
 560         for (i = 0; i < MMHUB_NUM_INSTANCES; i++) {
 561                 def = data = RREG32_SOC15_OFFSET(MMHUB, 0,
 562                                         mmATCL2_0_ATC_L2_MISC_CG,
 563                                         i * MMHUB_INSTANCE_REGISTER_OFFSET);
 564
 565                 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_MGCG))
 566                         data |= ATCL2_0_ATC_L2_MISC_CG__ENABLE_MASK;
 567                 else
 568                         data &= ~ATCL2_0_ATC_L2_MISC_CG__ENABLE_MASK;
 569
 570                 if (def != data)
 571                         WREG32_SOC15_OFFSET(MMHUB, 0, mmATCL2_0_ATC_L2_MISC_CG,
 572                                 i * MMHUB_INSTANCE_REGISTER_OFFSET, data);
 573
 574                 for (j = 0; j < 5; j++) {
 575                         def1 = data1 = RREG32_SOC15_OFFSET(MMHUB, 0,
 576                                         mmDAGB0_CNTL_MISC2,
 577                                         i * MMHUB_INSTANCE_REGISTER_OFFSET +
 578                                         j * dist);
 579                         if (enable &&
 580                             (adev->cg_flags & AMD_CG_SUPPORT_MC_MGCG)) {
 581                                 data1 &=
 582                                     ~(DAGB0_CNTL_MISC2__DISABLE_WRREQ_CG_MASK |
 583                                     DAGB0_CNTL_MISC2__DISABLE_WRRET_CG_MASK |
 584                                     DAGB0_CNTL_MISC2__DISABLE_RDREQ_CG_MASK |
 585                                     DAGB0_CNTL_MISC2__DISABLE_RDRET_CG_MASK |
 586                                     DAGB0_CNTL_MISC2__DISABLE_TLBWR_CG_MASK |
 587                                     DAGB0_CNTL_MISC2__DISABLE_TLBRD_CG_MASK);
 588                         } else {
 589                                 data1 |=
 590                                     (DAGB0_CNTL_MISC2__DISABLE_WRREQ_CG_MASK |
 591                                     DAGB0_CNTL_MISC2__DISABLE_WRRET_CG_MASK |
 592                                     DAGB0_CNTL_MISC2__DISABLE_RDREQ_CG_MASK |
 593                                     DAGB0_CNTL_MISC2__DISABLE_RDRET_CG_MASK |
 594                                     DAGB0_CNTL_MISC2__DISABLE_TLBWR_CG_MASK |
 595                                     DAGB0_CNTL_MISC2__DISABLE_TLBRD_CG_MASK);
 596                         }
 597
 598                         if (def1 != data1)
 599                                 WREG32_SOC15_OFFSET(MMHUB, 0,
 600                                         mmDAGB0_CNTL_MISC2,
 601                                         i * MMHUB_INSTANCE_REGISTER_OFFSET +
 602                                         j * dist, data1);
 603
 604                         if (i == 1 && j == 3)
 605                                 break;
 606                 }
 607         }
 608 }
 609
 610 static void mmhub_v9_4_update_medium_grain_light_sleep(struct amdgpu_device *adev,
 611                                                        bool enable)
 612 {
 613         uint32_t def, data;
 614         int i;
 615
 616         for (i = 0; i < MMHUB_NUM_INSTANCES; i++) {
 617                 def = data = RREG32_SOC15_OFFSET(MMHUB, 0,
 618                                         mmATCL2_0_ATC_L2_MISC_CG,
 619                                         i * MMHUB_INSTANCE_REGISTER_OFFSET);
 620
 621                 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_LS))
 622                         data |= ATCL2_0_ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK;
 623                 else
 624                         data &= ~ATCL2_0_ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK;
 625
 626                 if (def != data)
 627                         WREG32_SOC15_OFFSET(MMHUB, 0, mmATCL2_0_ATC_L2_MISC_CG,
 628                                 i * MMHUB_INSTANCE_REGISTER_OFFSET, data);
 629         }
 630 }
 631
 632 static int mmhub_v9_4_set_clockgating(struct amdgpu_device *adev,
 633                                enum amd_clockgating_state state)
 634 {
 635         if (amdgpu_sriov_vf(adev))
 636                 return 0;
 637
 638         switch (adev->asic_type) {
 639         case CHIP_ARCTURUS:
 640                 mmhub_v9_4_update_medium_grain_clock_gating(adev,
 641                                 state == AMD_CG_STATE_GATE);
 642                 mmhub_v9_4_update_medium_grain_light_sleep(adev,
 643                                 state == AMD_CG_STATE_GATE);
 644                 break;
 645         default:
 646                 break;
 647         }
 648
 649         return 0;
 650 }
 651
 652 static void mmhub_v9_4_get_clockgating(struct amdgpu_device *adev, u32 *flags)
 653 {
 654         int data, data1;
 655
 656         if (amdgpu_sriov_vf(adev))
 657                 *flags = 0;
 658
 659         /* AMD_CG_SUPPORT_MC_MGCG */
 660         data = RREG32_SOC15(MMHUB, 0, mmATCL2_0_ATC_L2_MISC_CG);
 661
 662         data1 = RREG32_SOC15(MMHUB, 0, mmATCL2_0_ATC_L2_MISC_CG);
 663
 664         if ((data & ATCL2_0_ATC_L2_MISC_CG__ENABLE_MASK) &&
 665             !(data1 & (DAGB0_CNTL_MISC2__DISABLE_WRREQ_CG_MASK |
 666                        DAGB0_CNTL_MISC2__DISABLE_WRRET_CG_MASK |
 667                        DAGB0_CNTL_MISC2__DISABLE_RDREQ_CG_MASK |
 668                        DAGB0_CNTL_MISC2__DISABLE_RDRET_CG_MASK |
 669                        DAGB0_CNTL_MISC2__DISABLE_TLBWR_CG_MASK |
 670                        DAGB0_CNTL_MISC2__DISABLE_TLBRD_CG_MASK)))
 671                 *flags |= AMD_CG_SUPPORT_MC_MGCG;
 672
 673         /* AMD_CG_SUPPORT_MC_LS */
 674         if (data & ATCL2_0_ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK)
 675                 *flags |= AMD_CG_SUPPORT_MC_LS;
 676 }
 677
 678 static const struct soc15_ras_field_entry mmhub_v9_4_ras_fields[] = {
 679         /* MMHUB Range 0 */
 680         { "MMEA0_DRAMRD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT),
 681         SOC15_REG_FIELD(MMEA0_EDC_CNT, DRAMRD_CMDMEM_SEC_COUNT),
 682         SOC15_REG_FIELD(MMEA0_EDC_CNT, DRAMRD_CMDMEM_DED_COUNT),
 683         },
 684         { "MMEA0_DRAMWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT),
 685         SOC15_REG_FIELD(MMEA0_EDC_CNT, DRAMWR_CMDMEM_SEC_COUNT),
 686         SOC15_REG_FIELD(MMEA0_EDC_CNT, DRAMWR_CMDMEM_DED_COUNT),
 687         },
 688         { "MMEA0_DRAMWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT),
 689         SOC15_REG_FIELD(MMEA0_EDC_CNT, DRAMWR_DATAMEM_SEC_COUNT),
 690         SOC15_REG_FIELD(MMEA0_EDC_CNT, DRAMWR_DATAMEM_DED_COUNT),
 691         },
 692         { "MMEA0_RRET_TAGMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT),
 693         SOC15_REG_FIELD(MMEA0_EDC_CNT, RRET_TAGMEM_SEC_COUNT),
 694         SOC15_REG_FIELD(MMEA0_EDC_CNT, RRET_TAGMEM_DED_COUNT),
 695         },
 696         { "MMEA0_WRET_TAGMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT),
 697         SOC15_REG_FIELD(MMEA0_EDC_CNT, WRET_TAGMEM_SEC_COUNT),
 698         SOC15_REG_FIELD(MMEA0_EDC_CNT, WRET_TAGMEM_DED_COUNT),
 699         },
 700         { "MMEA0_DRAMRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT),
 701         SOC15_REG_FIELD(MMEA0_EDC_CNT, DRAMRD_PAGEMEM_SED_COUNT),
 702         0, 0,
 703         },
 704         { "MMEA0_DRAMWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT),
 705         SOC15_REG_FIELD(MMEA0_EDC_CNT, DRAMWR_PAGEMEM_SED_COUNT),
 706         0, 0,
 707         },
 708         { "MMEA0_IORD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT),
 709         SOC15_REG_FIELD(MMEA0_EDC_CNT, IORD_CMDMEM_SED_COUNT),
 710         0, 0,
 711         },
 712         { "MMEA0_IOWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT),
 713         SOC15_REG_FIELD(MMEA0_EDC_CNT, IOWR_CMDMEM_SED_COUNT),
 714         0, 0,
 715         },
 716         { "MMEA0_IOWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT),
 717         SOC15_REG_FIELD(MMEA0_EDC_CNT, IOWR_DATAMEM_SED_COUNT),
 718         0, 0,
 719         },
 720         { "MMEA0_GMIRD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT2),
 721         SOC15_REG_FIELD(MMEA0_EDC_CNT2, GMIRD_CMDMEM_SEC_COUNT),
 722         SOC15_REG_FIELD(MMEA0_EDC_CNT2, GMIRD_CMDMEM_DED_COUNT),
 723         },
 724         { "MMEA0_GMIWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT2),
 725         SOC15_REG_FIELD(MMEA0_EDC_CNT2, GMIWR_CMDMEM_SEC_COUNT),
 726         SOC15_REG_FIELD(MMEA0_EDC_CNT2, GMIWR_CMDMEM_DED_COUNT),
 727         },
 728         { "MMEA0_GMIWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT2),
 729         SOC15_REG_FIELD(MMEA0_EDC_CNT2, GMIWR_DATAMEM_SEC_COUNT),
 730         SOC15_REG_FIELD(MMEA0_EDC_CNT2, GMIWR_DATAMEM_DED_COUNT),
 731         },
 732         { "MMEA0_GMIRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT2),
 733         SOC15_REG_FIELD(MMEA0_EDC_CNT2, GMIRD_PAGEMEM_SED_COUNT),
 734         0, 0,
 735         },
 736         { "MMEA0_GMIWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT2),
 737         SOC15_REG_FIELD(MMEA0_EDC_CNT2, GMIWR_PAGEMEM_SED_COUNT),
 738         0, 0,
 739         },
 740         { "MMEA0_DRAMRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT3),
 741         0, 0,
 742         SOC15_REG_FIELD(MMEA0_EDC_CNT3, DRAMRD_PAGEMEM_DED_COUNT),
 743         },
 744         { "MMEA0_DRAMWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT3),
 745         0, 0,
 746         SOC15_REG_FIELD(MMEA0_EDC_CNT3, DRAMWR_PAGEMEM_DED_COUNT),
 747         },
 748         { "MMEA0_IORD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT3),
 749         0, 0,
 750         SOC15_REG_FIELD(MMEA0_EDC_CNT3, IORD_CMDMEM_DED_COUNT),
 751         },
 752         { "MMEA0_IOWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT3),
 753         0, 0,
 754         SOC15_REG_FIELD(MMEA0_EDC_CNT3, IOWR_CMDMEM_DED_COUNT),
 755         },
 756         { "MMEA0_IOWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT3),
 757         0, 0,
 758         SOC15_REG_FIELD(MMEA0_EDC_CNT3, IOWR_DATAMEM_DED_COUNT),
 759         },
 760         { "MMEA0_GMIRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT3),
 761         0, 0,
 762         SOC15_REG_FIELD(MMEA0_EDC_CNT3, GMIRD_PAGEMEM_DED_COUNT),
 763         },
 764         { "MMEA0_GMIWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT3),
 765         0, 0,
 766         SOC15_REG_FIELD(MMEA0_EDC_CNT3, GMIWR_PAGEMEM_DED_COUNT),
 767         },
 768         { "MMEA0_MAM_D0MEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT2),
 769         SOC15_REG_FIELD(MMEA0_EDC_CNT2, MAM_D0MEM_SED_COUNT),
 770         SOC15_REG_FIELD(MMEA0_EDC_CNT2, MAM_D0MEM_DED_COUNT),
 771         },
 772         { "MMEA0_MAM_D1MEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT2),
 773         SOC15_REG_FIELD(MMEA0_EDC_CNT2, MAM_D1MEM_SED_COUNT),
 774         SOC15_REG_FIELD(MMEA0_EDC_CNT2, MAM_D1MEM_DED_COUNT),
 775         },
 776         { "MMEA0_MAM_D2MEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT2),
 777         SOC15_REG_FIELD(MMEA0_EDC_CNT2, MAM_D2MEM_SED_COUNT),
 778         SOC15_REG_FIELD(MMEA0_EDC_CNT2, MAM_D2MEM_DED_COUNT),
 779         },
 780         { "MMEA0_MAM_D3MEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT2),
 781         SOC15_REG_FIELD(MMEA0_EDC_CNT2, MAM_D3MEM_SED_COUNT),
 782         SOC15_REG_FIELD(MMEA0_EDC_CNT2, MAM_D3MEM_DED_COUNT),
 783         },
 784
 785         /* MMHUB Range 1 */
 786         { "MMEA1_DRAMRD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT),
 787         SOC15_REG_FIELD(MMEA1_EDC_CNT, DRAMRD_CMDMEM_SEC_COUNT),
 788         SOC15_REG_FIELD(MMEA1_EDC_CNT, DRAMRD_CMDMEM_DED_COUNT),
 789         },
 790         { "MMEA1_DRAMWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT),
 791         SOC15_REG_FIELD(MMEA1_EDC_CNT, DRAMWR_CMDMEM_SEC_COUNT),
 792         SOC15_REG_FIELD(MMEA1_EDC_CNT, DRAMWR_CMDMEM_DED_COUNT),
 793         },
 794         { "MMEA1_DRAMWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT),
 795         SOC15_REG_FIELD(MMEA1_EDC_CNT, DRAMWR_DATAMEM_SEC_COUNT),
 796         SOC15_REG_FIELD(MMEA1_EDC_CNT, DRAMWR_DATAMEM_DED_COUNT),
 797         },
 798         { "MMEA1_RRET_TAGMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT),
 799         SOC15_REG_FIELD(MMEA1_EDC_CNT, RRET_TAGMEM_SEC_COUNT),
 800         SOC15_REG_FIELD(MMEA1_EDC_CNT, RRET_TAGMEM_DED_COUNT),
 801         },
 802         { "MMEA1_WRET_TAGMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT),
 803         SOC15_REG_FIELD(MMEA1_EDC_CNT, WRET_TAGMEM_SEC_COUNT),
 804         SOC15_REG_FIELD(MMEA1_EDC_CNT, WRET_TAGMEM_DED_COUNT),
 805         },
 806         { "MMEA1_DRAMRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT),
 807         SOC15_REG_FIELD(MMEA1_EDC_CNT, DRAMRD_PAGEMEM_SED_COUNT),
 808         0, 0,
 809         },
 810         { "MMEA1_DRAMWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT),
 811         SOC15_REG_FIELD(MMEA1_EDC_CNT, DRAMWR_PAGEMEM_SED_COUNT),
 812         0, 0,
 813         },
 814         { "MMEA1_IORD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT),
 815         SOC15_REG_FIELD(MMEA1_EDC_CNT, IORD_CMDMEM_SED_COUNT),
 816         0, 0,
 817         },
 818         { "MMEA1_IOWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT),
 819         SOC15_REG_FIELD(MMEA1_EDC_CNT, IOWR_CMDMEM_SED_COUNT),
 820         0, 0,
 821         },
 822         { "MMEA1_IOWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT),
 823         SOC15_REG_FIELD(MMEA1_EDC_CNT, IOWR_DATAMEM_SED_COUNT),
 824         0, 0,
 825         },
 826         { "MMEA1_GMIRD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT2),
 827         SOC15_REG_FIELD(MMEA1_EDC_CNT2, GMIRD_CMDMEM_SEC_COUNT),
 828         SOC15_REG_FIELD(MMEA1_EDC_CNT2, GMIRD_CMDMEM_DED_COUNT),
 829         },
 830         { "MMEA1_GMIWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT2),
 831         SOC15_REG_FIELD(MMEA1_EDC_CNT2, GMIWR_CMDMEM_SEC_COUNT),
 832         SOC15_REG_FIELD(MMEA1_EDC_CNT2, GMIWR_CMDMEM_DED_COUNT),
 833         },
 834         { "MMEA1_GMIWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT2),
 835         SOC15_REG_FIELD(MMEA1_EDC_CNT2, GMIWR_DATAMEM_SEC_COUNT),
 836         SOC15_REG_FIELD(MMEA1_EDC_CNT2, GMIWR_DATAMEM_DED_COUNT),
 837         },
 838         { "MMEA1_GMIRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT2),
 839         SOC15_REG_FIELD(MMEA1_EDC_CNT2, GMIRD_PAGEMEM_SED_COUNT),
 840         0, 0,
 841         },
 842         { "MMEA1_GMIWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT2),
 843         SOC15_REG_FIELD(MMEA1_EDC_CNT2, GMIWR_PAGEMEM_SED_COUNT),
 844         0, 0,
 845         },
 846         { "MMEA1_DRAMRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT3),
 847         0, 0,
 848         SOC15_REG_FIELD(MMEA1_EDC_CNT3, DRAMRD_PAGEMEM_DED_COUNT),
 849         },
 850         { "MMEA1_DRAMWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT3),
 851         0, 0,
 852         SOC15_REG_FIELD(MMEA1_EDC_CNT3, DRAMWR_PAGEMEM_DED_COUNT),
 853         },
 854         { "MMEA1_IORD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT3),
 855         0, 0,
 856         SOC15_REG_FIELD(MMEA1_EDC_CNT3, IORD_CMDMEM_DED_COUNT),
 857         },
 858         { "MMEA1_IOWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT3),
 859         0, 0,
 860         SOC15_REG_FIELD(MMEA1_EDC_CNT3, IOWR_CMDMEM_DED_COUNT),
 861         },
 862         { "MMEA1_IOWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT3),
 863         0, 0,
 864         SOC15_REG_FIELD(MMEA1_EDC_CNT3, IOWR_DATAMEM_DED_COUNT),
 865         },
 866         { "MMEA1_GMIRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT3),
 867         0, 0,
 868         SOC15_REG_FIELD(MMEA1_EDC_CNT3, GMIRD_PAGEMEM_DED_COUNT),
 869         },
 870         { "MMEA1_GMIWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT3),
 871         0, 0,
 872         SOC15_REG_FIELD(MMEA1_EDC_CNT3, GMIWR_PAGEMEM_DED_COUNT),
 873         },
 874         { "MMEA1_MAM_D0MEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT2),
 875         SOC15_REG_FIELD(MMEA1_EDC_CNT2, MAM_D0MEM_SED_COUNT),
 876         SOC15_REG_FIELD(MMEA1_EDC_CNT2, MAM_D0MEM_DED_COUNT),
 877         },
 878         { "MMEA1_MAM_D1MEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT2),
 879         SOC15_REG_FIELD(MMEA1_EDC_CNT2, MAM_D1MEM_SED_COUNT),
 880         SOC15_REG_FIELD(MMEA1_EDC_CNT2, MAM_D1MEM_DED_COUNT),
 881         },
 882         { "MMEA1_MAM_D2MEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT2),
 883         SOC15_REG_FIELD(MMEA1_EDC_CNT2, MAM_D2MEM_SED_COUNT),
 884         SOC15_REG_FIELD(MMEA1_EDC_CNT2, MAM_D2MEM_DED_COUNT),
 885         },
 886         { "MMEA1_MAM_D3MEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT2),
 887         SOC15_REG_FIELD(MMEA1_EDC_CNT2, MAM_D3MEM_SED_COUNT),
 888         SOC15_REG_FIELD(MMEA1_EDC_CNT2, MAM_D3MEM_DED_COUNT),
 889         },
 890
 891         /* MMHAB Range 2*/
 892         { "MMEA2_DRAMRD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA2_EDC_CNT),
 893         SOC15_REG_FIELD(MMEA2_EDC_CNT, DRAMRD_CMDMEM_SEC_COUNT),
 894         SOC15_REG_FIELD(MMEA2_EDC_CNT, DRAMRD_CMDMEM_DED_COUNT),
 895         },
 896         { "MMEA2_DRAMWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA2_EDC_CNT),
 897         SOC15_REG_FIELD(MMEA2_EDC_CNT, DRAMWR_CMDMEM_SEC_COUNT),
 898         SOC15_REG_FIELD(MMEA2_EDC_CNT, DRAMWR_CMDMEM_DED_COUNT),
 899         },
 900         { "MMEA2_DRAMWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA2_EDC_CNT),
 901         SOC15_REG_FIELD(MMEA2_EDC_CNT, DRAMWR_DATAMEM_SEC_COUNT),
 902         SOC15_REG_FIELD(MMEA2_EDC_CNT, DRAMWR_DATAMEM_DED_COUNT),
 903         },
 904         { "MMEA2_RRET_TAGMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA2_EDC_CNT),
 905         SOC15_REG_FIELD(MMEA2_EDC_CNT, RRET_TAGMEM_SEC_COUNT),
 906         SOC15_REG_FIELD(MMEA2_EDC_CNT, RRET_TAGMEM_DED_COUNT),
 907         },
 908         { "MMEA2_WRET_TAGMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA2_EDC_CNT),
 909         SOC15_REG_FIELD(MMEA2_EDC_CNT, WRET_TAGMEM_SEC_COUNT),
 910         SOC15_REG_FIELD(MMEA2_EDC_CNT, WRET_TAGMEM_DED_COUNT),
 911         },
 912         { "MMEA2_DRAMRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA2_EDC_CNT),
 913         SOC15_REG_FIELD(MMEA2_EDC_CNT, DRAMRD_PAGEMEM_SED_COUNT),
 914         0, 0,
 915         },
 916         { "MMEA2_DRAMWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA2_EDC_CNT),
 917         SOC15_REG_FIELD(MMEA2_EDC_CNT, DRAMWR_PAGEMEM_SED_COUNT),
 918         0, 0,
 919         },
 920         { "MMEA2_IORD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA2_EDC_CNT),
 921         SOC15_REG_FIELD(MMEA2_EDC_CNT, IORD_CMDMEM_SED_COUNT),
 922         0, 0,
 923         },
 924         { "MMEA2_IOWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA2_EDC_CNT),
 925         SOC15_REG_FIELD(MMEA2_EDC_CNT, IOWR_CMDMEM_SED_COUNT),
 926         0, 0,
 927         },
 928         { "MMEA2_IOWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA2_EDC_CNT),
 929         SOC15_REG_FIELD(MMEA2_EDC_CNT, IOWR_DATAMEM_SED_COUNT),
 930         0, 0,
 931         },
 932         { "MMEA2_GMIRD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA2_EDC_CNT2),
 933         SOC15_REG_FIELD(MMEA2_EDC_CNT2, GMIRD_CMDMEM_SEC_COUNT),
 934         SOC15_REG_FIELD(MMEA2_EDC_CNT2, GMIRD_CMDMEM_DED_COUNT),
 935         },
 936         { "MMEA2_GMIWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA2_EDC_CNT2),
 937         SOC15_REG_FIELD(MMEA2_EDC_CNT2, GMIWR_CMDMEM_SEC_COUNT),
 938         SOC15_REG_FIELD(MMEA2_EDC_CNT2, GMIWR_CMDMEM_DED_COUNT),
 939         },
 940         { "MMEA2_GMIWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA2_EDC_CNT2),
 941         SOC15_REG_FIELD(MMEA2_EDC_CNT2, GMIWR_DATAMEM_SEC_COUNT),
 942         SOC15_REG_FIELD(MMEA2_EDC_CNT2, GMIWR_DATAMEM_DED_COUNT),
 943         },
 944         { "MMEA2_GMIRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA2_EDC_CNT2),
 945         SOC15_REG_FIELD(MMEA2_EDC_CNT2, GMIRD_PAGEMEM_SED_COUNT),
 946         0, 0,
 947         },
 948         { "MMEA2_GMIWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA2_EDC_CNT2),
 949         SOC15_REG_FIELD(MMEA2_EDC_CNT2, GMIWR_PAGEMEM_SED_COUNT),
 950         0, 0,
 951         },
 952         { "MMEA2_DRAMRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA2_EDC_CNT3),
 953         0, 0,
 954         SOC15_REG_FIELD(MMEA2_EDC_CNT3, DRAMRD_PAGEMEM_DED_COUNT),
 955         },
 956         { "MMEA2_DRAMWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA2_EDC_CNT3),
 957         0, 0,
 958         SOC15_REG_FIELD(MMEA2_EDC_CNT3, DRAMWR_PAGEMEM_DED_COUNT),
 959         },
 960         { "MMEA2_IORD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA2_EDC_CNT3),
 961         0, 0,
 962         SOC15_REG_FIELD(MMEA2_EDC_CNT3, IORD_CMDMEM_DED_COUNT),
 963         },
 964         { "MMEA2_IOWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA2_EDC_CNT3),
 965         0, 0,
 966         SOC15_REG_FIELD(MMEA2_EDC_CNT3, IOWR_CMDMEM_DED_COUNT),
 967         },
 968         { "MMEA2_IOWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA2_EDC_CNT3),
 969         0, 0,
 970         SOC15_REG_FIELD(MMEA2_EDC_CNT3, IOWR_DATAMEM_DED_COUNT),
 971         },
 972         { "MMEA2_GMIRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA2_EDC_CNT3),
 973         0, 0,
 974         SOC15_REG_FIELD(MMEA2_EDC_CNT3, GMIRD_PAGEMEM_DED_COUNT),
 975         },
 976         { "MMEA2_GMIWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA2_EDC_CNT3),
 977         0, 0,
 978         SOC15_REG_FIELD(MMEA2_EDC_CNT3, GMIWR_PAGEMEM_DED_COUNT),
 979         },
 980         { "MMEA2_MAM_D0MEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA2_EDC_CNT2),
 981         SOC15_REG_FIELD(MMEA2_EDC_CNT2, MAM_D0MEM_SED_COUNT),
 982         SOC15_REG_FIELD(MMEA2_EDC_CNT2, MAM_D0MEM_DED_COUNT),
 983         },
 984         { "MMEA2_MAM_D1MEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA2_EDC_CNT2),
 985         SOC15_REG_FIELD(MMEA2_EDC_CNT2, MAM_D1MEM_SED_COUNT),
 986         SOC15_REG_FIELD(MMEA2_EDC_CNT2, MAM_D1MEM_DED_COUNT),
 987         },
 988         { "MMEA2_MAM_D2MEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA2_EDC_CNT2),
 989         SOC15_REG_FIELD(MMEA2_EDC_CNT2, MAM_D2MEM_SED_COUNT),
 990         SOC15_REG_FIELD(MMEA2_EDC_CNT2, MAM_D2MEM_DED_COUNT),
 991         },
 992         { "MMEA2_MAM_D3MEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA2_EDC_CNT2),
 993         SOC15_REG_FIELD(MMEA2_EDC_CNT2, MAM_D3MEM_SED_COUNT),
 994         SOC15_REG_FIELD(MMEA2_EDC_CNT2, MAM_D3MEM_DED_COUNT),
 995         },
 996
 997         /* MMHUB Rang 3 */
 998         { "MMEA3_DRAMRD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA3_EDC_CNT),
 999         SOC15_REG_FIELD(MMEA3_EDC_CNT, DRAMRD_CMDMEM_SEC_COUNT),
1000         SOC15_REG_FIELD(MMEA3_EDC_CNT, DRAMRD_CMDMEM_DED_COUNT),
1001         },
1002         { "MMEA3_DRAMWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA3_EDC_CNT),
1003         SOC15_REG_FIELD(MMEA3_EDC_CNT, DRAMWR_CMDMEM_SEC_COUNT),
1004         SOC15_REG_FIELD(MMEA3_EDC_CNT, DRAMWR_CMDMEM_DED_COUNT),
1005         },
1006         { "MMEA3_DRAMWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA3_EDC_CNT),
1007         SOC15_REG_FIELD(MMEA3_EDC_CNT, DRAMWR_DATAMEM_SEC_COUNT),
1008         SOC15_REG_FIELD(MMEA3_EDC_CNT, DRAMWR_DATAMEM_DED_COUNT),
1009         },
1010         { "MMEA3_RRET_TAGMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA3_EDC_CNT),
1011         SOC15_REG_FIELD(MMEA3_EDC_CNT, RRET_TAGMEM_SEC_COUNT),
1012         SOC15_REG_FIELD(MMEA3_EDC_CNT, RRET_TAGMEM_DED_COUNT),
1013         },
1014         { "MMEA3_WRET_TAGMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA3_EDC_CNT),
1015         SOC15_REG_FIELD(MMEA3_EDC_CNT, WRET_TAGMEM_SEC_COUNT),
1016         SOC15_REG_FIELD(MMEA3_EDC_CNT, WRET_TAGMEM_DED_COUNT),
1017         },
1018         { "MMEA3_DRAMRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA3_EDC_CNT),
1019         SOC15_REG_FIELD(MMEA3_EDC_CNT, DRAMRD_PAGEMEM_SED_COUNT),
1020         0, 0,
1021         },
1022         { "MMEA3_DRAMWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA3_EDC_CNT),
1023         SOC15_REG_FIELD(MMEA3_EDC_CNT, DRAMWR_PAGEMEM_SED_COUNT),
1024         0, 0,
1025         },
1026         { "MMEA3_IORD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA3_EDC_CNT),
1027         SOC15_REG_FIELD(MMEA3_EDC_CNT, IORD_CMDMEM_SED_COUNT),
1028         0, 0,
1029         },
1030         { "MMEA3_IOWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA3_EDC_CNT),
1031         SOC15_REG_FIELD(MMEA3_EDC_CNT, IOWR_CMDMEM_SED_COUNT),
1032         0, 0,
1033         },
1034         { "MMEA3_IOWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA3_EDC_CNT),
1035         SOC15_REG_FIELD(MMEA3_EDC_CNT, IOWR_DATAMEM_SED_COUNT),
1036         0, 0,
1037         },
1038         { "MMEA3_GMIRD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA3_EDC_CNT2),
1039         SOC15_REG_FIELD(MMEA3_EDC_CNT2, GMIRD_CMDMEM_SEC_COUNT),
1040         SOC15_REG_FIELD(MMEA3_EDC_CNT2, GMIRD_CMDMEM_DED_COUNT),
1041         },
1042         { "MMEA3_GMIWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA3_EDC_CNT2),
1043         SOC15_REG_FIELD(MMEA3_EDC_CNT2, GMIWR_CMDMEM_SEC_COUNT),
1044         SOC15_REG_FIELD(MMEA3_EDC_CNT2, GMIWR_CMDMEM_DED_COUNT),
1045         },
1046         { "MMEA3_GMIWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA3_EDC_CNT2),
1047         SOC15_REG_FIELD(MMEA3_EDC_CNT2, GMIWR_DATAMEM_SEC_COUNT),
1048         SOC15_REG_FIELD(MMEA3_EDC_CNT2, GMIWR_DATAMEM_DED_COUNT),
1049         },
1050         { "MMEA3_GMIRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA3_EDC_CNT2),
1051         SOC15_REG_FIELD(MMEA3_EDC_CNT2, GMIRD_PAGEMEM_SED_COUNT),
1052         0, 0,
1053         },
1054         { "MMEA3_GMIWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA3_EDC_CNT2),
1055         SOC15_REG_FIELD(MMEA3_EDC_CNT2, GMIWR_PAGEMEM_SED_COUNT),
1056         0, 0,
1057         },
1058         { "MMEA3_DRAMRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA3_EDC_CNT3),
1059         0, 0,
1060         SOC15_REG_FIELD(MMEA3_EDC_CNT3, DRAMRD_PAGEMEM_DED_COUNT),
1061         },
1062         { "MMEA3_DRAMWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA3_EDC_CNT3),
1063         0, 0,
1064         SOC15_REG_FIELD(MMEA3_EDC_CNT3, DRAMWR_PAGEMEM_DED_COUNT),
1065         },
1066         { "MMEA3_IORD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA3_EDC_CNT3),
1067         0, 0,
1068         SOC15_REG_FIELD(MMEA3_EDC_CNT3, IORD_CMDMEM_DED_COUNT),
1069         },
1070         { "MMEA3_IOWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA3_EDC_CNT3),
1071         0, 0,
1072         SOC15_REG_FIELD(MMEA3_EDC_CNT3, IOWR_CMDMEM_DED_COUNT),
1073         },
1074         { "MMEA3_IOWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA3_EDC_CNT3),
1075         0, 0,
1076         SOC15_REG_FIELD(MMEA3_EDC_CNT3, IOWR_DATAMEM_DED_COUNT),
1077         },
1078         { "MMEA3_GMIRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA3_EDC_CNT3),
1079         0, 0,
1080         SOC15_REG_FIELD(MMEA3_EDC_CNT3, GMIRD_PAGEMEM_DED_COUNT),
1081         },
1082         { "MMEA3_GMIWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA3_EDC_CNT3),
1083         0, 0,
1084         SOC15_REG_FIELD(MMEA3_EDC_CNT3, GMIWR_PAGEMEM_DED_COUNT),
1085         },
1086         { "MMEA3_MAM_D0MEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA3_EDC_CNT2),
1087         SOC15_REG_FIELD(MMEA3_EDC_CNT2, MAM_D0MEM_SED_COUNT),
1088         SOC15_REG_FIELD(MMEA3_EDC_CNT2, MAM_D0MEM_DED_COUNT),
1089         },
1090         { "MMEA3_MAM_D1MEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA3_EDC_CNT2),
1091         SOC15_REG_FIELD(MMEA3_EDC_CNT2, MAM_D1MEM_SED_COUNT),
1092         SOC15_REG_FIELD(MMEA3_EDC_CNT2, MAM_D1MEM_DED_COUNT),
1093         },
1094         { "MMEA3_MAM_D2MEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA3_EDC_CNT2),
1095         SOC15_REG_FIELD(MMEA3_EDC_CNT2, MAM_D2MEM_SED_COUNT),
1096         SOC15_REG_FIELD(MMEA3_EDC_CNT2, MAM_D2MEM_DED_COUNT),
1097         },
1098         { "MMEA3_MAM_D3MEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA3_EDC_CNT2),
1099         SOC15_REG_FIELD(MMEA3_EDC_CNT2, MAM_D3MEM_SED_COUNT),
1100         SOC15_REG_FIELD(MMEA3_EDC_CNT2, MAM_D3MEM_DED_COUNT),
1101         },
1102
1103         /* MMHUB Range 4 */
1104         { "MMEA4_DRAMRD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA4_EDC_CNT),
1105         SOC15_REG_FIELD(MMEA4_EDC_CNT, DRAMRD_CMDMEM_SEC_COUNT),
1106         SOC15_REG_FIELD(MMEA4_EDC_CNT, DRAMRD_CMDMEM_DED_COUNT),
1107         },
1108         { "MMEA4_DRAMWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA4_EDC_CNT),
1109         SOC15_REG_FIELD(MMEA4_EDC_CNT, DRAMWR_CMDMEM_SEC_COUNT),
1110         SOC15_REG_FIELD(MMEA4_EDC_CNT, DRAMWR_CMDMEM_DED_COUNT),
1111         },
1112         { "MMEA4_DRAMWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA4_EDC_CNT),
1113         SOC15_REG_FIELD(MMEA4_EDC_CNT, DRAMWR_DATAMEM_SEC_COUNT),
1114         SOC15_REG_FIELD(MMEA4_EDC_CNT, DRAMWR_DATAMEM_DED_COUNT),
1115         },
1116         { "MMEA4_RRET_TAGMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA4_EDC_CNT),
1117         SOC15_REG_FIELD(MMEA4_EDC_CNT, RRET_TAGMEM_SEC_COUNT),
1118         SOC15_REG_FIELD(MMEA4_EDC_CNT, RRET_TAGMEM_DED_COUNT),
1119         },
1120         { "MMEA4_WRET_TAGMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA4_EDC_CNT),
1121         SOC15_REG_FIELD(MMEA4_EDC_CNT, WRET_TAGMEM_SEC_COUNT),
1122         SOC15_REG_FIELD(MMEA4_EDC_CNT, WRET_TAGMEM_DED_COUNT),
1123         },
1124         { "MMEA4_DRAMRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA4_EDC_CNT),
1125         SOC15_REG_FIELD(MMEA4_EDC_CNT, DRAMRD_PAGEMEM_SED_COUNT),
1126         0, 0,
1127         },
1128         { "MMEA4_DRAMWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA4_EDC_CNT),
1129         SOC15_REG_FIELD(MMEA4_EDC_CNT, DRAMWR_PAGEMEM_SED_COUNT),
1130         0, 0,
1131         },
1132         { "MMEA4_IORD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA4_EDC_CNT),
1133         SOC15_REG_FIELD(MMEA4_EDC_CNT, IORD_CMDMEM_SED_COUNT),
1134         0, 0,
1135         },
1136         { "MMEA4_IOWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA4_EDC_CNT),
1137         SOC15_REG_FIELD(MMEA4_EDC_CNT, IOWR_CMDMEM_SED_COUNT),
1138         0, 0,
1139         },
1140         { "MMEA4_IOWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA4_EDC_CNT),
1141         SOC15_REG_FIELD(MMEA4_EDC_CNT, IOWR_DATAMEM_SED_COUNT),
1142         0, 0,
1143         },
1144         { "MMEA4_GMIRD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA4_EDC_CNT2),
1145         SOC15_REG_FIELD(MMEA4_EDC_CNT2, GMIRD_CMDMEM_SEC_COUNT),
1146         SOC15_REG_FIELD(MMEA4_EDC_CNT2, GMIRD_CMDMEM_DED_COUNT),
1147         },
1148         { "MMEA4_GMIWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA4_EDC_CNT2),
1149         SOC15_REG_FIELD(MMEA4_EDC_CNT2, GMIWR_CMDMEM_SEC_COUNT),
1150         SOC15_REG_FIELD(MMEA4_EDC_CNT2, GMIWR_CMDMEM_DED_COUNT),
1151         },
1152         { "MMEA4_GMIWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA4_EDC_CNT2),
1153         SOC15_REG_FIELD(MMEA4_EDC_CNT2, GMIWR_DATAMEM_SEC_COUNT),
1154         SOC15_REG_FIELD(MMEA4_EDC_CNT2, GMIWR_DATAMEM_DED_COUNT),
1155         },
1156         { "MMEA4_GMIRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA4_EDC_CNT2),
1157         SOC15_REG_FIELD(MMEA4_EDC_CNT2, GMIRD_PAGEMEM_SED_COUNT),
1158         0, 0,
1159         },
1160         { "MMEA4_GMIWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA4_EDC_CNT2),
1161         SOC15_REG_FIELD(MMEA4_EDC_CNT2, GMIWR_PAGEMEM_SED_COUNT),
1162         0, 0,
1163         },
1164         { "MMEA4_DRAMRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA4_EDC_CNT3),
1165         0, 0,
1166         SOC15_REG_FIELD(MMEA4_EDC_CNT3, DRAMRD_PAGEMEM_DED_COUNT),
1167         },
1168         { "MMEA4_DRAMWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA4_EDC_CNT3),
1169         0, 0,
1170         SOC15_REG_FIELD(MMEA4_EDC_CNT3, DRAMWR_PAGEMEM_DED_COUNT),
1171         },
1172         { "MMEA4_IORD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA4_EDC_CNT3),
1173         0, 0,
1174         SOC15_REG_FIELD(MMEA4_EDC_CNT3, IORD_CMDMEM_DED_COUNT),
1175         },
1176         { "MMEA4_IOWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA4_EDC_CNT3),
1177         0, 0,
1178         SOC15_REG_FIELD(MMEA4_EDC_CNT3, IOWR_CMDMEM_DED_COUNT),
1179         },
1180         { "MMEA4_IOWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA4_EDC_CNT3),
1181         0, 0,
1182         SOC15_REG_FIELD(MMEA4_EDC_CNT3, IOWR_DATAMEM_DED_COUNT),
1183         },
1184         { "MMEA4_GMIRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA4_EDC_CNT3),
1185         0, 0,
1186         SOC15_REG_FIELD(MMEA4_EDC_CNT3, GMIRD_PAGEMEM_DED_COUNT),
1187         },
1188         { "MMEA4_GMIWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA4_EDC_CNT3),
1189         0, 0,
1190         SOC15_REG_FIELD(MMEA4_EDC_CNT3, GMIWR_PAGEMEM_DED_COUNT),
1191         },
1192         { "MMEA4_MAM_D0MEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA4_EDC_CNT2),
1193         SOC15_REG_FIELD(MMEA4_EDC_CNT2, MAM_D0MEM_SED_COUNT),
1194         SOC15_REG_FIELD(MMEA4_EDC_CNT2, MAM_D0MEM_DED_COUNT),
1195         },
1196         { "MMEA4_MAM_D1MEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA4_EDC_CNT2),
1197         SOC15_REG_FIELD(MMEA4_EDC_CNT2, MAM_D1MEM_SED_COUNT),
1198         SOC15_REG_FIELD(MMEA4_EDC_CNT2, MAM_D1MEM_DED_COUNT),
1199         },
1200         { "MMEA4_MAM_D2MEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA4_EDC_CNT2),
1201         SOC15_REG_FIELD(MMEA4_EDC_CNT2, MAM_D2MEM_SED_COUNT),
1202         SOC15_REG_FIELD(MMEA4_EDC_CNT2, MAM_D2MEM_DED_COUNT),
1203         },
1204         { "MMEA4_MAM_D3MEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA4_EDC_CNT2),
1205         SOC15_REG_FIELD(MMEA4_EDC_CNT2, MAM_D3MEM_SED_COUNT),
1206         SOC15_REG_FIELD(MMEA4_EDC_CNT2, MAM_D3MEM_DED_COUNT),
1207         },
1208
1209         /* MMHUAB Range 5 */
1210         { "MMEA5_DRAMRD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA5_EDC_CNT),
1211         SOC15_REG_FIELD(MMEA5_EDC_CNT, DRAMRD_CMDMEM_SEC_COUNT),
1212         SOC15_REG_FIELD(MMEA5_EDC_CNT, DRAMRD_CMDMEM_DED_COUNT),
1213         },
1214         { "MMEA5_DRAMWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA5_EDC_CNT),
1215         SOC15_REG_FIELD(MMEA5_EDC_CNT, DRAMWR_CMDMEM_SEC_COUNT),
1216         SOC15_REG_FIELD(MMEA5_EDC_CNT, DRAMWR_CMDMEM_DED_COUNT),
1217         },
1218         { "MMEA5_DRAMWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA5_EDC_CNT),
1219         SOC15_REG_FIELD(MMEA5_EDC_CNT, DRAMWR_DATAMEM_SEC_COUNT),
1220         SOC15_REG_FIELD(MMEA5_EDC_CNT, DRAMWR_DATAMEM_DED_COUNT),
1221         },
1222         { "MMEA5_RRET_TAGMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA5_EDC_CNT),
1223         SOC15_REG_FIELD(MMEA5_EDC_CNT, RRET_TAGMEM_SEC_COUNT),
1224         SOC15_REG_FIELD(MMEA5_EDC_CNT, RRET_TAGMEM_DED_COUNT),
1225         },
1226         { "MMEA5_WRET_TAGMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA5_EDC_CNT),
1227         SOC15_REG_FIELD(MMEA5_EDC_CNT, WRET_TAGMEM_SEC_COUNT),
1228         SOC15_REG_FIELD(MMEA5_EDC_CNT, WRET_TAGMEM_DED_COUNT),
1229         },
1230         { "MMEA5_DRAMRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA5_EDC_CNT),
1231         SOC15_REG_FIELD(MMEA5_EDC_CNT, DRAMRD_PAGEMEM_SED_COUNT),
1232         0, 0,
1233         },
1234         { "MMEA5_DRAMWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA5_EDC_CNT),
1235         SOC15_REG_FIELD(MMEA5_EDC_CNT, DRAMWR_PAGEMEM_SED_COUNT),
1236         0, 0,
1237         },
1238         { "MMEA5_IORD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA5_EDC_CNT),
1239         SOC15_REG_FIELD(MMEA5_EDC_CNT, IORD_CMDMEM_SED_COUNT),
1240         0, 0,
1241         },
1242         { "MMEA5_IOWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA5_EDC_CNT),
1243         SOC15_REG_FIELD(MMEA5_EDC_CNT, IOWR_CMDMEM_SED_COUNT),
1244         0, 0,
1245         },
1246         { "MMEA5_IOWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA5_EDC_CNT),
1247         SOC15_REG_FIELD(MMEA5_EDC_CNT, IOWR_DATAMEM_SED_COUNT),
1248         0, 0,
1249         },
1250         { "MMEA5_GMIRD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA5_EDC_CNT2),
1251         SOC15_REG_FIELD(MMEA5_EDC_CNT2, GMIRD_CMDMEM_SEC_COUNT),
1252         SOC15_REG_FIELD(MMEA5_EDC_CNT2, GMIRD_CMDMEM_DED_COUNT),
1253         },
1254         { "MMEA5_GMIWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA5_EDC_CNT2),
1255         SOC15_REG_FIELD(MMEA5_EDC_CNT2, GMIWR_CMDMEM_SEC_COUNT),
1256         SOC15_REG_FIELD(MMEA5_EDC_CNT2, GMIWR_CMDMEM_DED_COUNT),
1257         },
1258         { "MMEA5_GMIWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA5_EDC_CNT2),
1259         SOC15_REG_FIELD(MMEA5_EDC_CNT2, GMIWR_DATAMEM_SEC_COUNT),
1260         SOC15_REG_FIELD(MMEA5_EDC_CNT2, GMIWR_DATAMEM_DED_COUNT),
1261         },
1262         { "MMEA5_GMIRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA5_EDC_CNT2),
1263         SOC15_REG_FIELD(MMEA5_EDC_CNT2, GMIRD_PAGEMEM_SED_COUNT),
1264         0, 0,
1265         },
1266         { "MMEA5_GMIWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA5_EDC_CNT2),
1267         SOC15_REG_FIELD(MMEA5_EDC_CNT2, GMIWR_PAGEMEM_SED_COUNT),
1268         0, 0,
1269         },
1270         { "MMEA5_DRAMRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA5_EDC_CNT3),
1271         0, 0,
1272         SOC15_REG_FIELD(MMEA5_EDC_CNT3, DRAMRD_PAGEMEM_DED_COUNT),
1273         },
1274         { "MMEA5_DRAMWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA5_EDC_CNT3),
1275         0, 0,
1276         SOC15_REG_FIELD(MMEA5_EDC_CNT3, DRAMWR_PAGEMEM_DED_COUNT),
1277         },
1278         { "MMEA5_IORD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA5_EDC_CNT3),
1279         0, 0,
1280         SOC15_REG_FIELD(MMEA5_EDC_CNT3, IORD_CMDMEM_DED_COUNT),
1281         },
1282         { "MMEA5_IOWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA5_EDC_CNT3),
1283         0, 0,
1284         SOC15_REG_FIELD(MMEA5_EDC_CNT3, IOWR_CMDMEM_DED_COUNT),
1285         },
1286         { "MMEA5_IOWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA5_EDC_CNT3),
1287         0, 0,
1288         SOC15_REG_FIELD(MMEA5_EDC_CNT3, IOWR_DATAMEM_DED_COUNT),
1289         },
1290         { "MMEA5_GMIRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA5_EDC_CNT3),
1291         0, 0,
1292         SOC15_REG_FIELD(MMEA5_EDC_CNT3, GMIRD_PAGEMEM_DED_COUNT),
1293         },
1294         { "MMEA5_GMIWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA5_EDC_CNT3),
1295         0, 0,
1296         SOC15_REG_FIELD(MMEA5_EDC_CNT3, GMIWR_PAGEMEM_DED_COUNT),
1297         },
1298         { "MMEA5_MAM_D0MEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA5_EDC_CNT2),
1299         SOC15_REG_FIELD(MMEA5_EDC_CNT2, MAM_D0MEM_SED_COUNT),
1300         SOC15_REG_FIELD(MMEA5_EDC_CNT2, MAM_D0MEM_DED_COUNT),
1301         },
1302         { "MMEA5_MAM_D1MEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA5_EDC_CNT2),
1303         SOC15_REG_FIELD(MMEA5_EDC_CNT2, MAM_D1MEM_SED_COUNT),
1304         SOC15_REG_FIELD(MMEA5_EDC_CNT2, MAM_D1MEM_DED_COUNT),
1305         },
1306         { "MMEA5_MAM_D2MEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA5_EDC_CNT2),
1307         SOC15_REG_FIELD(MMEA5_EDC_CNT2, MAM_D2MEM_SED_COUNT),
1308         SOC15_REG_FIELD(MMEA5_EDC_CNT2, MAM_D2MEM_DED_COUNT),
1309         },
1310         { "MMEA5_MAM_D3MEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA5_EDC_CNT2),
1311         SOC15_REG_FIELD(MMEA5_EDC_CNT2, MAM_D3MEM_SED_COUNT),
1312         SOC15_REG_FIELD(MMEA5_EDC_CNT2, MAM_D3MEM_DED_COUNT),
1313         },
1314
1315         /* MMHUB Range 6 */
1316         { "MMEA6_DRAMRD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA6_EDC_CNT),
1317         SOC15_REG_FIELD(MMEA6_EDC_CNT, DRAMRD_CMDMEM_SEC_COUNT),
1318         SOC15_REG_FIELD(MMEA6_EDC_CNT, DRAMRD_CMDMEM_DED_COUNT),
1319         },
1320         { "MMEA6_DRAMWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA6_EDC_CNT),
1321         SOC15_REG_FIELD(MMEA6_EDC_CNT, DRAMWR_CMDMEM_SEC_COUNT),
1322         SOC15_REG_FIELD(MMEA6_EDC_CNT, DRAMWR_CMDMEM_DED_COUNT),
1323         },
1324         { "MMEA6_DRAMWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA6_EDC_CNT),
1325         SOC15_REG_FIELD(MMEA6_EDC_CNT, DRAMWR_DATAMEM_SEC_COUNT),
1326         SOC15_REG_FIELD(MMEA6_EDC_CNT, DRAMWR_DATAMEM_DED_COUNT),
1327         },
1328         { "MMEA6_RRET_TAGMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA6_EDC_CNT),
1329         SOC15_REG_FIELD(MMEA6_EDC_CNT, RRET_TAGMEM_SEC_COUNT),
1330         SOC15_REG_FIELD(MMEA6_EDC_CNT, RRET_TAGMEM_DED_COUNT),
1331         },
1332         { "MMEA6_WRET_TAGMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA6_EDC_CNT),
1333         SOC15_REG_FIELD(MMEA6_EDC_CNT, WRET_TAGMEM_SEC_COUNT),
1334         SOC15_REG_FIELD(MMEA6_EDC_CNT, WRET_TAGMEM_DED_COUNT),
1335         },
1336         { "MMEA6_DRAMRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA6_EDC_CNT),
1337         SOC15_REG_FIELD(MMEA6_EDC_CNT, DRAMRD_PAGEMEM_SED_COUNT),
1338         0, 0,
1339         },
1340         { "MMEA6_DRAMWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA6_EDC_CNT),
1341         SOC15_REG_FIELD(MMEA6_EDC_CNT, DRAMWR_PAGEMEM_SED_COUNT),
1342         0, 0,
1343         },
1344         { "MMEA6_IORD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA6_EDC_CNT),
1345         SOC15_REG_FIELD(MMEA6_EDC_CNT, IORD_CMDMEM_SED_COUNT),
1346         0, 0,
1347         },
1348         { "MMEA6_IOWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA6_EDC_CNT),
1349         SOC15_REG_FIELD(MMEA6_EDC_CNT, IOWR_CMDMEM_SED_COUNT),
1350         0, 0,
1351         },
1352         { "MMEA6_IOWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA6_EDC_CNT),
1353         SOC15_REG_FIELD(MMEA6_EDC_CNT, IOWR_DATAMEM_SED_COUNT),
1354         0, 0,
1355         },
1356         { "MMEA6_GMIRD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA6_EDC_CNT2),
1357         SOC15_REG_FIELD(MMEA6_EDC_CNT2, GMIRD_CMDMEM_SEC_COUNT),
1358         SOC15_REG_FIELD(MMEA6_EDC_CNT2, GMIRD_CMDMEM_DED_COUNT),
1359         },
1360         { "MMEA6_GMIWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA6_EDC_CNT2),
1361         SOC15_REG_FIELD(MMEA6_EDC_CNT2, GMIWR_CMDMEM_SEC_COUNT),
1362         SOC15_REG_FIELD(MMEA6_EDC_CNT2, GMIWR_CMDMEM_DED_COUNT),
1363         },
1364         { "MMEA6_GMIWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA6_EDC_CNT2),
1365         SOC15_REG_FIELD(MMEA6_EDC_CNT2, GMIWR_DATAMEM_SEC_COUNT),
1366         SOC15_REG_FIELD(MMEA6_EDC_CNT2, GMIWR_DATAMEM_DED_COUNT),
1367         },
1368         { "MMEA6_GMIRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA6_EDC_CNT2),
1369         SOC15_REG_FIELD(MMEA6_EDC_CNT2, GMIRD_PAGEMEM_SED_COUNT),
1370         0, 0,
1371         },
1372         { "MMEA6_GMIWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA6_EDC_CNT2),
1373         SOC15_REG_FIELD(MMEA6_EDC_CNT2, GMIWR_PAGEMEM_SED_COUNT),
1374         0, 0,
1375         },
1376         { "MMEA6_DRAMRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA6_EDC_CNT3),
1377         0, 0,
1378         SOC15_REG_FIELD(MMEA6_EDC_CNT3, DRAMRD_PAGEMEM_DED_COUNT),
1379         },
1380         { "MMEA6_DRAMWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA6_EDC_CNT3),
1381         0, 0,
1382         SOC15_REG_FIELD(MMEA6_EDC_CNT3, DRAMWR_PAGEMEM_DED_COUNT),
1383         },
1384         { "MMEA6_IORD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA6_EDC_CNT3),
1385         0, 0,
1386         SOC15_REG_FIELD(MMEA6_EDC_CNT3, IORD_CMDMEM_DED_COUNT),
1387         },
1388         { "MMEA6_IOWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA6_EDC_CNT3),
1389         0, 0,
1390         SOC15_REG_FIELD(MMEA6_EDC_CNT3, IOWR_CMDMEM_DED_COUNT),
1391         },
1392         { "MMEA6_IOWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA6_EDC_CNT3),
1393         0, 0,
1394         SOC15_REG_FIELD(MMEA6_EDC_CNT3, IOWR_DATAMEM_DED_COUNT),
1395         },
1396         { "MMEA6_GMIRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA6_EDC_CNT3),
1397         0, 0,
1398         SOC15_REG_FIELD(MMEA6_EDC_CNT3, GMIRD_PAGEMEM_DED_COUNT),
1399         },
1400         { "MMEA6_GMIWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA6_EDC_CNT3),
1401         0, 0,
1402         SOC15_REG_FIELD(MMEA6_EDC_CNT3, GMIWR_PAGEMEM_DED_COUNT),
1403         },
1404         { "MMEA6_MAM_D0MEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA6_EDC_CNT2),
1405         SOC15_REG_FIELD(MMEA6_EDC_CNT2, MAM_D0MEM_SED_COUNT),
1406         SOC15_REG_FIELD(MMEA6_EDC_CNT2, MAM_D0MEM_DED_COUNT),
1407         },
1408         { "MMEA6_MAM_D1MEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA6_EDC_CNT2),
1409         SOC15_REG_FIELD(MMEA6_EDC_CNT2, MAM_D1MEM_SED_COUNT),
1410         SOC15_REG_FIELD(MMEA6_EDC_CNT2, MAM_D1MEM_DED_COUNT),
1411         },
1412         { "MMEA6_MAM_D2MEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA6_EDC_CNT2),
1413         SOC15_REG_FIELD(MMEA6_EDC_CNT2, MAM_D2MEM_SED_COUNT),
1414         SOC15_REG_FIELD(MMEA6_EDC_CNT2, MAM_D2MEM_DED_COUNT),
1415         },
1416         { "MMEA6_MAM_D3MEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA6_EDC_CNT2),
1417         SOC15_REG_FIELD(MMEA6_EDC_CNT2, MAM_D3MEM_SED_COUNT),
1418         SOC15_REG_FIELD(MMEA6_EDC_CNT2, MAM_D3MEM_DED_COUNT),
1419         },
1420
1421         /* MMHUB Range 7*/
1422         { "MMEA7_DRAMRD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA7_EDC_CNT),
1423         SOC15_REG_FIELD(MMEA7_EDC_CNT, DRAMRD_CMDMEM_SEC_COUNT),
1424         SOC15_REG_FIELD(MMEA7_EDC_CNT, DRAMRD_CMDMEM_DED_COUNT),
1425         },
1426         { "MMEA7_DRAMWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA7_EDC_CNT),
1427         SOC15_REG_FIELD(MMEA7_EDC_CNT, DRAMWR_CMDMEM_SEC_COUNT),
1428         SOC15_REG_FIELD(MMEA7_EDC_CNT, DRAMWR_CMDMEM_DED_COUNT),
1429         },
1430         { "MMEA7_DRAMWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA7_EDC_CNT),
1431         SOC15_REG_FIELD(MMEA7_EDC_CNT, DRAMWR_DATAMEM_SEC_COUNT),
1432         SOC15_REG_FIELD(MMEA7_EDC_CNT, DRAMWR_DATAMEM_DED_COUNT),
1433         },
1434         { "MMEA7_RRET_TAGMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA7_EDC_CNT),
1435         SOC15_REG_FIELD(MMEA7_EDC_CNT, RRET_TAGMEM_SEC_COUNT),
1436         SOC15_REG_FIELD(MMEA7_EDC_CNT, RRET_TAGMEM_DED_COUNT),
1437         },
1438         { "MMEA7_WRET_TAGMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA7_EDC_CNT),
1439         SOC15_REG_FIELD(MMEA7_EDC_CNT, WRET_TAGMEM_SEC_COUNT),
1440         SOC15_REG_FIELD(MMEA7_EDC_CNT, WRET_TAGMEM_DED_COUNT),
1441         },
1442         { "MMEA7_DRAMRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA7_EDC_CNT),
1443         SOC15_REG_FIELD(MMEA7_EDC_CNT, DRAMRD_PAGEMEM_SED_COUNT),
1444         0, 0,
1445         },
1446         { "MMEA7_DRAMWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA7_EDC_CNT),
1447         SOC15_REG_FIELD(MMEA7_EDC_CNT, DRAMWR_PAGEMEM_SED_COUNT),
1448         0, 0,
1449         },
1450         { "MMEA7_IORD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA7_EDC_CNT),
1451         SOC15_REG_FIELD(MMEA7_EDC_CNT, IORD_CMDMEM_SED_COUNT),
1452         0, 0,
1453         },
1454         { "MMEA7_IOWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA7_EDC_CNT),
1455         SOC15_REG_FIELD(MMEA7_EDC_CNT, IOWR_CMDMEM_SED_COUNT),
1456         0, 0,
1457         },
1458         { "MMEA7_IOWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA7_EDC_CNT),
1459         SOC15_REG_FIELD(MMEA7_EDC_CNT, IOWR_DATAMEM_SED_COUNT),
1460         0, 0,
1461         },
1462         { "MMEA7_GMIRD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA7_EDC_CNT2),
1463         SOC15_REG_FIELD(MMEA7_EDC_CNT2, GMIRD_CMDMEM_SEC_COUNT),
1464         SOC15_REG_FIELD(MMEA7_EDC_CNT2, GMIRD_CMDMEM_DED_COUNT),
1465         },
1466         { "MMEA7_GMIWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA7_EDC_CNT2),
1467         SOC15_REG_FIELD(MMEA7_EDC_CNT2, GMIWR_CMDMEM_SEC_COUNT),
1468         SOC15_REG_FIELD(MMEA7_EDC_CNT2, GMIWR_CMDMEM_DED_COUNT),
1469         },
1470         { "MMEA7_GMIWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA7_EDC_CNT2),
1471         SOC15_REG_FIELD(MMEA7_EDC_CNT2, GMIWR_DATAMEM_SEC_COUNT),
1472         SOC15_REG_FIELD(MMEA7_EDC_CNT2, GMIWR_DATAMEM_DED_COUNT),
1473         },
1474         { "MMEA7_GMIRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA7_EDC_CNT2),
1475         SOC15_REG_FIELD(MMEA7_EDC_CNT2, GMIRD_PAGEMEM_SED_COUNT),
1476         0, 0,
1477         },
1478         { "MMEA7_GMIWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA7_EDC_CNT2),
1479         SOC15_REG_FIELD(MMEA7_EDC_CNT2, GMIWR_PAGEMEM_SED_COUNT),
1480         0, 0,
1481         },
1482         { "MMEA7_DRAMRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA7_EDC_CNT3),
1483         0, 0,
1484         SOC15_REG_FIELD(MMEA7_EDC_CNT3, DRAMRD_PAGEMEM_DED_COUNT),
1485         },
1486         { "MMEA7_DRAMWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA7_EDC_CNT3),
1487         0, 0,
1488         SOC15_REG_FIELD(MMEA7_EDC_CNT3, DRAMWR_PAGEMEM_DED_COUNT),
1489         },
1490         { "MMEA7_IORD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA7_EDC_CNT3),
1491         0, 0,
1492         SOC15_REG_FIELD(MMEA7_EDC_CNT3, IORD_CMDMEM_DED_COUNT),
1493         },
1494         { "MMEA7_IOWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA7_EDC_CNT3),
1495         0, 0,
1496         SOC15_REG_FIELD(MMEA7_EDC_CNT3, IOWR_CMDMEM_DED_COUNT),
1497         },
1498         { "MMEA7_IOWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA7_EDC_CNT3),
1499         0, 0,
1500         SOC15_REG_FIELD(MMEA7_EDC_CNT3, IOWR_DATAMEM_DED_COUNT),
1501         },
1502         { "MMEA7_GMIRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA7_EDC_CNT3),
1503         0, 0,
1504         SOC15_REG_FIELD(MMEA7_EDC_CNT3, GMIRD_PAGEMEM_DED_COUNT),
1505         },
1506         { "MMEA7_GMIWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA7_EDC_CNT3),
1507         0, 0,
1508         SOC15_REG_FIELD(MMEA7_EDC_CNT3, GMIWR_PAGEMEM_DED_COUNT),
1509         },
1510         { "MMEA7_MAM_D0MEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA7_EDC_CNT2),
1511         SOC15_REG_FIELD(MMEA7_EDC_CNT2, MAM_D0MEM_SED_COUNT),
1512         SOC15_REG_FIELD(MMEA7_EDC_CNT2, MAM_D0MEM_DED_COUNT),
1513         },
1514         { "MMEA7_MAM_D1MEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA7_EDC_CNT2),
1515         SOC15_REG_FIELD(MMEA7_EDC_CNT2, MAM_D1MEM_SED_COUNT),
1516         SOC15_REG_FIELD(MMEA7_EDC_CNT2, MAM_D1MEM_DED_COUNT),
1517         },
1518         { "MMEA7_MAM_D2MEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA7_EDC_CNT2),
1519         SOC15_REG_FIELD(MMEA7_EDC_CNT2, MAM_D2MEM_SED_COUNT),
1520         SOC15_REG_FIELD(MMEA7_EDC_CNT2, MAM_D2MEM_DED_COUNT),
1521         },
1522         { "MMEA7_MAM_D3MEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA7_EDC_CNT2),
1523         SOC15_REG_FIELD(MMEA7_EDC_CNT2, MAM_D3MEM_SED_COUNT),
1524         SOC15_REG_FIELD(MMEA7_EDC_CNT2, MAM_D3MEM_DED_COUNT),
1525         }
1526 };
1527
1528 static const struct soc15_reg_entry mmhub_v9_4_edc_cnt_regs[] = {
1529         { SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT), 0, 0, 0 },
1530         { SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT2), 0, 0, 0 },
1531         { SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT3), 0, 0, 0 },
1532         { SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT), 0, 0, 0 },
1533         { SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT2), 0, 0, 0 },
1534         { SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT3), 0, 0, 0 },
1535         { SOC15_REG_ENTRY(MMHUB, 0, mmMMEA2_EDC_CNT), 0, 0, 0 },
1536         { SOC15_REG_ENTRY(MMHUB, 0, mmMMEA2_EDC_CNT2), 0, 0, 0 },
1537         { SOC15_REG_ENTRY(MMHUB, 0, mmMMEA2_EDC_CNT3), 0, 0, 0 },
1538         { SOC15_REG_ENTRY(MMHUB, 0, mmMMEA3_EDC_CNT), 0, 0, 0 },
1539         { SOC15_REG_ENTRY(MMHUB, 0, mmMMEA3_EDC_CNT2), 0, 0, 0 },
1540         { SOC15_REG_ENTRY(MMHUB, 0, mmMMEA3_EDC_CNT3), 0, 0, 0 },
1541         { SOC15_REG_ENTRY(MMHUB, 0, mmMMEA4_EDC_CNT), 0, 0, 0 },
1542         { SOC15_REG_ENTRY(MMHUB, 0, mmMMEA4_EDC_CNT2), 0, 0, 0 },
1543         { SOC15_REG_ENTRY(MMHUB, 0, mmMMEA4_EDC_CNT3), 0, 0, 0 },
1544         { SOC15_REG_ENTRY(MMHUB, 0, mmMMEA5_EDC_CNT), 0, 0, 0 },
1545         { SOC15_REG_ENTRY(MMHUB, 0, mmMMEA5_EDC_CNT2), 0, 0, 0 },
1546         { SOC15_REG_ENTRY(MMHUB, 0, mmMMEA5_EDC_CNT3), 0, 0, 0 },
1547         { SOC15_REG_ENTRY(MMHUB, 0, mmMMEA6_EDC_CNT), 0, 0, 0 },
1548         { SOC15_REG_ENTRY(MMHUB, 0, mmMMEA6_EDC_CNT2), 0, 0, 0 },
1549         { SOC15_REG_ENTRY(MMHUB, 0, mmMMEA6_EDC_CNT3), 0, 0, 0 },
1550         { SOC15_REG_ENTRY(MMHUB, 0, mmMMEA7_EDC_CNT), 0, 0, 0 },
1551         { SOC15_REG_ENTRY(MMHUB, 0, mmMMEA7_EDC_CNT2), 0, 0, 0 },
1552         { SOC15_REG_ENTRY(MMHUB, 0, mmMMEA7_EDC_CNT3), 0, 0, 0 },
1553 };
1554
1555 static int mmhub_v9_4_get_ras_error_count(struct amdgpu_device *adev,
1556                                           const struct soc15_reg_entry *reg,
1557                                           uint32_t value,
1558                                           uint32_t *sec_count,
1559                                           uint32_t *ded_count)
1560 {
1561         uint32_t i;
1562         uint32_t sec_cnt, ded_cnt;
1563
1564         for (i = 0; i < ARRAY_SIZE(mmhub_v9_4_ras_fields); i++) {
1565                 if(mmhub_v9_4_ras_fields[i].reg_offset != reg->reg_offset)
1566                         continue;
1567
1568                 sec_cnt = (value &
1569                                 mmhub_v9_4_ras_fields[i].sec_count_mask) >>
1570                                 mmhub_v9_4_ras_fields[i].sec_count_shift;
1571                 if (sec_cnt) {
1572                         dev_info(adev->dev, "MMHUB SubBlock %s, SEC %d\n",
1573                                 mmhub_v9_4_ras_fields[i].name,
1574                                 sec_cnt);
1575                         *sec_count += sec_cnt;
1576                 }
1577
1578                 ded_cnt = (value &
1579                                 mmhub_v9_4_ras_fields[i].ded_count_mask) >>
1580                                 mmhub_v9_4_ras_fields[i].ded_count_shift;
1581                 if (ded_cnt) {
1582                         dev_info(adev->dev, "MMHUB SubBlock %s, DED %d\n",
1583                                 mmhub_v9_4_ras_fields[i].name,
1584                                 ded_cnt);
1585                         *ded_count += ded_cnt;
1586                 }
1587         }
1588
1589         return 0;
1590 }
1591
1592 static void mmhub_v9_4_query_ras_error_count(struct amdgpu_device *adev,
1593                                            void *ras_error_status)
1594 {
1595         struct ras_err_data *err_data = (struct ras_err_data *)ras_error_status;
1596         uint32_t sec_count = 0, ded_count = 0;
1597         uint32_t i;
1598         uint32_t reg_value;
1599
1600         err_data->ue_count = 0;
1601         err_data->ce_count = 0;
1602
1603         for (i = 0; i < ARRAY_SIZE(mmhub_v9_4_edc_cnt_regs); i++) {
1604                 reg_value =
1605                         RREG32(SOC15_REG_ENTRY_OFFSET(mmhub_v9_4_edc_cnt_regs[i]));
1606                 if (reg_value)
1607                         mmhub_v9_4_get_ras_error_count(adev, &mmhub_v9_4_edc_cnt_regs[i],
1608                                 reg_value, &sec_count, &ded_count);
1609         }
1610
1611         err_data->ce_count += sec_count;
1612         err_data->ue_count += ded_count;
1613 }
1614
1615 static void mmhub_v9_4_reset_ras_error_count(struct amdgpu_device *adev)
1616 {
1617         uint32_t i;
1618
1619         /* read back edc counter registers to reset the counters to 0 */
1620         if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__MMHUB)) {
1621                 for (i = 0; i < ARRAY_SIZE(mmhub_v9_4_edc_cnt_regs); i++)
1622                         RREG32(SOC15_REG_ENTRY_OFFSET(mmhub_v9_4_edc_cnt_regs[i]));
1623         }
1624 }
1625
1626 static const struct soc15_reg_entry mmhub_v9_4_err_status_regs[] = {
1627         { SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_ERR_STATUS), 0, 0, 0 },
1628         { SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_ERR_STATUS), 0, 0, 0 },
1629         { SOC15_REG_ENTRY(MMHUB, 0, mmMMEA2_ERR_STATUS), 0, 0, 0 },
1630         { SOC15_REG_ENTRY(MMHUB, 0, mmMMEA3_ERR_STATUS), 0, 0, 0 },
1631         { SOC15_REG_ENTRY(MMHUB, 0, mmMMEA4_ERR_STATUS), 0, 0, 0 },
1632         { SOC15_REG_ENTRY(MMHUB, 0, mmMMEA5_ERR_STATUS), 0, 0, 0 },
1633         { SOC15_REG_ENTRY(MMHUB, 0, mmMMEA6_ERR_STATUS), 0, 0, 0 },
1634         { SOC15_REG_ENTRY(MMHUB, 0, mmMMEA7_ERR_STATUS), 0, 0, 0 },
1635 };
1636
1637 static void mmhub_v9_4_query_ras_error_status(struct amdgpu_device *adev)
1638 {
1639         int i;
1640         uint32_t reg_value;
1641
1642         if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__MMHUB))
1643                 return;
1644
1645         for (i = 0; i < ARRAY_SIZE(mmhub_v9_4_err_status_regs); i++) {
1646                 reg_value =
1647                         RREG32(SOC15_REG_ENTRY_OFFSET(mmhub_v9_4_err_status_regs[i]));
1648                 if (REG_GET_FIELD(reg_value, MMEA0_ERR_STATUS, SDP_RDRSP_STATUS) ||
1649                     REG_GET_FIELD(reg_value, MMEA0_ERR_STATUS, SDP_WRRSP_STATUS) ||
1650                     REG_GET_FIELD(reg_value, MMEA0_ERR_STATUS, SDP_RDRSP_DATAPARITY_ERROR)) {
1651                         /* SDP read/write error/parity error in FUE_IS_FATAL mode
1652                          * can cause system fatal error in arcturas. Harvest the error
1653                          * status before GPU reset */
1654                         dev_warn(adev->dev, "MMHUB EA err detected at instance: %d, status: 0x%x!\n",
1655                                         i, reg_value);
1656                 }
1657         }
1658 }
1659
1660 const struct amdgpu_mmhub_ras_funcs mmhub_v9_4_ras_funcs = {
1661         .ras_late_init = amdgpu_mmhub_ras_late_init,
1662         .ras_fini = amdgpu_mmhub_ras_fini,
1663         .query_ras_error_count = mmhub_v9_4_query_ras_error_count,
1664         .reset_ras_error_count = mmhub_v9_4_reset_ras_error_count,
1665         .query_ras_error_status = mmhub_v9_4_query_ras_error_status,
1666 };
1667
1668 const struct amdgpu_mmhub_funcs mmhub_v9_4_funcs = {
1669         .get_fb_location = mmhub_v9_4_get_fb_location,
1670         .init = mmhub_v9_4_init,
1671         .gart_enable = mmhub_v9_4_gart_enable,
1672         .set_fault_enable_default = mmhub_v9_4_set_fault_enable_default,
1673         .gart_disable = mmhub_v9_4_gart_disable,
1674         .set_clockgating = mmhub_v9_4_set_clockgating,
1675         .get_clockgating = mmhub_v9_4_get_clockgating,
1676         .setup_vm_pt_regs = mmhub_v9_4_setup_vm_pt_regs,
1677 };