drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c

   1 /*
   2  * Copyright 2019 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #include "amdgpu.h"
  25 #include "mmhub_v2_0.h"
  26
  27 #include "mmhub/mmhub_2_0_0_offset.h"
  28 #include "mmhub/mmhub_2_0_0_sh_mask.h"
  29 #include "mmhub/mmhub_2_0_0_default.h"
  30 #include "navi10_enum.h"
  31
  32 #include "soc15_common.h"
  33
  34 #define mmMM_ATC_L2_MISC_CG_Sienna_Cichlid                      0x064d
  35 #define mmMM_ATC_L2_MISC_CG_Sienna_Cichlid_BASE_IDX             0
  36 #define mmDAGB0_CNTL_MISC2_Sienna_Cichlid                       0x0070
  37 #define mmDAGB0_CNTL_MISC2_Sienna_Cichlid_BASE_IDX              0
  38
  39 static const char *mmhub_client_ids_navi1x[][2] = {
  40         [3][0] = "DCEDMC",
  41         [4][0] = "DCEVGA",
  42         [5][0] = "MP0",
  43         [6][0] = "MP1",
  44         [13][0] = "VMC",
  45         [14][0] = "HDP",
  46         [15][0] = "OSS",
  47         [16][0] = "VCNU",
  48         [17][0] = "JPEG",
  49         [18][0] = "VCN",
  50         [3][1] = "DCEDMC",
  51         [4][1] = "DCEXFC",
  52         [5][1] = "DCEVGA",
  53         [6][1] = "DCEDWB",
  54         [7][1] = "MP0",
  55         [8][1] = "MP1",
  56         [9][1] = "DBGU1",
  57         [10][1] = "DBGU0",
  58         [11][1] = "XDP",
  59         [14][1] = "HDP",
  60         [15][1] = "OSS",
  61         [16][1] = "VCNU",
  62         [17][1] = "JPEG",
  63         [18][1] = "VCN",
  64 };
  65
  66 static const char *mmhub_client_ids_sienna_cichlid[][2] = {
  67         [3][0] = "DCEDMC",
  68         [4][0] = "DCEVGA",
  69         [5][0] = "MP0",
  70         [6][0] = "MP1",
  71         [8][0] = "VMC",
  72         [9][0] = "VCNU0",
  73         [10][0] = "JPEG",
  74         [12][0] = "VCNU1",
  75         [13][0] = "VCN1",
  76         [14][0] = "HDP",
  77         [15][0] = "OSS",
  78         [32+11][0] = "VCN0",
  79         [0][1] = "DBGU0",
  80         [1][1] = "DBGU1",
  81         [2][1] = "DCEDWB",
  82         [3][1] = "DCEDMC",
  83         [4][1] = "DCEVGA",
  84         [5][1] = "MP0",
  85         [6][1] = "MP1",
  86         [7][1] = "XDP",
  87         [9][1] = "VCNU0",
  88         [10][1] = "JPEG",
  89         [11][1] = "VCN0",
  90         [12][1] = "VCNU1",
  91         [13][1] = "VCN1",
  92         [14][1] = "HDP",
  93         [15][1] = "OSS",
  94 };
  95
  96 static const char *mmhub_client_ids_beige_goby[][2] = {
  97         [3][0] = "DCEDMC",
  98         [4][0] = "DCEVGA",
  99         [5][0] = "MP0",
 100         [6][0] = "MP1",
 101         [8][0] = "VMC",
 102         [9][0] = "VCNU0",
 103         [11][0] = "VCN0",
 104         [14][0] = "HDP",
 105         [15][0] = "OSS",
 106         [0][1] = "DBGU0",
 107         [1][1] = "DBGU1",
 108         [2][1] = "DCEDWB",
 109         [3][1] = "DCEDMC",
 110         [4][1] = "DCEVGA",
 111         [5][1] = "MP0",
 112         [6][1] = "MP1",
 113         [7][1] = "XDP",
 114         [9][1] = "VCNU0",
 115         [11][1] = "VCN0",
 116         [14][1] = "HDP",
 117         [15][1] = "OSS",
 118 };
 119
 120 static uint32_t mmhub_v2_0_get_invalidate_req(unsigned int vmid,
 121                                               uint32_t flush_type)
 122 {
 123         u32 req = 0;
 124
 125         /* invalidate using legacy mode on vmid*/
 126         req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ,
 127                             PER_VMID_INVALIDATE_REQ, 1 << vmid);
 128         req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, FLUSH_TYPE, flush_type);
 129         req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PTES, 1);
 130         req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE0, 1);
 131         req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE1, 1);
 132         req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE2, 1);
 133         req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, INVALIDATE_L1_PTES, 1);
 134         req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ,
 135                             CLEAR_PROTECTION_FAULT_STATUS_ADDR, 0);
 136
 137         return req;
 138 }
 139
 140 static void
 141 mmhub_v2_0_print_l2_protection_fault_status(struct amdgpu_device *adev,
 142                                              uint32_t status)
 143 {
 144         uint32_t cid, rw;
 145         const char *mmhub_cid = NULL;
 146
 147         cid = REG_GET_FIELD(status,
 148                             MMVM_L2_PROTECTION_FAULT_STATUS, CID);
 149         rw = REG_GET_FIELD(status,
 150                            MMVM_L2_PROTECTION_FAULT_STATUS, RW);
 151
 152         dev_err(adev->dev,
 153                 "MMVM_L2_PROTECTION_FAULT_STATUS:0x%08X\n",
 154                 status);
 155         switch (adev->asic_type) {
 156         case CHIP_NAVI10:
 157         case CHIP_NAVI12:
 158         case CHIP_NAVI14:
 159                 mmhub_cid = mmhub_client_ids_navi1x[cid][rw];
 160                 break;
 161         case CHIP_SIENNA_CICHLID:
 162         case CHIP_NAVY_FLOUNDER:
 163         case CHIP_DIMGREY_CAVEFISH:
 164                 mmhub_cid = mmhub_client_ids_sienna_cichlid[cid][rw];
 165                 break;
 166         case CHIP_BEIGE_GOBY:
 167                 mmhub_cid = mmhub_client_ids_beige_goby[cid][rw];
 168                 break;
 169         default:
 170                 mmhub_cid = NULL;
 171                 break;
 172         }
 173         dev_err(adev->dev, "\t Faulty UTCL2 client ID: %s (0x%x)\n",
 174                 mmhub_cid ? mmhub_cid : "unknown", cid);
 175         dev_err(adev->dev, "\t MORE_FAULTS: 0x%lx\n",
 176                 REG_GET_FIELD(status,
 177                 MMVM_L2_PROTECTION_FAULT_STATUS, MORE_FAULTS));
 178         dev_err(adev->dev, "\t WALKER_ERROR: 0x%lx\n",
 179                 REG_GET_FIELD(status,
 180                 MMVM_L2_PROTECTION_FAULT_STATUS, WALKER_ERROR));
 181         dev_err(adev->dev, "\t PERMISSION_FAULTS: 0x%lx\n",
 182                 REG_GET_FIELD(status,
 183                 MMVM_L2_PROTECTION_FAULT_STATUS, PERMISSION_FAULTS));
 184         dev_err(adev->dev, "\t MAPPING_ERROR: 0x%lx\n",
 185                 REG_GET_FIELD(status,
 186                 MMVM_L2_PROTECTION_FAULT_STATUS, MAPPING_ERROR));
 187         dev_err(adev->dev, "\t RW: 0x%x\n", rw);
 188 }
 189
 190 static void mmhub_v2_0_setup_vm_pt_regs(struct amdgpu_device *adev, uint32_t vmid,
 191                                 uint64_t page_table_base)
 192 {
 193         struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB_0];
 194
 195         WREG32_SOC15_OFFSET(MMHUB, 0, mmMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32,
 196                             hub->ctx_addr_distance * vmid,
 197                             lower_32_bits(page_table_base));
 198
 199         WREG32_SOC15_OFFSET(MMHUB, 0, mmMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32,
 200                             hub->ctx_addr_distance * vmid,
 201                             upper_32_bits(page_table_base));
 202 }
 203
 204 static void mmhub_v2_0_init_gart_aperture_regs(struct amdgpu_device *adev)
 205 {
 206         uint64_t pt_base = amdgpu_gmc_pd_addr(adev->gart.bo);
 207
 208         mmhub_v2_0_setup_vm_pt_regs(adev, 0, pt_base);
 209
 210         WREG32_SOC15(MMHUB, 0, mmMMVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32,
 211                      (u32)(adev->gmc.gart_start >> 12));
 212         WREG32_SOC15(MMHUB, 0, mmMMVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32,
 213                      (u32)(adev->gmc.gart_start >> 44));
 214
 215         WREG32_SOC15(MMHUB, 0, mmMMVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32,
 216                      (u32)(adev->gmc.gart_end >> 12));
 217         WREG32_SOC15(MMHUB, 0, mmMMVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32,
 218                      (u32)(adev->gmc.gart_end >> 44));
 219 }
 220
 221 static void mmhub_v2_0_init_system_aperture_regs(struct amdgpu_device *adev)
 222 {
 223         uint64_t value;
 224         uint32_t tmp;
 225
 226         /* Program the AGP BAR */
 227         WREG32_SOC15(MMHUB, 0, mmMMMC_VM_AGP_BASE, 0);
 228         WREG32_SOC15(MMHUB, 0, mmMMMC_VM_AGP_BOT, adev->gmc.agp_start >> 24);
 229         WREG32_SOC15(MMHUB, 0, mmMMMC_VM_AGP_TOP, adev->gmc.agp_end >> 24);
 230
 231         if (!amdgpu_sriov_vf(adev)) {
 232                 /* Program the system aperture low logical page number. */
 233                 WREG32_SOC15(MMHUB, 0, mmMMMC_VM_SYSTEM_APERTURE_LOW_ADDR,
 234                              min(adev->gmc.fb_start, adev->gmc.agp_start) >> 18);
 235                 WREG32_SOC15(MMHUB, 0, mmMMMC_VM_SYSTEM_APERTURE_HIGH_ADDR,
 236                              max(adev->gmc.fb_end, adev->gmc.agp_end) >> 18);
 237         }
 238
 239         /* Set default page address. */
 240         value = amdgpu_gmc_vram_mc2pa(adev, adev->vram_scratch.gpu_addr);
 241         WREG32_SOC15(MMHUB, 0, mmMMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB,
 242                      (u32)(value >> 12));
 243         WREG32_SOC15(MMHUB, 0, mmMMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB,
 244                      (u32)(value >> 44));
 245
 246         /* Program "protection fault". */
 247         WREG32_SOC15(MMHUB, 0, mmMMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32,
 248                      (u32)(adev->dummy_page_addr >> 12));
 249         WREG32_SOC15(MMHUB, 0, mmMMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32,
 250                      (u32)((u64)adev->dummy_page_addr >> 44));
 251
 252         tmp = RREG32_SOC15(MMHUB, 0, mmMMVM_L2_PROTECTION_FAULT_CNTL2);
 253         tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL2,
 254                             ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY, 1);
 255         WREG32_SOC15(MMHUB, 0, mmMMVM_L2_PROTECTION_FAULT_CNTL2, tmp);
 256 }
 257
 258 static void mmhub_v2_0_init_tlb_regs(struct amdgpu_device *adev)
 259 {
 260         uint32_t tmp;
 261
 262         /* Setup TLB control */
 263         tmp = RREG32_SOC15(MMHUB, 0, mmMMMC_VM_MX_L1_TLB_CNTL);
 264
 265         tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1);
 266         tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3);
 267         tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL,
 268                             ENABLE_ADVANCED_DRIVER_MODEL, 1);
 269         tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL,
 270                             SYSTEM_APERTURE_UNMAPPED_ACCESS, 0);
 271         tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, ECO_BITS, 0);
 272         tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL,
 273                             MTYPE, MTYPE_UC); /* UC, uncached */
 274
 275         WREG32_SOC15(MMHUB, 0, mmMMMC_VM_MX_L1_TLB_CNTL, tmp);
 276 }
 277
 278 static void mmhub_v2_0_init_cache_regs(struct amdgpu_device *adev)
 279 {
 280         uint32_t tmp;
 281
 282         /* These registers are not accessible to VF-SRIOV.
 283          * The PF will program them instead.
 284          */
 285         if (amdgpu_sriov_vf(adev))
 286                 return;
 287
 288         /* Setup L2 cache */
 289         tmp = RREG32_SOC15(MMHUB, 0, mmMMVM_L2_CNTL);
 290         tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, ENABLE_L2_CACHE, 1);
 291         tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 0);
 292         tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL,
 293                             ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY, 1);
 294         /* XXX for emulation, Refer to closed source code.*/
 295         tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, L2_PDE0_CACHE_TAG_GENERATION_MODE,
 296                             0);
 297         tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, PDE_FAULT_CLASSIFICATION, 0);
 298         tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1);
 299         tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, IDENTITY_MODE_FRAGMENT_SIZE, 0);
 300         WREG32_SOC15(MMHUB, 0, mmMMVM_L2_CNTL, tmp);
 301
 302         tmp = RREG32_SOC15(MMHUB, 0, mmMMVM_L2_CNTL2);
 303         tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1);
 304         tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL2, INVALIDATE_L2_CACHE, 1);
 305         WREG32_SOC15(MMHUB, 0, mmMMVM_L2_CNTL2, tmp);
 306
 307         tmp = mmMMVM_L2_CNTL3_DEFAULT;
 308         if (adev->gmc.translate_further) {
 309                 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3, BANK_SELECT, 12);
 310                 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3,
 311                                     L2_CACHE_BIGK_FRAGMENT_SIZE, 9);
 312         } else {
 313                 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3, BANK_SELECT, 9);
 314                 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3,
 315                                     L2_CACHE_BIGK_FRAGMENT_SIZE, 6);
 316         }
 317         WREG32_SOC15(MMHUB, 0, mmMMVM_L2_CNTL3, tmp);
 318
 319         tmp = mmMMVM_L2_CNTL4_DEFAULT;
 320         tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL4, VMC_TAP_PDE_REQUEST_PHYSICAL, 0);
 321         tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL4, VMC_TAP_PTE_REQUEST_PHYSICAL, 0);
 322         WREG32_SOC15(MMHUB, 0, mmMMVM_L2_CNTL4, tmp);
 323
 324         tmp = mmMMVM_L2_CNTL5_DEFAULT;
 325         tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL5, L2_CACHE_SMALLK_FRAGMENT_SIZE, 0);
 326         WREG32_SOC15(GC, 0, mmMMVM_L2_CNTL5, tmp);
 327 }
 328
 329 static void mmhub_v2_0_enable_system_domain(struct amdgpu_device *adev)
 330 {
 331         uint32_t tmp;
 332
 333         tmp = RREG32_SOC15(MMHUB, 0, mmMMVM_CONTEXT0_CNTL);
 334         tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1);
 335         tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0);
 336         tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT0_CNTL,
 337                             RETRY_PERMISSION_OR_INVALID_PAGE_FAULT, 0);
 338         WREG32_SOC15(MMHUB, 0, mmMMVM_CONTEXT0_CNTL, tmp);
 339 }
 340
 341 static void mmhub_v2_0_disable_identity_aperture(struct amdgpu_device *adev)
 342 {
 343         /* These registers are not accessible to VF-SRIOV.
 344          * The PF will program them instead.
 345          */
 346         if (amdgpu_sriov_vf(adev))
 347                 return;
 348
 349         WREG32_SOC15(MMHUB, 0,
 350                      mmMMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32,
 351                      0xFFFFFFFF);
 352         WREG32_SOC15(MMHUB, 0,
 353                      mmMMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32,
 354                      0x0000000F);
 355
 356         WREG32_SOC15(MMHUB, 0,
 357                      mmMMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32, 0);
 358         WREG32_SOC15(MMHUB, 0,
 359                      mmMMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32, 0);
 360
 361         WREG32_SOC15(MMHUB, 0, mmMMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32,
 362                      0);
 363         WREG32_SOC15(MMHUB, 0, mmMMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32,
 364                      0);
 365 }
 366
 367 static void mmhub_v2_0_setup_vmid_config(struct amdgpu_device *adev)
 368 {
 369         struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB_0];
 370         int i;
 371         uint32_t tmp;
 372
 373         for (i = 0; i <= 14; i++) {
 374                 tmp = RREG32_SOC15_OFFSET(MMHUB, 0, mmMMVM_CONTEXT1_CNTL, i);
 375                 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1);
 376                 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH,
 377                                     adev->vm_manager.num_level);
 378                 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,
 379                                     RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 380                 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,
 381                                     DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT,
 382                                     1);
 383                 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,
 384                                     PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 385                 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,
 386                                     VALID_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 387                 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,
 388                                     READ_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 389                 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,
 390                                     WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 391                 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,
 392                                     EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 393                 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,
 394                                     PAGE_TABLE_BLOCK_SIZE,
 395                                     adev->vm_manager.block_size - 9);
 396                 /* Send no-retry XNACK on fault to suppress VM fault storm. */
 397                 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,
 398                                     RETRY_PERMISSION_OR_INVALID_PAGE_FAULT,
 399                                     !adev->gmc.noretry);
 400                 WREG32_SOC15_OFFSET(MMHUB, 0, mmMMVM_CONTEXT1_CNTL,
 401                                     i * hub->ctx_distance, tmp);
 402                 WREG32_SOC15_OFFSET(MMHUB, 0, mmMMVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32,
 403                                     i * hub->ctx_addr_distance, 0);
 404                 WREG32_SOC15_OFFSET(MMHUB, 0, mmMMVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32,
 405                                     i * hub->ctx_addr_distance, 0);
 406                 WREG32_SOC15_OFFSET(MMHUB, 0, mmMMVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32,
 407                                     i * hub->ctx_addr_distance,
 408                                     lower_32_bits(adev->vm_manager.max_pfn - 1));
 409                 WREG32_SOC15_OFFSET(MMHUB, 0, mmMMVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32,
 410                                     i * hub->ctx_addr_distance,
 411                                     upper_32_bits(adev->vm_manager.max_pfn - 1));
 412         }
 413 }
 414
 415 static void mmhub_v2_0_program_invalidation(struct amdgpu_device *adev)
 416 {
 417         struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB_0];
 418         unsigned i;
 419
 420         for (i = 0; i < 18; ++i) {
 421                 WREG32_SOC15_OFFSET(MMHUB, 0, mmMMVM_INVALIDATE_ENG0_ADDR_RANGE_LO32,
 422                                     i * hub->eng_addr_distance, 0xffffffff);
 423                 WREG32_SOC15_OFFSET(MMHUB, 0, mmMMVM_INVALIDATE_ENG0_ADDR_RANGE_HI32,
 424                                     i * hub->eng_addr_distance, 0x1f);
 425         }
 426 }
 427
 428 static int mmhub_v2_0_gart_enable(struct amdgpu_device *adev)
 429 {
 430         /* GART Enable. */
 431         mmhub_v2_0_init_gart_aperture_regs(adev);
 432         mmhub_v2_0_init_system_aperture_regs(adev);
 433         mmhub_v2_0_init_tlb_regs(adev);
 434         mmhub_v2_0_init_cache_regs(adev);
 435
 436         mmhub_v2_0_enable_system_domain(adev);
 437         mmhub_v2_0_disable_identity_aperture(adev);
 438         mmhub_v2_0_setup_vmid_config(adev);
 439         mmhub_v2_0_program_invalidation(adev);
 440
 441         return 0;
 442 }
 443
 444 static void mmhub_v2_0_gart_disable(struct amdgpu_device *adev)
 445 {
 446         struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB_0];
 447         u32 tmp;
 448         u32 i;
 449
 450         /* Disable all tables */
 451         for (i = 0; i < AMDGPU_NUM_VMID; i++)
 452                 WREG32_SOC15_OFFSET(MMHUB, 0, mmMMVM_CONTEXT0_CNTL,
 453                                     i * hub->ctx_distance, 0);
 454
 455         /* Setup TLB control */
 456         tmp = RREG32_SOC15(MMHUB, 0, mmMMMC_VM_MX_L1_TLB_CNTL);
 457         tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0);
 458         tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL,
 459                             ENABLE_ADVANCED_DRIVER_MODEL, 0);
 460         WREG32_SOC15(MMHUB, 0, mmMMMC_VM_MX_L1_TLB_CNTL, tmp);
 461
 462         /* Setup L2 cache */
 463         tmp = RREG32_SOC15(MMHUB, 0, mmMMVM_L2_CNTL);
 464         tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, ENABLE_L2_CACHE, 0);
 465         WREG32_SOC15(MMHUB, 0, mmMMVM_L2_CNTL, tmp);
 466         WREG32_SOC15(MMHUB, 0, mmMMVM_L2_CNTL3, 0);
 467 }
 468
 469 /**
 470  * mmhub_v2_0_set_fault_enable_default - update GART/VM fault handling
 471  *
 472  * @adev: amdgpu_device pointer
 473  * @value: true redirects VM faults to the default page
 474  */
 475 static void mmhub_v2_0_set_fault_enable_default(struct amdgpu_device *adev, bool value)
 476 {
 477         u32 tmp;
 478
 479         /* These registers are not accessible to VF-SRIOV.
 480          * The PF will program them instead.
 481          */
 482         if (amdgpu_sriov_vf(adev))
 483                 return;
 484
 485         tmp = RREG32_SOC15(MMHUB, 0, mmMMVM_L2_PROTECTION_FAULT_CNTL);
 486         tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
 487                             RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 488         tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
 489                             PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 490         tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
 491                             PDE1_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 492         tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
 493                             PDE2_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 494         tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
 495                             TRANSLATE_FURTHER_PROTECTION_FAULT_ENABLE_DEFAULT,
 496                             value);
 497         tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
 498                             NACK_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 499         tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
 500                             DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 501         tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
 502                             VALID_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 503         tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
 504                             READ_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 505         tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
 506                             WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 507         tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
 508                             EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 509         if (!value) {
 510                 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
 511                                 CRASH_ON_NO_RETRY_FAULT, 1);
 512                 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
 513                                 CRASH_ON_RETRY_FAULT, 1);
 514         }
 515         WREG32_SOC15(MMHUB, 0, mmMMVM_L2_PROTECTION_FAULT_CNTL, tmp);
 516 }
 517
 518 static const struct amdgpu_vmhub_funcs mmhub_v2_0_vmhub_funcs = {
 519         .print_l2_protection_fault_status = mmhub_v2_0_print_l2_protection_fault_status,
 520         .get_invalidate_req = mmhub_v2_0_get_invalidate_req,
 521 };
 522
 523 static void mmhub_v2_0_init(struct amdgpu_device *adev)
 524 {
 525         struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB_0];
 526
 527         hub->ctx0_ptb_addr_lo32 =
 528                 SOC15_REG_OFFSET(MMHUB, 0,
 529                                  mmMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32);
 530         hub->ctx0_ptb_addr_hi32 =
 531                 SOC15_REG_OFFSET(MMHUB, 0,
 532                                  mmMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32);
 533         hub->vm_inv_eng0_sem =
 534                 SOC15_REG_OFFSET(MMHUB, 0, mmMMVM_INVALIDATE_ENG0_SEM);
 535         hub->vm_inv_eng0_req =
 536                 SOC15_REG_OFFSET(MMHUB, 0, mmMMVM_INVALIDATE_ENG0_REQ);
 537         hub->vm_inv_eng0_ack =
 538                 SOC15_REG_OFFSET(MMHUB, 0, mmMMVM_INVALIDATE_ENG0_ACK);
 539         hub->vm_context0_cntl =
 540                 SOC15_REG_OFFSET(MMHUB, 0, mmMMVM_CONTEXT0_CNTL);
 541         hub->vm_l2_pro_fault_status =
 542                 SOC15_REG_OFFSET(MMHUB, 0, mmMMVM_L2_PROTECTION_FAULT_STATUS);
 543         hub->vm_l2_pro_fault_cntl =
 544                 SOC15_REG_OFFSET(MMHUB, 0, mmMMVM_L2_PROTECTION_FAULT_CNTL);
 545
 546         hub->ctx_distance = mmMMVM_CONTEXT1_CNTL - mmMMVM_CONTEXT0_CNTL;
 547         hub->ctx_addr_distance = mmMMVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32 -
 548                 mmMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32;
 549         hub->eng_distance = mmMMVM_INVALIDATE_ENG1_REQ -
 550                 mmMMVM_INVALIDATE_ENG0_REQ;
 551         hub->eng_addr_distance = mmMMVM_INVALIDATE_ENG1_ADDR_RANGE_LO32 -
 552                 mmMMVM_INVALIDATE_ENG0_ADDR_RANGE_LO32;
 553
 554         hub->vm_cntx_cntl_vm_fault = MMVM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
 555                 MMVM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
 556                 MMVM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
 557                 MMVM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
 558                 MMVM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
 559                 MMVM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
 560                 MMVM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK;
 561
 562         hub->vmhub_funcs = &mmhub_v2_0_vmhub_funcs;
 563 }
 564
 565 static void mmhub_v2_0_update_medium_grain_clock_gating(struct amdgpu_device *adev,
 566                                                         bool enable)
 567 {
 568         uint32_t def, data, def1, data1;
 569
 570         switch (adev->asic_type) {
 571         case CHIP_SIENNA_CICHLID:
 572         case CHIP_NAVY_FLOUNDER:
 573         case CHIP_DIMGREY_CAVEFISH:
 574         case CHIP_BEIGE_GOBY:
 575                 def  = data  = RREG32_SOC15(MMHUB, 0, mmMM_ATC_L2_MISC_CG_Sienna_Cichlid);
 576                 def1 = data1 = RREG32_SOC15(MMHUB, 0, mmDAGB0_CNTL_MISC2_Sienna_Cichlid);
 577                 break;
 578         default:
 579                 def  = data  = RREG32_SOC15(MMHUB, 0, mmMM_ATC_L2_MISC_CG);
 580                 def1 = data1 = RREG32_SOC15(MMHUB, 0, mmDAGB0_CNTL_MISC2);
 581                 break;
 582         }
 583
 584         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_MGCG)) {
 585                 data |= MM_ATC_L2_MISC_CG__ENABLE_MASK;
 586
 587                 data1 &= ~(DAGB0_CNTL_MISC2__DISABLE_WRREQ_CG_MASK |
 588                            DAGB0_CNTL_MISC2__DISABLE_WRRET_CG_MASK |
 589                            DAGB0_CNTL_MISC2__DISABLE_RDREQ_CG_MASK |
 590                            DAGB0_CNTL_MISC2__DISABLE_RDRET_CG_MASK |
 591                            DAGB0_CNTL_MISC2__DISABLE_TLBWR_CG_MASK |
 592                            DAGB0_CNTL_MISC2__DISABLE_TLBRD_CG_MASK);
 593
 594         } else {
 595                 data &= ~MM_ATC_L2_MISC_CG__ENABLE_MASK;
 596
 597                 data1 |= (DAGB0_CNTL_MISC2__DISABLE_WRREQ_CG_MASK |
 598                           DAGB0_CNTL_MISC2__DISABLE_WRRET_CG_MASK |
 599                           DAGB0_CNTL_MISC2__DISABLE_RDREQ_CG_MASK |
 600                           DAGB0_CNTL_MISC2__DISABLE_RDRET_CG_MASK |
 601                           DAGB0_CNTL_MISC2__DISABLE_TLBWR_CG_MASK |
 602                           DAGB0_CNTL_MISC2__DISABLE_TLBRD_CG_MASK);
 603         }
 604
 605         switch (adev->asic_type) {
 606         case CHIP_SIENNA_CICHLID:
 607         case CHIP_NAVY_FLOUNDER:
 608         case CHIP_DIMGREY_CAVEFISH:
 609         case CHIP_BEIGE_GOBY:
 610                 if (def != data)
 611                         WREG32_SOC15(MMHUB, 0, mmMM_ATC_L2_MISC_CG_Sienna_Cichlid, data);
 612                 if (def1 != data1)
 613                         WREG32_SOC15(MMHUB, 0, mmDAGB0_CNTL_MISC2_Sienna_Cichlid, data1);
 614                 break;
 615         default:
 616                 if (def != data)
 617                         WREG32_SOC15(MMHUB, 0, mmMM_ATC_L2_MISC_CG, data);
 618                 if (def1 != data1)
 619                         WREG32_SOC15(MMHUB, 0, mmDAGB0_CNTL_MISC2, data1);
 620                 break;
 621         }
 622 }
 623
 624 static void mmhub_v2_0_update_medium_grain_light_sleep(struct amdgpu_device *adev,
 625                                                        bool enable)
 626 {
 627         uint32_t def, data;
 628
 629         switch (adev->asic_type) {
 630         case CHIP_SIENNA_CICHLID:
 631         case CHIP_NAVY_FLOUNDER:
 632         case CHIP_DIMGREY_CAVEFISH:
 633         case CHIP_BEIGE_GOBY:
 634                 def  = data  = RREG32_SOC15(MMHUB, 0, mmMM_ATC_L2_MISC_CG_Sienna_Cichlid);
 635                 break;
 636         default:
 637                 def  = data  = RREG32_SOC15(MMHUB, 0, mmMM_ATC_L2_MISC_CG);
 638                 break;
 639         }
 640
 641         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_LS))
 642                 data |= MM_ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK;
 643         else
 644                 data &= ~MM_ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK;
 645
 646         if (def != data) {
 647                 switch (adev->asic_type) {
 648                 case CHIP_SIENNA_CICHLID:
 649                 case CHIP_NAVY_FLOUNDER:
 650                 case CHIP_DIMGREY_CAVEFISH:
 651                 case CHIP_BEIGE_GOBY:
 652                         WREG32_SOC15(MMHUB, 0, mmMM_ATC_L2_MISC_CG_Sienna_Cichlid, data);
 653                         break;
 654                 default:
 655                         WREG32_SOC15(MMHUB, 0, mmMM_ATC_L2_MISC_CG, data);
 656                         break;
 657                 }
 658         }
 659 }
 660
 661 static int mmhub_v2_0_set_clockgating(struct amdgpu_device *adev,
 662                                enum amd_clockgating_state state)
 663 {
 664         if (amdgpu_sriov_vf(adev))
 665                 return 0;
 666
 667         switch (adev->asic_type) {
 668         case CHIP_NAVI10:
 669         case CHIP_NAVI14:
 670         case CHIP_NAVI12:
 671         case CHIP_SIENNA_CICHLID:
 672         case CHIP_NAVY_FLOUNDER:
 673         case CHIP_DIMGREY_CAVEFISH:
 674         case CHIP_BEIGE_GOBY:
 675                 mmhub_v2_0_update_medium_grain_clock_gating(adev,
 676                                 state == AMD_CG_STATE_GATE);
 677                 mmhub_v2_0_update_medium_grain_light_sleep(adev,
 678                                 state == AMD_CG_STATE_GATE);
 679                 break;
 680         default:
 681                 break;
 682         }
 683
 684         return 0;
 685 }
 686
 687 static void mmhub_v2_0_get_clockgating(struct amdgpu_device *adev, u32 *flags)
 688 {
 689         int data, data1;
 690
 691         if (amdgpu_sriov_vf(adev))
 692                 *flags = 0;
 693
 694         switch (adev->asic_type) {
 695         case CHIP_SIENNA_CICHLID:
 696         case CHIP_NAVY_FLOUNDER:
 697         case CHIP_DIMGREY_CAVEFISH:
 698         case CHIP_BEIGE_GOBY:
 699                 data  = RREG32_SOC15(MMHUB, 0, mmMM_ATC_L2_MISC_CG_Sienna_Cichlid);
 700                 data1 = RREG32_SOC15(MMHUB, 0, mmDAGB0_CNTL_MISC2_Sienna_Cichlid);
 701                 break;
 702         default:
 703                 data  = RREG32_SOC15(MMHUB, 0, mmMM_ATC_L2_MISC_CG);
 704                 data1 = RREG32_SOC15(MMHUB, 0, mmDAGB0_CNTL_MISC2);
 705                 break;
 706         }
 707
 708         /* AMD_CG_SUPPORT_MC_MGCG */
 709         if ((data & MM_ATC_L2_MISC_CG__ENABLE_MASK) &&
 710             !(data1 & (DAGB0_CNTL_MISC2__DISABLE_WRREQ_CG_MASK |
 711                        DAGB0_CNTL_MISC2__DISABLE_WRRET_CG_MASK |
 712                        DAGB0_CNTL_MISC2__DISABLE_RDREQ_CG_MASK |
 713                        DAGB0_CNTL_MISC2__DISABLE_RDRET_CG_MASK |
 714                        DAGB0_CNTL_MISC2__DISABLE_TLBWR_CG_MASK |
 715                        DAGB0_CNTL_MISC2__DISABLE_TLBRD_CG_MASK)))
 716                 *flags |= AMD_CG_SUPPORT_MC_MGCG;
 717
 718         /* AMD_CG_SUPPORT_MC_LS */
 719         if (data & MM_ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK)
 720                 *flags |= AMD_CG_SUPPORT_MC_LS;
 721 }
 722
 723 const struct amdgpu_mmhub_funcs mmhub_v2_0_funcs = {
 724         .init = mmhub_v2_0_init,
 725         .gart_enable = mmhub_v2_0_gart_enable,
 726         .set_fault_enable_default = mmhub_v2_0_set_fault_enable_default,
 727         .gart_disable = mmhub_v2_0_gart_disable,
 728         .set_clockgating = mmhub_v2_0_set_clockgating,
 729         .get_clockgating = mmhub_v2_0_get_clockgating,
 730         .setup_vm_pt_regs = mmhub_v2_0_setup_vm_pt_regs,
 731 };