2 * Copyright 2019 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
24 #ifndef __MES_API_DEF_H__
25 #define __MES_API_DEF_H__
29 #define MES_API_VERSION 1
31 /* Driver submits one API(cmd) as a single Frame and this command size is same
32 * for all API to ease the debugging and parsing of ring buffer.
34 enum { API_FRAME_SIZE_IN_DWORDS = 64 };
36 /* To avoid command in scheduler context to be overwritten whenenver mutilple
37 * interrupts come in, this creates another queue.
39 enum { API_NUMBER_OF_COMMAND_MAX = 32 };
42 MES_API_TYPE_SCHEDULER = 1,
46 enum MES_SCH_API_OPCODE {
47 MES_SCH_API_SET_HW_RSRC = 0,
48 MES_SCH_API_SET_SCHEDULING_CONFIG = 1, /* agreegated db, quantums, etc */
49 MES_SCH_API_ADD_QUEUE = 2,
50 MES_SCH_API_REMOVE_QUEUE = 3,
51 MES_SCH_API_PERFORM_YIELD = 4,
52 MES_SCH_API_SET_GANG_PRIORITY_LEVEL = 5,
53 MES_SCH_API_SUSPEND = 6,
54 MES_SCH_API_RESUME = 7,
55 MES_SCH_API_RESET = 8,
56 MES_SCH_API_SET_LOG_BUFFER = 9,
57 MES_SCH_API_CHANGE_GANG_PRORITY = 10,
58 MES_SCH_API_QUERY_SCHEDULER_STATUS = 11,
59 MES_SCH_API_PROGRAM_GDS = 12,
60 MES_SCH_API_SET_DEBUG_VMID = 13,
61 MES_SCH_API_MISC = 14,
62 MES_SCH_API_MAX = 0xFF
65 union MES_API_HEADER {
67 uint32_t type : 4; /* 0 - Invalid; 1 - Scheduling; 2 - TBD */
69 uint32_t dwsize : 8; /* including header */
70 uint32_t reserved : 12;
76 enum MES_AMD_PRIORITY_LEVEL {
77 AMD_PRIORITY_LEVEL_LOW = 0,
78 AMD_PRIORITY_LEVEL_NORMAL = 1,
79 AMD_PRIORITY_LEVEL_MEDIUM = 2,
80 AMD_PRIORITY_LEVEL_HIGH = 3,
81 AMD_PRIORITY_LEVEL_REALTIME = 4,
82 AMD_PRIORITY_NUM_LEVELS
87 MES_QUEUE_TYPE_COMPUTE,
92 struct MES_API_STATUS {
93 uint64_t api_completion_fence_addr;
94 uint64_t api_completion_fence_value;
97 enum { MAX_COMPUTE_PIPES = 8 };
98 enum { MAX_GFX_PIPES = 2 };
99 enum { MAX_SDMA_PIPES = 2 };
101 enum { MAX_COMPUTE_HQD_PER_PIPE = 8 };
102 enum { MAX_GFX_HQD_PER_PIPE = 8 };
103 enum { MAX_SDMA_HQD_PER_PIPE = 10 };
105 enum { MAX_QUEUES_IN_A_GANG = 8 };
113 enum { VMID_INVALID = 0xffff };
115 enum { MAX_VMID_GCHUB = 16 };
116 enum { MAX_VMID_MMHUB = 16 };
118 enum MES_LOG_OPERATION {
119 MES_LOG_OPERATION_CONTEXT_STATE_CHANGE = 0
122 enum MES_LOG_CONTEXT_STATE {
123 MES_LOG_CONTEXT_STATE_IDLE = 0,
124 MES_LOG_CONTEXT_STATE_RUNNING = 1,
125 MES_LOG_CONTEXT_STATE_READY = 2,
126 MES_LOG_CONTEXT_STATE_READY_STANDBY = 3,
129 struct MES_LOG_CONTEXT_STATE_CHANGE {
131 enum MES_LOG_CONTEXT_STATE new_context_state;
134 struct MES_LOG_ENTRY_HEADER {
135 uint32_t first_free_entry_index;
136 uint32_t wraparound_count;
137 uint64_t number_of_entries;
138 uint64_t reserved[2];
141 struct MES_LOG_ENTRY_DATA {
142 uint64_t gpu_time_stamp;
143 uint32_t operation_type; /* operation_type is of MES_LOG_OPERATION type */
144 uint32_t reserved_operation_type_bits;
146 struct MES_LOG_CONTEXT_STATE_CHANGE context_state_change;
147 uint64_t reserved_operation_data[2];
151 struct MES_LOG_BUFFER {
152 struct MES_LOG_ENTRY_HEADER header;
153 struct MES_LOG_ENTRY_DATA entries[1];
156 union MESAPI_SET_HW_RESOURCES {
158 union MES_API_HEADER header;
159 uint32_t vmid_mask_mmhub;
160 uint32_t vmid_mask_gfxhub;
162 uint32_t paging_vmid;
163 uint32_t compute_hqd_mask[MAX_COMPUTE_PIPES];
164 uint32_t gfx_hqd_mask[MAX_GFX_PIPES];
165 uint32_t sdma_hqd_mask[MAX_SDMA_PIPES];
166 uint32_t agreegated_doorbells[AMD_PRIORITY_NUM_LEVELS];
167 uint64_t g_sch_ctx_gpu_mc_ptr;
168 uint64_t query_status_fence_gpu_mc_ptr;
169 struct MES_API_STATUS api_status;
172 uint32_t disable_reset : 1;
173 uint32_t reserved : 31;
175 uint32_t uint32_t_all;
179 uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];
182 union MESAPI__ADD_QUEUE {
184 union MES_API_HEADER header;
186 uint64_t page_table_base_addr;
187 uint64_t process_va_start;
188 uint64_t process_va_end;
189 uint64_t process_quantum;
190 uint64_t process_context_addr;
191 uint64_t gang_quantum;
192 uint64_t gang_context_addr;
193 uint32_t inprocess_gang_priority;
194 enum MES_AMD_PRIORITY_LEVEL gang_global_priority_level;
195 uint32_t doorbell_offset;
198 enum MES_QUEUE_TYPE queue_type;
207 uint32_t debug_vmid : 4;
208 uint32_t program_gds : 1;
209 uint32_t is_gang_suspended : 1;
210 uint32_t is_tmz_queue : 1;
211 uint32_t reserved : 24;
213 struct MES_API_STATUS api_status;
216 uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];
219 union MESAPI__REMOVE_QUEUE {
221 union MES_API_HEADER header;
222 uint32_t doorbell_offset;
223 uint64_t gang_context_addr;
226 uint32_t unmap_legacy_gfx_queue : 1;
227 uint32_t reserved : 31;
229 struct MES_API_STATUS api_status;
232 uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];
235 union MESAPI__SET_SCHEDULING_CONFIG {
237 union MES_API_HEADER header;
238 /* Grace period when preempting another priority band for this
239 * priority band. The value for idle priority band is ignored,
240 * as it never preempts other bands.
242 uint64_t grace_period_other_levels[AMD_PRIORITY_NUM_LEVELS];
243 /* Default quantum for scheduling across processes within
246 uint64_t process_quantum_for_level[AMD_PRIORITY_NUM_LEVELS];
247 /* Default grace period for processes that preempt each other
248 * within a priority band.
250 uint64_t process_grace_period_same_level[AMD_PRIORITY_NUM_LEVELS];
251 /* For normal level this field specifies the target GPU
252 * percentage in situations when it's starved by the high level.
253 * Valid values are between 0 and 50, with the default being 10.
255 uint32_t normal_yield_percent;
256 struct MES_API_STATUS api_status;
259 uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];
262 union MESAPI__PERFORM_YIELD {
264 union MES_API_HEADER header;
266 struct MES_API_STATUS api_status;
269 uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];
272 union MESAPI__CHANGE_GANG_PRIORITY_LEVEL {
274 union MES_API_HEADER header;
275 uint32_t inprocess_gang_priority;
276 enum MES_AMD_PRIORITY_LEVEL gang_global_priority_level;
277 uint64_t gang_quantum;
278 uint64_t gang_context_addr;
279 struct MES_API_STATUS api_status;
282 uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];
285 union MESAPI__SUSPEND {
287 union MES_API_HEADER header;
288 /* false - suspend all gangs; true - specific gang */
290 uint32_t suspend_all_gangs : 1;
291 uint32_t reserved : 31;
293 /* gang_context_addr is valid only if suspend_all = false */
294 uint64_t gang_context_addr;
296 uint64_t suspend_fence_addr;
297 uint32_t suspend_fence_value;
299 struct MES_API_STATUS api_status;
302 uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];
305 union MESAPI__RESUME {
307 union MES_API_HEADER header;
308 /* false - resume all gangs; true - specified gang */
310 uint32_t resume_all_gangs : 1;
311 uint32_t reserved : 31;
313 /* valid only if resume_all_gangs = false */
314 uint64_t gang_context_addr;
316 struct MES_API_STATUS api_status;
319 uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];
322 union MESAPI__RESET {
324 union MES_API_HEADER header;
327 uint32_t reset_queue : 1;
328 uint32_t reserved : 31;
331 uint64_t gang_context_addr;
332 uint32_t doorbell_offset; /* valid only if reset_queue = true */
333 struct MES_API_STATUS api_status;
336 uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];
339 union MESAPI__SET_LOGGING_BUFFER {
341 union MES_API_HEADER header;
342 /* There are separate log buffers for each queue type */
343 enum MES_QUEUE_TYPE log_type;
344 /* Log buffer GPU Address */
345 uint64_t logging_buffer_addr;
346 /* number of entries in the log buffer */
347 uint32_t number_of_entries;
348 /* Entry index at which CPU interrupt needs to be signalled */
349 uint32_t interrupt_entry;
351 struct MES_API_STATUS api_status;
354 uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];
357 union MESAPI__QUERY_MES_STATUS {
359 union MES_API_HEADER header;
360 bool mes_healthy; /* 0 - not healthy, 1 - healthy */
361 struct MES_API_STATUS api_status;
364 uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];
367 union MESAPI__PROGRAM_GDS {
369 union MES_API_HEADER header;
370 uint64_t process_context_addr;
376 struct MES_API_STATUS api_status;
379 uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];
382 union MESAPI__SET_DEBUG_VMID {
384 union MES_API_HEADER header;
385 struct MES_API_STATUS api_status;
388 uint32_t use_gds : 1;
389 uint32_t reserved : 31;
395 uint64_t process_context_addr;
396 uint64_t page_table_base_addr;
397 uint64_t process_va_start;
398 uint64_t process_va_end;
406 uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];
409 enum MESAPI_MISC_OPCODE {
410 MESAPI_MISC__MODIFY_REG,
414 enum MODIFY_REG_SUBCODE {
415 MODIFY_REG__OVERWRITE,
421 enum { MISC_DATA_MAX_SIZE_IN_DWORDS = 20 };
425 union MES_API_HEADER header;
426 enum MESAPI_MISC_OPCODE opcode;
427 struct MES_API_STATUS api_status;
431 enum MODIFY_REG_SUBCODE subcode;
435 uint32_t data[MISC_DATA_MAX_SIZE_IN_DWORDS];
439 uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];