2 * Copyright 2021 Advanced Micro Devices, Inc.
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23 #include "amdgpu_ras.h"
25 #include "amdgpu_mca.h"
27 #define smnMCMP0_STATUST0 0x03830408
28 #define smnMCMP1_STATUST0 0x03b30408
29 #define smnMCMPIO_STATUST0 0x0c930408
32 static void mca_v3_0_mp0_query_ras_error_count(struct amdgpu_device *adev,
33 void *ras_error_status)
35 amdgpu_mca_query_ras_error_count(adev,
40 static int mca_v3_0_ras_block_match(struct amdgpu_ras_block_object *block_obj,
41 enum amdgpu_ras_block block, uint32_t sub_block_index)
46 if ((block_obj->ras_comm.block == block) &&
47 (block_obj->ras_comm.sub_block_index == sub_block_index)) {
54 static const struct amdgpu_ras_block_hw_ops mca_v3_0_mp0_hw_ops = {
55 .query_ras_error_count = mca_v3_0_mp0_query_ras_error_count,
56 .query_ras_error_address = NULL,
59 struct amdgpu_mca_ras_block mca_v3_0_mp0_ras = {
61 .hw_ops = &mca_v3_0_mp0_hw_ops,
62 .ras_block_match = mca_v3_0_ras_block_match,
66 static void mca_v3_0_mp1_query_ras_error_count(struct amdgpu_device *adev,
67 void *ras_error_status)
69 amdgpu_mca_query_ras_error_count(adev,
74 static const struct amdgpu_ras_block_hw_ops mca_v3_0_mp1_hw_ops = {
75 .query_ras_error_count = mca_v3_0_mp1_query_ras_error_count,
76 .query_ras_error_address = NULL,
79 struct amdgpu_mca_ras_block mca_v3_0_mp1_ras = {
81 .hw_ops = &mca_v3_0_mp1_hw_ops,
82 .ras_block_match = mca_v3_0_ras_block_match,
86 static void mca_v3_0_mpio_query_ras_error_count(struct amdgpu_device *adev,
87 void *ras_error_status)
89 amdgpu_mca_query_ras_error_count(adev,
94 static const struct amdgpu_ras_block_hw_ops mca_v3_0_mpio_hw_ops = {
95 .query_ras_error_count = mca_v3_0_mpio_query_ras_error_count,
96 .query_ras_error_address = NULL,
99 struct amdgpu_mca_ras_block mca_v3_0_mpio_ras = {
101 .hw_ops = &mca_v3_0_mpio_hw_ops,
102 .ras_block_match = mca_v3_0_ras_block_match,