2 * Copyright 2022 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
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9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
25 #include "amdgpu_jpeg.h"
28 #include "jpeg_v4_0_3.h"
29 #include "mmsch_v4_0_3.h"
31 #include "vcn/vcn_4_0_3_offset.h"
32 #include "vcn/vcn_4_0_3_sh_mask.h"
33 #include "ivsrcid/vcn/irqsrcs_vcn_4_0.h"
35 enum jpeg_engin_status {
36 UVD_PGFSM_STATUS__UVDJ_PWR_ON = 0,
37 UVD_PGFSM_STATUS__UVDJ_PWR_OFF = 2,
40 static void jpeg_v4_0_3_set_dec_ring_funcs(struct amdgpu_device *adev);
41 static void jpeg_v4_0_3_set_irq_funcs(struct amdgpu_device *adev);
42 static int jpeg_v4_0_3_set_powergating_state(void *handle,
43 enum amd_powergating_state state);
44 static void jpeg_v4_0_3_set_ras_funcs(struct amdgpu_device *adev);
45 static void jpeg_v4_0_3_dec_ring_set_wptr(struct amdgpu_ring *ring);
47 static int amdgpu_ih_srcid_jpeg[] = {
48 VCN_4_0__SRCID__JPEG_DECODE,
49 VCN_4_0__SRCID__JPEG1_DECODE,
50 VCN_4_0__SRCID__JPEG2_DECODE,
51 VCN_4_0__SRCID__JPEG3_DECODE,
52 VCN_4_0__SRCID__JPEG4_DECODE,
53 VCN_4_0__SRCID__JPEG5_DECODE,
54 VCN_4_0__SRCID__JPEG6_DECODE,
55 VCN_4_0__SRCID__JPEG7_DECODE
59 * jpeg_v4_0_3_early_init - set function pointers
61 * @handle: amdgpu_device pointer
63 * Set ring and irq function pointers
65 static int jpeg_v4_0_3_early_init(void *handle)
67 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
69 adev->jpeg.num_jpeg_rings = AMDGPU_MAX_JPEG_RINGS;
71 jpeg_v4_0_3_set_dec_ring_funcs(adev);
72 jpeg_v4_0_3_set_irq_funcs(adev);
73 jpeg_v4_0_3_set_ras_funcs(adev);
79 * jpeg_v4_0_3_sw_init - sw init for JPEG block
81 * @handle: amdgpu_device pointer
83 * Load firmware and sw initialization
85 static int jpeg_v4_0_3_sw_init(void *handle)
87 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
88 struct amdgpu_ring *ring;
89 int i, j, r, jpeg_inst;
91 for (j = 0; j < adev->jpeg.num_jpeg_rings; ++j) {
93 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VCN,
94 amdgpu_ih_srcid_jpeg[j], &adev->jpeg.inst->irq);
99 r = amdgpu_jpeg_sw_init(adev);
103 r = amdgpu_jpeg_resume(adev);
107 for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) {
108 jpeg_inst = GET_INST(JPEG, i);
110 for (j = 0; j < adev->jpeg.num_jpeg_rings; ++j) {
111 ring = &adev->jpeg.inst[i].ring_dec[j];
112 ring->use_doorbell = true;
113 ring->vm_hub = AMDGPU_MMHUB0(adev->jpeg.inst[i].aid_id);
114 if (!amdgpu_sriov_vf(adev)) {
115 ring->doorbell_index =
116 (adev->doorbell_index.vcn.vcn_ring0_1 << 1) +
117 1 + j + 9 * jpeg_inst;
120 ring->doorbell_index =
121 (adev->doorbell_index.vcn.vcn_ring0_1 << 1) +
122 4 + j + 32 * jpeg_inst;
124 ring->doorbell_index =
125 (adev->doorbell_index.vcn.vcn_ring0_1 << 1) +
126 8 + j + 32 * jpeg_inst;
128 sprintf(ring->name, "jpeg_dec_%d.%d", adev->jpeg.inst[i].aid_id, j);
129 r = amdgpu_ring_init(adev, ring, 512, &adev->jpeg.inst->irq, 0,
130 AMDGPU_RING_PRIO_DEFAULT, NULL);
134 adev->jpeg.internal.jpeg_pitch[j] =
135 regUVD_JRBC0_UVD_JRBC_SCRATCH0_INTERNAL_OFFSET;
136 adev->jpeg.inst[i].external.jpeg_pitch[j] =
139 regUVD_JRBC0_UVD_JRBC_SCRATCH0,
140 (j ? (0x40 * j - 0xc80) : 0));
144 if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__JPEG)) {
145 r = amdgpu_jpeg_ras_sw_init(adev);
147 dev_err(adev->dev, "Failed to initialize jpeg ras block!\n");
156 * jpeg_v4_0_3_sw_fini - sw fini for JPEG block
158 * @handle: amdgpu_device pointer
160 * JPEG suspend and free up sw allocation
162 static int jpeg_v4_0_3_sw_fini(void *handle)
164 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
167 r = amdgpu_jpeg_suspend(adev);
171 r = amdgpu_jpeg_sw_fini(adev);
176 static int jpeg_v4_0_3_start_sriov(struct amdgpu_device *adev)
178 struct amdgpu_ring *ring;
180 uint32_t param, resp, expected;
181 uint32_t tmp, timeout;
183 struct amdgpu_mm_table *table = &adev->virt.mm_table;
186 uint32_t size, size_dw, item_offset;
187 uint32_t init_status;
190 struct mmsch_v4_0_cmd_direct_write
192 struct mmsch_v4_0_cmd_end end = { {0} };
193 struct mmsch_v4_0_3_init_header header;
195 direct_wt.cmd_header.command_type =
196 MMSCH_COMMAND__DIRECT_REG_WRITE;
197 end.cmd_header.command_type =
200 for (i = 0; i < adev->jpeg.num_jpeg_inst; i++) {
201 jpeg_inst = GET_INST(JPEG, i);
203 memset(&header, 0, sizeof(struct mmsch_v4_0_3_init_header));
204 header.version = MMSCH_VERSION;
205 header.total_size = sizeof(struct mmsch_v4_0_3_init_header) >> 2;
207 table_loc = (uint32_t *)table->cpu_addr;
208 table_loc += header.total_size;
210 item_offset = header.total_size;
212 for (j = 0; j < adev->jpeg.num_jpeg_rings; j++) {
213 ring = &adev->jpeg.inst[i].ring_dec[j];
216 tmp = SOC15_REG_OFFSET(JPEG, 0, regUVD_JMI0_UVD_LMI_JRBC_RB_64BIT_BAR_LOW);
217 MMSCH_V4_0_INSERT_DIRECT_WT(tmp, lower_32_bits(ring->gpu_addr));
218 tmp = SOC15_REG_OFFSET(JPEG, 0, regUVD_JMI0_UVD_LMI_JRBC_RB_64BIT_BAR_HIGH);
219 MMSCH_V4_0_INSERT_DIRECT_WT(tmp, upper_32_bits(ring->gpu_addr));
220 tmp = SOC15_REG_OFFSET(JPEG, 0, regUVD_JRBC0_UVD_JRBC_RB_SIZE);
221 MMSCH_V4_0_INSERT_DIRECT_WT(tmp, ring->ring_size / 4);
224 header.mjpegdec0[j].table_offset = item_offset;
225 header.mjpegdec0[j].init_status = 0;
226 header.mjpegdec0[j].table_size = table_size;
228 header.mjpegdec1[j - 4].table_offset = item_offset;
229 header.mjpegdec1[j - 4].init_status = 0;
230 header.mjpegdec1[j - 4].table_size = table_size;
232 header.total_size += table_size;
233 item_offset += table_size;
236 MMSCH_V4_0_INSERT_END();
238 /* send init table to MMSCH */
239 size = sizeof(struct mmsch_v4_0_3_init_header);
240 table_loc = (uint32_t *)table->cpu_addr;
241 memcpy((void *)table_loc, &header, size);
243 ctx_addr = table->gpu_addr;
244 WREG32_SOC15(VCN, jpeg_inst, regMMSCH_VF_CTX_ADDR_LO, lower_32_bits(ctx_addr));
245 WREG32_SOC15(VCN, jpeg_inst, regMMSCH_VF_CTX_ADDR_HI, upper_32_bits(ctx_addr));
247 tmp = RREG32_SOC15(VCN, jpeg_inst, regMMSCH_VF_VMID);
248 tmp &= ~MMSCH_VF_VMID__VF_CTX_VMID_MASK;
249 tmp |= (0 << MMSCH_VF_VMID__VF_CTX_VMID__SHIFT);
250 WREG32_SOC15(VCN, jpeg_inst, regMMSCH_VF_VMID, tmp);
252 size = header.total_size;
253 WREG32_SOC15(VCN, jpeg_inst, regMMSCH_VF_CTX_SIZE, size);
255 WREG32_SOC15(VCN, jpeg_inst, regMMSCH_VF_MAILBOX_RESP, 0);
258 WREG32_SOC15(VCN, jpeg_inst, regMMSCH_VF_MAILBOX_HOST, param);
262 expected = MMSCH_VF_MAILBOX_RESP__OK;
264 ((struct mmsch_v4_0_3_init_header *)(table_loc))->mjpegdec0[i].init_status;
265 while (resp != expected) {
266 resp = RREG32_SOC15(VCN, jpeg_inst, regMMSCH_VF_MAILBOX_RESP);
272 if (tmp >= timeout) {
273 DRM_ERROR("failed to init MMSCH. TIME-OUT after %d usec"\
274 " waiting for regMMSCH_VF_MAILBOX_RESP "\
275 "(expected=0x%08x, readback=0x%08x)\n",
276 tmp, expected, resp);
280 if (resp != expected && resp != MMSCH_VF_MAILBOX_RESP__INCOMPLETE &&
281 init_status != MMSCH_VF_ENGINE_STATUS__PASS)
282 DRM_ERROR("MMSCH init status is incorrect! readback=0x%08x, header init status for jpeg: %x\n",
290 * jpeg_v4_0_3_hw_init - start and test JPEG block
292 * @handle: amdgpu_device pointer
295 static int jpeg_v4_0_3_hw_init(void *handle)
297 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
298 struct amdgpu_ring *ring;
299 int i, j, r, jpeg_inst;
301 if (amdgpu_sriov_vf(adev)) {
302 r = jpeg_v4_0_3_start_sriov(adev);
306 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
307 for (j = 0; j < adev->jpeg.num_jpeg_rings; ++j) {
308 ring = &adev->jpeg.inst[i].ring_dec[j];
311 jpeg_v4_0_3_dec_ring_set_wptr(ring);
312 ring->sched.ready = true;
316 for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) {
317 jpeg_inst = GET_INST(JPEG, i);
319 ring = adev->jpeg.inst[i].ring_dec;
321 if (ring->use_doorbell)
322 adev->nbio.funcs->vcn_doorbell_range(
323 adev, ring->use_doorbell,
324 (adev->doorbell_index.vcn.vcn_ring0_1 << 1) +
326 adev->jpeg.inst[i].aid_id);
328 for (j = 0; j < adev->jpeg.num_jpeg_rings; ++j) {
329 ring = &adev->jpeg.inst[i].ring_dec[j];
330 if (ring->use_doorbell)
332 VCN, GET_INST(VCN, i),
334 (ring->pipe ? (ring->pipe - 0x15) : 0),
336 << VCN_JPEG_DB_CTRL__OFFSET__SHIFT |
337 VCN_JPEG_DB_CTRL__EN_MASK);
338 r = amdgpu_ring_test_helper(ring);
344 DRM_DEV_INFO(adev->dev, "JPEG decode initialized successfully.\n");
350 * jpeg_v4_0_3_hw_fini - stop the hardware block
352 * @handle: amdgpu_device pointer
354 * Stop the JPEG block, mark ring as not ready any more
356 static int jpeg_v4_0_3_hw_fini(void *handle)
358 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
361 cancel_delayed_work_sync(&adev->jpeg.idle_work);
363 if (!amdgpu_sriov_vf(adev)) {
364 if (adev->jpeg.cur_state != AMD_PG_STATE_GATE)
365 ret = jpeg_v4_0_3_set_powergating_state(adev, AMD_PG_STATE_GATE);
372 * jpeg_v4_0_3_suspend - suspend JPEG block
374 * @handle: amdgpu_device pointer
376 * HW fini and suspend JPEG block
378 static int jpeg_v4_0_3_suspend(void *handle)
380 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
383 r = jpeg_v4_0_3_hw_fini(adev);
387 r = amdgpu_jpeg_suspend(adev);
393 * jpeg_v4_0_3_resume - resume JPEG block
395 * @handle: amdgpu_device pointer
397 * Resume firmware and hw init JPEG block
399 static int jpeg_v4_0_3_resume(void *handle)
401 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
404 r = amdgpu_jpeg_resume(adev);
408 r = jpeg_v4_0_3_hw_init(adev);
413 static void jpeg_v4_0_3_disable_clock_gating(struct amdgpu_device *adev, int inst_idx)
418 jpeg_inst = GET_INST(JPEG, inst_idx);
419 data = RREG32_SOC15(JPEG, jpeg_inst, regJPEG_CGC_CTRL);
420 if (adev->cg_flags & AMD_CG_SUPPORT_JPEG_MGCG) {
421 data |= 1 << JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
422 data &= (~(JPEG_CGC_CTRL__JPEG0_DEC_MODE_MASK << 1));
424 data &= ~JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
427 data |= 1 << JPEG_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT;
428 data |= 4 << JPEG_CGC_CTRL__CLK_OFF_DELAY__SHIFT;
429 WREG32_SOC15(JPEG, jpeg_inst, regJPEG_CGC_CTRL, data);
431 data = RREG32_SOC15(JPEG, jpeg_inst, regJPEG_CGC_GATE);
432 data &= ~(JPEG_CGC_GATE__JMCIF_MASK | JPEG_CGC_GATE__JRBBM_MASK);
433 for (i = 0; i < adev->jpeg.num_jpeg_rings; ++i)
434 data &= ~(JPEG_CGC_GATE__JPEG0_DEC_MASK << i);
435 WREG32_SOC15(JPEG, jpeg_inst, regJPEG_CGC_GATE, data);
438 static void jpeg_v4_0_3_enable_clock_gating(struct amdgpu_device *adev, int inst_idx)
443 jpeg_inst = GET_INST(JPEG, inst_idx);
444 data = RREG32_SOC15(JPEG, jpeg_inst, regJPEG_CGC_CTRL);
445 if (adev->cg_flags & AMD_CG_SUPPORT_JPEG_MGCG) {
446 data |= 1 << JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
447 data |= (JPEG_CGC_CTRL__JPEG0_DEC_MODE_MASK << 1);
449 data &= ~JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
452 data |= 1 << JPEG_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT;
453 data |= 4 << JPEG_CGC_CTRL__CLK_OFF_DELAY__SHIFT;
454 WREG32_SOC15(JPEG, jpeg_inst, regJPEG_CGC_CTRL, data);
456 data = RREG32_SOC15(JPEG, jpeg_inst, regJPEG_CGC_GATE);
457 data |= (JPEG_CGC_GATE__JMCIF_MASK | JPEG_CGC_GATE__JRBBM_MASK);
458 for (i = 0; i < adev->jpeg.num_jpeg_rings; ++i)
459 data |= (JPEG_CGC_GATE__JPEG0_DEC_MASK << i);
460 WREG32_SOC15(JPEG, jpeg_inst, regJPEG_CGC_GATE, data);
464 * jpeg_v4_0_3_start - start JPEG block
466 * @adev: amdgpu_device pointer
468 * Setup and start the JPEG block
470 static int jpeg_v4_0_3_start(struct amdgpu_device *adev)
472 struct amdgpu_ring *ring;
475 for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) {
476 jpeg_inst = GET_INST(JPEG, i);
478 WREG32_SOC15(JPEG, jpeg_inst, regUVD_PGFSM_CONFIG,
479 1 << UVD_PGFSM_CONFIG__UVDJ_PWR_CONFIG__SHIFT);
481 JPEG, jpeg_inst, regUVD_PGFSM_STATUS,
482 UVD_PGFSM_STATUS__UVDJ_PWR_ON
483 << UVD_PGFSM_STATUS__UVDJ_PWR_STATUS__SHIFT,
484 UVD_PGFSM_STATUS__UVDJ_PWR_STATUS_MASK);
486 /* disable anti hang mechanism */
487 WREG32_P(SOC15_REG_OFFSET(JPEG, jpeg_inst,
488 regUVD_JPEG_POWER_STATUS),
489 0, ~UVD_JPEG_POWER_STATUS__JPEG_POWER_STATUS_MASK);
491 /* JPEG disable CGC */
492 jpeg_v4_0_3_disable_clock_gating(adev, i);
494 /* MJPEG global tiling registers */
495 WREG32_SOC15(JPEG, jpeg_inst, regJPEG_DEC_GFX8_ADDR_CONFIG,
496 adev->gfx.config.gb_addr_config);
497 WREG32_SOC15(JPEG, jpeg_inst, regJPEG_DEC_GFX10_ADDR_CONFIG,
498 adev->gfx.config.gb_addr_config);
500 /* enable JMI channel */
501 WREG32_P(SOC15_REG_OFFSET(JPEG, jpeg_inst, regUVD_JMI_CNTL), 0,
502 ~UVD_JMI_CNTL__SOFT_RESET_MASK);
504 for (j = 0; j < adev->jpeg.num_jpeg_rings; ++j) {
505 unsigned int reg_offset = (j?(0x40 * j - 0xc80):0);
507 ring = &adev->jpeg.inst[i].ring_dec[j];
509 /* enable System Interrupt for JRBC */
510 WREG32_P(SOC15_REG_OFFSET(JPEG, jpeg_inst,
512 JPEG_SYS_INT_EN__DJRBC0_MASK << j,
513 ~(JPEG_SYS_INT_EN__DJRBC0_MASK << j));
515 WREG32_SOC15_OFFSET(JPEG, jpeg_inst,
516 regUVD_JMI0_UVD_LMI_JRBC_RB_VMID,
518 WREG32_SOC15_OFFSET(JPEG, jpeg_inst,
519 regUVD_JRBC0_UVD_JRBC_RB_CNTL,
521 (0x00000001L | 0x00000002L));
524 regUVD_JMI0_UVD_LMI_JRBC_RB_64BIT_BAR_LOW,
525 reg_offset, lower_32_bits(ring->gpu_addr));
528 regUVD_JMI0_UVD_LMI_JRBC_RB_64BIT_BAR_HIGH,
529 reg_offset, upper_32_bits(ring->gpu_addr));
530 WREG32_SOC15_OFFSET(JPEG, jpeg_inst,
531 regUVD_JRBC0_UVD_JRBC_RB_RPTR,
533 WREG32_SOC15_OFFSET(JPEG, jpeg_inst,
534 regUVD_JRBC0_UVD_JRBC_RB_WPTR,
536 WREG32_SOC15_OFFSET(JPEG, jpeg_inst,
537 regUVD_JRBC0_UVD_JRBC_RB_CNTL,
538 reg_offset, 0x00000002L);
539 WREG32_SOC15_OFFSET(JPEG, jpeg_inst,
540 regUVD_JRBC0_UVD_JRBC_RB_SIZE,
541 reg_offset, ring->ring_size / 4);
542 ring->wptr = RREG32_SOC15_OFFSET(
543 JPEG, jpeg_inst, regUVD_JRBC0_UVD_JRBC_RB_WPTR,
552 * jpeg_v4_0_3_stop - stop JPEG block
554 * @adev: amdgpu_device pointer
556 * stop the JPEG block
558 static int jpeg_v4_0_3_stop(struct amdgpu_device *adev)
562 for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) {
563 jpeg_inst = GET_INST(JPEG, i);
565 WREG32_P(SOC15_REG_OFFSET(JPEG, jpeg_inst, regUVD_JMI_CNTL),
566 UVD_JMI_CNTL__SOFT_RESET_MASK,
567 ~UVD_JMI_CNTL__SOFT_RESET_MASK);
569 jpeg_v4_0_3_enable_clock_gating(adev, i);
571 /* enable anti hang mechanism */
572 WREG32_P(SOC15_REG_OFFSET(JPEG, jpeg_inst,
573 regUVD_JPEG_POWER_STATUS),
574 UVD_JPEG_POWER_STATUS__JPEG_POWER_STATUS_MASK,
575 ~UVD_JPEG_POWER_STATUS__JPEG_POWER_STATUS_MASK);
577 WREG32_SOC15(JPEG, jpeg_inst, regUVD_PGFSM_CONFIG,
578 2 << UVD_PGFSM_CONFIG__UVDJ_PWR_CONFIG__SHIFT);
580 JPEG, jpeg_inst, regUVD_PGFSM_STATUS,
581 UVD_PGFSM_STATUS__UVDJ_PWR_OFF
582 << UVD_PGFSM_STATUS__UVDJ_PWR_STATUS__SHIFT,
583 UVD_PGFSM_STATUS__UVDJ_PWR_STATUS_MASK);
590 * jpeg_v4_0_3_dec_ring_get_rptr - get read pointer
592 * @ring: amdgpu_ring pointer
594 * Returns the current hardware read pointer
596 static uint64_t jpeg_v4_0_3_dec_ring_get_rptr(struct amdgpu_ring *ring)
598 struct amdgpu_device *adev = ring->adev;
600 return RREG32_SOC15_OFFSET(
601 JPEG, GET_INST(JPEG, ring->me), regUVD_JRBC0_UVD_JRBC_RB_RPTR,
602 ring->pipe ? (0x40 * ring->pipe - 0xc80) : 0);
606 * jpeg_v4_0_3_dec_ring_get_wptr - get write pointer
608 * @ring: amdgpu_ring pointer
610 * Returns the current hardware write pointer
612 static uint64_t jpeg_v4_0_3_dec_ring_get_wptr(struct amdgpu_ring *ring)
614 struct amdgpu_device *adev = ring->adev;
616 if (ring->use_doorbell)
617 return adev->wb.wb[ring->wptr_offs];
619 return RREG32_SOC15_OFFSET(
620 JPEG, GET_INST(JPEG, ring->me),
621 regUVD_JRBC0_UVD_JRBC_RB_WPTR,
622 ring->pipe ? (0x40 * ring->pipe - 0xc80) : 0);
626 * jpeg_v4_0_3_dec_ring_set_wptr - set write pointer
628 * @ring: amdgpu_ring pointer
630 * Commits the write pointer to the hardware
632 static void jpeg_v4_0_3_dec_ring_set_wptr(struct amdgpu_ring *ring)
634 struct amdgpu_device *adev = ring->adev;
636 if (ring->use_doorbell) {
637 adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr);
638 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr));
640 WREG32_SOC15_OFFSET(JPEG, GET_INST(JPEG, ring->me),
641 regUVD_JRBC0_UVD_JRBC_RB_WPTR,
642 (ring->pipe ? (0x40 * ring->pipe - 0xc80) :
644 lower_32_bits(ring->wptr));
649 * jpeg_v4_0_3_dec_ring_insert_start - insert a start command
651 * @ring: amdgpu_ring pointer
653 * Write a start command to the ring.
655 static void jpeg_v4_0_3_dec_ring_insert_start(struct amdgpu_ring *ring)
657 amdgpu_ring_write(ring, PACKETJ(regUVD_JRBC_EXTERNAL_REG_INTERNAL_OFFSET,
658 0, 0, PACKETJ_TYPE0));
659 amdgpu_ring_write(ring, 0x62a04); /* PCTL0_MMHUB_DEEPSLEEP_IB */
661 amdgpu_ring_write(ring, PACKETJ(JRBC_DEC_EXTERNAL_REG_WRITE_ADDR,
662 0, 0, PACKETJ_TYPE0));
663 amdgpu_ring_write(ring, 0x80004000);
667 * jpeg_v4_0_3_dec_ring_insert_end - insert a end command
669 * @ring: amdgpu_ring pointer
671 * Write a end command to the ring.
673 static void jpeg_v4_0_3_dec_ring_insert_end(struct amdgpu_ring *ring)
675 amdgpu_ring_write(ring, PACKETJ(regUVD_JRBC_EXTERNAL_REG_INTERNAL_OFFSET,
676 0, 0, PACKETJ_TYPE0));
677 amdgpu_ring_write(ring, 0x62a04);
679 amdgpu_ring_write(ring, PACKETJ(JRBC_DEC_EXTERNAL_REG_WRITE_ADDR,
680 0, 0, PACKETJ_TYPE0));
681 amdgpu_ring_write(ring, 0x00004000);
685 * jpeg_v4_0_3_dec_ring_emit_fence - emit an fence & trap command
687 * @ring: amdgpu_ring pointer
689 * @seq: sequence number
690 * @flags: fence related flags
692 * Write a fence and a trap command to the ring.
694 static void jpeg_v4_0_3_dec_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
697 WARN_ON(flags & AMDGPU_FENCE_FLAG_64BIT);
699 amdgpu_ring_write(ring, PACKETJ(regUVD_JPEG_GPCOM_DATA0_INTERNAL_OFFSET,
700 0, 0, PACKETJ_TYPE0));
701 amdgpu_ring_write(ring, seq);
703 amdgpu_ring_write(ring, PACKETJ(regUVD_JPEG_GPCOM_DATA1_INTERNAL_OFFSET,
704 0, 0, PACKETJ_TYPE0));
705 amdgpu_ring_write(ring, seq);
707 amdgpu_ring_write(ring, PACKETJ(regUVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_LOW_INTERNAL_OFFSET,
708 0, 0, PACKETJ_TYPE0));
709 amdgpu_ring_write(ring, lower_32_bits(addr));
711 amdgpu_ring_write(ring, PACKETJ(regUVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_HIGH_INTERNAL_OFFSET,
712 0, 0, PACKETJ_TYPE0));
713 amdgpu_ring_write(ring, upper_32_bits(addr));
715 amdgpu_ring_write(ring, PACKETJ(regUVD_JPEG_GPCOM_CMD_INTERNAL_OFFSET,
716 0, 0, PACKETJ_TYPE0));
717 amdgpu_ring_write(ring, 0x8);
719 amdgpu_ring_write(ring, PACKETJ(regUVD_JPEG_GPCOM_CMD_INTERNAL_OFFSET,
720 0, PACKETJ_CONDITION_CHECK0, PACKETJ_TYPE4));
721 amdgpu_ring_write(ring, 0);
723 if (ring->adev->jpeg.inst[ring->me].aid_id) {
724 amdgpu_ring_write(ring, PACKETJ(regUVD_JRBC_EXTERNAL_MCM_ADDR_INTERNAL_OFFSET,
725 0, PACKETJ_CONDITION_CHECK0, PACKETJ_TYPE0));
726 amdgpu_ring_write(ring, 0x4);
728 amdgpu_ring_write(ring, PACKETJ(0, 0, 0, PACKETJ_TYPE6));
729 amdgpu_ring_write(ring, 0);
732 amdgpu_ring_write(ring, PACKETJ(regUVD_JRBC_EXTERNAL_REG_INTERNAL_OFFSET,
733 0, 0, PACKETJ_TYPE0));
734 amdgpu_ring_write(ring, 0x3fbc);
736 if (ring->adev->jpeg.inst[ring->me].aid_id) {
737 amdgpu_ring_write(ring, PACKETJ(regUVD_JRBC_EXTERNAL_MCM_ADDR_INTERNAL_OFFSET,
738 0, PACKETJ_CONDITION_CHECK0, PACKETJ_TYPE0));
739 amdgpu_ring_write(ring, 0x0);
741 amdgpu_ring_write(ring, PACKETJ(0, 0, 0, PACKETJ_TYPE6));
742 amdgpu_ring_write(ring, 0);
745 amdgpu_ring_write(ring, PACKETJ(JRBC_DEC_EXTERNAL_REG_WRITE_ADDR,
746 0, 0, PACKETJ_TYPE0));
747 amdgpu_ring_write(ring, 0x1);
749 amdgpu_ring_write(ring, PACKETJ(0, 0, 0, PACKETJ_TYPE7));
750 amdgpu_ring_write(ring, 0);
754 * jpeg_v4_0_3_dec_ring_emit_ib - execute indirect buffer
756 * @ring: amdgpu_ring pointer
757 * @job: job to retrieve vmid from
758 * @ib: indirect buffer to execute
761 * Write ring commands to execute the indirect buffer.
763 static void jpeg_v4_0_3_dec_ring_emit_ib(struct amdgpu_ring *ring,
764 struct amdgpu_job *job,
765 struct amdgpu_ib *ib,
768 unsigned int vmid = AMDGPU_JOB_GET_VMID(job);
770 amdgpu_ring_write(ring, PACKETJ(regUVD_LMI_JRBC_IB_VMID_INTERNAL_OFFSET,
771 0, 0, PACKETJ_TYPE0));
772 amdgpu_ring_write(ring, (vmid | (vmid << 4)));
774 amdgpu_ring_write(ring, PACKETJ(regUVD_LMI_JPEG_VMID_INTERNAL_OFFSET,
775 0, 0, PACKETJ_TYPE0));
776 amdgpu_ring_write(ring, (vmid | (vmid << 4)));
778 amdgpu_ring_write(ring, PACKETJ(regUVD_LMI_JRBC_IB_64BIT_BAR_LOW_INTERNAL_OFFSET,
779 0, 0, PACKETJ_TYPE0));
780 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr));
782 amdgpu_ring_write(ring, PACKETJ(regUVD_LMI_JRBC_IB_64BIT_BAR_HIGH_INTERNAL_OFFSET,
783 0, 0, PACKETJ_TYPE0));
784 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
786 amdgpu_ring_write(ring, PACKETJ(regUVD_JRBC_IB_SIZE_INTERNAL_OFFSET,
787 0, 0, PACKETJ_TYPE0));
788 amdgpu_ring_write(ring, ib->length_dw);
790 amdgpu_ring_write(ring, PACKETJ(regUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_LOW_INTERNAL_OFFSET,
791 0, 0, PACKETJ_TYPE0));
792 amdgpu_ring_write(ring, lower_32_bits(ring->gpu_addr));
794 amdgpu_ring_write(ring, PACKETJ(regUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_HIGH_INTERNAL_OFFSET,
795 0, 0, PACKETJ_TYPE0));
796 amdgpu_ring_write(ring, upper_32_bits(ring->gpu_addr));
798 amdgpu_ring_write(ring, PACKETJ(0, 0, PACKETJ_CONDITION_CHECK0, PACKETJ_TYPE2));
799 amdgpu_ring_write(ring, 0);
801 amdgpu_ring_write(ring, PACKETJ(regUVD_JRBC_RB_COND_RD_TIMER_INTERNAL_OFFSET,
802 0, 0, PACKETJ_TYPE0));
803 amdgpu_ring_write(ring, 0x01400200);
805 amdgpu_ring_write(ring, PACKETJ(regUVD_JRBC_RB_REF_DATA_INTERNAL_OFFSET,
806 0, 0, PACKETJ_TYPE0));
807 amdgpu_ring_write(ring, 0x2);
809 amdgpu_ring_write(ring, PACKETJ(regUVD_JRBC_STATUS_INTERNAL_OFFSET,
810 0, PACKETJ_CONDITION_CHECK3, PACKETJ_TYPE3));
811 amdgpu_ring_write(ring, 0x2);
814 static void jpeg_v4_0_3_dec_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,
815 uint32_t val, uint32_t mask)
817 uint32_t reg_offset = (reg << 2);
819 amdgpu_ring_write(ring, PACKETJ(regUVD_JRBC_RB_COND_RD_TIMER_INTERNAL_OFFSET,
820 0, 0, PACKETJ_TYPE0));
821 amdgpu_ring_write(ring, 0x01400200);
823 amdgpu_ring_write(ring, PACKETJ(regUVD_JRBC_RB_REF_DATA_INTERNAL_OFFSET,
824 0, 0, PACKETJ_TYPE0));
825 amdgpu_ring_write(ring, val);
827 amdgpu_ring_write(ring, PACKETJ(regUVD_JRBC_EXTERNAL_REG_INTERNAL_OFFSET,
828 0, 0, PACKETJ_TYPE0));
829 if (reg_offset >= 0x10000 && reg_offset <= 0x105ff) {
830 amdgpu_ring_write(ring, 0);
831 amdgpu_ring_write(ring,
832 PACKETJ((reg_offset >> 2), 0, 0, PACKETJ_TYPE3));
834 amdgpu_ring_write(ring, reg_offset);
835 amdgpu_ring_write(ring, PACKETJ(JRBC_DEC_EXTERNAL_REG_WRITE_ADDR,
836 0, 0, PACKETJ_TYPE3));
838 amdgpu_ring_write(ring, mask);
841 static void jpeg_v4_0_3_dec_ring_emit_vm_flush(struct amdgpu_ring *ring,
842 unsigned int vmid, uint64_t pd_addr)
844 struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->vm_hub];
845 uint32_t data0, data1, mask;
847 pd_addr = amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
849 /* wait for register write */
850 data0 = hub->ctx0_ptb_addr_lo32 + vmid * hub->ctx_addr_distance;
851 data1 = lower_32_bits(pd_addr);
853 jpeg_v4_0_3_dec_ring_emit_reg_wait(ring, data0, data1, mask);
856 static void jpeg_v4_0_3_dec_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg, uint32_t val)
858 uint32_t reg_offset = (reg << 2);
860 amdgpu_ring_write(ring, PACKETJ(regUVD_JRBC_EXTERNAL_REG_INTERNAL_OFFSET,
861 0, 0, PACKETJ_TYPE0));
862 if (reg_offset >= 0x10000 && reg_offset <= 0x105ff) {
863 amdgpu_ring_write(ring, 0);
864 amdgpu_ring_write(ring,
865 PACKETJ((reg_offset >> 2), 0, 0, PACKETJ_TYPE0));
867 amdgpu_ring_write(ring, reg_offset);
868 amdgpu_ring_write(ring, PACKETJ(JRBC_DEC_EXTERNAL_REG_WRITE_ADDR,
869 0, 0, PACKETJ_TYPE0));
871 amdgpu_ring_write(ring, val);
874 static void jpeg_v4_0_3_dec_ring_nop(struct amdgpu_ring *ring, uint32_t count)
878 WARN_ON(ring->wptr % 2 || count % 2);
880 for (i = 0; i < count / 2; i++) {
881 amdgpu_ring_write(ring, PACKETJ(0, 0, 0, PACKETJ_TYPE6));
882 amdgpu_ring_write(ring, 0);
886 static bool jpeg_v4_0_3_is_idle(void *handle)
888 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
892 for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) {
893 for (j = 0; j < adev->jpeg.num_jpeg_rings; ++j) {
894 unsigned int reg_offset = (j?(0x40 * j - 0xc80):0);
896 ret &= ((RREG32_SOC15_OFFSET(
897 JPEG, GET_INST(JPEG, i),
898 regUVD_JRBC0_UVD_JRBC_STATUS,
900 UVD_JRBC0_UVD_JRBC_STATUS__RB_JOB_DONE_MASK) ==
901 UVD_JRBC0_UVD_JRBC_STATUS__RB_JOB_DONE_MASK);
908 static int jpeg_v4_0_3_wait_for_idle(void *handle)
910 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
914 for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) {
915 for (j = 0; j < adev->jpeg.num_jpeg_rings; ++j) {
916 unsigned int reg_offset = (j?(0x40 * j - 0xc80):0);
918 ret &= SOC15_WAIT_ON_RREG_OFFSET(
919 JPEG, GET_INST(JPEG, i),
920 regUVD_JRBC0_UVD_JRBC_STATUS, reg_offset,
921 UVD_JRBC0_UVD_JRBC_STATUS__RB_JOB_DONE_MASK,
922 UVD_JRBC0_UVD_JRBC_STATUS__RB_JOB_DONE_MASK);
928 static int jpeg_v4_0_3_set_clockgating_state(void *handle,
929 enum amd_clockgating_state state)
931 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
932 bool enable = state == AMD_CG_STATE_GATE;
935 for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) {
937 if (!jpeg_v4_0_3_is_idle(handle))
939 jpeg_v4_0_3_enable_clock_gating(adev, i);
941 jpeg_v4_0_3_disable_clock_gating(adev, i);
947 static int jpeg_v4_0_3_set_powergating_state(void *handle,
948 enum amd_powergating_state state)
950 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
953 if (amdgpu_sriov_vf(adev)) {
954 adev->jpeg.cur_state = AMD_PG_STATE_UNGATE;
958 if (state == adev->jpeg.cur_state)
961 if (state == AMD_PG_STATE_GATE)
962 ret = jpeg_v4_0_3_stop(adev);
964 ret = jpeg_v4_0_3_start(adev);
967 adev->jpeg.cur_state = state;
972 static int jpeg_v4_0_3_set_interrupt_state(struct amdgpu_device *adev,
973 struct amdgpu_irq_src *source,
975 enum amdgpu_interrupt_state state)
980 static int jpeg_v4_0_3_process_interrupt(struct amdgpu_device *adev,
981 struct amdgpu_irq_src *source,
982 struct amdgpu_iv_entry *entry)
986 i = node_id_to_phys_map[entry->node_id];
987 DRM_DEV_DEBUG(adev->dev, "IH: JPEG TRAP\n");
989 for (inst = 0; inst < adev->jpeg.num_jpeg_inst; ++inst)
990 if (adev->jpeg.inst[inst].aid_id == i)
993 if (inst >= adev->jpeg.num_jpeg_inst) {
994 dev_WARN_ONCE(adev->dev, 1,
995 "Interrupt received for unknown JPEG instance %d",
1000 switch (entry->src_id) {
1001 case VCN_4_0__SRCID__JPEG_DECODE:
1002 amdgpu_fence_process(&adev->jpeg.inst[inst].ring_dec[0]);
1004 case VCN_4_0__SRCID__JPEG1_DECODE:
1005 amdgpu_fence_process(&adev->jpeg.inst[inst].ring_dec[1]);
1007 case VCN_4_0__SRCID__JPEG2_DECODE:
1008 amdgpu_fence_process(&adev->jpeg.inst[inst].ring_dec[2]);
1010 case VCN_4_0__SRCID__JPEG3_DECODE:
1011 amdgpu_fence_process(&adev->jpeg.inst[inst].ring_dec[3]);
1013 case VCN_4_0__SRCID__JPEG4_DECODE:
1014 amdgpu_fence_process(&adev->jpeg.inst[inst].ring_dec[4]);
1016 case VCN_4_0__SRCID__JPEG5_DECODE:
1017 amdgpu_fence_process(&adev->jpeg.inst[inst].ring_dec[5]);
1019 case VCN_4_0__SRCID__JPEG6_DECODE:
1020 amdgpu_fence_process(&adev->jpeg.inst[inst].ring_dec[6]);
1022 case VCN_4_0__SRCID__JPEG7_DECODE:
1023 amdgpu_fence_process(&adev->jpeg.inst[inst].ring_dec[7]);
1026 DRM_DEV_ERROR(adev->dev, "Unhandled interrupt: %d %d\n",
1027 entry->src_id, entry->src_data[0]);
1034 static const struct amd_ip_funcs jpeg_v4_0_3_ip_funcs = {
1035 .name = "jpeg_v4_0_3",
1036 .early_init = jpeg_v4_0_3_early_init,
1038 .sw_init = jpeg_v4_0_3_sw_init,
1039 .sw_fini = jpeg_v4_0_3_sw_fini,
1040 .hw_init = jpeg_v4_0_3_hw_init,
1041 .hw_fini = jpeg_v4_0_3_hw_fini,
1042 .suspend = jpeg_v4_0_3_suspend,
1043 .resume = jpeg_v4_0_3_resume,
1044 .is_idle = jpeg_v4_0_3_is_idle,
1045 .wait_for_idle = jpeg_v4_0_3_wait_for_idle,
1046 .check_soft_reset = NULL,
1047 .pre_soft_reset = NULL,
1049 .post_soft_reset = NULL,
1050 .set_clockgating_state = jpeg_v4_0_3_set_clockgating_state,
1051 .set_powergating_state = jpeg_v4_0_3_set_powergating_state,
1054 static const struct amdgpu_ring_funcs jpeg_v4_0_3_dec_ring_vm_funcs = {
1055 .type = AMDGPU_RING_TYPE_VCN_JPEG,
1057 .get_rptr = jpeg_v4_0_3_dec_ring_get_rptr,
1058 .get_wptr = jpeg_v4_0_3_dec_ring_get_wptr,
1059 .set_wptr = jpeg_v4_0_3_dec_ring_set_wptr,
1061 SOC15_FLUSH_GPU_TLB_NUM_WREG * 6 +
1062 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 8 +
1063 8 + /* jpeg_v4_0_3_dec_ring_emit_vm_flush */
1064 22 + 22 + /* jpeg_v4_0_3_dec_ring_emit_fence x2 vm fence */
1066 .emit_ib_size = 22, /* jpeg_v4_0_3_dec_ring_emit_ib */
1067 .emit_ib = jpeg_v4_0_3_dec_ring_emit_ib,
1068 .emit_fence = jpeg_v4_0_3_dec_ring_emit_fence,
1069 .emit_vm_flush = jpeg_v4_0_3_dec_ring_emit_vm_flush,
1070 .test_ring = amdgpu_jpeg_dec_ring_test_ring,
1071 .test_ib = amdgpu_jpeg_dec_ring_test_ib,
1072 .insert_nop = jpeg_v4_0_3_dec_ring_nop,
1073 .insert_start = jpeg_v4_0_3_dec_ring_insert_start,
1074 .insert_end = jpeg_v4_0_3_dec_ring_insert_end,
1075 .pad_ib = amdgpu_ring_generic_pad_ib,
1076 .begin_use = amdgpu_jpeg_ring_begin_use,
1077 .end_use = amdgpu_jpeg_ring_end_use,
1078 .emit_wreg = jpeg_v4_0_3_dec_ring_emit_wreg,
1079 .emit_reg_wait = jpeg_v4_0_3_dec_ring_emit_reg_wait,
1080 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,
1083 static void jpeg_v4_0_3_set_dec_ring_funcs(struct amdgpu_device *adev)
1085 int i, j, jpeg_inst;
1087 for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) {
1088 for (j = 0; j < adev->jpeg.num_jpeg_rings; ++j) {
1089 adev->jpeg.inst[i].ring_dec[j].funcs = &jpeg_v4_0_3_dec_ring_vm_funcs;
1090 adev->jpeg.inst[i].ring_dec[j].me = i;
1091 adev->jpeg.inst[i].ring_dec[j].pipe = j;
1093 jpeg_inst = GET_INST(JPEG, i);
1094 adev->jpeg.inst[i].aid_id =
1095 jpeg_inst / adev->jpeg.num_inst_per_aid;
1097 DRM_DEV_INFO(adev->dev, "JPEG decode is enabled in VM mode\n");
1100 static const struct amdgpu_irq_src_funcs jpeg_v4_0_3_irq_funcs = {
1101 .set = jpeg_v4_0_3_set_interrupt_state,
1102 .process = jpeg_v4_0_3_process_interrupt,
1105 static void jpeg_v4_0_3_set_irq_funcs(struct amdgpu_device *adev)
1109 for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) {
1110 adev->jpeg.inst->irq.num_types += adev->jpeg.num_jpeg_rings;
1112 adev->jpeg.inst->irq.funcs = &jpeg_v4_0_3_irq_funcs;
1115 const struct amdgpu_ip_block_version jpeg_v4_0_3_ip_block = {
1116 .type = AMD_IP_BLOCK_TYPE_JPEG,
1120 .funcs = &jpeg_v4_0_3_ip_funcs,
1123 static const struct amdgpu_ras_err_status_reg_entry jpeg_v4_0_3_ue_reg_list[] = {
1124 {AMDGPU_RAS_REG_ENTRY(JPEG, 0, regVCN_UE_ERR_STATUS_LO_JPEG0S, regVCN_UE_ERR_STATUS_HI_JPEG0S),
1125 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "JPEG0S"},
1126 {AMDGPU_RAS_REG_ENTRY(JPEG, 0, regVCN_UE_ERR_STATUS_LO_JPEG0D, regVCN_UE_ERR_STATUS_HI_JPEG0D),
1127 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "JPEG0D"},
1128 {AMDGPU_RAS_REG_ENTRY(JPEG, 0, regVCN_UE_ERR_STATUS_LO_JPEG1S, regVCN_UE_ERR_STATUS_HI_JPEG1S),
1129 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "JPEG1S"},
1130 {AMDGPU_RAS_REG_ENTRY(JPEG, 0, regVCN_UE_ERR_STATUS_LO_JPEG1D, regVCN_UE_ERR_STATUS_HI_JPEG1D),
1131 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "JPEG1D"},
1132 {AMDGPU_RAS_REG_ENTRY(JPEG, 0, regVCN_UE_ERR_STATUS_LO_JPEG2S, regVCN_UE_ERR_STATUS_HI_JPEG2S),
1133 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "JPEG2S"},
1134 {AMDGPU_RAS_REG_ENTRY(JPEG, 0, regVCN_UE_ERR_STATUS_LO_JPEG2D, regVCN_UE_ERR_STATUS_HI_JPEG2D),
1135 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "JPEG2D"},
1136 {AMDGPU_RAS_REG_ENTRY(JPEG, 0, regVCN_UE_ERR_STATUS_LO_JPEG3S, regVCN_UE_ERR_STATUS_HI_JPEG3S),
1137 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "JPEG3S"},
1138 {AMDGPU_RAS_REG_ENTRY(JPEG, 0, regVCN_UE_ERR_STATUS_LO_JPEG3D, regVCN_UE_ERR_STATUS_HI_JPEG3D),
1139 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "JPEG3D"},
1140 {AMDGPU_RAS_REG_ENTRY(JPEG, 0, regVCN_UE_ERR_STATUS_LO_JPEG4S, regVCN_UE_ERR_STATUS_HI_JPEG4S),
1141 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "JPEG4S"},
1142 {AMDGPU_RAS_REG_ENTRY(JPEG, 0, regVCN_UE_ERR_STATUS_LO_JPEG4D, regVCN_UE_ERR_STATUS_HI_JPEG4D),
1143 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "JPEG4D"},
1144 {AMDGPU_RAS_REG_ENTRY(JPEG, 0, regVCN_UE_ERR_STATUS_LO_JPEG5S, regVCN_UE_ERR_STATUS_HI_JPEG5S),
1145 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "JPEG5S"},
1146 {AMDGPU_RAS_REG_ENTRY(JPEG, 0, regVCN_UE_ERR_STATUS_LO_JPEG5D, regVCN_UE_ERR_STATUS_HI_JPEG5D),
1147 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "JPEG5D"},
1148 {AMDGPU_RAS_REG_ENTRY(JPEG, 0, regVCN_UE_ERR_STATUS_LO_JPEG6S, regVCN_UE_ERR_STATUS_HI_JPEG6S),
1149 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "JPEG6S"},
1150 {AMDGPU_RAS_REG_ENTRY(JPEG, 0, regVCN_UE_ERR_STATUS_LO_JPEG6D, regVCN_UE_ERR_STATUS_HI_JPEG6D),
1151 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "JPEG6D"},
1152 {AMDGPU_RAS_REG_ENTRY(JPEG, 0, regVCN_UE_ERR_STATUS_LO_JPEG7S, regVCN_UE_ERR_STATUS_HI_JPEG7S),
1153 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "JPEG7S"},
1154 {AMDGPU_RAS_REG_ENTRY(JPEG, 0, regVCN_UE_ERR_STATUS_LO_JPEG7D, regVCN_UE_ERR_STATUS_HI_JPEG7D),
1155 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "JPEG7D"},
1158 static void jpeg_v4_0_3_inst_query_ras_error_count(struct amdgpu_device *adev,
1160 void *ras_err_status)
1162 struct ras_err_data *err_data = (struct ras_err_data *)ras_err_status;
1164 /* jpeg v4_0_3 only support uncorrectable errors */
1165 amdgpu_ras_inst_query_ras_error_count(adev,
1166 jpeg_v4_0_3_ue_reg_list,
1167 ARRAY_SIZE(jpeg_v4_0_3_ue_reg_list),
1168 NULL, 0, GET_INST(VCN, jpeg_inst),
1169 AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE,
1170 &err_data->ue_count);
1173 static void jpeg_v4_0_3_query_ras_error_count(struct amdgpu_device *adev,
1174 void *ras_err_status)
1178 if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__JPEG)) {
1179 dev_warn(adev->dev, "JPEG RAS is not supported\n");
1183 for (i = 0; i < adev->jpeg.num_jpeg_inst; i++)
1184 jpeg_v4_0_3_inst_query_ras_error_count(adev, i, ras_err_status);
1187 static void jpeg_v4_0_3_inst_reset_ras_error_count(struct amdgpu_device *adev,
1190 amdgpu_ras_inst_reset_ras_error_count(adev,
1191 jpeg_v4_0_3_ue_reg_list,
1192 ARRAY_SIZE(jpeg_v4_0_3_ue_reg_list),
1193 GET_INST(VCN, jpeg_inst));
1196 static void jpeg_v4_0_3_reset_ras_error_count(struct amdgpu_device *adev)
1200 if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__JPEG)) {
1201 dev_warn(adev->dev, "JPEG RAS is not supported\n");
1205 for (i = 0; i < adev->jpeg.num_jpeg_inst; i++)
1206 jpeg_v4_0_3_inst_reset_ras_error_count(adev, i);
1209 static const struct amdgpu_ras_block_hw_ops jpeg_v4_0_3_ras_hw_ops = {
1210 .query_ras_error_count = jpeg_v4_0_3_query_ras_error_count,
1211 .reset_ras_error_count = jpeg_v4_0_3_reset_ras_error_count,
1214 static struct amdgpu_jpeg_ras jpeg_v4_0_3_ras = {
1216 .hw_ops = &jpeg_v4_0_3_ras_hw_ops,
1220 static void jpeg_v4_0_3_set_ras_funcs(struct amdgpu_device *adev)
1222 adev->jpeg.ras = &jpeg_v4_0_3_ras;