2 * Copyright 2019 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
25 #include "amdgpu_jpeg.h"
26 #include "amdgpu_pm.h"
29 #include "jpeg_v2_0.h"
31 #include "vcn/vcn_2_0_0_offset.h"
32 #include "vcn/vcn_2_0_0_sh_mask.h"
33 #include "ivsrcid/vcn/irqsrcs_vcn_2_0.h"
35 #define mmUVD_JRBC_EXTERNAL_REG_INTERNAL_OFFSET 0x1bfff
36 #define mmUVD_JPEG_GPCOM_CMD_INTERNAL_OFFSET 0x4029
37 #define mmUVD_JPEG_GPCOM_DATA0_INTERNAL_OFFSET 0x402a
38 #define mmUVD_JPEG_GPCOM_DATA1_INTERNAL_OFFSET 0x402b
39 #define mmUVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_LOW_INTERNAL_OFFSET 0x40ea
40 #define mmUVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_HIGH_INTERNAL_OFFSET 0x40eb
41 #define mmUVD_LMI_JRBC_IB_VMID_INTERNAL_OFFSET 0x40cf
42 #define mmUVD_LMI_JPEG_VMID_INTERNAL_OFFSET 0x40d1
43 #define mmUVD_LMI_JRBC_IB_64BIT_BAR_LOW_INTERNAL_OFFSET 0x40e8
44 #define mmUVD_LMI_JRBC_IB_64BIT_BAR_HIGH_INTERNAL_OFFSET 0x40e9
45 #define mmUVD_JRBC_IB_SIZE_INTERNAL_OFFSET 0x4082
46 #define mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_LOW_INTERNAL_OFFSET 0x40ec
47 #define mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_HIGH_INTERNAL_OFFSET 0x40ed
48 #define mmUVD_JRBC_RB_COND_RD_TIMER_INTERNAL_OFFSET 0x4085
49 #define mmUVD_JRBC_RB_REF_DATA_INTERNAL_OFFSET 0x4084
50 #define mmUVD_JRBC_STATUS_INTERNAL_OFFSET 0x4089
51 #define mmUVD_JPEG_PITCH_INTERNAL_OFFSET 0x401f
53 #define JRBC_DEC_EXTERNAL_REG_WRITE_ADDR 0x18000
55 static void jpeg_v2_0_set_dec_ring_funcs(struct amdgpu_device *adev);
56 static void jpeg_v2_0_set_irq_funcs(struct amdgpu_device *adev);
57 static int jpeg_v2_0_set_powergating_state(void *handle,
58 enum amd_powergating_state state);
61 * jpeg_v2_0_early_init - set function pointers
63 * @handle: amdgpu_device pointer
65 * Set ring and irq function pointers
67 static int jpeg_v2_0_early_init(void *handle)
69 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
71 adev->jpeg.num_jpeg_inst = 1;
73 jpeg_v2_0_set_dec_ring_funcs(adev);
74 jpeg_v2_0_set_irq_funcs(adev);
80 * jpeg_v2_0_sw_init - sw init for JPEG block
82 * @handle: amdgpu_device pointer
84 * Load firmware and sw initialization
86 static int jpeg_v2_0_sw_init(void *handle)
88 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
89 struct amdgpu_ring *ring;
93 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VCN,
94 VCN_2_0__SRCID__JPEG_DECODE, &adev->jpeg.inst->irq);
98 r = amdgpu_jpeg_sw_init(adev);
102 r = amdgpu_jpeg_resume(adev);
106 ring = &adev->jpeg.inst->ring_dec;
107 ring->use_doorbell = true;
108 ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 1;
109 sprintf(ring->name, "jpeg_dec");
110 r = amdgpu_ring_init(adev, ring, 512, &adev->jpeg.inst->irq,
111 0, AMDGPU_RING_PRIO_DEFAULT, NULL);
115 adev->jpeg.internal.jpeg_pitch = mmUVD_JPEG_PITCH_INTERNAL_OFFSET;
116 adev->jpeg.inst->external.jpeg_pitch = SOC15_REG_OFFSET(JPEG, 0, mmUVD_JPEG_PITCH);
122 * jpeg_v2_0_sw_fini - sw fini for JPEG block
124 * @handle: amdgpu_device pointer
126 * JPEG suspend and free up sw allocation
128 static int jpeg_v2_0_sw_fini(void *handle)
131 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
133 r = amdgpu_jpeg_suspend(adev);
137 r = amdgpu_jpeg_sw_fini(adev);
143 * jpeg_v2_0_hw_init - start and test JPEG block
145 * @handle: amdgpu_device pointer
148 static int jpeg_v2_0_hw_init(void *handle)
150 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
151 struct amdgpu_ring *ring = &adev->jpeg.inst->ring_dec;
154 adev->nbio.funcs->vcn_doorbell_range(adev, ring->use_doorbell,
155 (adev->doorbell_index.vcn.vcn_ring0_1 << 1), 0);
157 r = amdgpu_ring_test_helper(ring);
159 DRM_INFO("JPEG decode initialized successfully.\n");
165 * jpeg_v2_0_hw_fini - stop the hardware block
167 * @handle: amdgpu_device pointer
169 * Stop the JPEG block, mark ring as not ready any more
171 static int jpeg_v2_0_hw_fini(void *handle)
173 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
175 cancel_delayed_work_sync(&adev->vcn.idle_work);
177 if (adev->jpeg.cur_state != AMD_PG_STATE_GATE &&
178 RREG32_SOC15(JPEG, 0, mmUVD_JRBC_STATUS))
179 jpeg_v2_0_set_powergating_state(adev, AMD_PG_STATE_GATE);
185 * jpeg_v2_0_suspend - suspend JPEG block
187 * @handle: amdgpu_device pointer
189 * HW fini and suspend JPEG block
191 static int jpeg_v2_0_suspend(void *handle)
193 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
196 r = jpeg_v2_0_hw_fini(adev);
200 r = amdgpu_jpeg_suspend(adev);
206 * jpeg_v2_0_resume - resume JPEG block
208 * @handle: amdgpu_device pointer
210 * Resume firmware and hw init JPEG block
212 static int jpeg_v2_0_resume(void *handle)
215 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
217 r = amdgpu_jpeg_resume(adev);
221 r = jpeg_v2_0_hw_init(adev);
226 static int jpeg_v2_0_disable_power_gating(struct amdgpu_device *adev)
231 if (adev->pg_flags & AMD_PG_SUPPORT_JPEG) {
232 data = 1 << UVD_PGFSM_CONFIG__UVDJ_PWR_CONFIG__SHIFT;
233 WREG32(SOC15_REG_OFFSET(JPEG, 0, mmUVD_PGFSM_CONFIG), data);
235 r = SOC15_WAIT_ON_RREG(JPEG, 0,
236 mmUVD_PGFSM_STATUS, UVD_PGFSM_STATUS_UVDJ_PWR_ON,
237 UVD_PGFSM_STATUS__UVDJ_PWR_STATUS_MASK);
240 DRM_ERROR("amdgpu: JPEG disable power gating failed\n");
245 /* Removing the anti hang mechanism to indicate the UVDJ tile is ON */
246 data = RREG32(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JPEG_POWER_STATUS)) & ~0x1;
247 WREG32(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JPEG_POWER_STATUS), data);
252 static int jpeg_v2_0_enable_power_gating(struct amdgpu_device *adev)
254 if (adev->pg_flags & AMD_PG_SUPPORT_JPEG) {
258 data = RREG32(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JPEG_POWER_STATUS));
259 data &= ~UVD_JPEG_POWER_STATUS__JPEG_POWER_STATUS_MASK;
260 data |= 0x1; //UVD_JPEG_POWER_STATUS__JPEG_POWER_STATUS_TILES_OFF;
261 WREG32(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JPEG_POWER_STATUS), data);
263 data = 2 << UVD_PGFSM_CONFIG__UVDJ_PWR_CONFIG__SHIFT;
264 WREG32(SOC15_REG_OFFSET(JPEG, 0, mmUVD_PGFSM_CONFIG), data);
266 r = SOC15_WAIT_ON_RREG(JPEG, 0, mmUVD_PGFSM_STATUS,
267 (2 << UVD_PGFSM_STATUS__UVDJ_PWR_STATUS__SHIFT),
268 UVD_PGFSM_STATUS__UVDJ_PWR_STATUS_MASK);
271 DRM_ERROR("amdgpu: JPEG enable power gating failed\n");
279 static void jpeg_v2_0_disable_clock_gating(struct amdgpu_device *adev)
283 data = RREG32_SOC15(JPEG, 0, mmJPEG_CGC_CTRL);
284 if (adev->cg_flags & AMD_CG_SUPPORT_JPEG_MGCG)
285 data |= 1 << JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
287 data &= ~JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
289 data |= 1 << JPEG_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT;
290 data |= 4 << JPEG_CGC_CTRL__CLK_OFF_DELAY__SHIFT;
291 WREG32_SOC15(JPEG, 0, mmJPEG_CGC_CTRL, data);
293 data = RREG32_SOC15(JPEG, 0, mmJPEG_CGC_GATE);
294 data &= ~(JPEG_CGC_GATE__JPEG_DEC_MASK
295 | JPEG_CGC_GATE__JPEG2_DEC_MASK
296 | JPEG_CGC_GATE__JPEG_ENC_MASK
297 | JPEG_CGC_GATE__JMCIF_MASK
298 | JPEG_CGC_GATE__JRBBM_MASK);
299 WREG32_SOC15(JPEG, 0, mmJPEG_CGC_GATE, data);
302 static void jpeg_v2_0_enable_clock_gating(struct amdgpu_device *adev)
306 data = RREG32_SOC15(JPEG, 0, mmJPEG_CGC_CTRL);
307 if (adev->cg_flags & AMD_CG_SUPPORT_JPEG_MGCG)
308 data |= 1 << JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
310 data |= 0 << JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
312 data |= 1 << JPEG_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT;
313 data |= 4 << JPEG_CGC_CTRL__CLK_OFF_DELAY__SHIFT;
314 WREG32_SOC15(JPEG, 0, mmJPEG_CGC_CTRL, data);
316 data = RREG32_SOC15(JPEG, 0, mmJPEG_CGC_GATE);
317 data |= (JPEG_CGC_GATE__JPEG_DEC_MASK
318 |JPEG_CGC_GATE__JPEG2_DEC_MASK
319 |JPEG_CGC_GATE__JPEG_ENC_MASK
320 |JPEG_CGC_GATE__JMCIF_MASK
321 |JPEG_CGC_GATE__JRBBM_MASK);
322 WREG32_SOC15(JPEG, 0, mmJPEG_CGC_GATE, data);
326 * jpeg_v2_0_start - start JPEG block
328 * @adev: amdgpu_device pointer
330 * Setup and start the JPEG block
332 static int jpeg_v2_0_start(struct amdgpu_device *adev)
334 struct amdgpu_ring *ring = &adev->jpeg.inst->ring_dec;
337 if (adev->pm.dpm_enabled)
338 amdgpu_dpm_enable_jpeg(adev, true);
340 /* disable power gating */
341 r = jpeg_v2_0_disable_power_gating(adev);
345 /* JPEG disable CGC */
346 jpeg_v2_0_disable_clock_gating(adev);
348 WREG32_SOC15(JPEG, 0, mmJPEG_DEC_GFX10_ADDR_CONFIG, adev->gfx.config.gb_addr_config);
350 /* enable JMI channel */
351 WREG32_P(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JMI_CNTL), 0,
352 ~UVD_JMI_CNTL__SOFT_RESET_MASK);
354 /* enable System Interrupt for JRBC */
355 WREG32_P(SOC15_REG_OFFSET(JPEG, 0, mmJPEG_SYS_INT_EN),
356 JPEG_SYS_INT_EN__DJRBC_MASK,
357 ~JPEG_SYS_INT_EN__DJRBC_MASK);
359 WREG32_SOC15(JPEG, 0, mmUVD_LMI_JRBC_RB_VMID, 0);
360 WREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_CNTL, (0x00000001L | 0x00000002L));
361 WREG32_SOC15(JPEG, 0, mmUVD_LMI_JRBC_RB_64BIT_BAR_LOW,
362 lower_32_bits(ring->gpu_addr));
363 WREG32_SOC15(JPEG, 0, mmUVD_LMI_JRBC_RB_64BIT_BAR_HIGH,
364 upper_32_bits(ring->gpu_addr));
365 WREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_RPTR, 0);
366 WREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_WPTR, 0);
367 WREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_CNTL, 0x00000002L);
368 WREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_SIZE, ring->ring_size / 4);
369 ring->wptr = RREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_WPTR);
375 * jpeg_v2_0_stop - stop JPEG block
377 * @adev: amdgpu_device pointer
379 * stop the JPEG block
381 static int jpeg_v2_0_stop(struct amdgpu_device *adev)
386 WREG32_P(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JMI_CNTL),
387 UVD_JMI_CNTL__SOFT_RESET_MASK,
388 ~UVD_JMI_CNTL__SOFT_RESET_MASK);
390 /* enable JPEG CGC */
391 jpeg_v2_0_enable_clock_gating(adev);
393 /* enable power gating */
394 r = jpeg_v2_0_enable_power_gating(adev);
398 if (adev->pm.dpm_enabled)
399 amdgpu_dpm_enable_jpeg(adev, false);
405 * jpeg_v2_0_dec_ring_get_rptr - get read pointer
407 * @ring: amdgpu_ring pointer
409 * Returns the current hardware read pointer
411 static uint64_t jpeg_v2_0_dec_ring_get_rptr(struct amdgpu_ring *ring)
413 struct amdgpu_device *adev = ring->adev;
415 return RREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_RPTR);
419 * jpeg_v2_0_dec_ring_get_wptr - get write pointer
421 * @ring: amdgpu_ring pointer
423 * Returns the current hardware write pointer
425 static uint64_t jpeg_v2_0_dec_ring_get_wptr(struct amdgpu_ring *ring)
427 struct amdgpu_device *adev = ring->adev;
429 if (ring->use_doorbell)
430 return adev->wb.wb[ring->wptr_offs];
432 return RREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_WPTR);
436 * jpeg_v2_0_dec_ring_set_wptr - set write pointer
438 * @ring: amdgpu_ring pointer
440 * Commits the write pointer to the hardware
442 static void jpeg_v2_0_dec_ring_set_wptr(struct amdgpu_ring *ring)
444 struct amdgpu_device *adev = ring->adev;
446 if (ring->use_doorbell) {
447 adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr);
448 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr));
450 WREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_WPTR, lower_32_bits(ring->wptr));
455 * jpeg_v2_0_dec_ring_insert_start - insert a start command
457 * @ring: amdgpu_ring pointer
459 * Write a start command to the ring.
461 void jpeg_v2_0_dec_ring_insert_start(struct amdgpu_ring *ring)
463 amdgpu_ring_write(ring, PACKETJ(mmUVD_JRBC_EXTERNAL_REG_INTERNAL_OFFSET,
464 0, 0, PACKETJ_TYPE0));
465 amdgpu_ring_write(ring, 0x68e04);
467 amdgpu_ring_write(ring, PACKETJ(JRBC_DEC_EXTERNAL_REG_WRITE_ADDR,
468 0, 0, PACKETJ_TYPE0));
469 amdgpu_ring_write(ring, 0x80010000);
473 * jpeg_v2_0_dec_ring_insert_end - insert a end command
475 * @ring: amdgpu_ring pointer
477 * Write a end command to the ring.
479 void jpeg_v2_0_dec_ring_insert_end(struct amdgpu_ring *ring)
481 amdgpu_ring_write(ring, PACKETJ(mmUVD_JRBC_EXTERNAL_REG_INTERNAL_OFFSET,
482 0, 0, PACKETJ_TYPE0));
483 amdgpu_ring_write(ring, 0x68e04);
485 amdgpu_ring_write(ring, PACKETJ(JRBC_DEC_EXTERNAL_REG_WRITE_ADDR,
486 0, 0, PACKETJ_TYPE0));
487 amdgpu_ring_write(ring, 0x00010000);
491 * jpeg_v2_0_dec_ring_emit_fence - emit an fence & trap command
493 * @ring: amdgpu_ring pointer
495 * @seq: sequence number
496 * @flags: fence related flags
498 * Write a fence and a trap command to the ring.
500 void jpeg_v2_0_dec_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
503 WARN_ON(flags & AMDGPU_FENCE_FLAG_64BIT);
505 amdgpu_ring_write(ring, PACKETJ(mmUVD_JPEG_GPCOM_DATA0_INTERNAL_OFFSET,
506 0, 0, PACKETJ_TYPE0));
507 amdgpu_ring_write(ring, seq);
509 amdgpu_ring_write(ring, PACKETJ(mmUVD_JPEG_GPCOM_DATA1_INTERNAL_OFFSET,
510 0, 0, PACKETJ_TYPE0));
511 amdgpu_ring_write(ring, seq);
513 amdgpu_ring_write(ring, PACKETJ(mmUVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_LOW_INTERNAL_OFFSET,
514 0, 0, PACKETJ_TYPE0));
515 amdgpu_ring_write(ring, lower_32_bits(addr));
517 amdgpu_ring_write(ring, PACKETJ(mmUVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_HIGH_INTERNAL_OFFSET,
518 0, 0, PACKETJ_TYPE0));
519 amdgpu_ring_write(ring, upper_32_bits(addr));
521 amdgpu_ring_write(ring, PACKETJ(mmUVD_JPEG_GPCOM_CMD_INTERNAL_OFFSET,
522 0, 0, PACKETJ_TYPE0));
523 amdgpu_ring_write(ring, 0x8);
525 amdgpu_ring_write(ring, PACKETJ(mmUVD_JPEG_GPCOM_CMD_INTERNAL_OFFSET,
526 0, PACKETJ_CONDITION_CHECK0, PACKETJ_TYPE4));
527 amdgpu_ring_write(ring, 0);
529 amdgpu_ring_write(ring, PACKETJ(mmUVD_JRBC_EXTERNAL_REG_INTERNAL_OFFSET,
530 0, 0, PACKETJ_TYPE0));
531 amdgpu_ring_write(ring, 0x3fbc);
533 amdgpu_ring_write(ring, PACKETJ(JRBC_DEC_EXTERNAL_REG_WRITE_ADDR,
534 0, 0, PACKETJ_TYPE0));
535 amdgpu_ring_write(ring, 0x1);
537 amdgpu_ring_write(ring, PACKETJ(0, 0, 0, PACKETJ_TYPE7));
538 amdgpu_ring_write(ring, 0);
542 * jpeg_v2_0_dec_ring_emit_ib - execute indirect buffer
544 * @ring: amdgpu_ring pointer
545 * @job: job to retrieve vmid from
546 * @ib: indirect buffer to execute
549 * Write ring commands to execute the indirect buffer.
551 void jpeg_v2_0_dec_ring_emit_ib(struct amdgpu_ring *ring,
552 struct amdgpu_job *job,
553 struct amdgpu_ib *ib,
556 unsigned vmid = AMDGPU_JOB_GET_VMID(job);
558 amdgpu_ring_write(ring, PACKETJ(mmUVD_LMI_JRBC_IB_VMID_INTERNAL_OFFSET,
559 0, 0, PACKETJ_TYPE0));
560 amdgpu_ring_write(ring, (vmid | (vmid << 4)));
562 amdgpu_ring_write(ring, PACKETJ(mmUVD_LMI_JPEG_VMID_INTERNAL_OFFSET,
563 0, 0, PACKETJ_TYPE0));
564 amdgpu_ring_write(ring, (vmid | (vmid << 4)));
566 amdgpu_ring_write(ring, PACKETJ(mmUVD_LMI_JRBC_IB_64BIT_BAR_LOW_INTERNAL_OFFSET,
567 0, 0, PACKETJ_TYPE0));
568 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr));
570 amdgpu_ring_write(ring, PACKETJ(mmUVD_LMI_JRBC_IB_64BIT_BAR_HIGH_INTERNAL_OFFSET,
571 0, 0, PACKETJ_TYPE0));
572 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
574 amdgpu_ring_write(ring, PACKETJ(mmUVD_JRBC_IB_SIZE_INTERNAL_OFFSET,
575 0, 0, PACKETJ_TYPE0));
576 amdgpu_ring_write(ring, ib->length_dw);
578 amdgpu_ring_write(ring, PACKETJ(mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_LOW_INTERNAL_OFFSET,
579 0, 0, PACKETJ_TYPE0));
580 amdgpu_ring_write(ring, lower_32_bits(ring->gpu_addr));
582 amdgpu_ring_write(ring, PACKETJ(mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_HIGH_INTERNAL_OFFSET,
583 0, 0, PACKETJ_TYPE0));
584 amdgpu_ring_write(ring, upper_32_bits(ring->gpu_addr));
586 amdgpu_ring_write(ring, PACKETJ(0, 0, PACKETJ_CONDITION_CHECK0, PACKETJ_TYPE2));
587 amdgpu_ring_write(ring, 0);
589 amdgpu_ring_write(ring, PACKETJ(mmUVD_JRBC_RB_COND_RD_TIMER_INTERNAL_OFFSET,
590 0, 0, PACKETJ_TYPE0));
591 amdgpu_ring_write(ring, 0x01400200);
593 amdgpu_ring_write(ring, PACKETJ(mmUVD_JRBC_RB_REF_DATA_INTERNAL_OFFSET,
594 0, 0, PACKETJ_TYPE0));
595 amdgpu_ring_write(ring, 0x2);
597 amdgpu_ring_write(ring, PACKETJ(mmUVD_JRBC_STATUS_INTERNAL_OFFSET,
598 0, PACKETJ_CONDITION_CHECK3, PACKETJ_TYPE3));
599 amdgpu_ring_write(ring, 0x2);
602 void jpeg_v2_0_dec_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,
603 uint32_t val, uint32_t mask)
605 uint32_t reg_offset = (reg << 2);
607 amdgpu_ring_write(ring, PACKETJ(mmUVD_JRBC_RB_COND_RD_TIMER_INTERNAL_OFFSET,
608 0, 0, PACKETJ_TYPE0));
609 amdgpu_ring_write(ring, 0x01400200);
611 amdgpu_ring_write(ring, PACKETJ(mmUVD_JRBC_RB_REF_DATA_INTERNAL_OFFSET,
612 0, 0, PACKETJ_TYPE0));
613 amdgpu_ring_write(ring, val);
615 amdgpu_ring_write(ring, PACKETJ(mmUVD_JRBC_EXTERNAL_REG_INTERNAL_OFFSET,
616 0, 0, PACKETJ_TYPE0));
617 if (reg_offset >= 0x10000 && reg_offset <= 0x105ff) {
618 amdgpu_ring_write(ring, 0);
619 amdgpu_ring_write(ring,
620 PACKETJ((reg_offset >> 2), 0, 0, PACKETJ_TYPE3));
622 amdgpu_ring_write(ring, reg_offset);
623 amdgpu_ring_write(ring, PACKETJ(JRBC_DEC_EXTERNAL_REG_WRITE_ADDR,
624 0, 0, PACKETJ_TYPE3));
626 amdgpu_ring_write(ring, mask);
629 void jpeg_v2_0_dec_ring_emit_vm_flush(struct amdgpu_ring *ring,
630 unsigned vmid, uint64_t pd_addr)
632 struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub];
633 uint32_t data0, data1, mask;
635 pd_addr = amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
637 /* wait for register write */
638 data0 = hub->ctx0_ptb_addr_lo32 + vmid * hub->ctx_addr_distance;
639 data1 = lower_32_bits(pd_addr);
641 jpeg_v2_0_dec_ring_emit_reg_wait(ring, data0, data1, mask);
644 void jpeg_v2_0_dec_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg, uint32_t val)
646 uint32_t reg_offset = (reg << 2);
648 amdgpu_ring_write(ring, PACKETJ(mmUVD_JRBC_EXTERNAL_REG_INTERNAL_OFFSET,
649 0, 0, PACKETJ_TYPE0));
650 if (reg_offset >= 0x10000 && reg_offset <= 0x105ff) {
651 amdgpu_ring_write(ring, 0);
652 amdgpu_ring_write(ring,
653 PACKETJ((reg_offset >> 2), 0, 0, PACKETJ_TYPE0));
655 amdgpu_ring_write(ring, reg_offset);
656 amdgpu_ring_write(ring, PACKETJ(JRBC_DEC_EXTERNAL_REG_WRITE_ADDR,
657 0, 0, PACKETJ_TYPE0));
659 amdgpu_ring_write(ring, val);
662 void jpeg_v2_0_dec_ring_nop(struct amdgpu_ring *ring, uint32_t count)
666 WARN_ON(ring->wptr % 2 || count % 2);
668 for (i = 0; i < count / 2; i++) {
669 amdgpu_ring_write(ring, PACKETJ(0, 0, 0, PACKETJ_TYPE6));
670 amdgpu_ring_write(ring, 0);
674 static bool jpeg_v2_0_is_idle(void *handle)
676 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
678 return ((RREG32_SOC15(JPEG, 0, mmUVD_JRBC_STATUS) &
679 UVD_JRBC_STATUS__RB_JOB_DONE_MASK) ==
680 UVD_JRBC_STATUS__RB_JOB_DONE_MASK);
683 static int jpeg_v2_0_wait_for_idle(void *handle)
685 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
688 ret = SOC15_WAIT_ON_RREG(JPEG, 0, mmUVD_JRBC_STATUS, UVD_JRBC_STATUS__RB_JOB_DONE_MASK,
689 UVD_JRBC_STATUS__RB_JOB_DONE_MASK);
694 static int jpeg_v2_0_set_clockgating_state(void *handle,
695 enum amd_clockgating_state state)
697 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
698 bool enable = (state == AMD_CG_STATE_GATE);
701 if (!jpeg_v2_0_is_idle(handle))
703 jpeg_v2_0_enable_clock_gating(adev);
705 jpeg_v2_0_disable_clock_gating(adev);
711 static int jpeg_v2_0_set_powergating_state(void *handle,
712 enum amd_powergating_state state)
714 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
717 if (state == adev->jpeg.cur_state)
720 if (state == AMD_PG_STATE_GATE)
721 ret = jpeg_v2_0_stop(adev);
723 ret = jpeg_v2_0_start(adev);
726 adev->jpeg.cur_state = state;
731 static int jpeg_v2_0_set_interrupt_state(struct amdgpu_device *adev,
732 struct amdgpu_irq_src *source,
734 enum amdgpu_interrupt_state state)
739 static int jpeg_v2_0_process_interrupt(struct amdgpu_device *adev,
740 struct amdgpu_irq_src *source,
741 struct amdgpu_iv_entry *entry)
743 DRM_DEBUG("IH: JPEG TRAP\n");
745 switch (entry->src_id) {
746 case VCN_2_0__SRCID__JPEG_DECODE:
747 amdgpu_fence_process(&adev->jpeg.inst->ring_dec);
750 DRM_ERROR("Unhandled interrupt: %d %d\n",
751 entry->src_id, entry->src_data[0]);
758 static const struct amd_ip_funcs jpeg_v2_0_ip_funcs = {
760 .early_init = jpeg_v2_0_early_init,
762 .sw_init = jpeg_v2_0_sw_init,
763 .sw_fini = jpeg_v2_0_sw_fini,
764 .hw_init = jpeg_v2_0_hw_init,
765 .hw_fini = jpeg_v2_0_hw_fini,
766 .suspend = jpeg_v2_0_suspend,
767 .resume = jpeg_v2_0_resume,
768 .is_idle = jpeg_v2_0_is_idle,
769 .wait_for_idle = jpeg_v2_0_wait_for_idle,
770 .check_soft_reset = NULL,
771 .pre_soft_reset = NULL,
773 .post_soft_reset = NULL,
774 .set_clockgating_state = jpeg_v2_0_set_clockgating_state,
775 .set_powergating_state = jpeg_v2_0_set_powergating_state,
778 static const struct amdgpu_ring_funcs jpeg_v2_0_dec_ring_vm_funcs = {
779 .type = AMDGPU_RING_TYPE_VCN_JPEG,
781 .vmhub = AMDGPU_MMHUB_0,
782 .get_rptr = jpeg_v2_0_dec_ring_get_rptr,
783 .get_wptr = jpeg_v2_0_dec_ring_get_wptr,
784 .set_wptr = jpeg_v2_0_dec_ring_set_wptr,
786 SOC15_FLUSH_GPU_TLB_NUM_WREG * 6 +
787 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 8 +
788 8 + /* jpeg_v2_0_dec_ring_emit_vm_flush */
789 18 + 18 + /* jpeg_v2_0_dec_ring_emit_fence x2 vm fence */
791 .emit_ib_size = 22, /* jpeg_v2_0_dec_ring_emit_ib */
792 .emit_ib = jpeg_v2_0_dec_ring_emit_ib,
793 .emit_fence = jpeg_v2_0_dec_ring_emit_fence,
794 .emit_vm_flush = jpeg_v2_0_dec_ring_emit_vm_flush,
795 .test_ring = amdgpu_jpeg_dec_ring_test_ring,
796 .test_ib = amdgpu_jpeg_dec_ring_test_ib,
797 .insert_nop = jpeg_v2_0_dec_ring_nop,
798 .insert_start = jpeg_v2_0_dec_ring_insert_start,
799 .insert_end = jpeg_v2_0_dec_ring_insert_end,
800 .pad_ib = amdgpu_ring_generic_pad_ib,
801 .begin_use = amdgpu_jpeg_ring_begin_use,
802 .end_use = amdgpu_jpeg_ring_end_use,
803 .emit_wreg = jpeg_v2_0_dec_ring_emit_wreg,
804 .emit_reg_wait = jpeg_v2_0_dec_ring_emit_reg_wait,
805 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,
808 static void jpeg_v2_0_set_dec_ring_funcs(struct amdgpu_device *adev)
810 adev->jpeg.inst->ring_dec.funcs = &jpeg_v2_0_dec_ring_vm_funcs;
811 DRM_INFO("JPEG decode is enabled in VM mode\n");
814 static const struct amdgpu_irq_src_funcs jpeg_v2_0_irq_funcs = {
815 .set = jpeg_v2_0_set_interrupt_state,
816 .process = jpeg_v2_0_process_interrupt,
819 static void jpeg_v2_0_set_irq_funcs(struct amdgpu_device *adev)
821 adev->jpeg.inst->irq.num_types = 1;
822 adev->jpeg.inst->irq.funcs = &jpeg_v2_0_irq_funcs;
825 const struct amdgpu_ip_block_version jpeg_v2_0_ip_block =
827 .type = AMD_IP_BLOCK_TYPE_JPEG,
831 .funcs = &jpeg_v2_0_ip_funcs,