Merge tag 'drm-misc-fixes-2020-08-12' of git://anongit.freedesktop.org/drm/drm-misc...
[linux-2.6-microblaze.git] / drivers / gpu / drm / amd / amdgpu / jpeg_v1_0.c
1 /*
2  * Copyright 2019 Advanced Micro Devices, Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  *
22  */
23
24 #include "amdgpu.h"
25 #include "amdgpu_jpeg.h"
26 #include "soc15.h"
27 #include "soc15d.h"
28 #include "vcn_v1_0.h"
29 #include "jpeg_v1_0.h"
30
31 #include "vcn/vcn_1_0_offset.h"
32 #include "vcn/vcn_1_0_sh_mask.h"
33
34 static void jpeg_v1_0_set_dec_ring_funcs(struct amdgpu_device *adev);
35 static void jpeg_v1_0_set_irq_funcs(struct amdgpu_device *adev);
36
37 static void jpeg_v1_0_decode_ring_patch_wreg(struct amdgpu_ring *ring, uint32_t *ptr, uint32_t reg_offset, uint32_t val)
38 {
39         struct amdgpu_device *adev = ring->adev;
40         ring->ring[(*ptr)++] = PACKETJ(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JRBC_EXTERNAL_REG_BASE), 0, 0, PACKETJ_TYPE0);
41         if (((reg_offset >= 0x1f800) && (reg_offset <= 0x21fff)) ||
42                 ((reg_offset >= 0x1e000) && (reg_offset <= 0x1e1ff))) {
43                 ring->ring[(*ptr)++] = 0;
44                 ring->ring[(*ptr)++] = PACKETJ((reg_offset >> 2), 0, 0, PACKETJ_TYPE0);
45         } else {
46                 ring->ring[(*ptr)++] = reg_offset;
47                 ring->ring[(*ptr)++] = PACKETJ(0, 0, 0, PACKETJ_TYPE0);
48         }
49         ring->ring[(*ptr)++] = val;
50 }
51
52 static void jpeg_v1_0_decode_ring_set_patch_ring(struct amdgpu_ring *ring, uint32_t ptr)
53 {
54         struct amdgpu_device *adev = ring->adev;
55
56         uint32_t reg, reg_offset, val, mask, i;
57
58         // 1st: program mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_LOW
59         reg = SOC15_REG_OFFSET(JPEG, 0, mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_LOW);
60         reg_offset = (reg << 2);
61         val = lower_32_bits(ring->gpu_addr);
62         jpeg_v1_0_decode_ring_patch_wreg(ring, &ptr, reg_offset, val);
63
64         // 2nd: program mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_HIGH
65         reg = SOC15_REG_OFFSET(JPEG, 0, mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_HIGH);
66         reg_offset = (reg << 2);
67         val = upper_32_bits(ring->gpu_addr);
68         jpeg_v1_0_decode_ring_patch_wreg(ring, &ptr, reg_offset, val);
69
70         // 3rd to 5th: issue MEM_READ commands
71         for (i = 0; i <= 2; i++) {
72                 ring->ring[ptr++] = PACKETJ(0, 0, 0, PACKETJ_TYPE2);
73                 ring->ring[ptr++] = 0;
74         }
75
76         // 6th: program mmUVD_JRBC_RB_CNTL register to enable NO_FETCH and RPTR write ability
77         reg = SOC15_REG_OFFSET(JPEG, 0, mmUVD_JRBC_RB_CNTL);
78         reg_offset = (reg << 2);
79         val = 0x13;
80         jpeg_v1_0_decode_ring_patch_wreg(ring, &ptr, reg_offset, val);
81
82         // 7th: program mmUVD_JRBC_RB_REF_DATA
83         reg = SOC15_REG_OFFSET(JPEG, 0, mmUVD_JRBC_RB_REF_DATA);
84         reg_offset = (reg << 2);
85         val = 0x1;
86         jpeg_v1_0_decode_ring_patch_wreg(ring, &ptr, reg_offset, val);
87
88         // 8th: issue conditional register read mmUVD_JRBC_RB_CNTL
89         reg = SOC15_REG_OFFSET(JPEG, 0, mmUVD_JRBC_RB_CNTL);
90         reg_offset = (reg << 2);
91         val = 0x1;
92         mask = 0x1;
93
94         ring->ring[ptr++] = PACKETJ(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JRBC_RB_COND_RD_TIMER), 0, 0, PACKETJ_TYPE0);
95         ring->ring[ptr++] = 0x01400200;
96         ring->ring[ptr++] = PACKETJ(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JRBC_RB_REF_DATA), 0, 0, PACKETJ_TYPE0);
97         ring->ring[ptr++] = val;
98         ring->ring[ptr++] = PACKETJ(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JRBC_EXTERNAL_REG_BASE), 0, 0, PACKETJ_TYPE0);
99         if (((reg_offset >= 0x1f800) && (reg_offset <= 0x21fff)) ||
100                 ((reg_offset >= 0x1e000) && (reg_offset <= 0x1e1ff))) {
101                 ring->ring[ptr++] = 0;
102                 ring->ring[ptr++] = PACKETJ((reg_offset >> 2), 0, 0, PACKETJ_TYPE3);
103         } else {
104                 ring->ring[ptr++] = reg_offset;
105                 ring->ring[ptr++] = PACKETJ(0, 0, 0, PACKETJ_TYPE3);
106         }
107         ring->ring[ptr++] = mask;
108
109         //9th to 21st: insert no-op
110         for (i = 0; i <= 12; i++) {
111                 ring->ring[ptr++] = PACKETJ(0, 0, 0, PACKETJ_TYPE6);
112                 ring->ring[ptr++] = 0;
113         }
114
115         //22nd: reset mmUVD_JRBC_RB_RPTR
116         reg = SOC15_REG_OFFSET(JPEG, 0, mmUVD_JRBC_RB_RPTR);
117         reg_offset = (reg << 2);
118         val = 0;
119         jpeg_v1_0_decode_ring_patch_wreg(ring, &ptr, reg_offset, val);
120
121         //23rd: program mmUVD_JRBC_RB_CNTL to disable no_fetch
122         reg = SOC15_REG_OFFSET(JPEG, 0, mmUVD_JRBC_RB_CNTL);
123         reg_offset = (reg << 2);
124         val = 0x12;
125         jpeg_v1_0_decode_ring_patch_wreg(ring, &ptr, reg_offset, val);
126 }
127
128 /**
129  * jpeg_v1_0_decode_ring_get_rptr - get read pointer
130  *
131  * @ring: amdgpu_ring pointer
132  *
133  * Returns the current hardware read pointer
134  */
135 static uint64_t jpeg_v1_0_decode_ring_get_rptr(struct amdgpu_ring *ring)
136 {
137         struct amdgpu_device *adev = ring->adev;
138
139         return RREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_RPTR);
140 }
141
142 /**
143  * jpeg_v1_0_decode_ring_get_wptr - get write pointer
144  *
145  * @ring: amdgpu_ring pointer
146  *
147  * Returns the current hardware write pointer
148  */
149 static uint64_t jpeg_v1_0_decode_ring_get_wptr(struct amdgpu_ring *ring)
150 {
151         struct amdgpu_device *adev = ring->adev;
152
153         return RREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_WPTR);
154 }
155
156 /**
157  * jpeg_v1_0_decode_ring_set_wptr - set write pointer
158  *
159  * @ring: amdgpu_ring pointer
160  *
161  * Commits the write pointer to the hardware
162  */
163 static void jpeg_v1_0_decode_ring_set_wptr(struct amdgpu_ring *ring)
164 {
165         struct amdgpu_device *adev = ring->adev;
166
167         WREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_WPTR, lower_32_bits(ring->wptr));
168 }
169
170 /**
171  * jpeg_v1_0_decode_ring_insert_start - insert a start command
172  *
173  * @ring: amdgpu_ring pointer
174  *
175  * Write a start command to the ring.
176  */
177 static void jpeg_v1_0_decode_ring_insert_start(struct amdgpu_ring *ring)
178 {
179         struct amdgpu_device *adev = ring->adev;
180
181         amdgpu_ring_write(ring,
182                 PACKETJ(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JRBC_EXTERNAL_REG_BASE), 0, 0, PACKETJ_TYPE0));
183         amdgpu_ring_write(ring, 0x68e04);
184
185         amdgpu_ring_write(ring, PACKETJ(0, 0, 0, PACKETJ_TYPE0));
186         amdgpu_ring_write(ring, 0x80010000);
187 }
188
189 /**
190  * jpeg_v1_0_decode_ring_insert_end - insert a end command
191  *
192  * @ring: amdgpu_ring pointer
193  *
194  * Write a end command to the ring.
195  */
196 static void jpeg_v1_0_decode_ring_insert_end(struct amdgpu_ring *ring)
197 {
198         struct amdgpu_device *adev = ring->adev;
199
200         amdgpu_ring_write(ring,
201                 PACKETJ(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JRBC_EXTERNAL_REG_BASE), 0, 0, PACKETJ_TYPE0));
202         amdgpu_ring_write(ring, 0x68e04);
203
204         amdgpu_ring_write(ring, PACKETJ(0, 0, 0, PACKETJ_TYPE0));
205         amdgpu_ring_write(ring, 0x00010000);
206 }
207
208 /**
209  * jpeg_v1_0_decode_ring_emit_fence - emit an fence & trap command
210  *
211  * @ring: amdgpu_ring pointer
212  * @fence: fence to emit
213  *
214  * Write a fence and a trap command to the ring.
215  */
216 static void jpeg_v1_0_decode_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
217                                      unsigned flags)
218 {
219         struct amdgpu_device *adev = ring->adev;
220
221         WARN_ON(flags & AMDGPU_FENCE_FLAG_64BIT);
222
223         amdgpu_ring_write(ring,
224                 PACKETJ(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JPEG_GPCOM_DATA0), 0, 0, PACKETJ_TYPE0));
225         amdgpu_ring_write(ring, seq);
226
227         amdgpu_ring_write(ring,
228                 PACKETJ(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JPEG_GPCOM_DATA1), 0, 0, PACKETJ_TYPE0));
229         amdgpu_ring_write(ring, seq);
230
231         amdgpu_ring_write(ring,
232                 PACKETJ(SOC15_REG_OFFSET(JPEG, 0, mmUVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_LOW), 0, 0, PACKETJ_TYPE0));
233         amdgpu_ring_write(ring, lower_32_bits(addr));
234
235         amdgpu_ring_write(ring,
236                 PACKETJ(SOC15_REG_OFFSET(JPEG, 0, mmUVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_HIGH), 0, 0, PACKETJ_TYPE0));
237         amdgpu_ring_write(ring, upper_32_bits(addr));
238
239         amdgpu_ring_write(ring,
240                 PACKETJ(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JPEG_GPCOM_CMD), 0, 0, PACKETJ_TYPE0));
241         amdgpu_ring_write(ring, 0x8);
242
243         amdgpu_ring_write(ring,
244                 PACKETJ(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JPEG_GPCOM_CMD), 0, PACKETJ_CONDITION_CHECK0, PACKETJ_TYPE4));
245         amdgpu_ring_write(ring, 0);
246
247         amdgpu_ring_write(ring,
248                 PACKETJ(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JRBC_RB_COND_RD_TIMER), 0, 0, PACKETJ_TYPE0));
249         amdgpu_ring_write(ring, 0x01400200);
250
251         amdgpu_ring_write(ring,
252                 PACKETJ(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JRBC_RB_REF_DATA), 0, 0, PACKETJ_TYPE0));
253         amdgpu_ring_write(ring, seq);
254
255         amdgpu_ring_write(ring,
256                 PACKETJ(SOC15_REG_OFFSET(JPEG, 0, mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_LOW), 0, 0, PACKETJ_TYPE0));
257         amdgpu_ring_write(ring, lower_32_bits(addr));
258
259         amdgpu_ring_write(ring,
260                 PACKETJ(SOC15_REG_OFFSET(JPEG, 0, mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_HIGH), 0, 0, PACKETJ_TYPE0));
261         amdgpu_ring_write(ring, upper_32_bits(addr));
262
263         amdgpu_ring_write(ring,
264                 PACKETJ(0, 0, PACKETJ_CONDITION_CHECK3, PACKETJ_TYPE2));
265         amdgpu_ring_write(ring, 0xffffffff);
266
267         amdgpu_ring_write(ring,
268                 PACKETJ(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JRBC_EXTERNAL_REG_BASE), 0, 0, PACKETJ_TYPE0));
269         amdgpu_ring_write(ring, 0x3fbc);
270
271         amdgpu_ring_write(ring,
272                 PACKETJ(0, 0, 0, PACKETJ_TYPE0));
273         amdgpu_ring_write(ring, 0x1);
274
275         /* emit trap */
276         amdgpu_ring_write(ring, PACKETJ(0, 0, 0, PACKETJ_TYPE7));
277         amdgpu_ring_write(ring, 0);
278 }
279
280 /**
281  * jpeg_v1_0_decode_ring_emit_ib - execute indirect buffer
282  *
283  * @ring: amdgpu_ring pointer
284  * @ib: indirect buffer to execute
285  *
286  * Write ring commands to execute the indirect buffer.
287  */
288 static void jpeg_v1_0_decode_ring_emit_ib(struct amdgpu_ring *ring,
289                                         struct amdgpu_job *job,
290                                         struct amdgpu_ib *ib,
291                                         uint32_t flags)
292 {
293         struct amdgpu_device *adev = ring->adev;
294         unsigned vmid = AMDGPU_JOB_GET_VMID(job);
295
296         amdgpu_ring_write(ring,
297                 PACKETJ(SOC15_REG_OFFSET(JPEG, 0, mmUVD_LMI_JRBC_IB_VMID), 0, 0, PACKETJ_TYPE0));
298         amdgpu_ring_write(ring, (vmid | (vmid << 4)));
299
300         amdgpu_ring_write(ring,
301                 PACKETJ(SOC15_REG_OFFSET(JPEG, 0, mmUVD_LMI_JPEG_VMID), 0, 0, PACKETJ_TYPE0));
302         amdgpu_ring_write(ring, (vmid | (vmid << 4)));
303
304         amdgpu_ring_write(ring,
305                 PACKETJ(SOC15_REG_OFFSET(JPEG, 0, mmUVD_LMI_JRBC_IB_64BIT_BAR_LOW), 0, 0, PACKETJ_TYPE0));
306         amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr));
307
308         amdgpu_ring_write(ring,
309                 PACKETJ(SOC15_REG_OFFSET(JPEG, 0, mmUVD_LMI_JRBC_IB_64BIT_BAR_HIGH), 0, 0, PACKETJ_TYPE0));
310         amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
311
312         amdgpu_ring_write(ring,
313                 PACKETJ(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JRBC_IB_SIZE), 0, 0, PACKETJ_TYPE0));
314         amdgpu_ring_write(ring, ib->length_dw);
315
316         amdgpu_ring_write(ring,
317                 PACKETJ(SOC15_REG_OFFSET(JPEG, 0, mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_LOW), 0, 0, PACKETJ_TYPE0));
318         amdgpu_ring_write(ring, lower_32_bits(ring->gpu_addr));
319
320         amdgpu_ring_write(ring,
321                 PACKETJ(SOC15_REG_OFFSET(JPEG, 0, mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_HIGH), 0, 0, PACKETJ_TYPE0));
322         amdgpu_ring_write(ring, upper_32_bits(ring->gpu_addr));
323
324         amdgpu_ring_write(ring,
325                 PACKETJ(0, 0, PACKETJ_CONDITION_CHECK0, PACKETJ_TYPE2));
326         amdgpu_ring_write(ring, 0);
327
328         amdgpu_ring_write(ring,
329                 PACKETJ(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JRBC_RB_COND_RD_TIMER), 0, 0, PACKETJ_TYPE0));
330         amdgpu_ring_write(ring, 0x01400200);
331
332         amdgpu_ring_write(ring,
333                 PACKETJ(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JRBC_RB_REF_DATA), 0, 0, PACKETJ_TYPE0));
334         amdgpu_ring_write(ring, 0x2);
335
336         amdgpu_ring_write(ring,
337                 PACKETJ(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JRBC_STATUS), 0, PACKETJ_CONDITION_CHECK3, PACKETJ_TYPE3));
338         amdgpu_ring_write(ring, 0x2);
339 }
340
341 static void jpeg_v1_0_decode_ring_emit_reg_wait(struct amdgpu_ring *ring,
342                                             uint32_t reg, uint32_t val,
343                                             uint32_t mask)
344 {
345         struct amdgpu_device *adev = ring->adev;
346         uint32_t reg_offset = (reg << 2);
347
348         amdgpu_ring_write(ring,
349                 PACKETJ(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JRBC_RB_COND_RD_TIMER), 0, 0, PACKETJ_TYPE0));
350         amdgpu_ring_write(ring, 0x01400200);
351
352         amdgpu_ring_write(ring,
353                 PACKETJ(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JRBC_RB_REF_DATA), 0, 0, PACKETJ_TYPE0));
354         amdgpu_ring_write(ring, val);
355
356         amdgpu_ring_write(ring,
357                 PACKETJ(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JRBC_EXTERNAL_REG_BASE), 0, 0, PACKETJ_TYPE0));
358         if (((reg_offset >= 0x1f800) && (reg_offset <= 0x21fff)) ||
359                 ((reg_offset >= 0x1e000) && (reg_offset <= 0x1e1ff))) {
360                 amdgpu_ring_write(ring, 0);
361                 amdgpu_ring_write(ring,
362                         PACKETJ((reg_offset >> 2), 0, 0, PACKETJ_TYPE3));
363         } else {
364                 amdgpu_ring_write(ring, reg_offset);
365                 amdgpu_ring_write(ring,
366                         PACKETJ(0, 0, 0, PACKETJ_TYPE3));
367         }
368         amdgpu_ring_write(ring, mask);
369 }
370
371 static void jpeg_v1_0_decode_ring_emit_vm_flush(struct amdgpu_ring *ring,
372                 unsigned vmid, uint64_t pd_addr)
373 {
374         struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub];
375         uint32_t data0, data1, mask;
376
377         pd_addr = amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
378
379         /* wait for register write */
380         data0 = hub->ctx0_ptb_addr_lo32 + vmid * hub->ctx_addr_distance;
381         data1 = lower_32_bits(pd_addr);
382         mask = 0xffffffff;
383         jpeg_v1_0_decode_ring_emit_reg_wait(ring, data0, data1, mask);
384 }
385
386 static void jpeg_v1_0_decode_ring_emit_wreg(struct amdgpu_ring *ring,
387                                         uint32_t reg, uint32_t val)
388 {
389         struct amdgpu_device *adev = ring->adev;
390         uint32_t reg_offset = (reg << 2);
391
392         amdgpu_ring_write(ring,
393                 PACKETJ(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JRBC_EXTERNAL_REG_BASE), 0, 0, PACKETJ_TYPE0));
394         if (((reg_offset >= 0x1f800) && (reg_offset <= 0x21fff)) ||
395                         ((reg_offset >= 0x1e000) && (reg_offset <= 0x1e1ff))) {
396                 amdgpu_ring_write(ring, 0);
397                 amdgpu_ring_write(ring,
398                         PACKETJ((reg_offset >> 2), 0, 0, PACKETJ_TYPE0));
399         } else {
400                 amdgpu_ring_write(ring, reg_offset);
401                 amdgpu_ring_write(ring,
402                         PACKETJ(0, 0, 0, PACKETJ_TYPE0));
403         }
404         amdgpu_ring_write(ring, val);
405 }
406
407 static void jpeg_v1_0_decode_ring_nop(struct amdgpu_ring *ring, uint32_t count)
408 {
409         int i;
410
411         WARN_ON(ring->wptr % 2 || count % 2);
412
413         for (i = 0; i < count / 2; i++) {
414                 amdgpu_ring_write(ring, PACKETJ(0, 0, 0, PACKETJ_TYPE6));
415                 amdgpu_ring_write(ring, 0);
416         }
417 }
418
419 static int jpeg_v1_0_set_interrupt_state(struct amdgpu_device *adev,
420                                         struct amdgpu_irq_src *source,
421                                         unsigned type,
422                                         enum amdgpu_interrupt_state state)
423 {
424         return 0;
425 }
426
427 static int jpeg_v1_0_process_interrupt(struct amdgpu_device *adev,
428                                       struct amdgpu_irq_src *source,
429                                       struct amdgpu_iv_entry *entry)
430 {
431         DRM_DEBUG("IH: JPEG decode TRAP\n");
432
433         switch (entry->src_id) {
434         case 126:
435                 amdgpu_fence_process(&adev->jpeg.inst->ring_dec);
436                 break;
437         default:
438                 DRM_ERROR("Unhandled interrupt: %d %d\n",
439                           entry->src_id, entry->src_data[0]);
440                 break;
441         }
442
443         return 0;
444 }
445
446 /**
447  * jpeg_v1_0_early_init - set function pointers
448  *
449  * @handle: amdgpu_device pointer
450  *
451  * Set ring and irq function pointers
452  */
453 int jpeg_v1_0_early_init(void *handle)
454 {
455         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
456
457         adev->jpeg.num_jpeg_inst = 1;
458
459         jpeg_v1_0_set_dec_ring_funcs(adev);
460         jpeg_v1_0_set_irq_funcs(adev);
461
462         return 0;
463 }
464
465 /**
466  * jpeg_v1_0_sw_init - sw init for JPEG block
467  *
468  * @handle: amdgpu_device pointer
469  *
470  */
471 int jpeg_v1_0_sw_init(void *handle)
472 {
473         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
474         struct amdgpu_ring *ring;
475         int r;
476
477         /* JPEG TRAP */
478         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VCN, 126, &adev->jpeg.inst->irq);
479         if (r)
480                 return r;
481
482         ring = &adev->jpeg.inst->ring_dec;
483         sprintf(ring->name, "jpeg_dec");
484         r = amdgpu_ring_init(adev, ring, 512, &adev->jpeg.inst->irq,
485                              0, AMDGPU_RING_PRIO_DEFAULT);
486         if (r)
487                 return r;
488
489         adev->jpeg.internal.jpeg_pitch = adev->jpeg.inst->external.jpeg_pitch =
490                 SOC15_REG_OFFSET(JPEG, 0, mmUVD_JPEG_PITCH);
491
492         return 0;
493 }
494
495 /**
496  * jpeg_v1_0_sw_fini - sw fini for JPEG block
497  *
498  * @handle: amdgpu_device pointer
499  *
500  * JPEG free up sw allocation
501  */
502 void jpeg_v1_0_sw_fini(void *handle)
503 {
504         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
505
506         amdgpu_ring_fini(&adev->jpeg.inst[0].ring_dec);
507 }
508
509 /**
510  * jpeg_v1_0_start - start JPEG block
511  *
512  * @adev: amdgpu_device pointer
513  *
514  * Setup and start the JPEG block
515  */
516 void jpeg_v1_0_start(struct amdgpu_device *adev, int mode)
517 {
518         struct amdgpu_ring *ring = &adev->jpeg.inst->ring_dec;
519
520         if (mode == 0) {
521                 WREG32_SOC15(JPEG, 0, mmUVD_LMI_JRBC_RB_VMID, 0);
522                 WREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_CNTL, UVD_JRBC_RB_CNTL__RB_NO_FETCH_MASK |
523                                 UVD_JRBC_RB_CNTL__RB_RPTR_WR_EN_MASK);
524                 WREG32_SOC15(JPEG, 0, mmUVD_LMI_JRBC_RB_64BIT_BAR_LOW, lower_32_bits(ring->gpu_addr));
525                 WREG32_SOC15(JPEG, 0, mmUVD_LMI_JRBC_RB_64BIT_BAR_HIGH, upper_32_bits(ring->gpu_addr));
526                 WREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_RPTR, 0);
527                 WREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_WPTR, 0);
528                 WREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_CNTL, UVD_JRBC_RB_CNTL__RB_RPTR_WR_EN_MASK);
529         }
530
531         /* initialize wptr */
532         ring->wptr = RREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_WPTR);
533
534         /* copy patch commands to the jpeg ring */
535         jpeg_v1_0_decode_ring_set_patch_ring(ring,
536                 (ring->wptr + ring->max_dw * amdgpu_sched_hw_submission));
537 }
538
539 static const struct amdgpu_ring_funcs jpeg_v1_0_decode_ring_vm_funcs = {
540         .type = AMDGPU_RING_TYPE_VCN_JPEG,
541         .align_mask = 0xf,
542         .nop = PACKET0(0x81ff, 0),
543         .support_64bit_ptrs = false,
544         .no_user_fence = true,
545         .vmhub = AMDGPU_MMHUB_0,
546         .extra_dw = 64,
547         .get_rptr = jpeg_v1_0_decode_ring_get_rptr,
548         .get_wptr = jpeg_v1_0_decode_ring_get_wptr,
549         .set_wptr = jpeg_v1_0_decode_ring_set_wptr,
550         .emit_frame_size =
551                 6 + 6 + /* hdp invalidate / flush */
552                 SOC15_FLUSH_GPU_TLB_NUM_WREG * 6 +
553                 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 8 +
554                 8 + /* jpeg_v1_0_decode_ring_emit_vm_flush */
555                 26 + 26 + /* jpeg_v1_0_decode_ring_emit_fence x2 vm fence */
556                 6,
557         .emit_ib_size = 22, /* jpeg_v1_0_decode_ring_emit_ib */
558         .emit_ib = jpeg_v1_0_decode_ring_emit_ib,
559         .emit_fence = jpeg_v1_0_decode_ring_emit_fence,
560         .emit_vm_flush = jpeg_v1_0_decode_ring_emit_vm_flush,
561         .test_ring = amdgpu_jpeg_dec_ring_test_ring,
562         .test_ib = amdgpu_jpeg_dec_ring_test_ib,
563         .insert_nop = jpeg_v1_0_decode_ring_nop,
564         .insert_start = jpeg_v1_0_decode_ring_insert_start,
565         .insert_end = jpeg_v1_0_decode_ring_insert_end,
566         .pad_ib = amdgpu_ring_generic_pad_ib,
567         .begin_use = vcn_v1_0_ring_begin_use,
568         .end_use = amdgpu_vcn_ring_end_use,
569         .emit_wreg = jpeg_v1_0_decode_ring_emit_wreg,
570         .emit_reg_wait = jpeg_v1_0_decode_ring_emit_reg_wait,
571         .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,
572 };
573
574 static void jpeg_v1_0_set_dec_ring_funcs(struct amdgpu_device *adev)
575 {
576         adev->jpeg.inst->ring_dec.funcs = &jpeg_v1_0_decode_ring_vm_funcs;
577         DRM_INFO("JPEG decode is enabled in VM mode\n");
578 }
579
580 static const struct amdgpu_irq_src_funcs jpeg_v1_0_irq_funcs = {
581         .set = jpeg_v1_0_set_interrupt_state,
582         .process = jpeg_v1_0_process_interrupt,
583 };
584
585 static void jpeg_v1_0_set_irq_funcs(struct amdgpu_device *adev)
586 {
587         adev->jpeg.inst->irq.funcs = &jpeg_v1_0_irq_funcs;
588 }