drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c

   1 /*
   2  * Copyright 2016 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #include <linux/firmware.h>
  25 #include <linux/pci.h>
  26
  27 #include <drm/drm_cache.h>
  28
  29 #include "amdgpu.h"
  30 #include "gmc_v9_0.h"
  31 #include "amdgpu_atomfirmware.h"
  32 #include "amdgpu_gem.h"
  33
  34 #include "hdp/hdp_4_0_offset.h"
  35 #include "hdp/hdp_4_0_sh_mask.h"
  36 #include "gc/gc_9_0_sh_mask.h"
  37 #include "dce/dce_12_0_offset.h"
  38 #include "dce/dce_12_0_sh_mask.h"
  39 #include "vega10_enum.h"
  40 #include "mmhub/mmhub_1_0_offset.h"
  41 #include "athub/athub_1_0_offset.h"
  42 #include "oss/osssys_4_0_offset.h"
  43
  44 #include "soc15.h"
  45 #include "soc15_common.h"
  46 #include "umc/umc_6_0_sh_mask.h"
  47
  48 #include "gfxhub_v1_0.h"
  49 #include "mmhub_v1_0.h"
  50 #include "gfxhub_v1_1.h"
  51
  52 #include "ivsrcid/vmc/irqsrcs_vmc_1_0.h"
  53
  54 #include "amdgpu_ras.h"
  55
  56 /* add these here since we already include dce12 headers and these are for DCN */
  57 #define mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION                                                          0x055d
  58 #define mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_BASE_IDX                                                 2
  59 #define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_WIDTH__SHIFT                                        0x0
  60 #define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_HEIGHT__SHIFT                                       0x10
  61 #define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_WIDTH_MASK                                          0x00003FFFL
  62 #define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_HEIGHT_MASK                                         0x3FFF0000L
  63
  64 /* XXX Move this macro to VEGA10 header file, which is like vid.h for VI.*/
  65 #define AMDGPU_NUM_OF_VMIDS                     8
  66
  67 static const u32 golden_settings_vega10_hdp[] =
  68 {
  69         0xf64, 0x0fffffff, 0x00000000,
  70         0xf65, 0x0fffffff, 0x00000000,
  71         0xf66, 0x0fffffff, 0x00000000,
  72         0xf67, 0x0fffffff, 0x00000000,
  73         0xf68, 0x0fffffff, 0x00000000,
  74         0xf6a, 0x0fffffff, 0x00000000,
  75         0xf6b, 0x0fffffff, 0x00000000,
  76         0xf6c, 0x0fffffff, 0x00000000,
  77         0xf6d, 0x0fffffff, 0x00000000,
  78         0xf6e, 0x0fffffff, 0x00000000,
  79 };
  80
  81 static const struct soc15_reg_golden golden_settings_mmhub_1_0_0[] =
  82 {
  83         SOC15_REG_GOLDEN_VALUE(MMHUB, 0, mmDAGB1_WRCLI2, 0x00000007, 0xfe5fe0fa),
  84         SOC15_REG_GOLDEN_VALUE(MMHUB, 0, mmMMEA1_DRAM_WR_CLI2GRP_MAP0, 0x00000030, 0x55555565)
  85 };
  86
  87 static const struct soc15_reg_golden golden_settings_athub_1_0_0[] =
  88 {
  89         SOC15_REG_GOLDEN_VALUE(ATHUB, 0, mmRPB_ARB_CNTL, 0x0000ff00, 0x00000800),
  90         SOC15_REG_GOLDEN_VALUE(ATHUB, 0, mmRPB_ARB_CNTL2, 0x00ff00ff, 0x00080008)
  91 };
  92
  93 static const uint32_t ecc_umc_mcumc_ctrl_addrs[] = {
  94         (0x000143c0 + 0x00000000),
  95         (0x000143c0 + 0x00000800),
  96         (0x000143c0 + 0x00001000),
  97         (0x000143c0 + 0x00001800),
  98         (0x000543c0 + 0x00000000),
  99         (0x000543c0 + 0x00000800),
 100         (0x000543c0 + 0x00001000),
 101         (0x000543c0 + 0x00001800),
 102         (0x000943c0 + 0x00000000),
 103         (0x000943c0 + 0x00000800),
 104         (0x000943c0 + 0x00001000),
 105         (0x000943c0 + 0x00001800),
 106         (0x000d43c0 + 0x00000000),
 107         (0x000d43c0 + 0x00000800),
 108         (0x000d43c0 + 0x00001000),
 109         (0x000d43c0 + 0x00001800),
 110         (0x001143c0 + 0x00000000),
 111         (0x001143c0 + 0x00000800),
 112         (0x001143c0 + 0x00001000),
 113         (0x001143c0 + 0x00001800),
 114         (0x001543c0 + 0x00000000),
 115         (0x001543c0 + 0x00000800),
 116         (0x001543c0 + 0x00001000),
 117         (0x001543c0 + 0x00001800),
 118         (0x001943c0 + 0x00000000),
 119         (0x001943c0 + 0x00000800),
 120         (0x001943c0 + 0x00001000),
 121         (0x001943c0 + 0x00001800),
 122         (0x001d43c0 + 0x00000000),
 123         (0x001d43c0 + 0x00000800),
 124         (0x001d43c0 + 0x00001000),
 125         (0x001d43c0 + 0x00001800),
 126 };
 127
 128 static const uint32_t ecc_umc_mcumc_ctrl_mask_addrs[] = {
 129         (0x000143e0 + 0x00000000),
 130         (0x000143e0 + 0x00000800),
 131         (0x000143e0 + 0x00001000),
 132         (0x000143e0 + 0x00001800),
 133         (0x000543e0 + 0x00000000),
 134         (0x000543e0 + 0x00000800),
 135         (0x000543e0 + 0x00001000),
 136         (0x000543e0 + 0x00001800),
 137         (0x000943e0 + 0x00000000),
 138         (0x000943e0 + 0x00000800),
 139         (0x000943e0 + 0x00001000),
 140         (0x000943e0 + 0x00001800),
 141         (0x000d43e0 + 0x00000000),
 142         (0x000d43e0 + 0x00000800),
 143         (0x000d43e0 + 0x00001000),
 144         (0x000d43e0 + 0x00001800),
 145         (0x001143e0 + 0x00000000),
 146         (0x001143e0 + 0x00000800),
 147         (0x001143e0 + 0x00001000),
 148         (0x001143e0 + 0x00001800),
 149         (0x001543e0 + 0x00000000),
 150         (0x001543e0 + 0x00000800),
 151         (0x001543e0 + 0x00001000),
 152         (0x001543e0 + 0x00001800),
 153         (0x001943e0 + 0x00000000),
 154         (0x001943e0 + 0x00000800),
 155         (0x001943e0 + 0x00001000),
 156         (0x001943e0 + 0x00001800),
 157         (0x001d43e0 + 0x00000000),
 158         (0x001d43e0 + 0x00000800),
 159         (0x001d43e0 + 0x00001000),
 160         (0x001d43e0 + 0x00001800),
 161 };
 162
 163 static const uint32_t ecc_umc_mcumc_status_addrs[] = {
 164         (0x000143c2 + 0x00000000),
 165         (0x000143c2 + 0x00000800),
 166         (0x000143c2 + 0x00001000),
 167         (0x000143c2 + 0x00001800),
 168         (0x000543c2 + 0x00000000),
 169         (0x000543c2 + 0x00000800),
 170         (0x000543c2 + 0x00001000),
 171         (0x000543c2 + 0x00001800),
 172         (0x000943c2 + 0x00000000),
 173         (0x000943c2 + 0x00000800),
 174         (0x000943c2 + 0x00001000),
 175         (0x000943c2 + 0x00001800),
 176         (0x000d43c2 + 0x00000000),
 177         (0x000d43c2 + 0x00000800),
 178         (0x000d43c2 + 0x00001000),
 179         (0x000d43c2 + 0x00001800),
 180         (0x001143c2 + 0x00000000),
 181         (0x001143c2 + 0x00000800),
 182         (0x001143c2 + 0x00001000),
 183         (0x001143c2 + 0x00001800),
 184         (0x001543c2 + 0x00000000),
 185         (0x001543c2 + 0x00000800),
 186         (0x001543c2 + 0x00001000),
 187         (0x001543c2 + 0x00001800),
 188         (0x001943c2 + 0x00000000),
 189         (0x001943c2 + 0x00000800),
 190         (0x001943c2 + 0x00001000),
 191         (0x001943c2 + 0x00001800),
 192         (0x001d43c2 + 0x00000000),
 193         (0x001d43c2 + 0x00000800),
 194         (0x001d43c2 + 0x00001000),
 195         (0x001d43c2 + 0x00001800),
 196 };
 197
 198 static int gmc_v9_0_ecc_interrupt_state(struct amdgpu_device *adev,
 199                 struct amdgpu_irq_src *src,
 200                 unsigned type,
 201                 enum amdgpu_interrupt_state state)
 202 {
 203         u32 bits, i, tmp, reg;
 204
 205         bits = 0x7f;
 206
 207         switch (state) {
 208         case AMDGPU_IRQ_STATE_DISABLE:
 209                 for (i = 0; i < ARRAY_SIZE(ecc_umc_mcumc_ctrl_addrs); i++) {
 210                         reg = ecc_umc_mcumc_ctrl_addrs[i];
 211                         tmp = RREG32(reg);
 212                         tmp &= ~bits;
 213                         WREG32(reg, tmp);
 214                 }
 215                 for (i = 0; i < ARRAY_SIZE(ecc_umc_mcumc_ctrl_mask_addrs); i++) {
 216                         reg = ecc_umc_mcumc_ctrl_mask_addrs[i];
 217                         tmp = RREG32(reg);
 218                         tmp &= ~bits;
 219                         WREG32(reg, tmp);
 220                 }
 221                 break;
 222         case AMDGPU_IRQ_STATE_ENABLE:
 223                 for (i = 0; i < ARRAY_SIZE(ecc_umc_mcumc_ctrl_addrs); i++) {
 224                         reg = ecc_umc_mcumc_ctrl_addrs[i];
 225                         tmp = RREG32(reg);
 226                         tmp |= bits;
 227                         WREG32(reg, tmp);
 228                 }
 229                 for (i = 0; i < ARRAY_SIZE(ecc_umc_mcumc_ctrl_mask_addrs); i++) {
 230                         reg = ecc_umc_mcumc_ctrl_mask_addrs[i];
 231                         tmp = RREG32(reg);
 232                         tmp |= bits;
 233                         WREG32(reg, tmp);
 234                 }
 235                 break;
 236         default:
 237                 break;
 238         }
 239
 240         return 0;
 241 }
 242
 243 static int gmc_v9_0_process_ras_data_cb(struct amdgpu_device *adev,
 244                 struct amdgpu_iv_entry *entry)
 245 {
 246         kgd2kfd_set_sram_ecc_flag(adev->kfd.dev);
 247         amdgpu_ras_reset_gpu(adev, 0);
 248         return AMDGPU_RAS_UE;
 249 }
 250
 251 static int gmc_v9_0_process_ecc_irq(struct amdgpu_device *adev,
 252                 struct amdgpu_irq_src *source,
 253                 struct amdgpu_iv_entry *entry)
 254 {
 255         struct ras_common_if *ras_if = adev->gmc.ras_if;
 256         struct ras_dispatch_if ih_data = {
 257                 .entry = entry,
 258         };
 259
 260         if (!ras_if)
 261                 return 0;
 262
 263         ih_data.head = *ras_if;
 264
 265         amdgpu_ras_interrupt_dispatch(adev, &ih_data);
 266         return 0;
 267 }
 268
 269 static int gmc_v9_0_vm_fault_interrupt_state(struct amdgpu_device *adev,
 270                                         struct amdgpu_irq_src *src,
 271                                         unsigned type,
 272                                         enum amdgpu_interrupt_state state)
 273 {
 274         struct amdgpu_vmhub *hub;
 275         u32 tmp, reg, bits, i, j;
 276
 277         bits = VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
 278                 VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
 279                 VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
 280                 VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
 281                 VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
 282                 VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
 283                 VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK;
 284
 285         switch (state) {
 286         case AMDGPU_IRQ_STATE_DISABLE:
 287                 for (j = 0; j < adev->num_vmhubs; j++) {
 288                         hub = &adev->vmhub[j];
 289                         for (i = 0; i < 16; i++) {
 290                                 reg = hub->vm_context0_cntl + i;
 291                                 tmp = RREG32(reg);
 292                                 tmp &= ~bits;
 293                                 WREG32(reg, tmp);
 294                         }
 295                 }
 296                 break;
 297         case AMDGPU_IRQ_STATE_ENABLE:
 298                 for (j = 0; j < adev->num_vmhubs; j++) {
 299                         hub = &adev->vmhub[j];
 300                         for (i = 0; i < 16; i++) {
 301                                 reg = hub->vm_context0_cntl + i;
 302                                 tmp = RREG32(reg);
 303                                 tmp |= bits;
 304                                 WREG32(reg, tmp);
 305                         }
 306                 }
 307         default:
 308                 break;
 309         }
 310
 311         return 0;
 312 }
 313
 314 static int gmc_v9_0_process_interrupt(struct amdgpu_device *adev,
 315                                 struct amdgpu_irq_src *source,
 316                                 struct amdgpu_iv_entry *entry)
 317 {
 318         struct amdgpu_vmhub *hub = &adev->vmhub[entry->vmid_src];
 319         bool retry_fault = !!(entry->src_data[1] & 0x80);
 320         uint32_t status = 0;
 321         u64 addr;
 322
 323         addr = (u64)entry->src_data[0] << 12;
 324         addr |= ((u64)entry->src_data[1] & 0xf) << 44;
 325
 326         if (retry_fault && amdgpu_gmc_filter_faults(adev, addr, entry->pasid,
 327                                                     entry->timestamp))
 328                 return 1; /* This also prevents sending it to KFD */
 329
 330         /* If it's the first fault for this address, process it normally */
 331         if (!amdgpu_sriov_vf(adev)) {
 332                 status = RREG32(hub->vm_l2_pro_fault_status);
 333                 WREG32_P(hub->vm_l2_pro_fault_cntl, 1, ~1);
 334         }
 335
 336         if (printk_ratelimit()) {
 337                 struct amdgpu_task_info task_info;
 338
 339                 memset(&task_info, 0, sizeof(struct amdgpu_task_info));
 340                 amdgpu_vm_get_task_info(adev, entry->pasid, &task_info);
 341
 342                 dev_err(adev->dev,
 343                         "[%s] %s page fault (src_id:%u ring:%u vmid:%u "
 344                         "pasid:%u, for process %s pid %d thread %s pid %d)\n",
 345                         entry->vmid_src ? "mmhub" : "gfxhub",
 346                         retry_fault ? "retry" : "no-retry",
 347                         entry->src_id, entry->ring_id, entry->vmid,
 348                         entry->pasid, task_info.process_name, task_info.tgid,
 349                         task_info.task_name, task_info.pid);
 350                 dev_err(adev->dev, "  in page starting at address 0x%016llx from %d\n",
 351                         addr, entry->client_id);
 352                 if (!amdgpu_sriov_vf(adev))
 353                         dev_err(adev->dev,
 354                                 "VM_L2_PROTECTION_FAULT_STATUS:0x%08X\n",
 355                                 status);
 356         }
 357
 358         return 0;
 359 }
 360
 361 static const struct amdgpu_irq_src_funcs gmc_v9_0_irq_funcs = {
 362         .set = gmc_v9_0_vm_fault_interrupt_state,
 363         .process = gmc_v9_0_process_interrupt,
 364 };
 365
 366
 367 static const struct amdgpu_irq_src_funcs gmc_v9_0_ecc_funcs = {
 368         .set = gmc_v9_0_ecc_interrupt_state,
 369         .process = gmc_v9_0_process_ecc_irq,
 370 };
 371
 372 static void gmc_v9_0_set_irq_funcs(struct amdgpu_device *adev)
 373 {
 374         adev->gmc.vm_fault.num_types = 1;
 375         adev->gmc.vm_fault.funcs = &gmc_v9_0_irq_funcs;
 376
 377         adev->gmc.ecc_irq.num_types = 1;
 378         adev->gmc.ecc_irq.funcs = &gmc_v9_0_ecc_funcs;
 379 }
 380
 381 static uint32_t gmc_v9_0_get_invalidate_req(unsigned int vmid,
 382                                         uint32_t flush_type)
 383 {
 384         u32 req = 0;
 385
 386         req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ,
 387                             PER_VMID_INVALIDATE_REQ, 1 << vmid);
 388         req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, FLUSH_TYPE, flush_type);
 389         req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PTES, 1);
 390         req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE0, 1);
 391         req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE1, 1);
 392         req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE2, 1);
 393         req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L1_PTES, 1);
 394         req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ,
 395                             CLEAR_PROTECTION_FAULT_STATUS_ADDR, 0);
 396
 397         return req;
 398 }
 399
 400 /*
 401  * GART
 402  * VMID 0 is the physical GPU addresses as used by the kernel.
 403  * VMIDs 1-15 are used for userspace clients and are handled
 404  * by the amdgpu vm/hsa code.
 405  */
 406
 407 /**
 408  * gmc_v9_0_flush_gpu_tlb - tlb flush with certain type
 409  *
 410  * @adev: amdgpu_device pointer
 411  * @vmid: vm instance to flush
 412  * @flush_type: the flush type
 413  *
 414  * Flush the TLB for the requested page table using certain type.
 415  */
 416 static void gmc_v9_0_flush_gpu_tlb(struct amdgpu_device *adev,
 417                                 uint32_t vmid, uint32_t flush_type)
 418 {
 419         const unsigned eng = 17;
 420         unsigned i, j;
 421
 422         for (i = 0; i < adev->num_vmhubs; ++i) {
 423                 struct amdgpu_vmhub *hub = &adev->vmhub[i];
 424                 u32 tmp = gmc_v9_0_get_invalidate_req(vmid, flush_type);
 425
 426                 /* This is necessary for a HW workaround under SRIOV as well
 427                  * as GFXOFF under bare metal
 428                  */
 429                 if (adev->gfx.kiq.ring.sched.ready &&
 430                     (amdgpu_sriov_runtime(adev) || !amdgpu_sriov_vf(adev)) &&
 431                     !adev->in_gpu_reset) {
 432                         uint32_t req = hub->vm_inv_eng0_req + eng;
 433                         uint32_t ack = hub->vm_inv_eng0_ack + eng;
 434
 435                         amdgpu_virt_kiq_reg_write_reg_wait(adev, req, ack, tmp,
 436                                                            1 << vmid);
 437                         continue;
 438                 }
 439
 440                 spin_lock(&adev->gmc.invalidate_lock);
 441                 WREG32_NO_KIQ(hub->vm_inv_eng0_req + eng, tmp);
 442                 for (j = 0; j < adev->usec_timeout; j++) {
 443                         tmp = RREG32_NO_KIQ(hub->vm_inv_eng0_ack + eng);
 444                         if (tmp & (1 << vmid))
 445                                 break;
 446                         udelay(1);
 447                 }
 448                 spin_unlock(&adev->gmc.invalidate_lock);
 449                 if (j < adev->usec_timeout)
 450                         continue;
 451
 452                 DRM_ERROR("Timeout waiting for VM flush ACK!\n");
 453         }
 454 }
 455
 456 static uint64_t gmc_v9_0_emit_flush_gpu_tlb(struct amdgpu_ring *ring,
 457                                             unsigned vmid, uint64_t pd_addr)
 458 {
 459         struct amdgpu_device *adev = ring->adev;
 460         struct amdgpu_vmhub *hub = &adev->vmhub[ring->funcs->vmhub];
 461         uint32_t req = gmc_v9_0_get_invalidate_req(vmid, 0);
 462         unsigned eng = ring->vm_inv_eng;
 463
 464         amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_lo32 + (2 * vmid),
 465                               lower_32_bits(pd_addr));
 466
 467         amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_hi32 + (2 * vmid),
 468                               upper_32_bits(pd_addr));
 469
 470         amdgpu_ring_emit_reg_write_reg_wait(ring, hub->vm_inv_eng0_req + eng,
 471                                             hub->vm_inv_eng0_ack + eng,
 472                                             req, 1 << vmid);
 473
 474         return pd_addr;
 475 }
 476
 477 static void gmc_v9_0_emit_pasid_mapping(struct amdgpu_ring *ring, unsigned vmid,
 478                                         unsigned pasid)
 479 {
 480         struct amdgpu_device *adev = ring->adev;
 481         uint32_t reg;
 482
 483         if (ring->funcs->vmhub == AMDGPU_GFXHUB_0)
 484                 reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT) + vmid;
 485         else
 486                 reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT_MM) + vmid;
 487
 488         amdgpu_ring_emit_wreg(ring, reg, pasid);
 489 }
 490
 491 /*
 492  * PTE format on VEGA 10:
 493  * 63:59 reserved
 494  * 58:57 mtype
 495  * 56 F
 496  * 55 L
 497  * 54 P
 498  * 53 SW
 499  * 52 T
 500  * 50:48 reserved
 501  * 47:12 4k physical page base address
 502  * 11:7 fragment
 503  * 6 write
 504  * 5 read
 505  * 4 exe
 506  * 3 Z
 507  * 2 snooped
 508  * 1 system
 509  * 0 valid
 510  *
 511  * PDE format on VEGA 10:
 512  * 63:59 block fragment size
 513  * 58:55 reserved
 514  * 54 P
 515  * 53:48 reserved
 516  * 47:6 physical base address of PD or PTE
 517  * 5:3 reserved
 518  * 2 C
 519  * 1 system
 520  * 0 valid
 521  */
 522
 523 static uint64_t gmc_v9_0_get_vm_pte_flags(struct amdgpu_device *adev,
 524                                                 uint32_t flags)
 525
 526 {
 527         uint64_t pte_flag = 0;
 528
 529         if (flags & AMDGPU_VM_PAGE_EXECUTABLE)
 530                 pte_flag |= AMDGPU_PTE_EXECUTABLE;
 531         if (flags & AMDGPU_VM_PAGE_READABLE)
 532                 pte_flag |= AMDGPU_PTE_READABLE;
 533         if (flags & AMDGPU_VM_PAGE_WRITEABLE)
 534                 pte_flag |= AMDGPU_PTE_WRITEABLE;
 535
 536         switch (flags & AMDGPU_VM_MTYPE_MASK) {
 537         case AMDGPU_VM_MTYPE_DEFAULT:
 538                 pte_flag |= AMDGPU_PTE_MTYPE_VG10(MTYPE_NC);
 539                 break;
 540         case AMDGPU_VM_MTYPE_NC:
 541                 pte_flag |= AMDGPU_PTE_MTYPE_VG10(MTYPE_NC);
 542                 break;
 543         case AMDGPU_VM_MTYPE_WC:
 544                 pte_flag |= AMDGPU_PTE_MTYPE_VG10(MTYPE_WC);
 545                 break;
 546         case AMDGPU_VM_MTYPE_CC:
 547                 pte_flag |= AMDGPU_PTE_MTYPE_VG10(MTYPE_CC);
 548                 break;
 549         case AMDGPU_VM_MTYPE_UC:
 550                 pte_flag |= AMDGPU_PTE_MTYPE_VG10(MTYPE_UC);
 551                 break;
 552         default:
 553                 pte_flag |= AMDGPU_PTE_MTYPE_VG10(MTYPE_NC);
 554                 break;
 555         }
 556
 557         if (flags & AMDGPU_VM_PAGE_PRT)
 558                 pte_flag |= AMDGPU_PTE_PRT;
 559
 560         return pte_flag;
 561 }
 562
 563 static void gmc_v9_0_get_vm_pde(struct amdgpu_device *adev, int level,
 564                                 uint64_t *addr, uint64_t *flags)
 565 {
 566         if (!(*flags & AMDGPU_PDE_PTE) && !(*flags & AMDGPU_PTE_SYSTEM))
 567                 *addr = adev->vm_manager.vram_base_offset + *addr -
 568                         adev->gmc.vram_start;
 569         BUG_ON(*addr & 0xFFFF00000000003FULL);
 570
 571         if (!adev->gmc.translate_further)
 572                 return;
 573
 574         if (level == AMDGPU_VM_PDB1) {
 575                 /* Set the block fragment size */
 576                 if (!(*flags & AMDGPU_PDE_PTE))
 577                         *flags |= AMDGPU_PDE_BFS(0x9);
 578
 579         } else if (level == AMDGPU_VM_PDB0) {
 580                 if (*flags & AMDGPU_PDE_PTE)
 581                         *flags &= ~AMDGPU_PDE_PTE;
 582                 else
 583                         *flags |= AMDGPU_PTE_TF;
 584         }
 585 }
 586
 587 static const struct amdgpu_gmc_funcs gmc_v9_0_gmc_funcs = {
 588         .flush_gpu_tlb = gmc_v9_0_flush_gpu_tlb,
 589         .emit_flush_gpu_tlb = gmc_v9_0_emit_flush_gpu_tlb,
 590         .emit_pasid_mapping = gmc_v9_0_emit_pasid_mapping,
 591         .get_vm_pte_flags = gmc_v9_0_get_vm_pte_flags,
 592         .get_vm_pde = gmc_v9_0_get_vm_pde
 593 };
 594
 595 static void gmc_v9_0_set_gmc_funcs(struct amdgpu_device *adev)
 596 {
 597         adev->gmc.gmc_funcs = &gmc_v9_0_gmc_funcs;
 598 }
 599
 600 static int gmc_v9_0_early_init(void *handle)
 601 {
 602         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 603
 604         gmc_v9_0_set_gmc_funcs(adev);
 605         gmc_v9_0_set_irq_funcs(adev);
 606
 607         adev->gmc.shared_aperture_start = 0x2000000000000000ULL;
 608         adev->gmc.shared_aperture_end =
 609                 adev->gmc.shared_aperture_start + (4ULL << 30) - 1;
 610         adev->gmc.private_aperture_start = 0x1000000000000000ULL;
 611         adev->gmc.private_aperture_end =
 612                 adev->gmc.private_aperture_start + (4ULL << 30) - 1;
 613
 614         return 0;
 615 }
 616
 617 static bool gmc_v9_0_keep_stolen_memory(struct amdgpu_device *adev)
 618 {
 619
 620         /*
 621          * TODO:
 622          * Currently there is a bug where some memory client outside
 623          * of the driver writes to first 8M of VRAM on S3 resume,
 624          * this overrides GART which by default gets placed in first 8M and
 625          * causes VM_FAULTS once GTT is accessed.
 626          * Keep the stolen memory reservation until the while this is not solved.
 627          * Also check code in gmc_v9_0_get_vbios_fb_size and gmc_v9_0_late_init
 628          */
 629         switch (adev->asic_type) {
 630         case CHIP_VEGA10:
 631         case CHIP_RAVEN:
 632                 return true;
 633         case CHIP_VEGA12:
 634         case CHIP_VEGA20:
 635         default:
 636                 return false;
 637         }
 638 }
 639
 640 static int gmc_v9_0_allocate_vm_inv_eng(struct amdgpu_device *adev)
 641 {
 642         struct amdgpu_ring *ring;
 643         unsigned vm_inv_engs[AMDGPU_MAX_VMHUBS] =
 644                 {GFXHUB_FREE_VM_INV_ENGS_BITMAP, MMHUB_FREE_VM_INV_ENGS_BITMAP,
 645                 GFXHUB_FREE_VM_INV_ENGS_BITMAP};
 646         unsigned i;
 647         unsigned vmhub, inv_eng;
 648
 649         for (i = 0; i < adev->num_rings; ++i) {
 650                 ring = adev->rings[i];
 651                 vmhub = ring->funcs->vmhub;
 652
 653                 inv_eng = ffs(vm_inv_engs[vmhub]);
 654                 if (!inv_eng) {
 655                         dev_err(adev->dev, "no VM inv eng for ring %s\n",
 656                                 ring->name);
 657                         return -EINVAL;
 658                 }
 659
 660                 ring->vm_inv_eng = inv_eng - 1;
 661                 vm_inv_engs[vmhub] &= ~(1 << ring->vm_inv_eng);
 662
 663                 dev_info(adev->dev, "ring %s uses VM inv eng %u on hub %u\n",
 664                          ring->name, ring->vm_inv_eng, ring->funcs->vmhub);
 665         }
 666
 667         return 0;
 668 }
 669
 670 static int gmc_v9_0_ecc_late_init(void *handle)
 671 {
 672         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 673         struct ras_common_if **ras_if = &adev->gmc.ras_if;
 674         struct ras_ih_if ih_info = {
 675                 .cb = gmc_v9_0_process_ras_data_cb,
 676         };
 677         struct ras_fs_if fs_info = {
 678                 .sysfs_name = "umc_err_count",
 679                 .debugfs_name = "umc_err_inject",
 680         };
 681         struct ras_common_if ras_block = {
 682                 .block = AMDGPU_RAS_BLOCK__UMC,
 683                 .type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE,
 684                 .sub_block_index = 0,
 685                 .name = "umc",
 686         };
 687         int r;
 688
 689         if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__UMC)) {
 690                 amdgpu_ras_feature_enable_on_boot(adev, &ras_block, 0);
 691                 return 0;
 692         }
 693         /* handle resume path. */
 694         if (*ras_if) {
 695                 /* resend ras TA enable cmd during resume.
 696                  * prepare to handle failure.
 697                  */
 698                 ih_info.head = **ras_if;
 699                 r = amdgpu_ras_feature_enable_on_boot(adev, *ras_if, 1);
 700                 if (r) {
 701                         if (r == -EAGAIN) {
 702                                 /* request a gpu reset. will run again. */
 703                                 amdgpu_ras_request_reset_on_boot(adev,
 704                                                 AMDGPU_RAS_BLOCK__UMC);
 705                                 return 0;
 706                         }
 707                         /* fail to enable ras, cleanup all. */
 708                         goto irq;
 709                 }
 710                 /* enable successfully. continue. */
 711                 goto resume;
 712         }
 713
 714         *ras_if = kmalloc(sizeof(**ras_if), GFP_KERNEL);
 715         if (!*ras_if)
 716                 return -ENOMEM;
 717
 718         **ras_if = ras_block;
 719
 720         r = amdgpu_ras_feature_enable_on_boot(adev, *ras_if, 1);
 721         if (r) {
 722                 if (r == -EAGAIN) {
 723                         amdgpu_ras_request_reset_on_boot(adev,
 724                                         AMDGPU_RAS_BLOCK__UMC);
 725                         r = 0;
 726                 }
 727                 goto feature;
 728         }
 729
 730         ih_info.head = **ras_if;
 731         fs_info.head = **ras_if;
 732
 733         r = amdgpu_ras_interrupt_add_handler(adev, &ih_info);
 734         if (r)
 735                 goto interrupt;
 736
 737         amdgpu_ras_debugfs_create(adev, &fs_info);
 738
 739         r = amdgpu_ras_sysfs_create(adev, &fs_info);
 740         if (r)
 741                 goto sysfs;
 742 resume:
 743         r = amdgpu_irq_get(adev, &adev->gmc.ecc_irq, 0);
 744         if (r)
 745                 goto irq;
 746
 747         return 0;
 748 irq:
 749         amdgpu_ras_sysfs_remove(adev, *ras_if);
 750 sysfs:
 751         amdgpu_ras_debugfs_remove(adev, *ras_if);
 752         amdgpu_ras_interrupt_remove_handler(adev, &ih_info);
 753 interrupt:
 754         amdgpu_ras_feature_enable(adev, *ras_if, 0);
 755 feature:
 756         kfree(*ras_if);
 757         *ras_if = NULL;
 758         return r;
 759 }
 760
 761
 762 static int gmc_v9_0_late_init(void *handle)
 763 {
 764         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 765         bool r;
 766
 767         if (!gmc_v9_0_keep_stolen_memory(adev))
 768                 amdgpu_bo_late_init(adev);
 769
 770         r = gmc_v9_0_allocate_vm_inv_eng(adev);
 771         if (r)
 772                 return r;
 773         /* Check if ecc is available */
 774         if (!amdgpu_sriov_vf(adev)) {
 775                 switch (adev->asic_type) {
 776                 case CHIP_VEGA10:
 777                 case CHIP_VEGA20:
 778                         r = amdgpu_atomfirmware_mem_ecc_supported(adev);
 779                         if (!r) {
 780                                 DRM_INFO("ECC is not present.\n");
 781                                 if (adev->df_funcs->enable_ecc_force_par_wr_rmw)
 782                                         adev->df_funcs->enable_ecc_force_par_wr_rmw(adev, false);
 783                         } else {
 784                                 DRM_INFO("ECC is active.\n");
 785                         }
 786
 787                         r = amdgpu_atomfirmware_sram_ecc_supported(adev);
 788                         if (!r) {
 789                                 DRM_INFO("SRAM ECC is not present.\n");
 790                         } else {
 791                                 DRM_INFO("SRAM ECC is active.\n");
 792                         }
 793                         break;
 794                 default:
 795                         break;
 796                 }
 797         }
 798
 799         r = gmc_v9_0_ecc_late_init(handle);
 800         if (r)
 801                 return r;
 802
 803         return amdgpu_irq_get(adev, &adev->gmc.vm_fault, 0);
 804 }
 805
 806 static void gmc_v9_0_vram_gtt_location(struct amdgpu_device *adev,
 807                                         struct amdgpu_gmc *mc)
 808 {
 809         u64 base = 0;
 810         if (!amdgpu_sriov_vf(adev))
 811                 base = mmhub_v1_0_get_fb_location(adev);
 812         /* add the xgmi offset of the physical node */
 813         base += adev->gmc.xgmi.physical_node_id * adev->gmc.xgmi.node_segment_size;
 814         amdgpu_gmc_vram_location(adev, mc, base);
 815         amdgpu_gmc_gart_location(adev, mc);
 816         if (!amdgpu_sriov_vf(adev))
 817                 amdgpu_gmc_agp_location(adev, mc);
 818         /* base offset of vram pages */
 819         adev->vm_manager.vram_base_offset = gfxhub_v1_0_get_mc_fb_offset(adev);
 820
 821         /* XXX: add the xgmi offset of the physical node? */
 822         adev->vm_manager.vram_base_offset +=
 823                 adev->gmc.xgmi.physical_node_id * adev->gmc.xgmi.node_segment_size;
 824 }
 825
 826 /**
 827  * gmc_v9_0_mc_init - initialize the memory controller driver params
 828  *
 829  * @adev: amdgpu_device pointer
 830  *
 831  * Look up the amount of vram, vram width, and decide how to place
 832  * vram and gart within the GPU's physical address space.
 833  * Returns 0 for success.
 834  */
 835 static int gmc_v9_0_mc_init(struct amdgpu_device *adev)
 836 {
 837         int chansize, numchan;
 838         int r;
 839
 840         if (amdgpu_sriov_vf(adev)) {
 841                 /* For Vega10 SR-IOV, vram_width can't be read from ATOM as RAVEN,
 842                  * and DF related registers is not readable, seems hardcord is the
 843                  * only way to set the correct vram_width
 844                  */
 845                 adev->gmc.vram_width = 2048;
 846         } else if (amdgpu_emu_mode != 1) {
 847                 adev->gmc.vram_width = amdgpu_atomfirmware_get_vram_width(adev);
 848         }
 849
 850         if (!adev->gmc.vram_width) {
 851                 /* hbm memory channel size */
 852                 if (adev->flags & AMD_IS_APU)
 853                         chansize = 64;
 854                 else
 855                         chansize = 128;
 856
 857                 numchan = adev->df_funcs->get_hbm_channel_number(adev);
 858                 adev->gmc.vram_width = numchan * chansize;
 859         }
 860
 861         /* size in MB on si */
 862         adev->gmc.mc_vram_size =
 863                 adev->nbio_funcs->get_memsize(adev) * 1024ULL * 1024ULL;
 864         adev->gmc.real_vram_size = adev->gmc.mc_vram_size;
 865
 866         if (!(adev->flags & AMD_IS_APU)) {
 867                 r = amdgpu_device_resize_fb_bar(adev);
 868                 if (r)
 869                         return r;
 870         }
 871         adev->gmc.aper_base = pci_resource_start(adev->pdev, 0);
 872         adev->gmc.aper_size = pci_resource_len(adev->pdev, 0);
 873
 874 #ifdef CONFIG_X86_64
 875         if (adev->flags & AMD_IS_APU) {
 876                 adev->gmc.aper_base = gfxhub_v1_0_get_mc_fb_offset(adev);
 877                 adev->gmc.aper_size = adev->gmc.real_vram_size;
 878         }
 879 #endif
 880         /* In case the PCI BAR is larger than the actual amount of vram */
 881         adev->gmc.visible_vram_size = adev->gmc.aper_size;
 882         if (adev->gmc.visible_vram_size > adev->gmc.real_vram_size)
 883                 adev->gmc.visible_vram_size = adev->gmc.real_vram_size;
 884
 885         /* set the gart size */
 886         if (amdgpu_gart_size == -1) {
 887                 switch (adev->asic_type) {
 888                 case CHIP_VEGA10:  /* all engines support GPUVM */
 889                 case CHIP_VEGA12:  /* all engines support GPUVM */
 890                 case CHIP_VEGA20:
 891                 case CHIP_ARCTURUS:
 892                 default:
 893                         adev->gmc.gart_size = 512ULL << 20;
 894                         break;
 895                 case CHIP_RAVEN:   /* DCE SG support */
 896                         adev->gmc.gart_size = 1024ULL << 20;
 897                         break;
 898                 }
 899         } else {
 900                 adev->gmc.gart_size = (u64)amdgpu_gart_size << 20;
 901         }
 902
 903         gmc_v9_0_vram_gtt_location(adev, &adev->gmc);
 904
 905         return 0;
 906 }
 907
 908 static int gmc_v9_0_gart_init(struct amdgpu_device *adev)
 909 {
 910         int r;
 911
 912         if (adev->gart.bo) {
 913                 WARN(1, "VEGA10 PCIE GART already initialized\n");
 914                 return 0;
 915         }
 916         /* Initialize common gart structure */
 917         r = amdgpu_gart_init(adev);
 918         if (r)
 919                 return r;
 920         adev->gart.table_size = adev->gart.num_gpu_pages * 8;
 921         adev->gart.gart_pte_flags = AMDGPU_PTE_MTYPE_VG10(MTYPE_UC) |
 922                                  AMDGPU_PTE_EXECUTABLE;
 923         return amdgpu_gart_table_vram_alloc(adev);
 924 }
 925
 926 static unsigned gmc_v9_0_get_vbios_fb_size(struct amdgpu_device *adev)
 927 {
 928         u32 d1vga_control = RREG32_SOC15(DCE, 0, mmD1VGA_CONTROL);
 929         unsigned size;
 930
 931         /*
 932          * TODO Remove once GART corruption is resolved
 933          * Check related code in gmc_v9_0_sw_fini
 934          * */
 935         if (gmc_v9_0_keep_stolen_memory(adev))
 936                 return 9 * 1024 * 1024;
 937
 938         if (REG_GET_FIELD(d1vga_control, D1VGA_CONTROL, D1VGA_MODE_ENABLE)) {
 939                 size = 9 * 1024 * 1024; /* reserve 8MB for vga emulator and 1 MB for FB */
 940         } else {
 941                 u32 viewport;
 942
 943                 switch (adev->asic_type) {
 944                 case CHIP_RAVEN:
 945                         viewport = RREG32_SOC15(DCE, 0, mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION);
 946                         size = (REG_GET_FIELD(viewport,
 947                                               HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION, PRI_VIEWPORT_HEIGHT) *
 948                                 REG_GET_FIELD(viewport,
 949                                               HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION, PRI_VIEWPORT_WIDTH) *
 950                                 4);
 951                         break;
 952                 case CHIP_VEGA10:
 953                 case CHIP_VEGA12:
 954                 case CHIP_VEGA20:
 955                 default:
 956                         viewport = RREG32_SOC15(DCE, 0, mmSCL0_VIEWPORT_SIZE);
 957                         size = (REG_GET_FIELD(viewport, SCL0_VIEWPORT_SIZE, VIEWPORT_HEIGHT) *
 958                                 REG_GET_FIELD(viewport, SCL0_VIEWPORT_SIZE, VIEWPORT_WIDTH) *
 959                                 4);
 960                         break;
 961                 }
 962         }
 963         /* return 0 if the pre-OS buffer uses up most of vram */
 964         if ((adev->gmc.real_vram_size - size) < (8 * 1024 * 1024))
 965                 return 0;
 966
 967         return size;
 968 }
 969
 970 static int gmc_v9_0_sw_init(void *handle)
 971 {
 972         int r;
 973         int dma_bits;
 974         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 975
 976         gfxhub_v1_0_init(adev);
 977         mmhub_v1_0_init(adev);
 978
 979         spin_lock_init(&adev->gmc.invalidate_lock);
 980
 981         adev->gmc.vram_type = amdgpu_atomfirmware_get_vram_type(adev);
 982         switch (adev->asic_type) {
 983         case CHIP_RAVEN:
 984                 adev->num_vmhubs = 2;
 985
 986                 if (adev->rev_id == 0x0 || adev->rev_id == 0x1) {
 987                         amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 48);
 988                 } else {
 989                         /* vm_size is 128TB + 512GB for legacy 3-level page support */
 990                         amdgpu_vm_adjust_size(adev, 128 * 1024 + 512, 9, 2, 48);
 991                         adev->gmc.translate_further =
 992                                 adev->vm_manager.num_level > 1;
 993                 }
 994                 break;
 995         case CHIP_VEGA10:
 996         case CHIP_VEGA12:
 997         case CHIP_VEGA20:
 998                 adev->num_vmhubs = 2;
 999
1000                 /*
1001                  * To fulfill 4-level page support,
1002                  * vm size is 256TB (48bit), maximum size of Vega10,
1003                  * block size 512 (9bit)
1004                  */
1005                 /* sriov restrict max_pfn below AMDGPU_GMC_HOLE */
1006                 if (amdgpu_sriov_vf(adev))
1007                         amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 47);
1008                 else
1009                         amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 48);
1010                 break;
1011         case CHIP_ARCTURUS:
1012                 adev->num_vmhubs = 3;
1013
1014                 /* Keep the vm size same with Vega20 */
1015                 amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 48);
1016                 break;
1017         default:
1018                 break;
1019         }
1020
1021         /* This interrupt is VMC page fault.*/
1022         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VMC, VMC_1_0__SRCID__VM_FAULT,
1023                                 &adev->gmc.vm_fault);
1024         if (r)
1025                 return r;
1026
1027         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_UTCL2, UTCL2_1_0__SRCID__FAULT,
1028                                 &adev->gmc.vm_fault);
1029
1030         if (r)
1031                 return r;
1032
1033         /* interrupt sent to DF. */
1034         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DF, 0,
1035                         &adev->gmc.ecc_irq);
1036         if (r)
1037                 return r;
1038
1039         /* Set the internal MC address mask
1040          * This is the max address of the GPU's
1041          * internal address space.
1042          */
1043         adev->gmc.mc_mask = 0xffffffffffffULL; /* 48 bit MC */
1044
1045         /* set DMA mask + need_dma32 flags.
1046          * PCIE - can handle 44-bits.
1047          * IGP - can handle 44-bits
1048          * PCI - dma32 for legacy pci gart, 44 bits on vega10
1049          */
1050         adev->need_dma32 = false;
1051         dma_bits = adev->need_dma32 ? 32 : 44;
1052         r = pci_set_dma_mask(adev->pdev, DMA_BIT_MASK(dma_bits));
1053         if (r) {
1054                 adev->need_dma32 = true;
1055                 dma_bits = 32;
1056                 printk(KERN_WARNING "amdgpu: No suitable DMA available.\n");
1057         }
1058         r = pci_set_consistent_dma_mask(adev->pdev, DMA_BIT_MASK(dma_bits));
1059         if (r) {
1060                 pci_set_consistent_dma_mask(adev->pdev, DMA_BIT_MASK(32));
1061                 printk(KERN_WARNING "amdgpu: No coherent DMA available.\n");
1062         }
1063         adev->need_swiotlb = drm_need_swiotlb(dma_bits);
1064
1065         if (adev->gmc.xgmi.supported) {
1066                 r = gfxhub_v1_1_get_xgmi_info(adev);
1067                 if (r)
1068                         return r;
1069         }
1070
1071         r = gmc_v9_0_mc_init(adev);
1072         if (r)
1073                 return r;
1074
1075         adev->gmc.stolen_size = gmc_v9_0_get_vbios_fb_size(adev);
1076
1077         /* Memory manager */
1078         r = amdgpu_bo_init(adev);
1079         if (r)
1080                 return r;
1081
1082         r = gmc_v9_0_gart_init(adev);
1083         if (r)
1084                 return r;
1085
1086         /*
1087          * number of VMs
1088          * VMID 0 is reserved for System
1089          * amdgpu graphics/compute will use VMIDs 1-7
1090          * amdkfd will use VMIDs 8-15
1091          */
1092         adev->vm_manager.id_mgr[AMDGPU_GFXHUB_0].num_ids = AMDGPU_NUM_OF_VMIDS;
1093         adev->vm_manager.id_mgr[AMDGPU_MMHUB_0].num_ids = AMDGPU_NUM_OF_VMIDS;
1094         adev->vm_manager.id_mgr[AMDGPU_MMHUB_1].num_ids = AMDGPU_NUM_OF_VMIDS;
1095
1096         amdgpu_vm_manager_init(adev);
1097
1098         return 0;
1099 }
1100
1101 static int gmc_v9_0_sw_fini(void *handle)
1102 {
1103         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1104
1105         if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__UMC) &&
1106                         adev->gmc.ras_if) {
1107                 struct ras_common_if *ras_if = adev->gmc.ras_if;
1108                 struct ras_ih_if ih_info = {
1109                         .head = *ras_if,
1110                 };
1111
1112                 /*remove fs first*/
1113                 amdgpu_ras_debugfs_remove(adev, ras_if);
1114                 amdgpu_ras_sysfs_remove(adev, ras_if);
1115                 /*remove the IH*/
1116                 amdgpu_ras_interrupt_remove_handler(adev, &ih_info);
1117                 amdgpu_ras_feature_enable(adev, ras_if, 0);
1118                 kfree(ras_if);
1119         }
1120
1121         amdgpu_gem_force_release(adev);
1122         amdgpu_vm_manager_fini(adev);
1123
1124         if (gmc_v9_0_keep_stolen_memory(adev))
1125                 amdgpu_bo_free_kernel(&adev->stolen_vga_memory, NULL, NULL);
1126
1127         amdgpu_gart_table_vram_free(adev);
1128         amdgpu_bo_fini(adev);
1129         amdgpu_gart_fini(adev);
1130
1131         return 0;
1132 }
1133
1134 static void gmc_v9_0_init_golden_registers(struct amdgpu_device *adev)
1135 {
1136
1137         switch (adev->asic_type) {
1138         case CHIP_VEGA10:
1139                 if (amdgpu_virt_support_skip_setting(adev))
1140                         break;
1141                 /* fall through */
1142         case CHIP_VEGA20:
1143                 soc15_program_register_sequence(adev,
1144                                                 golden_settings_mmhub_1_0_0,
1145                                                 ARRAY_SIZE(golden_settings_mmhub_1_0_0));
1146                 soc15_program_register_sequence(adev,
1147                                                 golden_settings_athub_1_0_0,
1148                                                 ARRAY_SIZE(golden_settings_athub_1_0_0));
1149                 break;
1150         case CHIP_VEGA12:
1151                 break;
1152         case CHIP_RAVEN:
1153                 soc15_program_register_sequence(adev,
1154                                                 golden_settings_athub_1_0_0,
1155                                                 ARRAY_SIZE(golden_settings_athub_1_0_0));
1156                 break;
1157         default:
1158                 break;
1159         }
1160 }
1161
1162 /**
1163  * gmc_v9_0_gart_enable - gart enable
1164  *
1165  * @adev: amdgpu_device pointer
1166  */
1167 static int gmc_v9_0_gart_enable(struct amdgpu_device *adev)
1168 {
1169         int r;
1170         bool value;
1171         u32 tmp;
1172
1173         amdgpu_device_program_register_sequence(adev,
1174                                                 golden_settings_vega10_hdp,
1175                                                 ARRAY_SIZE(golden_settings_vega10_hdp));
1176
1177         if (adev->gart.bo == NULL) {
1178                 dev_err(adev->dev, "No VRAM object for PCIE GART.\n");
1179                 return -EINVAL;
1180         }
1181         r = amdgpu_gart_table_vram_pin(adev);
1182         if (r)
1183                 return r;
1184
1185         switch (adev->asic_type) {
1186         case CHIP_RAVEN:
1187                 mmhub_v1_0_update_power_gating(adev, true);
1188                 break;
1189         default:
1190                 break;
1191         }
1192
1193         r = gfxhub_v1_0_gart_enable(adev);
1194         if (r)
1195                 return r;
1196
1197         r = mmhub_v1_0_gart_enable(adev);
1198         if (r)
1199                 return r;
1200
1201         WREG32_FIELD15(HDP, 0, HDP_MISC_CNTL, FLUSH_INVALIDATE_CACHE, 1);
1202
1203         tmp = RREG32_SOC15(HDP, 0, mmHDP_HOST_PATH_CNTL);
1204         WREG32_SOC15(HDP, 0, mmHDP_HOST_PATH_CNTL, tmp);
1205
1206         WREG32_SOC15(HDP, 0, mmHDP_NONSURFACE_BASE, (adev->gmc.vram_start >> 8));
1207         WREG32_SOC15(HDP, 0, mmHDP_NONSURFACE_BASE_HI, (adev->gmc.vram_start >> 40));
1208
1209         /* After HDP is initialized, flush HDP.*/
1210         adev->nbio_funcs->hdp_flush(adev, NULL);
1211
1212         if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS)
1213                 value = false;
1214         else
1215                 value = true;
1216
1217         gfxhub_v1_0_set_fault_enable_default(adev, value);
1218         mmhub_v1_0_set_fault_enable_default(adev, value);
1219         gmc_v9_0_flush_gpu_tlb(adev, 0, 0);
1220
1221         DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
1222                  (unsigned)(adev->gmc.gart_size >> 20),
1223                  (unsigned long long)amdgpu_bo_gpu_offset(adev->gart.bo));
1224         adev->gart.ready = true;
1225         return 0;
1226 }
1227
1228 static int gmc_v9_0_hw_init(void *handle)
1229 {
1230         int r;
1231         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1232
1233         /* The sequence of these two function calls matters.*/
1234         gmc_v9_0_init_golden_registers(adev);
1235
1236         if (adev->mode_info.num_crtc) {
1237                 /* Lockout access through VGA aperture*/
1238                 WREG32_FIELD15(DCE, 0, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 1);
1239
1240                 /* disable VGA render */
1241                 WREG32_FIELD15(DCE, 0, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0);
1242         }
1243
1244         r = gmc_v9_0_gart_enable(adev);
1245
1246         return r;
1247 }
1248
1249 /**
1250  * gmc_v9_0_gart_disable - gart disable
1251  *
1252  * @adev: amdgpu_device pointer
1253  *
1254  * This disables all VM page table.
1255  */
1256 static void gmc_v9_0_gart_disable(struct amdgpu_device *adev)
1257 {
1258         gfxhub_v1_0_gart_disable(adev);
1259         mmhub_v1_0_gart_disable(adev);
1260         amdgpu_gart_table_vram_unpin(adev);
1261 }
1262
1263 static int gmc_v9_0_hw_fini(void *handle)
1264 {
1265         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1266
1267         if (amdgpu_sriov_vf(adev)) {
1268                 /* full access mode, so don't touch any GMC register */
1269                 DRM_DEBUG("For SRIOV client, shouldn't do anything.\n");
1270                 return 0;
1271         }
1272
1273         amdgpu_irq_put(adev, &adev->gmc.ecc_irq, 0);
1274         amdgpu_irq_put(adev, &adev->gmc.vm_fault, 0);
1275         gmc_v9_0_gart_disable(adev);
1276
1277         return 0;
1278 }
1279
1280 static int gmc_v9_0_suspend(void *handle)
1281 {
1282         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1283
1284         return gmc_v9_0_hw_fini(adev);
1285 }
1286
1287 static int gmc_v9_0_resume(void *handle)
1288 {
1289         int r;
1290         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1291
1292         r = gmc_v9_0_hw_init(adev);
1293         if (r)
1294                 return r;
1295
1296         amdgpu_vmid_reset_all(adev);
1297
1298         return 0;
1299 }
1300
1301 static bool gmc_v9_0_is_idle(void *handle)
1302 {
1303         /* MC is always ready in GMC v9.*/
1304         return true;
1305 }
1306
1307 static int gmc_v9_0_wait_for_idle(void *handle)
1308 {
1309         /* There is no need to wait for MC idle in GMC v9.*/
1310         return 0;
1311 }
1312
1313 static int gmc_v9_0_soft_reset(void *handle)
1314 {
1315         /* XXX for emulation.*/
1316         return 0;
1317 }
1318
1319 static int gmc_v9_0_set_clockgating_state(void *handle,
1320                                         enum amd_clockgating_state state)
1321 {
1322         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1323
1324         return mmhub_v1_0_set_clockgating(adev, state);
1325 }
1326
1327 static void gmc_v9_0_get_clockgating_state(void *handle, u32 *flags)
1328 {
1329         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1330
1331         mmhub_v1_0_get_clockgating(adev, flags);
1332 }
1333
1334 static int gmc_v9_0_set_powergating_state(void *handle,
1335                                         enum amd_powergating_state state)
1336 {
1337         return 0;
1338 }
1339
1340 const struct amd_ip_funcs gmc_v9_0_ip_funcs = {
1341         .name = "gmc_v9_0",
1342         .early_init = gmc_v9_0_early_init,
1343         .late_init = gmc_v9_0_late_init,
1344         .sw_init = gmc_v9_0_sw_init,
1345         .sw_fini = gmc_v9_0_sw_fini,
1346         .hw_init = gmc_v9_0_hw_init,
1347         .hw_fini = gmc_v9_0_hw_fini,
1348         .suspend = gmc_v9_0_suspend,
1349         .resume = gmc_v9_0_resume,
1350         .is_idle = gmc_v9_0_is_idle,
1351         .wait_for_idle = gmc_v9_0_wait_for_idle,
1352         .soft_reset = gmc_v9_0_soft_reset,
1353         .set_clockgating_state = gmc_v9_0_set_clockgating_state,
1354         .set_powergating_state = gmc_v9_0_set_powergating_state,
1355         .get_clockgating_state = gmc_v9_0_get_clockgating_state,
1356 };
1357
1358 const struct amdgpu_ip_block_version gmc_v9_0_ip_block =
1359 {
1360         .type = AMD_IP_BLOCK_TYPE_GMC,
1361         .major = 9,
1362         .minor = 0,
1363         .rev = 0,
1364         .funcs = &gmc_v9_0_ip_funcs,
1365 };