drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c

   1 /*
   2  * Copyright 2016 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #include <linux/firmware.h>
  25 #include <linux/pci.h>
  26
  27 #include <drm/drm_cache.h>
  28
  29 #include "amdgpu.h"
  30 #include "gmc_v9_0.h"
  31 #include "amdgpu_atomfirmware.h"
  32 #include "amdgpu_gem.h"
  33
  34 #include "hdp/hdp_4_0_offset.h"
  35 #include "hdp/hdp_4_0_sh_mask.h"
  36 #include "gc/gc_9_0_sh_mask.h"
  37 #include "dce/dce_12_0_offset.h"
  38 #include "dce/dce_12_0_sh_mask.h"
  39 #include "vega10_enum.h"
  40 #include "mmhub/mmhub_1_0_offset.h"
  41 #include "athub/athub_1_0_offset.h"
  42 #include "oss/osssys_4_0_offset.h"
  43
  44 #include "soc15.h"
  45 #include "soc15_common.h"
  46 #include "umc/umc_6_0_sh_mask.h"
  47
  48 #include "gfxhub_v1_0.h"
  49 #include "mmhub_v1_0.h"
  50 #include "athub_v1_0.h"
  51 #include "gfxhub_v1_1.h"
  52 #include "mmhub_v9_4.h"
  53 #include "umc_v6_1.h"
  54
  55 #include "ivsrcid/vmc/irqsrcs_vmc_1_0.h"
  56
  57 #include "amdgpu_ras.h"
  58 #include "amdgpu_xgmi.h"
  59
  60 /* add these here since we already include dce12 headers and these are for DCN */
  61 #define mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION                                                          0x055d
  62 #define mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_BASE_IDX                                                 2
  63 #define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_WIDTH__SHIFT                                        0x0
  64 #define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_HEIGHT__SHIFT                                       0x10
  65 #define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_WIDTH_MASK                                          0x00003FFFL
  66 #define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_HEIGHT_MASK                                         0x3FFF0000L
  67
  68 /* XXX Move this macro to VEGA10 header file, which is like vid.h for VI.*/
  69 #define AMDGPU_NUM_OF_VMIDS                     8
  70
  71 static const u32 golden_settings_vega10_hdp[] =
  72 {
  73         0xf64, 0x0fffffff, 0x00000000,
  74         0xf65, 0x0fffffff, 0x00000000,
  75         0xf66, 0x0fffffff, 0x00000000,
  76         0xf67, 0x0fffffff, 0x00000000,
  77         0xf68, 0x0fffffff, 0x00000000,
  78         0xf6a, 0x0fffffff, 0x00000000,
  79         0xf6b, 0x0fffffff, 0x00000000,
  80         0xf6c, 0x0fffffff, 0x00000000,
  81         0xf6d, 0x0fffffff, 0x00000000,
  82         0xf6e, 0x0fffffff, 0x00000000,
  83 };
  84
  85 static const struct soc15_reg_golden golden_settings_mmhub_1_0_0[] =
  86 {
  87         SOC15_REG_GOLDEN_VALUE(MMHUB, 0, mmDAGB1_WRCLI2, 0x00000007, 0xfe5fe0fa),
  88         SOC15_REG_GOLDEN_VALUE(MMHUB, 0, mmMMEA1_DRAM_WR_CLI2GRP_MAP0, 0x00000030, 0x55555565)
  89 };
  90
  91 static const struct soc15_reg_golden golden_settings_athub_1_0_0[] =
  92 {
  93         SOC15_REG_GOLDEN_VALUE(ATHUB, 0, mmRPB_ARB_CNTL, 0x0000ff00, 0x00000800),
  94         SOC15_REG_GOLDEN_VALUE(ATHUB, 0, mmRPB_ARB_CNTL2, 0x00ff00ff, 0x00080008)
  95 };
  96
  97 static const uint32_t ecc_umc_mcumc_ctrl_addrs[] = {
  98         (0x000143c0 + 0x00000000),
  99         (0x000143c0 + 0x00000800),
 100         (0x000143c0 + 0x00001000),
 101         (0x000143c0 + 0x00001800),
 102         (0x000543c0 + 0x00000000),
 103         (0x000543c0 + 0x00000800),
 104         (0x000543c0 + 0x00001000),
 105         (0x000543c0 + 0x00001800),
 106         (0x000943c0 + 0x00000000),
 107         (0x000943c0 + 0x00000800),
 108         (0x000943c0 + 0x00001000),
 109         (0x000943c0 + 0x00001800),
 110         (0x000d43c0 + 0x00000000),
 111         (0x000d43c0 + 0x00000800),
 112         (0x000d43c0 + 0x00001000),
 113         (0x000d43c0 + 0x00001800),
 114         (0x001143c0 + 0x00000000),
 115         (0x001143c0 + 0x00000800),
 116         (0x001143c0 + 0x00001000),
 117         (0x001143c0 + 0x00001800),
 118         (0x001543c0 + 0x00000000),
 119         (0x001543c0 + 0x00000800),
 120         (0x001543c0 + 0x00001000),
 121         (0x001543c0 + 0x00001800),
 122         (0x001943c0 + 0x00000000),
 123         (0x001943c0 + 0x00000800),
 124         (0x001943c0 + 0x00001000),
 125         (0x001943c0 + 0x00001800),
 126         (0x001d43c0 + 0x00000000),
 127         (0x001d43c0 + 0x00000800),
 128         (0x001d43c0 + 0x00001000),
 129         (0x001d43c0 + 0x00001800),
 130 };
 131
 132 static const uint32_t ecc_umc_mcumc_ctrl_mask_addrs[] = {
 133         (0x000143e0 + 0x00000000),
 134         (0x000143e0 + 0x00000800),
 135         (0x000143e0 + 0x00001000),
 136         (0x000143e0 + 0x00001800),
 137         (0x000543e0 + 0x00000000),
 138         (0x000543e0 + 0x00000800),
 139         (0x000543e0 + 0x00001000),
 140         (0x000543e0 + 0x00001800),
 141         (0x000943e0 + 0x00000000),
 142         (0x000943e0 + 0x00000800),
 143         (0x000943e0 + 0x00001000),
 144         (0x000943e0 + 0x00001800),
 145         (0x000d43e0 + 0x00000000),
 146         (0x000d43e0 + 0x00000800),
 147         (0x000d43e0 + 0x00001000),
 148         (0x000d43e0 + 0x00001800),
 149         (0x001143e0 + 0x00000000),
 150         (0x001143e0 + 0x00000800),
 151         (0x001143e0 + 0x00001000),
 152         (0x001143e0 + 0x00001800),
 153         (0x001543e0 + 0x00000000),
 154         (0x001543e0 + 0x00000800),
 155         (0x001543e0 + 0x00001000),
 156         (0x001543e0 + 0x00001800),
 157         (0x001943e0 + 0x00000000),
 158         (0x001943e0 + 0x00000800),
 159         (0x001943e0 + 0x00001000),
 160         (0x001943e0 + 0x00001800),
 161         (0x001d43e0 + 0x00000000),
 162         (0x001d43e0 + 0x00000800),
 163         (0x001d43e0 + 0x00001000),
 164         (0x001d43e0 + 0x00001800),
 165 };
 166
 167 static const uint32_t ecc_umc_mcumc_status_addrs[] = {
 168         (0x000143c2 + 0x00000000),
 169         (0x000143c2 + 0x00000800),
 170         (0x000143c2 + 0x00001000),
 171         (0x000143c2 + 0x00001800),
 172         (0x000543c2 + 0x00000000),
 173         (0x000543c2 + 0x00000800),
 174         (0x000543c2 + 0x00001000),
 175         (0x000543c2 + 0x00001800),
 176         (0x000943c2 + 0x00000000),
 177         (0x000943c2 + 0x00000800),
 178         (0x000943c2 + 0x00001000),
 179         (0x000943c2 + 0x00001800),
 180         (0x000d43c2 + 0x00000000),
 181         (0x000d43c2 + 0x00000800),
 182         (0x000d43c2 + 0x00001000),
 183         (0x000d43c2 + 0x00001800),
 184         (0x001143c2 + 0x00000000),
 185         (0x001143c2 + 0x00000800),
 186         (0x001143c2 + 0x00001000),
 187         (0x001143c2 + 0x00001800),
 188         (0x001543c2 + 0x00000000),
 189         (0x001543c2 + 0x00000800),
 190         (0x001543c2 + 0x00001000),
 191         (0x001543c2 + 0x00001800),
 192         (0x001943c2 + 0x00000000),
 193         (0x001943c2 + 0x00000800),
 194         (0x001943c2 + 0x00001000),
 195         (0x001943c2 + 0x00001800),
 196         (0x001d43c2 + 0x00000000),
 197         (0x001d43c2 + 0x00000800),
 198         (0x001d43c2 + 0x00001000),
 199         (0x001d43c2 + 0x00001800),
 200 };
 201
 202 static int gmc_v9_0_ecc_interrupt_state(struct amdgpu_device *adev,
 203                 struct amdgpu_irq_src *src,
 204                 unsigned type,
 205                 enum amdgpu_interrupt_state state)
 206 {
 207         u32 bits, i, tmp, reg;
 208
 209         bits = 0x7f;
 210
 211         switch (state) {
 212         case AMDGPU_IRQ_STATE_DISABLE:
 213                 for (i = 0; i < ARRAY_SIZE(ecc_umc_mcumc_ctrl_addrs); i++) {
 214                         reg = ecc_umc_mcumc_ctrl_addrs[i];
 215                         tmp = RREG32(reg);
 216                         tmp &= ~bits;
 217                         WREG32(reg, tmp);
 218                 }
 219                 for (i = 0; i < ARRAY_SIZE(ecc_umc_mcumc_ctrl_mask_addrs); i++) {
 220                         reg = ecc_umc_mcumc_ctrl_mask_addrs[i];
 221                         tmp = RREG32(reg);
 222                         tmp &= ~bits;
 223                         WREG32(reg, tmp);
 224                 }
 225                 break;
 226         case AMDGPU_IRQ_STATE_ENABLE:
 227                 for (i = 0; i < ARRAY_SIZE(ecc_umc_mcumc_ctrl_addrs); i++) {
 228                         reg = ecc_umc_mcumc_ctrl_addrs[i];
 229                         tmp = RREG32(reg);
 230                         tmp |= bits;
 231                         WREG32(reg, tmp);
 232                 }
 233                 for (i = 0; i < ARRAY_SIZE(ecc_umc_mcumc_ctrl_mask_addrs); i++) {
 234                         reg = ecc_umc_mcumc_ctrl_mask_addrs[i];
 235                         tmp = RREG32(reg);
 236                         tmp |= bits;
 237                         WREG32(reg, tmp);
 238                 }
 239                 break;
 240         default:
 241                 break;
 242         }
 243
 244         return 0;
 245 }
 246
 247 static int gmc_v9_0_process_ras_data_cb(struct amdgpu_device *adev,
 248                 struct ras_err_data *err_data,
 249                 struct amdgpu_iv_entry *entry)
 250 {
 251         if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__GFX))
 252                 return AMDGPU_RAS_SUCCESS;
 253
 254         kgd2kfd_set_sram_ecc_flag(adev->kfd.dev);
 255         if (adev->umc.funcs &&
 256             adev->umc.funcs->query_ras_error_count)
 257             adev->umc.funcs->query_ras_error_count(adev, err_data);
 258
 259         if (adev->umc.funcs &&
 260             adev->umc.funcs->query_ras_error_address &&
 261             adev->umc.max_ras_err_cnt_per_query) {
 262                 err_data->err_addr =
 263                         kcalloc(adev->umc.max_ras_err_cnt_per_query,
 264                                 sizeof(struct eeprom_table_record), GFP_KERNEL);
 265                 /* still call query_ras_error_address to clear error status
 266                  * even NOMEM error is encountered
 267                  */
 268                 if(!err_data->err_addr)
 269                         DRM_WARN("Failed to alloc memory for umc error address record!\n");
 270
 271                 /* umc query_ras_error_address is also responsible for clearing
 272                  * error status
 273                  */
 274                 adev->umc.funcs->query_ras_error_address(adev, err_data);
 275         }
 276
 277         /* only uncorrectable error needs gpu reset */
 278         if (err_data->ue_count) {
 279                 if (err_data->err_addr_cnt &&
 280                     amdgpu_ras_add_bad_pages(adev, err_data->err_addr,
 281                                                 err_data->err_addr_cnt))
 282                         DRM_WARN("Failed to add ras bad page!\n");
 283
 284                 amdgpu_ras_reset_gpu(adev, 0);
 285         }
 286
 287         kfree(err_data->err_addr);
 288         return AMDGPU_RAS_SUCCESS;
 289 }
 290
 291 static int gmc_v9_0_process_ecc_irq(struct amdgpu_device *adev,
 292                 struct amdgpu_irq_src *source,
 293                 struct amdgpu_iv_entry *entry)
 294 {
 295         struct ras_common_if *ras_if = adev->gmc.umc_ras_if;
 296         struct ras_dispatch_if ih_data = {
 297                 .entry = entry,
 298         };
 299
 300         if (!ras_if)
 301                 return 0;
 302
 303         ih_data.head = *ras_if;
 304
 305         amdgpu_ras_interrupt_dispatch(adev, &ih_data);
 306         return 0;
 307 }
 308
 309 static int gmc_v9_0_vm_fault_interrupt_state(struct amdgpu_device *adev,
 310                                         struct amdgpu_irq_src *src,
 311                                         unsigned type,
 312                                         enum amdgpu_interrupt_state state)
 313 {
 314         struct amdgpu_vmhub *hub;
 315         u32 tmp, reg, bits, i, j;
 316
 317         bits = VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
 318                 VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
 319                 VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
 320                 VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
 321                 VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
 322                 VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
 323                 VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK;
 324
 325         switch (state) {
 326         case AMDGPU_IRQ_STATE_DISABLE:
 327                 for (j = 0; j < adev->num_vmhubs; j++) {
 328                         hub = &adev->vmhub[j];
 329                         for (i = 0; i < 16; i++) {
 330                                 reg = hub->vm_context0_cntl + i;
 331                                 tmp = RREG32(reg);
 332                                 tmp &= ~bits;
 333                                 WREG32(reg, tmp);
 334                         }
 335                 }
 336                 break;
 337         case AMDGPU_IRQ_STATE_ENABLE:
 338                 for (j = 0; j < adev->num_vmhubs; j++) {
 339                         hub = &adev->vmhub[j];
 340                         for (i = 0; i < 16; i++) {
 341                                 reg = hub->vm_context0_cntl + i;
 342                                 tmp = RREG32(reg);
 343                                 tmp |= bits;
 344                                 WREG32(reg, tmp);
 345                         }
 346                 }
 347         default:
 348                 break;
 349         }
 350
 351         return 0;
 352 }
 353
 354 static int gmc_v9_0_process_interrupt(struct amdgpu_device *adev,
 355                                 struct amdgpu_irq_src *source,
 356                                 struct amdgpu_iv_entry *entry)
 357 {
 358         struct amdgpu_vmhub *hub;
 359         bool retry_fault = !!(entry->src_data[1] & 0x80);
 360         uint32_t status = 0;
 361         u64 addr;
 362         char hub_name[10];
 363
 364         addr = (u64)entry->src_data[0] << 12;
 365         addr |= ((u64)entry->src_data[1] & 0xf) << 44;
 366
 367         if (retry_fault && amdgpu_gmc_filter_faults(adev, addr, entry->pasid,
 368                                                     entry->timestamp))
 369                 return 1; /* This also prevents sending it to KFD */
 370
 371         if (entry->client_id == SOC15_IH_CLIENTID_VMC) {
 372                 snprintf(hub_name, sizeof(hub_name), "mmhub0");
 373                 hub = &adev->vmhub[AMDGPU_MMHUB_0];
 374         } else if (entry->client_id == SOC15_IH_CLIENTID_VMC1) {
 375                 snprintf(hub_name, sizeof(hub_name), "mmhub1");
 376                 hub = &adev->vmhub[AMDGPU_MMHUB_1];
 377         } else {
 378                 snprintf(hub_name, sizeof(hub_name), "gfxhub0");
 379                 hub = &adev->vmhub[AMDGPU_GFXHUB_0];
 380         }
 381
 382         /* If it's the first fault for this address, process it normally */
 383         if (!amdgpu_sriov_vf(adev)) {
 384                 /*
 385                  * Issue a dummy read to wait for the status register to
 386                  * be updated to avoid reading an incorrect value due to
 387                  * the new fast GRBM interface.
 388                  */
 389                 if (entry->vmid_src == AMDGPU_GFXHUB_0)
 390                         RREG32(hub->vm_l2_pro_fault_status);
 391
 392                 status = RREG32(hub->vm_l2_pro_fault_status);
 393                 WREG32_P(hub->vm_l2_pro_fault_cntl, 1, ~1);
 394         }
 395
 396         if (printk_ratelimit()) {
 397                 struct amdgpu_task_info task_info;
 398
 399                 memset(&task_info, 0, sizeof(struct amdgpu_task_info));
 400                 amdgpu_vm_get_task_info(adev, entry->pasid, &task_info);
 401
 402                 dev_err(adev->dev,
 403                         "[%s] %s page fault (src_id:%u ring:%u vmid:%u "
 404                         "pasid:%u, for process %s pid %d thread %s pid %d)\n",
 405                         hub_name, retry_fault ? "retry" : "no-retry",
 406                         entry->src_id, entry->ring_id, entry->vmid,
 407                         entry->pasid, task_info.process_name, task_info.tgid,
 408                         task_info.task_name, task_info.pid);
 409                 dev_err(adev->dev, "  in page starting at address 0x%016llx from client %d\n",
 410                         addr, entry->client_id);
 411                 if (!amdgpu_sriov_vf(adev)) {
 412                         dev_err(adev->dev,
 413                                 "VM_L2_PROTECTION_FAULT_STATUS:0x%08X\n",
 414                                 status);
 415                         dev_err(adev->dev, "\t MORE_FAULTS: 0x%lx\n",
 416                                 REG_GET_FIELD(status,
 417                                 VM_L2_PROTECTION_FAULT_STATUS, MORE_FAULTS));
 418                         dev_err(adev->dev, "\t WALKER_ERROR: 0x%lx\n",
 419                                 REG_GET_FIELD(status,
 420                                 VM_L2_PROTECTION_FAULT_STATUS, WALKER_ERROR));
 421                         dev_err(adev->dev, "\t PERMISSION_FAULTS: 0x%lx\n",
 422                                 REG_GET_FIELD(status,
 423                                 VM_L2_PROTECTION_FAULT_STATUS, PERMISSION_FAULTS));
 424                         dev_err(adev->dev, "\t MAPPING_ERROR: 0x%lx\n",
 425                                 REG_GET_FIELD(status,
 426                                 VM_L2_PROTECTION_FAULT_STATUS, MAPPING_ERROR));
 427                         dev_err(adev->dev, "\t RW: 0x%lx\n",
 428                                 REG_GET_FIELD(status,
 429                                 VM_L2_PROTECTION_FAULT_STATUS, RW));
 430
 431                 }
 432         }
 433
 434         return 0;
 435 }
 436
 437 static const struct amdgpu_irq_src_funcs gmc_v9_0_irq_funcs = {
 438         .set = gmc_v9_0_vm_fault_interrupt_state,
 439         .process = gmc_v9_0_process_interrupt,
 440 };
 441
 442
 443 static const struct amdgpu_irq_src_funcs gmc_v9_0_ecc_funcs = {
 444         .set = gmc_v9_0_ecc_interrupt_state,
 445         .process = gmc_v9_0_process_ecc_irq,
 446 };
 447
 448 static void gmc_v9_0_set_irq_funcs(struct amdgpu_device *adev)
 449 {
 450         adev->gmc.vm_fault.num_types = 1;
 451         adev->gmc.vm_fault.funcs = &gmc_v9_0_irq_funcs;
 452
 453         adev->gmc.ecc_irq.num_types = 1;
 454         adev->gmc.ecc_irq.funcs = &gmc_v9_0_ecc_funcs;
 455 }
 456
 457 static uint32_t gmc_v9_0_get_invalidate_req(unsigned int vmid,
 458                                         uint32_t flush_type)
 459 {
 460         u32 req = 0;
 461
 462         req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ,
 463                             PER_VMID_INVALIDATE_REQ, 1 << vmid);
 464         req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, FLUSH_TYPE, flush_type);
 465         req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PTES, 1);
 466         req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE0, 1);
 467         req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE1, 1);
 468         req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE2, 1);
 469         req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L1_PTES, 1);
 470         req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ,
 471                             CLEAR_PROTECTION_FAULT_STATUS_ADDR, 0);
 472
 473         return req;
 474 }
 475
 476 /*
 477  * GART
 478  * VMID 0 is the physical GPU addresses as used by the kernel.
 479  * VMIDs 1-15 are used for userspace clients and are handled
 480  * by the amdgpu vm/hsa code.
 481  */
 482
 483 /**
 484  * gmc_v9_0_flush_gpu_tlb - tlb flush with certain type
 485  *
 486  * @adev: amdgpu_device pointer
 487  * @vmid: vm instance to flush
 488  * @flush_type: the flush type
 489  *
 490  * Flush the TLB for the requested page table using certain type.
 491  */
 492 static void gmc_v9_0_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid,
 493                                         uint32_t vmhub, uint32_t flush_type)
 494 {
 495         const unsigned eng = 17;
 496         u32 j, tmp;
 497         struct amdgpu_vmhub *hub;
 498
 499         BUG_ON(vmhub >= adev->num_vmhubs);
 500
 501         hub = &adev->vmhub[vmhub];
 502         tmp = gmc_v9_0_get_invalidate_req(vmid, flush_type);
 503
 504         /* This is necessary for a HW workaround under SRIOV as well
 505          * as GFXOFF under bare metal
 506          */
 507         if (adev->gfx.kiq.ring.sched.ready &&
 508                         (amdgpu_sriov_runtime(adev) || !amdgpu_sriov_vf(adev)) &&
 509                         !adev->in_gpu_reset) {
 510                 uint32_t req = hub->vm_inv_eng0_req + eng;
 511                 uint32_t ack = hub->vm_inv_eng0_ack + eng;
 512
 513                 amdgpu_virt_kiq_reg_write_reg_wait(adev, req, ack, tmp,
 514                                 1 << vmid);
 515                 return;
 516         }
 517
 518         spin_lock(&adev->gmc.invalidate_lock);
 519         WREG32_NO_KIQ(hub->vm_inv_eng0_req + eng, tmp);
 520
 521         /*
 522          * Issue a dummy read to wait for the ACK register to be cleared
 523          * to avoid a false ACK due to the new fast GRBM interface.
 524          */
 525         if (vmhub == AMDGPU_GFXHUB_0)
 526                 RREG32_NO_KIQ(hub->vm_inv_eng0_req + eng);
 527
 528         for (j = 0; j < adev->usec_timeout; j++) {
 529                 tmp = RREG32_NO_KIQ(hub->vm_inv_eng0_ack + eng);
 530                 if (tmp & (1 << vmid))
 531                         break;
 532                 udelay(1);
 533         }
 534         spin_unlock(&adev->gmc.invalidate_lock);
 535         if (j < adev->usec_timeout)
 536                 return;
 537
 538         DRM_ERROR("Timeout waiting for VM flush ACK!\n");
 539 }
 540
 541 static uint64_t gmc_v9_0_emit_flush_gpu_tlb(struct amdgpu_ring *ring,
 542                                             unsigned vmid, uint64_t pd_addr)
 543 {
 544         struct amdgpu_device *adev = ring->adev;
 545         struct amdgpu_vmhub *hub = &adev->vmhub[ring->funcs->vmhub];
 546         uint32_t req = gmc_v9_0_get_invalidate_req(vmid, 0);
 547         unsigned eng = ring->vm_inv_eng;
 548
 549         amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_lo32 + (2 * vmid),
 550                               lower_32_bits(pd_addr));
 551
 552         amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_hi32 + (2 * vmid),
 553                               upper_32_bits(pd_addr));
 554
 555         amdgpu_ring_emit_reg_write_reg_wait(ring, hub->vm_inv_eng0_req + eng,
 556                                             hub->vm_inv_eng0_ack + eng,
 557                                             req, 1 << vmid);
 558
 559         return pd_addr;
 560 }
 561
 562 static void gmc_v9_0_emit_pasid_mapping(struct amdgpu_ring *ring, unsigned vmid,
 563                                         unsigned pasid)
 564 {
 565         struct amdgpu_device *adev = ring->adev;
 566         uint32_t reg;
 567
 568         /* Do nothing because there's no lut register for mmhub1. */
 569         if (ring->funcs->vmhub == AMDGPU_MMHUB_1)
 570                 return;
 571
 572         if (ring->funcs->vmhub == AMDGPU_GFXHUB_0)
 573                 reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT) + vmid;
 574         else
 575                 reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT_MM) + vmid;
 576
 577         amdgpu_ring_emit_wreg(ring, reg, pasid);
 578 }
 579
 580 /*
 581  * PTE format on VEGA 10:
 582  * 63:59 reserved
 583  * 58:57 mtype
 584  * 56 F
 585  * 55 L
 586  * 54 P
 587  * 53 SW
 588  * 52 T
 589  * 50:48 reserved
 590  * 47:12 4k physical page base address
 591  * 11:7 fragment
 592  * 6 write
 593  * 5 read
 594  * 4 exe
 595  * 3 Z
 596  * 2 snooped
 597  * 1 system
 598  * 0 valid
 599  *
 600  * PDE format on VEGA 10:
 601  * 63:59 block fragment size
 602  * 58:55 reserved
 603  * 54 P
 604  * 53:48 reserved
 605  * 47:6 physical base address of PD or PTE
 606  * 5:3 reserved
 607  * 2 C
 608  * 1 system
 609  * 0 valid
 610  */
 611
 612 static uint64_t gmc_v9_0_map_mtype(struct amdgpu_device *adev, uint32_t flags)
 613
 614 {
 615         switch (flags) {
 616         case AMDGPU_VM_MTYPE_DEFAULT:
 617                 return AMDGPU_PTE_MTYPE_VG10(MTYPE_NC);
 618         case AMDGPU_VM_MTYPE_NC:
 619                 return AMDGPU_PTE_MTYPE_VG10(MTYPE_NC);
 620         case AMDGPU_VM_MTYPE_WC:
 621                 return AMDGPU_PTE_MTYPE_VG10(MTYPE_WC);
 622         case AMDGPU_VM_MTYPE_RW:
 623                 return AMDGPU_PTE_MTYPE_VG10(MTYPE_RW);
 624         case AMDGPU_VM_MTYPE_CC:
 625                 return AMDGPU_PTE_MTYPE_VG10(MTYPE_CC);
 626         case AMDGPU_VM_MTYPE_UC:
 627                 return AMDGPU_PTE_MTYPE_VG10(MTYPE_UC);
 628         default:
 629                 return AMDGPU_PTE_MTYPE_VG10(MTYPE_NC);
 630         }
 631 }
 632
 633 static void gmc_v9_0_get_vm_pde(struct amdgpu_device *adev, int level,
 634                                 uint64_t *addr, uint64_t *flags)
 635 {
 636         if (!(*flags & AMDGPU_PDE_PTE) && !(*flags & AMDGPU_PTE_SYSTEM))
 637                 *addr = adev->vm_manager.vram_base_offset + *addr -
 638                         adev->gmc.vram_start;
 639         BUG_ON(*addr & 0xFFFF00000000003FULL);
 640
 641         if (!adev->gmc.translate_further)
 642                 return;
 643
 644         if (level == AMDGPU_VM_PDB1) {
 645                 /* Set the block fragment size */
 646                 if (!(*flags & AMDGPU_PDE_PTE))
 647                         *flags |= AMDGPU_PDE_BFS(0x9);
 648
 649         } else if (level == AMDGPU_VM_PDB0) {
 650                 if (*flags & AMDGPU_PDE_PTE)
 651                         *flags &= ~AMDGPU_PDE_PTE;
 652                 else
 653                         *flags |= AMDGPU_PTE_TF;
 654         }
 655 }
 656
 657 static void gmc_v9_0_get_vm_pte(struct amdgpu_device *adev,
 658                                 struct amdgpu_bo_va_mapping *mapping,
 659                                 uint64_t *flags)
 660 {
 661         *flags &= ~AMDGPU_PTE_EXECUTABLE;
 662         *flags |= mapping->flags & AMDGPU_PTE_EXECUTABLE;
 663
 664         *flags &= ~AMDGPU_PTE_MTYPE_VG10_MASK;
 665         *flags |= mapping->flags & AMDGPU_PTE_MTYPE_VG10_MASK;
 666
 667         if (mapping->flags & AMDGPU_PTE_PRT) {
 668                 *flags |= AMDGPU_PTE_PRT;
 669                 *flags &= ~AMDGPU_PTE_VALID;
 670         }
 671
 672         if (adev->asic_type == CHIP_ARCTURUS &&
 673             !(*flags & AMDGPU_PTE_SYSTEM) &&
 674             mapping->bo_va->is_xgmi)
 675                 *flags |= AMDGPU_PTE_SNOOPED;
 676 }
 677
 678 static const struct amdgpu_gmc_funcs gmc_v9_0_gmc_funcs = {
 679         .flush_gpu_tlb = gmc_v9_0_flush_gpu_tlb,
 680         .emit_flush_gpu_tlb = gmc_v9_0_emit_flush_gpu_tlb,
 681         .emit_pasid_mapping = gmc_v9_0_emit_pasid_mapping,
 682         .map_mtype = gmc_v9_0_map_mtype,
 683         .get_vm_pde = gmc_v9_0_get_vm_pde,
 684         .get_vm_pte = gmc_v9_0_get_vm_pte
 685 };
 686
 687 static void gmc_v9_0_set_gmc_funcs(struct amdgpu_device *adev)
 688 {
 689         adev->gmc.gmc_funcs = &gmc_v9_0_gmc_funcs;
 690 }
 691
 692 static void gmc_v9_0_set_umc_funcs(struct amdgpu_device *adev)
 693 {
 694         switch (adev->asic_type) {
 695         case CHIP_VEGA20:
 696                 adev->umc.max_ras_err_cnt_per_query = UMC_V6_1_TOTAL_CHANNEL_NUM;
 697                 adev->umc.channel_inst_num = UMC_V6_1_CHANNEL_INSTANCE_NUM;
 698                 adev->umc.umc_inst_num = UMC_V6_1_UMC_INSTANCE_NUM;
 699                 adev->umc.channel_offs = UMC_V6_1_PER_CHANNEL_OFFSET;
 700                 adev->umc.channel_idx_tbl = &umc_v6_1_channel_idx_tbl[0][0];
 701                 adev->umc.funcs = &umc_v6_1_funcs;
 702                 break;
 703         default:
 704                 break;
 705         }
 706 }
 707
 708 static void gmc_v9_0_set_mmhub_funcs(struct amdgpu_device *adev)
 709 {
 710         switch (adev->asic_type) {
 711         case CHIP_VEGA20:
 712                 adev->mmhub_funcs = &mmhub_v1_0_funcs;
 713                 break;
 714         default:
 715                 break;
 716         }
 717 }
 718
 719 static int gmc_v9_0_early_init(void *handle)
 720 {
 721         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 722
 723         gmc_v9_0_set_gmc_funcs(adev);
 724         gmc_v9_0_set_irq_funcs(adev);
 725         gmc_v9_0_set_umc_funcs(adev);
 726         gmc_v9_0_set_mmhub_funcs(adev);
 727
 728         adev->gmc.shared_aperture_start = 0x2000000000000000ULL;
 729         adev->gmc.shared_aperture_end =
 730                 adev->gmc.shared_aperture_start + (4ULL << 30) - 1;
 731         adev->gmc.private_aperture_start = 0x1000000000000000ULL;
 732         adev->gmc.private_aperture_end =
 733                 adev->gmc.private_aperture_start + (4ULL << 30) - 1;
 734
 735         return 0;
 736 }
 737
 738 static bool gmc_v9_0_keep_stolen_memory(struct amdgpu_device *adev)
 739 {
 740
 741         /*
 742          * TODO:
 743          * Currently there is a bug where some memory client outside
 744          * of the driver writes to first 8M of VRAM on S3 resume,
 745          * this overrides GART which by default gets placed in first 8M and
 746          * causes VM_FAULTS once GTT is accessed.
 747          * Keep the stolen memory reservation until the while this is not solved.
 748          * Also check code in gmc_v9_0_get_vbios_fb_size and gmc_v9_0_late_init
 749          */
 750         switch (adev->asic_type) {
 751         case CHIP_VEGA10:
 752         case CHIP_RAVEN:
 753         case CHIP_ARCTURUS:
 754         case CHIP_RENOIR:
 755                 return true;
 756         case CHIP_VEGA12:
 757         case CHIP_VEGA20:
 758         default:
 759                 return false;
 760         }
 761 }
 762
 763 static int gmc_v9_0_allocate_vm_inv_eng(struct amdgpu_device *adev)
 764 {
 765         struct amdgpu_ring *ring;
 766         unsigned vm_inv_engs[AMDGPU_MAX_VMHUBS] =
 767                 {GFXHUB_FREE_VM_INV_ENGS_BITMAP, MMHUB_FREE_VM_INV_ENGS_BITMAP,
 768                 GFXHUB_FREE_VM_INV_ENGS_BITMAP};
 769         unsigned i;
 770         unsigned vmhub, inv_eng;
 771
 772         for (i = 0; i < adev->num_rings; ++i) {
 773                 ring = adev->rings[i];
 774                 vmhub = ring->funcs->vmhub;
 775
 776                 inv_eng = ffs(vm_inv_engs[vmhub]);
 777                 if (!inv_eng) {
 778                         dev_err(adev->dev, "no VM inv eng for ring %s\n",
 779                                 ring->name);
 780                         return -EINVAL;
 781                 }
 782
 783                 ring->vm_inv_eng = inv_eng - 1;
 784                 vm_inv_engs[vmhub] &= ~(1 << ring->vm_inv_eng);
 785
 786                 dev_info(adev->dev, "ring %s uses VM inv eng %u on hub %u\n",
 787                          ring->name, ring->vm_inv_eng, ring->funcs->vmhub);
 788         }
 789
 790         return 0;
 791 }
 792
 793 static int gmc_v9_0_ecc_late_init(void *handle)
 794 {
 795         int r;
 796         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 797         struct ras_ih_if umc_ih_info = {
 798                 .cb = gmc_v9_0_process_ras_data_cb,
 799         };
 800
 801         if (adev->umc.funcs && adev->umc.funcs->ras_late_init) {
 802                 r = adev->umc.funcs->ras_late_init(adev, &umc_ih_info);
 803                 if (r)
 804                         return r;
 805         }
 806
 807         if (adev->mmhub_funcs && adev->mmhub_funcs->ras_late_init) {
 808                 r = adev->mmhub_funcs->ras_late_init(adev);
 809                 if (r)
 810                         return r;
 811         }
 812
 813         return amdgpu_xgmi_ras_late_init(adev);
 814 }
 815
 816 static int gmc_v9_0_late_init(void *handle)
 817 {
 818         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 819         int r;
 820
 821         if (!gmc_v9_0_keep_stolen_memory(adev))
 822                 amdgpu_bo_late_init(adev);
 823
 824         r = gmc_v9_0_allocate_vm_inv_eng(adev);
 825         if (r)
 826                 return r;
 827         /* Check if ecc is available */
 828         if (!amdgpu_sriov_vf(adev)) {
 829                 switch (adev->asic_type) {
 830                 case CHIP_VEGA10:
 831                 case CHIP_VEGA20:
 832                         r = amdgpu_atomfirmware_mem_ecc_supported(adev);
 833                         if (!r) {
 834                                 DRM_INFO("ECC is not present.\n");
 835                                 if (adev->df_funcs->enable_ecc_force_par_wr_rmw)
 836                                         adev->df_funcs->enable_ecc_force_par_wr_rmw(adev, false);
 837                         } else {
 838                                 DRM_INFO("ECC is active.\n");
 839                         }
 840
 841                         r = amdgpu_atomfirmware_sram_ecc_supported(adev);
 842                         if (!r) {
 843                                 DRM_INFO("SRAM ECC is not present.\n");
 844                         } else {
 845                                 DRM_INFO("SRAM ECC is active.\n");
 846                         }
 847                         break;
 848                 default:
 849                         break;
 850                 }
 851         }
 852
 853         r = gmc_v9_0_ecc_late_init(handle);
 854         if (r)
 855                 return r;
 856
 857         return amdgpu_irq_get(adev, &adev->gmc.vm_fault, 0);
 858 }
 859
 860 static void gmc_v9_0_vram_gtt_location(struct amdgpu_device *adev,
 861                                         struct amdgpu_gmc *mc)
 862 {
 863         u64 base = 0;
 864
 865         if (adev->asic_type == CHIP_ARCTURUS)
 866                 base = mmhub_v9_4_get_fb_location(adev);
 867         else if (!amdgpu_sriov_vf(adev))
 868                 base = mmhub_v1_0_get_fb_location(adev);
 869
 870         /* add the xgmi offset of the physical node */
 871         base += adev->gmc.xgmi.physical_node_id * adev->gmc.xgmi.node_segment_size;
 872         amdgpu_gmc_vram_location(adev, mc, base);
 873         amdgpu_gmc_gart_location(adev, mc);
 874         amdgpu_gmc_agp_location(adev, mc);
 875         /* base offset of vram pages */
 876         adev->vm_manager.vram_base_offset = gfxhub_v1_0_get_mc_fb_offset(adev);
 877
 878         /* XXX: add the xgmi offset of the physical node? */
 879         adev->vm_manager.vram_base_offset +=
 880                 adev->gmc.xgmi.physical_node_id * adev->gmc.xgmi.node_segment_size;
 881 }
 882
 883 /**
 884  * gmc_v9_0_mc_init - initialize the memory controller driver params
 885  *
 886  * @adev: amdgpu_device pointer
 887  *
 888  * Look up the amount of vram, vram width, and decide how to place
 889  * vram and gart within the GPU's physical address space.
 890  * Returns 0 for success.
 891  */
 892 static int gmc_v9_0_mc_init(struct amdgpu_device *adev)
 893 {
 894         int chansize, numchan;
 895         int r;
 896
 897         if (amdgpu_sriov_vf(adev)) {
 898                 /* For Vega10 SR-IOV, vram_width can't be read from ATOM as RAVEN,
 899                  * and DF related registers is not readable, seems hardcord is the
 900                  * only way to set the correct vram_width
 901                  */
 902                 adev->gmc.vram_width = 2048;
 903         } else if (amdgpu_emu_mode != 1) {
 904                 adev->gmc.vram_width = amdgpu_atomfirmware_get_vram_width(adev);
 905         }
 906
 907         if (!adev->gmc.vram_width) {
 908                 /* hbm memory channel size */
 909                 if (adev->flags & AMD_IS_APU)
 910                         chansize = 64;
 911                 else
 912                         chansize = 128;
 913
 914                 numchan = adev->df_funcs->get_hbm_channel_number(adev);
 915                 adev->gmc.vram_width = numchan * chansize;
 916         }
 917
 918         /* size in MB on si */
 919         adev->gmc.mc_vram_size =
 920                 adev->nbio.funcs->get_memsize(adev) * 1024ULL * 1024ULL;
 921         adev->gmc.real_vram_size = adev->gmc.mc_vram_size;
 922
 923         if (!(adev->flags & AMD_IS_APU)) {
 924                 r = amdgpu_device_resize_fb_bar(adev);
 925                 if (r)
 926                         return r;
 927         }
 928         adev->gmc.aper_base = pci_resource_start(adev->pdev, 0);
 929         adev->gmc.aper_size = pci_resource_len(adev->pdev, 0);
 930
 931 #ifdef CONFIG_X86_64
 932         if (adev->flags & AMD_IS_APU) {
 933                 adev->gmc.aper_base = gfxhub_v1_0_get_mc_fb_offset(adev);
 934                 adev->gmc.aper_size = adev->gmc.real_vram_size;
 935         }
 936 #endif
 937         /* In case the PCI BAR is larger than the actual amount of vram */
 938         adev->gmc.visible_vram_size = adev->gmc.aper_size;
 939         if (adev->gmc.visible_vram_size > adev->gmc.real_vram_size)
 940                 adev->gmc.visible_vram_size = adev->gmc.real_vram_size;
 941
 942         /* set the gart size */
 943         if (amdgpu_gart_size == -1) {
 944                 switch (adev->asic_type) {
 945                 case CHIP_VEGA10:  /* all engines support GPUVM */
 946                 case CHIP_VEGA12:  /* all engines support GPUVM */
 947                 case CHIP_VEGA20:
 948                 case CHIP_ARCTURUS:
 949                 default:
 950                         adev->gmc.gart_size = 512ULL << 20;
 951                         break;
 952                 case CHIP_RAVEN:   /* DCE SG support */
 953                 case CHIP_RENOIR:
 954                         adev->gmc.gart_size = 1024ULL << 20;
 955                         break;
 956                 }
 957         } else {
 958                 adev->gmc.gart_size = (u64)amdgpu_gart_size << 20;
 959         }
 960
 961         gmc_v9_0_vram_gtt_location(adev, &adev->gmc);
 962
 963         return 0;
 964 }
 965
 966 static int gmc_v9_0_gart_init(struct amdgpu_device *adev)
 967 {
 968         int r;
 969
 970         if (adev->gart.bo) {
 971                 WARN(1, "VEGA10 PCIE GART already initialized\n");
 972                 return 0;
 973         }
 974         /* Initialize common gart structure */
 975         r = amdgpu_gart_init(adev);
 976         if (r)
 977                 return r;
 978         adev->gart.table_size = adev->gart.num_gpu_pages * 8;
 979         adev->gart.gart_pte_flags = AMDGPU_PTE_MTYPE_VG10(MTYPE_UC) |
 980                                  AMDGPU_PTE_EXECUTABLE;
 981         return amdgpu_gart_table_vram_alloc(adev);
 982 }
 983
 984 static unsigned gmc_v9_0_get_vbios_fb_size(struct amdgpu_device *adev)
 985 {
 986         u32 d1vga_control;
 987         unsigned size;
 988
 989         /*
 990          * TODO Remove once GART corruption is resolved
 991          * Check related code in gmc_v9_0_sw_fini
 992          * */
 993         if (gmc_v9_0_keep_stolen_memory(adev))
 994                 return 9 * 1024 * 1024;
 995
 996         d1vga_control = RREG32_SOC15(DCE, 0, mmD1VGA_CONTROL);
 997         if (REG_GET_FIELD(d1vga_control, D1VGA_CONTROL, D1VGA_MODE_ENABLE)) {
 998                 size = 9 * 1024 * 1024; /* reserve 8MB for vga emulator and 1 MB for FB */
 999         } else {
1000                 u32 viewport;
1001
1002                 switch (adev->asic_type) {
1003                 case CHIP_RAVEN:
1004                 case CHIP_RENOIR:
1005                         viewport = RREG32_SOC15(DCE, 0, mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION);
1006                         size = (REG_GET_FIELD(viewport,
1007                                               HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION, PRI_VIEWPORT_HEIGHT) *
1008                                 REG_GET_FIELD(viewport,
1009                                               HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION, PRI_VIEWPORT_WIDTH) *
1010                                 4);
1011                         break;
1012                 case CHIP_VEGA10:
1013                 case CHIP_VEGA12:
1014                 case CHIP_VEGA20:
1015                 default:
1016                         viewport = RREG32_SOC15(DCE, 0, mmSCL0_VIEWPORT_SIZE);
1017                         size = (REG_GET_FIELD(viewport, SCL0_VIEWPORT_SIZE, VIEWPORT_HEIGHT) *
1018                                 REG_GET_FIELD(viewport, SCL0_VIEWPORT_SIZE, VIEWPORT_WIDTH) *
1019                                 4);
1020                         break;
1021                 }
1022         }
1023         /* return 0 if the pre-OS buffer uses up most of vram */
1024         if ((adev->gmc.real_vram_size - size) < (8 * 1024 * 1024))
1025                 return 0;
1026
1027         return size;
1028 }
1029
1030 static int gmc_v9_0_sw_init(void *handle)
1031 {
1032         int r;
1033         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1034
1035         gfxhub_v1_0_init(adev);
1036         if (adev->asic_type == CHIP_ARCTURUS)
1037                 mmhub_v9_4_init(adev);
1038         else
1039                 mmhub_v1_0_init(adev);
1040
1041         spin_lock_init(&adev->gmc.invalidate_lock);
1042
1043         adev->gmc.vram_type = amdgpu_atomfirmware_get_vram_type(adev);
1044         switch (adev->asic_type) {
1045         case CHIP_RAVEN:
1046                 adev->num_vmhubs = 2;
1047
1048                 if (adev->rev_id == 0x0 || adev->rev_id == 0x1) {
1049                         amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 48);
1050                 } else {
1051                         /* vm_size is 128TB + 512GB for legacy 3-level page support */
1052                         amdgpu_vm_adjust_size(adev, 128 * 1024 + 512, 9, 2, 48);
1053                         adev->gmc.translate_further =
1054                                 adev->vm_manager.num_level > 1;
1055                 }
1056                 break;
1057         case CHIP_VEGA10:
1058         case CHIP_VEGA12:
1059         case CHIP_VEGA20:
1060         case CHIP_RENOIR:
1061                 adev->num_vmhubs = 2;
1062
1063
1064                 /*
1065                  * To fulfill 4-level page support,
1066                  * vm size is 256TB (48bit), maximum size of Vega10,
1067                  * block size 512 (9bit)
1068                  */
1069                 /* sriov restrict max_pfn below AMDGPU_GMC_HOLE */
1070                 if (amdgpu_sriov_vf(adev))
1071                         amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 47);
1072                 else
1073                         amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 48);
1074                 break;
1075         case CHIP_ARCTURUS:
1076                 adev->num_vmhubs = 3;
1077
1078                 /* Keep the vm size same with Vega20 */
1079                 amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 48);
1080                 break;
1081         default:
1082                 break;
1083         }
1084
1085         /* This interrupt is VMC page fault.*/
1086         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VMC, VMC_1_0__SRCID__VM_FAULT,
1087                                 &adev->gmc.vm_fault);
1088         if (r)
1089                 return r;
1090
1091         if (adev->asic_type == CHIP_ARCTURUS) {
1092                 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VMC1, VMC_1_0__SRCID__VM_FAULT,
1093                                         &adev->gmc.vm_fault);
1094                 if (r)
1095                         return r;
1096         }
1097
1098         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_UTCL2, UTCL2_1_0__SRCID__FAULT,
1099                                 &adev->gmc.vm_fault);
1100
1101         if (r)
1102                 return r;
1103
1104         /* interrupt sent to DF. */
1105         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DF, 0,
1106                         &adev->gmc.ecc_irq);
1107         if (r)
1108                 return r;
1109
1110         /* Set the internal MC address mask
1111          * This is the max address of the GPU's
1112          * internal address space.
1113          */
1114         adev->gmc.mc_mask = 0xffffffffffffULL; /* 48 bit MC */
1115
1116         r = dma_set_mask_and_coherent(adev->dev, DMA_BIT_MASK(44));
1117         if (r) {
1118                 printk(KERN_WARNING "amdgpu: No suitable DMA available.\n");
1119                 return r;
1120         }
1121         adev->need_swiotlb = drm_need_swiotlb(44);
1122
1123         if (adev->gmc.xgmi.supported) {
1124                 r = gfxhub_v1_1_get_xgmi_info(adev);
1125                 if (r)
1126                         return r;
1127         }
1128
1129         r = gmc_v9_0_mc_init(adev);
1130         if (r)
1131                 return r;
1132
1133         adev->gmc.stolen_size = gmc_v9_0_get_vbios_fb_size(adev);
1134
1135         /* Memory manager */
1136         r = amdgpu_bo_init(adev);
1137         if (r)
1138                 return r;
1139
1140         r = gmc_v9_0_gart_init(adev);
1141         if (r)
1142                 return r;
1143
1144         /*
1145          * number of VMs
1146          * VMID 0 is reserved for System
1147          * amdgpu graphics/compute will use VMIDs 1-7
1148          * amdkfd will use VMIDs 8-15
1149          */
1150         adev->vm_manager.id_mgr[AMDGPU_GFXHUB_0].num_ids = AMDGPU_NUM_OF_VMIDS;
1151         adev->vm_manager.id_mgr[AMDGPU_MMHUB_0].num_ids = AMDGPU_NUM_OF_VMIDS;
1152         adev->vm_manager.id_mgr[AMDGPU_MMHUB_1].num_ids = AMDGPU_NUM_OF_VMIDS;
1153
1154         amdgpu_vm_manager_init(adev);
1155
1156         return 0;
1157 }
1158
1159 static int gmc_v9_0_sw_fini(void *handle)
1160 {
1161         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1162         void *stolen_vga_buf;
1163
1164         if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__UMC) &&
1165                         adev->gmc.umc_ras_if) {
1166                 struct ras_common_if *ras_if = adev->gmc.umc_ras_if;
1167                 struct ras_ih_if ih_info = {
1168                         .head = *ras_if,
1169                 };
1170
1171                 /* remove fs first */
1172                 amdgpu_ras_debugfs_remove(adev, ras_if);
1173                 amdgpu_ras_sysfs_remove(adev, ras_if);
1174                 /* remove the IH */
1175                 amdgpu_ras_interrupt_remove_handler(adev, &ih_info);
1176                 amdgpu_ras_feature_enable(adev, ras_if, 0);
1177                 kfree(ras_if);
1178         }
1179
1180         if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__MMHUB) &&
1181                         adev->gmc.mmhub_ras_if) {
1182                 struct ras_common_if *ras_if = adev->gmc.mmhub_ras_if;
1183
1184                 /* remove fs and disable ras feature */
1185                 amdgpu_ras_debugfs_remove(adev, ras_if);
1186                 amdgpu_ras_sysfs_remove(adev, ras_if);
1187                 amdgpu_ras_feature_enable(adev, ras_if, 0);
1188                 kfree(ras_if);
1189         }
1190
1191         amdgpu_gem_force_release(adev);
1192         amdgpu_vm_manager_fini(adev);
1193
1194         if (gmc_v9_0_keep_stolen_memory(adev))
1195                 amdgpu_bo_free_kernel(&adev->stolen_vga_memory, NULL, &stolen_vga_buf);
1196
1197         amdgpu_gart_table_vram_free(adev);
1198         amdgpu_bo_fini(adev);
1199         amdgpu_gart_fini(adev);
1200
1201         return 0;
1202 }
1203
1204 static void gmc_v9_0_init_golden_registers(struct amdgpu_device *adev)
1205 {
1206
1207         switch (adev->asic_type) {
1208         case CHIP_VEGA10:
1209                 if (amdgpu_sriov_vf(adev))
1210                         break;
1211                 /* fall through */
1212         case CHIP_VEGA20:
1213                 soc15_program_register_sequence(adev,
1214                                                 golden_settings_mmhub_1_0_0,
1215                                                 ARRAY_SIZE(golden_settings_mmhub_1_0_0));
1216                 soc15_program_register_sequence(adev,
1217                                                 golden_settings_athub_1_0_0,
1218                                                 ARRAY_SIZE(golden_settings_athub_1_0_0));
1219                 break;
1220         case CHIP_VEGA12:
1221                 break;
1222         case CHIP_RAVEN:
1223                 /* TODO for renoir */
1224                 soc15_program_register_sequence(adev,
1225                                                 golden_settings_athub_1_0_0,
1226                                                 ARRAY_SIZE(golden_settings_athub_1_0_0));
1227                 break;
1228         default:
1229                 break;
1230         }
1231 }
1232
1233 /**
1234  * gmc_v9_0_gart_enable - gart enable
1235  *
1236  * @adev: amdgpu_device pointer
1237  */
1238 static int gmc_v9_0_gart_enable(struct amdgpu_device *adev)
1239 {
1240         int r, i;
1241         bool value;
1242         u32 tmp;
1243
1244         amdgpu_device_program_register_sequence(adev,
1245                                                 golden_settings_vega10_hdp,
1246                                                 ARRAY_SIZE(golden_settings_vega10_hdp));
1247
1248         if (adev->gart.bo == NULL) {
1249                 dev_err(adev->dev, "No VRAM object for PCIE GART.\n");
1250                 return -EINVAL;
1251         }
1252         r = amdgpu_gart_table_vram_pin(adev);
1253         if (r)
1254                 return r;
1255
1256         switch (adev->asic_type) {
1257         case CHIP_RAVEN:
1258                 /* TODO for renoir */
1259                 mmhub_v1_0_update_power_gating(adev, true);
1260                 break;
1261         default:
1262                 break;
1263         }
1264
1265         r = gfxhub_v1_0_gart_enable(adev);
1266         if (r)
1267                 return r;
1268
1269         if (adev->asic_type == CHIP_ARCTURUS)
1270                 r = mmhub_v9_4_gart_enable(adev);
1271         else
1272                 r = mmhub_v1_0_gart_enable(adev);
1273         if (r)
1274                 return r;
1275
1276         WREG32_FIELD15(HDP, 0, HDP_MISC_CNTL, FLUSH_INVALIDATE_CACHE, 1);
1277
1278         tmp = RREG32_SOC15(HDP, 0, mmHDP_HOST_PATH_CNTL);
1279         WREG32_SOC15(HDP, 0, mmHDP_HOST_PATH_CNTL, tmp);
1280
1281         WREG32_SOC15(HDP, 0, mmHDP_NONSURFACE_BASE, (adev->gmc.vram_start >> 8));
1282         WREG32_SOC15(HDP, 0, mmHDP_NONSURFACE_BASE_HI, (adev->gmc.vram_start >> 40));
1283
1284         /* After HDP is initialized, flush HDP.*/
1285         adev->nbio.funcs->hdp_flush(adev, NULL);
1286
1287         if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS)
1288                 value = false;
1289         else
1290                 value = true;
1291
1292         gfxhub_v1_0_set_fault_enable_default(adev, value);
1293         if (adev->asic_type == CHIP_ARCTURUS)
1294                 mmhub_v9_4_set_fault_enable_default(adev, value);
1295         else
1296                 mmhub_v1_0_set_fault_enable_default(adev, value);
1297
1298         for (i = 0; i < adev->num_vmhubs; ++i)
1299                 gmc_v9_0_flush_gpu_tlb(adev, 0, i, 0);
1300
1301         DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
1302                  (unsigned)(adev->gmc.gart_size >> 20),
1303                  (unsigned long long)amdgpu_bo_gpu_offset(adev->gart.bo));
1304         adev->gart.ready = true;
1305         return 0;
1306 }
1307
1308 static int gmc_v9_0_hw_init(void *handle)
1309 {
1310         int r;
1311         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1312
1313         /* The sequence of these two function calls matters.*/
1314         gmc_v9_0_init_golden_registers(adev);
1315
1316         if (adev->mode_info.num_crtc) {
1317                 /* Lockout access through VGA aperture*/
1318                 WREG32_FIELD15(DCE, 0, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 1);
1319
1320                 /* disable VGA render */
1321                 WREG32_FIELD15(DCE, 0, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0);
1322         }
1323
1324         r = gmc_v9_0_gart_enable(adev);
1325
1326         return r;
1327 }
1328
1329 /**
1330  * gmc_v9_0_gart_disable - gart disable
1331  *
1332  * @adev: amdgpu_device pointer
1333  *
1334  * This disables all VM page table.
1335  */
1336 static void gmc_v9_0_gart_disable(struct amdgpu_device *adev)
1337 {
1338         gfxhub_v1_0_gart_disable(adev);
1339         if (adev->asic_type == CHIP_ARCTURUS)
1340                 mmhub_v9_4_gart_disable(adev);
1341         else
1342                 mmhub_v1_0_gart_disable(adev);
1343         amdgpu_gart_table_vram_unpin(adev);
1344 }
1345
1346 static int gmc_v9_0_hw_fini(void *handle)
1347 {
1348         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1349
1350         if (amdgpu_sriov_vf(adev)) {
1351                 /* full access mode, so don't touch any GMC register */
1352                 DRM_DEBUG("For SRIOV client, shouldn't do anything.\n");
1353                 return 0;
1354         }
1355
1356         amdgpu_irq_put(adev, &adev->gmc.ecc_irq, 0);
1357         amdgpu_irq_put(adev, &adev->gmc.vm_fault, 0);
1358         gmc_v9_0_gart_disable(adev);
1359
1360         return 0;
1361 }
1362
1363 static int gmc_v9_0_suspend(void *handle)
1364 {
1365         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1366
1367         return gmc_v9_0_hw_fini(adev);
1368 }
1369
1370 static int gmc_v9_0_resume(void *handle)
1371 {
1372         int r;
1373         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1374
1375         r = gmc_v9_0_hw_init(adev);
1376         if (r)
1377                 return r;
1378
1379         amdgpu_vmid_reset_all(adev);
1380
1381         return 0;
1382 }
1383
1384 static bool gmc_v9_0_is_idle(void *handle)
1385 {
1386         /* MC is always ready in GMC v9.*/
1387         return true;
1388 }
1389
1390 static int gmc_v9_0_wait_for_idle(void *handle)
1391 {
1392         /* There is no need to wait for MC idle in GMC v9.*/
1393         return 0;
1394 }
1395
1396 static int gmc_v9_0_soft_reset(void *handle)
1397 {
1398         /* XXX for emulation.*/
1399         return 0;
1400 }
1401
1402 static int gmc_v9_0_set_clockgating_state(void *handle,
1403                                         enum amd_clockgating_state state)
1404 {
1405         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1406
1407         if (adev->asic_type == CHIP_ARCTURUS)
1408                 mmhub_v9_4_set_clockgating(adev, state);
1409         else
1410                 mmhub_v1_0_set_clockgating(adev, state);
1411
1412         athub_v1_0_set_clockgating(adev, state);
1413
1414         return 0;
1415 }
1416
1417 static void gmc_v9_0_get_clockgating_state(void *handle, u32 *flags)
1418 {
1419         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1420
1421         if (adev->asic_type == CHIP_ARCTURUS)
1422                 mmhub_v9_4_get_clockgating(adev, flags);
1423         else
1424                 mmhub_v1_0_get_clockgating(adev, flags);
1425
1426         athub_v1_0_get_clockgating(adev, flags);
1427 }
1428
1429 static int gmc_v9_0_set_powergating_state(void *handle,
1430                                         enum amd_powergating_state state)
1431 {
1432         return 0;
1433 }
1434
1435 const struct amd_ip_funcs gmc_v9_0_ip_funcs = {
1436         .name = "gmc_v9_0",
1437         .early_init = gmc_v9_0_early_init,
1438         .late_init = gmc_v9_0_late_init,
1439         .sw_init = gmc_v9_0_sw_init,
1440         .sw_fini = gmc_v9_0_sw_fini,
1441         .hw_init = gmc_v9_0_hw_init,
1442         .hw_fini = gmc_v9_0_hw_fini,
1443         .suspend = gmc_v9_0_suspend,
1444         .resume = gmc_v9_0_resume,
1445         .is_idle = gmc_v9_0_is_idle,
1446         .wait_for_idle = gmc_v9_0_wait_for_idle,
1447         .soft_reset = gmc_v9_0_soft_reset,
1448         .set_clockgating_state = gmc_v9_0_set_clockgating_state,
1449         .set_powergating_state = gmc_v9_0_set_powergating_state,
1450         .get_clockgating_state = gmc_v9_0_get_clockgating_state,
1451 };
1452
1453 const struct amdgpu_ip_block_version gmc_v9_0_ip_block =
1454 {
1455         .type = AMD_IP_BLOCK_TYPE_GMC,
1456         .major = 9,
1457         .minor = 0,
1458         .rev = 0,
1459         .funcs = &gmc_v9_0_ip_funcs,
1460 };