drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c

   1 /*
   2  * Copyright 2014 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23 #include <linux/firmware.h>
  24 #include <drm/drmP.h>
  25 #include <drm/drm_cache.h>
  26 #include "amdgpu.h"
  27 #include "gmc_v8_0.h"
  28 #include "amdgpu_ucode.h"
  29 #include "amdgpu_amdkfd.h"
  30 #include "amdgpu_gem.h"
  31
  32 #include "gmc/gmc_8_1_d.h"
  33 #include "gmc/gmc_8_1_sh_mask.h"
  34
  35 #include "bif/bif_5_0_d.h"
  36 #include "bif/bif_5_0_sh_mask.h"
  37
  38 #include "oss/oss_3_0_d.h"
  39 #include "oss/oss_3_0_sh_mask.h"
  40
  41 #include "dce/dce_10_0_d.h"
  42 #include "dce/dce_10_0_sh_mask.h"
  43
  44 #include "vid.h"
  45 #include "vi.h"
  46
  47 #include "amdgpu_atombios.h"
  48
  49 #include "ivsrcid/ivsrcid_vislands30.h"
  50
  51 static void gmc_v8_0_set_gmc_funcs(struct amdgpu_device *adev);
  52 static void gmc_v8_0_set_irq_funcs(struct amdgpu_device *adev);
  53 static int gmc_v8_0_wait_for_idle(void *handle);
  54
  55 MODULE_FIRMWARE("amdgpu/tonga_mc.bin");
  56 MODULE_FIRMWARE("amdgpu/polaris11_mc.bin");
  57 MODULE_FIRMWARE("amdgpu/polaris10_mc.bin");
  58 MODULE_FIRMWARE("amdgpu/polaris12_mc.bin");
  59 MODULE_FIRMWARE("amdgpu/polaris11_k_mc.bin");
  60 MODULE_FIRMWARE("amdgpu/polaris10_k_mc.bin");
  61 MODULE_FIRMWARE("amdgpu/polaris12_k_mc.bin");
  62
  63 static const u32 golden_settings_tonga_a11[] =
  64 {
  65         mmMC_ARB_WTM_GRPWT_RD, 0x00000003, 0x00000000,
  66         mmMC_HUB_RDREQ_DMIF_LIMIT, 0x0000007f, 0x00000028,
  67         mmMC_HUB_WDP_UMC, 0x00007fb6, 0x00000991,
  68         mmVM_PRT_APERTURE0_LOW_ADDR, 0x0fffffff, 0x0fffffff,
  69         mmVM_PRT_APERTURE1_LOW_ADDR, 0x0fffffff, 0x0fffffff,
  70         mmVM_PRT_APERTURE2_LOW_ADDR, 0x0fffffff, 0x0fffffff,
  71         mmVM_PRT_APERTURE3_LOW_ADDR, 0x0fffffff, 0x0fffffff,
  72 };
  73
  74 static const u32 tonga_mgcg_cgcg_init[] =
  75 {
  76         mmMC_MEM_POWER_LS, 0xffffffff, 0x00000104
  77 };
  78
  79 static const u32 golden_settings_fiji_a10[] =
  80 {
  81         mmVM_PRT_APERTURE0_LOW_ADDR, 0x0fffffff, 0x0fffffff,
  82         mmVM_PRT_APERTURE1_LOW_ADDR, 0x0fffffff, 0x0fffffff,
  83         mmVM_PRT_APERTURE2_LOW_ADDR, 0x0fffffff, 0x0fffffff,
  84         mmVM_PRT_APERTURE3_LOW_ADDR, 0x0fffffff, 0x0fffffff,
  85 };
  86
  87 static const u32 fiji_mgcg_cgcg_init[] =
  88 {
  89         mmMC_MEM_POWER_LS, 0xffffffff, 0x00000104
  90 };
  91
  92 static const u32 golden_settings_polaris11_a11[] =
  93 {
  94         mmVM_PRT_APERTURE0_LOW_ADDR, 0x0fffffff, 0x0fffffff,
  95         mmVM_PRT_APERTURE1_LOW_ADDR, 0x0fffffff, 0x0fffffff,
  96         mmVM_PRT_APERTURE2_LOW_ADDR, 0x0fffffff, 0x0fffffff,
  97         mmVM_PRT_APERTURE3_LOW_ADDR, 0x0fffffff, 0x0fffffff
  98 };
  99
 100 static const u32 golden_settings_polaris10_a11[] =
 101 {
 102         mmMC_ARB_WTM_GRPWT_RD, 0x00000003, 0x00000000,
 103         mmVM_PRT_APERTURE0_LOW_ADDR, 0x0fffffff, 0x0fffffff,
 104         mmVM_PRT_APERTURE1_LOW_ADDR, 0x0fffffff, 0x0fffffff,
 105         mmVM_PRT_APERTURE2_LOW_ADDR, 0x0fffffff, 0x0fffffff,
 106         mmVM_PRT_APERTURE3_LOW_ADDR, 0x0fffffff, 0x0fffffff
 107 };
 108
 109 static const u32 cz_mgcg_cgcg_init[] =
 110 {
 111         mmMC_MEM_POWER_LS, 0xffffffff, 0x00000104
 112 };
 113
 114 static const u32 stoney_mgcg_cgcg_init[] =
 115 {
 116         mmATC_MISC_CG, 0xffffffff, 0x000c0200,
 117         mmMC_MEM_POWER_LS, 0xffffffff, 0x00000104
 118 };
 119
 120 static const u32 golden_settings_stoney_common[] =
 121 {
 122         mmMC_HUB_RDREQ_UVD, MC_HUB_RDREQ_UVD__PRESCALE_MASK, 0x00000004,
 123         mmMC_RD_GRP_OTH, MC_RD_GRP_OTH__UVD_MASK, 0x00600000
 124 };
 125
 126 static void gmc_v8_0_init_golden_registers(struct amdgpu_device *adev)
 127 {
 128         switch (adev->asic_type) {
 129         case CHIP_FIJI:
 130                 amdgpu_device_program_register_sequence(adev,
 131                                                         fiji_mgcg_cgcg_init,
 132                                                         ARRAY_SIZE(fiji_mgcg_cgcg_init));
 133                 amdgpu_device_program_register_sequence(adev,
 134                                                         golden_settings_fiji_a10,
 135                                                         ARRAY_SIZE(golden_settings_fiji_a10));
 136                 break;
 137         case CHIP_TONGA:
 138                 amdgpu_device_program_register_sequence(adev,
 139                                                         tonga_mgcg_cgcg_init,
 140                                                         ARRAY_SIZE(tonga_mgcg_cgcg_init));
 141                 amdgpu_device_program_register_sequence(adev,
 142                                                         golden_settings_tonga_a11,
 143                                                         ARRAY_SIZE(golden_settings_tonga_a11));
 144                 break;
 145         case CHIP_POLARIS11:
 146         case CHIP_POLARIS12:
 147         case CHIP_VEGAM:
 148                 amdgpu_device_program_register_sequence(adev,
 149                                                         golden_settings_polaris11_a11,
 150                                                         ARRAY_SIZE(golden_settings_polaris11_a11));
 151                 break;
 152         case CHIP_POLARIS10:
 153                 amdgpu_device_program_register_sequence(adev,
 154                                                         golden_settings_polaris10_a11,
 155                                                         ARRAY_SIZE(golden_settings_polaris10_a11));
 156                 break;
 157         case CHIP_CARRIZO:
 158                 amdgpu_device_program_register_sequence(adev,
 159                                                         cz_mgcg_cgcg_init,
 160                                                         ARRAY_SIZE(cz_mgcg_cgcg_init));
 161                 break;
 162         case CHIP_STONEY:
 163                 amdgpu_device_program_register_sequence(adev,
 164                                                         stoney_mgcg_cgcg_init,
 165                                                         ARRAY_SIZE(stoney_mgcg_cgcg_init));
 166                 amdgpu_device_program_register_sequence(adev,
 167                                                         golden_settings_stoney_common,
 168                                                         ARRAY_SIZE(golden_settings_stoney_common));
 169                 break;
 170         default:
 171                 break;
 172         }
 173 }
 174
 175 static void gmc_v8_0_mc_stop(struct amdgpu_device *adev)
 176 {
 177         u32 blackout;
 178
 179         gmc_v8_0_wait_for_idle(adev);
 180
 181         blackout = RREG32(mmMC_SHARED_BLACKOUT_CNTL);
 182         if (REG_GET_FIELD(blackout, MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE) != 1) {
 183                 /* Block CPU access */
 184                 WREG32(mmBIF_FB_EN, 0);
 185                 /* blackout the MC */
 186                 blackout = REG_SET_FIELD(blackout,
 187                                          MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE, 1);
 188                 WREG32(mmMC_SHARED_BLACKOUT_CNTL, blackout);
 189         }
 190         /* wait for the MC to settle */
 191         udelay(100);
 192 }
 193
 194 static void gmc_v8_0_mc_resume(struct amdgpu_device *adev)
 195 {
 196         u32 tmp;
 197
 198         /* unblackout the MC */
 199         tmp = RREG32(mmMC_SHARED_BLACKOUT_CNTL);
 200         tmp = REG_SET_FIELD(tmp, MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE, 0);
 201         WREG32(mmMC_SHARED_BLACKOUT_CNTL, tmp);
 202         /* allow CPU access */
 203         tmp = REG_SET_FIELD(0, BIF_FB_EN, FB_READ_EN, 1);
 204         tmp = REG_SET_FIELD(tmp, BIF_FB_EN, FB_WRITE_EN, 1);
 205         WREG32(mmBIF_FB_EN, tmp);
 206 }
 207
 208 /**
 209  * gmc_v8_0_init_microcode - load ucode images from disk
 210  *
 211  * @adev: amdgpu_device pointer
 212  *
 213  * Use the firmware interface to load the ucode images into
 214  * the driver (not loaded into hw).
 215  * Returns 0 on success, error on failure.
 216  */
 217 static int gmc_v8_0_init_microcode(struct amdgpu_device *adev)
 218 {
 219         const char *chip_name;
 220         char fw_name[30];
 221         int err;
 222
 223         DRM_DEBUG("\n");
 224
 225         switch (adev->asic_type) {
 226         case CHIP_TONGA:
 227                 chip_name = "tonga";
 228                 break;
 229         case CHIP_POLARIS11:
 230                 if (((adev->pdev->device == 0x67ef) &&
 231                      ((adev->pdev->revision == 0xe0) ||
 232                       (adev->pdev->revision == 0xe5))) ||
 233                     ((adev->pdev->device == 0x67ff) &&
 234                      ((adev->pdev->revision == 0xcf) ||
 235                       (adev->pdev->revision == 0xef) ||
 236                       (adev->pdev->revision == 0xff))))
 237                         chip_name = "polaris11_k";
 238                 else if ((adev->pdev->device == 0x67ef) &&
 239                          (adev->pdev->revision == 0xe2))
 240                         chip_name = "polaris11_k";
 241                 else
 242                         chip_name = "polaris11";
 243                 break;
 244         case CHIP_POLARIS10:
 245                 if ((adev->pdev->device == 0x67df) &&
 246                     ((adev->pdev->revision == 0xe1) ||
 247                      (adev->pdev->revision == 0xf7)))
 248                         chip_name = "polaris10_k";
 249                 else
 250                         chip_name = "polaris10";
 251                 break;
 252         case CHIP_POLARIS12:
 253                 if (((adev->pdev->device == 0x6987) &&
 254                      ((adev->pdev->revision == 0xc0) ||
 255                       (adev->pdev->revision == 0xc3))) ||
 256                     ((adev->pdev->device == 0x6981) &&
 257                      ((adev->pdev->revision == 0x00) ||
 258                       (adev->pdev->revision == 0x01) ||
 259                       (adev->pdev->revision == 0x10))))
 260                         chip_name = "polaris12_k";
 261                 else
 262                         chip_name = "polaris12";
 263                 break;
 264         case CHIP_FIJI:
 265         case CHIP_CARRIZO:
 266         case CHIP_STONEY:
 267         case CHIP_VEGAM:
 268                 return 0;
 269         default: BUG();
 270         }
 271
 272         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mc.bin", chip_name);
 273         err = request_firmware(&adev->gmc.fw, fw_name, adev->dev);
 274         if (err)
 275                 goto out;
 276         err = amdgpu_ucode_validate(adev->gmc.fw);
 277
 278 out:
 279         if (err) {
 280                 pr_err("mc: Failed to load firmware \"%s\"\n", fw_name);
 281                 release_firmware(adev->gmc.fw);
 282                 adev->gmc.fw = NULL;
 283         }
 284         return err;
 285 }
 286
 287 /**
 288  * gmc_v8_0_tonga_mc_load_microcode - load tonga MC ucode into the hw
 289  *
 290  * @adev: amdgpu_device pointer
 291  *
 292  * Load the GDDR MC ucode into the hw (CIK).
 293  * Returns 0 on success, error on failure.
 294  */
 295 static int gmc_v8_0_tonga_mc_load_microcode(struct amdgpu_device *adev)
 296 {
 297         const struct mc_firmware_header_v1_0 *hdr;
 298         const __le32 *fw_data = NULL;
 299         const __le32 *io_mc_regs = NULL;
 300         u32 running;
 301         int i, ucode_size, regs_size;
 302
 303         /* Skip MC ucode loading on SR-IOV capable boards.
 304          * vbios does this for us in asic_init in that case.
 305          * Skip MC ucode loading on VF, because hypervisor will do that
 306          * for this adaptor.
 307          */
 308         if (amdgpu_sriov_bios(adev))
 309                 return 0;
 310
 311         if (!adev->gmc.fw)
 312                 return -EINVAL;
 313
 314         hdr = (const struct mc_firmware_header_v1_0 *)adev->gmc.fw->data;
 315         amdgpu_ucode_print_mc_hdr(&hdr->header);
 316
 317         adev->gmc.fw_version = le32_to_cpu(hdr->header.ucode_version);
 318         regs_size = le32_to_cpu(hdr->io_debug_size_bytes) / (4 * 2);
 319         io_mc_regs = (const __le32 *)
 320                 (adev->gmc.fw->data + le32_to_cpu(hdr->io_debug_array_offset_bytes));
 321         ucode_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
 322         fw_data = (const __le32 *)
 323                 (adev->gmc.fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes));
 324
 325         running = REG_GET_FIELD(RREG32(mmMC_SEQ_SUP_CNTL), MC_SEQ_SUP_CNTL, RUN);
 326
 327         if (running == 0) {
 328                 /* reset the engine and set to writable */
 329                 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008);
 330                 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000010);
 331
 332                 /* load mc io regs */
 333                 for (i = 0; i < regs_size; i++) {
 334                         WREG32(mmMC_SEQ_IO_DEBUG_INDEX, le32_to_cpup(io_mc_regs++));
 335                         WREG32(mmMC_SEQ_IO_DEBUG_DATA, le32_to_cpup(io_mc_regs++));
 336                 }
 337                 /* load the MC ucode */
 338                 for (i = 0; i < ucode_size; i++)
 339                         WREG32(mmMC_SEQ_SUP_PGM, le32_to_cpup(fw_data++));
 340
 341                 /* put the engine back into the active state */
 342                 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008);
 343                 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000004);
 344                 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000001);
 345
 346                 /* wait for training to complete */
 347                 for (i = 0; i < adev->usec_timeout; i++) {
 348                         if (REG_GET_FIELD(RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL),
 349                                           MC_SEQ_TRAIN_WAKEUP_CNTL, TRAIN_DONE_D0))
 350                                 break;
 351                         udelay(1);
 352                 }
 353                 for (i = 0; i < adev->usec_timeout; i++) {
 354                         if (REG_GET_FIELD(RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL),
 355                                           MC_SEQ_TRAIN_WAKEUP_CNTL, TRAIN_DONE_D1))
 356                                 break;
 357                         udelay(1);
 358                 }
 359         }
 360
 361         return 0;
 362 }
 363
 364 static int gmc_v8_0_polaris_mc_load_microcode(struct amdgpu_device *adev)
 365 {
 366         const struct mc_firmware_header_v1_0 *hdr;
 367         const __le32 *fw_data = NULL;
 368         const __le32 *io_mc_regs = NULL;
 369         u32 data;
 370         int i, ucode_size, regs_size;
 371
 372         /* Skip MC ucode loading on SR-IOV capable boards.
 373          * vbios does this for us in asic_init in that case.
 374          * Skip MC ucode loading on VF, because hypervisor will do that
 375          * for this adaptor.
 376          */
 377         if (amdgpu_sriov_bios(adev))
 378                 return 0;
 379
 380         if (!adev->gmc.fw)
 381                 return -EINVAL;
 382
 383         hdr = (const struct mc_firmware_header_v1_0 *)adev->gmc.fw->data;
 384         amdgpu_ucode_print_mc_hdr(&hdr->header);
 385
 386         adev->gmc.fw_version = le32_to_cpu(hdr->header.ucode_version);
 387         regs_size = le32_to_cpu(hdr->io_debug_size_bytes) / (4 * 2);
 388         io_mc_regs = (const __le32 *)
 389                 (adev->gmc.fw->data + le32_to_cpu(hdr->io_debug_array_offset_bytes));
 390         ucode_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
 391         fw_data = (const __le32 *)
 392                 (adev->gmc.fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes));
 393
 394         data = RREG32(mmMC_SEQ_MISC0);
 395         data &= ~(0x40);
 396         WREG32(mmMC_SEQ_MISC0, data);
 397
 398         /* load mc io regs */
 399         for (i = 0; i < regs_size; i++) {
 400                 WREG32(mmMC_SEQ_IO_DEBUG_INDEX, le32_to_cpup(io_mc_regs++));
 401                 WREG32(mmMC_SEQ_IO_DEBUG_DATA, le32_to_cpup(io_mc_regs++));
 402         }
 403
 404         WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008);
 405         WREG32(mmMC_SEQ_SUP_CNTL, 0x00000010);
 406
 407         /* load the MC ucode */
 408         for (i = 0; i < ucode_size; i++)
 409                 WREG32(mmMC_SEQ_SUP_PGM, le32_to_cpup(fw_data++));
 410
 411         /* put the engine back into the active state */
 412         WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008);
 413         WREG32(mmMC_SEQ_SUP_CNTL, 0x00000004);
 414         WREG32(mmMC_SEQ_SUP_CNTL, 0x00000001);
 415
 416         /* wait for training to complete */
 417         for (i = 0; i < adev->usec_timeout; i++) {
 418                 data = RREG32(mmMC_SEQ_MISC0);
 419                 if (data & 0x80)
 420                         break;
 421                 udelay(1);
 422         }
 423
 424         return 0;
 425 }
 426
 427 static void gmc_v8_0_vram_gtt_location(struct amdgpu_device *adev,
 428                                        struct amdgpu_gmc *mc)
 429 {
 430         u64 base = 0;
 431
 432         if (!amdgpu_sriov_vf(adev))
 433                 base = RREG32(mmMC_VM_FB_LOCATION) & 0xFFFF;
 434         base <<= 24;
 435
 436         amdgpu_gmc_vram_location(adev, &adev->gmc, base);
 437         amdgpu_gmc_gart_location(adev, mc);
 438 }
 439
 440 /**
 441  * gmc_v8_0_mc_program - program the GPU memory controller
 442  *
 443  * @adev: amdgpu_device pointer
 444  *
 445  * Set the location of vram, gart, and AGP in the GPU's
 446  * physical address space (CIK).
 447  */
 448 static void gmc_v8_0_mc_program(struct amdgpu_device *adev)
 449 {
 450         u32 tmp;
 451         int i, j;
 452
 453         /* Initialize HDP */
 454         for (i = 0, j = 0; i < 32; i++, j += 0x6) {
 455                 WREG32((0xb05 + j), 0x00000000);
 456                 WREG32((0xb06 + j), 0x00000000);
 457                 WREG32((0xb07 + j), 0x00000000);
 458                 WREG32((0xb08 + j), 0x00000000);
 459                 WREG32((0xb09 + j), 0x00000000);
 460         }
 461         WREG32(mmHDP_REG_COHERENCY_FLUSH_CNTL, 0);
 462
 463         if (gmc_v8_0_wait_for_idle((void *)adev)) {
 464                 dev_warn(adev->dev, "Wait for MC idle timedout !\n");
 465         }
 466         if (adev->mode_info.num_crtc) {
 467                 /* Lockout access through VGA aperture*/
 468                 tmp = RREG32(mmVGA_HDP_CONTROL);
 469                 tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 1);
 470                 WREG32(mmVGA_HDP_CONTROL, tmp);
 471
 472                 /* disable VGA render */
 473                 tmp = RREG32(mmVGA_RENDER_CONTROL);
 474                 tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0);
 475                 WREG32(mmVGA_RENDER_CONTROL, tmp);
 476         }
 477         /* Update configuration */
 478         WREG32(mmMC_VM_SYSTEM_APERTURE_LOW_ADDR,
 479                adev->gmc.vram_start >> 12);
 480         WREG32(mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR,
 481                adev->gmc.vram_end >> 12);
 482         WREG32(mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR,
 483                adev->vram_scratch.gpu_addr >> 12);
 484
 485         if (amdgpu_sriov_vf(adev)) {
 486                 tmp = ((adev->gmc.vram_end >> 24) & 0xFFFF) << 16;
 487                 tmp |= ((adev->gmc.vram_start >> 24) & 0xFFFF);
 488                 WREG32(mmMC_VM_FB_LOCATION, tmp);
 489                 /* XXX double check these! */
 490                 WREG32(mmHDP_NONSURFACE_BASE, (adev->gmc.vram_start >> 8));
 491                 WREG32(mmHDP_NONSURFACE_INFO, (2 << 7) | (1 << 30));
 492                 WREG32(mmHDP_NONSURFACE_SIZE, 0x3FFFFFFF);
 493         }
 494
 495         WREG32(mmMC_VM_AGP_BASE, 0);
 496         WREG32(mmMC_VM_AGP_TOP, 0x0FFFFFFF);
 497         WREG32(mmMC_VM_AGP_BOT, 0x0FFFFFFF);
 498         if (gmc_v8_0_wait_for_idle((void *)adev)) {
 499                 dev_warn(adev->dev, "Wait for MC idle timedout !\n");
 500         }
 501
 502         WREG32(mmBIF_FB_EN, BIF_FB_EN__FB_READ_EN_MASK | BIF_FB_EN__FB_WRITE_EN_MASK);
 503
 504         tmp = RREG32(mmHDP_MISC_CNTL);
 505         tmp = REG_SET_FIELD(tmp, HDP_MISC_CNTL, FLUSH_INVALIDATE_CACHE, 0);
 506         WREG32(mmHDP_MISC_CNTL, tmp);
 507
 508         tmp = RREG32(mmHDP_HOST_PATH_CNTL);
 509         WREG32(mmHDP_HOST_PATH_CNTL, tmp);
 510 }
 511
 512 /**
 513  * gmc_v8_0_mc_init - initialize the memory controller driver params
 514  *
 515  * @adev: amdgpu_device pointer
 516  *
 517  * Look up the amount of vram, vram width, and decide how to place
 518  * vram and gart within the GPU's physical address space (CIK).
 519  * Returns 0 for success.
 520  */
 521 static int gmc_v8_0_mc_init(struct amdgpu_device *adev)
 522 {
 523         int r;
 524
 525         adev->gmc.vram_width = amdgpu_atombios_get_vram_width(adev);
 526         if (!adev->gmc.vram_width) {
 527                 u32 tmp;
 528                 int chansize, numchan;
 529
 530                 /* Get VRAM informations */
 531                 tmp = RREG32(mmMC_ARB_RAMCFG);
 532                 if (REG_GET_FIELD(tmp, MC_ARB_RAMCFG, CHANSIZE)) {
 533                         chansize = 64;
 534                 } else {
 535                         chansize = 32;
 536                 }
 537                 tmp = RREG32(mmMC_SHARED_CHMAP);
 538                 switch (REG_GET_FIELD(tmp, MC_SHARED_CHMAP, NOOFCHAN)) {
 539                 case 0:
 540                 default:
 541                         numchan = 1;
 542                         break;
 543                 case 1:
 544                         numchan = 2;
 545                         break;
 546                 case 2:
 547                         numchan = 4;
 548                         break;
 549                 case 3:
 550                         numchan = 8;
 551                         break;
 552                 case 4:
 553                         numchan = 3;
 554                         break;
 555                 case 5:
 556                         numchan = 6;
 557                         break;
 558                 case 6:
 559                         numchan = 10;
 560                         break;
 561                 case 7:
 562                         numchan = 12;
 563                         break;
 564                 case 8:
 565                         numchan = 16;
 566                         break;
 567                 }
 568                 adev->gmc.vram_width = numchan * chansize;
 569         }
 570         /* size in MB on si */
 571         adev->gmc.mc_vram_size = RREG32(mmCONFIG_MEMSIZE) * 1024ULL * 1024ULL;
 572         adev->gmc.real_vram_size = RREG32(mmCONFIG_MEMSIZE) * 1024ULL * 1024ULL;
 573
 574         if (!(adev->flags & AMD_IS_APU)) {
 575                 r = amdgpu_device_resize_fb_bar(adev);
 576                 if (r)
 577                         return r;
 578         }
 579         adev->gmc.aper_base = pci_resource_start(adev->pdev, 0);
 580         adev->gmc.aper_size = pci_resource_len(adev->pdev, 0);
 581
 582 #ifdef CONFIG_X86_64
 583         if (adev->flags & AMD_IS_APU) {
 584                 adev->gmc.aper_base = ((u64)RREG32(mmMC_VM_FB_OFFSET)) << 22;
 585                 adev->gmc.aper_size = adev->gmc.real_vram_size;
 586         }
 587 #endif
 588
 589         /* In case the PCI BAR is larger than the actual amount of vram */
 590         adev->gmc.visible_vram_size = adev->gmc.aper_size;
 591         if (adev->gmc.visible_vram_size > adev->gmc.real_vram_size)
 592                 adev->gmc.visible_vram_size = adev->gmc.real_vram_size;
 593
 594         /* set the gart size */
 595         if (amdgpu_gart_size == -1) {
 596                 switch (adev->asic_type) {
 597                 case CHIP_POLARIS10: /* all engines support GPUVM */
 598                 case CHIP_POLARIS11: /* all engines support GPUVM */
 599                 case CHIP_POLARIS12: /* all engines support GPUVM */
 600                 case CHIP_VEGAM:     /* all engines support GPUVM */
 601                 default:
 602                         adev->gmc.gart_size = 256ULL << 20;
 603                         break;
 604                 case CHIP_TONGA:   /* UVD, VCE do not support GPUVM */
 605                 case CHIP_FIJI:    /* UVD, VCE do not support GPUVM */
 606                 case CHIP_CARRIZO: /* UVD, VCE do not support GPUVM, DCE SG support */
 607                 case CHIP_STONEY:  /* UVD does not support GPUVM, DCE SG support */
 608                         adev->gmc.gart_size = 1024ULL << 20;
 609                         break;
 610                 }
 611         } else {
 612                 adev->gmc.gart_size = (u64)amdgpu_gart_size << 20;
 613         }
 614
 615         gmc_v8_0_vram_gtt_location(adev, &adev->gmc);
 616
 617         return 0;
 618 }
 619
 620 /*
 621  * GART
 622  * VMID 0 is the physical GPU addresses as used by the kernel.
 623  * VMIDs 1-15 are used for userspace clients and are handled
 624  * by the amdgpu vm/hsa code.
 625  */
 626
 627 /**
 628  * gmc_v8_0_flush_gpu_tlb - gart tlb flush callback
 629  *
 630  * @adev: amdgpu_device pointer
 631  * @vmid: vm instance to flush
 632  *
 633  * Flush the TLB for the requested page table (CIK).
 634  */
 635 static void gmc_v8_0_flush_gpu_tlb(struct amdgpu_device *adev,
 636                                 uint32_t vmid, uint32_t flush_type)
 637 {
 638         /* bits 0-15 are the VM contexts0-15 */
 639         WREG32(mmVM_INVALIDATE_REQUEST, 1 << vmid);
 640 }
 641
 642 static uint64_t gmc_v8_0_emit_flush_gpu_tlb(struct amdgpu_ring *ring,
 643                                             unsigned vmid, uint64_t pd_addr)
 644 {
 645         uint32_t reg;
 646
 647         if (vmid < 8)
 648                 reg = mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + vmid;
 649         else
 650                 reg = mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + vmid - 8;
 651         amdgpu_ring_emit_wreg(ring, reg, pd_addr >> 12);
 652
 653         /* bits 0-15 are the VM contexts0-15 */
 654         amdgpu_ring_emit_wreg(ring, mmVM_INVALIDATE_REQUEST, 1 << vmid);
 655
 656         return pd_addr;
 657 }
 658
 659 static void gmc_v8_0_emit_pasid_mapping(struct amdgpu_ring *ring, unsigned vmid,
 660                                         unsigned pasid)
 661 {
 662         amdgpu_ring_emit_wreg(ring, mmIH_VMID_0_LUT + vmid, pasid);
 663 }
 664
 665 /**
 666  * gmc_v8_0_set_pte_pde - update the page tables using MMIO
 667  *
 668  * @adev: amdgpu_device pointer
 669  * @cpu_pt_addr: cpu address of the page table
 670  * @gpu_page_idx: entry in the page table to update
 671  * @addr: dst addr to write into pte/pde
 672  * @flags: access flags
 673  *
 674  * Update the page tables using the CPU.
 675  */
 676 static int gmc_v8_0_set_pte_pde(struct amdgpu_device *adev, void *cpu_pt_addr,
 677                                 uint32_t gpu_page_idx, uint64_t addr,
 678                                 uint64_t flags)
 679 {
 680         void __iomem *ptr = (void *)cpu_pt_addr;
 681         uint64_t value;
 682
 683         /*
 684          * PTE format on VI:
 685          * 63:40 reserved
 686          * 39:12 4k physical page base address
 687          * 11:7 fragment
 688          * 6 write
 689          * 5 read
 690          * 4 exe
 691          * 3 reserved
 692          * 2 snooped
 693          * 1 system
 694          * 0 valid
 695          *
 696          * PDE format on VI:
 697          * 63:59 block fragment size
 698          * 58:40 reserved
 699          * 39:1 physical base address of PTE
 700          * bits 5:1 must be 0.
 701          * 0 valid
 702          */
 703         value = addr & 0x000000FFFFFFF000ULL;
 704         value |= flags;
 705         writeq(value, ptr + (gpu_page_idx * 8));
 706
 707         return 0;
 708 }
 709
 710 static uint64_t gmc_v8_0_get_vm_pte_flags(struct amdgpu_device *adev,
 711                                           uint32_t flags)
 712 {
 713         uint64_t pte_flag = 0;
 714
 715         if (flags & AMDGPU_VM_PAGE_EXECUTABLE)
 716                 pte_flag |= AMDGPU_PTE_EXECUTABLE;
 717         if (flags & AMDGPU_VM_PAGE_READABLE)
 718                 pte_flag |= AMDGPU_PTE_READABLE;
 719         if (flags & AMDGPU_VM_PAGE_WRITEABLE)
 720                 pte_flag |= AMDGPU_PTE_WRITEABLE;
 721         if (flags & AMDGPU_VM_PAGE_PRT)
 722                 pte_flag |= AMDGPU_PTE_PRT;
 723
 724         return pte_flag;
 725 }
 726
 727 static void gmc_v8_0_get_vm_pde(struct amdgpu_device *adev, int level,
 728                                 uint64_t *addr, uint64_t *flags)
 729 {
 730         BUG_ON(*addr & 0xFFFFFF0000000FFFULL);
 731 }
 732
 733 /**
 734  * gmc_v8_0_set_fault_enable_default - update VM fault handling
 735  *
 736  * @adev: amdgpu_device pointer
 737  * @value: true redirects VM faults to the default page
 738  */
 739 static void gmc_v8_0_set_fault_enable_default(struct amdgpu_device *adev,
 740                                               bool value)
 741 {
 742         u32 tmp;
 743
 744         tmp = RREG32(mmVM_CONTEXT1_CNTL);
 745         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 746                             RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 747         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 748                             DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 749         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 750                             PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 751         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 752                             VALID_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 753         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 754                             READ_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 755         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 756                             WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 757         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 758                             EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 759         WREG32(mmVM_CONTEXT1_CNTL, tmp);
 760 }
 761
 762 /**
 763  * gmc_v8_0_set_prt - set PRT VM fault
 764  *
 765  * @adev: amdgpu_device pointer
 766  * @enable: enable/disable VM fault handling for PRT
 767 */
 768 static void gmc_v8_0_set_prt(struct amdgpu_device *adev, bool enable)
 769 {
 770         u32 tmp;
 771
 772         if (enable && !adev->gmc.prt_warning) {
 773                 dev_warn(adev->dev, "Disabling VM faults because of PRT request!\n");
 774                 adev->gmc.prt_warning = true;
 775         }
 776
 777         tmp = RREG32(mmVM_PRT_CNTL);
 778         tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
 779                             CB_DISABLE_READ_FAULT_ON_UNMAPPED_ACCESS, enable);
 780         tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
 781                             CB_DISABLE_WRITE_FAULT_ON_UNMAPPED_ACCESS, enable);
 782         tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
 783                             TC_DISABLE_READ_FAULT_ON_UNMAPPED_ACCESS, enable);
 784         tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
 785                             TC_DISABLE_WRITE_FAULT_ON_UNMAPPED_ACCESS, enable);
 786         tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
 787                             L2_CACHE_STORE_INVALID_ENTRIES, enable);
 788         tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
 789                             L1_TLB_STORE_INVALID_ENTRIES, enable);
 790         tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
 791                             MASK_PDE0_FAULT, enable);
 792         WREG32(mmVM_PRT_CNTL, tmp);
 793
 794         if (enable) {
 795                 uint32_t low = AMDGPU_VA_RESERVED_SIZE >> AMDGPU_GPU_PAGE_SHIFT;
 796                 uint32_t high = adev->vm_manager.max_pfn -
 797                         (AMDGPU_VA_RESERVED_SIZE >> AMDGPU_GPU_PAGE_SHIFT);
 798
 799                 WREG32(mmVM_PRT_APERTURE0_LOW_ADDR, low);
 800                 WREG32(mmVM_PRT_APERTURE1_LOW_ADDR, low);
 801                 WREG32(mmVM_PRT_APERTURE2_LOW_ADDR, low);
 802                 WREG32(mmVM_PRT_APERTURE3_LOW_ADDR, low);
 803                 WREG32(mmVM_PRT_APERTURE0_HIGH_ADDR, high);
 804                 WREG32(mmVM_PRT_APERTURE1_HIGH_ADDR, high);
 805                 WREG32(mmVM_PRT_APERTURE2_HIGH_ADDR, high);
 806                 WREG32(mmVM_PRT_APERTURE3_HIGH_ADDR, high);
 807         } else {
 808                 WREG32(mmVM_PRT_APERTURE0_LOW_ADDR, 0xfffffff);
 809                 WREG32(mmVM_PRT_APERTURE1_LOW_ADDR, 0xfffffff);
 810                 WREG32(mmVM_PRT_APERTURE2_LOW_ADDR, 0xfffffff);
 811                 WREG32(mmVM_PRT_APERTURE3_LOW_ADDR, 0xfffffff);
 812                 WREG32(mmVM_PRT_APERTURE0_HIGH_ADDR, 0x0);
 813                 WREG32(mmVM_PRT_APERTURE1_HIGH_ADDR, 0x0);
 814                 WREG32(mmVM_PRT_APERTURE2_HIGH_ADDR, 0x0);
 815                 WREG32(mmVM_PRT_APERTURE3_HIGH_ADDR, 0x0);
 816         }
 817 }
 818
 819 /**
 820  * gmc_v8_0_gart_enable - gart enable
 821  *
 822  * @adev: amdgpu_device pointer
 823  *
 824  * This sets up the TLBs, programs the page tables for VMID0,
 825  * sets up the hw for VMIDs 1-15 which are allocated on
 826  * demand, and sets up the global locations for the LDS, GDS,
 827  * and GPUVM for FSA64 clients (CIK).
 828  * Returns 0 for success, errors for failure.
 829  */
 830 static int gmc_v8_0_gart_enable(struct amdgpu_device *adev)
 831 {
 832         uint64_t table_addr;
 833         int r, i;
 834         u32 tmp, field;
 835
 836         if (adev->gart.bo == NULL) {
 837                 dev_err(adev->dev, "No VRAM object for PCIE GART.\n");
 838                 return -EINVAL;
 839         }
 840         r = amdgpu_gart_table_vram_pin(adev);
 841         if (r)
 842                 return r;
 843
 844         table_addr = amdgpu_bo_gpu_offset(adev->gart.bo);
 845
 846         /* Setup TLB control */
 847         tmp = RREG32(mmMC_VM_MX_L1_TLB_CNTL);
 848         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1);
 849         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_FRAGMENT_PROCESSING, 1);
 850         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3);
 851         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_ADVANCED_DRIVER_MODEL, 1);
 852         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, SYSTEM_APERTURE_UNMAPPED_ACCESS, 0);
 853         WREG32(mmMC_VM_MX_L1_TLB_CNTL, tmp);
 854         /* Setup L2 cache */
 855         tmp = RREG32(mmVM_L2_CNTL);
 856         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 1);
 857         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 1);
 858         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE, 1);
 859         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE, 1);
 860         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, EFFECTIVE_L2_QUEUE_SIZE, 7);
 861         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1);
 862         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY, 1);
 863         WREG32(mmVM_L2_CNTL, tmp);
 864         tmp = RREG32(mmVM_L2_CNTL2);
 865         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1);
 866         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_L2_CACHE, 1);
 867         WREG32(mmVM_L2_CNTL2, tmp);
 868
 869         field = adev->vm_manager.fragment_size;
 870         tmp = RREG32(mmVM_L2_CNTL3);
 871         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY, 1);
 872         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, field);
 873         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, L2_CACHE_BIGK_FRAGMENT_SIZE, field);
 874         WREG32(mmVM_L2_CNTL3, tmp);
 875         /* XXX: set to enable PTE/PDE in system memory */
 876         tmp = RREG32(mmVM_L2_CNTL4);
 877         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PDE_REQUEST_PHYSICAL, 0);
 878         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PDE_REQUEST_SHARED, 0);
 879         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PDE_REQUEST_SNOOP, 0);
 880         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PTE_REQUEST_PHYSICAL, 0);
 881         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PTE_REQUEST_SHARED, 0);
 882         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PTE_REQUEST_SNOOP, 0);
 883         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PDE_REQUEST_PHYSICAL, 0);
 884         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PDE_REQUEST_SHARED, 0);
 885         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PDE_REQUEST_SNOOP, 0);
 886         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PTE_REQUEST_PHYSICAL, 0);
 887         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PTE_REQUEST_SHARED, 0);
 888         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PTE_REQUEST_SNOOP, 0);
 889         WREG32(mmVM_L2_CNTL4, tmp);
 890         /* setup context0 */
 891         WREG32(mmVM_CONTEXT0_PAGE_TABLE_START_ADDR, adev->gmc.gart_start >> 12);
 892         WREG32(mmVM_CONTEXT0_PAGE_TABLE_END_ADDR, adev->gmc.gart_end >> 12);
 893         WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR, table_addr >> 12);
 894         WREG32(mmVM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
 895                         (u32)(adev->dummy_page_addr >> 12));
 896         WREG32(mmVM_CONTEXT0_CNTL2, 0);
 897         tmp = RREG32(mmVM_CONTEXT0_CNTL);
 898         tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1);
 899         tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0);
 900         tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 901         WREG32(mmVM_CONTEXT0_CNTL, tmp);
 902
 903         WREG32(mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR, 0);
 904         WREG32(mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR, 0);
 905         WREG32(mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET, 0);
 906
 907         /* empty context1-15 */
 908         /* FIXME start with 4G, once using 2 level pt switch to full
 909          * vm size space
 910          */
 911         /* set vm size, must be a multiple of 4 */
 912         WREG32(mmVM_CONTEXT1_PAGE_TABLE_START_ADDR, 0);
 913         WREG32(mmVM_CONTEXT1_PAGE_TABLE_END_ADDR, adev->vm_manager.max_pfn - 1);
 914         for (i = 1; i < 16; i++) {
 915                 if (i < 8)
 916                         WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + i,
 917                                table_addr >> 12);
 918                 else
 919                         WREG32(mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + i - 8,
 920                                table_addr >> 12);
 921         }
 922
 923         /* enable context1-15 */
 924         WREG32(mmVM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR,
 925                (u32)(adev->dummy_page_addr >> 12));
 926         WREG32(mmVM_CONTEXT1_CNTL2, 4);
 927         tmp = RREG32(mmVM_CONTEXT1_CNTL);
 928         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1);
 929         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH, 1);
 930         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 931         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 932         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 933         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, VALID_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 934         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, READ_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 935         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 936         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 937         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_BLOCK_SIZE,
 938                             adev->vm_manager.block_size - 9);
 939         WREG32(mmVM_CONTEXT1_CNTL, tmp);
 940         if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS)
 941                 gmc_v8_0_set_fault_enable_default(adev, false);
 942         else
 943                 gmc_v8_0_set_fault_enable_default(adev, true);
 944
 945         gmc_v8_0_flush_gpu_tlb(adev, 0, 0);
 946         DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
 947                  (unsigned)(adev->gmc.gart_size >> 20),
 948                  (unsigned long long)table_addr);
 949         adev->gart.ready = true;
 950         return 0;
 951 }
 952
 953 static int gmc_v8_0_gart_init(struct amdgpu_device *adev)
 954 {
 955         int r;
 956
 957         if (adev->gart.bo) {
 958                 WARN(1, "R600 PCIE GART already initialized\n");
 959                 return 0;
 960         }
 961         /* Initialize common gart structure */
 962         r = amdgpu_gart_init(adev);
 963         if (r)
 964                 return r;
 965         adev->gart.table_size = adev->gart.num_gpu_pages * 8;
 966         adev->gart.gart_pte_flags = AMDGPU_PTE_EXECUTABLE;
 967         return amdgpu_gart_table_vram_alloc(adev);
 968 }
 969
 970 /**
 971  * gmc_v8_0_gart_disable - gart disable
 972  *
 973  * @adev: amdgpu_device pointer
 974  *
 975  * This disables all VM page table (CIK).
 976  */
 977 static void gmc_v8_0_gart_disable(struct amdgpu_device *adev)
 978 {
 979         u32 tmp;
 980
 981         /* Disable all tables */
 982         WREG32(mmVM_CONTEXT0_CNTL, 0);
 983         WREG32(mmVM_CONTEXT1_CNTL, 0);
 984         /* Setup TLB control */
 985         tmp = RREG32(mmMC_VM_MX_L1_TLB_CNTL);
 986         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0);
 987         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_FRAGMENT_PROCESSING, 0);
 988         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_ADVANCED_DRIVER_MODEL, 0);
 989         WREG32(mmMC_VM_MX_L1_TLB_CNTL, tmp);
 990         /* Setup L2 cache */
 991         tmp = RREG32(mmVM_L2_CNTL);
 992         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 0);
 993         WREG32(mmVM_L2_CNTL, tmp);
 994         WREG32(mmVM_L2_CNTL2, 0);
 995         amdgpu_gart_table_vram_unpin(adev);
 996 }
 997
 998 /**
 999  * gmc_v8_0_vm_decode_fault - print human readable fault info
1000  *
1001  * @adev: amdgpu_device pointer
1002  * @status: VM_CONTEXT1_PROTECTION_FAULT_STATUS register value
1003  * @addr: VM_CONTEXT1_PROTECTION_FAULT_ADDR register value
1004  *
1005  * Print human readable fault information (CIK).
1006  */
1007 static void gmc_v8_0_vm_decode_fault(struct amdgpu_device *adev, u32 status,
1008                                      u32 addr, u32 mc_client, unsigned pasid)
1009 {
1010         u32 vmid = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, VMID);
1011         u32 protections = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS,
1012                                         PROTECTIONS);
1013         char block[5] = { mc_client >> 24, (mc_client >> 16) & 0xff,
1014                 (mc_client >> 8) & 0xff, mc_client & 0xff, 0 };
1015         u32 mc_id;
1016
1017         mc_id = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS,
1018                               MEMORY_CLIENT_ID);
1019
1020         dev_err(adev->dev, "VM fault (0x%02x, vmid %d, pasid %d) at page %u, %s from '%s' (0x%08x) (%d)\n",
1021                protections, vmid, pasid, addr,
1022                REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS,
1023                              MEMORY_CLIENT_RW) ?
1024                "write" : "read", block, mc_client, mc_id);
1025 }
1026
1027 static int gmc_v8_0_convert_vram_type(int mc_seq_vram_type)
1028 {
1029         switch (mc_seq_vram_type) {
1030         case MC_SEQ_MISC0__MT__GDDR1:
1031                 return AMDGPU_VRAM_TYPE_GDDR1;
1032         case MC_SEQ_MISC0__MT__DDR2:
1033                 return AMDGPU_VRAM_TYPE_DDR2;
1034         case MC_SEQ_MISC0__MT__GDDR3:
1035                 return AMDGPU_VRAM_TYPE_GDDR3;
1036         case MC_SEQ_MISC0__MT__GDDR4:
1037                 return AMDGPU_VRAM_TYPE_GDDR4;
1038         case MC_SEQ_MISC0__MT__GDDR5:
1039                 return AMDGPU_VRAM_TYPE_GDDR5;
1040         case MC_SEQ_MISC0__MT__HBM:
1041                 return AMDGPU_VRAM_TYPE_HBM;
1042         case MC_SEQ_MISC0__MT__DDR3:
1043                 return AMDGPU_VRAM_TYPE_DDR3;
1044         default:
1045                 return AMDGPU_VRAM_TYPE_UNKNOWN;
1046         }
1047 }
1048
1049 static int gmc_v8_0_early_init(void *handle)
1050 {
1051         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1052
1053         gmc_v8_0_set_gmc_funcs(adev);
1054         gmc_v8_0_set_irq_funcs(adev);
1055
1056         adev->gmc.shared_aperture_start = 0x2000000000000000ULL;
1057         adev->gmc.shared_aperture_end =
1058                 adev->gmc.shared_aperture_start + (4ULL << 30) - 1;
1059         adev->gmc.private_aperture_start =
1060                 adev->gmc.shared_aperture_end + 1;
1061         adev->gmc.private_aperture_end =
1062                 adev->gmc.private_aperture_start + (4ULL << 30) - 1;
1063
1064         return 0;
1065 }
1066
1067 static int gmc_v8_0_late_init(void *handle)
1068 {
1069         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1070
1071         amdgpu_bo_late_init(adev);
1072
1073         if (amdgpu_vm_fault_stop != AMDGPU_VM_FAULT_STOP_ALWAYS)
1074                 return amdgpu_irq_get(adev, &adev->gmc.vm_fault, 0);
1075         else
1076                 return 0;
1077 }
1078
1079 static unsigned gmc_v8_0_get_vbios_fb_size(struct amdgpu_device *adev)
1080 {
1081         u32 d1vga_control = RREG32(mmD1VGA_CONTROL);
1082         unsigned size;
1083
1084         if (REG_GET_FIELD(d1vga_control, D1VGA_CONTROL, D1VGA_MODE_ENABLE)) {
1085                 size = 9 * 1024 * 1024; /* reserve 8MB for vga emulator and 1 MB for FB */
1086         } else {
1087                 u32 viewport = RREG32(mmVIEWPORT_SIZE);
1088                 size = (REG_GET_FIELD(viewport, VIEWPORT_SIZE, VIEWPORT_HEIGHT) *
1089                         REG_GET_FIELD(viewport, VIEWPORT_SIZE, VIEWPORT_WIDTH) *
1090                         4);
1091         }
1092         /* return 0 if the pre-OS buffer uses up most of vram */
1093         if ((adev->gmc.real_vram_size - size) < (8 * 1024 * 1024))
1094                 return 0;
1095         return size;
1096 }
1097
1098 #define mmMC_SEQ_MISC0_FIJI 0xA71
1099
1100 static int gmc_v8_0_sw_init(void *handle)
1101 {
1102         int r;
1103         int dma_bits;
1104         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1105
1106         if (adev->flags & AMD_IS_APU) {
1107                 adev->gmc.vram_type = AMDGPU_VRAM_TYPE_UNKNOWN;
1108         } else {
1109                 u32 tmp;
1110
1111                 if ((adev->asic_type == CHIP_FIJI) ||
1112                     (adev->asic_type == CHIP_VEGAM))
1113                         tmp = RREG32(mmMC_SEQ_MISC0_FIJI);
1114                 else
1115                         tmp = RREG32(mmMC_SEQ_MISC0);
1116                 tmp &= MC_SEQ_MISC0__MT__MASK;
1117                 adev->gmc.vram_type = gmc_v8_0_convert_vram_type(tmp);
1118         }
1119
1120         r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_GFX_PAGE_INV_FAULT, &adev->gmc.vm_fault);
1121         if (r)
1122                 return r;
1123
1124         r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_GFX_MEM_PROT_FAULT, &adev->gmc.vm_fault);
1125         if (r)
1126                 return r;
1127
1128         /* Adjust VM size here.
1129          * Currently set to 4GB ((1 << 20) 4k pages).
1130          * Max GPUVM size for cayman and SI is 40 bits.
1131          */
1132         amdgpu_vm_adjust_size(adev, 64, 9, 1, 40);
1133
1134         /* Set the internal MC address mask
1135          * This is the max address of the GPU's
1136          * internal address space.
1137          */
1138         adev->gmc.mc_mask = 0xffffffffffULL; /* 40 bit MC */
1139
1140         /* set DMA mask + need_dma32 flags.
1141          * PCIE - can handle 40-bits.
1142          * IGP - can handle 40-bits
1143          * PCI - dma32 for legacy pci gart, 40 bits on newer asics
1144          */
1145         adev->need_dma32 = false;
1146         dma_bits = adev->need_dma32 ? 32 : 40;
1147         r = pci_set_dma_mask(adev->pdev, DMA_BIT_MASK(dma_bits));
1148         if (r) {
1149                 adev->need_dma32 = true;
1150                 dma_bits = 32;
1151                 pr_warn("amdgpu: No suitable DMA available\n");
1152         }
1153         r = pci_set_consistent_dma_mask(adev->pdev, DMA_BIT_MASK(dma_bits));
1154         if (r) {
1155                 pci_set_consistent_dma_mask(adev->pdev, DMA_BIT_MASK(32));
1156                 pr_warn("amdgpu: No coherent DMA available\n");
1157         }
1158         adev->need_swiotlb = drm_get_max_iomem() > ((u64)1 << dma_bits);
1159
1160         r = gmc_v8_0_init_microcode(adev);
1161         if (r) {
1162                 DRM_ERROR("Failed to load mc firmware!\n");
1163                 return r;
1164         }
1165
1166         r = gmc_v8_0_mc_init(adev);
1167         if (r)
1168                 return r;
1169
1170         adev->gmc.stolen_size = gmc_v8_0_get_vbios_fb_size(adev);
1171
1172         /* Memory manager */
1173         r = amdgpu_bo_init(adev);
1174         if (r)
1175                 return r;
1176
1177         r = gmc_v8_0_gart_init(adev);
1178         if (r)
1179                 return r;
1180
1181         /*
1182          * number of VMs
1183          * VMID 0 is reserved for System
1184          * amdgpu graphics/compute will use VMIDs 1-7
1185          * amdkfd will use VMIDs 8-15
1186          */
1187         adev->vm_manager.id_mgr[0].num_ids = AMDGPU_NUM_OF_VMIDS;
1188         amdgpu_vm_manager_init(adev);
1189
1190         /* base offset of vram pages */
1191         if (adev->flags & AMD_IS_APU) {
1192                 u64 tmp = RREG32(mmMC_VM_FB_OFFSET);
1193
1194                 tmp <<= 22;
1195                 adev->vm_manager.vram_base_offset = tmp;
1196         } else {
1197                 adev->vm_manager.vram_base_offset = 0;
1198         }
1199
1200         adev->gmc.vm_fault_info = kmalloc(sizeof(struct kfd_vm_fault_info),
1201                                         GFP_KERNEL);
1202         if (!adev->gmc.vm_fault_info)
1203                 return -ENOMEM;
1204         atomic_set(&adev->gmc.vm_fault_info_updated, 0);
1205
1206         return 0;
1207 }
1208
1209 static int gmc_v8_0_sw_fini(void *handle)
1210 {
1211         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1212
1213         amdgpu_gem_force_release(adev);
1214         amdgpu_vm_manager_fini(adev);
1215         kfree(adev->gmc.vm_fault_info);
1216         amdgpu_gart_table_vram_free(adev);
1217         amdgpu_bo_fini(adev);
1218         amdgpu_gart_fini(adev);
1219         release_firmware(adev->gmc.fw);
1220         adev->gmc.fw = NULL;
1221
1222         return 0;
1223 }
1224
1225 static int gmc_v8_0_hw_init(void *handle)
1226 {
1227         int r;
1228         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1229
1230         gmc_v8_0_init_golden_registers(adev);
1231
1232         gmc_v8_0_mc_program(adev);
1233
1234         if (adev->asic_type == CHIP_TONGA) {
1235                 r = gmc_v8_0_tonga_mc_load_microcode(adev);
1236                 if (r) {
1237                         DRM_ERROR("Failed to load MC firmware!\n");
1238                         return r;
1239                 }
1240         } else if (adev->asic_type == CHIP_POLARIS11 ||
1241                         adev->asic_type == CHIP_POLARIS10 ||
1242                         adev->asic_type == CHIP_POLARIS12) {
1243                 r = gmc_v8_0_polaris_mc_load_microcode(adev);
1244                 if (r) {
1245                         DRM_ERROR("Failed to load MC firmware!\n");
1246                         return r;
1247                 }
1248         }
1249
1250         r = gmc_v8_0_gart_enable(adev);
1251         if (r)
1252                 return r;
1253
1254         return r;
1255 }
1256
1257 static int gmc_v8_0_hw_fini(void *handle)
1258 {
1259         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1260
1261         amdgpu_irq_put(adev, &adev->gmc.vm_fault, 0);
1262         gmc_v8_0_gart_disable(adev);
1263
1264         return 0;
1265 }
1266
1267 static int gmc_v8_0_suspend(void *handle)
1268 {
1269         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1270
1271         gmc_v8_0_hw_fini(adev);
1272
1273         return 0;
1274 }
1275
1276 static int gmc_v8_0_resume(void *handle)
1277 {
1278         int r;
1279         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1280
1281         r = gmc_v8_0_hw_init(adev);
1282         if (r)
1283                 return r;
1284
1285         amdgpu_vmid_reset_all(adev);
1286
1287         return 0;
1288 }
1289
1290 static bool gmc_v8_0_is_idle(void *handle)
1291 {
1292         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1293         u32 tmp = RREG32(mmSRBM_STATUS);
1294
1295         if (tmp & (SRBM_STATUS__MCB_BUSY_MASK | SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK |
1296                    SRBM_STATUS__MCC_BUSY_MASK | SRBM_STATUS__MCD_BUSY_MASK | SRBM_STATUS__VMC_BUSY_MASK))
1297                 return false;
1298
1299         return true;
1300 }
1301
1302 static int gmc_v8_0_wait_for_idle(void *handle)
1303 {
1304         unsigned i;
1305         u32 tmp;
1306         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1307
1308         for (i = 0; i < adev->usec_timeout; i++) {
1309                 /* read MC_STATUS */
1310                 tmp = RREG32(mmSRBM_STATUS) & (SRBM_STATUS__MCB_BUSY_MASK |
1311                                                SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK |
1312                                                SRBM_STATUS__MCC_BUSY_MASK |
1313                                                SRBM_STATUS__MCD_BUSY_MASK |
1314                                                SRBM_STATUS__VMC_BUSY_MASK |
1315                                                SRBM_STATUS__VMC1_BUSY_MASK);
1316                 if (!tmp)
1317                         return 0;
1318                 udelay(1);
1319         }
1320         return -ETIMEDOUT;
1321
1322 }
1323
1324 static bool gmc_v8_0_check_soft_reset(void *handle)
1325 {
1326         u32 srbm_soft_reset = 0;
1327         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1328         u32 tmp = RREG32(mmSRBM_STATUS);
1329
1330         if (tmp & SRBM_STATUS__VMC_BUSY_MASK)
1331                 srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset,
1332                                                 SRBM_SOFT_RESET, SOFT_RESET_VMC, 1);
1333
1334         if (tmp & (SRBM_STATUS__MCB_BUSY_MASK | SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK |
1335                    SRBM_STATUS__MCC_BUSY_MASK | SRBM_STATUS__MCD_BUSY_MASK)) {
1336                 if (!(adev->flags & AMD_IS_APU))
1337                         srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset,
1338                                                         SRBM_SOFT_RESET, SOFT_RESET_MC, 1);
1339         }
1340         if (srbm_soft_reset) {
1341                 adev->gmc.srbm_soft_reset = srbm_soft_reset;
1342                 return true;
1343         } else {
1344                 adev->gmc.srbm_soft_reset = 0;
1345                 return false;
1346         }
1347 }
1348
1349 static int gmc_v8_0_pre_soft_reset(void *handle)
1350 {
1351         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1352
1353         if (!adev->gmc.srbm_soft_reset)
1354                 return 0;
1355
1356         gmc_v8_0_mc_stop(adev);
1357         if (gmc_v8_0_wait_for_idle(adev)) {
1358                 dev_warn(adev->dev, "Wait for GMC idle timed out !\n");
1359         }
1360
1361         return 0;
1362 }
1363
1364 static int gmc_v8_0_soft_reset(void *handle)
1365 {
1366         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1367         u32 srbm_soft_reset;
1368
1369         if (!adev->gmc.srbm_soft_reset)
1370                 return 0;
1371         srbm_soft_reset = adev->gmc.srbm_soft_reset;
1372
1373         if (srbm_soft_reset) {
1374                 u32 tmp;
1375
1376                 tmp = RREG32(mmSRBM_SOFT_RESET);
1377                 tmp |= srbm_soft_reset;
1378                 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
1379                 WREG32(mmSRBM_SOFT_RESET, tmp);
1380                 tmp = RREG32(mmSRBM_SOFT_RESET);
1381
1382                 udelay(50);
1383
1384                 tmp &= ~srbm_soft_reset;
1385                 WREG32(mmSRBM_SOFT_RESET, tmp);
1386                 tmp = RREG32(mmSRBM_SOFT_RESET);
1387
1388                 /* Wait a little for things to settle down */
1389                 udelay(50);
1390         }
1391
1392         return 0;
1393 }
1394
1395 static int gmc_v8_0_post_soft_reset(void *handle)
1396 {
1397         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1398
1399         if (!adev->gmc.srbm_soft_reset)
1400                 return 0;
1401
1402         gmc_v8_0_mc_resume(adev);
1403         return 0;
1404 }
1405
1406 static int gmc_v8_0_vm_fault_interrupt_state(struct amdgpu_device *adev,
1407                                              struct amdgpu_irq_src *src,
1408                                              unsigned type,
1409                                              enum amdgpu_interrupt_state state)
1410 {
1411         u32 tmp;
1412         u32 bits = (VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1413                     VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1414                     VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1415                     VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1416                     VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1417                     VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1418                     VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK);
1419
1420         switch (state) {
1421         case AMDGPU_IRQ_STATE_DISABLE:
1422                 /* system context */
1423                 tmp = RREG32(mmVM_CONTEXT0_CNTL);
1424                 tmp &= ~bits;
1425                 WREG32(mmVM_CONTEXT0_CNTL, tmp);
1426                 /* VMs */
1427                 tmp = RREG32(mmVM_CONTEXT1_CNTL);
1428                 tmp &= ~bits;
1429                 WREG32(mmVM_CONTEXT1_CNTL, tmp);
1430                 break;
1431         case AMDGPU_IRQ_STATE_ENABLE:
1432                 /* system context */
1433                 tmp = RREG32(mmVM_CONTEXT0_CNTL);
1434                 tmp |= bits;
1435                 WREG32(mmVM_CONTEXT0_CNTL, tmp);
1436                 /* VMs */
1437                 tmp = RREG32(mmVM_CONTEXT1_CNTL);
1438                 tmp |= bits;
1439                 WREG32(mmVM_CONTEXT1_CNTL, tmp);
1440                 break;
1441         default:
1442                 break;
1443         }
1444
1445         return 0;
1446 }
1447
1448 static int gmc_v8_0_process_interrupt(struct amdgpu_device *adev,
1449                                       struct amdgpu_irq_src *source,
1450                                       struct amdgpu_iv_entry *entry)
1451 {
1452         u32 addr, status, mc_client, vmid;
1453
1454         if (amdgpu_sriov_vf(adev)) {
1455                 dev_err(adev->dev, "GPU fault detected: %d 0x%08x\n",
1456                         entry->src_id, entry->src_data[0]);
1457                 dev_err(adev->dev, " Can't decode VM fault info here on SRIOV VF\n");
1458                 return 0;
1459         }
1460
1461         addr = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_ADDR);
1462         status = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_STATUS);
1463         mc_client = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_MCCLIENT);
1464         /* reset addr and status */
1465         WREG32_P(mmVM_CONTEXT1_CNTL2, 1, ~1);
1466
1467         if (!addr && !status)
1468                 return 0;
1469
1470         if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_FIRST)
1471                 gmc_v8_0_set_fault_enable_default(adev, false);
1472
1473         if (printk_ratelimit()) {
1474                 struct amdgpu_task_info task_info = { 0 };
1475
1476                 amdgpu_vm_get_task_info(adev, entry->pasid, &task_info);
1477
1478                 dev_err(adev->dev, "GPU fault detected: %d 0x%08x for process %s pid %d thread %s pid %d\n",
1479                         entry->src_id, entry->src_data[0], task_info.process_name,
1480                         task_info.tgid, task_info.task_name, task_info.pid);
1481                 dev_err(adev->dev, "  VM_CONTEXT1_PROTECTION_FAULT_ADDR   0x%08X\n",
1482                         addr);
1483                 dev_err(adev->dev, "  VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n",
1484                         status);
1485                 gmc_v8_0_vm_decode_fault(adev, status, addr, mc_client,
1486                                          entry->pasid);
1487         }
1488
1489         vmid = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS,
1490                              VMID);
1491         if (amdgpu_amdkfd_is_kfd_vmid(adev, vmid)
1492                 && !atomic_read(&adev->gmc.vm_fault_info_updated)) {
1493                 struct kfd_vm_fault_info *info = adev->gmc.vm_fault_info;
1494                 u32 protections = REG_GET_FIELD(status,
1495                                         VM_CONTEXT1_PROTECTION_FAULT_STATUS,
1496                                         PROTECTIONS);
1497
1498                 info->vmid = vmid;
1499                 info->mc_id = REG_GET_FIELD(status,
1500                                             VM_CONTEXT1_PROTECTION_FAULT_STATUS,
1501                                             MEMORY_CLIENT_ID);
1502                 info->status = status;
1503                 info->page_addr = addr;
1504                 info->prot_valid = protections & 0x7 ? true : false;
1505                 info->prot_read = protections & 0x8 ? true : false;
1506                 info->prot_write = protections & 0x10 ? true : false;
1507                 info->prot_exec = protections & 0x20 ? true : false;
1508                 mb();
1509                 atomic_set(&adev->gmc.vm_fault_info_updated, 1);
1510         }
1511
1512         return 0;
1513 }
1514
1515 static void fiji_update_mc_medium_grain_clock_gating(struct amdgpu_device *adev,
1516                                                      bool enable)
1517 {
1518         uint32_t data;
1519
1520         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_MGCG)) {
1521                 data = RREG32(mmMC_HUB_MISC_HUB_CG);
1522                 data |= MC_HUB_MISC_HUB_CG__ENABLE_MASK;
1523                 WREG32(mmMC_HUB_MISC_HUB_CG, data);
1524
1525                 data = RREG32(mmMC_HUB_MISC_SIP_CG);
1526                 data |= MC_HUB_MISC_SIP_CG__ENABLE_MASK;
1527                 WREG32(mmMC_HUB_MISC_SIP_CG, data);
1528
1529                 data = RREG32(mmMC_HUB_MISC_VM_CG);
1530                 data |= MC_HUB_MISC_VM_CG__ENABLE_MASK;
1531                 WREG32(mmMC_HUB_MISC_VM_CG, data);
1532
1533                 data = RREG32(mmMC_XPB_CLK_GAT);
1534                 data |= MC_XPB_CLK_GAT__ENABLE_MASK;
1535                 WREG32(mmMC_XPB_CLK_GAT, data);
1536
1537                 data = RREG32(mmATC_MISC_CG);
1538                 data |= ATC_MISC_CG__ENABLE_MASK;
1539                 WREG32(mmATC_MISC_CG, data);
1540
1541                 data = RREG32(mmMC_CITF_MISC_WR_CG);
1542                 data |= MC_CITF_MISC_WR_CG__ENABLE_MASK;
1543                 WREG32(mmMC_CITF_MISC_WR_CG, data);
1544
1545                 data = RREG32(mmMC_CITF_MISC_RD_CG);
1546                 data |= MC_CITF_MISC_RD_CG__ENABLE_MASK;
1547                 WREG32(mmMC_CITF_MISC_RD_CG, data);
1548
1549                 data = RREG32(mmMC_CITF_MISC_VM_CG);
1550                 data |= MC_CITF_MISC_VM_CG__ENABLE_MASK;
1551                 WREG32(mmMC_CITF_MISC_VM_CG, data);
1552
1553                 data = RREG32(mmVM_L2_CG);
1554                 data |= VM_L2_CG__ENABLE_MASK;
1555                 WREG32(mmVM_L2_CG, data);
1556         } else {
1557                 data = RREG32(mmMC_HUB_MISC_HUB_CG);
1558                 data &= ~MC_HUB_MISC_HUB_CG__ENABLE_MASK;
1559                 WREG32(mmMC_HUB_MISC_HUB_CG, data);
1560
1561                 data = RREG32(mmMC_HUB_MISC_SIP_CG);
1562                 data &= ~MC_HUB_MISC_SIP_CG__ENABLE_MASK;
1563                 WREG32(mmMC_HUB_MISC_SIP_CG, data);
1564
1565                 data = RREG32(mmMC_HUB_MISC_VM_CG);
1566                 data &= ~MC_HUB_MISC_VM_CG__ENABLE_MASK;
1567                 WREG32(mmMC_HUB_MISC_VM_CG, data);
1568
1569                 data = RREG32(mmMC_XPB_CLK_GAT);
1570                 data &= ~MC_XPB_CLK_GAT__ENABLE_MASK;
1571                 WREG32(mmMC_XPB_CLK_GAT, data);
1572
1573                 data = RREG32(mmATC_MISC_CG);
1574                 data &= ~ATC_MISC_CG__ENABLE_MASK;
1575                 WREG32(mmATC_MISC_CG, data);
1576
1577                 data = RREG32(mmMC_CITF_MISC_WR_CG);
1578                 data &= ~MC_CITF_MISC_WR_CG__ENABLE_MASK;
1579                 WREG32(mmMC_CITF_MISC_WR_CG, data);
1580
1581                 data = RREG32(mmMC_CITF_MISC_RD_CG);
1582                 data &= ~MC_CITF_MISC_RD_CG__ENABLE_MASK;
1583                 WREG32(mmMC_CITF_MISC_RD_CG, data);
1584
1585                 data = RREG32(mmMC_CITF_MISC_VM_CG);
1586                 data &= ~MC_CITF_MISC_VM_CG__ENABLE_MASK;
1587                 WREG32(mmMC_CITF_MISC_VM_CG, data);
1588
1589                 data = RREG32(mmVM_L2_CG);
1590                 data &= ~VM_L2_CG__ENABLE_MASK;
1591                 WREG32(mmVM_L2_CG, data);
1592         }
1593 }
1594
1595 static void fiji_update_mc_light_sleep(struct amdgpu_device *adev,
1596                                        bool enable)
1597 {
1598         uint32_t data;
1599
1600         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_LS)) {
1601                 data = RREG32(mmMC_HUB_MISC_HUB_CG);
1602                 data |= MC_HUB_MISC_HUB_CG__MEM_LS_ENABLE_MASK;
1603                 WREG32(mmMC_HUB_MISC_HUB_CG, data);
1604
1605                 data = RREG32(mmMC_HUB_MISC_SIP_CG);
1606                 data |= MC_HUB_MISC_SIP_CG__MEM_LS_ENABLE_MASK;
1607                 WREG32(mmMC_HUB_MISC_SIP_CG, data);
1608
1609                 data = RREG32(mmMC_HUB_MISC_VM_CG);
1610                 data |= MC_HUB_MISC_VM_CG__MEM_LS_ENABLE_MASK;
1611                 WREG32(mmMC_HUB_MISC_VM_CG, data);
1612
1613                 data = RREG32(mmMC_XPB_CLK_GAT);
1614                 data |= MC_XPB_CLK_GAT__MEM_LS_ENABLE_MASK;
1615                 WREG32(mmMC_XPB_CLK_GAT, data);
1616
1617                 data = RREG32(mmATC_MISC_CG);
1618                 data |= ATC_MISC_CG__MEM_LS_ENABLE_MASK;
1619                 WREG32(mmATC_MISC_CG, data);
1620
1621                 data = RREG32(mmMC_CITF_MISC_WR_CG);
1622                 data |= MC_CITF_MISC_WR_CG__MEM_LS_ENABLE_MASK;
1623                 WREG32(mmMC_CITF_MISC_WR_CG, data);
1624
1625                 data = RREG32(mmMC_CITF_MISC_RD_CG);
1626                 data |= MC_CITF_MISC_RD_CG__MEM_LS_ENABLE_MASK;
1627                 WREG32(mmMC_CITF_MISC_RD_CG, data);
1628
1629                 data = RREG32(mmMC_CITF_MISC_VM_CG);
1630                 data |= MC_CITF_MISC_VM_CG__MEM_LS_ENABLE_MASK;
1631                 WREG32(mmMC_CITF_MISC_VM_CG, data);
1632
1633                 data = RREG32(mmVM_L2_CG);
1634                 data |= VM_L2_CG__MEM_LS_ENABLE_MASK;
1635                 WREG32(mmVM_L2_CG, data);
1636         } else {
1637                 data = RREG32(mmMC_HUB_MISC_HUB_CG);
1638                 data &= ~MC_HUB_MISC_HUB_CG__MEM_LS_ENABLE_MASK;
1639                 WREG32(mmMC_HUB_MISC_HUB_CG, data);
1640
1641                 data = RREG32(mmMC_HUB_MISC_SIP_CG);
1642                 data &= ~MC_HUB_MISC_SIP_CG__MEM_LS_ENABLE_MASK;
1643                 WREG32(mmMC_HUB_MISC_SIP_CG, data);
1644
1645                 data = RREG32(mmMC_HUB_MISC_VM_CG);
1646                 data &= ~MC_HUB_MISC_VM_CG__MEM_LS_ENABLE_MASK;
1647                 WREG32(mmMC_HUB_MISC_VM_CG, data);
1648
1649                 data = RREG32(mmMC_XPB_CLK_GAT);
1650                 data &= ~MC_XPB_CLK_GAT__MEM_LS_ENABLE_MASK;
1651                 WREG32(mmMC_XPB_CLK_GAT, data);
1652
1653                 data = RREG32(mmATC_MISC_CG);
1654                 data &= ~ATC_MISC_CG__MEM_LS_ENABLE_MASK;
1655                 WREG32(mmATC_MISC_CG, data);
1656
1657                 data = RREG32(mmMC_CITF_MISC_WR_CG);
1658                 data &= ~MC_CITF_MISC_WR_CG__MEM_LS_ENABLE_MASK;
1659                 WREG32(mmMC_CITF_MISC_WR_CG, data);
1660
1661                 data = RREG32(mmMC_CITF_MISC_RD_CG);
1662                 data &= ~MC_CITF_MISC_RD_CG__MEM_LS_ENABLE_MASK;
1663                 WREG32(mmMC_CITF_MISC_RD_CG, data);
1664
1665                 data = RREG32(mmMC_CITF_MISC_VM_CG);
1666                 data &= ~MC_CITF_MISC_VM_CG__MEM_LS_ENABLE_MASK;
1667                 WREG32(mmMC_CITF_MISC_VM_CG, data);
1668
1669                 data = RREG32(mmVM_L2_CG);
1670                 data &= ~VM_L2_CG__MEM_LS_ENABLE_MASK;
1671                 WREG32(mmVM_L2_CG, data);
1672         }
1673 }
1674
1675 static int gmc_v8_0_set_clockgating_state(void *handle,
1676                                           enum amd_clockgating_state state)
1677 {
1678         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1679
1680         if (amdgpu_sriov_vf(adev))
1681                 return 0;
1682
1683         switch (adev->asic_type) {
1684         case CHIP_FIJI:
1685                 fiji_update_mc_medium_grain_clock_gating(adev,
1686                                 state == AMD_CG_STATE_GATE);
1687                 fiji_update_mc_light_sleep(adev,
1688                                 state == AMD_CG_STATE_GATE);
1689                 break;
1690         default:
1691                 break;
1692         }
1693         return 0;
1694 }
1695
1696 static int gmc_v8_0_set_powergating_state(void *handle,
1697                                           enum amd_powergating_state state)
1698 {
1699         return 0;
1700 }
1701
1702 static void gmc_v8_0_get_clockgating_state(void *handle, u32 *flags)
1703 {
1704         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1705         int data;
1706
1707         if (amdgpu_sriov_vf(adev))
1708                 *flags = 0;
1709
1710         /* AMD_CG_SUPPORT_MC_MGCG */
1711         data = RREG32(mmMC_HUB_MISC_HUB_CG);
1712         if (data & MC_HUB_MISC_HUB_CG__ENABLE_MASK)
1713                 *flags |= AMD_CG_SUPPORT_MC_MGCG;
1714
1715         /* AMD_CG_SUPPORT_MC_LS */
1716         if (data & MC_HUB_MISC_HUB_CG__MEM_LS_ENABLE_MASK)
1717                 *flags |= AMD_CG_SUPPORT_MC_LS;
1718 }
1719
1720 static const struct amd_ip_funcs gmc_v8_0_ip_funcs = {
1721         .name = "gmc_v8_0",
1722         .early_init = gmc_v8_0_early_init,
1723         .late_init = gmc_v8_0_late_init,
1724         .sw_init = gmc_v8_0_sw_init,
1725         .sw_fini = gmc_v8_0_sw_fini,
1726         .hw_init = gmc_v8_0_hw_init,
1727         .hw_fini = gmc_v8_0_hw_fini,
1728         .suspend = gmc_v8_0_suspend,
1729         .resume = gmc_v8_0_resume,
1730         .is_idle = gmc_v8_0_is_idle,
1731         .wait_for_idle = gmc_v8_0_wait_for_idle,
1732         .check_soft_reset = gmc_v8_0_check_soft_reset,
1733         .pre_soft_reset = gmc_v8_0_pre_soft_reset,
1734         .soft_reset = gmc_v8_0_soft_reset,
1735         .post_soft_reset = gmc_v8_0_post_soft_reset,
1736         .set_clockgating_state = gmc_v8_0_set_clockgating_state,
1737         .set_powergating_state = gmc_v8_0_set_powergating_state,
1738         .get_clockgating_state = gmc_v8_0_get_clockgating_state,
1739 };
1740
1741 static const struct amdgpu_gmc_funcs gmc_v8_0_gmc_funcs = {
1742         .flush_gpu_tlb = gmc_v8_0_flush_gpu_tlb,
1743         .emit_flush_gpu_tlb = gmc_v8_0_emit_flush_gpu_tlb,
1744         .emit_pasid_mapping = gmc_v8_0_emit_pasid_mapping,
1745         .set_pte_pde = gmc_v8_0_set_pte_pde,
1746         .set_prt = gmc_v8_0_set_prt,
1747         .get_vm_pte_flags = gmc_v8_0_get_vm_pte_flags,
1748         .get_vm_pde = gmc_v8_0_get_vm_pde
1749 };
1750
1751 static const struct amdgpu_irq_src_funcs gmc_v8_0_irq_funcs = {
1752         .set = gmc_v8_0_vm_fault_interrupt_state,
1753         .process = gmc_v8_0_process_interrupt,
1754 };
1755
1756 static void gmc_v8_0_set_gmc_funcs(struct amdgpu_device *adev)
1757 {
1758         adev->gmc.gmc_funcs = &gmc_v8_0_gmc_funcs;
1759 }
1760
1761 static void gmc_v8_0_set_irq_funcs(struct amdgpu_device *adev)
1762 {
1763         adev->gmc.vm_fault.num_types = 1;
1764         adev->gmc.vm_fault.funcs = &gmc_v8_0_irq_funcs;
1765 }
1766
1767 const struct amdgpu_ip_block_version gmc_v8_0_ip_block =
1768 {
1769         .type = AMD_IP_BLOCK_TYPE_GMC,
1770         .major = 8,
1771         .minor = 0,
1772         .rev = 0,
1773         .funcs = &gmc_v8_0_ip_funcs,
1774 };
1775
1776 const struct amdgpu_ip_block_version gmc_v8_1_ip_block =
1777 {
1778         .type = AMD_IP_BLOCK_TYPE_GMC,
1779         .major = 8,
1780         .minor = 1,
1781         .rev = 0,
1782         .funcs = &gmc_v8_0_ip_funcs,
1783 };
1784
1785 const struct amdgpu_ip_block_version gmc_v8_5_ip_block =
1786 {
1787         .type = AMD_IP_BLOCK_TYPE_GMC,
1788         .major = 8,
1789         .minor = 5,
1790         .rev = 0,
1791         .funcs = &gmc_v8_0_ip_funcs,
1792 };