2 * Copyright 2014 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
24 #include <linux/firmware.h>
25 #include <linux/module.h>
26 #include <linux/pci.h>
28 #include <drm/drm_cache.h>
33 #include "amdgpu_ucode.h"
34 #include "amdgpu_amdkfd.h"
35 #include "amdgpu_gem.h"
37 #include "bif/bif_4_1_d.h"
38 #include "bif/bif_4_1_sh_mask.h"
40 #include "gmc/gmc_7_1_d.h"
41 #include "gmc/gmc_7_1_sh_mask.h"
43 #include "oss/oss_2_0_d.h"
44 #include "oss/oss_2_0_sh_mask.h"
46 #include "dce/dce_8_0_d.h"
47 #include "dce/dce_8_0_sh_mask.h"
49 #include "amdgpu_atombios.h"
51 #include "ivsrcid/ivsrcid_vislands30.h"
53 static void gmc_v7_0_set_gmc_funcs(struct amdgpu_device *adev);
54 static void gmc_v7_0_set_irq_funcs(struct amdgpu_device *adev);
55 static int gmc_v7_0_wait_for_idle(void *handle);
57 MODULE_FIRMWARE("amdgpu/bonaire_mc.bin");
58 MODULE_FIRMWARE("amdgpu/hawaii_mc.bin");
59 MODULE_FIRMWARE("amdgpu/topaz_mc.bin");
61 static const u32 golden_settings_iceland_a11[] = {
62 mmVM_PRT_APERTURE0_LOW_ADDR, 0x0fffffff, 0x0fffffff,
63 mmVM_PRT_APERTURE1_LOW_ADDR, 0x0fffffff, 0x0fffffff,
64 mmVM_PRT_APERTURE2_LOW_ADDR, 0x0fffffff, 0x0fffffff,
65 mmVM_PRT_APERTURE3_LOW_ADDR, 0x0fffffff, 0x0fffffff
68 static const u32 iceland_mgcg_cgcg_init[] = {
69 mmMC_MEM_POWER_LS, 0xffffffff, 0x00000104
72 static void gmc_v7_0_init_golden_registers(struct amdgpu_device *adev)
74 switch (adev->asic_type) {
76 amdgpu_device_program_register_sequence(adev,
77 iceland_mgcg_cgcg_init,
78 ARRAY_SIZE(iceland_mgcg_cgcg_init));
79 amdgpu_device_program_register_sequence(adev,
80 golden_settings_iceland_a11,
81 ARRAY_SIZE(golden_settings_iceland_a11));
88 static void gmc_v7_0_mc_stop(struct amdgpu_device *adev)
92 gmc_v7_0_wait_for_idle((void *)adev);
94 blackout = RREG32(mmMC_SHARED_BLACKOUT_CNTL);
95 if (REG_GET_FIELD(blackout, MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE) != 1) {
96 /* Block CPU access */
97 WREG32(mmBIF_FB_EN, 0);
99 blackout = REG_SET_FIELD(blackout,
100 MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE, 0);
101 WREG32(mmMC_SHARED_BLACKOUT_CNTL, blackout | 1);
103 /* wait for the MC to settle */
107 static void gmc_v7_0_mc_resume(struct amdgpu_device *adev)
111 /* unblackout the MC */
112 tmp = RREG32(mmMC_SHARED_BLACKOUT_CNTL);
113 tmp = REG_SET_FIELD(tmp, MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE, 0);
114 WREG32(mmMC_SHARED_BLACKOUT_CNTL, tmp);
115 /* allow CPU access */
116 tmp = REG_SET_FIELD(0, BIF_FB_EN, FB_READ_EN, 1);
117 tmp = REG_SET_FIELD(tmp, BIF_FB_EN, FB_WRITE_EN, 1);
118 WREG32(mmBIF_FB_EN, tmp);
122 * gmc_v7_0_init_microcode - load ucode images from disk
124 * @adev: amdgpu_device pointer
126 * Use the firmware interface to load the ucode images into
127 * the driver (not loaded into hw).
128 * Returns 0 on success, error on failure.
130 static int gmc_v7_0_init_microcode(struct amdgpu_device *adev)
132 const char *chip_name;
138 switch (adev->asic_type) {
140 chip_name = "bonaire";
143 chip_name = "hawaii";
156 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mc.bin", chip_name);
158 err = amdgpu_ucode_request(adev, &adev->gmc.fw, fw_name);
160 pr_err("cik_mc: Failed to load firmware \"%s\"\n", fw_name);
161 amdgpu_ucode_release(&adev->gmc.fw);
167 * gmc_v7_0_mc_load_microcode - load MC ucode into the hw
169 * @adev: amdgpu_device pointer
171 * Load the GDDR MC ucode into the hw (CIK).
172 * Returns 0 on success, error on failure.
174 static int gmc_v7_0_mc_load_microcode(struct amdgpu_device *adev)
176 const struct mc_firmware_header_v1_0 *hdr;
177 const __le32 *fw_data = NULL;
178 const __le32 *io_mc_regs = NULL;
180 int i, ucode_size, regs_size;
185 hdr = (const struct mc_firmware_header_v1_0 *)adev->gmc.fw->data;
186 amdgpu_ucode_print_mc_hdr(&hdr->header);
188 adev->gmc.fw_version = le32_to_cpu(hdr->header.ucode_version);
189 regs_size = le32_to_cpu(hdr->io_debug_size_bytes) / (4 * 2);
190 io_mc_regs = (const __le32 *)
191 (adev->gmc.fw->data + le32_to_cpu(hdr->io_debug_array_offset_bytes));
192 ucode_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
193 fw_data = (const __le32 *)
194 (adev->gmc.fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes));
196 running = REG_GET_FIELD(RREG32(mmMC_SEQ_SUP_CNTL), MC_SEQ_SUP_CNTL, RUN);
199 /* reset the engine and set to writable */
200 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008);
201 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000010);
203 /* load mc io regs */
204 for (i = 0; i < regs_size; i++) {
205 WREG32(mmMC_SEQ_IO_DEBUG_INDEX, le32_to_cpup(io_mc_regs++));
206 WREG32(mmMC_SEQ_IO_DEBUG_DATA, le32_to_cpup(io_mc_regs++));
208 /* load the MC ucode */
209 for (i = 0; i < ucode_size; i++)
210 WREG32(mmMC_SEQ_SUP_PGM, le32_to_cpup(fw_data++));
212 /* put the engine back into the active state */
213 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008);
214 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000004);
215 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000001);
217 /* wait for training to complete */
218 for (i = 0; i < adev->usec_timeout; i++) {
219 if (REG_GET_FIELD(RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL),
220 MC_SEQ_TRAIN_WAKEUP_CNTL, TRAIN_DONE_D0))
224 for (i = 0; i < adev->usec_timeout; i++) {
225 if (REG_GET_FIELD(RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL),
226 MC_SEQ_TRAIN_WAKEUP_CNTL, TRAIN_DONE_D1))
235 static void gmc_v7_0_vram_gtt_location(struct amdgpu_device *adev,
236 struct amdgpu_gmc *mc)
238 u64 base = RREG32(mmMC_VM_FB_LOCATION) & 0xFFFF;
242 amdgpu_gmc_vram_location(adev, mc, base);
243 amdgpu_gmc_gart_location(adev, mc, AMDGPU_GART_PLACEMENT_BEST_FIT);
247 * gmc_v7_0_mc_program - program the GPU memory controller
249 * @adev: amdgpu_device pointer
251 * Set the location of vram, gart, and AGP in the GPU's
252 * physical address space (CIK).
254 static void gmc_v7_0_mc_program(struct amdgpu_device *adev)
260 for (i = 0, j = 0; i < 32; i++, j += 0x6) {
261 WREG32((0xb05 + j), 0x00000000);
262 WREG32((0xb06 + j), 0x00000000);
263 WREG32((0xb07 + j), 0x00000000);
264 WREG32((0xb08 + j), 0x00000000);
265 WREG32((0xb09 + j), 0x00000000);
267 WREG32(mmHDP_REG_COHERENCY_FLUSH_CNTL, 0);
269 if (gmc_v7_0_wait_for_idle((void *)adev))
270 dev_warn(adev->dev, "Wait for MC idle timedout !\n");
272 if (adev->mode_info.num_crtc) {
273 /* Lockout access through VGA aperture*/
274 tmp = RREG32(mmVGA_HDP_CONTROL);
275 tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 1);
276 WREG32(mmVGA_HDP_CONTROL, tmp);
278 /* disable VGA render */
279 tmp = RREG32(mmVGA_RENDER_CONTROL);
280 tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0);
281 WREG32(mmVGA_RENDER_CONTROL, tmp);
283 /* Update configuration */
284 WREG32(mmMC_VM_SYSTEM_APERTURE_LOW_ADDR,
285 adev->gmc.vram_start >> 12);
286 WREG32(mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR,
287 adev->gmc.vram_end >> 12);
288 WREG32(mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR,
289 adev->mem_scratch.gpu_addr >> 12);
290 WREG32(mmMC_VM_AGP_BASE, 0);
291 WREG32(mmMC_VM_AGP_TOP, adev->gmc.agp_end >> 22);
292 WREG32(mmMC_VM_AGP_BOT, adev->gmc.agp_start >> 22);
293 if (gmc_v7_0_wait_for_idle((void *)adev))
294 dev_warn(adev->dev, "Wait for MC idle timedout !\n");
296 WREG32(mmBIF_FB_EN, BIF_FB_EN__FB_READ_EN_MASK | BIF_FB_EN__FB_WRITE_EN_MASK);
298 tmp = RREG32(mmHDP_MISC_CNTL);
299 tmp = REG_SET_FIELD(tmp, HDP_MISC_CNTL, FLUSH_INVALIDATE_CACHE, 0);
300 WREG32(mmHDP_MISC_CNTL, tmp);
302 tmp = RREG32(mmHDP_HOST_PATH_CNTL);
303 WREG32(mmHDP_HOST_PATH_CNTL, tmp);
307 * gmc_v7_0_mc_init - initialize the memory controller driver params
309 * @adev: amdgpu_device pointer
311 * Look up the amount of vram, vram width, and decide how to place
312 * vram and gart within the GPU's physical address space (CIK).
313 * Returns 0 for success.
315 static int gmc_v7_0_mc_init(struct amdgpu_device *adev)
319 adev->gmc.vram_width = amdgpu_atombios_get_vram_width(adev);
320 if (!adev->gmc.vram_width) {
322 int chansize, numchan;
324 /* Get VRAM informations */
325 tmp = RREG32(mmMC_ARB_RAMCFG);
326 if (REG_GET_FIELD(tmp, MC_ARB_RAMCFG, CHANSIZE))
331 tmp = RREG32(mmMC_SHARED_CHMAP);
332 switch (REG_GET_FIELD(tmp, MC_SHARED_CHMAP, NOOFCHAN)) {
362 adev->gmc.vram_width = numchan * chansize;
364 /* size in MB on si */
365 adev->gmc.mc_vram_size = RREG32(mmCONFIG_MEMSIZE) * 1024ULL * 1024ULL;
366 adev->gmc.real_vram_size = RREG32(mmCONFIG_MEMSIZE) * 1024ULL * 1024ULL;
368 if (!(adev->flags & AMD_IS_APU)) {
369 r = amdgpu_device_resize_fb_bar(adev);
373 adev->gmc.aper_base = pci_resource_start(adev->pdev, 0);
374 adev->gmc.aper_size = pci_resource_len(adev->pdev, 0);
377 if ((adev->flags & AMD_IS_APU) &&
378 adev->gmc.real_vram_size > adev->gmc.aper_size &&
379 !amdgpu_passthrough(adev)) {
380 adev->gmc.aper_base = ((u64)RREG32(mmMC_VM_FB_OFFSET)) << 22;
381 adev->gmc.aper_size = adev->gmc.real_vram_size;
385 adev->gmc.visible_vram_size = adev->gmc.aper_size;
387 /* set the gart size */
388 if (amdgpu_gart_size == -1) {
389 switch (adev->asic_type) {
390 case CHIP_TOPAZ: /* no MM engines */
392 adev->gmc.gart_size = 256ULL << 20;
394 #ifdef CONFIG_DRM_AMDGPU_CIK
395 case CHIP_BONAIRE: /* UVD, VCE do not support GPUVM */
396 case CHIP_HAWAII: /* UVD, VCE do not support GPUVM */
397 case CHIP_KAVERI: /* UVD, VCE do not support GPUVM */
398 case CHIP_KABINI: /* UVD, VCE do not support GPUVM */
399 case CHIP_MULLINS: /* UVD, VCE do not support GPUVM */
400 adev->gmc.gart_size = 1024ULL << 20;
405 adev->gmc.gart_size = (u64)amdgpu_gart_size << 20;
408 adev->gmc.gart_size += adev->pm.smu_prv_buffer_size;
409 gmc_v7_0_vram_gtt_location(adev, &adev->gmc);
415 * gmc_v7_0_flush_gpu_tlb_pasid - tlb flush via pasid
417 * @adev: amdgpu_device pointer
418 * @pasid: pasid to be flush
419 * @flush_type: type of flush
420 * @all_hub: flush all hubs
421 * @inst: is used to select which instance of KIQ to use for the invalidation
423 * Flush the TLB for the requested pasid.
425 static void gmc_v7_0_flush_gpu_tlb_pasid(struct amdgpu_device *adev,
426 uint16_t pasid, uint32_t flush_type,
427 bool all_hub, uint32_t inst)
432 for (vmid = 1; vmid < 16; vmid++) {
433 u32 tmp = RREG32(mmATC_VMID0_PASID_MAPPING + vmid);
435 if ((tmp & ATC_VMID0_PASID_MAPPING__VALID_MASK) &&
436 (tmp & ATC_VMID0_PASID_MAPPING__PASID_MASK) == pasid)
440 WREG32(mmVM_INVALIDATE_REQUEST, mask);
441 RREG32(mmVM_INVALIDATE_RESPONSE);
446 * VMID 0 is the physical GPU addresses as used by the kernel.
447 * VMIDs 1-15 are used for userspace clients and are handled
448 * by the amdgpu vm/hsa code.
452 * gmc_v7_0_flush_gpu_tlb - gart tlb flush callback
454 * @adev: amdgpu_device pointer
455 * @vmid: vm instance to flush
456 * @vmhub: which hub to flush
457 * @flush_type: type of flush
459 * Flush the TLB for the requested page table (CIK).
461 static void gmc_v7_0_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid,
462 uint32_t vmhub, uint32_t flush_type)
464 /* bits 0-15 are the VM contexts0-15 */
465 WREG32(mmVM_INVALIDATE_REQUEST, 1 << vmid);
468 static uint64_t gmc_v7_0_emit_flush_gpu_tlb(struct amdgpu_ring *ring,
469 unsigned int vmid, uint64_t pd_addr)
474 reg = mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + vmid;
476 reg = mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + vmid - 8;
477 amdgpu_ring_emit_wreg(ring, reg, pd_addr >> 12);
479 /* bits 0-15 are the VM contexts0-15 */
480 amdgpu_ring_emit_wreg(ring, mmVM_INVALIDATE_REQUEST, 1 << vmid);
485 static void gmc_v7_0_emit_pasid_mapping(struct amdgpu_ring *ring, unsigned int vmid,
488 amdgpu_ring_emit_wreg(ring, mmIH_VMID_0_LUT + vmid, pasid);
491 static void gmc_v7_0_get_vm_pde(struct amdgpu_device *adev, int level,
492 uint64_t *addr, uint64_t *flags)
494 BUG_ON(*addr & 0xFFFFFF0000000FFFULL);
497 static void gmc_v7_0_get_vm_pte(struct amdgpu_device *adev,
498 struct amdgpu_bo_va_mapping *mapping,
501 *flags &= ~AMDGPU_PTE_EXECUTABLE;
502 *flags &= ~AMDGPU_PTE_PRT;
506 * gmc_v7_0_set_fault_enable_default - update VM fault handling
508 * @adev: amdgpu_device pointer
509 * @value: true redirects VM faults to the default page
511 static void gmc_v7_0_set_fault_enable_default(struct amdgpu_device *adev,
516 tmp = RREG32(mmVM_CONTEXT1_CNTL);
517 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
518 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
519 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
520 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
521 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
522 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, value);
523 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
524 VALID_PROTECTION_FAULT_ENABLE_DEFAULT, value);
525 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
526 READ_PROTECTION_FAULT_ENABLE_DEFAULT, value);
527 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
528 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
529 WREG32(mmVM_CONTEXT1_CNTL, tmp);
533 * gmc_v7_0_set_prt - set PRT VM fault
535 * @adev: amdgpu_device pointer
536 * @enable: enable/disable VM fault handling for PRT
538 static void gmc_v7_0_set_prt(struct amdgpu_device *adev, bool enable)
542 if (enable && !adev->gmc.prt_warning) {
543 dev_warn(adev->dev, "Disabling VM faults because of PRT request!\n");
544 adev->gmc.prt_warning = true;
547 tmp = RREG32(mmVM_PRT_CNTL);
548 tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
549 CB_DISABLE_READ_FAULT_ON_UNMAPPED_ACCESS, enable);
550 tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
551 CB_DISABLE_WRITE_FAULT_ON_UNMAPPED_ACCESS, enable);
552 tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
553 TC_DISABLE_READ_FAULT_ON_UNMAPPED_ACCESS, enable);
554 tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
555 TC_DISABLE_WRITE_FAULT_ON_UNMAPPED_ACCESS, enable);
556 tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
557 L2_CACHE_STORE_INVALID_ENTRIES, enable);
558 tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
559 L1_TLB_STORE_INVALID_ENTRIES, enable);
560 tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
561 MASK_PDE0_FAULT, enable);
562 WREG32(mmVM_PRT_CNTL, tmp);
565 uint32_t low = AMDGPU_VA_RESERVED_SIZE >> AMDGPU_GPU_PAGE_SHIFT;
566 uint32_t high = adev->vm_manager.max_pfn -
567 (AMDGPU_VA_RESERVED_SIZE >> AMDGPU_GPU_PAGE_SHIFT);
569 WREG32(mmVM_PRT_APERTURE0_LOW_ADDR, low);
570 WREG32(mmVM_PRT_APERTURE1_LOW_ADDR, low);
571 WREG32(mmVM_PRT_APERTURE2_LOW_ADDR, low);
572 WREG32(mmVM_PRT_APERTURE3_LOW_ADDR, low);
573 WREG32(mmVM_PRT_APERTURE0_HIGH_ADDR, high);
574 WREG32(mmVM_PRT_APERTURE1_HIGH_ADDR, high);
575 WREG32(mmVM_PRT_APERTURE2_HIGH_ADDR, high);
576 WREG32(mmVM_PRT_APERTURE3_HIGH_ADDR, high);
578 WREG32(mmVM_PRT_APERTURE0_LOW_ADDR, 0xfffffff);
579 WREG32(mmVM_PRT_APERTURE1_LOW_ADDR, 0xfffffff);
580 WREG32(mmVM_PRT_APERTURE2_LOW_ADDR, 0xfffffff);
581 WREG32(mmVM_PRT_APERTURE3_LOW_ADDR, 0xfffffff);
582 WREG32(mmVM_PRT_APERTURE0_HIGH_ADDR, 0x0);
583 WREG32(mmVM_PRT_APERTURE1_HIGH_ADDR, 0x0);
584 WREG32(mmVM_PRT_APERTURE2_HIGH_ADDR, 0x0);
585 WREG32(mmVM_PRT_APERTURE3_HIGH_ADDR, 0x0);
590 * gmc_v7_0_gart_enable - gart enable
592 * @adev: amdgpu_device pointer
594 * This sets up the TLBs, programs the page tables for VMID0,
595 * sets up the hw for VMIDs 1-15 which are allocated on
596 * demand, and sets up the global locations for the LDS, GDS,
597 * and GPUVM for FSA64 clients (CIK).
598 * Returns 0 for success, errors for failure.
600 static int gmc_v7_0_gart_enable(struct amdgpu_device *adev)
606 if (adev->gart.bo == NULL) {
607 dev_err(adev->dev, "No VRAM object for PCIE GART.\n");
610 amdgpu_gtt_mgr_recover(&adev->mman.gtt_mgr);
611 table_addr = amdgpu_bo_gpu_offset(adev->gart.bo);
613 /* Setup TLB control */
614 tmp = RREG32(mmMC_VM_MX_L1_TLB_CNTL);
615 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1);
616 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_FRAGMENT_PROCESSING, 1);
617 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3);
618 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_ADVANCED_DRIVER_MODEL, 1);
619 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, SYSTEM_APERTURE_UNMAPPED_ACCESS, 0);
620 WREG32(mmMC_VM_MX_L1_TLB_CNTL, tmp);
622 tmp = RREG32(mmVM_L2_CNTL);
623 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 1);
624 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 1);
625 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE, 1);
626 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE, 1);
627 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, EFFECTIVE_L2_QUEUE_SIZE, 7);
628 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1);
629 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY, 1);
630 WREG32(mmVM_L2_CNTL, tmp);
631 tmp = REG_SET_FIELD(0, VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1);
632 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_L2_CACHE, 1);
633 WREG32(mmVM_L2_CNTL2, tmp);
635 field = adev->vm_manager.fragment_size;
636 tmp = RREG32(mmVM_L2_CNTL3);
637 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY, 1);
638 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, field);
639 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, L2_CACHE_BIGK_FRAGMENT_SIZE, field);
640 WREG32(mmVM_L2_CNTL3, tmp);
642 WREG32(mmVM_CONTEXT0_PAGE_TABLE_START_ADDR, adev->gmc.gart_start >> 12);
643 WREG32(mmVM_CONTEXT0_PAGE_TABLE_END_ADDR, adev->gmc.gart_end >> 12);
644 WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR, table_addr >> 12);
645 WREG32(mmVM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
646 (u32)(adev->dummy_page_addr >> 12));
647 WREG32(mmVM_CONTEXT0_CNTL2, 0);
648 tmp = RREG32(mmVM_CONTEXT0_CNTL);
649 tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1);
650 tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0);
651 tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
652 WREG32(mmVM_CONTEXT0_CNTL, tmp);
658 /* empty context1-15 */
659 /* FIXME start with 4G, once using 2 level pt switch to full
662 /* set vm size, must be a multiple of 4 */
663 WREG32(mmVM_CONTEXT1_PAGE_TABLE_START_ADDR, 0);
664 WREG32(mmVM_CONTEXT1_PAGE_TABLE_END_ADDR, adev->vm_manager.max_pfn - 1);
665 for (i = 1; i < AMDGPU_NUM_VMID; i++) {
667 WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + i,
670 WREG32(mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + i - 8,
674 /* enable context1-15 */
675 WREG32(mmVM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR,
676 (u32)(adev->dummy_page_addr >> 12));
677 WREG32(mmVM_CONTEXT1_CNTL2, 4);
678 tmp = RREG32(mmVM_CONTEXT1_CNTL);
679 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1);
680 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH, 1);
681 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_BLOCK_SIZE,
682 adev->vm_manager.block_size - 9);
683 WREG32(mmVM_CONTEXT1_CNTL, tmp);
684 if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS)
685 gmc_v7_0_set_fault_enable_default(adev, false);
687 gmc_v7_0_set_fault_enable_default(adev, true);
689 if (adev->asic_type == CHIP_KAVERI) {
690 tmp = RREG32(mmCHUB_CONTROL);
692 WREG32(mmCHUB_CONTROL, tmp);
695 gmc_v7_0_flush_gpu_tlb(adev, 0, 0, 0);
696 DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
697 (unsigned int)(adev->gmc.gart_size >> 20),
698 (unsigned long long)table_addr);
702 static int gmc_v7_0_gart_init(struct amdgpu_device *adev)
707 WARN(1, "R600 PCIE GART already initialized\n");
710 /* Initialize common gart structure */
711 r = amdgpu_gart_init(adev);
714 adev->gart.table_size = adev->gart.num_gpu_pages * 8;
715 adev->gart.gart_pte_flags = 0;
716 return amdgpu_gart_table_vram_alloc(adev);
720 * gmc_v7_0_gart_disable - gart disable
722 * @adev: amdgpu_device pointer
724 * This disables all VM page table (CIK).
726 static void gmc_v7_0_gart_disable(struct amdgpu_device *adev)
730 /* Disable all tables */
731 WREG32(mmVM_CONTEXT0_CNTL, 0);
732 WREG32(mmVM_CONTEXT1_CNTL, 0);
733 /* Setup TLB control */
734 tmp = RREG32(mmMC_VM_MX_L1_TLB_CNTL);
735 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0);
736 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_FRAGMENT_PROCESSING, 0);
737 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_ADVANCED_DRIVER_MODEL, 0);
738 WREG32(mmMC_VM_MX_L1_TLB_CNTL, tmp);
740 tmp = RREG32(mmVM_L2_CNTL);
741 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 0);
742 WREG32(mmVM_L2_CNTL, tmp);
743 WREG32(mmVM_L2_CNTL2, 0);
747 * gmc_v7_0_vm_decode_fault - print human readable fault info
749 * @adev: amdgpu_device pointer
750 * @status: VM_CONTEXT1_PROTECTION_FAULT_STATUS register value
751 * @addr: VM_CONTEXT1_PROTECTION_FAULT_ADDR register value
752 * @mc_client: VM_CONTEXT1_PROTECTION_FAULT_MCCLIENT register value
753 * @pasid: debug logging only - no functional use
755 * Print human readable fault information (CIK).
757 static void gmc_v7_0_vm_decode_fault(struct amdgpu_device *adev, u32 status,
758 u32 addr, u32 mc_client, unsigned int pasid)
760 u32 vmid = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, VMID);
761 u32 protections = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS,
763 char block[5] = { mc_client >> 24, (mc_client >> 16) & 0xff,
764 (mc_client >> 8) & 0xff, mc_client & 0xff, 0 };
767 mc_id = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS,
770 dev_err(adev->dev, "VM fault (0x%02x, vmid %d, pasid %d) at page %u, %s from '%s' (0x%08x) (%d)\n",
771 protections, vmid, pasid, addr,
772 REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS,
774 "write" : "read", block, mc_client, mc_id);
778 static const u32 mc_cg_registers[] = {
779 mmMC_HUB_MISC_HUB_CG,
780 mmMC_HUB_MISC_SIP_CG,
784 mmMC_CITF_MISC_WR_CG,
785 mmMC_CITF_MISC_RD_CG,
786 mmMC_CITF_MISC_VM_CG,
790 static const u32 mc_cg_ls_en[] = {
791 MC_HUB_MISC_HUB_CG__MEM_LS_ENABLE_MASK,
792 MC_HUB_MISC_SIP_CG__MEM_LS_ENABLE_MASK,
793 MC_HUB_MISC_VM_CG__MEM_LS_ENABLE_MASK,
794 MC_XPB_CLK_GAT__MEM_LS_ENABLE_MASK,
795 ATC_MISC_CG__MEM_LS_ENABLE_MASK,
796 MC_CITF_MISC_WR_CG__MEM_LS_ENABLE_MASK,
797 MC_CITF_MISC_RD_CG__MEM_LS_ENABLE_MASK,
798 MC_CITF_MISC_VM_CG__MEM_LS_ENABLE_MASK,
799 VM_L2_CG__MEM_LS_ENABLE_MASK,
802 static const u32 mc_cg_en[] = {
803 MC_HUB_MISC_HUB_CG__ENABLE_MASK,
804 MC_HUB_MISC_SIP_CG__ENABLE_MASK,
805 MC_HUB_MISC_VM_CG__ENABLE_MASK,
806 MC_XPB_CLK_GAT__ENABLE_MASK,
807 ATC_MISC_CG__ENABLE_MASK,
808 MC_CITF_MISC_WR_CG__ENABLE_MASK,
809 MC_CITF_MISC_RD_CG__ENABLE_MASK,
810 MC_CITF_MISC_VM_CG__ENABLE_MASK,
811 VM_L2_CG__ENABLE_MASK,
814 static void gmc_v7_0_enable_mc_ls(struct amdgpu_device *adev,
820 for (i = 0; i < ARRAY_SIZE(mc_cg_registers); i++) {
821 orig = data = RREG32(mc_cg_registers[i]);
822 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_LS))
823 data |= mc_cg_ls_en[i];
825 data &= ~mc_cg_ls_en[i];
827 WREG32(mc_cg_registers[i], data);
831 static void gmc_v7_0_enable_mc_mgcg(struct amdgpu_device *adev,
837 for (i = 0; i < ARRAY_SIZE(mc_cg_registers); i++) {
838 orig = data = RREG32(mc_cg_registers[i]);
839 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_MGCG))
842 data &= ~mc_cg_en[i];
844 WREG32(mc_cg_registers[i], data);
848 static void gmc_v7_0_enable_bif_mgls(struct amdgpu_device *adev,
853 orig = data = RREG32_PCIE(ixPCIE_CNTL2);
855 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_BIF_LS)) {
856 data = REG_SET_FIELD(data, PCIE_CNTL2, SLV_MEM_LS_EN, 1);
857 data = REG_SET_FIELD(data, PCIE_CNTL2, MST_MEM_LS_EN, 1);
858 data = REG_SET_FIELD(data, PCIE_CNTL2, REPLAY_MEM_LS_EN, 1);
859 data = REG_SET_FIELD(data, PCIE_CNTL2, SLV_MEM_AGGRESSIVE_LS_EN, 1);
861 data = REG_SET_FIELD(data, PCIE_CNTL2, SLV_MEM_LS_EN, 0);
862 data = REG_SET_FIELD(data, PCIE_CNTL2, MST_MEM_LS_EN, 0);
863 data = REG_SET_FIELD(data, PCIE_CNTL2, REPLAY_MEM_LS_EN, 0);
864 data = REG_SET_FIELD(data, PCIE_CNTL2, SLV_MEM_AGGRESSIVE_LS_EN, 0);
868 WREG32_PCIE(ixPCIE_CNTL2, data);
871 static void gmc_v7_0_enable_hdp_mgcg(struct amdgpu_device *adev,
876 orig = data = RREG32(mmHDP_HOST_PATH_CNTL);
878 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_HDP_MGCG))
879 data = REG_SET_FIELD(data, HDP_HOST_PATH_CNTL, CLOCK_GATING_DIS, 0);
881 data = REG_SET_FIELD(data, HDP_HOST_PATH_CNTL, CLOCK_GATING_DIS, 1);
884 WREG32(mmHDP_HOST_PATH_CNTL, data);
887 static void gmc_v7_0_enable_hdp_ls(struct amdgpu_device *adev,
892 orig = data = RREG32(mmHDP_MEM_POWER_LS);
894 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS))
895 data = REG_SET_FIELD(data, HDP_MEM_POWER_LS, LS_ENABLE, 1);
897 data = REG_SET_FIELD(data, HDP_MEM_POWER_LS, LS_ENABLE, 0);
900 WREG32(mmHDP_MEM_POWER_LS, data);
903 static int gmc_v7_0_convert_vram_type(int mc_seq_vram_type)
905 switch (mc_seq_vram_type) {
906 case MC_SEQ_MISC0__MT__GDDR1:
907 return AMDGPU_VRAM_TYPE_GDDR1;
908 case MC_SEQ_MISC0__MT__DDR2:
909 return AMDGPU_VRAM_TYPE_DDR2;
910 case MC_SEQ_MISC0__MT__GDDR3:
911 return AMDGPU_VRAM_TYPE_GDDR3;
912 case MC_SEQ_MISC0__MT__GDDR4:
913 return AMDGPU_VRAM_TYPE_GDDR4;
914 case MC_SEQ_MISC0__MT__GDDR5:
915 return AMDGPU_VRAM_TYPE_GDDR5;
916 case MC_SEQ_MISC0__MT__HBM:
917 return AMDGPU_VRAM_TYPE_HBM;
918 case MC_SEQ_MISC0__MT__DDR3:
919 return AMDGPU_VRAM_TYPE_DDR3;
921 return AMDGPU_VRAM_TYPE_UNKNOWN;
925 static int gmc_v7_0_early_init(void *handle)
927 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
929 gmc_v7_0_set_gmc_funcs(adev);
930 gmc_v7_0_set_irq_funcs(adev);
932 adev->gmc.shared_aperture_start = 0x2000000000000000ULL;
933 adev->gmc.shared_aperture_end =
934 adev->gmc.shared_aperture_start + (4ULL << 30) - 1;
935 adev->gmc.private_aperture_start =
936 adev->gmc.shared_aperture_end + 1;
937 adev->gmc.private_aperture_end =
938 adev->gmc.private_aperture_start + (4ULL << 30) - 1;
939 adev->gmc.noretry_flags = AMDGPU_VM_NORETRY_FLAGS_TF;
944 static int gmc_v7_0_late_init(void *handle)
946 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
948 if (amdgpu_vm_fault_stop != AMDGPU_VM_FAULT_STOP_ALWAYS)
949 return amdgpu_irq_get(adev, &adev->gmc.vm_fault, 0);
954 static unsigned int gmc_v7_0_get_vbios_fb_size(struct amdgpu_device *adev)
956 u32 d1vga_control = RREG32(mmD1VGA_CONTROL);
959 if (REG_GET_FIELD(d1vga_control, D1VGA_CONTROL, D1VGA_MODE_ENABLE)) {
960 size = AMDGPU_VBIOS_VGA_ALLOCATION;
962 u32 viewport = RREG32(mmVIEWPORT_SIZE);
964 size = (REG_GET_FIELD(viewport, VIEWPORT_SIZE, VIEWPORT_HEIGHT) *
965 REG_GET_FIELD(viewport, VIEWPORT_SIZE, VIEWPORT_WIDTH) *
972 static int gmc_v7_0_sw_init(void *handle)
975 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
977 set_bit(AMDGPU_GFXHUB(0), adev->vmhubs_mask);
979 if (adev->flags & AMD_IS_APU) {
980 adev->gmc.vram_type = AMDGPU_VRAM_TYPE_UNKNOWN;
982 u32 tmp = RREG32(mmMC_SEQ_MISC0);
984 tmp &= MC_SEQ_MISC0__MT__MASK;
985 adev->gmc.vram_type = gmc_v7_0_convert_vram_type(tmp);
988 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_GFX_PAGE_INV_FAULT, &adev->gmc.vm_fault);
992 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_GFX_MEM_PROT_FAULT, &adev->gmc.vm_fault);
996 /* Adjust VM size here.
997 * Currently set to 4GB ((1 << 20) 4k pages).
998 * Max GPUVM size for cayman and SI is 40 bits.
1000 amdgpu_vm_adjust_size(adev, 64, 9, 1, 40);
1002 /* Set the internal MC address mask
1003 * This is the max address of the GPU's
1004 * internal address space.
1006 adev->gmc.mc_mask = 0xffffffffffULL; /* 40 bit MC */
1008 r = dma_set_mask_and_coherent(adev->dev, DMA_BIT_MASK(40));
1010 pr_warn("No suitable DMA available\n");
1013 adev->need_swiotlb = drm_need_swiotlb(40);
1015 r = gmc_v7_0_init_microcode(adev);
1017 DRM_ERROR("Failed to load mc firmware!\n");
1021 r = gmc_v7_0_mc_init(adev);
1025 amdgpu_gmc_get_vbios_allocations(adev);
1027 /* Memory manager */
1028 r = amdgpu_bo_init(adev);
1032 r = gmc_v7_0_gart_init(adev);
1038 * VMID 0 is reserved for System
1039 * amdgpu graphics/compute will use VMIDs 1-7
1040 * amdkfd will use VMIDs 8-15
1042 adev->vm_manager.first_kfd_vmid = 8;
1043 amdgpu_vm_manager_init(adev);
1045 /* base offset of vram pages */
1046 if (adev->flags & AMD_IS_APU) {
1047 u64 tmp = RREG32(mmMC_VM_FB_OFFSET);
1050 adev->vm_manager.vram_base_offset = tmp;
1052 adev->vm_manager.vram_base_offset = 0;
1055 adev->gmc.vm_fault_info = kmalloc(sizeof(struct kfd_vm_fault_info),
1057 if (!adev->gmc.vm_fault_info)
1059 atomic_set(&adev->gmc.vm_fault_info_updated, 0);
1064 static int gmc_v7_0_sw_fini(void *handle)
1066 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1068 amdgpu_gem_force_release(adev);
1069 amdgpu_vm_manager_fini(adev);
1070 kfree(adev->gmc.vm_fault_info);
1071 amdgpu_gart_table_vram_free(adev);
1072 amdgpu_bo_fini(adev);
1073 amdgpu_ucode_release(&adev->gmc.fw);
1078 static int gmc_v7_0_hw_init(void *handle)
1081 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1083 gmc_v7_0_init_golden_registers(adev);
1085 gmc_v7_0_mc_program(adev);
1087 if (!(adev->flags & AMD_IS_APU)) {
1088 r = gmc_v7_0_mc_load_microcode(adev);
1090 DRM_ERROR("Failed to load MC firmware!\n");
1095 r = gmc_v7_0_gart_enable(adev);
1099 if (amdgpu_emu_mode == 1)
1100 return amdgpu_gmc_vram_checking(adev);
1105 static int gmc_v7_0_hw_fini(void *handle)
1107 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1109 amdgpu_irq_put(adev, &adev->gmc.vm_fault, 0);
1110 gmc_v7_0_gart_disable(adev);
1115 static int gmc_v7_0_suspend(void *handle)
1117 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1119 gmc_v7_0_hw_fini(adev);
1124 static int gmc_v7_0_resume(void *handle)
1127 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1129 r = gmc_v7_0_hw_init(adev);
1133 amdgpu_vmid_reset_all(adev);
1138 static bool gmc_v7_0_is_idle(void *handle)
1140 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1141 u32 tmp = RREG32(mmSRBM_STATUS);
1143 if (tmp & (SRBM_STATUS__MCB_BUSY_MASK | SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK |
1144 SRBM_STATUS__MCC_BUSY_MASK | SRBM_STATUS__MCD_BUSY_MASK | SRBM_STATUS__VMC_BUSY_MASK))
1150 static int gmc_v7_0_wait_for_idle(void *handle)
1154 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1156 for (i = 0; i < adev->usec_timeout; i++) {
1157 /* read MC_STATUS */
1158 tmp = RREG32(mmSRBM_STATUS) & (SRBM_STATUS__MCB_BUSY_MASK |
1159 SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK |
1160 SRBM_STATUS__MCC_BUSY_MASK |
1161 SRBM_STATUS__MCD_BUSY_MASK |
1162 SRBM_STATUS__VMC_BUSY_MASK);
1171 static int gmc_v7_0_soft_reset(void *handle)
1173 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1174 u32 srbm_soft_reset = 0;
1175 u32 tmp = RREG32(mmSRBM_STATUS);
1177 if (tmp & SRBM_STATUS__VMC_BUSY_MASK)
1178 srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset,
1179 SRBM_SOFT_RESET, SOFT_RESET_VMC, 1);
1181 if (tmp & (SRBM_STATUS__MCB_BUSY_MASK | SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK |
1182 SRBM_STATUS__MCC_BUSY_MASK | SRBM_STATUS__MCD_BUSY_MASK)) {
1183 if (!(adev->flags & AMD_IS_APU))
1184 srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset,
1185 SRBM_SOFT_RESET, SOFT_RESET_MC, 1);
1188 if (srbm_soft_reset) {
1189 gmc_v7_0_mc_stop(adev);
1190 if (gmc_v7_0_wait_for_idle((void *)adev))
1191 dev_warn(adev->dev, "Wait for GMC idle timed out !\n");
1193 tmp = RREG32(mmSRBM_SOFT_RESET);
1194 tmp |= srbm_soft_reset;
1195 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
1196 WREG32(mmSRBM_SOFT_RESET, tmp);
1197 tmp = RREG32(mmSRBM_SOFT_RESET);
1201 tmp &= ~srbm_soft_reset;
1202 WREG32(mmSRBM_SOFT_RESET, tmp);
1203 tmp = RREG32(mmSRBM_SOFT_RESET);
1205 /* Wait a little for things to settle down */
1208 gmc_v7_0_mc_resume(adev);
1215 static int gmc_v7_0_vm_fault_interrupt_state(struct amdgpu_device *adev,
1216 struct amdgpu_irq_src *src,
1218 enum amdgpu_interrupt_state state)
1221 u32 bits = (VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1222 VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1223 VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1224 VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1225 VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1226 VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK);
1229 case AMDGPU_IRQ_STATE_DISABLE:
1230 /* system context */
1231 tmp = RREG32(mmVM_CONTEXT0_CNTL);
1233 WREG32(mmVM_CONTEXT0_CNTL, tmp);
1235 tmp = RREG32(mmVM_CONTEXT1_CNTL);
1237 WREG32(mmVM_CONTEXT1_CNTL, tmp);
1239 case AMDGPU_IRQ_STATE_ENABLE:
1240 /* system context */
1241 tmp = RREG32(mmVM_CONTEXT0_CNTL);
1243 WREG32(mmVM_CONTEXT0_CNTL, tmp);
1245 tmp = RREG32(mmVM_CONTEXT1_CNTL);
1247 WREG32(mmVM_CONTEXT1_CNTL, tmp);
1256 static int gmc_v7_0_process_interrupt(struct amdgpu_device *adev,
1257 struct amdgpu_irq_src *source,
1258 struct amdgpu_iv_entry *entry)
1260 u32 addr, status, mc_client, vmid;
1262 addr = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_ADDR);
1263 status = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_STATUS);
1264 mc_client = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_MCCLIENT);
1265 /* reset addr and status */
1266 WREG32_P(mmVM_CONTEXT1_CNTL2, 1, ~1);
1268 if (!addr && !status)
1271 amdgpu_vm_update_fault_cache(adev, entry->pasid,
1272 ((u64)addr) << AMDGPU_GPU_PAGE_SHIFT, status, AMDGPU_GFXHUB(0));
1274 if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_FIRST)
1275 gmc_v7_0_set_fault_enable_default(adev, false);
1277 if (printk_ratelimit()) {
1278 dev_err(adev->dev, "GPU fault detected: %d 0x%08x\n",
1279 entry->src_id, entry->src_data[0]);
1280 dev_err(adev->dev, " VM_CONTEXT1_PROTECTION_FAULT_ADDR 0x%08X\n",
1282 dev_err(adev->dev, " VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n",
1284 gmc_v7_0_vm_decode_fault(adev, status, addr, mc_client,
1288 vmid = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS,
1290 if (amdgpu_amdkfd_is_kfd_vmid(adev, vmid)
1291 && !atomic_read(&adev->gmc.vm_fault_info_updated)) {
1292 struct kfd_vm_fault_info *info = adev->gmc.vm_fault_info;
1293 u32 protections = REG_GET_FIELD(status,
1294 VM_CONTEXT1_PROTECTION_FAULT_STATUS,
1298 info->mc_id = REG_GET_FIELD(status,
1299 VM_CONTEXT1_PROTECTION_FAULT_STATUS,
1301 info->status = status;
1302 info->page_addr = addr;
1303 info->prot_valid = protections & 0x7 ? true : false;
1304 info->prot_read = protections & 0x8 ? true : false;
1305 info->prot_write = protections & 0x10 ? true : false;
1306 info->prot_exec = protections & 0x20 ? true : false;
1308 atomic_set(&adev->gmc.vm_fault_info_updated, 1);
1314 static int gmc_v7_0_set_clockgating_state(void *handle,
1315 enum amd_clockgating_state state)
1318 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1320 if (state == AMD_CG_STATE_GATE)
1323 if (!(adev->flags & AMD_IS_APU)) {
1324 gmc_v7_0_enable_mc_mgcg(adev, gate);
1325 gmc_v7_0_enable_mc_ls(adev, gate);
1327 gmc_v7_0_enable_bif_mgls(adev, gate);
1328 gmc_v7_0_enable_hdp_mgcg(adev, gate);
1329 gmc_v7_0_enable_hdp_ls(adev, gate);
1334 static int gmc_v7_0_set_powergating_state(void *handle,
1335 enum amd_powergating_state state)
1340 static const struct amd_ip_funcs gmc_v7_0_ip_funcs = {
1342 .early_init = gmc_v7_0_early_init,
1343 .late_init = gmc_v7_0_late_init,
1344 .sw_init = gmc_v7_0_sw_init,
1345 .sw_fini = gmc_v7_0_sw_fini,
1346 .hw_init = gmc_v7_0_hw_init,
1347 .hw_fini = gmc_v7_0_hw_fini,
1348 .suspend = gmc_v7_0_suspend,
1349 .resume = gmc_v7_0_resume,
1350 .is_idle = gmc_v7_0_is_idle,
1351 .wait_for_idle = gmc_v7_0_wait_for_idle,
1352 .soft_reset = gmc_v7_0_soft_reset,
1353 .set_clockgating_state = gmc_v7_0_set_clockgating_state,
1354 .set_powergating_state = gmc_v7_0_set_powergating_state,
1357 static const struct amdgpu_gmc_funcs gmc_v7_0_gmc_funcs = {
1358 .flush_gpu_tlb = gmc_v7_0_flush_gpu_tlb,
1359 .flush_gpu_tlb_pasid = gmc_v7_0_flush_gpu_tlb_pasid,
1360 .emit_flush_gpu_tlb = gmc_v7_0_emit_flush_gpu_tlb,
1361 .emit_pasid_mapping = gmc_v7_0_emit_pasid_mapping,
1362 .set_prt = gmc_v7_0_set_prt,
1363 .get_vm_pde = gmc_v7_0_get_vm_pde,
1364 .get_vm_pte = gmc_v7_0_get_vm_pte,
1365 .get_vbios_fb_size = gmc_v7_0_get_vbios_fb_size,
1368 static const struct amdgpu_irq_src_funcs gmc_v7_0_irq_funcs = {
1369 .set = gmc_v7_0_vm_fault_interrupt_state,
1370 .process = gmc_v7_0_process_interrupt,
1373 static void gmc_v7_0_set_gmc_funcs(struct amdgpu_device *adev)
1375 adev->gmc.gmc_funcs = &gmc_v7_0_gmc_funcs;
1378 static void gmc_v7_0_set_irq_funcs(struct amdgpu_device *adev)
1380 adev->gmc.vm_fault.num_types = 1;
1381 adev->gmc.vm_fault.funcs = &gmc_v7_0_irq_funcs;
1384 const struct amdgpu_ip_block_version gmc_v7_0_ip_block = {
1385 .type = AMD_IP_BLOCK_TYPE_GMC,
1389 .funcs = &gmc_v7_0_ip_funcs,
1392 const struct amdgpu_ip_block_version gmc_v7_4_ip_block = {
1393 .type = AMD_IP_BLOCK_TYPE_GMC,
1397 .funcs = &gmc_v7_0_ip_funcs,