drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c

   1 /*
   2  * Copyright 2014 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23 #include <linux/firmware.h>
  24 #include <drm/drmP.h>
  25 #include <drm/drm_cache.h>
  26 #include "amdgpu.h"
  27 #include "gmc_v6_0.h"
  28 #include "amdgpu_ucode.h"
  29 #include "amdgpu_gem.h"
  30
  31 #include "bif/bif_3_0_d.h"
  32 #include "bif/bif_3_0_sh_mask.h"
  33 #include "oss/oss_1_0_d.h"
  34 #include "oss/oss_1_0_sh_mask.h"
  35 #include "gmc/gmc_6_0_d.h"
  36 #include "gmc/gmc_6_0_sh_mask.h"
  37 #include "dce/dce_6_0_d.h"
  38 #include "dce/dce_6_0_sh_mask.h"
  39 #include "si_enums.h"
  40
  41 static void gmc_v6_0_set_gmc_funcs(struct amdgpu_device *adev);
  42 static void gmc_v6_0_set_irq_funcs(struct amdgpu_device *adev);
  43 static int gmc_v6_0_wait_for_idle(void *handle);
  44
  45 MODULE_FIRMWARE("amdgpu/tahiti_mc.bin");
  46 MODULE_FIRMWARE("amdgpu/pitcairn_mc.bin");
  47 MODULE_FIRMWARE("amdgpu/verde_mc.bin");
  48 MODULE_FIRMWARE("amdgpu/oland_mc.bin");
  49 MODULE_FIRMWARE("amdgpu/hainan_mc.bin");
  50 MODULE_FIRMWARE("amdgpu/si58_mc.bin");
  51
  52 #define MC_SEQ_MISC0__MT__MASK   0xf0000000
  53 #define MC_SEQ_MISC0__MT__GDDR1  0x10000000
  54 #define MC_SEQ_MISC0__MT__DDR2   0x20000000
  55 #define MC_SEQ_MISC0__MT__GDDR3  0x30000000
  56 #define MC_SEQ_MISC0__MT__GDDR4  0x40000000
  57 #define MC_SEQ_MISC0__MT__GDDR5  0x50000000
  58 #define MC_SEQ_MISC0__MT__HBM    0x60000000
  59 #define MC_SEQ_MISC0__MT__DDR3   0xB0000000
  60
  61
  62 static const u32 crtc_offsets[6] =
  63 {
  64         SI_CRTC0_REGISTER_OFFSET,
  65         SI_CRTC1_REGISTER_OFFSET,
  66         SI_CRTC2_REGISTER_OFFSET,
  67         SI_CRTC3_REGISTER_OFFSET,
  68         SI_CRTC4_REGISTER_OFFSET,
  69         SI_CRTC5_REGISTER_OFFSET
  70 };
  71
  72 static void gmc_v6_0_mc_stop(struct amdgpu_device *adev)
  73 {
  74         u32 blackout;
  75
  76         gmc_v6_0_wait_for_idle((void *)adev);
  77
  78         blackout = RREG32(mmMC_SHARED_BLACKOUT_CNTL);
  79         if (REG_GET_FIELD(blackout, MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE) != 1) {
  80                 /* Block CPU access */
  81                 WREG32(mmBIF_FB_EN, 0);
  82                 /* blackout the MC */
  83                 blackout = REG_SET_FIELD(blackout,
  84                                          MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE, 0);
  85                 WREG32(mmMC_SHARED_BLACKOUT_CNTL, blackout | 1);
  86         }
  87         /* wait for the MC to settle */
  88         udelay(100);
  89
  90 }
  91
  92 static void gmc_v6_0_mc_resume(struct amdgpu_device *adev)
  93 {
  94         u32 tmp;
  95
  96         /* unblackout the MC */
  97         tmp = RREG32(mmMC_SHARED_BLACKOUT_CNTL);
  98         tmp = REG_SET_FIELD(tmp, MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE, 0);
  99         WREG32(mmMC_SHARED_BLACKOUT_CNTL, tmp);
 100         /* allow CPU access */
 101         tmp = REG_SET_FIELD(0, BIF_FB_EN, FB_READ_EN, 1);
 102         tmp = REG_SET_FIELD(tmp, BIF_FB_EN, FB_WRITE_EN, 1);
 103         WREG32(mmBIF_FB_EN, tmp);
 104 }
 105
 106 static int gmc_v6_0_init_microcode(struct amdgpu_device *adev)
 107 {
 108         const char *chip_name;
 109         char fw_name[30];
 110         int err;
 111         bool is_58_fw = false;
 112
 113         DRM_DEBUG("\n");
 114
 115         switch (adev->asic_type) {
 116         case CHIP_TAHITI:
 117                 chip_name = "tahiti";
 118                 break;
 119         case CHIP_PITCAIRN:
 120                 chip_name = "pitcairn";
 121                 break;
 122         case CHIP_VERDE:
 123                 chip_name = "verde";
 124                 break;
 125         case CHIP_OLAND:
 126                 chip_name = "oland";
 127                 break;
 128         case CHIP_HAINAN:
 129                 chip_name = "hainan";
 130                 break;
 131         default: BUG();
 132         }
 133
 134         /* this memory configuration requires special firmware */
 135         if (((RREG32(mmMC_SEQ_MISC0) & 0xff000000) >> 24) == 0x58)
 136                 is_58_fw = true;
 137
 138         if (is_58_fw)
 139                 snprintf(fw_name, sizeof(fw_name), "amdgpu/si58_mc.bin");
 140         else
 141                 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mc.bin", chip_name);
 142         err = request_firmware(&adev->gmc.fw, fw_name, adev->dev);
 143         if (err)
 144                 goto out;
 145
 146         err = amdgpu_ucode_validate(adev->gmc.fw);
 147
 148 out:
 149         if (err) {
 150                 dev_err(adev->dev,
 151                        "si_mc: Failed to load firmware \"%s\"\n",
 152                        fw_name);
 153                 release_firmware(adev->gmc.fw);
 154                 adev->gmc.fw = NULL;
 155         }
 156         return err;
 157 }
 158
 159 static int gmc_v6_0_mc_load_microcode(struct amdgpu_device *adev)
 160 {
 161         const __le32 *new_fw_data = NULL;
 162         u32 running;
 163         const __le32 *new_io_mc_regs = NULL;
 164         int i, regs_size, ucode_size;
 165         const struct mc_firmware_header_v1_0 *hdr;
 166
 167         if (!adev->gmc.fw)
 168                 return -EINVAL;
 169
 170         hdr = (const struct mc_firmware_header_v1_0 *)adev->gmc.fw->data;
 171
 172         amdgpu_ucode_print_mc_hdr(&hdr->header);
 173
 174         adev->gmc.fw_version = le32_to_cpu(hdr->header.ucode_version);
 175         regs_size = le32_to_cpu(hdr->io_debug_size_bytes) / (4 * 2);
 176         new_io_mc_regs = (const __le32 *)
 177                 (adev->gmc.fw->data + le32_to_cpu(hdr->io_debug_array_offset_bytes));
 178         ucode_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
 179         new_fw_data = (const __le32 *)
 180                 (adev->gmc.fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes));
 181
 182         running = RREG32(mmMC_SEQ_SUP_CNTL) & MC_SEQ_SUP_CNTL__RUN_MASK;
 183
 184         if (running == 0) {
 185
 186                 /* reset the engine and set to writable */
 187                 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008);
 188                 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000010);
 189
 190                 /* load mc io regs */
 191                 for (i = 0; i < regs_size; i++) {
 192                         WREG32(mmMC_SEQ_IO_DEBUG_INDEX, le32_to_cpup(new_io_mc_regs++));
 193                         WREG32(mmMC_SEQ_IO_DEBUG_DATA, le32_to_cpup(new_io_mc_regs++));
 194                 }
 195                 /* load the MC ucode */
 196                 for (i = 0; i < ucode_size; i++) {
 197                         WREG32(mmMC_SEQ_SUP_PGM, le32_to_cpup(new_fw_data++));
 198                 }
 199
 200                 /* put the engine back into the active state */
 201                 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008);
 202                 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000004);
 203                 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000001);
 204
 205                 /* wait for training to complete */
 206                 for (i = 0; i < adev->usec_timeout; i++) {
 207                         if (RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL) & MC_SEQ_TRAIN_WAKEUP_CNTL__TRAIN_DONE_D0_MASK)
 208                                 break;
 209                         udelay(1);
 210                 }
 211                 for (i = 0; i < adev->usec_timeout; i++) {
 212                         if (RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL) & MC_SEQ_TRAIN_WAKEUP_CNTL__TRAIN_DONE_D1_MASK)
 213                                 break;
 214                         udelay(1);
 215                 }
 216
 217         }
 218
 219         return 0;
 220 }
 221
 222 static void gmc_v6_0_vram_gtt_location(struct amdgpu_device *adev,
 223                                        struct amdgpu_gmc *mc)
 224 {
 225         u64 base = RREG32(mmMC_VM_FB_LOCATION) & 0xFFFF;
 226         base <<= 24;
 227
 228         amdgpu_gmc_vram_location(adev, &adev->gmc, base);
 229         amdgpu_gmc_gart_location(adev, mc);
 230 }
 231
 232 static void gmc_v6_0_mc_program(struct amdgpu_device *adev)
 233 {
 234         int i, j;
 235
 236         /* Initialize HDP */
 237         for (i = 0, j = 0; i < 32; i++, j += 0x6) {
 238                 WREG32((0xb05 + j), 0x00000000);
 239                 WREG32((0xb06 + j), 0x00000000);
 240                 WREG32((0xb07 + j), 0x00000000);
 241                 WREG32((0xb08 + j), 0x00000000);
 242                 WREG32((0xb09 + j), 0x00000000);
 243         }
 244         WREG32(mmHDP_REG_COHERENCY_FLUSH_CNTL, 0);
 245
 246         if (gmc_v6_0_wait_for_idle((void *)adev)) {
 247                 dev_warn(adev->dev, "Wait for MC idle timedout !\n");
 248         }
 249
 250         if (adev->mode_info.num_crtc) {
 251                 u32 tmp;
 252
 253                 /* Lockout access through VGA aperture*/
 254                 tmp = RREG32(mmVGA_HDP_CONTROL);
 255                 tmp |= VGA_HDP_CONTROL__VGA_MEMORY_DISABLE_MASK;
 256                 WREG32(mmVGA_HDP_CONTROL, tmp);
 257
 258                 /* disable VGA render */
 259                 tmp = RREG32(mmVGA_RENDER_CONTROL);
 260                 tmp &= ~VGA_VSTATUS_CNTL;
 261                 WREG32(mmVGA_RENDER_CONTROL, tmp);
 262         }
 263         /* Update configuration */
 264         WREG32(mmMC_VM_SYSTEM_APERTURE_LOW_ADDR,
 265                adev->gmc.vram_start >> 12);
 266         WREG32(mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR,
 267                adev->gmc.vram_end >> 12);
 268         WREG32(mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR,
 269                adev->vram_scratch.gpu_addr >> 12);
 270         WREG32(mmMC_VM_AGP_BASE, 0);
 271         WREG32(mmMC_VM_AGP_TOP, 0x0FFFFFFF);
 272         WREG32(mmMC_VM_AGP_BOT, 0x0FFFFFFF);
 273
 274         if (gmc_v6_0_wait_for_idle((void *)adev)) {
 275                 dev_warn(adev->dev, "Wait for MC idle timedout !\n");
 276         }
 277 }
 278
 279 static int gmc_v6_0_mc_init(struct amdgpu_device *adev)
 280 {
 281
 282         u32 tmp;
 283         int chansize, numchan;
 284         int r;
 285
 286         tmp = RREG32(mmMC_ARB_RAMCFG);
 287         if (tmp & (1 << 11)) {
 288                 chansize = 16;
 289         } else if (tmp & MC_ARB_RAMCFG__CHANSIZE_MASK) {
 290                 chansize = 64;
 291         } else {
 292                 chansize = 32;
 293         }
 294         tmp = RREG32(mmMC_SHARED_CHMAP);
 295         switch ((tmp & MC_SHARED_CHMAP__NOOFCHAN_MASK) >> MC_SHARED_CHMAP__NOOFCHAN__SHIFT) {
 296         case 0:
 297         default:
 298                 numchan = 1;
 299                 break;
 300         case 1:
 301                 numchan = 2;
 302                 break;
 303         case 2:
 304                 numchan = 4;
 305                 break;
 306         case 3:
 307                 numchan = 8;
 308                 break;
 309         case 4:
 310                 numchan = 3;
 311                 break;
 312         case 5:
 313                 numchan = 6;
 314                 break;
 315         case 6:
 316                 numchan = 10;
 317                 break;
 318         case 7:
 319                 numchan = 12;
 320                 break;
 321         case 8:
 322                 numchan = 16;
 323                 break;
 324         }
 325         adev->gmc.vram_width = numchan * chansize;
 326         /* size in MB on si */
 327         adev->gmc.mc_vram_size = RREG32(mmCONFIG_MEMSIZE) * 1024ULL * 1024ULL;
 328         adev->gmc.real_vram_size = RREG32(mmCONFIG_MEMSIZE) * 1024ULL * 1024ULL;
 329
 330         if (!(adev->flags & AMD_IS_APU)) {
 331                 r = amdgpu_device_resize_fb_bar(adev);
 332                 if (r)
 333                         return r;
 334         }
 335         adev->gmc.aper_base = pci_resource_start(adev->pdev, 0);
 336         adev->gmc.aper_size = pci_resource_len(adev->pdev, 0);
 337         adev->gmc.visible_vram_size = adev->gmc.aper_size;
 338
 339         /* set the gart size */
 340         if (amdgpu_gart_size == -1) {
 341                 switch (adev->asic_type) {
 342                 case CHIP_HAINAN:    /* no MM engines */
 343                 default:
 344                         adev->gmc.gart_size = 256ULL << 20;
 345                         break;
 346                 case CHIP_VERDE:    /* UVD, VCE do not support GPUVM */
 347                 case CHIP_TAHITI:   /* UVD, VCE do not support GPUVM */
 348                 case CHIP_PITCAIRN: /* UVD, VCE do not support GPUVM */
 349                 case CHIP_OLAND:    /* UVD, VCE do not support GPUVM */
 350                         adev->gmc.gart_size = 1024ULL << 20;
 351                         break;
 352                 }
 353         } else {
 354                 adev->gmc.gart_size = (u64)amdgpu_gart_size << 20;
 355         }
 356
 357         gmc_v6_0_vram_gtt_location(adev, &adev->gmc);
 358
 359         return 0;
 360 }
 361
 362 static void gmc_v6_0_flush_gpu_tlb(struct amdgpu_device *adev,
 363                                 uint32_t vmid, uint32_t flush_type)
 364 {
 365         WREG32(mmVM_INVALIDATE_REQUEST, 1 << vmid);
 366 }
 367
 368 static uint64_t gmc_v6_0_emit_flush_gpu_tlb(struct amdgpu_ring *ring,
 369                                             unsigned vmid, uint64_t pd_addr)
 370 {
 371         uint32_t reg;
 372
 373         /* write new base address */
 374         if (vmid < 8)
 375                 reg = mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + vmid;
 376         else
 377                 reg = mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + (vmid - 8);
 378         amdgpu_ring_emit_wreg(ring, reg, pd_addr >> 12);
 379
 380         /* bits 0-15 are the VM contexts0-15 */
 381         amdgpu_ring_emit_wreg(ring, mmVM_INVALIDATE_REQUEST, 1 << vmid);
 382
 383         return pd_addr;
 384 }
 385
 386 static int gmc_v6_0_set_pte_pde(struct amdgpu_device *adev, void *cpu_pt_addr,
 387                                 uint32_t gpu_page_idx, uint64_t addr,
 388                                 uint64_t flags)
 389 {
 390         void __iomem *ptr = (void *)cpu_pt_addr;
 391         uint64_t value;
 392
 393         value = addr & 0xFFFFFFFFFFFFF000ULL;
 394         value |= flags;
 395         writeq(value, ptr + (gpu_page_idx * 8));
 396
 397         return 0;
 398 }
 399
 400 static uint64_t gmc_v6_0_get_vm_pte_flags(struct amdgpu_device *adev,
 401                                           uint32_t flags)
 402 {
 403         uint64_t pte_flag = 0;
 404
 405         if (flags & AMDGPU_VM_PAGE_READABLE)
 406                 pte_flag |= AMDGPU_PTE_READABLE;
 407         if (flags & AMDGPU_VM_PAGE_WRITEABLE)
 408                 pte_flag |= AMDGPU_PTE_WRITEABLE;
 409         if (flags & AMDGPU_VM_PAGE_PRT)
 410                 pte_flag |= AMDGPU_PTE_PRT;
 411
 412         return pte_flag;
 413 }
 414
 415 static void gmc_v6_0_get_vm_pde(struct amdgpu_device *adev, int level,
 416                                 uint64_t *addr, uint64_t *flags)
 417 {
 418         BUG_ON(*addr & 0xFFFFFF0000000FFFULL);
 419 }
 420
 421 static void gmc_v6_0_set_fault_enable_default(struct amdgpu_device *adev,
 422                                               bool value)
 423 {
 424         u32 tmp;
 425
 426         tmp = RREG32(mmVM_CONTEXT1_CNTL);
 427         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 428                             RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 429         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 430                             DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 431         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 432                             PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 433         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 434                             VALID_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 435         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 436                             READ_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 437         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 438                             WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 439         WREG32(mmVM_CONTEXT1_CNTL, tmp);
 440 }
 441
 442  /**
 443    + * gmc_v8_0_set_prt - set PRT VM fault
 444    + *
 445    + * @adev: amdgpu_device pointer
 446    + * @enable: enable/disable VM fault handling for PRT
 447    +*/
 448 static void gmc_v6_0_set_prt(struct amdgpu_device *adev, bool enable)
 449 {
 450         u32 tmp;
 451
 452         if (enable && !adev->gmc.prt_warning) {
 453                 dev_warn(adev->dev, "Disabling VM faults because of PRT request!\n");
 454                 adev->gmc.prt_warning = true;
 455         }
 456
 457         tmp = RREG32(mmVM_PRT_CNTL);
 458         tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
 459                             CB_DISABLE_FAULT_ON_UNMAPPED_ACCESS,
 460                             enable);
 461         tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
 462                             TC_DISABLE_FAULT_ON_UNMAPPED_ACCESS,
 463                             enable);
 464         tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
 465                             L2_CACHE_STORE_INVALID_ENTRIES,
 466                             enable);
 467         tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
 468                             L1_TLB_STORE_INVALID_ENTRIES,
 469                             enable);
 470         WREG32(mmVM_PRT_CNTL, tmp);
 471
 472         if (enable) {
 473                 uint32_t low = AMDGPU_VA_RESERVED_SIZE >> AMDGPU_GPU_PAGE_SHIFT;
 474                 uint32_t high = adev->vm_manager.max_pfn -
 475                         (AMDGPU_VA_RESERVED_SIZE >> AMDGPU_GPU_PAGE_SHIFT);
 476
 477                 WREG32(mmVM_PRT_APERTURE0_LOW_ADDR, low);
 478                 WREG32(mmVM_PRT_APERTURE1_LOW_ADDR, low);
 479                 WREG32(mmVM_PRT_APERTURE2_LOW_ADDR, low);
 480                 WREG32(mmVM_PRT_APERTURE3_LOW_ADDR, low);
 481                 WREG32(mmVM_PRT_APERTURE0_HIGH_ADDR, high);
 482                 WREG32(mmVM_PRT_APERTURE1_HIGH_ADDR, high);
 483                 WREG32(mmVM_PRT_APERTURE2_HIGH_ADDR, high);
 484                 WREG32(mmVM_PRT_APERTURE3_HIGH_ADDR, high);
 485         } else {
 486                 WREG32(mmVM_PRT_APERTURE0_LOW_ADDR, 0xfffffff);
 487                 WREG32(mmVM_PRT_APERTURE1_LOW_ADDR, 0xfffffff);
 488                 WREG32(mmVM_PRT_APERTURE2_LOW_ADDR, 0xfffffff);
 489                 WREG32(mmVM_PRT_APERTURE3_LOW_ADDR, 0xfffffff);
 490                 WREG32(mmVM_PRT_APERTURE0_HIGH_ADDR, 0x0);
 491                 WREG32(mmVM_PRT_APERTURE1_HIGH_ADDR, 0x0);
 492                 WREG32(mmVM_PRT_APERTURE2_HIGH_ADDR, 0x0);
 493                 WREG32(mmVM_PRT_APERTURE3_HIGH_ADDR, 0x0);
 494         }
 495 }
 496
 497 static int gmc_v6_0_gart_enable(struct amdgpu_device *adev)
 498 {
 499         uint64_t table_addr;
 500         int r, i;
 501         u32 field;
 502
 503         if (adev->gart.bo == NULL) {
 504                 dev_err(adev->dev, "No VRAM object for PCIE GART.\n");
 505                 return -EINVAL;
 506         }
 507         r = amdgpu_gart_table_vram_pin(adev);
 508         if (r)
 509                 return r;
 510
 511         table_addr = amdgpu_bo_gpu_offset(adev->gart.bo);
 512
 513         /* Setup TLB control */
 514         WREG32(mmMC_VM_MX_L1_TLB_CNTL,
 515                (0xA << 7) |
 516                MC_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB_MASK |
 517                MC_VM_MX_L1_TLB_CNTL__ENABLE_L1_FRAGMENT_PROCESSING_MASK |
 518                MC_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE_MASK |
 519                MC_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL_MASK |
 520                (0UL << MC_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS__SHIFT));
 521         /* Setup L2 cache */
 522         WREG32(mmVM_L2_CNTL,
 523                VM_L2_CNTL__ENABLE_L2_CACHE_MASK |
 524                VM_L2_CNTL__ENABLE_L2_FRAGMENT_PROCESSING_MASK |
 525                VM_L2_CNTL__ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE_MASK |
 526                VM_L2_CNTL__ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE_MASK |
 527                (7UL << VM_L2_CNTL__EFFECTIVE_L2_QUEUE_SIZE__SHIFT) |
 528                (1UL << VM_L2_CNTL__CONTEXT1_IDENTITY_ACCESS_MODE__SHIFT));
 529         WREG32(mmVM_L2_CNTL2,
 530                VM_L2_CNTL2__INVALIDATE_ALL_L1_TLBS_MASK |
 531                VM_L2_CNTL2__INVALIDATE_L2_CACHE_MASK);
 532
 533         field = adev->vm_manager.fragment_size;
 534         WREG32(mmVM_L2_CNTL3,
 535                VM_L2_CNTL3__L2_CACHE_BIGK_ASSOCIATIVITY_MASK |
 536                (field << VM_L2_CNTL3__BANK_SELECT__SHIFT) |
 537                (field << VM_L2_CNTL3__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT));
 538         /* setup context0 */
 539         WREG32(mmVM_CONTEXT0_PAGE_TABLE_START_ADDR, adev->gmc.gart_start >> 12);
 540         WREG32(mmVM_CONTEXT0_PAGE_TABLE_END_ADDR, adev->gmc.gart_end >> 12);
 541         WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR, table_addr >> 12);
 542         WREG32(mmVM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
 543                         (u32)(adev->dummy_page_addr >> 12));
 544         WREG32(mmVM_CONTEXT0_CNTL2, 0);
 545         WREG32(mmVM_CONTEXT0_CNTL,
 546                VM_CONTEXT0_CNTL__ENABLE_CONTEXT_MASK |
 547                (0UL << VM_CONTEXT0_CNTL__PAGE_TABLE_DEPTH__SHIFT) |
 548                VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK);
 549
 550         WREG32(0x575, 0);
 551         WREG32(0x576, 0);
 552         WREG32(0x577, 0);
 553
 554         /* empty context1-15 */
 555         /* set vm size, must be a multiple of 4 */
 556         WREG32(mmVM_CONTEXT1_PAGE_TABLE_START_ADDR, 0);
 557         WREG32(mmVM_CONTEXT1_PAGE_TABLE_END_ADDR, adev->vm_manager.max_pfn - 1);
 558         /* Assign the pt base to something valid for now; the pts used for
 559          * the VMs are determined by the application and setup and assigned
 560          * on the fly in the vm part of radeon_gart.c
 561          */
 562         for (i = 1; i < 16; i++) {
 563                 if (i < 8)
 564                         WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + i,
 565                                table_addr >> 12);
 566                 else
 567                         WREG32(mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + i - 8,
 568                                table_addr >> 12);
 569         }
 570
 571         /* enable context1-15 */
 572         WREG32(mmVM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR,
 573                (u32)(adev->dummy_page_addr >> 12));
 574         WREG32(mmVM_CONTEXT1_CNTL2, 4);
 575         WREG32(mmVM_CONTEXT1_CNTL,
 576                VM_CONTEXT1_CNTL__ENABLE_CONTEXT_MASK |
 577                (1UL << VM_CONTEXT1_CNTL__PAGE_TABLE_DEPTH__SHIFT) |
 578                ((adev->vm_manager.block_size - 9)
 579                << VM_CONTEXT1_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT));
 580         if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS)
 581                 gmc_v6_0_set_fault_enable_default(adev, false);
 582         else
 583                 gmc_v6_0_set_fault_enable_default(adev, true);
 584
 585         gmc_v6_0_flush_gpu_tlb(adev, 0, 0);
 586         dev_info(adev->dev, "PCIE GART of %uM enabled (table at 0x%016llX).\n",
 587                  (unsigned)(adev->gmc.gart_size >> 20),
 588                  (unsigned long long)table_addr);
 589         adev->gart.ready = true;
 590         return 0;
 591 }
 592
 593 static int gmc_v6_0_gart_init(struct amdgpu_device *adev)
 594 {
 595         int r;
 596
 597         if (adev->gart.bo) {
 598                 dev_warn(adev->dev, "gmc_v6_0 PCIE GART already initialized\n");
 599                 return 0;
 600         }
 601         r = amdgpu_gart_init(adev);
 602         if (r)
 603                 return r;
 604         adev->gart.table_size = adev->gart.num_gpu_pages * 8;
 605         adev->gart.gart_pte_flags = 0;
 606         return amdgpu_gart_table_vram_alloc(adev);
 607 }
 608
 609 static void gmc_v6_0_gart_disable(struct amdgpu_device *adev)
 610 {
 611         /*unsigned i;
 612
 613         for (i = 1; i < 16; ++i) {
 614                 uint32_t reg;
 615                 if (i < 8)
 616                         reg = VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + i ;
 617                 else
 618                         reg = VM_CONTEXT8_PAGE_TABLE_BASE_ADDR + (i - 8);
 619                 adev->vm_manager.saved_table_addr[i] = RREG32(reg);
 620         }*/
 621
 622         /* Disable all tables */
 623         WREG32(mmVM_CONTEXT0_CNTL, 0);
 624         WREG32(mmVM_CONTEXT1_CNTL, 0);
 625         /* Setup TLB control */
 626         WREG32(mmMC_VM_MX_L1_TLB_CNTL,
 627                MC_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE_MASK |
 628                (0UL << MC_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS__SHIFT));
 629         /* Setup L2 cache */
 630         WREG32(mmVM_L2_CNTL,
 631                VM_L2_CNTL__ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE_MASK |
 632                VM_L2_CNTL__ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE_MASK |
 633                (7UL << VM_L2_CNTL__EFFECTIVE_L2_QUEUE_SIZE__SHIFT) |
 634                (1UL << VM_L2_CNTL__CONTEXT1_IDENTITY_ACCESS_MODE__SHIFT));
 635         WREG32(mmVM_L2_CNTL2, 0);
 636         WREG32(mmVM_L2_CNTL3,
 637                VM_L2_CNTL3__L2_CACHE_BIGK_ASSOCIATIVITY_MASK |
 638                (0UL << VM_L2_CNTL3__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT));
 639         amdgpu_gart_table_vram_unpin(adev);
 640 }
 641
 642 static void gmc_v6_0_vm_decode_fault(struct amdgpu_device *adev,
 643                                      u32 status, u32 addr, u32 mc_client)
 644 {
 645         u32 mc_id;
 646         u32 vmid = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, VMID);
 647         u32 protections = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS,
 648                                         PROTECTIONS);
 649         char block[5] = { mc_client >> 24, (mc_client >> 16) & 0xff,
 650                 (mc_client >> 8) & 0xff, mc_client & 0xff, 0 };
 651
 652         mc_id = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS,
 653                               MEMORY_CLIENT_ID);
 654
 655         dev_err(adev->dev, "VM fault (0x%02x, vmid %d) at page %u, %s from '%s' (0x%08x) (%d)\n",
 656                protections, vmid, addr,
 657                REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS,
 658                              MEMORY_CLIENT_RW) ?
 659                "write" : "read", block, mc_client, mc_id);
 660 }
 661
 662 /*
 663 static const u32 mc_cg_registers[] = {
 664         MC_HUB_MISC_HUB_CG,
 665         MC_HUB_MISC_SIP_CG,
 666         MC_HUB_MISC_VM_CG,
 667         MC_XPB_CLK_GAT,
 668         ATC_MISC_CG,
 669         MC_CITF_MISC_WR_CG,
 670         MC_CITF_MISC_RD_CG,
 671         MC_CITF_MISC_VM_CG,
 672         VM_L2_CG,
 673 };
 674
 675 static const u32 mc_cg_ls_en[] = {
 676         MC_HUB_MISC_HUB_CG__MEM_LS_ENABLE_MASK,
 677         MC_HUB_MISC_SIP_CG__MEM_LS_ENABLE_MASK,
 678         MC_HUB_MISC_VM_CG__MEM_LS_ENABLE_MASK,
 679         MC_XPB_CLK_GAT__MEM_LS_ENABLE_MASK,
 680         ATC_MISC_CG__MEM_LS_ENABLE_MASK,
 681         MC_CITF_MISC_WR_CG__MEM_LS_ENABLE_MASK,
 682         MC_CITF_MISC_RD_CG__MEM_LS_ENABLE_MASK,
 683         MC_CITF_MISC_VM_CG__MEM_LS_ENABLE_MASK,
 684         VM_L2_CG__MEM_LS_ENABLE_MASK,
 685 };
 686
 687 static const u32 mc_cg_en[] = {
 688         MC_HUB_MISC_HUB_CG__ENABLE_MASK,
 689         MC_HUB_MISC_SIP_CG__ENABLE_MASK,
 690         MC_HUB_MISC_VM_CG__ENABLE_MASK,
 691         MC_XPB_CLK_GAT__ENABLE_MASK,
 692         ATC_MISC_CG__ENABLE_MASK,
 693         MC_CITF_MISC_WR_CG__ENABLE_MASK,
 694         MC_CITF_MISC_RD_CG__ENABLE_MASK,
 695         MC_CITF_MISC_VM_CG__ENABLE_MASK,
 696         VM_L2_CG__ENABLE_MASK,
 697 };
 698
 699 static void gmc_v6_0_enable_mc_ls(struct amdgpu_device *adev,
 700                                   bool enable)
 701 {
 702         int i;
 703         u32 orig, data;
 704
 705         for (i = 0; i < ARRAY_SIZE(mc_cg_registers); i++) {
 706                 orig = data = RREG32(mc_cg_registers[i]);
 707                 if (enable && (adev->cg_flags & AMDGPU_CG_SUPPORT_MC_LS))
 708                         data |= mc_cg_ls_en[i];
 709                 else
 710                         data &= ~mc_cg_ls_en[i];
 711                 if (data != orig)
 712                         WREG32(mc_cg_registers[i], data);
 713         }
 714 }
 715
 716 static void gmc_v6_0_enable_mc_mgcg(struct amdgpu_device *adev,
 717                                     bool enable)
 718 {
 719         int i;
 720         u32 orig, data;
 721
 722         for (i = 0; i < ARRAY_SIZE(mc_cg_registers); i++) {
 723                 orig = data = RREG32(mc_cg_registers[i]);
 724                 if (enable && (adev->cg_flags & AMDGPU_CG_SUPPORT_MC_MGCG))
 725                         data |= mc_cg_en[i];
 726                 else
 727                         data &= ~mc_cg_en[i];
 728                 if (data != orig)
 729                         WREG32(mc_cg_registers[i], data);
 730         }
 731 }
 732
 733 static void gmc_v6_0_enable_bif_mgls(struct amdgpu_device *adev,
 734                                      bool enable)
 735 {
 736         u32 orig, data;
 737
 738         orig = data = RREG32_PCIE(ixPCIE_CNTL2);
 739
 740         if (enable && (adev->cg_flags & AMDGPU_CG_SUPPORT_BIF_LS)) {
 741                 data = REG_SET_FIELD(data, PCIE_CNTL2, SLV_MEM_LS_EN, 1);
 742                 data = REG_SET_FIELD(data, PCIE_CNTL2, MST_MEM_LS_EN, 1);
 743                 data = REG_SET_FIELD(data, PCIE_CNTL2, REPLAY_MEM_LS_EN, 1);
 744                 data = REG_SET_FIELD(data, PCIE_CNTL2, SLV_MEM_AGGRESSIVE_LS_EN, 1);
 745         } else {
 746                 data = REG_SET_FIELD(data, PCIE_CNTL2, SLV_MEM_LS_EN, 0);
 747                 data = REG_SET_FIELD(data, PCIE_CNTL2, MST_MEM_LS_EN, 0);
 748                 data = REG_SET_FIELD(data, PCIE_CNTL2, REPLAY_MEM_LS_EN, 0);
 749                 data = REG_SET_FIELD(data, PCIE_CNTL2, SLV_MEM_AGGRESSIVE_LS_EN, 0);
 750         }
 751
 752         if (orig != data)
 753                 WREG32_PCIE(ixPCIE_CNTL2, data);
 754 }
 755
 756 static void gmc_v6_0_enable_hdp_mgcg(struct amdgpu_device *adev,
 757                                      bool enable)
 758 {
 759         u32 orig, data;
 760
 761         orig = data = RREG32(mmHDP_HOST_PATH_CNTL);
 762
 763         if (enable && (adev->cg_flags & AMDGPU_CG_SUPPORT_HDP_MGCG))
 764                 data = REG_SET_FIELD(data, HDP_HOST_PATH_CNTL, CLOCK_GATING_DIS, 0);
 765         else
 766                 data = REG_SET_FIELD(data, HDP_HOST_PATH_CNTL, CLOCK_GATING_DIS, 1);
 767
 768         if (orig != data)
 769                 WREG32(mmHDP_HOST_PATH_CNTL, data);
 770 }
 771
 772 static void gmc_v6_0_enable_hdp_ls(struct amdgpu_device *adev,
 773                                    bool enable)
 774 {
 775         u32 orig, data;
 776
 777         orig = data = RREG32(mmHDP_MEM_POWER_LS);
 778
 779         if (enable && (adev->cg_flags & AMDGPU_CG_SUPPORT_HDP_LS))
 780                 data = REG_SET_FIELD(data, HDP_MEM_POWER_LS, LS_ENABLE, 1);
 781         else
 782                 data = REG_SET_FIELD(data, HDP_MEM_POWER_LS, LS_ENABLE, 0);
 783
 784         if (orig != data)
 785                 WREG32(mmHDP_MEM_POWER_LS, data);
 786 }
 787 */
 788
 789 static int gmc_v6_0_convert_vram_type(int mc_seq_vram_type)
 790 {
 791         switch (mc_seq_vram_type) {
 792         case MC_SEQ_MISC0__MT__GDDR1:
 793                 return AMDGPU_VRAM_TYPE_GDDR1;
 794         case MC_SEQ_MISC0__MT__DDR2:
 795                 return AMDGPU_VRAM_TYPE_DDR2;
 796         case MC_SEQ_MISC0__MT__GDDR3:
 797                 return AMDGPU_VRAM_TYPE_GDDR3;
 798         case MC_SEQ_MISC0__MT__GDDR4:
 799                 return AMDGPU_VRAM_TYPE_GDDR4;
 800         case MC_SEQ_MISC0__MT__GDDR5:
 801                 return AMDGPU_VRAM_TYPE_GDDR5;
 802         case MC_SEQ_MISC0__MT__DDR3:
 803                 return AMDGPU_VRAM_TYPE_DDR3;
 804         default:
 805                 return AMDGPU_VRAM_TYPE_UNKNOWN;
 806         }
 807 }
 808
 809 static int gmc_v6_0_early_init(void *handle)
 810 {
 811         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 812
 813         gmc_v6_0_set_gmc_funcs(adev);
 814         gmc_v6_0_set_irq_funcs(adev);
 815
 816         return 0;
 817 }
 818
 819 static int gmc_v6_0_late_init(void *handle)
 820 {
 821         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 822
 823         amdgpu_bo_late_init(adev);
 824
 825         if (amdgpu_vm_fault_stop != AMDGPU_VM_FAULT_STOP_ALWAYS)
 826                 return amdgpu_irq_get(adev, &adev->gmc.vm_fault, 0);
 827         else
 828                 return 0;
 829 }
 830
 831 static unsigned gmc_v6_0_get_vbios_fb_size(struct amdgpu_device *adev)
 832 {
 833         u32 d1vga_control = RREG32(mmD1VGA_CONTROL);
 834         unsigned size;
 835
 836         if (REG_GET_FIELD(d1vga_control, D1VGA_CONTROL, D1VGA_MODE_ENABLE)) {
 837                 size = 9 * 1024 * 1024; /* reserve 8MB for vga emulator and 1 MB for FB */
 838         } else {
 839                 u32 viewport = RREG32(mmVIEWPORT_SIZE);
 840                 size = (REG_GET_FIELD(viewport, VIEWPORT_SIZE, VIEWPORT_HEIGHT) *
 841                         REG_GET_FIELD(viewport, VIEWPORT_SIZE, VIEWPORT_WIDTH) *
 842                         4);
 843         }
 844         /* return 0 if the pre-OS buffer uses up most of vram */
 845         if ((adev->gmc.real_vram_size - size) < (8 * 1024 * 1024))
 846                 return 0;
 847         return size;
 848 }
 849
 850 static int gmc_v6_0_sw_init(void *handle)
 851 {
 852         int r;
 853         int dma_bits;
 854         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 855
 856         if (adev->flags & AMD_IS_APU) {
 857                 adev->gmc.vram_type = AMDGPU_VRAM_TYPE_UNKNOWN;
 858         } else {
 859                 u32 tmp = RREG32(mmMC_SEQ_MISC0);
 860                 tmp &= MC_SEQ_MISC0__MT__MASK;
 861                 adev->gmc.vram_type = gmc_v6_0_convert_vram_type(tmp);
 862         }
 863
 864         r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, 146, &adev->gmc.vm_fault);
 865         if (r)
 866                 return r;
 867
 868         r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, 147, &adev->gmc.vm_fault);
 869         if (r)
 870                 return r;
 871
 872         amdgpu_vm_adjust_size(adev, 64, 9, 1, 40);
 873
 874         adev->gmc.mc_mask = 0xffffffffffULL;
 875
 876         adev->need_dma32 = false;
 877         dma_bits = adev->need_dma32 ? 32 : 40;
 878         r = pci_set_dma_mask(adev->pdev, DMA_BIT_MASK(dma_bits));
 879         if (r) {
 880                 adev->need_dma32 = true;
 881                 dma_bits = 32;
 882                 dev_warn(adev->dev, "amdgpu: No suitable DMA available.\n");
 883         }
 884         r = pci_set_consistent_dma_mask(adev->pdev, DMA_BIT_MASK(dma_bits));
 885         if (r) {
 886                 pci_set_consistent_dma_mask(adev->pdev, DMA_BIT_MASK(32));
 887                 dev_warn(adev->dev, "amdgpu: No coherent DMA available.\n");
 888         }
 889         adev->need_swiotlb = drm_get_max_iomem() > ((u64)1 << dma_bits);
 890
 891         r = gmc_v6_0_init_microcode(adev);
 892         if (r) {
 893                 dev_err(adev->dev, "Failed to load mc firmware!\n");
 894                 return r;
 895         }
 896
 897         r = gmc_v6_0_mc_init(adev);
 898         if (r)
 899                 return r;
 900
 901         adev->gmc.stolen_size = gmc_v6_0_get_vbios_fb_size(adev);
 902
 903         r = amdgpu_bo_init(adev);
 904         if (r)
 905                 return r;
 906
 907         r = gmc_v6_0_gart_init(adev);
 908         if (r)
 909                 return r;
 910
 911         /*
 912          * number of VMs
 913          * VMID 0 is reserved for System
 914          * amdgpu graphics/compute will use VMIDs 1-7
 915          * amdkfd will use VMIDs 8-15
 916          */
 917         adev->vm_manager.id_mgr[0].num_ids = AMDGPU_NUM_OF_VMIDS;
 918         amdgpu_vm_manager_init(adev);
 919
 920         /* base offset of vram pages */
 921         if (adev->flags & AMD_IS_APU) {
 922                 u64 tmp = RREG32(mmMC_VM_FB_OFFSET);
 923
 924                 tmp <<= 22;
 925                 adev->vm_manager.vram_base_offset = tmp;
 926         } else {
 927                 adev->vm_manager.vram_base_offset = 0;
 928         }
 929
 930         return 0;
 931 }
 932
 933 static int gmc_v6_0_sw_fini(void *handle)
 934 {
 935         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 936
 937         amdgpu_gem_force_release(adev);
 938         amdgpu_vm_manager_fini(adev);
 939         amdgpu_gart_table_vram_free(adev);
 940         amdgpu_bo_fini(adev);
 941         amdgpu_gart_fini(adev);
 942         release_firmware(adev->gmc.fw);
 943         adev->gmc.fw = NULL;
 944
 945         return 0;
 946 }
 947
 948 static int gmc_v6_0_hw_init(void *handle)
 949 {
 950         int r;
 951         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 952
 953         gmc_v6_0_mc_program(adev);
 954
 955         if (!(adev->flags & AMD_IS_APU)) {
 956                 r = gmc_v6_0_mc_load_microcode(adev);
 957                 if (r) {
 958                         dev_err(adev->dev, "Failed to load MC firmware!\n");
 959                         return r;
 960                 }
 961         }
 962
 963         r = gmc_v6_0_gart_enable(adev);
 964         if (r)
 965                 return r;
 966
 967         return r;
 968 }
 969
 970 static int gmc_v6_0_hw_fini(void *handle)
 971 {
 972         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 973
 974         amdgpu_irq_put(adev, &adev->gmc.vm_fault, 0);
 975         gmc_v6_0_gart_disable(adev);
 976
 977         return 0;
 978 }
 979
 980 static int gmc_v6_0_suspend(void *handle)
 981 {
 982         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 983
 984         gmc_v6_0_hw_fini(adev);
 985
 986         return 0;
 987 }
 988
 989 static int gmc_v6_0_resume(void *handle)
 990 {
 991         int r;
 992         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 993
 994         r = gmc_v6_0_hw_init(adev);
 995         if (r)
 996                 return r;
 997
 998         amdgpu_vmid_reset_all(adev);
 999
1000         return 0;
1001 }
1002
1003 static bool gmc_v6_0_is_idle(void *handle)
1004 {
1005         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1006         u32 tmp = RREG32(mmSRBM_STATUS);
1007
1008         if (tmp & (SRBM_STATUS__MCB_BUSY_MASK | SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK |
1009                    SRBM_STATUS__MCC_BUSY_MASK | SRBM_STATUS__MCD_BUSY_MASK | SRBM_STATUS__VMC_BUSY_MASK))
1010                 return false;
1011
1012         return true;
1013 }
1014
1015 static int gmc_v6_0_wait_for_idle(void *handle)
1016 {
1017         unsigned i;
1018         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1019
1020         for (i = 0; i < adev->usec_timeout; i++) {
1021                 if (gmc_v6_0_is_idle(handle))
1022                         return 0;
1023                 udelay(1);
1024         }
1025         return -ETIMEDOUT;
1026
1027 }
1028
1029 static int gmc_v6_0_soft_reset(void *handle)
1030 {
1031         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1032         u32 srbm_soft_reset = 0;
1033         u32 tmp = RREG32(mmSRBM_STATUS);
1034
1035         if (tmp & SRBM_STATUS__VMC_BUSY_MASK)
1036                 srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset,
1037                                                 SRBM_SOFT_RESET, SOFT_RESET_VMC, 1);
1038
1039         if (tmp & (SRBM_STATUS__MCB_BUSY_MASK | SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK |
1040                    SRBM_STATUS__MCC_BUSY_MASK | SRBM_STATUS__MCD_BUSY_MASK)) {
1041                 if (!(adev->flags & AMD_IS_APU))
1042                         srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset,
1043                                                         SRBM_SOFT_RESET, SOFT_RESET_MC, 1);
1044         }
1045
1046         if (srbm_soft_reset) {
1047                 gmc_v6_0_mc_stop(adev);
1048                 if (gmc_v6_0_wait_for_idle(adev)) {
1049                         dev_warn(adev->dev, "Wait for GMC idle timed out !\n");
1050                 }
1051
1052
1053                 tmp = RREG32(mmSRBM_SOFT_RESET);
1054                 tmp |= srbm_soft_reset;
1055                 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
1056                 WREG32(mmSRBM_SOFT_RESET, tmp);
1057                 tmp = RREG32(mmSRBM_SOFT_RESET);
1058
1059                 udelay(50);
1060
1061                 tmp &= ~srbm_soft_reset;
1062                 WREG32(mmSRBM_SOFT_RESET, tmp);
1063                 tmp = RREG32(mmSRBM_SOFT_RESET);
1064
1065                 udelay(50);
1066
1067                 gmc_v6_0_mc_resume(adev);
1068                 udelay(50);
1069         }
1070
1071         return 0;
1072 }
1073
1074 static int gmc_v6_0_vm_fault_interrupt_state(struct amdgpu_device *adev,
1075                                              struct amdgpu_irq_src *src,
1076                                              unsigned type,
1077                                              enum amdgpu_interrupt_state state)
1078 {
1079         u32 tmp;
1080         u32 bits = (VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1081                     VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1082                     VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1083                     VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1084                     VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1085                     VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK);
1086
1087         switch (state) {
1088         case AMDGPU_IRQ_STATE_DISABLE:
1089                 tmp = RREG32(mmVM_CONTEXT0_CNTL);
1090                 tmp &= ~bits;
1091                 WREG32(mmVM_CONTEXT0_CNTL, tmp);
1092                 tmp = RREG32(mmVM_CONTEXT1_CNTL);
1093                 tmp &= ~bits;
1094                 WREG32(mmVM_CONTEXT1_CNTL, tmp);
1095                 break;
1096         case AMDGPU_IRQ_STATE_ENABLE:
1097                 tmp = RREG32(mmVM_CONTEXT0_CNTL);
1098                 tmp |= bits;
1099                 WREG32(mmVM_CONTEXT0_CNTL, tmp);
1100                 tmp = RREG32(mmVM_CONTEXT1_CNTL);
1101                 tmp |= bits;
1102                 WREG32(mmVM_CONTEXT1_CNTL, tmp);
1103                 break;
1104         default:
1105                 break;
1106         }
1107
1108         return 0;
1109 }
1110
1111 static int gmc_v6_0_process_interrupt(struct amdgpu_device *adev,
1112                                       struct amdgpu_irq_src *source,
1113                                       struct amdgpu_iv_entry *entry)
1114 {
1115         u32 addr, status;
1116
1117         addr = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_ADDR);
1118         status = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_STATUS);
1119         WREG32_P(mmVM_CONTEXT1_CNTL2, 1, ~1);
1120
1121         if (!addr && !status)
1122                 return 0;
1123
1124         if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_FIRST)
1125                 gmc_v6_0_set_fault_enable_default(adev, false);
1126
1127         if (printk_ratelimit()) {
1128                 dev_err(adev->dev, "GPU fault detected: %d 0x%08x\n",
1129                         entry->src_id, entry->src_data[0]);
1130                 dev_err(adev->dev, "  VM_CONTEXT1_PROTECTION_FAULT_ADDR   0x%08X\n",
1131                         addr);
1132                 dev_err(adev->dev, "  VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n",
1133                         status);
1134                 gmc_v6_0_vm_decode_fault(adev, status, addr, 0);
1135         }
1136
1137         return 0;
1138 }
1139
1140 static int gmc_v6_0_set_clockgating_state(void *handle,
1141                                           enum amd_clockgating_state state)
1142 {
1143         return 0;
1144 }
1145
1146 static int gmc_v6_0_set_powergating_state(void *handle,
1147                                           enum amd_powergating_state state)
1148 {
1149         return 0;
1150 }
1151
1152 static const struct amd_ip_funcs gmc_v6_0_ip_funcs = {
1153         .name = "gmc_v6_0",
1154         .early_init = gmc_v6_0_early_init,
1155         .late_init = gmc_v6_0_late_init,
1156         .sw_init = gmc_v6_0_sw_init,
1157         .sw_fini = gmc_v6_0_sw_fini,
1158         .hw_init = gmc_v6_0_hw_init,
1159         .hw_fini = gmc_v6_0_hw_fini,
1160         .suspend = gmc_v6_0_suspend,
1161         .resume = gmc_v6_0_resume,
1162         .is_idle = gmc_v6_0_is_idle,
1163         .wait_for_idle = gmc_v6_0_wait_for_idle,
1164         .soft_reset = gmc_v6_0_soft_reset,
1165         .set_clockgating_state = gmc_v6_0_set_clockgating_state,
1166         .set_powergating_state = gmc_v6_0_set_powergating_state,
1167 };
1168
1169 static const struct amdgpu_gmc_funcs gmc_v6_0_gmc_funcs = {
1170         .flush_gpu_tlb = gmc_v6_0_flush_gpu_tlb,
1171         .emit_flush_gpu_tlb = gmc_v6_0_emit_flush_gpu_tlb,
1172         .set_pte_pde = gmc_v6_0_set_pte_pde,
1173         .set_prt = gmc_v6_0_set_prt,
1174         .get_vm_pde = gmc_v6_0_get_vm_pde,
1175         .get_vm_pte_flags = gmc_v6_0_get_vm_pte_flags
1176 };
1177
1178 static const struct amdgpu_irq_src_funcs gmc_v6_0_irq_funcs = {
1179         .set = gmc_v6_0_vm_fault_interrupt_state,
1180         .process = gmc_v6_0_process_interrupt,
1181 };
1182
1183 static void gmc_v6_0_set_gmc_funcs(struct amdgpu_device *adev)
1184 {
1185         adev->gmc.gmc_funcs = &gmc_v6_0_gmc_funcs;
1186 }
1187
1188 static void gmc_v6_0_set_irq_funcs(struct amdgpu_device *adev)
1189 {
1190         adev->gmc.vm_fault.num_types = 1;
1191         adev->gmc.vm_fault.funcs = &gmc_v6_0_irq_funcs;
1192 }
1193
1194 const struct amdgpu_ip_block_version gmc_v6_0_ip_block =
1195 {
1196         .type = AMD_IP_BLOCK_TYPE_GMC,
1197         .major = 6,
1198         .minor = 0,
1199         .rev = 0,
1200         .funcs = &gmc_v6_0_ip_funcs,
1201 };