2 * Copyright 2019 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
23 #include <linux/firmware.h>
24 #include <linux/pci.h>
26 #include <drm/drm_cache.h>
29 #include "amdgpu_atomfirmware.h"
30 #include "gmc_v10_0.h"
33 #include "athub/athub_2_0_0_sh_mask.h"
34 #include "athub/athub_2_0_0_offset.h"
35 #include "dcn/dcn_2_0_0_offset.h"
36 #include "dcn/dcn_2_0_0_sh_mask.h"
37 #include "oss/osssys_5_0_0_offset.h"
38 #include "ivsrcid/vmc/irqsrcs_vmc_1_0.h"
39 #include "navi10_enum.h"
43 #include "soc15_common.h"
45 #include "nbio_v2_3.h"
47 #include "gfxhub_v2_0.h"
48 #include "gfxhub_v2_1.h"
49 #include "mmhub_v2_0.h"
50 #include "mmhub_v2_3.h"
51 #include "athub_v2_0.h"
52 #include "athub_v2_1.h"
54 #include "amdgpu_reset.h"
56 static int gmc_v10_0_ecc_interrupt_state(struct amdgpu_device *adev,
57 struct amdgpu_irq_src *src,
59 enum amdgpu_interrupt_state state)
65 gmc_v10_0_vm_fault_interrupt_state(struct amdgpu_device *adev,
66 struct amdgpu_irq_src *src, unsigned int type,
67 enum amdgpu_interrupt_state state)
70 case AMDGPU_IRQ_STATE_DISABLE:
72 amdgpu_gmc_set_vm_fault_masks(adev, AMDGPU_MMHUB0(0), false);
74 /* This works because this interrupt is only
75 * enabled at init/resume and disabled in
76 * fini/suspend, so the overall state doesn't
77 * change over the course of suspend/resume.
80 amdgpu_gmc_set_vm_fault_masks(adev, AMDGPU_GFXHUB(0), false);
82 case AMDGPU_IRQ_STATE_ENABLE:
84 amdgpu_gmc_set_vm_fault_masks(adev, AMDGPU_MMHUB0(0), true);
86 /* This works because this interrupt is only
87 * enabled at init/resume and disabled in
88 * fini/suspend, so the overall state doesn't
89 * change over the course of suspend/resume.
92 amdgpu_gmc_set_vm_fault_masks(adev, AMDGPU_GFXHUB(0), true);
101 static int gmc_v10_0_process_interrupt(struct amdgpu_device *adev,
102 struct amdgpu_irq_src *source,
103 struct amdgpu_iv_entry *entry)
105 uint32_t vmhub_index = entry->client_id == SOC15_IH_CLIENTID_VMC ?
106 AMDGPU_MMHUB0(0) : AMDGPU_GFXHUB(0);
107 struct amdgpu_vmhub *hub = &adev->vmhub[vmhub_index];
108 bool retry_fault = !!(entry->src_data[1] & 0x80);
109 bool write_fault = !!(entry->src_data[1] & 0x20);
110 struct amdgpu_task_info task_info;
114 addr = (u64)entry->src_data[0] << 12;
115 addr |= ((u64)entry->src_data[1] & 0xf) << 44;
118 /* Returning 1 here also prevents sending the IV to the KFD */
120 /* Process it onyl if it's the first fault for this address */
121 if (entry->ih != &adev->irq.ih_soft &&
122 amdgpu_gmc_filter_faults(adev, entry->ih, addr, entry->pasid,
126 /* Delegate it to a different ring if the hardware hasn't
129 if (entry->ih == &adev->irq.ih) {
130 amdgpu_irq_delegate(adev, entry, 8);
134 /* Try to handle the recoverable page faults by filling page
137 if (amdgpu_vm_handle_fault(adev, entry->pasid, 0, 0, addr, write_fault))
141 if (!amdgpu_sriov_vf(adev)) {
143 * Issue a dummy read to wait for the status register to
144 * be updated to avoid reading an incorrect value due to
145 * the new fast GRBM interface.
147 if ((entry->vmid_src == AMDGPU_GFXHUB(0)) &&
148 (adev->ip_versions[GC_HWIP][0] < IP_VERSION(10, 3, 0)))
149 RREG32(hub->vm_l2_pro_fault_status);
151 status = RREG32(hub->vm_l2_pro_fault_status);
152 WREG32_P(hub->vm_l2_pro_fault_cntl, 1, ~1);
155 if (!printk_ratelimit())
158 memset(&task_info, 0, sizeof(struct amdgpu_task_info));
159 amdgpu_vm_get_task_info(adev, entry->pasid, &task_info);
162 "[%s] page fault (src_id:%u ring:%u vmid:%u pasid:%u, for process %s pid %d thread %s pid %d)\n",
163 entry->vmid_src ? "mmhub" : "gfxhub",
164 entry->src_id, entry->ring_id, entry->vmid,
165 entry->pasid, task_info.process_name, task_info.tgid,
166 task_info.task_name, task_info.pid);
167 dev_err(adev->dev, " in page starting at address 0x%016llx from client 0x%x (%s)\n",
168 addr, entry->client_id,
169 soc15_ih_clientid_name[entry->client_id]);
171 if (!amdgpu_sriov_vf(adev))
172 hub->vmhub_funcs->print_l2_protection_fault_status(adev,
178 static const struct amdgpu_irq_src_funcs gmc_v10_0_irq_funcs = {
179 .set = gmc_v10_0_vm_fault_interrupt_state,
180 .process = gmc_v10_0_process_interrupt,
183 static const struct amdgpu_irq_src_funcs gmc_v10_0_ecc_funcs = {
184 .set = gmc_v10_0_ecc_interrupt_state,
185 .process = amdgpu_umc_process_ecc_irq,
188 static void gmc_v10_0_set_irq_funcs(struct amdgpu_device *adev)
190 adev->gmc.vm_fault.num_types = 1;
191 adev->gmc.vm_fault.funcs = &gmc_v10_0_irq_funcs;
193 if (!amdgpu_sriov_vf(adev)) {
194 adev->gmc.ecc_irq.num_types = 1;
195 adev->gmc.ecc_irq.funcs = &gmc_v10_0_ecc_funcs;
200 * gmc_v10_0_use_invalidate_semaphore - judge whether to use semaphore
202 * @adev: amdgpu_device pointer
206 static bool gmc_v10_0_use_invalidate_semaphore(struct amdgpu_device *adev,
209 return ((vmhub == AMDGPU_MMHUB0(0)) &&
210 (!amdgpu_sriov_vf(adev)));
213 static bool gmc_v10_0_get_atc_vmid_pasid_mapping_info(
214 struct amdgpu_device *adev,
215 uint8_t vmid, uint16_t *p_pasid)
219 value = RREG32(SOC15_REG_OFFSET(ATHUB, 0, mmATC_VMID0_PASID_MAPPING)
221 *p_pasid = value & ATC_VMID0_PASID_MAPPING__PASID_MASK;
223 return !!(value & ATC_VMID0_PASID_MAPPING__VALID_MASK);
228 * VMID 0 is the physical GPU addresses as used by the kernel.
229 * VMIDs 1-15 are used for userspace clients and are handled
230 * by the amdgpu vm/hsa code.
233 static void gmc_v10_0_flush_vm_hub(struct amdgpu_device *adev, uint32_t vmid,
234 unsigned int vmhub, uint32_t flush_type)
236 bool use_semaphore = gmc_v10_0_use_invalidate_semaphore(adev, vmhub);
237 struct amdgpu_vmhub *hub = &adev->vmhub[vmhub];
238 u32 inv_req = hub->vmhub_funcs->get_invalidate_req(vmid, flush_type);
240 /* Use register 17 for GART */
241 const unsigned int eng = 17;
243 unsigned char hub_ip = 0;
245 hub_ip = (vmhub == AMDGPU_GFXHUB(0)) ?
246 GC_HWIP : MMHUB_HWIP;
248 spin_lock(&adev->gmc.invalidate_lock);
250 * It may lose gpuvm invalidate acknowldege state across power-gating
251 * off cycle, add semaphore acquire before invalidation and semaphore
252 * release after invalidation to avoid entering power gated state
256 /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */
258 for (i = 0; i < adev->usec_timeout; i++) {
259 /* a read return value of 1 means semaphore acuqire */
260 tmp = RREG32_RLC_NO_KIQ(hub->vm_inv_eng0_sem +
261 hub->eng_distance * eng, hub_ip);
268 if (i >= adev->usec_timeout)
269 DRM_ERROR("Timeout waiting for sem acquire in VM flush!\n");
272 WREG32_RLC_NO_KIQ(hub->vm_inv_eng0_req +
273 hub->eng_distance * eng,
277 * Issue a dummy read to wait for the ACK register to be cleared
278 * to avoid a false ACK due to the new fast GRBM interface.
280 if ((vmhub == AMDGPU_GFXHUB(0)) &&
281 (adev->ip_versions[GC_HWIP][0] < IP_VERSION(10, 3, 0)))
282 RREG32_RLC_NO_KIQ(hub->vm_inv_eng0_req +
283 hub->eng_distance * eng, hub_ip);
285 /* Wait for ACK with a delay.*/
286 for (i = 0; i < adev->usec_timeout; i++) {
287 tmp = RREG32_RLC_NO_KIQ(hub->vm_inv_eng0_ack +
288 hub->eng_distance * eng, hub_ip);
297 /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */
300 * add semaphore release after invalidation,
301 * write with 0 means semaphore release
303 WREG32_RLC_NO_KIQ(hub->vm_inv_eng0_sem +
304 hub->eng_distance * eng, 0, hub_ip);
306 spin_unlock(&adev->gmc.invalidate_lock);
308 if (i < adev->usec_timeout)
311 DRM_ERROR("Timeout waiting for VM flush hub: %d!\n", vmhub);
315 * gmc_v10_0_flush_gpu_tlb - gart tlb flush callback
317 * @adev: amdgpu_device pointer
318 * @vmid: vm instance to flush
320 * @flush_type: the flush type
322 * Flush the TLB for the requested page table.
324 static void gmc_v10_0_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid,
325 uint32_t vmhub, uint32_t flush_type)
327 struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring;
328 struct dma_fence *fence;
329 struct amdgpu_job *job;
333 /* flush hdp cache */
334 adev->hdp.funcs->flush_hdp(adev, NULL);
336 /* For SRIOV run time, driver shouldn't access the register through MMIO
337 * Directly use kiq to do the vm invalidation instead
339 if (adev->gfx.kiq[0].ring.sched.ready && !adev->enable_mes &&
340 (amdgpu_sriov_runtime(adev) || !amdgpu_sriov_vf(adev)) &&
341 down_read_trylock(&adev->reset_domain->sem)) {
342 struct amdgpu_vmhub *hub = &adev->vmhub[vmhub];
343 const unsigned int eng = 17;
344 u32 inv_req = hub->vmhub_funcs->get_invalidate_req(vmid, flush_type);
345 u32 req = hub->vm_inv_eng0_req + hub->eng_distance * eng;
346 u32 ack = hub->vm_inv_eng0_ack + hub->eng_distance * eng;
348 amdgpu_virt_kiq_reg_write_reg_wait(adev, req, ack, inv_req,
351 up_read(&adev->reset_domain->sem);
355 mutex_lock(&adev->mman.gtt_window_lock);
357 if (vmhub == AMDGPU_MMHUB0(0)) {
358 gmc_v10_0_flush_vm_hub(adev, vmid, AMDGPU_MMHUB0(0), 0);
359 mutex_unlock(&adev->mman.gtt_window_lock);
363 BUG_ON(vmhub != AMDGPU_GFXHUB(0));
365 if (!adev->mman.buffer_funcs_enabled ||
366 !adev->ib_pool_ready ||
367 amdgpu_in_reset(adev) ||
368 ring->sched.ready == false) {
369 gmc_v10_0_flush_vm_hub(adev, vmid, AMDGPU_GFXHUB(0), 0);
370 mutex_unlock(&adev->mman.gtt_window_lock);
374 /* The SDMA on Navi has a bug which can theoretically result in memory
375 * corruption if an invalidation happens at the same time as an VA
376 * translation. Avoid this by doing the invalidation from the SDMA
379 r = amdgpu_job_alloc_with_ib(ring->adev, &adev->mman.high_pr,
380 AMDGPU_FENCE_OWNER_UNDEFINED,
381 16 * 4, AMDGPU_IB_POOL_IMMEDIATE,
386 job->vm_pd_addr = amdgpu_gmc_pd_addr(adev->gart.bo);
387 job->vm_needs_flush = true;
388 job->ibs->ptr[job->ibs->length_dw++] = ring->funcs->nop;
389 amdgpu_ring_pad_ib(ring, &job->ibs[0]);
390 fence = amdgpu_job_submit(job);
392 mutex_unlock(&adev->mman.gtt_window_lock);
394 dma_fence_wait(fence, false);
395 dma_fence_put(fence);
400 mutex_unlock(&adev->mman.gtt_window_lock);
401 DRM_ERROR("Error flushing GPU TLB using the SDMA (%d)!\n", r);
405 * gmc_v10_0_flush_gpu_tlb_pasid - tlb flush via pasid
407 * @adev: amdgpu_device pointer
408 * @pasid: pasid to be flush
409 * @flush_type: the flush type
410 * @all_hub: Used with PACKET3_INVALIDATE_TLBS_ALL_HUB()
411 * @inst: is used to select which instance of KIQ to use for the invalidation
413 * Flush the TLB for the requested pasid.
415 static int gmc_v10_0_flush_gpu_tlb_pasid(struct amdgpu_device *adev,
416 uint16_t pasid, uint32_t flush_type,
417 bool all_hub, uint32_t inst)
422 uint16_t queried_pasid;
424 u32 usec_timeout = amdgpu_sriov_vf(adev) ? SRIOV_USEC_TIMEOUT : adev->usec_timeout;
425 struct amdgpu_ring *ring = &adev->gfx.kiq[0].ring;
426 struct amdgpu_kiq *kiq = &adev->gfx.kiq[0];
428 if (amdgpu_emu_mode == 0 && ring->sched.ready) {
429 spin_lock(&adev->gfx.kiq[0].ring_lock);
430 /* 2 dwords flush + 8 dwords fence */
431 amdgpu_ring_alloc(ring, kiq->pmf->invalidate_tlbs_size + 8);
432 kiq->pmf->kiq_invalidate_tlbs(ring,
433 pasid, flush_type, all_hub);
434 r = amdgpu_fence_emit_polling(ring, &seq, MAX_KIQ_REG_WAIT);
436 amdgpu_ring_undo(ring);
437 spin_unlock(&adev->gfx.kiq[0].ring_lock);
441 amdgpu_ring_commit(ring);
442 spin_unlock(&adev->gfx.kiq[0].ring_lock);
443 r = amdgpu_fence_wait_polling(ring, seq, usec_timeout);
445 dev_err(adev->dev, "wait for kiq fence error: %ld.\n", r);
452 for (vmid = 1; vmid < AMDGPU_NUM_VMID; vmid++) {
454 ret = gmc_v10_0_get_atc_vmid_pasid_mapping_info(adev, vmid,
456 if (ret && queried_pasid == pasid) {
458 for_each_set_bit(i, adev->vmhubs_mask, AMDGPU_MAX_VMHUBS)
459 gmc_v10_0_flush_gpu_tlb(adev, vmid,
462 gmc_v10_0_flush_gpu_tlb(adev, vmid,
463 AMDGPU_GFXHUB(0), flush_type);
465 if (!adev->enable_mes)
473 static uint64_t gmc_v10_0_emit_flush_gpu_tlb(struct amdgpu_ring *ring,
474 unsigned int vmid, uint64_t pd_addr)
476 bool use_semaphore = gmc_v10_0_use_invalidate_semaphore(ring->adev, ring->vm_hub);
477 struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->vm_hub];
478 uint32_t req = hub->vmhub_funcs->get_invalidate_req(vmid, 0);
479 unsigned int eng = ring->vm_inv_eng;
482 * It may lose gpuvm invalidate acknowldege state across power-gating
483 * off cycle, add semaphore acquire before invalidation and semaphore
484 * release after invalidation to avoid entering power gated state
488 /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */
490 /* a read return value of 1 means semaphore acuqire */
491 amdgpu_ring_emit_reg_wait(ring,
492 hub->vm_inv_eng0_sem +
493 hub->eng_distance * eng, 0x1, 0x1);
495 amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_lo32 +
496 (hub->ctx_addr_distance * vmid),
497 lower_32_bits(pd_addr));
499 amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_hi32 +
500 (hub->ctx_addr_distance * vmid),
501 upper_32_bits(pd_addr));
503 amdgpu_ring_emit_reg_write_reg_wait(ring, hub->vm_inv_eng0_req +
504 hub->eng_distance * eng,
505 hub->vm_inv_eng0_ack +
506 hub->eng_distance * eng,
509 /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */
512 * add semaphore release after invalidation,
513 * write with 0 means semaphore release
515 amdgpu_ring_emit_wreg(ring, hub->vm_inv_eng0_sem +
516 hub->eng_distance * eng, 0);
521 static void gmc_v10_0_emit_pasid_mapping(struct amdgpu_ring *ring, unsigned int vmid,
524 struct amdgpu_device *adev = ring->adev;
527 /* MES fw manages IH_VMID_x_LUT updating */
528 if (ring->is_mes_queue)
531 if (ring->vm_hub == AMDGPU_GFXHUB(0))
532 reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT) + vmid;
534 reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT_MM) + vmid;
536 amdgpu_ring_emit_wreg(ring, reg, pasid);
540 * PTE format on NAVI 10:
542 * 58 reserved and for sienna_cichlid is used for MALL noalloc
550 * 47:12 4k physical page base address
560 * PDE format on NAVI 10:
561 * 63:59 block fragment size
565 * 47:6 physical base address of PD or PTE
572 static uint64_t gmc_v10_0_map_mtype(struct amdgpu_device *adev, uint32_t flags)
575 case AMDGPU_VM_MTYPE_DEFAULT:
576 return AMDGPU_PTE_MTYPE_NV10(MTYPE_NC);
577 case AMDGPU_VM_MTYPE_NC:
578 return AMDGPU_PTE_MTYPE_NV10(MTYPE_NC);
579 case AMDGPU_VM_MTYPE_WC:
580 return AMDGPU_PTE_MTYPE_NV10(MTYPE_WC);
581 case AMDGPU_VM_MTYPE_CC:
582 return AMDGPU_PTE_MTYPE_NV10(MTYPE_CC);
583 case AMDGPU_VM_MTYPE_UC:
584 return AMDGPU_PTE_MTYPE_NV10(MTYPE_UC);
586 return AMDGPU_PTE_MTYPE_NV10(MTYPE_NC);
590 static void gmc_v10_0_get_vm_pde(struct amdgpu_device *adev, int level,
591 uint64_t *addr, uint64_t *flags)
593 if (!(*flags & AMDGPU_PDE_PTE) && !(*flags & AMDGPU_PTE_SYSTEM))
594 *addr = amdgpu_gmc_vram_mc2pa(adev, *addr);
595 BUG_ON(*addr & 0xFFFF00000000003FULL);
597 if (!adev->gmc.translate_further)
600 if (level == AMDGPU_VM_PDB1) {
601 /* Set the block fragment size */
602 if (!(*flags & AMDGPU_PDE_PTE))
603 *flags |= AMDGPU_PDE_BFS(0x9);
605 } else if (level == AMDGPU_VM_PDB0) {
606 if (*flags & AMDGPU_PDE_PTE)
607 *flags &= ~AMDGPU_PDE_PTE;
609 *flags |= AMDGPU_PTE_TF;
613 static void gmc_v10_0_get_vm_pte(struct amdgpu_device *adev,
614 struct amdgpu_bo_va_mapping *mapping,
617 struct amdgpu_bo *bo = mapping->bo_va->base.bo;
619 *flags &= ~AMDGPU_PTE_EXECUTABLE;
620 *flags |= mapping->flags & AMDGPU_PTE_EXECUTABLE;
622 *flags &= ~AMDGPU_PTE_MTYPE_NV10_MASK;
623 *flags |= (mapping->flags & AMDGPU_PTE_MTYPE_NV10_MASK);
625 *flags &= ~AMDGPU_PTE_NOALLOC;
626 *flags |= (mapping->flags & AMDGPU_PTE_NOALLOC);
628 if (mapping->flags & AMDGPU_PTE_PRT) {
629 *flags |= AMDGPU_PTE_PRT;
630 *flags |= AMDGPU_PTE_SNOOPED;
631 *flags |= AMDGPU_PTE_LOG;
632 *flags |= AMDGPU_PTE_SYSTEM;
633 *flags &= ~AMDGPU_PTE_VALID;
636 if (bo && bo->flags & (AMDGPU_GEM_CREATE_COHERENT |
637 AMDGPU_GEM_CREATE_UNCACHED))
638 *flags = (*flags & ~AMDGPU_PTE_MTYPE_NV10_MASK) |
639 AMDGPU_PTE_MTYPE_NV10(MTYPE_UC);
642 static unsigned int gmc_v10_0_get_vbios_fb_size(struct amdgpu_device *adev)
644 u32 d1vga_control = RREG32_SOC15(DCE, 0, mmD1VGA_CONTROL);
647 if (REG_GET_FIELD(d1vga_control, D1VGA_CONTROL, D1VGA_MODE_ENABLE)) {
648 size = AMDGPU_VBIOS_VGA_ALLOCATION;
653 viewport = RREG32_SOC15(DCE, 0, mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION);
654 pitch = RREG32_SOC15(DCE, 0, mmHUBPREQ0_DCSURF_SURFACE_PITCH);
655 size = (REG_GET_FIELD(viewport,
656 HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION, PRI_VIEWPORT_HEIGHT) *
657 REG_GET_FIELD(pitch, HUBPREQ0_DCSURF_SURFACE_PITCH, PITCH) *
664 static const struct amdgpu_gmc_funcs gmc_v10_0_gmc_funcs = {
665 .flush_gpu_tlb = gmc_v10_0_flush_gpu_tlb,
666 .flush_gpu_tlb_pasid = gmc_v10_0_flush_gpu_tlb_pasid,
667 .emit_flush_gpu_tlb = gmc_v10_0_emit_flush_gpu_tlb,
668 .emit_pasid_mapping = gmc_v10_0_emit_pasid_mapping,
669 .map_mtype = gmc_v10_0_map_mtype,
670 .get_vm_pde = gmc_v10_0_get_vm_pde,
671 .get_vm_pte = gmc_v10_0_get_vm_pte,
672 .get_vbios_fb_size = gmc_v10_0_get_vbios_fb_size,
675 static void gmc_v10_0_set_gmc_funcs(struct amdgpu_device *adev)
677 if (adev->gmc.gmc_funcs == NULL)
678 adev->gmc.gmc_funcs = &gmc_v10_0_gmc_funcs;
681 static void gmc_v10_0_set_umc_funcs(struct amdgpu_device *adev)
683 switch (adev->ip_versions[UMC_HWIP][0]) {
684 case IP_VERSION(8, 7, 0):
685 adev->umc.max_ras_err_cnt_per_query = UMC_V8_7_TOTAL_CHANNEL_NUM;
686 adev->umc.channel_inst_num = UMC_V8_7_CHANNEL_INSTANCE_NUM;
687 adev->umc.umc_inst_num = UMC_V8_7_UMC_INSTANCE_NUM;
688 adev->umc.channel_offs = UMC_V8_7_PER_CHANNEL_OFFSET_SIENNA;
689 adev->umc.retire_unit = 1;
690 adev->umc.channel_idx_tbl = &umc_v8_7_channel_idx_tbl[0][0];
691 adev->umc.ras = &umc_v8_7_ras;
698 static void gmc_v10_0_set_mmhub_funcs(struct amdgpu_device *adev)
700 switch (adev->ip_versions[MMHUB_HWIP][0]) {
701 case IP_VERSION(2, 3, 0):
702 case IP_VERSION(2, 4, 0):
703 case IP_VERSION(2, 4, 1):
704 adev->mmhub.funcs = &mmhub_v2_3_funcs;
707 adev->mmhub.funcs = &mmhub_v2_0_funcs;
712 static void gmc_v10_0_set_gfxhub_funcs(struct amdgpu_device *adev)
714 switch (adev->ip_versions[GC_HWIP][0]) {
715 case IP_VERSION(10, 3, 0):
716 case IP_VERSION(10, 3, 2):
717 case IP_VERSION(10, 3, 1):
718 case IP_VERSION(10, 3, 4):
719 case IP_VERSION(10, 3, 5):
720 case IP_VERSION(10, 3, 6):
721 case IP_VERSION(10, 3, 3):
722 case IP_VERSION(10, 3, 7):
723 adev->gfxhub.funcs = &gfxhub_v2_1_funcs;
726 adev->gfxhub.funcs = &gfxhub_v2_0_funcs;
732 static int gmc_v10_0_early_init(void *handle)
734 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
736 gmc_v10_0_set_mmhub_funcs(adev);
737 gmc_v10_0_set_gfxhub_funcs(adev);
738 gmc_v10_0_set_gmc_funcs(adev);
739 gmc_v10_0_set_irq_funcs(adev);
740 gmc_v10_0_set_umc_funcs(adev);
742 adev->gmc.shared_aperture_start = 0x2000000000000000ULL;
743 adev->gmc.shared_aperture_end =
744 adev->gmc.shared_aperture_start + (4ULL << 30) - 1;
745 adev->gmc.private_aperture_start = 0x1000000000000000ULL;
746 adev->gmc.private_aperture_end =
747 adev->gmc.private_aperture_start + (4ULL << 30) - 1;
748 adev->gmc.noretry_flags = AMDGPU_VM_NORETRY_FLAGS_TF;
753 static int gmc_v10_0_late_init(void *handle)
755 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
758 r = amdgpu_gmc_allocate_vm_inv_eng(adev);
762 r = amdgpu_gmc_ras_late_init(adev);
766 return amdgpu_irq_get(adev, &adev->gmc.vm_fault, 0);
769 static void gmc_v10_0_vram_gtt_location(struct amdgpu_device *adev,
770 struct amdgpu_gmc *mc)
774 base = adev->gfxhub.funcs->get_fb_location(adev);
776 /* add the xgmi offset of the physical node */
777 base += adev->gmc.xgmi.physical_node_id * adev->gmc.xgmi.node_segment_size;
779 amdgpu_gmc_vram_location(adev, &adev->gmc, base);
780 amdgpu_gmc_gart_location(adev, mc);
781 amdgpu_gmc_agp_location(adev, mc);
783 /* base offset of vram pages */
784 adev->vm_manager.vram_base_offset = adev->gfxhub.funcs->get_mc_fb_offset(adev);
786 /* add the xgmi offset of the physical node */
787 adev->vm_manager.vram_base_offset +=
788 adev->gmc.xgmi.physical_node_id * adev->gmc.xgmi.node_segment_size;
792 * gmc_v10_0_mc_init - initialize the memory controller driver params
794 * @adev: amdgpu_device pointer
796 * Look up the amount of vram, vram width, and decide how to place
797 * vram and gart within the GPU's physical address space.
798 * Returns 0 for success.
800 static int gmc_v10_0_mc_init(struct amdgpu_device *adev)
804 /* size in MB on si */
805 adev->gmc.mc_vram_size =
806 adev->nbio.funcs->get_memsize(adev) * 1024ULL * 1024ULL;
807 adev->gmc.real_vram_size = adev->gmc.mc_vram_size;
809 if (!(adev->flags & AMD_IS_APU)) {
810 r = amdgpu_device_resize_fb_bar(adev);
814 adev->gmc.aper_base = pci_resource_start(adev->pdev, 0);
815 adev->gmc.aper_size = pci_resource_len(adev->pdev, 0);
818 if ((adev->flags & AMD_IS_APU) && !amdgpu_passthrough(adev)) {
819 adev->gmc.aper_base = adev->gfxhub.funcs->get_mc_fb_offset(adev);
820 adev->gmc.aper_size = adev->gmc.real_vram_size;
824 adev->gmc.visible_vram_size = adev->gmc.aper_size;
826 /* set the gart size */
827 if (amdgpu_gart_size == -1) {
828 switch (adev->ip_versions[GC_HWIP][0]) {
830 adev->gmc.gart_size = 512ULL << 20;
832 case IP_VERSION(10, 3, 1): /* DCE SG support */
833 case IP_VERSION(10, 3, 3): /* DCE SG support */
834 case IP_VERSION(10, 3, 6): /* DCE SG support */
835 case IP_VERSION(10, 3, 7): /* DCE SG support */
836 adev->gmc.gart_size = 1024ULL << 20;
840 adev->gmc.gart_size = (u64)amdgpu_gart_size << 20;
843 gmc_v10_0_vram_gtt_location(adev, &adev->gmc);
848 static int gmc_v10_0_gart_init(struct amdgpu_device *adev)
853 WARN(1, "NAVI10 PCIE GART already initialized\n");
857 /* Initialize common gart structure */
858 r = amdgpu_gart_init(adev);
862 adev->gart.table_size = adev->gart.num_gpu_pages * 8;
863 adev->gart.gart_pte_flags = AMDGPU_PTE_MTYPE_NV10(MTYPE_UC) |
864 AMDGPU_PTE_EXECUTABLE;
866 return amdgpu_gart_table_vram_alloc(adev);
869 static int gmc_v10_0_sw_init(void *handle)
871 int r, vram_width = 0, vram_type = 0, vram_vendor = 0;
872 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
874 adev->gfxhub.funcs->init(adev);
876 adev->mmhub.funcs->init(adev);
878 spin_lock_init(&adev->gmc.invalidate_lock);
880 if ((adev->flags & AMD_IS_APU) && amdgpu_emu_mode == 1) {
881 adev->gmc.vram_type = AMDGPU_VRAM_TYPE_DDR4;
882 adev->gmc.vram_width = 64;
883 } else if (amdgpu_emu_mode == 1) {
884 adev->gmc.vram_type = AMDGPU_VRAM_TYPE_GDDR6;
885 adev->gmc.vram_width = 1 * 128; /* numchan * chansize */
887 r = amdgpu_atomfirmware_get_vram_info(adev,
888 &vram_width, &vram_type, &vram_vendor);
889 adev->gmc.vram_width = vram_width;
891 adev->gmc.vram_type = vram_type;
892 adev->gmc.vram_vendor = vram_vendor;
895 switch (adev->ip_versions[GC_HWIP][0]) {
896 case IP_VERSION(10, 3, 0):
897 adev->gmc.mall_size = 128 * 1024 * 1024;
899 case IP_VERSION(10, 3, 2):
900 adev->gmc.mall_size = 96 * 1024 * 1024;
902 case IP_VERSION(10, 3, 4):
903 adev->gmc.mall_size = 32 * 1024 * 1024;
905 case IP_VERSION(10, 3, 5):
906 adev->gmc.mall_size = 16 * 1024 * 1024;
909 adev->gmc.mall_size = 0;
913 switch (adev->ip_versions[GC_HWIP][0]) {
914 case IP_VERSION(10, 1, 10):
915 case IP_VERSION(10, 1, 1):
916 case IP_VERSION(10, 1, 2):
917 case IP_VERSION(10, 1, 3):
918 case IP_VERSION(10, 1, 4):
919 case IP_VERSION(10, 3, 0):
920 case IP_VERSION(10, 3, 2):
921 case IP_VERSION(10, 3, 1):
922 case IP_VERSION(10, 3, 4):
923 case IP_VERSION(10, 3, 5):
924 case IP_VERSION(10, 3, 6):
925 case IP_VERSION(10, 3, 3):
926 case IP_VERSION(10, 3, 7):
927 set_bit(AMDGPU_GFXHUB(0), adev->vmhubs_mask);
928 set_bit(AMDGPU_MMHUB0(0), adev->vmhubs_mask);
930 * To fulfill 4-level page support,
931 * vm size is 256TB (48bit), maximum size of Navi10/Navi14/Navi12,
932 * block size 512 (9bit)
934 amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 48);
940 /* This interrupt is VMC page fault.*/
941 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VMC,
942 VMC_1_0__SRCID__VM_FAULT,
943 &adev->gmc.vm_fault);
948 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_UTCL2,
949 UTCL2_1_0__SRCID__FAULT,
950 &adev->gmc.vm_fault);
954 if (!amdgpu_sriov_vf(adev)) {
955 /* interrupt sent to DF. */
956 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DF, 0,
963 * Set the internal MC address mask This is the max address of the GPU's
964 * internal address space.
966 adev->gmc.mc_mask = 0xffffffffffffULL; /* 48 bit MC */
968 r = dma_set_mask_and_coherent(adev->dev, DMA_BIT_MASK(44));
970 dev_warn(adev->dev, "amdgpu: No suitable DMA available.\n");
974 adev->need_swiotlb = drm_need_swiotlb(44);
976 r = gmc_v10_0_mc_init(adev);
980 amdgpu_gmc_get_vbios_allocations(adev);
983 r = amdgpu_bo_init(adev);
987 r = gmc_v10_0_gart_init(adev);
993 * VMID 0 is reserved for System
994 * amdgpu graphics/compute will use VMIDs 1-7
995 * amdkfd will use VMIDs 8-15
997 adev->vm_manager.first_kfd_vmid = 8;
999 amdgpu_vm_manager_init(adev);
1001 r = amdgpu_gmc_ras_sw_init(adev);
1009 * gmc_v10_0_gart_fini - vm fini callback
1011 * @adev: amdgpu_device pointer
1013 * Tears down the driver GART/VM setup (CIK).
1015 static void gmc_v10_0_gart_fini(struct amdgpu_device *adev)
1017 amdgpu_gart_table_vram_free(adev);
1020 static int gmc_v10_0_sw_fini(void *handle)
1022 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1024 amdgpu_vm_manager_fini(adev);
1025 gmc_v10_0_gart_fini(adev);
1026 amdgpu_gem_force_release(adev);
1027 amdgpu_bo_fini(adev);
1032 static void gmc_v10_0_init_golden_registers(struct amdgpu_device *adev)
1037 * gmc_v10_0_gart_enable - gart enable
1039 * @adev: amdgpu_device pointer
1041 static int gmc_v10_0_gart_enable(struct amdgpu_device *adev)
1046 if (adev->gart.bo == NULL) {
1047 dev_err(adev->dev, "No VRAM object for PCIE GART.\n");
1051 amdgpu_gtt_mgr_recover(&adev->mman.gtt_mgr);
1053 if (!adev->in_s0ix) {
1054 r = adev->gfxhub.funcs->gart_enable(adev);
1059 r = adev->mmhub.funcs->gart_enable(adev);
1063 adev->hdp.funcs->init_registers(adev);
1065 /* Flush HDP after it is initialized */
1066 adev->hdp.funcs->flush_hdp(adev, NULL);
1068 value = (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS) ?
1072 adev->gfxhub.funcs->set_fault_enable_default(adev, value);
1073 adev->mmhub.funcs->set_fault_enable_default(adev, value);
1074 gmc_v10_0_flush_gpu_tlb(adev, 0, AMDGPU_MMHUB0(0), 0);
1076 gmc_v10_0_flush_gpu_tlb(adev, 0, AMDGPU_GFXHUB(0), 0);
1078 DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
1079 (unsigned int)(adev->gmc.gart_size >> 20),
1080 (unsigned long long)amdgpu_bo_gpu_offset(adev->gart.bo));
1085 static int gmc_v10_0_hw_init(void *handle)
1088 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1090 /* The sequence of these two function calls matters.*/
1091 gmc_v10_0_init_golden_registers(adev);
1094 * harvestable groups in gc_utcl2 need to be programmed before any GFX block
1095 * register setup within GMC, or else system hang when harvesting SA.
1097 if (!adev->in_s0ix && adev->gfxhub.funcs && adev->gfxhub.funcs->utcl2_harvest)
1098 adev->gfxhub.funcs->utcl2_harvest(adev);
1100 r = gmc_v10_0_gart_enable(adev);
1104 if (amdgpu_emu_mode == 1) {
1105 r = amdgpu_gmc_vram_checking(adev);
1110 if (adev->umc.funcs && adev->umc.funcs->init_registers)
1111 adev->umc.funcs->init_registers(adev);
1117 * gmc_v10_0_gart_disable - gart disable
1119 * @adev: amdgpu_device pointer
1121 * This disables all VM page table.
1123 static void gmc_v10_0_gart_disable(struct amdgpu_device *adev)
1126 adev->gfxhub.funcs->gart_disable(adev);
1127 adev->mmhub.funcs->gart_disable(adev);
1130 static int gmc_v10_0_hw_fini(void *handle)
1132 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1134 gmc_v10_0_gart_disable(adev);
1136 if (amdgpu_sriov_vf(adev)) {
1137 /* full access mode, so don't touch any GMC register */
1138 DRM_DEBUG("For SRIOV client, shouldn't do anything.\n");
1142 amdgpu_irq_put(adev, &adev->gmc.vm_fault, 0);
1147 static int gmc_v10_0_suspend(void *handle)
1149 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1151 gmc_v10_0_hw_fini(adev);
1156 static int gmc_v10_0_resume(void *handle)
1159 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1161 r = gmc_v10_0_hw_init(adev);
1165 amdgpu_vmid_reset_all(adev);
1170 static bool gmc_v10_0_is_idle(void *handle)
1172 /* MC is always ready in GMC v10.*/
1176 static int gmc_v10_0_wait_for_idle(void *handle)
1178 /* There is no need to wait for MC idle in GMC v10.*/
1182 static int gmc_v10_0_soft_reset(void *handle)
1187 static int gmc_v10_0_set_clockgating_state(void *handle,
1188 enum amd_clockgating_state state)
1191 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1194 * The issue mmhub can't disconnect from DF with MMHUB clock gating being disabled
1195 * is a new problem observed at DF 3.0.3, however with the same suspend sequence not
1196 * seen any issue on the DF 3.0.2 series platform.
1198 if (adev->in_s0ix && adev->ip_versions[DF_HWIP][0] > IP_VERSION(3, 0, 2)) {
1199 dev_dbg(adev->dev, "keep mmhub clock gating being enabled for s0ix\n");
1203 r = adev->mmhub.funcs->set_clockgating(adev, state);
1207 if (adev->ip_versions[ATHUB_HWIP][0] >= IP_VERSION(2, 1, 0))
1208 return athub_v2_1_set_clockgating(adev, state);
1210 return athub_v2_0_set_clockgating(adev, state);
1213 static void gmc_v10_0_get_clockgating_state(void *handle, u64 *flags)
1215 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1217 if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 1, 3) ||
1218 adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 1, 4))
1221 adev->mmhub.funcs->get_clockgating(adev, flags);
1223 if (adev->ip_versions[ATHUB_HWIP][0] >= IP_VERSION(2, 1, 0))
1224 athub_v2_1_get_clockgating(adev, flags);
1226 athub_v2_0_get_clockgating(adev, flags);
1229 static int gmc_v10_0_set_powergating_state(void *handle,
1230 enum amd_powergating_state state)
1235 const struct amd_ip_funcs gmc_v10_0_ip_funcs = {
1236 .name = "gmc_v10_0",
1237 .early_init = gmc_v10_0_early_init,
1238 .late_init = gmc_v10_0_late_init,
1239 .sw_init = gmc_v10_0_sw_init,
1240 .sw_fini = gmc_v10_0_sw_fini,
1241 .hw_init = gmc_v10_0_hw_init,
1242 .hw_fini = gmc_v10_0_hw_fini,
1243 .suspend = gmc_v10_0_suspend,
1244 .resume = gmc_v10_0_resume,
1245 .is_idle = gmc_v10_0_is_idle,
1246 .wait_for_idle = gmc_v10_0_wait_for_idle,
1247 .soft_reset = gmc_v10_0_soft_reset,
1248 .set_clockgating_state = gmc_v10_0_set_clockgating_state,
1249 .set_powergating_state = gmc_v10_0_set_powergating_state,
1250 .get_clockgating_state = gmc_v10_0_get_clockgating_state,
1253 const struct amdgpu_ip_block_version gmc_v10_0_ip_block = {
1254 .type = AMD_IP_BLOCK_TYPE_GMC,
1258 .funcs = &gmc_v10_0_ip_funcs,