2 * Copyright 2019 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
23 #include <linux/firmware.h>
24 #include <linux/pci.h>
26 #include "amdgpu_atomfirmware.h"
27 #include "gmc_v10_0.h"
30 #include "athub/athub_2_0_0_sh_mask.h"
31 #include "athub/athub_2_0_0_offset.h"
32 #include "dcn/dcn_2_0_0_offset.h"
33 #include "dcn/dcn_2_0_0_sh_mask.h"
34 #include "oss/osssys_5_0_0_offset.h"
35 #include "ivsrcid/vmc/irqsrcs_vmc_1_0.h"
36 #include "navi10_enum.h"
40 #include "soc15_common.h"
42 #include "nbio_v2_3.h"
44 #include "gfxhub_v2_0.h"
45 #include "gfxhub_v2_1.h"
46 #include "mmhub_v2_0.h"
47 #include "mmhub_v2_3.h"
48 #include "athub_v2_0.h"
49 #include "athub_v2_1.h"
52 static const struct soc15_reg_golden golden_settings_navi10_hdp[] =
54 /* TODO add golden setting for hdp */
58 static int gmc_v10_0_ecc_interrupt_state(struct amdgpu_device *adev,
59 struct amdgpu_irq_src *src,
61 enum amdgpu_interrupt_state state)
67 gmc_v10_0_vm_fault_interrupt_state(struct amdgpu_device *adev,
68 struct amdgpu_irq_src *src, unsigned type,
69 enum amdgpu_interrupt_state state)
72 case AMDGPU_IRQ_STATE_DISABLE:
74 amdgpu_gmc_set_vm_fault_masks(adev, AMDGPU_MMHUB_0, false);
76 amdgpu_gmc_set_vm_fault_masks(adev, AMDGPU_GFXHUB_0, false);
78 case AMDGPU_IRQ_STATE_ENABLE:
80 amdgpu_gmc_set_vm_fault_masks(adev, AMDGPU_MMHUB_0, true);
82 amdgpu_gmc_set_vm_fault_masks(adev, AMDGPU_GFXHUB_0, true);
91 static int gmc_v10_0_process_interrupt(struct amdgpu_device *adev,
92 struct amdgpu_irq_src *source,
93 struct amdgpu_iv_entry *entry)
95 bool retry_fault = !!(entry->src_data[1] & 0x80);
96 struct amdgpu_vmhub *hub = &adev->vmhub[entry->vmid_src];
97 struct amdgpu_task_info task_info;
101 addr = (u64)entry->src_data[0] << 12;
102 addr |= ((u64)entry->src_data[1] & 0xf) << 44;
105 /* Returning 1 here also prevents sending the IV to the KFD */
107 /* Process it onyl if it's the first fault for this address */
108 if (entry->ih != &adev->irq.ih_soft &&
109 amdgpu_gmc_filter_faults(adev, addr, entry->pasid,
113 /* Delegate it to a different ring if the hardware hasn't
116 if (entry->ih == &adev->irq.ih) {
117 amdgpu_irq_delegate(adev, entry, 8);
121 /* Try to handle the recoverable page faults by filling page
124 if (amdgpu_vm_handle_fault(adev, entry->pasid, addr))
128 if (!amdgpu_sriov_vf(adev)) {
130 * Issue a dummy read to wait for the status register to
131 * be updated to avoid reading an incorrect value due to
132 * the new fast GRBM interface.
134 if ((entry->vmid_src == AMDGPU_GFXHUB_0) &&
135 (adev->asic_type < CHIP_SIENNA_CICHLID))
136 RREG32(hub->vm_l2_pro_fault_status);
138 status = RREG32(hub->vm_l2_pro_fault_status);
139 WREG32_P(hub->vm_l2_pro_fault_cntl, 1, ~1);
142 if (!printk_ratelimit())
145 memset(&task_info, 0, sizeof(struct amdgpu_task_info));
146 amdgpu_vm_get_task_info(adev, entry->pasid, &task_info);
149 "[%s] page fault (src_id:%u ring:%u vmid:%u pasid:%u, "
150 "for process %s pid %d thread %s pid %d)\n",
151 entry->vmid_src ? "mmhub" : "gfxhub",
152 entry->src_id, entry->ring_id, entry->vmid,
153 entry->pasid, task_info.process_name, task_info.tgid,
154 task_info.task_name, task_info.pid);
155 dev_err(adev->dev, " in page starting at address 0x%016llx from client 0x%x (%s)\n",
156 addr, entry->client_id,
157 soc15_ih_clientid_name[entry->client_id]);
159 if (!amdgpu_sriov_vf(adev))
160 hub->vmhub_funcs->print_l2_protection_fault_status(adev,
166 static const struct amdgpu_irq_src_funcs gmc_v10_0_irq_funcs = {
167 .set = gmc_v10_0_vm_fault_interrupt_state,
168 .process = gmc_v10_0_process_interrupt,
171 static const struct amdgpu_irq_src_funcs gmc_v10_0_ecc_funcs = {
172 .set = gmc_v10_0_ecc_interrupt_state,
173 .process = amdgpu_umc_process_ecc_irq,
176 static void gmc_v10_0_set_irq_funcs(struct amdgpu_device *adev)
178 adev->gmc.vm_fault.num_types = 1;
179 adev->gmc.vm_fault.funcs = &gmc_v10_0_irq_funcs;
181 if (!amdgpu_sriov_vf(adev)) {
182 adev->gmc.ecc_irq.num_types = 1;
183 adev->gmc.ecc_irq.funcs = &gmc_v10_0_ecc_funcs;
188 * gmc_v10_0_use_invalidate_semaphore - judge whether to use semaphore
190 * @adev: amdgpu_device pointer
194 static bool gmc_v10_0_use_invalidate_semaphore(struct amdgpu_device *adev,
197 return ((vmhub == AMDGPU_MMHUB_0 ||
198 vmhub == AMDGPU_MMHUB_1) &&
199 (!amdgpu_sriov_vf(adev)));
202 static bool gmc_v10_0_get_atc_vmid_pasid_mapping_info(
203 struct amdgpu_device *adev,
204 uint8_t vmid, uint16_t *p_pasid)
208 value = RREG32(SOC15_REG_OFFSET(ATHUB, 0, mmATC_VMID0_PASID_MAPPING)
210 *p_pasid = value & ATC_VMID0_PASID_MAPPING__PASID_MASK;
212 return !!(value & ATC_VMID0_PASID_MAPPING__VALID_MASK);
217 * VMID 0 is the physical GPU addresses as used by the kernel.
218 * VMIDs 1-15 are used for userspace clients and are handled
219 * by the amdgpu vm/hsa code.
222 static void gmc_v10_0_flush_vm_hub(struct amdgpu_device *adev, uint32_t vmid,
223 unsigned int vmhub, uint32_t flush_type)
225 bool use_semaphore = gmc_v10_0_use_invalidate_semaphore(adev, vmhub);
226 struct amdgpu_vmhub *hub = &adev->vmhub[vmhub];
227 u32 inv_req = hub->vmhub_funcs->get_invalidate_req(vmid, flush_type);
229 /* Use register 17 for GART */
230 const unsigned eng = 17;
232 unsigned char hub_ip = 0;
234 hub_ip = (vmhub == AMDGPU_GFXHUB_0) ?
235 GC_HWIP : MMHUB_HWIP;
237 spin_lock(&adev->gmc.invalidate_lock);
239 * It may lose gpuvm invalidate acknowldege state across power-gating
240 * off cycle, add semaphore acquire before invalidation and semaphore
241 * release after invalidation to avoid entering power gated state
245 /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */
247 for (i = 0; i < adev->usec_timeout; i++) {
248 /* a read return value of 1 means semaphore acuqire */
249 tmp = RREG32_RLC_NO_KIQ(hub->vm_inv_eng0_sem +
250 hub->eng_distance * eng, hub_ip);
257 if (i >= adev->usec_timeout)
258 DRM_ERROR("Timeout waiting for sem acquire in VM flush!\n");
261 WREG32_RLC_NO_KIQ(hub->vm_inv_eng0_req +
262 hub->eng_distance * eng,
266 * Issue a dummy read to wait for the ACK register to be cleared
267 * to avoid a false ACK due to the new fast GRBM interface.
269 if ((vmhub == AMDGPU_GFXHUB_0) &&
270 (adev->asic_type < CHIP_SIENNA_CICHLID))
271 RREG32_RLC_NO_KIQ(hub->vm_inv_eng0_req +
272 hub->eng_distance * eng, hub_ip);
274 /* Wait for ACK with a delay.*/
275 for (i = 0; i < adev->usec_timeout; i++) {
276 tmp = RREG32_RLC_NO_KIQ(hub->vm_inv_eng0_ack +
277 hub->eng_distance * eng, hub_ip);
286 /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */
289 * add semaphore release after invalidation,
290 * write with 0 means semaphore release
292 WREG32_RLC_NO_KIQ(hub->vm_inv_eng0_sem +
293 hub->eng_distance * eng, 0, hub_ip);
295 spin_unlock(&adev->gmc.invalidate_lock);
297 if (i < adev->usec_timeout)
300 DRM_ERROR("Timeout waiting for VM flush hub: %d!\n", vmhub);
304 * gmc_v10_0_flush_gpu_tlb - gart tlb flush callback
306 * @adev: amdgpu_device pointer
307 * @vmid: vm instance to flush
309 * @flush_type: the flush type
311 * Flush the TLB for the requested page table.
313 static void gmc_v10_0_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid,
314 uint32_t vmhub, uint32_t flush_type)
316 struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring;
317 struct dma_fence *fence;
318 struct amdgpu_job *job;
322 /* flush hdp cache */
323 adev->hdp.funcs->flush_hdp(adev, NULL);
325 /* For SRIOV run time, driver shouldn't access the register through MMIO
326 * Directly use kiq to do the vm invalidation instead
328 if (adev->gfx.kiq.ring.sched.ready &&
329 (amdgpu_sriov_runtime(adev) || !amdgpu_sriov_vf(adev)) &&
330 down_read_trylock(&adev->reset_sem)) {
331 struct amdgpu_vmhub *hub = &adev->vmhub[vmhub];
332 const unsigned eng = 17;
333 u32 inv_req = hub->vmhub_funcs->get_invalidate_req(vmid, flush_type);
334 u32 req = hub->vm_inv_eng0_req + hub->eng_distance * eng;
335 u32 ack = hub->vm_inv_eng0_ack + hub->eng_distance * eng;
337 amdgpu_virt_kiq_reg_write_reg_wait(adev, req, ack, inv_req,
340 up_read(&adev->reset_sem);
344 mutex_lock(&adev->mman.gtt_window_lock);
346 if (vmhub == AMDGPU_MMHUB_0) {
347 gmc_v10_0_flush_vm_hub(adev, vmid, AMDGPU_MMHUB_0, 0);
348 mutex_unlock(&adev->mman.gtt_window_lock);
352 BUG_ON(vmhub != AMDGPU_GFXHUB_0);
354 if (!adev->mman.buffer_funcs_enabled ||
355 !adev->ib_pool_ready ||
356 amdgpu_in_reset(adev) ||
357 ring->sched.ready == false) {
358 gmc_v10_0_flush_vm_hub(adev, vmid, AMDGPU_GFXHUB_0, 0);
359 mutex_unlock(&adev->mman.gtt_window_lock);
363 /* The SDMA on Navi has a bug which can theoretically result in memory
364 * corruption if an invalidation happens at the same time as an VA
365 * translation. Avoid this by doing the invalidation from the SDMA
368 r = amdgpu_job_alloc_with_ib(adev, 16 * 4, AMDGPU_IB_POOL_IMMEDIATE,
373 job->vm_pd_addr = amdgpu_gmc_pd_addr(adev->gart.bo);
374 job->vm_needs_flush = true;
375 job->ibs->ptr[job->ibs->length_dw++] = ring->funcs->nop;
376 amdgpu_ring_pad_ib(ring, &job->ibs[0]);
377 r = amdgpu_job_submit(job, &adev->mman.entity,
378 AMDGPU_FENCE_OWNER_UNDEFINED, &fence);
382 mutex_unlock(&adev->mman.gtt_window_lock);
384 dma_fence_wait(fence, false);
385 dma_fence_put(fence);
390 amdgpu_job_free(job);
393 mutex_unlock(&adev->mman.gtt_window_lock);
394 DRM_ERROR("Error flushing GPU TLB using the SDMA (%d)!\n", r);
398 * gmc_v10_0_flush_gpu_tlb_pasid - tlb flush via pasid
400 * @adev: amdgpu_device pointer
401 * @pasid: pasid to be flush
402 * @flush_type: the flush type
403 * @all_hub: Used with PACKET3_INVALIDATE_TLBS_ALL_HUB()
405 * Flush the TLB for the requested pasid.
407 static int gmc_v10_0_flush_gpu_tlb_pasid(struct amdgpu_device *adev,
408 uint16_t pasid, uint32_t flush_type,
414 uint16_t queried_pasid;
416 struct amdgpu_ring *ring = &adev->gfx.kiq.ring;
417 struct amdgpu_kiq *kiq = &adev->gfx.kiq;
419 if (amdgpu_emu_mode == 0 && ring->sched.ready) {
420 spin_lock(&adev->gfx.kiq.ring_lock);
421 /* 2 dwords flush + 8 dwords fence */
422 amdgpu_ring_alloc(ring, kiq->pmf->invalidate_tlbs_size + 8);
423 kiq->pmf->kiq_invalidate_tlbs(ring,
424 pasid, flush_type, all_hub);
425 r = amdgpu_fence_emit_polling(ring, &seq, MAX_KIQ_REG_WAIT);
427 amdgpu_ring_undo(ring);
428 spin_unlock(&adev->gfx.kiq.ring_lock);
432 amdgpu_ring_commit(ring);
433 spin_unlock(&adev->gfx.kiq.ring_lock);
434 r = amdgpu_fence_wait_polling(ring, seq, adev->usec_timeout);
436 dev_err(adev->dev, "wait for kiq fence error: %ld.\n", r);
443 for (vmid = 1; vmid < AMDGPU_NUM_VMID; vmid++) {
445 ret = gmc_v10_0_get_atc_vmid_pasid_mapping_info(adev, vmid,
447 if (ret && queried_pasid == pasid) {
449 for (i = 0; i < adev->num_vmhubs; i++)
450 gmc_v10_0_flush_gpu_tlb(adev, vmid,
453 gmc_v10_0_flush_gpu_tlb(adev, vmid,
454 AMDGPU_GFXHUB_0, flush_type);
463 static uint64_t gmc_v10_0_emit_flush_gpu_tlb(struct amdgpu_ring *ring,
464 unsigned vmid, uint64_t pd_addr)
466 bool use_semaphore = gmc_v10_0_use_invalidate_semaphore(ring->adev, ring->funcs->vmhub);
467 struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub];
468 uint32_t req = hub->vmhub_funcs->get_invalidate_req(vmid, 0);
469 unsigned eng = ring->vm_inv_eng;
472 * It may lose gpuvm invalidate acknowldege state across power-gating
473 * off cycle, add semaphore acquire before invalidation and semaphore
474 * release after invalidation to avoid entering power gated state
478 /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */
480 /* a read return value of 1 means semaphore acuqire */
481 amdgpu_ring_emit_reg_wait(ring,
482 hub->vm_inv_eng0_sem +
483 hub->eng_distance * eng, 0x1, 0x1);
485 amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_lo32 +
486 (hub->ctx_addr_distance * vmid),
487 lower_32_bits(pd_addr));
489 amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_hi32 +
490 (hub->ctx_addr_distance * vmid),
491 upper_32_bits(pd_addr));
493 amdgpu_ring_emit_reg_write_reg_wait(ring, hub->vm_inv_eng0_req +
494 hub->eng_distance * eng,
495 hub->vm_inv_eng0_ack +
496 hub->eng_distance * eng,
499 /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */
502 * add semaphore release after invalidation,
503 * write with 0 means semaphore release
505 amdgpu_ring_emit_wreg(ring, hub->vm_inv_eng0_sem +
506 hub->eng_distance * eng, 0);
511 static void gmc_v10_0_emit_pasid_mapping(struct amdgpu_ring *ring, unsigned vmid,
514 struct amdgpu_device *adev = ring->adev;
517 if (ring->funcs->vmhub == AMDGPU_GFXHUB_0)
518 reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT) + vmid;
520 reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT_MM) + vmid;
522 amdgpu_ring_emit_wreg(ring, reg, pasid);
526 * PTE format on NAVI 10:
528 * 58 reserved and for sienna_cichlid is used for MALL noalloc
536 * 47:12 4k physical page base address
546 * PDE format on NAVI 10:
547 * 63:59 block fragment size
551 * 47:6 physical base address of PD or PTE
558 static uint64_t gmc_v10_0_map_mtype(struct amdgpu_device *adev, uint32_t flags)
561 case AMDGPU_VM_MTYPE_DEFAULT:
562 return AMDGPU_PTE_MTYPE_NV10(MTYPE_NC);
563 case AMDGPU_VM_MTYPE_NC:
564 return AMDGPU_PTE_MTYPE_NV10(MTYPE_NC);
565 case AMDGPU_VM_MTYPE_WC:
566 return AMDGPU_PTE_MTYPE_NV10(MTYPE_WC);
567 case AMDGPU_VM_MTYPE_CC:
568 return AMDGPU_PTE_MTYPE_NV10(MTYPE_CC);
569 case AMDGPU_VM_MTYPE_UC:
570 return AMDGPU_PTE_MTYPE_NV10(MTYPE_UC);
572 return AMDGPU_PTE_MTYPE_NV10(MTYPE_NC);
576 static void gmc_v10_0_get_vm_pde(struct amdgpu_device *adev, int level,
577 uint64_t *addr, uint64_t *flags)
579 if (!(*flags & AMDGPU_PDE_PTE) && !(*flags & AMDGPU_PTE_SYSTEM))
580 *addr = amdgpu_gmc_vram_mc2pa(adev, *addr);
581 BUG_ON(*addr & 0xFFFF00000000003FULL);
583 if (!adev->gmc.translate_further)
586 if (level == AMDGPU_VM_PDB1) {
587 /* Set the block fragment size */
588 if (!(*flags & AMDGPU_PDE_PTE))
589 *flags |= AMDGPU_PDE_BFS(0x9);
591 } else if (level == AMDGPU_VM_PDB0) {
592 if (*flags & AMDGPU_PDE_PTE)
593 *flags &= ~AMDGPU_PDE_PTE;
595 *flags |= AMDGPU_PTE_TF;
599 static void gmc_v10_0_get_vm_pte(struct amdgpu_device *adev,
600 struct amdgpu_bo_va_mapping *mapping,
603 *flags &= ~AMDGPU_PTE_EXECUTABLE;
604 *flags |= mapping->flags & AMDGPU_PTE_EXECUTABLE;
606 *flags &= ~AMDGPU_PTE_MTYPE_NV10_MASK;
607 *flags |= (mapping->flags & AMDGPU_PTE_MTYPE_NV10_MASK);
609 if (mapping->flags & AMDGPU_PTE_PRT) {
610 *flags |= AMDGPU_PTE_PRT;
611 *flags |= AMDGPU_PTE_SNOOPED;
612 *flags |= AMDGPU_PTE_LOG;
613 *flags |= AMDGPU_PTE_SYSTEM;
614 *flags &= ~AMDGPU_PTE_VALID;
618 static unsigned gmc_v10_0_get_vbios_fb_size(struct amdgpu_device *adev)
620 u32 d1vga_control = RREG32_SOC15(DCE, 0, mmD1VGA_CONTROL);
623 if (REG_GET_FIELD(d1vga_control, D1VGA_CONTROL, D1VGA_MODE_ENABLE)) {
624 size = AMDGPU_VBIOS_VGA_ALLOCATION;
629 viewport = RREG32_SOC15(DCE, 0, mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION);
630 pitch = RREG32_SOC15(DCE, 0, mmHUBPREQ0_DCSURF_SURFACE_PITCH);
631 size = (REG_GET_FIELD(viewport,
632 HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION, PRI_VIEWPORT_HEIGHT) *
633 REG_GET_FIELD(pitch, HUBPREQ0_DCSURF_SURFACE_PITCH, PITCH) *
640 static const struct amdgpu_gmc_funcs gmc_v10_0_gmc_funcs = {
641 .flush_gpu_tlb = gmc_v10_0_flush_gpu_tlb,
642 .flush_gpu_tlb_pasid = gmc_v10_0_flush_gpu_tlb_pasid,
643 .emit_flush_gpu_tlb = gmc_v10_0_emit_flush_gpu_tlb,
644 .emit_pasid_mapping = gmc_v10_0_emit_pasid_mapping,
645 .map_mtype = gmc_v10_0_map_mtype,
646 .get_vm_pde = gmc_v10_0_get_vm_pde,
647 .get_vm_pte = gmc_v10_0_get_vm_pte,
648 .get_vbios_fb_size = gmc_v10_0_get_vbios_fb_size,
651 static void gmc_v10_0_set_gmc_funcs(struct amdgpu_device *adev)
653 if (adev->gmc.gmc_funcs == NULL)
654 adev->gmc.gmc_funcs = &gmc_v10_0_gmc_funcs;
657 static void gmc_v10_0_set_umc_funcs(struct amdgpu_device *adev)
659 switch (adev->asic_type) {
660 case CHIP_SIENNA_CICHLID:
661 adev->umc.max_ras_err_cnt_per_query = UMC_V8_7_TOTAL_CHANNEL_NUM;
662 adev->umc.channel_inst_num = UMC_V8_7_CHANNEL_INSTANCE_NUM;
663 adev->umc.umc_inst_num = UMC_V8_7_UMC_INSTANCE_NUM;
664 adev->umc.channel_offs = UMC_V8_7_PER_CHANNEL_OFFSET_SIENNA;
665 adev->umc.channel_idx_tbl = &umc_v8_7_channel_idx_tbl[0][0];
666 adev->umc.ras_funcs = &umc_v8_7_ras_funcs;
674 static void gmc_v10_0_set_mmhub_funcs(struct amdgpu_device *adev)
676 switch (adev->asic_type) {
678 case CHIP_YELLOW_CARP:
679 adev->mmhub.funcs = &mmhub_v2_3_funcs;
682 adev->mmhub.funcs = &mmhub_v2_0_funcs;
687 static void gmc_v10_0_set_gfxhub_funcs(struct amdgpu_device *adev)
689 switch (adev->asic_type) {
690 case CHIP_SIENNA_CICHLID:
691 case CHIP_NAVY_FLOUNDER:
693 case CHIP_DIMGREY_CAVEFISH:
694 case CHIP_BEIGE_GOBY:
695 case CHIP_YELLOW_CARP:
696 adev->gfxhub.funcs = &gfxhub_v2_1_funcs;
699 adev->gfxhub.funcs = &gfxhub_v2_0_funcs;
705 static int gmc_v10_0_early_init(void *handle)
707 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
709 gmc_v10_0_set_mmhub_funcs(adev);
710 gmc_v10_0_set_gfxhub_funcs(adev);
711 gmc_v10_0_set_gmc_funcs(adev);
712 gmc_v10_0_set_irq_funcs(adev);
713 gmc_v10_0_set_umc_funcs(adev);
715 adev->gmc.shared_aperture_start = 0x2000000000000000ULL;
716 adev->gmc.shared_aperture_end =
717 adev->gmc.shared_aperture_start + (4ULL << 30) - 1;
718 adev->gmc.private_aperture_start = 0x1000000000000000ULL;
719 adev->gmc.private_aperture_end =
720 adev->gmc.private_aperture_start + (4ULL << 30) - 1;
725 static int gmc_v10_0_late_init(void *handle)
727 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
730 r = amdgpu_gmc_allocate_vm_inv_eng(adev);
734 r = amdgpu_gmc_ras_late_init(adev);
738 return amdgpu_irq_get(adev, &adev->gmc.vm_fault, 0);
741 static void gmc_v10_0_vram_gtt_location(struct amdgpu_device *adev,
742 struct amdgpu_gmc *mc)
746 base = adev->gfxhub.funcs->get_fb_location(adev);
748 /* add the xgmi offset of the physical node */
749 base += adev->gmc.xgmi.physical_node_id * adev->gmc.xgmi.node_segment_size;
751 amdgpu_gmc_vram_location(adev, &adev->gmc, base);
752 amdgpu_gmc_gart_location(adev, mc);
753 amdgpu_gmc_agp_location(adev, mc);
755 /* base offset of vram pages */
756 adev->vm_manager.vram_base_offset = adev->gfxhub.funcs->get_mc_fb_offset(adev);
758 /* add the xgmi offset of the physical node */
759 adev->vm_manager.vram_base_offset +=
760 adev->gmc.xgmi.physical_node_id * adev->gmc.xgmi.node_segment_size;
764 * gmc_v10_0_mc_init - initialize the memory controller driver params
766 * @adev: amdgpu_device pointer
768 * Look up the amount of vram, vram width, and decide how to place
769 * vram and gart within the GPU's physical address space.
770 * Returns 0 for success.
772 static int gmc_v10_0_mc_init(struct amdgpu_device *adev)
776 /* size in MB on si */
777 adev->gmc.mc_vram_size =
778 adev->nbio.funcs->get_memsize(adev) * 1024ULL * 1024ULL;
779 adev->gmc.real_vram_size = adev->gmc.mc_vram_size;
781 if (!(adev->flags & AMD_IS_APU)) {
782 r = amdgpu_device_resize_fb_bar(adev);
786 adev->gmc.aper_base = pci_resource_start(adev->pdev, 0);
787 adev->gmc.aper_size = pci_resource_len(adev->pdev, 0);
790 if (adev->flags & AMD_IS_APU) {
791 adev->gmc.aper_base = adev->gfxhub.funcs->get_mc_fb_offset(adev);
792 adev->gmc.aper_size = adev->gmc.real_vram_size;
796 /* In case the PCI BAR is larger than the actual amount of vram */
797 adev->gmc.visible_vram_size = adev->gmc.aper_size;
798 if (adev->gmc.visible_vram_size > adev->gmc.real_vram_size)
799 adev->gmc.visible_vram_size = adev->gmc.real_vram_size;
801 /* set the gart size */
802 if (amdgpu_gart_size == -1) {
803 switch (adev->asic_type) {
807 case CHIP_SIENNA_CICHLID:
808 case CHIP_NAVY_FLOUNDER:
810 case CHIP_DIMGREY_CAVEFISH:
811 case CHIP_BEIGE_GOBY:
812 case CHIP_YELLOW_CARP:
814 adev->gmc.gart_size = 512ULL << 20;
818 adev->gmc.gart_size = (u64)amdgpu_gart_size << 20;
820 gmc_v10_0_vram_gtt_location(adev, &adev->gmc);
825 static int gmc_v10_0_gart_init(struct amdgpu_device *adev)
830 WARN(1, "NAVI10 PCIE GART already initialized\n");
834 /* Initialize common gart structure */
835 r = amdgpu_gart_init(adev);
839 adev->gart.table_size = adev->gart.num_gpu_pages * 8;
840 adev->gart.gart_pte_flags = AMDGPU_PTE_MTYPE_NV10(MTYPE_UC) |
841 AMDGPU_PTE_EXECUTABLE;
843 return amdgpu_gart_table_vram_alloc(adev);
846 static int gmc_v10_0_sw_init(void *handle)
848 int r, vram_width = 0, vram_type = 0, vram_vendor = 0;
849 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
851 adev->gfxhub.funcs->init(adev);
853 adev->mmhub.funcs->init(adev);
855 spin_lock_init(&adev->gmc.invalidate_lock);
857 if ((adev->flags & AMD_IS_APU) && amdgpu_emu_mode == 1) {
858 adev->gmc.vram_type = AMDGPU_VRAM_TYPE_DDR4;
859 adev->gmc.vram_width = 64;
860 } else if (amdgpu_emu_mode == 1) {
861 adev->gmc.vram_type = AMDGPU_VRAM_TYPE_GDDR6;
862 adev->gmc.vram_width = 1 * 128; /* numchan * chansize */
864 r = amdgpu_atomfirmware_get_vram_info(adev,
865 &vram_width, &vram_type, &vram_vendor);
866 adev->gmc.vram_width = vram_width;
868 adev->gmc.vram_type = vram_type;
869 adev->gmc.vram_vendor = vram_vendor;
872 switch (adev->asic_type) {
876 case CHIP_SIENNA_CICHLID:
877 case CHIP_NAVY_FLOUNDER:
879 case CHIP_DIMGREY_CAVEFISH:
880 case CHIP_BEIGE_GOBY:
881 case CHIP_YELLOW_CARP:
882 adev->num_vmhubs = 2;
884 * To fulfill 4-level page support,
885 * vm size is 256TB (48bit), maximum size of Navi10/Navi14/Navi12,
886 * block size 512 (9bit)
888 amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 48);
894 /* This interrupt is VMC page fault.*/
895 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VMC,
896 VMC_1_0__SRCID__VM_FAULT,
897 &adev->gmc.vm_fault);
902 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_UTCL2,
903 UTCL2_1_0__SRCID__FAULT,
904 &adev->gmc.vm_fault);
908 if (!amdgpu_sriov_vf(adev)) {
909 /* interrupt sent to DF. */
910 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DF, 0,
917 * Set the internal MC address mask This is the max address of the GPU's
918 * internal address space.
920 adev->gmc.mc_mask = 0xffffffffffffULL; /* 48 bit MC */
922 r = dma_set_mask_and_coherent(adev->dev, DMA_BIT_MASK(44));
924 printk(KERN_WARNING "amdgpu: No suitable DMA available.\n");
928 if (adev->gmc.xgmi.supported) {
929 r = adev->gfxhub.funcs->get_xgmi_info(adev);
934 r = gmc_v10_0_mc_init(adev);
938 amdgpu_gmc_get_vbios_allocations(adev);
939 amdgpu_gmc_get_reserved_allocation(adev);
942 r = amdgpu_bo_init(adev);
946 r = gmc_v10_0_gart_init(adev);
952 * VMID 0 is reserved for System
953 * amdgpu graphics/compute will use VMIDs 1-7
954 * amdkfd will use VMIDs 8-15
956 adev->vm_manager.first_kfd_vmid = 8;
958 amdgpu_vm_manager_init(adev);
964 * gmc_v10_0_gart_fini - vm fini callback
966 * @adev: amdgpu_device pointer
968 * Tears down the driver GART/VM setup (CIK).
970 static void gmc_v10_0_gart_fini(struct amdgpu_device *adev)
972 amdgpu_gart_table_vram_free(adev);
975 static int gmc_v10_0_sw_fini(void *handle)
977 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
979 amdgpu_vm_manager_fini(adev);
980 gmc_v10_0_gart_fini(adev);
981 amdgpu_gem_force_release(adev);
982 amdgpu_bo_fini(adev);
987 static void gmc_v10_0_init_golden_registers(struct amdgpu_device *adev)
989 switch (adev->asic_type) {
993 case CHIP_SIENNA_CICHLID:
994 case CHIP_NAVY_FLOUNDER:
996 case CHIP_DIMGREY_CAVEFISH:
997 case CHIP_BEIGE_GOBY:
998 case CHIP_YELLOW_CARP:
1006 * gmc_v10_0_gart_enable - gart enable
1008 * @adev: amdgpu_device pointer
1010 static int gmc_v10_0_gart_enable(struct amdgpu_device *adev)
1015 if (adev->gart.bo == NULL) {
1016 dev_err(adev->dev, "No VRAM object for PCIE GART.\n");
1020 r = amdgpu_gart_table_vram_pin(adev);
1024 r = adev->gfxhub.funcs->gart_enable(adev);
1028 r = adev->mmhub.funcs->gart_enable(adev);
1032 adev->hdp.funcs->init_registers(adev);
1034 /* Flush HDP after it is initialized */
1035 adev->hdp.funcs->flush_hdp(adev, NULL);
1037 value = (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS) ?
1040 adev->gfxhub.funcs->set_fault_enable_default(adev, value);
1041 adev->mmhub.funcs->set_fault_enable_default(adev, value);
1042 gmc_v10_0_flush_gpu_tlb(adev, 0, AMDGPU_MMHUB_0, 0);
1043 gmc_v10_0_flush_gpu_tlb(adev, 0, AMDGPU_GFXHUB_0, 0);
1045 DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
1046 (unsigned)(adev->gmc.gart_size >> 20),
1047 (unsigned long long)amdgpu_bo_gpu_offset(adev->gart.bo));
1049 adev->gart.ready = true;
1054 static int gmc_v10_0_hw_init(void *handle)
1057 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1059 /* The sequence of these two function calls matters.*/
1060 gmc_v10_0_init_golden_registers(adev);
1063 * harvestable groups in gc_utcl2 need to be programmed before any GFX block
1064 * register setup within GMC, or else system hang when harvesting SA.
1066 if (adev->gfxhub.funcs && adev->gfxhub.funcs->utcl2_harvest)
1067 adev->gfxhub.funcs->utcl2_harvest(adev);
1069 r = gmc_v10_0_gart_enable(adev);
1073 if (adev->umc.funcs && adev->umc.funcs->init_registers)
1074 adev->umc.funcs->init_registers(adev);
1080 * gmc_v10_0_gart_disable - gart disable
1082 * @adev: amdgpu_device pointer
1084 * This disables all VM page table.
1086 static void gmc_v10_0_gart_disable(struct amdgpu_device *adev)
1088 adev->gfxhub.funcs->gart_disable(adev);
1089 adev->mmhub.funcs->gart_disable(adev);
1090 amdgpu_gart_table_vram_unpin(adev);
1093 static int gmc_v10_0_hw_fini(void *handle)
1095 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1097 if (amdgpu_sriov_vf(adev)) {
1098 /* full access mode, so don't touch any GMC register */
1099 DRM_DEBUG("For SRIOV client, shouldn't do anything.\n");
1103 amdgpu_irq_put(adev, &adev->gmc.ecc_irq, 0);
1104 amdgpu_irq_put(adev, &adev->gmc.vm_fault, 0);
1105 gmc_v10_0_gart_disable(adev);
1110 static int gmc_v10_0_suspend(void *handle)
1112 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1114 gmc_v10_0_hw_fini(adev);
1119 static int gmc_v10_0_resume(void *handle)
1122 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1124 r = gmc_v10_0_hw_init(adev);
1128 amdgpu_vmid_reset_all(adev);
1133 static bool gmc_v10_0_is_idle(void *handle)
1135 /* MC is always ready in GMC v10.*/
1139 static int gmc_v10_0_wait_for_idle(void *handle)
1141 /* There is no need to wait for MC idle in GMC v10.*/
1145 static int gmc_v10_0_soft_reset(void *handle)
1150 static int gmc_v10_0_set_clockgating_state(void *handle,
1151 enum amd_clockgating_state state)
1154 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1156 r = adev->mmhub.funcs->set_clockgating(adev, state);
1160 if (adev->asic_type >= CHIP_SIENNA_CICHLID &&
1161 adev->asic_type <= CHIP_YELLOW_CARP)
1162 return athub_v2_1_set_clockgating(adev, state);
1164 return athub_v2_0_set_clockgating(adev, state);
1167 static void gmc_v10_0_get_clockgating_state(void *handle, u32 *flags)
1169 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1171 adev->mmhub.funcs->get_clockgating(adev, flags);
1173 if (adev->asic_type >= CHIP_SIENNA_CICHLID &&
1174 adev->asic_type <= CHIP_YELLOW_CARP)
1175 athub_v2_1_get_clockgating(adev, flags);
1177 athub_v2_0_get_clockgating(adev, flags);
1180 static int gmc_v10_0_set_powergating_state(void *handle,
1181 enum amd_powergating_state state)
1186 const struct amd_ip_funcs gmc_v10_0_ip_funcs = {
1187 .name = "gmc_v10_0",
1188 .early_init = gmc_v10_0_early_init,
1189 .late_init = gmc_v10_0_late_init,
1190 .sw_init = gmc_v10_0_sw_init,
1191 .sw_fini = gmc_v10_0_sw_fini,
1192 .hw_init = gmc_v10_0_hw_init,
1193 .hw_fini = gmc_v10_0_hw_fini,
1194 .suspend = gmc_v10_0_suspend,
1195 .resume = gmc_v10_0_resume,
1196 .is_idle = gmc_v10_0_is_idle,
1197 .wait_for_idle = gmc_v10_0_wait_for_idle,
1198 .soft_reset = gmc_v10_0_soft_reset,
1199 .set_clockgating_state = gmc_v10_0_set_clockgating_state,
1200 .set_powergating_state = gmc_v10_0_set_powergating_state,
1201 .get_clockgating_state = gmc_v10_0_get_clockgating_state,
1204 const struct amdgpu_ip_block_version gmc_v10_0_ip_block =
1206 .type = AMD_IP_BLOCK_TYPE_GMC,
1210 .funcs = &gmc_v10_0_ip_funcs,