2 * Copyright 2019 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
25 #include "gfxhub_v2_1.h"
27 #include "gc/gc_10_3_0_offset.h"
28 #include "gc/gc_10_3_0_sh_mask.h"
29 #include "gc/gc_10_3_0_default.h"
30 #include "navi10_enum.h"
32 #include "soc15_common.h"
34 u64 gfxhub_v2_1_get_fb_location(struct amdgpu_device *adev)
36 u64 base = RREG32_SOC15(GC, 0, mmGCMC_VM_FB_LOCATION_BASE);
38 base &= GCMC_VM_FB_LOCATION_BASE__FB_BASE_MASK;
44 u64 gfxhub_v2_1_get_mc_fb_offset(struct amdgpu_device *adev)
46 return (u64)RREG32_SOC15(GC, 0, mmGCMC_VM_FB_OFFSET) << 24;
49 void gfxhub_v2_1_setup_vm_pt_regs(struct amdgpu_device *adev, uint32_t vmid,
50 uint64_t page_table_base)
52 struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB_0];
54 WREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32,
55 hub->ctx_addr_distance * vmid,
56 lower_32_bits(page_table_base));
58 WREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32,
59 hub->ctx_addr_distance * vmid,
60 upper_32_bits(page_table_base));
63 static void gfxhub_v2_1_init_gart_aperture_regs(struct amdgpu_device *adev)
65 uint64_t pt_base = amdgpu_gmc_pd_addr(adev->gart.bo);
67 gfxhub_v2_1_setup_vm_pt_regs(adev, 0, pt_base);
69 WREG32_SOC15(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32,
70 (u32)(adev->gmc.gart_start >> 12));
71 WREG32_SOC15(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32,
72 (u32)(adev->gmc.gart_start >> 44));
74 WREG32_SOC15(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32,
75 (u32)(adev->gmc.gart_end >> 12));
76 WREG32_SOC15(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32,
77 (u32)(adev->gmc.gart_end >> 44));
80 static void gfxhub_v2_1_init_system_aperture_regs(struct amdgpu_device *adev)
85 WREG32_SOC15(GC, 0, mmGCMC_VM_AGP_BASE, 0);
86 WREG32_SOC15(GC, 0, mmGCMC_VM_AGP_TOP, 0);
87 WREG32_SOC15(GC, 0, mmGCMC_VM_AGP_BOT, 0x00FFFFFF);
89 /* Program the system aperture low logical page number. */
90 WREG32_SOC15(GC, 0, mmGCMC_VM_SYSTEM_APERTURE_LOW_ADDR,
91 adev->gmc.vram_start >> 18);
92 WREG32_SOC15(GC, 0, mmGCMC_VM_SYSTEM_APERTURE_HIGH_ADDR,
93 adev->gmc.vram_end >> 18);
95 /* Set default page address. */
96 value = adev->vram_scratch.gpu_addr - adev->gmc.vram_start
97 + adev->vm_manager.vram_base_offset;
98 WREG32_SOC15(GC, 0, mmGCMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB,
100 WREG32_SOC15(GC, 0, mmGCMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB,
103 /* Program "protection fault". */
104 WREG32_SOC15(GC, 0, mmGCVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32,
105 (u32)(adev->dummy_page_addr >> 12));
106 WREG32_SOC15(GC, 0, mmGCVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32,
107 (u32)((u64)adev->dummy_page_addr >> 44));
109 WREG32_FIELD15(GC, 0, GCVM_L2_PROTECTION_FAULT_CNTL2,
110 ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY, 1);
114 static void gfxhub_v2_1_init_tlb_regs(struct amdgpu_device *adev)
118 /* Setup TLB control */
119 tmp = RREG32_SOC15(GC, 0, mmGCMC_VM_MX_L1_TLB_CNTL);
121 tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1);
122 tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3);
123 tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL,
124 ENABLE_ADVANCED_DRIVER_MODEL, 1);
125 tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL,
126 SYSTEM_APERTURE_UNMAPPED_ACCESS, 0);
127 tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, ECO_BITS, 0);
128 tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL,
129 MTYPE, MTYPE_UC); /* UC, uncached */
131 WREG32_SOC15(GC, 0, mmGCMC_VM_MX_L1_TLB_CNTL, tmp);
134 static void gfxhub_v2_1_init_cache_regs(struct amdgpu_device *adev)
139 tmp = RREG32_SOC15(GC, 0, mmGCVM_L2_CNTL);
140 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, ENABLE_L2_CACHE, 1);
141 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 0);
142 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL,
143 ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY, 1);
144 /* XXX for emulation, Refer to closed source code.*/
145 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL,
146 L2_PDE0_CACHE_TAG_GENERATION_MODE, 0);
147 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, PDE_FAULT_CLASSIFICATION, 0);
148 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1);
149 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, IDENTITY_MODE_FRAGMENT_SIZE, 0);
150 WREG32_SOC15(GC, 0, mmGCVM_L2_CNTL, tmp);
152 tmp = RREG32_SOC15(GC, 0, mmGCVM_L2_CNTL2);
153 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1);
154 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL2, INVALIDATE_L2_CACHE, 1);
155 WREG32_SOC15(GC, 0, mmGCVM_L2_CNTL2, tmp);
157 tmp = mmGCVM_L2_CNTL3_DEFAULT;
158 if (adev->gmc.translate_further) {
159 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL3, BANK_SELECT, 12);
160 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL3,
161 L2_CACHE_BIGK_FRAGMENT_SIZE, 9);
163 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL3, BANK_SELECT, 9);
164 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL3,
165 L2_CACHE_BIGK_FRAGMENT_SIZE, 6);
167 WREG32_SOC15(GC, 0, mmGCVM_L2_CNTL3, tmp);
169 tmp = mmGCVM_L2_CNTL4_DEFAULT;
170 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL4, VMC_TAP_PDE_REQUEST_PHYSICAL, 0);
171 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL4, VMC_TAP_PTE_REQUEST_PHYSICAL, 0);
172 WREG32_SOC15(GC, 0, mmGCVM_L2_CNTL4, tmp);
174 tmp = mmGCVM_L2_CNTL5_DEFAULT;
175 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL5, L2_CACHE_SMALLK_FRAGMENT_SIZE, 0);
176 WREG32_SOC15(GC, 0, mmGCVM_L2_CNTL5, tmp);
179 static void gfxhub_v2_1_enable_system_domain(struct amdgpu_device *adev)
183 tmp = RREG32_SOC15(GC, 0, mmGCVM_CONTEXT0_CNTL);
184 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1);
185 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0);
186 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT0_CNTL,
187 RETRY_PERMISSION_OR_INVALID_PAGE_FAULT, 0);
188 WREG32_SOC15(GC, 0, mmGCVM_CONTEXT0_CNTL, tmp);
191 static void gfxhub_v2_1_disable_identity_aperture(struct amdgpu_device *adev)
193 WREG32_SOC15(GC, 0, mmGCVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32,
195 WREG32_SOC15(GC, 0, mmGCVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32,
198 WREG32_SOC15(GC, 0, mmGCVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32,
200 WREG32_SOC15(GC, 0, mmGCVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32,
203 WREG32_SOC15(GC, 0, mmGCVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32, 0);
204 WREG32_SOC15(GC, 0, mmGCVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32, 0);
208 static void gfxhub_v2_1_setup_vmid_config(struct amdgpu_device *adev)
210 struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB_0];
214 for (i = 0; i <= 14; i++) {
215 tmp = RREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT1_CNTL, i);
216 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1);
217 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH,
218 adev->vm_manager.num_level);
219 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,
220 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
221 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,
222 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
223 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,
224 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
225 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,
226 VALID_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
227 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,
228 READ_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
229 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,
230 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
231 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,
232 EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
233 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,
234 PAGE_TABLE_BLOCK_SIZE,
235 adev->vm_manager.block_size - 9);
236 /* Send no-retry XNACK on fault to suppress VM fault storm. */
237 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,
238 RETRY_PERMISSION_OR_INVALID_PAGE_FAULT,
240 WREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT1_CNTL,
241 i * hub->ctx_distance, tmp);
242 WREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32,
243 i * hub->ctx_addr_distance, 0);
244 WREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32,
245 i * hub->ctx_addr_distance, 0);
246 WREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32,
247 i * hub->ctx_addr_distance,
248 lower_32_bits(adev->vm_manager.max_pfn - 1));
249 WREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32,
250 i * hub->ctx_addr_distance,
251 upper_32_bits(adev->vm_manager.max_pfn - 1));
255 static void gfxhub_v2_1_program_invalidation(struct amdgpu_device *adev)
257 struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB_0];
260 for (i = 0 ; i < 18; ++i) {
261 WREG32_SOC15_OFFSET(GC, 0, mmGCVM_INVALIDATE_ENG0_ADDR_RANGE_LO32,
262 i * hub->eng_addr_distance, 0xffffffff);
263 WREG32_SOC15_OFFSET(GC, 0, mmGCVM_INVALIDATE_ENG0_ADDR_RANGE_HI32,
264 i * hub->eng_addr_distance, 0x1f);
268 int gfxhub_v2_1_gart_enable(struct amdgpu_device *adev)
270 if (amdgpu_sriov_vf(adev)) {
272 * GCMC_VM_FB_LOCATION_BASE/TOP is NULL for VF, becuase they are
273 * VF copy registers so vbios post doesn't program them, for
274 * SRIOV driver need to program them
276 WREG32_SOC15(GC, 0, mmGCMC_VM_FB_LOCATION_BASE,
277 adev->gmc.vram_start >> 24);
278 WREG32_SOC15(GC, 0, mmGCMC_VM_FB_LOCATION_TOP,
279 adev->gmc.vram_end >> 24);
283 gfxhub_v2_1_init_gart_aperture_regs(adev);
284 gfxhub_v2_1_init_system_aperture_regs(adev);
285 gfxhub_v2_1_init_tlb_regs(adev);
286 gfxhub_v2_1_init_cache_regs(adev);
288 gfxhub_v2_1_enable_system_domain(adev);
289 gfxhub_v2_1_disable_identity_aperture(adev);
290 gfxhub_v2_1_setup_vmid_config(adev);
291 gfxhub_v2_1_program_invalidation(adev);
296 void gfxhub_v2_1_gart_disable(struct amdgpu_device *adev)
298 struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB_0];
302 /* Disable all tables */
303 for (i = 0; i < 16; i++)
304 WREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT0_CNTL,
305 i * hub->ctx_distance, 0);
307 /* Setup TLB control */
308 tmp = RREG32_SOC15(GC, 0, mmGCMC_VM_MX_L1_TLB_CNTL);
309 tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0);
310 tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL,
311 ENABLE_ADVANCED_DRIVER_MODEL, 0);
312 WREG32_SOC15(GC, 0, mmGCMC_VM_MX_L1_TLB_CNTL, tmp);
315 WREG32_FIELD15(GC, 0, GCVM_L2_CNTL, ENABLE_L2_CACHE, 0);
316 WREG32_SOC15(GC, 0, mmGCVM_L2_CNTL3, 0);
320 * gfxhub_v2_1_set_fault_enable_default - update GART/VM fault handling
322 * @adev: amdgpu_device pointer
323 * @value: true redirects VM faults to the default page
325 void gfxhub_v2_1_set_fault_enable_default(struct amdgpu_device *adev,
329 tmp = RREG32_SOC15(GC, 0, mmGCVM_L2_PROTECTION_FAULT_CNTL);
330 tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,
331 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
332 tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,
333 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, value);
334 tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,
335 PDE1_PROTECTION_FAULT_ENABLE_DEFAULT, value);
336 tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,
337 PDE2_PROTECTION_FAULT_ENABLE_DEFAULT, value);
338 tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,
339 TRANSLATE_FURTHER_PROTECTION_FAULT_ENABLE_DEFAULT,
341 tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,
342 NACK_PROTECTION_FAULT_ENABLE_DEFAULT, value);
343 tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,
344 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
345 tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,
346 VALID_PROTECTION_FAULT_ENABLE_DEFAULT, value);
347 tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,
348 READ_PROTECTION_FAULT_ENABLE_DEFAULT, value);
349 tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,
350 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
351 tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,
352 EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
354 tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,
355 CRASH_ON_NO_RETRY_FAULT, 1);
356 tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,
357 CRASH_ON_RETRY_FAULT, 1);
359 WREG32_SOC15(GC, 0, mmGCVM_L2_PROTECTION_FAULT_CNTL, tmp);
362 void gfxhub_v2_1_init(struct amdgpu_device *adev)
364 struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB_0];
366 hub->ctx0_ptb_addr_lo32 =
367 SOC15_REG_OFFSET(GC, 0,
368 mmGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32);
369 hub->ctx0_ptb_addr_hi32 =
370 SOC15_REG_OFFSET(GC, 0,
371 mmGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32);
372 hub->vm_inv_eng0_sem =
373 SOC15_REG_OFFSET(GC, 0, mmGCVM_INVALIDATE_ENG0_SEM);
374 hub->vm_inv_eng0_req =
375 SOC15_REG_OFFSET(GC, 0, mmGCVM_INVALIDATE_ENG0_REQ);
376 hub->vm_inv_eng0_ack =
377 SOC15_REG_OFFSET(GC, 0, mmGCVM_INVALIDATE_ENG0_ACK);
378 hub->vm_context0_cntl =
379 SOC15_REG_OFFSET(GC, 0, mmGCVM_CONTEXT0_CNTL);
380 hub->vm_l2_pro_fault_status =
381 SOC15_REG_OFFSET(GC, 0, mmGCVM_L2_PROTECTION_FAULT_STATUS);
382 hub->vm_l2_pro_fault_cntl =
383 SOC15_REG_OFFSET(GC, 0, mmGCVM_L2_PROTECTION_FAULT_CNTL);
385 hub->ctx_distance = mmGCVM_CONTEXT1_CNTL - mmGCVM_CONTEXT0_CNTL;
386 hub->ctx_addr_distance = mmGCVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32 -
387 mmGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32;
388 hub->eng_distance = mmGCVM_INVALIDATE_ENG1_REQ -
389 mmGCVM_INVALIDATE_ENG0_REQ;
390 hub->eng_addr_distance = mmGCVM_INVALIDATE_ENG1_ADDR_RANGE_LO32 -
391 mmGCVM_INVALIDATE_ENG0_ADDR_RANGE_LO32;
394 int gfxhub_v2_1_get_xgmi_info(struct amdgpu_device *adev)
396 u32 xgmi_lfb_cntl = RREG32_SOC15(GC, 0, mmGCMC_VM_XGMI_LFB_CNTL);
398 REG_GET_FIELD(xgmi_lfb_cntl, GCMC_VM_XGMI_LFB_CNTL, PF_MAX_REGION);
399 u32 max_num_physical_nodes = 0;
400 u32 max_physical_node_id = 0;
402 switch (adev->asic_type) {
403 case CHIP_SIENNA_CICHLID:
404 max_num_physical_nodes = 4;
405 max_physical_node_id = 3;
411 /* PF_MAX_REGION=0 means xgmi is disabled */
413 adev->gmc.xgmi.num_physical_nodes = max_region + 1;
414 if (adev->gmc.xgmi.num_physical_nodes > max_num_physical_nodes)
417 adev->gmc.xgmi.physical_node_id =
418 REG_GET_FIELD(xgmi_lfb_cntl, GCMC_VM_XGMI_LFB_CNTL, PF_LFB_REGION);
419 if (adev->gmc.xgmi.physical_node_id > max_physical_node_id)
422 adev->gmc.xgmi.node_segment_size = REG_GET_FIELD(
423 RREG32_SOC15(GC, 0, mmGCMC_VM_XGMI_LFB_SIZE),
424 GCMC_VM_XGMI_LFB_SIZE, PF_LFB_SIZE) << 24;