drivers/gpu/drm/amd/amdgpu/gfxhub_v2_1.c

   1 /*
   2  * Copyright 2019 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #include "amdgpu.h"
  25 #include "gfxhub_v2_1.h"
  26
  27 #include "gc/gc_10_3_0_offset.h"
  28 #include "gc/gc_10_3_0_sh_mask.h"
  29 #include "gc/gc_10_3_0_default.h"
  30 #include "navi10_enum.h"
  31
  32 #include "soc15_common.h"
  33
  34 u64 gfxhub_v2_1_get_fb_location(struct amdgpu_device *adev)
  35 {
  36         u64 base = RREG32_SOC15(GC, 0, mmGCMC_VM_FB_LOCATION_BASE);
  37
  38         base &= GCMC_VM_FB_LOCATION_BASE__FB_BASE_MASK;
  39         base <<= 24;
  40
  41         return base;
  42 }
  43
  44 u64 gfxhub_v2_1_get_mc_fb_offset(struct amdgpu_device *adev)
  45 {
  46         return (u64)RREG32_SOC15(GC, 0, mmGCMC_VM_FB_OFFSET) << 24;
  47 }
  48
  49 void gfxhub_v2_1_setup_vm_pt_regs(struct amdgpu_device *adev, uint32_t vmid,
  50                                 uint64_t page_table_base)
  51 {
  52         struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB_0];
  53
  54         WREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32,
  55                             hub->ctx_addr_distance * vmid,
  56                             lower_32_bits(page_table_base));
  57
  58         WREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32,
  59                             hub->ctx_addr_distance * vmid,
  60                             upper_32_bits(page_table_base));
  61 }
  62
  63 static void gfxhub_v2_1_init_gart_aperture_regs(struct amdgpu_device *adev)
  64 {
  65         uint64_t pt_base = amdgpu_gmc_pd_addr(adev->gart.bo);
  66
  67         gfxhub_v2_1_setup_vm_pt_regs(adev, 0, pt_base);
  68
  69         WREG32_SOC15(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32,
  70                      (u32)(adev->gmc.gart_start >> 12));
  71         WREG32_SOC15(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32,
  72                      (u32)(adev->gmc.gart_start >> 44));
  73
  74         WREG32_SOC15(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32,
  75                      (u32)(adev->gmc.gart_end >> 12));
  76         WREG32_SOC15(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32,
  77                      (u32)(adev->gmc.gart_end >> 44));
  78 }
  79
  80 static void gfxhub_v2_1_init_system_aperture_regs(struct amdgpu_device *adev)
  81 {
  82         uint64_t value;
  83
  84         /* Disable AGP. */
  85         WREG32_SOC15(GC, 0, mmGCMC_VM_AGP_BASE, 0);
  86         WREG32_SOC15(GC, 0, mmGCMC_VM_AGP_TOP, 0);
  87         WREG32_SOC15(GC, 0, mmGCMC_VM_AGP_BOT, 0x00FFFFFF);
  88
  89         /* Program the system aperture low logical page number. */
  90         WREG32_SOC15(GC, 0, mmGCMC_VM_SYSTEM_APERTURE_LOW_ADDR,
  91                      adev->gmc.vram_start >> 18);
  92         WREG32_SOC15(GC, 0, mmGCMC_VM_SYSTEM_APERTURE_HIGH_ADDR,
  93                      adev->gmc.vram_end >> 18);
  94
  95         /* Set default page address. */
  96         value = adev->vram_scratch.gpu_addr - adev->gmc.vram_start
  97                 + adev->vm_manager.vram_base_offset;
  98         WREG32_SOC15(GC, 0, mmGCMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB,
  99                      (u32)(value >> 12));
 100         WREG32_SOC15(GC, 0, mmGCMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB,
 101                      (u32)(value >> 44));
 102
 103         /* Program "protection fault". */
 104         WREG32_SOC15(GC, 0, mmGCVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32,
 105                      (u32)(adev->dummy_page_addr >> 12));
 106         WREG32_SOC15(GC, 0, mmGCVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32,
 107                      (u32)((u64)adev->dummy_page_addr >> 44));
 108
 109         WREG32_FIELD15(GC, 0, GCVM_L2_PROTECTION_FAULT_CNTL2,
 110                        ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY, 1);
 111 }
 112
 113
 114 static void gfxhub_v2_1_init_tlb_regs(struct amdgpu_device *adev)
 115 {
 116         uint32_t tmp;
 117
 118         /* Setup TLB control */
 119         tmp = RREG32_SOC15(GC, 0, mmGCMC_VM_MX_L1_TLB_CNTL);
 120
 121         tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1);
 122         tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3);
 123         tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL,
 124                             ENABLE_ADVANCED_DRIVER_MODEL, 1);
 125         tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL,
 126                             SYSTEM_APERTURE_UNMAPPED_ACCESS, 0);
 127         tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, ECO_BITS, 0);
 128         tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL,
 129                             MTYPE, MTYPE_UC); /* UC, uncached */
 130
 131         WREG32_SOC15(GC, 0, mmGCMC_VM_MX_L1_TLB_CNTL, tmp);
 132 }
 133
 134 static void gfxhub_v2_1_init_cache_regs(struct amdgpu_device *adev)
 135 {
 136         uint32_t tmp;
 137
 138         /* These registers are not accessible to VF-SRIOV.
 139          * The PF will program them instead.
 140          */
 141         if (amdgpu_sriov_vf(adev))
 142                 return;
 143
 144         /* Setup L2 cache */
 145         tmp = RREG32_SOC15(GC, 0, mmGCVM_L2_CNTL);
 146         tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, ENABLE_L2_CACHE, 1);
 147         tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 0);
 148         tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL,
 149                             ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY, 1);
 150         /* XXX for emulation, Refer to closed source code.*/
 151         tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL,
 152                             L2_PDE0_CACHE_TAG_GENERATION_MODE, 0);
 153         tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, PDE_FAULT_CLASSIFICATION, 0);
 154         tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1);
 155         tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, IDENTITY_MODE_FRAGMENT_SIZE, 0);
 156         WREG32_SOC15(GC, 0, mmGCVM_L2_CNTL, tmp);
 157
 158         tmp = RREG32_SOC15(GC, 0, mmGCVM_L2_CNTL2);
 159         tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1);
 160         tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL2, INVALIDATE_L2_CACHE, 1);
 161         WREG32_SOC15(GC, 0, mmGCVM_L2_CNTL2, tmp);
 162
 163         tmp = mmGCVM_L2_CNTL3_DEFAULT;
 164         if (adev->gmc.translate_further) {
 165                 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL3, BANK_SELECT, 12);
 166                 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL3,
 167                                     L2_CACHE_BIGK_FRAGMENT_SIZE, 9);
 168         } else {
 169                 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL3, BANK_SELECT, 9);
 170                 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL3,
 171                                     L2_CACHE_BIGK_FRAGMENT_SIZE, 6);
 172         }
 173         WREG32_SOC15(GC, 0, mmGCVM_L2_CNTL3, tmp);
 174
 175         tmp = mmGCVM_L2_CNTL4_DEFAULT;
 176         tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL4, VMC_TAP_PDE_REQUEST_PHYSICAL, 0);
 177         tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL4, VMC_TAP_PTE_REQUEST_PHYSICAL, 0);
 178         WREG32_SOC15(GC, 0, mmGCVM_L2_CNTL4, tmp);
 179
 180         tmp = mmGCVM_L2_CNTL5_DEFAULT;
 181         tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL5, L2_CACHE_SMALLK_FRAGMENT_SIZE, 0);
 182         WREG32_SOC15(GC, 0, mmGCVM_L2_CNTL5, tmp);
 183 }
 184
 185 static void gfxhub_v2_1_enable_system_domain(struct amdgpu_device *adev)
 186 {
 187         uint32_t tmp;
 188
 189         tmp = RREG32_SOC15(GC, 0, mmGCVM_CONTEXT0_CNTL);
 190         tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1);
 191         tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0);
 192         tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT0_CNTL,
 193                             RETRY_PERMISSION_OR_INVALID_PAGE_FAULT, 0);
 194         WREG32_SOC15(GC, 0, mmGCVM_CONTEXT0_CNTL, tmp);
 195 }
 196
 197 static void gfxhub_v2_1_disable_identity_aperture(struct amdgpu_device *adev)
 198 {
 199         /* These registers are not accessible to VF-SRIOV.
 200          * The PF will program them instead.
 201          */
 202         if (amdgpu_sriov_vf(adev))
 203                 return;
 204
 205         WREG32_SOC15(GC, 0, mmGCVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32,
 206                      0xFFFFFFFF);
 207         WREG32_SOC15(GC, 0, mmGCVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32,
 208                      0x0000000F);
 209
 210         WREG32_SOC15(GC, 0, mmGCVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32,
 211                      0);
 212         WREG32_SOC15(GC, 0, mmGCVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32,
 213                      0);
 214
 215         WREG32_SOC15(GC, 0, mmGCVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32, 0);
 216         WREG32_SOC15(GC, 0, mmGCVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32, 0);
 217
 218 }
 219
 220 static void gfxhub_v2_1_setup_vmid_config(struct amdgpu_device *adev)
 221 {
 222         struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB_0];
 223         int i;
 224         uint32_t tmp;
 225
 226         for (i = 0; i <= 14; i++) {
 227                 tmp = RREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT1_CNTL, i);
 228                 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1);
 229                 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH,
 230                                     adev->vm_manager.num_level);
 231                 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,
 232                                 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 233                 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,
 234                                 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 235                 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,
 236                                 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 237                 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,
 238                                 VALID_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 239                 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,
 240                                 READ_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 241                 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,
 242                                 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 243                 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,
 244                                 EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 245                 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,
 246                                 PAGE_TABLE_BLOCK_SIZE,
 247                                 adev->vm_manager.block_size - 9);
 248                 /* Send no-retry XNACK on fault to suppress VM fault storm. */
 249                 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,
 250                                     RETRY_PERMISSION_OR_INVALID_PAGE_FAULT,
 251                                     !amdgpu_noretry);
 252                 WREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT1_CNTL,
 253                                     i * hub->ctx_distance, tmp);
 254                 WREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32,
 255                                     i * hub->ctx_addr_distance, 0);
 256                 WREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32,
 257                                     i * hub->ctx_addr_distance, 0);
 258                 WREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32,
 259                                     i * hub->ctx_addr_distance,
 260                                     lower_32_bits(adev->vm_manager.max_pfn - 1));
 261                 WREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32,
 262                                     i * hub->ctx_addr_distance,
 263                                     upper_32_bits(adev->vm_manager.max_pfn - 1));
 264         }
 265 }
 266
 267 static void gfxhub_v2_1_program_invalidation(struct amdgpu_device *adev)
 268 {
 269         struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB_0];
 270         unsigned i;
 271
 272         for (i = 0 ; i < 18; ++i) {
 273                 WREG32_SOC15_OFFSET(GC, 0, mmGCVM_INVALIDATE_ENG0_ADDR_RANGE_LO32,
 274                                     i * hub->eng_addr_distance, 0xffffffff);
 275                 WREG32_SOC15_OFFSET(GC, 0, mmGCVM_INVALIDATE_ENG0_ADDR_RANGE_HI32,
 276                                     i * hub->eng_addr_distance, 0x1f);
 277         }
 278 }
 279
 280 int gfxhub_v2_1_gart_enable(struct amdgpu_device *adev)
 281 {
 282         if (amdgpu_sriov_vf(adev)) {
 283                 /*
 284                  * GCMC_VM_FB_LOCATION_BASE/TOP is NULL for VF, becuase they are
 285                  * VF copy registers so vbios post doesn't program them, for
 286                  * SRIOV driver need to program them
 287                  */
 288                 WREG32_SOC15(GC, 0, mmGCMC_VM_FB_LOCATION_BASE,
 289                              adev->gmc.vram_start >> 24);
 290                 WREG32_SOC15(GC, 0, mmGCMC_VM_FB_LOCATION_TOP,
 291                              adev->gmc.vram_end >> 24);
 292         }
 293
 294         /* GART Enable. */
 295         gfxhub_v2_1_init_gart_aperture_regs(adev);
 296         gfxhub_v2_1_init_system_aperture_regs(adev);
 297         gfxhub_v2_1_init_tlb_regs(adev);
 298         gfxhub_v2_1_init_cache_regs(adev);
 299
 300         gfxhub_v2_1_enable_system_domain(adev);
 301         gfxhub_v2_1_disable_identity_aperture(adev);
 302         gfxhub_v2_1_setup_vmid_config(adev);
 303         gfxhub_v2_1_program_invalidation(adev);
 304
 305         return 0;
 306 }
 307
 308 void gfxhub_v2_1_gart_disable(struct amdgpu_device *adev)
 309 {
 310         struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB_0];
 311         u32 tmp;
 312         u32 i;
 313
 314         /* Disable all tables */
 315         for (i = 0; i < 16; i++)
 316                 WREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT0_CNTL,
 317                                     i * hub->ctx_distance, 0);
 318
 319         /* Setup TLB control */
 320         tmp = RREG32_SOC15(GC, 0, mmGCMC_VM_MX_L1_TLB_CNTL);
 321         tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0);
 322         tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL,
 323                             ENABLE_ADVANCED_DRIVER_MODEL, 0);
 324         WREG32_SOC15(GC, 0, mmGCMC_VM_MX_L1_TLB_CNTL, tmp);
 325
 326         /* Setup L2 cache */
 327         WREG32_FIELD15(GC, 0, GCVM_L2_CNTL, ENABLE_L2_CACHE, 0);
 328         WREG32_SOC15(GC, 0, mmGCVM_L2_CNTL3, 0);
 329 }
 330
 331 /**
 332  * gfxhub_v2_1_set_fault_enable_default - update GART/VM fault handling
 333  *
 334  * @adev: amdgpu_device pointer
 335  * @value: true redirects VM faults to the default page
 336  */
 337 void gfxhub_v2_1_set_fault_enable_default(struct amdgpu_device *adev,
 338                                           bool value)
 339 {
 340         u32 tmp;
 341
 342         /* These registers are not accessible to VF-SRIOV.
 343          * The PF will program them instead.
 344          */
 345         if (amdgpu_sriov_vf(adev))
 346                 return;
 347
 348         tmp = RREG32_SOC15(GC, 0, mmGCVM_L2_PROTECTION_FAULT_CNTL);
 349         tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,
 350                             RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 351         tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,
 352                             PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 353         tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,
 354                             PDE1_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 355         tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,
 356                             PDE2_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 357         tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,
 358                             TRANSLATE_FURTHER_PROTECTION_FAULT_ENABLE_DEFAULT,
 359                             value);
 360         tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,
 361                             NACK_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 362         tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,
 363                             DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 364         tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,
 365                             VALID_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 366         tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,
 367                             READ_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 368         tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,
 369                             WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 370         tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,
 371                             EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 372         if (!value) {
 373                 tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,
 374                                 CRASH_ON_NO_RETRY_FAULT, 1);
 375                 tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,
 376                                 CRASH_ON_RETRY_FAULT, 1);
 377         }
 378         WREG32_SOC15(GC, 0, mmGCVM_L2_PROTECTION_FAULT_CNTL, tmp);
 379 }
 380
 381 void gfxhub_v2_1_init(struct amdgpu_device *adev)
 382 {
 383         struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB_0];
 384
 385         hub->ctx0_ptb_addr_lo32 =
 386                 SOC15_REG_OFFSET(GC, 0,
 387                                  mmGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32);
 388         hub->ctx0_ptb_addr_hi32 =
 389                 SOC15_REG_OFFSET(GC, 0,
 390                                  mmGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32);
 391         hub->vm_inv_eng0_sem =
 392                 SOC15_REG_OFFSET(GC, 0, mmGCVM_INVALIDATE_ENG0_SEM);
 393         hub->vm_inv_eng0_req =
 394                 SOC15_REG_OFFSET(GC, 0, mmGCVM_INVALIDATE_ENG0_REQ);
 395         hub->vm_inv_eng0_ack =
 396                 SOC15_REG_OFFSET(GC, 0, mmGCVM_INVALIDATE_ENG0_ACK);
 397         hub->vm_context0_cntl =
 398                 SOC15_REG_OFFSET(GC, 0, mmGCVM_CONTEXT0_CNTL);
 399         hub->vm_l2_pro_fault_status =
 400                 SOC15_REG_OFFSET(GC, 0, mmGCVM_L2_PROTECTION_FAULT_STATUS);
 401         hub->vm_l2_pro_fault_cntl =
 402                 SOC15_REG_OFFSET(GC, 0, mmGCVM_L2_PROTECTION_FAULT_CNTL);
 403
 404         hub->ctx_distance = mmGCVM_CONTEXT1_CNTL - mmGCVM_CONTEXT0_CNTL;
 405         hub->ctx_addr_distance = mmGCVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32 -
 406                 mmGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32;
 407         hub->eng_distance = mmGCVM_INVALIDATE_ENG1_REQ -
 408                 mmGCVM_INVALIDATE_ENG0_REQ;
 409         hub->eng_addr_distance = mmGCVM_INVALIDATE_ENG1_ADDR_RANGE_LO32 -
 410                 mmGCVM_INVALIDATE_ENG0_ADDR_RANGE_LO32;
 411 }
 412
 413 int gfxhub_v2_1_get_xgmi_info(struct amdgpu_device *adev)
 414 {
 415         u32 xgmi_lfb_cntl = RREG32_SOC15(GC, 0, mmGCMC_VM_XGMI_LFB_CNTL);
 416         u32 max_region =
 417                 REG_GET_FIELD(xgmi_lfb_cntl, GCMC_VM_XGMI_LFB_CNTL, PF_MAX_REGION);
 418         u32 max_num_physical_nodes   = 0;
 419         u32 max_physical_node_id     = 0;
 420
 421         switch (adev->asic_type) {
 422         case CHIP_SIENNA_CICHLID:
 423                 max_num_physical_nodes   = 4;
 424                 max_physical_node_id     = 3;
 425                 break;
 426         default:
 427                 return -EINVAL;
 428         }
 429
 430         /* PF_MAX_REGION=0 means xgmi is disabled */
 431         if (max_region) {
 432                 adev->gmc.xgmi.num_physical_nodes = max_region + 1;
 433                 if (adev->gmc.xgmi.num_physical_nodes > max_num_physical_nodes)
 434                         return -EINVAL;
 435
 436                 adev->gmc.xgmi.physical_node_id =
 437                         REG_GET_FIELD(xgmi_lfb_cntl, GCMC_VM_XGMI_LFB_CNTL, PF_LFB_REGION);
 438                 if (adev->gmc.xgmi.physical_node_id > max_physical_node_id)
 439                         return -EINVAL;
 440
 441                 adev->gmc.xgmi.node_segment_size = REG_GET_FIELD(
 442                         RREG32_SOC15(GC, 0, mmGCMC_VM_XGMI_LFB_SIZE),
 443                         GCMC_VM_XGMI_LFB_SIZE, PF_LFB_SIZE) << 24;
 444         }
 445
 446         return 0;
 447 }