2 * Copyright 2016 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
24 #include "gfxhub_v1_0.h"
25 #include "gfxhub_v1_1.h"
27 #include "gc/gc_9_0_offset.h"
28 #include "gc/gc_9_0_sh_mask.h"
29 #include "gc/gc_9_0_default.h"
30 #include "vega10_enum.h"
32 #include "soc15_common.h"
34 static u64 gfxhub_v1_0_get_mc_fb_offset(struct amdgpu_device *adev)
36 return (u64)RREG32_SOC15(GC, 0, mmMC_VM_FB_OFFSET) << 24;
39 static void gfxhub_v1_0_setup_vm_pt_regs(struct amdgpu_device *adev,
41 uint64_t page_table_base)
43 struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB_0];
45 WREG32_SOC15_OFFSET(GC, 0, mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32,
46 hub->ctx_addr_distance * vmid,
47 lower_32_bits(page_table_base));
49 WREG32_SOC15_OFFSET(GC, 0, mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32,
50 hub->ctx_addr_distance * vmid,
51 upper_32_bits(page_table_base));
54 static void gfxhub_v1_0_init_gart_aperture_regs(struct amdgpu_device *adev)
56 uint64_t pt_base = amdgpu_gmc_pd_addr(adev->gart.bo);
58 gfxhub_v1_0_setup_vm_pt_regs(adev, 0, pt_base);
60 WREG32_SOC15(GC, 0, mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32,
61 (u32)(adev->gmc.gart_start >> 12));
62 WREG32_SOC15(GC, 0, mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32,
63 (u32)(adev->gmc.gart_start >> 44));
65 WREG32_SOC15(GC, 0, mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32,
66 (u32)(adev->gmc.gart_end >> 12));
67 WREG32_SOC15(GC, 0, mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32,
68 (u32)(adev->gmc.gart_end >> 44));
71 static void gfxhub_v1_0_init_system_aperture_regs(struct amdgpu_device *adev)
75 /* Program the AGP BAR */
76 WREG32_SOC15_RLC(GC, 0, mmMC_VM_AGP_BASE, 0);
77 WREG32_SOC15_RLC(GC, 0, mmMC_VM_AGP_BOT, adev->gmc.agp_start >> 24);
78 WREG32_SOC15_RLC(GC, 0, mmMC_VM_AGP_TOP, adev->gmc.agp_end >> 24);
80 if (!amdgpu_sriov_vf(adev) || adev->asic_type <= CHIP_VEGA10) {
81 /* Program the system aperture low logical page number. */
82 WREG32_SOC15_RLC(GC, 0, mmMC_VM_SYSTEM_APERTURE_LOW_ADDR,
83 min(adev->gmc.fb_start, adev->gmc.agp_start) >> 18);
85 if (adev->apu_flags & AMD_APU_IS_RAVEN2)
87 * Raven2 has a HW issue that it is unable to use the
88 * vram which is out of MC_VM_SYSTEM_APERTURE_HIGH_ADDR.
89 * So here is the workaround that increase system
90 * aperture high address (add 1) to get rid of the VM
91 * fault and hardware hang.
93 WREG32_SOC15_RLC(GC, 0,
94 mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR,
95 max((adev->gmc.fb_end >> 18) + 0x1,
96 adev->gmc.agp_end >> 18));
99 GC, 0, mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR,
100 max(adev->gmc.fb_end, adev->gmc.agp_end) >> 18);
102 /* Set default page address. */
103 value = adev->vram_scratch.gpu_addr - adev->gmc.vram_start +
104 adev->vm_manager.vram_base_offset;
105 WREG32_SOC15(GC, 0, mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB,
107 WREG32_SOC15(GC, 0, mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB,
110 /* Program "protection fault". */
111 WREG32_SOC15(GC, 0, mmVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32,
112 (u32)(adev->dummy_page_addr >> 12));
113 WREG32_SOC15(GC, 0, mmVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32,
114 (u32)((u64)adev->dummy_page_addr >> 44));
116 WREG32_FIELD15(GC, 0, VM_L2_PROTECTION_FAULT_CNTL2,
117 ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY, 1);
121 static void gfxhub_v1_0_init_tlb_regs(struct amdgpu_device *adev)
125 /* Setup TLB control */
126 tmp = RREG32_SOC15(GC, 0, mmMC_VM_MX_L1_TLB_CNTL);
128 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1);
129 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3);
130 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL,
131 ENABLE_ADVANCED_DRIVER_MODEL, 1);
132 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL,
133 SYSTEM_APERTURE_UNMAPPED_ACCESS, 0);
134 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ECO_BITS, 0);
135 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL,
136 MTYPE, MTYPE_UC);/* XXX for emulation. */
137 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ATC_EN, 1);
139 WREG32_SOC15_RLC(GC, 0, mmMC_VM_MX_L1_TLB_CNTL, tmp);
142 static void gfxhub_v1_0_init_cache_regs(struct amdgpu_device *adev)
147 tmp = RREG32_SOC15(GC, 0, mmVM_L2_CNTL);
148 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 1);
149 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 1);
150 /* XXX for emulation, Refer to closed source code.*/
151 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, L2_PDE0_CACHE_TAG_GENERATION_MODE,
153 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, PDE_FAULT_CLASSIFICATION, 0);
154 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1);
155 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, IDENTITY_MODE_FRAGMENT_SIZE, 0);
156 WREG32_SOC15_RLC(GC, 0, mmVM_L2_CNTL, tmp);
158 tmp = RREG32_SOC15(GC, 0, mmVM_L2_CNTL2);
159 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1);
160 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_L2_CACHE, 1);
161 WREG32_SOC15_RLC(GC, 0, mmVM_L2_CNTL2, tmp);
163 tmp = mmVM_L2_CNTL3_DEFAULT;
164 if (adev->gmc.translate_further) {
165 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, 12);
166 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3,
167 L2_CACHE_BIGK_FRAGMENT_SIZE, 9);
169 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, 9);
170 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3,
171 L2_CACHE_BIGK_FRAGMENT_SIZE, 6);
173 WREG32_SOC15_RLC(GC, 0, mmVM_L2_CNTL3, tmp);
175 tmp = mmVM_L2_CNTL4_DEFAULT;
176 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_PDE_REQUEST_PHYSICAL, 0);
177 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_PTE_REQUEST_PHYSICAL, 0);
178 WREG32_SOC15_RLC(GC, 0, mmVM_L2_CNTL4, tmp);
181 static void gfxhub_v1_0_enable_system_domain(struct amdgpu_device *adev)
185 tmp = RREG32_SOC15(GC, 0, mmVM_CONTEXT0_CNTL);
186 tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1);
187 tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0);
188 tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL,
189 RETRY_PERMISSION_OR_INVALID_PAGE_FAULT, 0);
190 WREG32_SOC15(GC, 0, mmVM_CONTEXT0_CNTL, tmp);
193 static void gfxhub_v1_0_disable_identity_aperture(struct amdgpu_device *adev)
195 WREG32_SOC15(GC, 0, mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32,
197 WREG32_SOC15(GC, 0, mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32,
200 WREG32_SOC15(GC, 0, mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32,
202 WREG32_SOC15(GC, 0, mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32,
205 WREG32_SOC15(GC, 0, mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32, 0);
206 WREG32_SOC15(GC, 0, mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32, 0);
210 static void gfxhub_v1_0_setup_vmid_config(struct amdgpu_device *adev)
212 struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB_0];
213 unsigned num_level, block_size;
217 num_level = adev->vm_manager.num_level;
218 block_size = adev->vm_manager.block_size;
219 if (adev->gmc.translate_further)
224 for (i = 0; i <= 14; i++) {
225 tmp = RREG32_SOC15_OFFSET(GC, 0, mmVM_CONTEXT1_CNTL, i);
226 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1);
227 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH,
229 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
230 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
231 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
232 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT,
234 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
235 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
236 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
237 VALID_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
238 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
239 READ_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
240 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
241 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
242 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
243 EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
244 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
245 PAGE_TABLE_BLOCK_SIZE,
247 /* Send no-retry XNACK on fault to suppress VM fault storm. */
248 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
249 RETRY_PERMISSION_OR_INVALID_PAGE_FAULT,
251 WREG32_SOC15_OFFSET(GC, 0, mmVM_CONTEXT1_CNTL,
252 i * hub->ctx_distance, tmp);
253 WREG32_SOC15_OFFSET(GC, 0, mmVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32,
254 i * hub->ctx_addr_distance, 0);
255 WREG32_SOC15_OFFSET(GC, 0, mmVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32,
256 i * hub->ctx_addr_distance, 0);
257 WREG32_SOC15_OFFSET(GC, 0, mmVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32,
258 i * hub->ctx_addr_distance,
259 lower_32_bits(adev->vm_manager.max_pfn - 1));
260 WREG32_SOC15_OFFSET(GC, 0, mmVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32,
261 i * hub->ctx_addr_distance,
262 upper_32_bits(adev->vm_manager.max_pfn - 1));
266 static void gfxhub_v1_0_program_invalidation(struct amdgpu_device *adev)
268 struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB_0];
271 for (i = 0 ; i < 18; ++i) {
272 WREG32_SOC15_OFFSET(GC, 0, mmVM_INVALIDATE_ENG0_ADDR_RANGE_LO32,
273 i * hub->eng_addr_distance, 0xffffffff);
274 WREG32_SOC15_OFFSET(GC, 0, mmVM_INVALIDATE_ENG0_ADDR_RANGE_HI32,
275 i * hub->eng_addr_distance, 0x1f);
279 static int gfxhub_v1_0_gart_enable(struct amdgpu_device *adev)
281 if (amdgpu_sriov_vf(adev) && adev->asic_type != CHIP_ARCTURUS) {
283 * MC_VM_FB_LOCATION_BASE/TOP is NULL for VF, becuase they are
284 * VF copy registers so vbios post doesn't program them, for
285 * SRIOV driver need to program them
287 WREG32_SOC15_RLC(GC, 0, mmMC_VM_FB_LOCATION_BASE,
288 adev->gmc.vram_start >> 24);
289 WREG32_SOC15_RLC(GC, 0, mmMC_VM_FB_LOCATION_TOP,
290 adev->gmc.vram_end >> 24);
294 gfxhub_v1_0_init_gart_aperture_regs(adev);
295 gfxhub_v1_0_init_system_aperture_regs(adev);
296 gfxhub_v1_0_init_tlb_regs(adev);
297 if (!amdgpu_sriov_vf(adev))
298 gfxhub_v1_0_init_cache_regs(adev);
300 gfxhub_v1_0_enable_system_domain(adev);
301 if (!amdgpu_sriov_vf(adev))
302 gfxhub_v1_0_disable_identity_aperture(adev);
303 gfxhub_v1_0_setup_vmid_config(adev);
304 gfxhub_v1_0_program_invalidation(adev);
309 static void gfxhub_v1_0_gart_disable(struct amdgpu_device *adev)
311 struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB_0];
315 /* Disable all tables */
316 for (i = 0; i < 16; i++)
317 WREG32_SOC15_OFFSET(GC, 0, mmVM_CONTEXT0_CNTL,
318 i * hub->ctx_distance, 0);
320 /* Setup TLB control */
321 tmp = RREG32_SOC15(GC, 0, mmMC_VM_MX_L1_TLB_CNTL);
322 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0);
323 tmp = REG_SET_FIELD(tmp,
324 MC_VM_MX_L1_TLB_CNTL,
325 ENABLE_ADVANCED_DRIVER_MODEL,
327 WREG32_SOC15_RLC(GC, 0, mmMC_VM_MX_L1_TLB_CNTL, tmp);
330 WREG32_FIELD15(GC, 0, VM_L2_CNTL, ENABLE_L2_CACHE, 0);
331 WREG32_SOC15(GC, 0, mmVM_L2_CNTL3, 0);
335 * gfxhub_v1_0_set_fault_enable_default - update GART/VM fault handling
337 * @adev: amdgpu_device pointer
338 * @value: true redirects VM faults to the default page
340 static void gfxhub_v1_0_set_fault_enable_default(struct amdgpu_device *adev,
344 tmp = RREG32_SOC15(GC, 0, mmVM_L2_PROTECTION_FAULT_CNTL);
345 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
346 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
347 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
348 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, value);
349 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
350 PDE1_PROTECTION_FAULT_ENABLE_DEFAULT, value);
351 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
352 PDE2_PROTECTION_FAULT_ENABLE_DEFAULT, value);
353 tmp = REG_SET_FIELD(tmp,
354 VM_L2_PROTECTION_FAULT_CNTL,
355 TRANSLATE_FURTHER_PROTECTION_FAULT_ENABLE_DEFAULT,
357 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
358 NACK_PROTECTION_FAULT_ENABLE_DEFAULT, value);
359 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
360 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
361 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
362 VALID_PROTECTION_FAULT_ENABLE_DEFAULT, value);
363 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
364 READ_PROTECTION_FAULT_ENABLE_DEFAULT, value);
365 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
366 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
367 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
368 EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
370 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
371 CRASH_ON_NO_RETRY_FAULT, 1);
372 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
373 CRASH_ON_RETRY_FAULT, 1);
375 WREG32_SOC15(GC, 0, mmVM_L2_PROTECTION_FAULT_CNTL, tmp);
378 static void gfxhub_v1_0_init(struct amdgpu_device *adev)
380 struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB_0];
382 hub->ctx0_ptb_addr_lo32 =
383 SOC15_REG_OFFSET(GC, 0,
384 mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32);
385 hub->ctx0_ptb_addr_hi32 =
386 SOC15_REG_OFFSET(GC, 0,
387 mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32);
388 hub->vm_inv_eng0_sem =
389 SOC15_REG_OFFSET(GC, 0, mmVM_INVALIDATE_ENG0_SEM);
390 hub->vm_inv_eng0_req =
391 SOC15_REG_OFFSET(GC, 0, mmVM_INVALIDATE_ENG0_REQ);
392 hub->vm_inv_eng0_ack =
393 SOC15_REG_OFFSET(GC, 0, mmVM_INVALIDATE_ENG0_ACK);
394 hub->vm_context0_cntl =
395 SOC15_REG_OFFSET(GC, 0, mmVM_CONTEXT0_CNTL);
396 hub->vm_l2_pro_fault_status =
397 SOC15_REG_OFFSET(GC, 0, mmVM_L2_PROTECTION_FAULT_STATUS);
398 hub->vm_l2_pro_fault_cntl =
399 SOC15_REG_OFFSET(GC, 0, mmVM_L2_PROTECTION_FAULT_CNTL);
401 hub->ctx_distance = mmVM_CONTEXT1_CNTL - mmVM_CONTEXT0_CNTL;
402 hub->ctx_addr_distance = mmVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32 -
403 mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32;
404 hub->eng_distance = mmVM_INVALIDATE_ENG1_REQ - mmVM_INVALIDATE_ENG0_REQ;
405 hub->eng_addr_distance = mmVM_INVALIDATE_ENG1_ADDR_RANGE_LO32 -
406 mmVM_INVALIDATE_ENG0_ADDR_RANGE_LO32;
410 const struct amdgpu_gfxhub_funcs gfxhub_v1_0_funcs = {
411 .get_mc_fb_offset = gfxhub_v1_0_get_mc_fb_offset,
412 .setup_vm_pt_regs = gfxhub_v1_0_setup_vm_pt_regs,
413 .gart_enable = gfxhub_v1_0_gart_enable,
414 .gart_disable = gfxhub_v1_0_gart_disable,
415 .set_fault_enable_default = gfxhub_v1_0_set_fault_enable_default,
416 .init = gfxhub_v1_0_init,
417 .get_xgmi_info = gfxhub_v1_1_get_xgmi_info,