drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c

   1 /*
   2  * Copyright 2016 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23 #include "amdgpu.h"
  24 #include "gfxhub_v1_0.h"
  25
  26 #include "gc/gc_9_0_offset.h"
  27 #include "gc/gc_9_0_sh_mask.h"
  28 #include "gc/gc_9_0_default.h"
  29 #include "vega10_enum.h"
  30
  31 #include "soc15_common.h"
  32
  33 u64 gfxhub_v1_0_get_mc_fb_offset(struct amdgpu_device *adev)
  34 {
  35         return (u64)RREG32_SOC15(GC, 0, mmMC_VM_FB_OFFSET) << 24;
  36 }
  37
  38 void gfxhub_v1_0_setup_vm_pt_regs(struct amdgpu_device *adev, uint32_t vmid,
  39                                 uint64_t page_table_base)
  40 {
  41         struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB_0];
  42
  43         WREG32_SOC15_OFFSET(GC, 0, mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32,
  44                             hub->ctx_addr_distance * vmid,
  45                             lower_32_bits(page_table_base));
  46
  47         WREG32_SOC15_OFFSET(GC, 0, mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32,
  48                             hub->ctx_addr_distance * vmid,
  49                             upper_32_bits(page_table_base));
  50 }
  51
  52 static void gfxhub_v1_0_init_gart_aperture_regs(struct amdgpu_device *adev)
  53 {
  54         uint64_t pt_base = amdgpu_gmc_pd_addr(adev->gart.bo);
  55
  56         gfxhub_v1_0_setup_vm_pt_regs(adev, 0, pt_base);
  57
  58         WREG32_SOC15(GC, 0, mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32,
  59                      (u32)(adev->gmc.gart_start >> 12));
  60         WREG32_SOC15(GC, 0, mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32,
  61                      (u32)(adev->gmc.gart_start >> 44));
  62
  63         WREG32_SOC15(GC, 0, mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32,
  64                      (u32)(adev->gmc.gart_end >> 12));
  65         WREG32_SOC15(GC, 0, mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32,
  66                      (u32)(adev->gmc.gart_end >> 44));
  67 }
  68
  69 static void gfxhub_v1_0_init_system_aperture_regs(struct amdgpu_device *adev)
  70 {
  71         uint64_t value;
  72
  73         /* Program the AGP BAR */
  74         WREG32_SOC15_RLC(GC, 0, mmMC_VM_AGP_BASE, 0);
  75         WREG32_SOC15_RLC(GC, 0, mmMC_VM_AGP_BOT, adev->gmc.agp_start >> 24);
  76         WREG32_SOC15_RLC(GC, 0, mmMC_VM_AGP_TOP, adev->gmc.agp_end >> 24);
  77
  78         if (!amdgpu_sriov_vf(adev) || adev->asic_type <= CHIP_VEGA10) {
  79                 /* Program the system aperture low logical page number. */
  80                 WREG32_SOC15_RLC(GC, 0, mmMC_VM_SYSTEM_APERTURE_LOW_ADDR,
  81                         min(adev->gmc.fb_start, adev->gmc.agp_start) >> 18);
  82
  83                 if (adev->apu_flags & AMD_APU_IS_RAVEN2)
  84                         /*
  85                         * Raven2 has a HW issue that it is unable to use the
  86                         * vram which is out of MC_VM_SYSTEM_APERTURE_HIGH_ADDR.
  87                         * So here is the workaround that increase system
  88                         * aperture high address (add 1) to get rid of the VM
  89                         * fault and hardware hang.
  90                         */
  91                         WREG32_SOC15_RLC(GC, 0,
  92                                          mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR,
  93                                          max((adev->gmc.fb_end >> 18) + 0x1,
  94                                              adev->gmc.agp_end >> 18));
  95                 else
  96                         WREG32_SOC15_RLC(
  97                                 GC, 0, mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR,
  98                                 max(adev->gmc.fb_end, adev->gmc.agp_end) >> 18);
  99
 100                 /* Set default page address. */
 101                 value = adev->vram_scratch.gpu_addr - adev->gmc.vram_start +
 102                         adev->vm_manager.vram_base_offset;
 103                 WREG32_SOC15(GC, 0, mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB,
 104                              (u32)(value >> 12));
 105                 WREG32_SOC15(GC, 0, mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB,
 106                              (u32)(value >> 44));
 107
 108                 /* Program "protection fault". */
 109                 WREG32_SOC15(GC, 0, mmVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32,
 110                              (u32)(adev->dummy_page_addr >> 12));
 111                 WREG32_SOC15(GC, 0, mmVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32,
 112                              (u32)((u64)adev->dummy_page_addr >> 44));
 113
 114                 WREG32_FIELD15(GC, 0, VM_L2_PROTECTION_FAULT_CNTL2,
 115                                ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY, 1);
 116         }
 117 }
 118
 119 static void gfxhub_v1_0_init_tlb_regs(struct amdgpu_device *adev)
 120 {
 121         uint32_t tmp;
 122
 123         /* Setup TLB control */
 124         tmp = RREG32_SOC15(GC, 0, mmMC_VM_MX_L1_TLB_CNTL);
 125
 126         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1);
 127         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3);
 128         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL,
 129                             ENABLE_ADVANCED_DRIVER_MODEL, 1);
 130         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL,
 131                             SYSTEM_APERTURE_UNMAPPED_ACCESS, 0);
 132         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ECO_BITS, 0);
 133         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL,
 134                             MTYPE, MTYPE_UC);/* XXX for emulation. */
 135         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ATC_EN, 1);
 136
 137         WREG32_SOC15_RLC(GC, 0, mmMC_VM_MX_L1_TLB_CNTL, tmp);
 138 }
 139
 140 static void gfxhub_v1_0_init_cache_regs(struct amdgpu_device *adev)
 141 {
 142         uint32_t tmp;
 143
 144         /* Setup L2 cache */
 145         tmp = RREG32_SOC15(GC, 0, mmVM_L2_CNTL);
 146         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 1);
 147         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 1);
 148         /* XXX for emulation, Refer to closed source code.*/
 149         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, L2_PDE0_CACHE_TAG_GENERATION_MODE,
 150                             0);
 151         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, PDE_FAULT_CLASSIFICATION, 0);
 152         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1);
 153         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, IDENTITY_MODE_FRAGMENT_SIZE, 0);
 154         WREG32_SOC15_RLC(GC, 0, mmVM_L2_CNTL, tmp);
 155
 156         tmp = RREG32_SOC15(GC, 0, mmVM_L2_CNTL2);
 157         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1);
 158         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_L2_CACHE, 1);
 159         WREG32_SOC15_RLC(GC, 0, mmVM_L2_CNTL2, tmp);
 160
 161         tmp = mmVM_L2_CNTL3_DEFAULT;
 162         if (adev->gmc.translate_further) {
 163                 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, 12);
 164                 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3,
 165                                     L2_CACHE_BIGK_FRAGMENT_SIZE, 9);
 166         } else {
 167                 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, 9);
 168                 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3,
 169                                     L2_CACHE_BIGK_FRAGMENT_SIZE, 6);
 170         }
 171         WREG32_SOC15_RLC(GC, 0, mmVM_L2_CNTL3, tmp);
 172
 173         tmp = mmVM_L2_CNTL4_DEFAULT;
 174         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_PDE_REQUEST_PHYSICAL, 0);
 175         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_PTE_REQUEST_PHYSICAL, 0);
 176         WREG32_SOC15_RLC(GC, 0, mmVM_L2_CNTL4, tmp);
 177 }
 178
 179 static void gfxhub_v1_0_enable_system_domain(struct amdgpu_device *adev)
 180 {
 181         uint32_t tmp;
 182
 183         tmp = RREG32_SOC15(GC, 0, mmVM_CONTEXT0_CNTL);
 184         tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1);
 185         tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0);
 186         tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL,
 187                             RETRY_PERMISSION_OR_INVALID_PAGE_FAULT, 0);
 188         WREG32_SOC15(GC, 0, mmVM_CONTEXT0_CNTL, tmp);
 189 }
 190
 191 static void gfxhub_v1_0_disable_identity_aperture(struct amdgpu_device *adev)
 192 {
 193         WREG32_SOC15(GC, 0, mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32,
 194                      0XFFFFFFFF);
 195         WREG32_SOC15(GC, 0, mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32,
 196                      0x0000000F);
 197
 198         WREG32_SOC15(GC, 0, mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32,
 199                      0);
 200         WREG32_SOC15(GC, 0, mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32,
 201                      0);
 202
 203         WREG32_SOC15(GC, 0, mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32, 0);
 204         WREG32_SOC15(GC, 0, mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32, 0);
 205
 206 }
 207
 208 static void gfxhub_v1_0_setup_vmid_config(struct amdgpu_device *adev)
 209 {
 210         struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB_0];
 211         unsigned num_level, block_size;
 212         uint32_t tmp;
 213         int i;
 214
 215         num_level = adev->vm_manager.num_level;
 216         block_size = adev->vm_manager.block_size;
 217         if (adev->gmc.translate_further)
 218                 num_level -= 1;
 219         else
 220                 block_size -= 9;
 221
 222         for (i = 0; i <= 14; i++) {
 223                 tmp = RREG32_SOC15_OFFSET(GC, 0, mmVM_CONTEXT1_CNTL, i);
 224                 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1);
 225                 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH,
 226                                     num_level);
 227                 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 228                                     RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 229                 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 230                                     DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT,
 231                                     1);
 232                 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 233                                     PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 234                 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 235                                     VALID_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 236                 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 237                                     READ_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 238                 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 239                                     WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 240                 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 241                                     EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 242                 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 243                                     PAGE_TABLE_BLOCK_SIZE,
 244                                     block_size);
 245                 /* Send no-retry XNACK on fault to suppress VM fault storm. */
 246                 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 247                                     RETRY_PERMISSION_OR_INVALID_PAGE_FAULT,
 248                                     !amdgpu_noretry);
 249                 WREG32_SOC15_OFFSET(GC, 0, mmVM_CONTEXT1_CNTL,
 250                                     i * hub->ctx_distance, tmp);
 251                 WREG32_SOC15_OFFSET(GC, 0, mmVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32,
 252                                     i * hub->ctx_addr_distance, 0);
 253                 WREG32_SOC15_OFFSET(GC, 0, mmVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32,
 254                                     i * hub->ctx_addr_distance, 0);
 255                 WREG32_SOC15_OFFSET(GC, 0, mmVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32,
 256                                     i * hub->ctx_addr_distance,
 257                                     lower_32_bits(adev->vm_manager.max_pfn - 1));
 258                 WREG32_SOC15_OFFSET(GC, 0, mmVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32,
 259                                     i * hub->ctx_addr_distance,
 260                                     upper_32_bits(adev->vm_manager.max_pfn - 1));
 261         }
 262 }
 263
 264 static void gfxhub_v1_0_program_invalidation(struct amdgpu_device *adev)
 265 {
 266         struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB_0];
 267         unsigned i;
 268
 269         for (i = 0 ; i < 18; ++i) {
 270                 WREG32_SOC15_OFFSET(GC, 0, mmVM_INVALIDATE_ENG0_ADDR_RANGE_LO32,
 271                                     i * hub->eng_addr_distance, 0xffffffff);
 272                 WREG32_SOC15_OFFSET(GC, 0, mmVM_INVALIDATE_ENG0_ADDR_RANGE_HI32,
 273                                     i * hub->eng_addr_distance, 0x1f);
 274         }
 275 }
 276
 277 int gfxhub_v1_0_gart_enable(struct amdgpu_device *adev)
 278 {
 279         if (amdgpu_sriov_vf(adev) && adev->asic_type != CHIP_ARCTURUS) {
 280                 /*
 281                  * MC_VM_FB_LOCATION_BASE/TOP is NULL for VF, becuase they are
 282                  * VF copy registers so vbios post doesn't program them, for
 283                  * SRIOV driver need to program them
 284                  */
 285                 WREG32_SOC15_RLC(GC, 0, mmMC_VM_FB_LOCATION_BASE,
 286                              adev->gmc.vram_start >> 24);
 287                 WREG32_SOC15_RLC(GC, 0, mmMC_VM_FB_LOCATION_TOP,
 288                              adev->gmc.vram_end >> 24);
 289         }
 290
 291         /* GART Enable. */
 292         gfxhub_v1_0_init_gart_aperture_regs(adev);
 293         gfxhub_v1_0_init_system_aperture_regs(adev);
 294         gfxhub_v1_0_init_tlb_regs(adev);
 295         if (!amdgpu_sriov_vf(adev))
 296                 gfxhub_v1_0_init_cache_regs(adev);
 297
 298         gfxhub_v1_0_enable_system_domain(adev);
 299         if (!amdgpu_sriov_vf(adev))
 300                 gfxhub_v1_0_disable_identity_aperture(adev);
 301         gfxhub_v1_0_setup_vmid_config(adev);
 302         gfxhub_v1_0_program_invalidation(adev);
 303
 304         return 0;
 305 }
 306
 307 void gfxhub_v1_0_gart_disable(struct amdgpu_device *adev)
 308 {
 309         struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB_0];
 310         u32 tmp;
 311         u32 i;
 312
 313         /* Disable all tables */
 314         for (i = 0; i < 16; i++)
 315                 WREG32_SOC15_OFFSET(GC, 0, mmVM_CONTEXT0_CNTL,
 316                                     i * hub->ctx_distance, 0);
 317
 318         /* Setup TLB control */
 319         tmp = RREG32_SOC15(GC, 0, mmMC_VM_MX_L1_TLB_CNTL);
 320         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0);
 321         tmp = REG_SET_FIELD(tmp,
 322                                 MC_VM_MX_L1_TLB_CNTL,
 323                                 ENABLE_ADVANCED_DRIVER_MODEL,
 324                                 0);
 325         WREG32_SOC15_RLC(GC, 0, mmMC_VM_MX_L1_TLB_CNTL, tmp);
 326
 327         /* Setup L2 cache */
 328         WREG32_FIELD15(GC, 0, VM_L2_CNTL, ENABLE_L2_CACHE, 0);
 329         WREG32_SOC15(GC, 0, mmVM_L2_CNTL3, 0);
 330 }
 331
 332 /**
 333  * gfxhub_v1_0_set_fault_enable_default - update GART/VM fault handling
 334  *
 335  * @adev: amdgpu_device pointer
 336  * @value: true redirects VM faults to the default page
 337  */
 338 void gfxhub_v1_0_set_fault_enable_default(struct amdgpu_device *adev,
 339                                           bool value)
 340 {
 341         u32 tmp;
 342         tmp = RREG32_SOC15(GC, 0, mmVM_L2_PROTECTION_FAULT_CNTL);
 343         tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
 344                         RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 345         tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
 346                         PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 347         tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
 348                         PDE1_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 349         tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
 350                         PDE2_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 351         tmp = REG_SET_FIELD(tmp,
 352                         VM_L2_PROTECTION_FAULT_CNTL,
 353                         TRANSLATE_FURTHER_PROTECTION_FAULT_ENABLE_DEFAULT,
 354                         value);
 355         tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
 356                         NACK_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 357         tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
 358                         DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 359         tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
 360                         VALID_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 361         tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
 362                         READ_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 363         tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
 364                         WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 365         tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
 366                         EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 367         if (!value) {
 368                 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
 369                                 CRASH_ON_NO_RETRY_FAULT, 1);
 370                 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
 371                                 CRASH_ON_RETRY_FAULT, 1);
 372         }
 373         WREG32_SOC15(GC, 0, mmVM_L2_PROTECTION_FAULT_CNTL, tmp);
 374 }
 375
 376 void gfxhub_v1_0_init(struct amdgpu_device *adev)
 377 {
 378         struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB_0];
 379
 380         hub->ctx0_ptb_addr_lo32 =
 381                 SOC15_REG_OFFSET(GC, 0,
 382                                  mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32);
 383         hub->ctx0_ptb_addr_hi32 =
 384                 SOC15_REG_OFFSET(GC, 0,
 385                                  mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32);
 386         hub->vm_inv_eng0_sem =
 387                 SOC15_REG_OFFSET(GC, 0, mmVM_INVALIDATE_ENG0_SEM);
 388         hub->vm_inv_eng0_req =
 389                 SOC15_REG_OFFSET(GC, 0, mmVM_INVALIDATE_ENG0_REQ);
 390         hub->vm_inv_eng0_ack =
 391                 SOC15_REG_OFFSET(GC, 0, mmVM_INVALIDATE_ENG0_ACK);
 392         hub->vm_context0_cntl =
 393                 SOC15_REG_OFFSET(GC, 0, mmVM_CONTEXT0_CNTL);
 394         hub->vm_l2_pro_fault_status =
 395                 SOC15_REG_OFFSET(GC, 0, mmVM_L2_PROTECTION_FAULT_STATUS);
 396         hub->vm_l2_pro_fault_cntl =
 397                 SOC15_REG_OFFSET(GC, 0, mmVM_L2_PROTECTION_FAULT_CNTL);
 398
 399         hub->ctx_distance = mmVM_CONTEXT1_CNTL - mmVM_CONTEXT0_CNTL;
 400         hub->ctx_addr_distance = mmVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32 -
 401                 mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32;
 402         hub->eng_distance = mmVM_INVALIDATE_ENG1_REQ - mmVM_INVALIDATE_ENG0_REQ;
 403         hub->eng_addr_distance = mmVM_INVALIDATE_ENG1_ADDR_RANGE_LO32 -
 404                 mmVM_INVALIDATE_ENG0_ADDR_RANGE_LO32;
 405 }