2 * Copyright 2022 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
23 #include <linux/firmware.h>
26 #include "amdgpu_gfx.h"
29 #include "soc15_common.h"
30 #include "vega10_enum.h"
32 #include "v9_structs.h"
34 #include "ivsrcid/gfx/irqsrcs_gfx_9_0.h"
36 #include "gc/gc_9_4_3_offset.h"
37 #include "gc/gc_9_4_3_sh_mask.h"
39 #include "gfx_v9_4_3.h"
40 #include "amdgpu_xcp.h"
42 MODULE_FIRMWARE("amdgpu/gc_9_4_3_mec.bin");
43 MODULE_FIRMWARE("amdgpu/gc_9_4_3_rlc.bin");
45 #define GFX9_MEC_HPD_SIZE 4096
46 #define RLCG_UCODE_LOADING_START_ADDRESS 0x00002000L
48 #define GOLDEN_GB_ADDR_CONFIG 0x2a114042
49 #define CP_HQD_PERSISTENT_STATE_DEFAULT 0xbe05301
51 struct amdgpu_gfx_ras gfx_v9_4_3_ras;
53 static void gfx_v9_4_3_set_ring_funcs(struct amdgpu_device *adev);
54 static void gfx_v9_4_3_set_irq_funcs(struct amdgpu_device *adev);
55 static void gfx_v9_4_3_set_gds_init(struct amdgpu_device *adev);
56 static void gfx_v9_4_3_set_rlc_funcs(struct amdgpu_device *adev);
57 static int gfx_v9_4_3_get_cu_info(struct amdgpu_device *adev,
58 struct amdgpu_cu_info *cu_info);
60 static void gfx_v9_4_3_kiq_set_resources(struct amdgpu_ring *kiq_ring,
63 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_RESOURCES, 6));
64 amdgpu_ring_write(kiq_ring,
65 PACKET3_SET_RESOURCES_VMID_MASK(0) |
66 /* vmid_mask:0* queue_type:0 (KIQ) */
67 PACKET3_SET_RESOURCES_QUEUE_TYPE(0));
68 amdgpu_ring_write(kiq_ring,
69 lower_32_bits(queue_mask)); /* queue mask lo */
70 amdgpu_ring_write(kiq_ring,
71 upper_32_bits(queue_mask)); /* queue mask hi */
72 amdgpu_ring_write(kiq_ring, 0); /* gws mask lo */
73 amdgpu_ring_write(kiq_ring, 0); /* gws mask hi */
74 amdgpu_ring_write(kiq_ring, 0); /* oac mask */
75 amdgpu_ring_write(kiq_ring, 0); /* gds heap base:0, gds heap size:0 */
78 static void gfx_v9_4_3_kiq_map_queues(struct amdgpu_ring *kiq_ring,
79 struct amdgpu_ring *ring)
81 struct amdgpu_device *adev = kiq_ring->adev;
82 uint64_t mqd_addr = amdgpu_bo_gpu_offset(ring->mqd_obj);
83 uint64_t wptr_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
84 uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0;
86 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5));
87 /* Q_sel:0, vmid:0, vidmem: 1, engine:0, num_Q:1*/
88 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */
89 PACKET3_MAP_QUEUES_QUEUE_SEL(0) | /* Queue_Sel */
90 PACKET3_MAP_QUEUES_VMID(0) | /* VMID */
91 PACKET3_MAP_QUEUES_QUEUE(ring->queue) |
92 PACKET3_MAP_QUEUES_PIPE(ring->pipe) |
93 PACKET3_MAP_QUEUES_ME((ring->me == 1 ? 0 : 1)) |
94 /*queue_type: normal compute queue */
95 PACKET3_MAP_QUEUES_QUEUE_TYPE(0) |
96 /* alloc format: all_on_one_pipe */
97 PACKET3_MAP_QUEUES_ALLOC_FORMAT(0) |
98 PACKET3_MAP_QUEUES_ENGINE_SEL(eng_sel) |
99 /* num_queues: must be 1 */
100 PACKET3_MAP_QUEUES_NUM_QUEUES(1));
101 amdgpu_ring_write(kiq_ring,
102 PACKET3_MAP_QUEUES_DOORBELL_OFFSET(ring->doorbell_index));
103 amdgpu_ring_write(kiq_ring, lower_32_bits(mqd_addr));
104 amdgpu_ring_write(kiq_ring, upper_32_bits(mqd_addr));
105 amdgpu_ring_write(kiq_ring, lower_32_bits(wptr_addr));
106 amdgpu_ring_write(kiq_ring, upper_32_bits(wptr_addr));
109 static void gfx_v9_4_3_kiq_unmap_queues(struct amdgpu_ring *kiq_ring,
110 struct amdgpu_ring *ring,
111 enum amdgpu_unmap_queues_action action,
112 u64 gpu_addr, u64 seq)
114 uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0;
116 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_UNMAP_QUEUES, 4));
117 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */
118 PACKET3_UNMAP_QUEUES_ACTION(action) |
119 PACKET3_UNMAP_QUEUES_QUEUE_SEL(0) |
120 PACKET3_UNMAP_QUEUES_ENGINE_SEL(eng_sel) |
121 PACKET3_UNMAP_QUEUES_NUM_QUEUES(1));
122 amdgpu_ring_write(kiq_ring,
123 PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET0(ring->doorbell_index));
125 if (action == PREEMPT_QUEUES_NO_UNMAP) {
126 amdgpu_ring_write(kiq_ring, lower_32_bits(gpu_addr));
127 amdgpu_ring_write(kiq_ring, upper_32_bits(gpu_addr));
128 amdgpu_ring_write(kiq_ring, seq);
130 amdgpu_ring_write(kiq_ring, 0);
131 amdgpu_ring_write(kiq_ring, 0);
132 amdgpu_ring_write(kiq_ring, 0);
136 static void gfx_v9_4_3_kiq_query_status(struct amdgpu_ring *kiq_ring,
137 struct amdgpu_ring *ring,
141 uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0;
143 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_QUERY_STATUS, 5));
144 amdgpu_ring_write(kiq_ring,
145 PACKET3_QUERY_STATUS_CONTEXT_ID(0) |
146 PACKET3_QUERY_STATUS_INTERRUPT_SEL(0) |
147 PACKET3_QUERY_STATUS_COMMAND(2));
148 /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */
149 amdgpu_ring_write(kiq_ring,
150 PACKET3_QUERY_STATUS_DOORBELL_OFFSET(ring->doorbell_index) |
151 PACKET3_QUERY_STATUS_ENG_SEL(eng_sel));
152 amdgpu_ring_write(kiq_ring, lower_32_bits(addr));
153 amdgpu_ring_write(kiq_ring, upper_32_bits(addr));
154 amdgpu_ring_write(kiq_ring, lower_32_bits(seq));
155 amdgpu_ring_write(kiq_ring, upper_32_bits(seq));
158 static void gfx_v9_4_3_kiq_invalidate_tlbs(struct amdgpu_ring *kiq_ring,
159 uint16_t pasid, uint32_t flush_type,
162 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_INVALIDATE_TLBS, 0));
163 amdgpu_ring_write(kiq_ring,
164 PACKET3_INVALIDATE_TLBS_DST_SEL(1) |
165 PACKET3_INVALIDATE_TLBS_ALL_HUB(all_hub) |
166 PACKET3_INVALIDATE_TLBS_PASID(pasid) |
167 PACKET3_INVALIDATE_TLBS_FLUSH_TYPE(flush_type));
170 static const struct kiq_pm4_funcs gfx_v9_4_3_kiq_pm4_funcs = {
171 .kiq_set_resources = gfx_v9_4_3_kiq_set_resources,
172 .kiq_map_queues = gfx_v9_4_3_kiq_map_queues,
173 .kiq_unmap_queues = gfx_v9_4_3_kiq_unmap_queues,
174 .kiq_query_status = gfx_v9_4_3_kiq_query_status,
175 .kiq_invalidate_tlbs = gfx_v9_4_3_kiq_invalidate_tlbs,
176 .set_resources_size = 8,
177 .map_queues_size = 7,
178 .unmap_queues_size = 6,
179 .query_status_size = 7,
180 .invalidate_tlbs_size = 2,
183 static void gfx_v9_4_3_set_kiq_pm4_funcs(struct amdgpu_device *adev)
187 num_xcc = NUM_XCC(adev->gfx.xcc_mask);
188 for (i = 0; i < num_xcc; i++)
189 adev->gfx.kiq[i].pmf = &gfx_v9_4_3_kiq_pm4_funcs;
192 static void gfx_v9_4_3_init_golden_registers(struct amdgpu_device *adev)
194 int i, num_xcc, dev_inst;
196 num_xcc = NUM_XCC(adev->gfx.xcc_mask);
197 for (i = 0; i < num_xcc; i++) {
198 dev_inst = GET_INST(GC, i);
200 WREG32_SOC15(GC, dev_inst, regGB_ADDR_CONFIG,
201 GOLDEN_GB_ADDR_CONFIG);
202 /* Golden settings applied by driver for ASIC with rev_id 0 */
203 if (adev->rev_id == 0) {
204 WREG32_FIELD15_PREREG(GC, dev_inst, TCP_UTCL1_CNTL1,
205 REDUCE_FIFO_DEPTH_BY_2, 2);
207 WREG32_FIELD15_PREREG(GC, dev_inst, TCP_UTCL1_CNTL2,
213 static void gfx_v9_4_3_write_data_to_reg(struct amdgpu_ring *ring, int eng_sel,
214 bool wc, uint32_t reg, uint32_t val)
216 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
217 amdgpu_ring_write(ring, WRITE_DATA_ENGINE_SEL(eng_sel) |
218 WRITE_DATA_DST_SEL(0) |
219 (wc ? WR_CONFIRM : 0));
220 amdgpu_ring_write(ring, reg);
221 amdgpu_ring_write(ring, 0);
222 amdgpu_ring_write(ring, val);
225 static void gfx_v9_4_3_wait_reg_mem(struct amdgpu_ring *ring, int eng_sel,
226 int mem_space, int opt, uint32_t addr0,
227 uint32_t addr1, uint32_t ref, uint32_t mask,
230 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
231 amdgpu_ring_write(ring,
232 /* memory (1) or register (0) */
233 (WAIT_REG_MEM_MEM_SPACE(mem_space) |
234 WAIT_REG_MEM_OPERATION(opt) | /* wait */
235 WAIT_REG_MEM_FUNCTION(3) | /* equal */
236 WAIT_REG_MEM_ENGINE(eng_sel)));
239 BUG_ON(addr0 & 0x3); /* Dword align */
240 amdgpu_ring_write(ring, addr0);
241 amdgpu_ring_write(ring, addr1);
242 amdgpu_ring_write(ring, ref);
243 amdgpu_ring_write(ring, mask);
244 amdgpu_ring_write(ring, inv); /* poll interval */
247 static int gfx_v9_4_3_ring_test_ring(struct amdgpu_ring *ring)
249 uint32_t scratch_reg0_offset, xcc_offset;
250 struct amdgpu_device *adev = ring->adev;
255 /* Use register offset which is local to XCC in the packet */
256 xcc_offset = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG0);
257 scratch_reg0_offset = SOC15_REG_OFFSET(GC, GET_INST(GC, ring->xcc_id), regSCRATCH_REG0);
258 WREG32(scratch_reg0_offset, 0xCAFEDEAD);
259 tmp = RREG32(scratch_reg0_offset);
261 r = amdgpu_ring_alloc(ring, 3);
265 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1));
266 amdgpu_ring_write(ring, xcc_offset - PACKET3_SET_UCONFIG_REG_START);
267 amdgpu_ring_write(ring, 0xDEADBEEF);
268 amdgpu_ring_commit(ring);
270 for (i = 0; i < adev->usec_timeout; i++) {
271 tmp = RREG32(scratch_reg0_offset);
272 if (tmp == 0xDEADBEEF)
277 if (i >= adev->usec_timeout)
282 static int gfx_v9_4_3_ring_test_ib(struct amdgpu_ring *ring, long timeout)
284 struct amdgpu_device *adev = ring->adev;
286 struct dma_fence *f = NULL;
293 r = amdgpu_device_wb_get(adev, &index);
297 gpu_addr = adev->wb.gpu_addr + (index * 4);
298 adev->wb.wb[index] = cpu_to_le32(0xCAFEDEAD);
299 memset(&ib, 0, sizeof(ib));
300 r = amdgpu_ib_get(adev, NULL, 16,
301 AMDGPU_IB_POOL_DIRECT, &ib);
305 ib.ptr[0] = PACKET3(PACKET3_WRITE_DATA, 3);
306 ib.ptr[1] = WRITE_DATA_DST_SEL(5) | WR_CONFIRM;
307 ib.ptr[2] = lower_32_bits(gpu_addr);
308 ib.ptr[3] = upper_32_bits(gpu_addr);
309 ib.ptr[4] = 0xDEADBEEF;
312 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
316 r = dma_fence_wait_timeout(f, false, timeout);
324 tmp = adev->wb.wb[index];
325 if (tmp == 0xDEADBEEF)
331 amdgpu_ib_free(adev, &ib, NULL);
334 amdgpu_device_wb_free(adev, index);
339 /* This value might differs per partition */
340 static uint64_t gfx_v9_4_3_get_gpu_clock_counter(struct amdgpu_device *adev)
344 mutex_lock(&adev->gfx.gpu_clock_mutex);
345 WREG32_SOC15(GC, GET_INST(GC, 0), regRLC_CAPTURE_GPU_CLOCK_COUNT, 1);
346 clock = (uint64_t)RREG32_SOC15(GC, GET_INST(GC, 0), regRLC_GPU_CLOCK_COUNT_LSB) |
347 ((uint64_t)RREG32_SOC15(GC, GET_INST(GC, 0), regRLC_GPU_CLOCK_COUNT_MSB) << 32ULL);
348 mutex_unlock(&adev->gfx.gpu_clock_mutex);
353 static void gfx_v9_4_3_free_microcode(struct amdgpu_device *adev)
355 amdgpu_ucode_release(&adev->gfx.pfp_fw);
356 amdgpu_ucode_release(&adev->gfx.me_fw);
357 amdgpu_ucode_release(&adev->gfx.ce_fw);
358 amdgpu_ucode_release(&adev->gfx.rlc_fw);
359 amdgpu_ucode_release(&adev->gfx.mec_fw);
360 amdgpu_ucode_release(&adev->gfx.mec2_fw);
362 kfree(adev->gfx.rlc.register_list_format);
365 static int gfx_v9_4_3_init_rlc_microcode(struct amdgpu_device *adev,
366 const char *chip_name)
370 const struct rlc_firmware_header_v2_0 *rlc_hdr;
371 uint16_t version_major;
372 uint16_t version_minor;
374 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_rlc.bin", chip_name);
376 err = amdgpu_ucode_request(adev, &adev->gfx.rlc_fw, fw_name);
379 rlc_hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data;
381 version_major = le16_to_cpu(rlc_hdr->header.header_version_major);
382 version_minor = le16_to_cpu(rlc_hdr->header.header_version_minor);
383 err = amdgpu_gfx_rlc_init_microcode(adev, version_major, version_minor);
386 amdgpu_ucode_release(&adev->gfx.rlc_fw);
391 static bool gfx_v9_4_3_should_disable_gfxoff(struct pci_dev *pdev)
396 static void gfx_v9_4_3_check_if_need_gfxoff(struct amdgpu_device *adev)
398 if (gfx_v9_4_3_should_disable_gfxoff(adev->pdev))
399 adev->pm.pp_feature &= ~PP_GFXOFF_MASK;
402 static int gfx_v9_4_3_init_cp_compute_microcode(struct amdgpu_device *adev,
403 const char *chip_name)
408 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec.bin", chip_name);
410 err = amdgpu_ucode_request(adev, &adev->gfx.mec_fw, fw_name);
413 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC1);
414 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC1_JT);
416 adev->gfx.mec2_fw_version = adev->gfx.mec_fw_version;
417 adev->gfx.mec2_feature_version = adev->gfx.mec_feature_version;
419 gfx_v9_4_3_check_if_need_gfxoff(adev);
423 amdgpu_ucode_release(&adev->gfx.mec_fw);
427 static int gfx_v9_4_3_init_microcode(struct amdgpu_device *adev)
429 const char *chip_name;
432 chip_name = "gc_9_4_3";
434 r = gfx_v9_4_3_init_rlc_microcode(adev, chip_name);
438 r = gfx_v9_4_3_init_cp_compute_microcode(adev, chip_name);
445 static void gfx_v9_4_3_mec_fini(struct amdgpu_device *adev)
447 amdgpu_bo_free_kernel(&adev->gfx.mec.hpd_eop_obj, NULL, NULL);
448 amdgpu_bo_free_kernel(&adev->gfx.mec.mec_fw_obj, NULL, NULL);
451 static int gfx_v9_4_3_mec_init(struct amdgpu_device *adev)
455 const __le32 *fw_data;
460 const struct gfx_firmware_header_v1_0 *mec_hdr;
462 num_xcc = NUM_XCC(adev->gfx.xcc_mask);
463 for (i = 0; i < num_xcc; i++)
464 bitmap_zero(adev->gfx.mec_bitmap[i].queue_bitmap,
465 AMDGPU_MAX_COMPUTE_QUEUES);
467 /* take ownership of the relevant compute queues */
468 amdgpu_gfx_compute_queue_acquire(adev);
470 adev->gfx.num_compute_rings * num_xcc * GFX9_MEC_HPD_SIZE;
472 r = amdgpu_bo_create_reserved(adev, mec_hpd_size, PAGE_SIZE,
473 AMDGPU_GEM_DOMAIN_VRAM |
474 AMDGPU_GEM_DOMAIN_GTT,
475 &adev->gfx.mec.hpd_eop_obj,
476 &adev->gfx.mec.hpd_eop_gpu_addr,
479 dev_warn(adev->dev, "(%d) create HDP EOP bo failed\n", r);
480 gfx_v9_4_3_mec_fini(adev);
484 if (amdgpu_emu_mode == 1) {
485 for (i = 0; i < mec_hpd_size / 4; i++) {
486 memset((void *)(hpd + i), 0, 4);
491 memset(hpd, 0, mec_hpd_size);
494 amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj);
495 amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj);
498 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
500 fw_data = (const __le32 *)
501 (adev->gfx.mec_fw->data +
502 le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes));
503 fw_size = le32_to_cpu(mec_hdr->header.ucode_size_bytes);
505 r = amdgpu_bo_create_reserved(adev, mec_hdr->header.ucode_size_bytes,
506 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,
507 &adev->gfx.mec.mec_fw_obj,
508 &adev->gfx.mec.mec_fw_gpu_addr,
511 dev_warn(adev->dev, "(%d) create mec firmware bo failed\n", r);
512 gfx_v9_4_3_mec_fini(adev);
516 memcpy(fw, fw_data, fw_size);
518 amdgpu_bo_kunmap(adev->gfx.mec.mec_fw_obj);
519 amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_obj);
524 static void gfx_v9_4_3_xcc_select_se_sh(struct amdgpu_device *adev, u32 se_num,
525 u32 sh_num, u32 instance, int xcc_id)
529 if (instance == 0xffffffff)
530 data = REG_SET_FIELD(0, GRBM_GFX_INDEX,
531 INSTANCE_BROADCAST_WRITES, 1);
533 data = REG_SET_FIELD(0, GRBM_GFX_INDEX,
534 INSTANCE_INDEX, instance);
536 if (se_num == 0xffffffff)
537 data = REG_SET_FIELD(data, GRBM_GFX_INDEX,
538 SE_BROADCAST_WRITES, 1);
540 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num);
542 if (sh_num == 0xffffffff)
543 data = REG_SET_FIELD(data, GRBM_GFX_INDEX,
544 SH_BROADCAST_WRITES, 1);
546 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_INDEX, sh_num);
548 WREG32_SOC15_RLC_SHADOW_EX(reg, GC, GET_INST(GC, xcc_id), regGRBM_GFX_INDEX, data);
551 static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, uint32_t wave, uint32_t address)
553 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regSQ_IND_INDEX,
554 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) |
555 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) |
556 (address << SQ_IND_INDEX__INDEX__SHIFT) |
557 (SQ_IND_INDEX__FORCE_READ_MASK));
558 return RREG32_SOC15(GC, GET_INST(GC, xcc_id), regSQ_IND_DATA);
561 static void wave_read_regs(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd,
562 uint32_t wave, uint32_t thread,
563 uint32_t regno, uint32_t num, uint32_t *out)
565 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regSQ_IND_INDEX,
566 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) |
567 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) |
568 (regno << SQ_IND_INDEX__INDEX__SHIFT) |
569 (thread << SQ_IND_INDEX__THREAD_ID__SHIFT) |
570 (SQ_IND_INDEX__FORCE_READ_MASK) |
571 (SQ_IND_INDEX__AUTO_INCR_MASK));
573 *(out++) = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regSQ_IND_DATA);
576 static void gfx_v9_4_3_read_wave_data(struct amdgpu_device *adev,
577 uint32_t xcc_id, uint32_t simd, uint32_t wave,
578 uint32_t *dst, int *no_fields)
580 /* type 1 wave data */
581 dst[(*no_fields)++] = 1;
582 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_STATUS);
583 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_PC_LO);
584 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_PC_HI);
585 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_EXEC_LO);
586 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_EXEC_HI);
587 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_HW_ID);
588 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_INST_DW0);
589 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_INST_DW1);
590 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_GPR_ALLOC);
591 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_LDS_ALLOC);
592 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_TRAPSTS);
593 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_IB_STS);
594 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_IB_DBG0);
595 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_M0);
596 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_MODE);
599 static void gfx_v9_4_3_read_wave_sgprs(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd,
600 uint32_t wave, uint32_t start,
601 uint32_t size, uint32_t *dst)
603 wave_read_regs(adev, xcc_id, simd, wave, 0,
604 start + SQIND_WAVE_SGPRS_OFFSET, size, dst);
607 static void gfx_v9_4_3_read_wave_vgprs(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd,
608 uint32_t wave, uint32_t thread,
609 uint32_t start, uint32_t size,
612 wave_read_regs(adev, xcc_id, simd, wave, thread,
613 start + SQIND_WAVE_VGPRS_OFFSET, size, dst);
616 static void gfx_v9_4_3_select_me_pipe_q(struct amdgpu_device *adev,
617 u32 me, u32 pipe, u32 q, u32 vm, u32 xcc_id)
619 soc15_grbm_select(adev, me, pipe, q, vm, GET_INST(GC, xcc_id));
623 static int gfx_v9_4_3_switch_compute_partition(struct amdgpu_device *adev,
624 int num_xccs_per_xcp)
629 if (adev->psp.funcs) {
630 ret = psp_spatial_partition(&adev->psp,
631 NUM_XCC(adev->gfx.xcc_mask) /
636 num_xcc = NUM_XCC(adev->gfx.xcc_mask);
638 for (i = 0; i < num_xcc; i++) {
639 tmp = REG_SET_FIELD(tmp, CP_HYP_XCP_CTL, NUM_XCC_IN_XCP,
641 tmp = REG_SET_FIELD(tmp, CP_HYP_XCP_CTL, VIRTUAL_XCC_ID,
642 i % num_xccs_per_xcp);
643 WREG32_SOC15(GC, GET_INST(GC, i), regCP_HYP_XCP_CTL,
649 adev->gfx.num_xcc_per_xcp = num_xccs_per_xcp;
654 static int gfx_v9_4_3_ih_to_xcc_inst(struct amdgpu_device *adev, int ih_node)
658 xcc = hweight8(adev->gfx.xcc_mask & GENMASK(ih_node / 2, 0));
660 dev_err(adev->dev, "Couldn't find xcc mapping from IH node");
667 static const struct amdgpu_gfx_funcs gfx_v9_4_3_gfx_funcs = {
668 .get_gpu_clock_counter = &gfx_v9_4_3_get_gpu_clock_counter,
669 .select_se_sh = &gfx_v9_4_3_xcc_select_se_sh,
670 .read_wave_data = &gfx_v9_4_3_read_wave_data,
671 .read_wave_sgprs = &gfx_v9_4_3_read_wave_sgprs,
672 .read_wave_vgprs = &gfx_v9_4_3_read_wave_vgprs,
673 .select_me_pipe_q = &gfx_v9_4_3_select_me_pipe_q,
674 .switch_partition_mode = &gfx_v9_4_3_switch_compute_partition,
675 .ih_node_to_logical_xcc = &gfx_v9_4_3_ih_to_xcc_inst,
678 static int gfx_v9_4_3_gpu_early_init(struct amdgpu_device *adev)
682 adev->gfx.funcs = &gfx_v9_4_3_gfx_funcs;
683 adev->gfx.ras = &gfx_v9_4_3_ras;
685 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
686 case IP_VERSION(9, 4, 3):
687 adev->gfx.config.max_hw_contexts = 8;
688 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
689 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
690 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
691 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0;
692 gb_addr_config = RREG32_SOC15(GC, GET_INST(GC, 0), regGB_ADDR_CONFIG);
699 adev->gfx.config.gb_addr_config = gb_addr_config;
701 adev->gfx.config.gb_addr_config_fields.num_pipes = 1 <<
703 adev->gfx.config.gb_addr_config,
707 adev->gfx.config.max_tile_pipes =
708 adev->gfx.config.gb_addr_config_fields.num_pipes;
710 adev->gfx.config.gb_addr_config_fields.num_banks = 1 <<
712 adev->gfx.config.gb_addr_config,
715 adev->gfx.config.gb_addr_config_fields.max_compress_frags = 1 <<
717 adev->gfx.config.gb_addr_config,
719 MAX_COMPRESSED_FRAGS);
720 adev->gfx.config.gb_addr_config_fields.num_rb_per_se = 1 <<
722 adev->gfx.config.gb_addr_config,
725 adev->gfx.config.gb_addr_config_fields.num_se = 1 <<
727 adev->gfx.config.gb_addr_config,
730 adev->gfx.config.gb_addr_config_fields.pipe_interleave_size = 1 << (8 +
732 adev->gfx.config.gb_addr_config,
734 PIPE_INTERLEAVE_SIZE));
739 static int gfx_v9_4_3_compute_ring_init(struct amdgpu_device *adev, int ring_id,
740 int xcc_id, int mec, int pipe, int queue)
743 struct amdgpu_ring *ring = &adev->gfx.compute_ring[ring_id];
744 unsigned int hw_prio;
745 uint32_t xcc_doorbell_start;
747 ring = &adev->gfx.compute_ring[xcc_id * adev->gfx.num_compute_rings +
751 ring->xcc_id = xcc_id;
756 ring->ring_obj = NULL;
757 ring->use_doorbell = true;
758 xcc_doorbell_start = adev->doorbell_index.mec_ring0 +
759 xcc_id * adev->doorbell_index.xcc_doorbell_range;
760 ring->doorbell_index = (xcc_doorbell_start + ring_id) << 1;
761 ring->eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr +
762 (ring_id + xcc_id * adev->gfx.num_compute_rings) *
764 ring->vm_hub = AMDGPU_GFXHUB(xcc_id);
765 sprintf(ring->name, "comp_%d.%d.%d.%d",
766 ring->xcc_id, ring->me, ring->pipe, ring->queue);
768 irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP
769 + ((ring->me - 1) * adev->gfx.mec.num_pipe_per_mec)
771 hw_prio = amdgpu_gfx_is_high_priority_compute_queue(adev, ring) ?
772 AMDGPU_GFX_PIPE_PRIO_HIGH : AMDGPU_GFX_PIPE_PRIO_NORMAL;
773 /* type-2 packets are deprecated on MEC, use type-3 instead */
774 return amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, irq_type,
778 static int gfx_v9_4_3_sw_init(void *handle)
780 int i, j, k, r, ring_id, xcc_id, num_xcc;
781 struct amdgpu_kiq *kiq;
782 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
784 adev->gfx.mec.num_mec = 2;
785 adev->gfx.mec.num_pipe_per_mec = 4;
786 adev->gfx.mec.num_queue_per_pipe = 8;
788 num_xcc = NUM_XCC(adev->gfx.xcc_mask);
791 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_9_0__SRCID__CP_EOP_INTERRUPT, &adev->gfx.eop_irq);
796 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_9_0__SRCID__CP_PRIV_REG_FAULT,
797 &adev->gfx.priv_reg_irq);
801 /* Privileged inst */
802 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_9_0__SRCID__CP_PRIV_INSTR_FAULT,
803 &adev->gfx.priv_inst_irq);
807 adev->gfx.gfx_current_status = AMDGPU_GFX_NORMAL_MODE;
809 r = adev->gfx.rlc.funcs->init(adev);
811 DRM_ERROR("Failed to init rlc BOs!\n");
815 r = gfx_v9_4_3_mec_init(adev);
817 DRM_ERROR("Failed to init MEC BOs!\n");
821 /* set up the compute queues - allocate horizontally across pipes */
822 for (xcc_id = 0; xcc_id < num_xcc; xcc_id++) {
824 for (i = 0; i < adev->gfx.mec.num_mec; ++i) {
825 for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) {
826 for (k = 0; k < adev->gfx.mec.num_pipe_per_mec;
828 if (!amdgpu_gfx_is_mec_queue_enabled(
829 adev, xcc_id, i, k, j))
832 r = gfx_v9_4_3_compute_ring_init(adev,
844 r = amdgpu_gfx_kiq_init(adev, GFX9_MEC_HPD_SIZE, xcc_id);
846 DRM_ERROR("Failed to init KIQ BOs!\n");
850 kiq = &adev->gfx.kiq[xcc_id];
851 r = amdgpu_gfx_kiq_init_ring(adev, &kiq->ring, &kiq->irq, xcc_id);
855 /* create MQD for all compute queues as wel as KIQ for SRIOV case */
856 r = amdgpu_gfx_mqd_sw_init(adev,
857 sizeof(struct v9_mqd_allocation), xcc_id);
862 r = gfx_v9_4_3_gpu_early_init(adev);
866 r = amdgpu_gfx_ras_sw_init(adev);
871 if (!amdgpu_sriov_vf(adev))
872 r = amdgpu_gfx_sysfs_init(adev);
877 static int gfx_v9_4_3_sw_fini(void *handle)
880 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
882 num_xcc = NUM_XCC(adev->gfx.xcc_mask);
883 for (i = 0; i < adev->gfx.num_compute_rings * num_xcc; i++)
884 amdgpu_ring_fini(&adev->gfx.compute_ring[i]);
886 for (i = 0; i < num_xcc; i++) {
887 amdgpu_gfx_mqd_sw_fini(adev, i);
888 amdgpu_gfx_kiq_free_ring(&adev->gfx.kiq[i].ring);
889 amdgpu_gfx_kiq_fini(adev, i);
892 gfx_v9_4_3_mec_fini(adev);
893 amdgpu_bo_unref(&adev->gfx.rlc.clear_state_obj);
894 gfx_v9_4_3_free_microcode(adev);
895 if (!amdgpu_sriov_vf(adev))
896 amdgpu_gfx_sysfs_fini(adev);
901 #define DEFAULT_SH_MEM_BASES (0x6000)
902 static void gfx_v9_4_3_xcc_init_compute_vmid(struct amdgpu_device *adev,
906 uint32_t sh_mem_config;
907 uint32_t sh_mem_bases;
911 * Configure apertures:
912 * LDS: 0x60000000'00000000 - 0x60000001'00000000 (4GB)
913 * Scratch: 0x60000001'00000000 - 0x60000002'00000000 (4GB)
914 * GPUVM: 0x60010000'00000000 - 0x60020000'00000000 (1TB)
916 sh_mem_bases = DEFAULT_SH_MEM_BASES | (DEFAULT_SH_MEM_BASES << 16);
918 sh_mem_config = SH_MEM_ADDRESS_MODE_64 |
919 SH_MEM_ALIGNMENT_MODE_UNALIGNED <<
920 SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT;
922 mutex_lock(&adev->srbm_mutex);
923 for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) {
924 soc15_grbm_select(adev, 0, 0, 0, i, GET_INST(GC, xcc_id));
926 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regSH_MEM_CONFIG, sh_mem_config);
927 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regSH_MEM_BASES, sh_mem_bases);
929 /* Enable trap for each kfd vmid. */
930 data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regSPI_GDBG_PER_VMID_CNTL);
931 data = REG_SET_FIELD(data, SPI_GDBG_PER_VMID_CNTL, TRAP_EN, 1);
932 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regSPI_GDBG_PER_VMID_CNTL, data);
934 soc15_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id));
935 mutex_unlock(&adev->srbm_mutex);
937 /* Initialize all compute VMIDs to have no GDS, GWS, or OA
938 acccess. These should be enabled by FW for target VMIDs. */
939 for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) {
940 WREG32_SOC15_OFFSET(GC, GET_INST(GC, xcc_id), regGDS_VMID0_BASE, 2 * i, 0);
941 WREG32_SOC15_OFFSET(GC, GET_INST(GC, xcc_id), regGDS_VMID0_SIZE, 2 * i, 0);
942 WREG32_SOC15_OFFSET(GC, GET_INST(GC, xcc_id), regGDS_GWS_VMID0, i, 0);
943 WREG32_SOC15_OFFSET(GC, GET_INST(GC, xcc_id), regGDS_OA_VMID0, i, 0);
947 static void gfx_v9_4_3_xcc_init_gds_vmid(struct amdgpu_device *adev, int xcc_id)
952 * Initialize all compute and user-gfx VMIDs to have no GDS, GWS, or OA
953 * access. Compute VMIDs should be enabled by FW for target VMIDs,
954 * the driver can enable them for graphics. VMID0 should maintain
955 * access so that HWS firmware can save/restore entries.
957 for (vmid = 1; vmid < AMDGPU_NUM_VMID; vmid++) {
958 WREG32_SOC15_OFFSET(GC, GET_INST(GC, xcc_id), regGDS_VMID0_BASE, 2 * vmid, 0);
959 WREG32_SOC15_OFFSET(GC, GET_INST(GC, xcc_id), regGDS_VMID0_SIZE, 2 * vmid, 0);
960 WREG32_SOC15_OFFSET(GC, GET_INST(GC, xcc_id), regGDS_GWS_VMID0, vmid, 0);
961 WREG32_SOC15_OFFSET(GC, GET_INST(GC, xcc_id), regGDS_OA_VMID0, vmid, 0);
965 static void gfx_v9_4_3_xcc_constants_init(struct amdgpu_device *adev,
971 /* XXX SH_MEM regs */
972 /* where to put LDS, scratch, GPUVM in FSA64 space */
973 mutex_lock(&adev->srbm_mutex);
974 for (i = 0; i < adev->vm_manager.id_mgr[AMDGPU_GFXHUB(0)].num_ids; i++) {
975 soc15_grbm_select(adev, 0, 0, 0, i, GET_INST(GC, xcc_id));
978 tmp = REG_SET_FIELD(0, SH_MEM_CONFIG, ALIGNMENT_MODE,
979 SH_MEM_ALIGNMENT_MODE_UNALIGNED);
980 tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, RETRY_DISABLE,
981 !!adev->gmc.noretry);
982 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id),
983 regSH_MEM_CONFIG, tmp);
984 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id),
987 tmp = REG_SET_FIELD(0, SH_MEM_CONFIG, ALIGNMENT_MODE,
988 SH_MEM_ALIGNMENT_MODE_UNALIGNED);
989 tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, RETRY_DISABLE,
990 !!adev->gmc.noretry);
991 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id),
992 regSH_MEM_CONFIG, tmp);
993 tmp = REG_SET_FIELD(0, SH_MEM_BASES, PRIVATE_BASE,
994 (adev->gmc.private_aperture_start >>
996 tmp = REG_SET_FIELD(tmp, SH_MEM_BASES, SHARED_BASE,
997 (adev->gmc.shared_aperture_start >>
999 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id),
1000 regSH_MEM_BASES, tmp);
1003 soc15_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, 0));
1005 mutex_unlock(&adev->srbm_mutex);
1007 gfx_v9_4_3_xcc_init_compute_vmid(adev, xcc_id);
1008 gfx_v9_4_3_xcc_init_gds_vmid(adev, xcc_id);
1011 static void gfx_v9_4_3_constants_init(struct amdgpu_device *adev)
1015 num_xcc = NUM_XCC(adev->gfx.xcc_mask);
1017 gfx_v9_4_3_get_cu_info(adev, &adev->gfx.cu_info);
1018 adev->gfx.config.db_debug2 =
1019 RREG32_SOC15(GC, GET_INST(GC, 0), regDB_DEBUG2);
1021 for (i = 0; i < num_xcc; i++)
1022 gfx_v9_4_3_xcc_constants_init(adev, i);
1026 gfx_v9_4_3_xcc_enable_save_restore_machine(struct amdgpu_device *adev,
1029 WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), RLC_SRM_CNTL, SRM_ENABLE, 1);
1032 static void gfx_v9_4_3_xcc_init_pg(struct amdgpu_device *adev, int xcc_id)
1035 * Rlc save restore list is workable since v2_1.
1036 * And it's needed by gfxoff feature.
1038 if (adev->gfx.rlc.is_rlc_v2_1)
1039 gfx_v9_4_3_xcc_enable_save_restore_machine(adev, xcc_id);
1042 static void gfx_v9_4_3_xcc_disable_gpa_mode(struct amdgpu_device *adev, int xcc_id)
1046 data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCPC_PSP_DEBUG);
1047 data |= CPC_PSP_DEBUG__UTCL2IUGPAOVERRIDE_MASK;
1048 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCPC_PSP_DEBUG, data);
1051 static bool gfx_v9_4_3_is_rlc_enabled(struct amdgpu_device *adev)
1053 uint32_t rlc_setting;
1055 /* if RLC is not enabled, do nothing */
1056 rlc_setting = RREG32_SOC15(GC, GET_INST(GC, 0), regRLC_CNTL);
1057 if (!(rlc_setting & RLC_CNTL__RLC_ENABLE_F32_MASK))
1063 static void gfx_v9_4_3_xcc_set_safe_mode(struct amdgpu_device *adev, int xcc_id)
1068 data = RLC_SAFE_MODE__CMD_MASK;
1069 data |= (1 << RLC_SAFE_MODE__MESSAGE__SHIFT);
1070 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_SAFE_MODE, data);
1072 /* wait for RLC_SAFE_MODE */
1073 for (i = 0; i < adev->usec_timeout; i++) {
1074 if (!REG_GET_FIELD(RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_SAFE_MODE), RLC_SAFE_MODE, CMD))
1080 static void gfx_v9_4_3_xcc_unset_safe_mode(struct amdgpu_device *adev,
1085 data = RLC_SAFE_MODE__CMD_MASK;
1086 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_SAFE_MODE, data);
1089 static void gfx_v9_4_3_init_rlcg_reg_access_ctrl(struct amdgpu_device *adev)
1091 int xcc_id, num_xcc;
1092 struct amdgpu_rlcg_reg_access_ctrl *reg_access_ctrl;
1094 num_xcc = NUM_XCC(adev->gfx.xcc_mask);
1095 for (xcc_id = 0; xcc_id < num_xcc; xcc_id++) {
1096 reg_access_ctrl = &adev->gfx.rlc.reg_access_ctrl[GET_INST(GC, xcc_id)];
1097 reg_access_ctrl->scratch_reg0 = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regSCRATCH_REG0);
1098 reg_access_ctrl->scratch_reg1 = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regSCRATCH_REG1);
1099 reg_access_ctrl->scratch_reg2 = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regSCRATCH_REG2);
1100 reg_access_ctrl->scratch_reg3 = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regSCRATCH_REG3);
1101 reg_access_ctrl->grbm_cntl = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regGRBM_GFX_CNTL);
1102 reg_access_ctrl->grbm_idx = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regGRBM_GFX_INDEX);
1103 reg_access_ctrl->spare_int = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regRLC_SPARE_INT);
1107 static int gfx_v9_4_3_rlc_init(struct amdgpu_device *adev)
1109 /* init spm vmid with 0xf */
1110 if (adev->gfx.rlc.funcs->update_spm_vmid)
1111 adev->gfx.rlc.funcs->update_spm_vmid(adev, 0xf);
1116 static void gfx_v9_4_3_xcc_wait_for_rlc_serdes(struct amdgpu_device *adev,
1122 mutex_lock(&adev->grbm_idx_mutex);
1123 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
1124 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
1125 gfx_v9_4_3_xcc_select_se_sh(adev, i, j, 0xffffffff,
1127 for (k = 0; k < adev->usec_timeout; k++) {
1128 if (RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_SERDES_CU_MASTER_BUSY) == 0)
1132 if (k == adev->usec_timeout) {
1133 gfx_v9_4_3_xcc_select_se_sh(adev, 0xffffffff,
1135 0xffffffff, xcc_id);
1136 mutex_unlock(&adev->grbm_idx_mutex);
1137 DRM_INFO("Timeout wait for RLC serdes %u,%u\n",
1143 gfx_v9_4_3_xcc_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff,
1145 mutex_unlock(&adev->grbm_idx_mutex);
1147 mask = RLC_SERDES_NONCU_MASTER_BUSY__SE_MASTER_BUSY_MASK |
1148 RLC_SERDES_NONCU_MASTER_BUSY__GC_MASTER_BUSY_MASK |
1149 RLC_SERDES_NONCU_MASTER_BUSY__TC0_MASTER_BUSY_MASK |
1150 RLC_SERDES_NONCU_MASTER_BUSY__TC1_MASTER_BUSY_MASK;
1151 for (k = 0; k < adev->usec_timeout; k++) {
1152 if ((RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_SERDES_NONCU_MASTER_BUSY) & mask) == 0)
1158 static void gfx_v9_4_3_xcc_enable_gui_idle_interrupt(struct amdgpu_device *adev,
1159 bool enable, int xcc_id)
1163 /* These interrupts should be enabled to drive DS clock */
1165 tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_INT_CNTL_RING0);
1167 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE, enable ? 1 : 0);
1168 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE, enable ? 1 : 0);
1169 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE, enable ? 1 : 0);
1171 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_INT_CNTL_RING0, tmp);
1174 static void gfx_v9_4_3_xcc_rlc_stop(struct amdgpu_device *adev, int xcc_id)
1176 WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), RLC_CNTL,
1178 gfx_v9_4_3_xcc_enable_gui_idle_interrupt(adev, false, xcc_id);
1179 gfx_v9_4_3_xcc_wait_for_rlc_serdes(adev, xcc_id);
1182 static void gfx_v9_4_3_rlc_stop(struct amdgpu_device *adev)
1186 num_xcc = NUM_XCC(adev->gfx.xcc_mask);
1187 for (i = 0; i < num_xcc; i++)
1188 gfx_v9_4_3_xcc_rlc_stop(adev, i);
1191 static void gfx_v9_4_3_xcc_rlc_reset(struct amdgpu_device *adev, int xcc_id)
1193 WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), GRBM_SOFT_RESET,
1196 WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), GRBM_SOFT_RESET,
1201 static void gfx_v9_4_3_rlc_reset(struct amdgpu_device *adev)
1205 num_xcc = NUM_XCC(adev->gfx.xcc_mask);
1206 for (i = 0; i < num_xcc; i++)
1207 gfx_v9_4_3_xcc_rlc_reset(adev, i);
1210 static void gfx_v9_4_3_xcc_rlc_start(struct amdgpu_device *adev, int xcc_id)
1212 WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), RLC_CNTL,
1216 /* carrizo do enable cp interrupt after cp inited */
1217 if (!(adev->flags & AMD_IS_APU)) {
1218 gfx_v9_4_3_xcc_enable_gui_idle_interrupt(adev, true, xcc_id);
1223 static void gfx_v9_4_3_rlc_start(struct amdgpu_device *adev)
1225 #ifdef AMDGPU_RLC_DEBUG_RETRY
1230 num_xcc = NUM_XCC(adev->gfx.xcc_mask);
1231 for (i = 0; i < num_xcc; i++) {
1232 gfx_v9_4_3_xcc_rlc_start(adev, i);
1233 #ifdef AMDGPU_RLC_DEBUG_RETRY
1234 /* RLC_GPM_GENERAL_6 : RLC Ucode version */
1235 rlc_ucode_ver = RREG32_SOC15(GC, GET_INST(GC, i), regRLC_GPM_GENERAL_6);
1236 if (rlc_ucode_ver == 0x108) {
1238 "Using rlc debug ucode. regRLC_GPM_GENERAL_6 ==0x08%x / fw_ver == %i \n",
1239 rlc_ucode_ver, adev->gfx.rlc_fw_version);
1240 /* RLC_GPM_TIMER_INT_3 : Timer interval in RefCLK cycles,
1241 * default is 0x9C4 to create a 100us interval */
1242 WREG32_SOC15(GC, GET_INST(GC, i), regRLC_GPM_TIMER_INT_3, 0x9C4);
1243 /* RLC_GPM_GENERAL_12 : Minimum gap between wptr and rptr
1244 * to disable the page fault retry interrupts, default is
1246 WREG32_SOC15(GC, GET_INST(GC, i), regRLC_GPM_GENERAL_12, 0x100);
1252 static int gfx_v9_4_3_xcc_rlc_load_microcode(struct amdgpu_device *adev,
1255 const struct rlc_firmware_header_v2_0 *hdr;
1256 const __le32 *fw_data;
1257 unsigned i, fw_size;
1259 if (!adev->gfx.rlc_fw)
1262 hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data;
1263 amdgpu_ucode_print_rlc_hdr(&hdr->header);
1265 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data +
1266 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
1267 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
1269 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_GPM_UCODE_ADDR,
1270 RLCG_UCODE_LOADING_START_ADDRESS);
1271 for (i = 0; i < fw_size; i++) {
1272 if (amdgpu_emu_mode == 1 && i % 100 == 0) {
1273 dev_info(adev->dev, "Write RLC ucode data %u DWs\n", i);
1276 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_GPM_UCODE_DATA, le32_to_cpup(fw_data++));
1278 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_GPM_UCODE_ADDR, adev->gfx.rlc_fw_version);
1283 static int gfx_v9_4_3_xcc_rlc_resume(struct amdgpu_device *adev, int xcc_id)
1287 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
1288 gfx_v9_4_3_xcc_rlc_stop(adev, xcc_id);
1289 /* legacy rlc firmware loading */
1290 r = gfx_v9_4_3_xcc_rlc_load_microcode(adev, xcc_id);
1293 gfx_v9_4_3_xcc_rlc_start(adev, xcc_id);
1296 amdgpu_gfx_rlc_enter_safe_mode(adev, xcc_id);
1298 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGCG_CGLS_CTRL, 0);
1299 gfx_v9_4_3_xcc_init_pg(adev, xcc_id);
1300 amdgpu_gfx_rlc_exit_safe_mode(adev, xcc_id);
1305 static int gfx_v9_4_3_rlc_resume(struct amdgpu_device *adev)
1309 if (amdgpu_sriov_vf(adev))
1312 num_xcc = NUM_XCC(adev->gfx.xcc_mask);
1313 for (i = 0; i < num_xcc; i++) {
1314 r = gfx_v9_4_3_xcc_rlc_resume(adev, i);
1322 static void gfx_v9_4_3_update_spm_vmid(struct amdgpu_device *adev,
1327 reg = SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regRLC_SPM_MC_CNTL);
1328 if (amdgpu_sriov_is_pp_one_vf(adev))
1329 data = RREG32_NO_KIQ(reg);
1333 data &= ~RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK;
1334 data |= (vmid & RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK) << RLC_SPM_MC_CNTL__RLC_SPM_VMID__SHIFT;
1336 if (amdgpu_sriov_is_pp_one_vf(adev))
1337 WREG32_SOC15_NO_KIQ(GC, GET_INST(GC, 0), regRLC_SPM_MC_CNTL, data);
1339 WREG32_SOC15(GC, GET_INST(GC, 0), regRLC_SPM_MC_CNTL, data);
1342 static const struct soc15_reg_rlcg rlcg_access_gc_9_4_3[] = {
1343 {SOC15_REG_ENTRY(GC, 0, regGRBM_GFX_INDEX)},
1344 {SOC15_REG_ENTRY(GC, 0, regSQ_IND_INDEX)},
1347 static bool gfx_v9_4_3_check_rlcg_range(struct amdgpu_device *adev,
1349 struct soc15_reg_rlcg *entries, int arr_size)
1357 for (i = 0; i < arr_size; i++) {
1358 const struct soc15_reg_rlcg *entry;
1360 entry = &entries[i];
1361 inst = adev->ip_map.logical_to_dev_inst ?
1362 adev->ip_map.logical_to_dev_inst(
1363 adev, entry->hwip, entry->instance) :
1365 reg = adev->reg_offset[entry->hwip][inst][entry->segment] +
1374 static bool gfx_v9_4_3_is_rlcg_access_range(struct amdgpu_device *adev, u32 offset)
1376 return gfx_v9_4_3_check_rlcg_range(adev, offset,
1377 (void *)rlcg_access_gc_9_4_3,
1378 ARRAY_SIZE(rlcg_access_gc_9_4_3));
1381 static void gfx_v9_4_3_xcc_cp_compute_enable(struct amdgpu_device *adev,
1382 bool enable, int xcc_id)
1385 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_MEC_CNTL, 0);
1387 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_MEC_CNTL,
1388 (CP_MEC_CNTL__MEC_ME1_HALT_MASK | CP_MEC_CNTL__MEC_ME2_HALT_MASK));
1389 adev->gfx.kiq[xcc_id].ring.sched.ready = false;
1394 static int gfx_v9_4_3_xcc_cp_compute_load_microcode(struct amdgpu_device *adev,
1397 const struct gfx_firmware_header_v1_0 *mec_hdr;
1398 const __le32 *fw_data;
1401 u32 mec_ucode_addr_offset;
1402 u32 mec_ucode_data_offset;
1404 if (!adev->gfx.mec_fw)
1407 gfx_v9_4_3_xcc_cp_compute_enable(adev, false, xcc_id);
1409 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
1410 amdgpu_ucode_print_gfx_hdr(&mec_hdr->header);
1412 fw_data = (const __le32 *)
1413 (adev->gfx.mec_fw->data +
1414 le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes));
1416 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, VMID, 0);
1417 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0);
1418 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_CPC_IC_BASE_CNTL, tmp);
1420 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_CPC_IC_BASE_LO,
1421 adev->gfx.mec.mec_fw_gpu_addr & 0xFFFFF000);
1422 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_CPC_IC_BASE_HI,
1423 upper_32_bits(adev->gfx.mec.mec_fw_gpu_addr));
1425 mec_ucode_addr_offset =
1426 SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regCP_MEC_ME1_UCODE_ADDR);
1427 mec_ucode_data_offset =
1428 SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regCP_MEC_ME1_UCODE_DATA);
1431 WREG32(mec_ucode_addr_offset, mec_hdr->jt_offset);
1432 for (i = 0; i < mec_hdr->jt_size; i++)
1433 WREG32(mec_ucode_data_offset,
1434 le32_to_cpup(fw_data + mec_hdr->jt_offset + i));
1436 WREG32(mec_ucode_addr_offset, adev->gfx.mec_fw_version);
1437 /* Todo : Loading MEC2 firmware is only necessary if MEC2 should run different microcode than MEC1. */
1443 static void gfx_v9_4_3_xcc_kiq_setting(struct amdgpu_ring *ring, int xcc_id)
1446 struct amdgpu_device *adev = ring->adev;
1448 /* tell RLC which is KIQ queue */
1449 tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CP_SCHEDULERS);
1451 tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue);
1452 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regRLC_CP_SCHEDULERS, tmp);
1454 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regRLC_CP_SCHEDULERS, tmp);
1457 static void gfx_v9_4_3_mqd_set_priority(struct amdgpu_ring *ring, struct v9_mqd *mqd)
1459 struct amdgpu_device *adev = ring->adev;
1461 if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) {
1462 if (amdgpu_gfx_is_high_priority_compute_queue(adev, ring)) {
1463 mqd->cp_hqd_pipe_priority = AMDGPU_GFX_PIPE_PRIO_HIGH;
1464 mqd->cp_hqd_queue_priority =
1465 AMDGPU_GFX_QUEUE_PRIORITY_MAXIMUM;
1470 static int gfx_v9_4_3_xcc_mqd_init(struct amdgpu_ring *ring, int xcc_id)
1472 struct amdgpu_device *adev = ring->adev;
1473 struct v9_mqd *mqd = ring->mqd_ptr;
1474 uint64_t hqd_gpu_addr, wb_gpu_addr, eop_base_addr;
1477 mqd->header = 0xC0310800;
1478 mqd->compute_pipelinestat_enable = 0x00000001;
1479 mqd->compute_static_thread_mgmt_se0 = 0xffffffff;
1480 mqd->compute_static_thread_mgmt_se1 = 0xffffffff;
1481 mqd->compute_static_thread_mgmt_se2 = 0xffffffff;
1482 mqd->compute_static_thread_mgmt_se3 = 0xffffffff;
1483 mqd->compute_misc_reserved = 0x00000003;
1485 mqd->dynamic_cu_mask_addr_lo =
1486 lower_32_bits(ring->mqd_gpu_addr
1487 + offsetof(struct v9_mqd_allocation, dynamic_cu_mask));
1488 mqd->dynamic_cu_mask_addr_hi =
1489 upper_32_bits(ring->mqd_gpu_addr
1490 + offsetof(struct v9_mqd_allocation, dynamic_cu_mask));
1492 eop_base_addr = ring->eop_gpu_addr >> 8;
1493 mqd->cp_hqd_eop_base_addr_lo = eop_base_addr;
1494 mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr);
1496 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */
1497 tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_EOP_CONTROL);
1498 tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE,
1499 (order_base_2(GFX9_MEC_HPD_SIZE / 4) - 1));
1501 mqd->cp_hqd_eop_control = tmp;
1503 /* enable doorbell? */
1504 tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_DOORBELL_CONTROL);
1506 if (ring->use_doorbell) {
1507 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
1508 DOORBELL_OFFSET, ring->doorbell_index);
1509 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
1511 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
1512 DOORBELL_SOURCE, 0);
1513 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
1516 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
1520 mqd->cp_hqd_pq_doorbell_control = tmp;
1522 /* disable the queue if it's active */
1524 mqd->cp_hqd_dequeue_request = 0;
1525 mqd->cp_hqd_pq_rptr = 0;
1526 mqd->cp_hqd_pq_wptr_lo = 0;
1527 mqd->cp_hqd_pq_wptr_hi = 0;
1529 /* set the pointer to the MQD */
1530 mqd->cp_mqd_base_addr_lo = ring->mqd_gpu_addr & 0xfffffffc;
1531 mqd->cp_mqd_base_addr_hi = upper_32_bits(ring->mqd_gpu_addr);
1533 /* set MQD vmid to 0 */
1534 tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MQD_CONTROL);
1535 tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0);
1536 mqd->cp_mqd_control = tmp;
1538 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */
1539 hqd_gpu_addr = ring->gpu_addr >> 8;
1540 mqd->cp_hqd_pq_base_lo = hqd_gpu_addr;
1541 mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr);
1543 /* set up the HQD, this is similar to CP_RB0_CNTL */
1544 tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_CONTROL);
1545 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE,
1546 (order_base_2(ring->ring_size / 4) - 1));
1547 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE,
1548 ((order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1) << 8));
1550 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ENDIAN_SWAP, 1);
1552 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 0);
1553 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ROQ_PQ_IB_FLIP, 0);
1554 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1);
1555 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1);
1556 mqd->cp_hqd_pq_control = tmp;
1558 /* set the wb address whether it's enabled or not */
1559 wb_gpu_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
1560 mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc;
1561 mqd->cp_hqd_pq_rptr_report_addr_hi =
1562 upper_32_bits(wb_gpu_addr) & 0xffff;
1564 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */
1565 wb_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
1566 mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc;
1567 mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff;
1569 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */
1571 mqd->cp_hqd_pq_rptr = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_RPTR);
1573 /* set the vmid for the queue */
1574 mqd->cp_hqd_vmid = 0;
1576 tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PERSISTENT_STATE);
1577 tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, PRELOAD_SIZE, 0x53);
1578 mqd->cp_hqd_persistent_state = tmp;
1580 /* set MIN_IB_AVAIL_SIZE */
1581 tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_IB_CONTROL);
1582 tmp = REG_SET_FIELD(tmp, CP_HQD_IB_CONTROL, MIN_IB_AVAIL_SIZE, 3);
1583 mqd->cp_hqd_ib_control = tmp;
1585 /* set static priority for a queue/ring */
1586 gfx_v9_4_3_mqd_set_priority(ring, mqd);
1587 mqd->cp_hqd_quantum = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_QUANTUM);
1589 /* map_queues packet doesn't need activate the queue,
1590 * so only kiq need set this field.
1592 if (ring->funcs->type == AMDGPU_RING_TYPE_KIQ)
1593 mqd->cp_hqd_active = 1;
1598 static int gfx_v9_4_3_xcc_kiq_init_register(struct amdgpu_ring *ring,
1601 struct amdgpu_device *adev = ring->adev;
1602 struct v9_mqd *mqd = ring->mqd_ptr;
1605 /* disable wptr polling */
1606 WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), CP_PQ_WPTR_POLL_CNTL, EN, 0);
1608 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_EOP_BASE_ADDR,
1609 mqd->cp_hqd_eop_base_addr_lo);
1610 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_EOP_BASE_ADDR_HI,
1611 mqd->cp_hqd_eop_base_addr_hi);
1613 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */
1614 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_EOP_CONTROL,
1615 mqd->cp_hqd_eop_control);
1617 /* enable doorbell? */
1618 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_DOORBELL_CONTROL,
1619 mqd->cp_hqd_pq_doorbell_control);
1621 /* disable the queue if it's active */
1622 if (RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_ACTIVE) & 1) {
1623 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_DEQUEUE_REQUEST, 1);
1624 for (j = 0; j < adev->usec_timeout; j++) {
1625 if (!(RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_ACTIVE) & 1))
1629 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_DEQUEUE_REQUEST,
1630 mqd->cp_hqd_dequeue_request);
1631 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_RPTR,
1632 mqd->cp_hqd_pq_rptr);
1633 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_LO,
1634 mqd->cp_hqd_pq_wptr_lo);
1635 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_HI,
1636 mqd->cp_hqd_pq_wptr_hi);
1639 /* set the pointer to the MQD */
1640 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_MQD_BASE_ADDR,
1641 mqd->cp_mqd_base_addr_lo);
1642 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_MQD_BASE_ADDR_HI,
1643 mqd->cp_mqd_base_addr_hi);
1645 /* set MQD vmid to 0 */
1646 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_MQD_CONTROL,
1647 mqd->cp_mqd_control);
1649 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */
1650 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_BASE,
1651 mqd->cp_hqd_pq_base_lo);
1652 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_BASE_HI,
1653 mqd->cp_hqd_pq_base_hi);
1655 /* set up the HQD, this is similar to CP_RB0_CNTL */
1656 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_CONTROL,
1657 mqd->cp_hqd_pq_control);
1659 /* set the wb address whether it's enabled or not */
1660 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_RPTR_REPORT_ADDR,
1661 mqd->cp_hqd_pq_rptr_report_addr_lo);
1662 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_RPTR_REPORT_ADDR_HI,
1663 mqd->cp_hqd_pq_rptr_report_addr_hi);
1665 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */
1666 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_POLL_ADDR,
1667 mqd->cp_hqd_pq_wptr_poll_addr_lo);
1668 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_POLL_ADDR_HI,
1669 mqd->cp_hqd_pq_wptr_poll_addr_hi);
1671 /* enable the doorbell if requested */
1672 if (ring->use_doorbell) {
1674 GC, GET_INST(GC, xcc_id),
1675 regCP_MEC_DOORBELL_RANGE_LOWER,
1676 ((adev->doorbell_index.kiq +
1677 xcc_id * adev->doorbell_index.xcc_doorbell_range) *
1680 GC, GET_INST(GC, xcc_id),
1681 regCP_MEC_DOORBELL_RANGE_UPPER,
1682 ((adev->doorbell_index.userqueue_end +
1683 xcc_id * adev->doorbell_index.xcc_doorbell_range) *
1687 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_DOORBELL_CONTROL,
1688 mqd->cp_hqd_pq_doorbell_control);
1690 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */
1691 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_LO,
1692 mqd->cp_hqd_pq_wptr_lo);
1693 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_HI,
1694 mqd->cp_hqd_pq_wptr_hi);
1696 /* set the vmid for the queue */
1697 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_VMID, mqd->cp_hqd_vmid);
1699 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PERSISTENT_STATE,
1700 mqd->cp_hqd_persistent_state);
1702 /* activate the queue */
1703 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_ACTIVE,
1704 mqd->cp_hqd_active);
1706 if (ring->use_doorbell)
1707 WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), CP_PQ_STATUS, DOORBELL_ENABLE, 1);
1712 static int gfx_v9_4_3_xcc_q_fini_register(struct amdgpu_ring *ring,
1715 struct amdgpu_device *adev = ring->adev;
1718 /* disable the queue if it's active */
1719 if (RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_ACTIVE) & 1) {
1721 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_DEQUEUE_REQUEST, 1);
1723 for (j = 0; j < adev->usec_timeout; j++) {
1724 if (!(RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_ACTIVE) & 1))
1729 if (j == AMDGPU_MAX_USEC_TIMEOUT) {
1730 DRM_DEBUG("%s dequeue request failed.\n", ring->name);
1732 /* Manual disable if dequeue request times out */
1733 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_ACTIVE, 0);
1736 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_DEQUEUE_REQUEST,
1740 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_IQ_TIMER, 0);
1741 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_IB_CONTROL, 0);
1742 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PERSISTENT_STATE, CP_HQD_PERSISTENT_STATE_DEFAULT);
1743 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_DOORBELL_CONTROL, 0x40000000);
1744 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_DOORBELL_CONTROL, 0);
1745 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_RPTR, 0);
1746 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_HI, 0);
1747 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_LO, 0);
1752 static int gfx_v9_4_3_xcc_kiq_init_queue(struct amdgpu_ring *ring, int xcc_id)
1754 struct amdgpu_device *adev = ring->adev;
1755 struct v9_mqd *mqd = ring->mqd_ptr;
1756 struct v9_mqd *tmp_mqd;
1758 gfx_v9_4_3_xcc_kiq_setting(ring, xcc_id);
1760 /* GPU could be in bad state during probe, driver trigger the reset
1761 * after load the SMU, in this case , the mqd is not be initialized.
1762 * driver need to re-init the mqd.
1763 * check mqd->cp_hqd_pq_control since this value should not be 0
1765 tmp_mqd = (struct v9_mqd *)adev->gfx.kiq[xcc_id].mqd_backup;
1766 if (amdgpu_in_reset(adev) && tmp_mqd->cp_hqd_pq_control) {
1767 /* for GPU_RESET case , reset MQD to a clean status */
1768 if (adev->gfx.kiq[xcc_id].mqd_backup)
1769 memcpy(mqd, adev->gfx.kiq[xcc_id].mqd_backup, sizeof(struct v9_mqd_allocation));
1771 /* reset ring buffer */
1773 amdgpu_ring_clear_ring(ring);
1774 mutex_lock(&adev->srbm_mutex);
1775 soc15_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0, GET_INST(GC, xcc_id));
1776 gfx_v9_4_3_xcc_kiq_init_register(ring, xcc_id);
1777 soc15_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id));
1778 mutex_unlock(&adev->srbm_mutex);
1780 memset((void *)mqd, 0, sizeof(struct v9_mqd_allocation));
1781 ((struct v9_mqd_allocation *)mqd)->dynamic_cu_mask = 0xFFFFFFFF;
1782 ((struct v9_mqd_allocation *)mqd)->dynamic_rb_mask = 0xFFFFFFFF;
1783 mutex_lock(&adev->srbm_mutex);
1784 if (amdgpu_sriov_vf(adev) && adev->in_suspend)
1785 amdgpu_ring_clear_ring(ring);
1786 soc15_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0, GET_INST(GC, xcc_id));
1787 gfx_v9_4_3_xcc_mqd_init(ring, xcc_id);
1788 gfx_v9_4_3_xcc_kiq_init_register(ring, xcc_id);
1789 soc15_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id));
1790 mutex_unlock(&adev->srbm_mutex);
1792 if (adev->gfx.kiq[xcc_id].mqd_backup)
1793 memcpy(adev->gfx.kiq[xcc_id].mqd_backup, mqd, sizeof(struct v9_mqd_allocation));
1799 static int gfx_v9_4_3_xcc_kcq_init_queue(struct amdgpu_ring *ring, int xcc_id)
1801 struct amdgpu_device *adev = ring->adev;
1802 struct v9_mqd *mqd = ring->mqd_ptr;
1803 int mqd_idx = ring - &adev->gfx.compute_ring[0];
1804 struct v9_mqd *tmp_mqd;
1806 /* Same as above kiq init, driver need to re-init the mqd if mqd->cp_hqd_pq_control
1807 * is not be initialized before
1809 tmp_mqd = (struct v9_mqd *)adev->gfx.mec.mqd_backup[mqd_idx];
1811 if (!tmp_mqd->cp_hqd_pq_control ||
1812 (!amdgpu_in_reset(adev) && !adev->in_suspend)) {
1813 memset((void *)mqd, 0, sizeof(struct v9_mqd_allocation));
1814 ((struct v9_mqd_allocation *)mqd)->dynamic_cu_mask = 0xFFFFFFFF;
1815 ((struct v9_mqd_allocation *)mqd)->dynamic_rb_mask = 0xFFFFFFFF;
1816 mutex_lock(&adev->srbm_mutex);
1817 soc15_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0, GET_INST(GC, xcc_id));
1818 gfx_v9_4_3_xcc_mqd_init(ring, xcc_id);
1819 soc15_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id));
1820 mutex_unlock(&adev->srbm_mutex);
1822 if (adev->gfx.mec.mqd_backup[mqd_idx])
1823 memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(struct v9_mqd_allocation));
1825 /* restore MQD to a clean status */
1826 if (adev->gfx.mec.mqd_backup[mqd_idx])
1827 memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(struct v9_mqd_allocation));
1828 /* reset ring buffer */
1830 atomic64_set((atomic64_t *)&adev->wb.wb[ring->wptr_offs], 0);
1831 amdgpu_ring_clear_ring(ring);
1837 static int gfx_v9_4_3_xcc_kcq_fini_register(struct amdgpu_device *adev, int xcc_id)
1839 struct amdgpu_ring *ring;
1842 for (j = 0; j < adev->gfx.num_compute_rings; j++) {
1843 ring = &adev->gfx.compute_ring[j + xcc_id * adev->gfx.num_compute_rings];
1844 if (!amdgpu_in_reset(adev) && !adev->in_suspend) {
1845 mutex_lock(&adev->srbm_mutex);
1846 soc15_grbm_select(adev, ring->me,
1848 ring->queue, 0, GET_INST(GC, xcc_id));
1849 gfx_v9_4_3_xcc_q_fini_register(ring, xcc_id);
1850 soc15_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id));
1851 mutex_unlock(&adev->srbm_mutex);
1858 static int gfx_v9_4_3_xcc_kiq_resume(struct amdgpu_device *adev, int xcc_id)
1860 struct amdgpu_ring *ring;
1863 ring = &adev->gfx.kiq[xcc_id].ring;
1865 r = amdgpu_bo_reserve(ring->mqd_obj, false);
1866 if (unlikely(r != 0))
1869 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr);
1870 if (unlikely(r != 0)) {
1871 amdgpu_bo_unreserve(ring->mqd_obj);
1875 gfx_v9_4_3_xcc_kiq_init_queue(ring, xcc_id);
1876 amdgpu_bo_kunmap(ring->mqd_obj);
1877 ring->mqd_ptr = NULL;
1878 amdgpu_bo_unreserve(ring->mqd_obj);
1882 static int gfx_v9_4_3_xcc_kcq_resume(struct amdgpu_device *adev, int xcc_id)
1884 struct amdgpu_ring *ring = NULL;
1887 gfx_v9_4_3_xcc_cp_compute_enable(adev, true, xcc_id);
1889 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
1890 ring = &adev->gfx.compute_ring[i + xcc_id * adev->gfx.num_compute_rings];
1892 r = amdgpu_bo_reserve(ring->mqd_obj, false);
1893 if (unlikely(r != 0))
1895 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr);
1897 r = gfx_v9_4_3_xcc_kcq_init_queue(ring, xcc_id);
1898 amdgpu_bo_kunmap(ring->mqd_obj);
1899 ring->mqd_ptr = NULL;
1901 amdgpu_bo_unreserve(ring->mqd_obj);
1906 r = amdgpu_gfx_enable_kcq(adev, xcc_id);
1911 static int gfx_v9_4_3_xcc_cp_resume(struct amdgpu_device *adev, int xcc_id)
1913 struct amdgpu_ring *ring;
1916 gfx_v9_4_3_xcc_enable_gui_idle_interrupt(adev, false, xcc_id);
1918 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
1919 gfx_v9_4_3_xcc_disable_gpa_mode(adev, xcc_id);
1921 r = gfx_v9_4_3_xcc_cp_compute_load_microcode(adev, xcc_id);
1926 r = gfx_v9_4_3_xcc_kiq_resume(adev, xcc_id);
1930 r = gfx_v9_4_3_xcc_kcq_resume(adev, xcc_id);
1934 for (j = 0; j < adev->gfx.num_compute_rings; j++) {
1935 ring = &adev->gfx.compute_ring
1936 [j + xcc_id * adev->gfx.num_compute_rings];
1937 r = amdgpu_ring_test_helper(ring);
1942 gfx_v9_4_3_xcc_enable_gui_idle_interrupt(adev, true, xcc_id);
1947 static int gfx_v9_4_3_cp_resume(struct amdgpu_device *adev)
1949 int r = 0, i, num_xcc;
1951 if (amdgpu_xcp_query_partition_mode(adev->xcp_mgr,
1952 AMDGPU_XCP_FL_NONE) ==
1953 AMDGPU_UNKNOWN_COMPUTE_PARTITION_MODE)
1954 r = amdgpu_xcp_switch_partition_mode(adev->xcp_mgr,
1955 amdgpu_user_partt_mode);
1960 num_xcc = NUM_XCC(adev->gfx.xcc_mask);
1961 for (i = 0; i < num_xcc; i++) {
1962 r = gfx_v9_4_3_xcc_cp_resume(adev, i);
1970 static void gfx_v9_4_3_xcc_cp_enable(struct amdgpu_device *adev, bool enable,
1973 gfx_v9_4_3_xcc_cp_compute_enable(adev, enable, xcc_id);
1976 static void gfx_v9_4_3_xcc_fini(struct amdgpu_device *adev, int xcc_id)
1978 if (amdgpu_gfx_disable_kcq(adev, xcc_id))
1979 DRM_ERROR("XCD %d KCQ disable failed\n", xcc_id);
1981 if (amdgpu_sriov_vf(adev)) {
1982 /* must disable polling for SRIOV when hw finished, otherwise
1983 * CPC engine may still keep fetching WB address which is already
1984 * invalid after sw finished and trigger DMAR reading error in
1987 WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), CP_PQ_WPTR_POLL_CNTL, EN, 0);
1991 /* Use deinitialize sequence from CAIL when unbinding device
1992 * from driver, otherwise KIQ is hanging when binding back
1994 if (!amdgpu_in_reset(adev) && !adev->in_suspend) {
1995 mutex_lock(&adev->srbm_mutex);
1996 soc15_grbm_select(adev, adev->gfx.kiq[xcc_id].ring.me,
1997 adev->gfx.kiq[xcc_id].ring.pipe,
1998 adev->gfx.kiq[xcc_id].ring.queue, 0,
1999 GET_INST(GC, xcc_id));
2000 gfx_v9_4_3_xcc_q_fini_register(&adev->gfx.kiq[xcc_id].ring,
2002 soc15_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id));
2003 mutex_unlock(&adev->srbm_mutex);
2006 gfx_v9_4_3_xcc_kcq_fini_register(adev, xcc_id);
2007 gfx_v9_4_3_xcc_cp_enable(adev, false, xcc_id);
2010 static int gfx_v9_4_3_hw_init(void *handle)
2013 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2015 if (!amdgpu_sriov_vf(adev))
2016 gfx_v9_4_3_init_golden_registers(adev);
2018 gfx_v9_4_3_constants_init(adev);
2020 r = adev->gfx.rlc.funcs->resume(adev);
2024 r = gfx_v9_4_3_cp_resume(adev);
2031 static int gfx_v9_4_3_hw_fini(void *handle)
2033 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2036 amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0);
2037 amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0);
2039 num_xcc = NUM_XCC(adev->gfx.xcc_mask);
2040 for (i = 0; i < num_xcc; i++) {
2041 gfx_v9_4_3_xcc_fini(adev, i);
2047 static int gfx_v9_4_3_suspend(void *handle)
2049 return gfx_v9_4_3_hw_fini(handle);
2052 static int gfx_v9_4_3_resume(void *handle)
2054 return gfx_v9_4_3_hw_init(handle);
2057 static bool gfx_v9_4_3_is_idle(void *handle)
2059 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2062 num_xcc = NUM_XCC(adev->gfx.xcc_mask);
2063 for (i = 0; i < num_xcc; i++) {
2064 if (REG_GET_FIELD(RREG32_SOC15(GC, GET_INST(GC, i), regGRBM_STATUS),
2065 GRBM_STATUS, GUI_ACTIVE))
2071 static int gfx_v9_4_3_wait_for_idle(void *handle)
2074 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2076 for (i = 0; i < adev->usec_timeout; i++) {
2077 if (gfx_v9_4_3_is_idle(handle))
2084 static int gfx_v9_4_3_soft_reset(void *handle)
2086 u32 grbm_soft_reset = 0;
2088 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2091 tmp = RREG32_SOC15(GC, GET_INST(GC, 0), regGRBM_STATUS);
2092 if (tmp & (GRBM_STATUS__PA_BUSY_MASK | GRBM_STATUS__SC_BUSY_MASK |
2093 GRBM_STATUS__BCI_BUSY_MASK | GRBM_STATUS__SX_BUSY_MASK |
2094 GRBM_STATUS__TA_BUSY_MASK | GRBM_STATUS__VGT_BUSY_MASK |
2095 GRBM_STATUS__DB_BUSY_MASK | GRBM_STATUS__CB_BUSY_MASK |
2096 GRBM_STATUS__GDS_BUSY_MASK | GRBM_STATUS__SPI_BUSY_MASK |
2097 GRBM_STATUS__IA_BUSY_MASK | GRBM_STATUS__IA_BUSY_NO_DMA_MASK)) {
2098 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
2099 GRBM_SOFT_RESET, SOFT_RESET_CP, 1);
2100 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
2101 GRBM_SOFT_RESET, SOFT_RESET_GFX, 1);
2104 if (tmp & (GRBM_STATUS__CP_BUSY_MASK | GRBM_STATUS__CP_COHERENCY_BUSY_MASK)) {
2105 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
2106 GRBM_SOFT_RESET, SOFT_RESET_CP, 1);
2110 tmp = RREG32_SOC15(GC, GET_INST(GC, 0), regGRBM_STATUS2);
2111 if (REG_GET_FIELD(tmp, GRBM_STATUS2, RLC_BUSY))
2112 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
2113 GRBM_SOFT_RESET, SOFT_RESET_RLC, 1);
2116 if (grbm_soft_reset) {
2118 adev->gfx.rlc.funcs->stop(adev);
2120 /* Disable MEC parsing/prefetching */
2121 gfx_v9_4_3_xcc_cp_compute_enable(adev, false, 0);
2123 if (grbm_soft_reset) {
2124 tmp = RREG32_SOC15(GC, GET_INST(GC, 0), regGRBM_SOFT_RESET);
2125 tmp |= grbm_soft_reset;
2126 dev_info(adev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp);
2127 WREG32_SOC15(GC, GET_INST(GC, 0), regGRBM_SOFT_RESET, tmp);
2128 tmp = RREG32_SOC15(GC, GET_INST(GC, 0), regGRBM_SOFT_RESET);
2132 tmp &= ~grbm_soft_reset;
2133 WREG32_SOC15(GC, GET_INST(GC, 0), regGRBM_SOFT_RESET, tmp);
2134 tmp = RREG32_SOC15(GC, GET_INST(GC, 0), regGRBM_SOFT_RESET);
2137 /* Wait a little for things to settle down */
2143 static void gfx_v9_4_3_ring_emit_gds_switch(struct amdgpu_ring *ring,
2145 uint32_t gds_base, uint32_t gds_size,
2146 uint32_t gws_base, uint32_t gws_size,
2147 uint32_t oa_base, uint32_t oa_size)
2149 struct amdgpu_device *adev = ring->adev;
2152 gfx_v9_4_3_write_data_to_reg(ring, 0, false,
2153 SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regGDS_VMID0_BASE) + 2 * vmid,
2157 gfx_v9_4_3_write_data_to_reg(ring, 0, false,
2158 SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regGDS_VMID0_SIZE) + 2 * vmid,
2162 gfx_v9_4_3_write_data_to_reg(ring, 0, false,
2163 SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regGDS_GWS_VMID0) + vmid,
2164 gws_size << GDS_GWS_VMID0__SIZE__SHIFT | gws_base);
2167 gfx_v9_4_3_write_data_to_reg(ring, 0, false,
2168 SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regGDS_OA_VMID0) + vmid,
2169 (1 << (oa_size + oa_base)) - (1 << oa_base));
2172 static int gfx_v9_4_3_early_init(void *handle)
2174 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2176 adev->gfx.num_compute_rings = min(amdgpu_gfx_get_num_kcq(adev),
2177 AMDGPU_MAX_COMPUTE_RINGS);
2178 gfx_v9_4_3_set_kiq_pm4_funcs(adev);
2179 gfx_v9_4_3_set_ring_funcs(adev);
2180 gfx_v9_4_3_set_irq_funcs(adev);
2181 gfx_v9_4_3_set_gds_init(adev);
2182 gfx_v9_4_3_set_rlc_funcs(adev);
2184 /* init rlcg reg access ctrl */
2185 gfx_v9_4_3_init_rlcg_reg_access_ctrl(adev);
2187 return gfx_v9_4_3_init_microcode(adev);
2190 static int gfx_v9_4_3_late_init(void *handle)
2192 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2195 r = amdgpu_irq_get(adev, &adev->gfx.priv_reg_irq, 0);
2199 r = amdgpu_irq_get(adev, &adev->gfx.priv_inst_irq, 0);
2203 if (adev->gfx.ras &&
2204 adev->gfx.ras->enable_watchdog_timer)
2205 adev->gfx.ras->enable_watchdog_timer(adev);
2210 static void gfx_v9_4_3_xcc_update_sram_fgcg(struct amdgpu_device *adev,
2211 bool enable, int xcc_id)
2215 if (!(adev->cg_flags & AMD_CG_SUPPORT_GFX_FGCG))
2218 def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id),
2219 regRLC_CGTT_MGCG_OVERRIDE);
2222 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK;
2224 data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK;
2227 WREG32_SOC15(GC, GET_INST(GC, xcc_id),
2228 regRLC_CGTT_MGCG_OVERRIDE, data);
2232 static void gfx_v9_4_3_xcc_update_repeater_fgcg(struct amdgpu_device *adev,
2233 bool enable, int xcc_id)
2237 if (!(adev->cg_flags & AMD_CG_SUPPORT_REPEATER_FGCG))
2240 def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id),
2241 regRLC_CGTT_MGCG_OVERRIDE);
2244 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_REP_FGCG_OVERRIDE_MASK;
2246 data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_REP_FGCG_OVERRIDE_MASK;
2249 WREG32_SOC15(GC, GET_INST(GC, xcc_id),
2250 regRLC_CGTT_MGCG_OVERRIDE, data);
2254 gfx_v9_4_3_xcc_update_medium_grain_clock_gating(struct amdgpu_device *adev,
2255 bool enable, int xcc_id)
2259 /* It is disabled by HW by default */
2260 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) {
2261 /* 1 - RLC_CGTT_MGCG_OVERRIDE */
2262 def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGTT_MGCG_OVERRIDE);
2264 data &= ~(RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK |
2265 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK |
2266 RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK |
2267 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK);
2270 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGTT_MGCG_OVERRIDE, data);
2272 /* MGLS is a global flag to control all MGLS in GFX */
2273 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGLS) {
2274 /* 2 - RLC memory Light sleep */
2275 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_RLC_LS) {
2276 def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_MEM_SLP_CNTL);
2277 data |= RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK;
2279 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_MEM_SLP_CNTL, data);
2281 /* 3 - CP memory Light sleep */
2282 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CP_LS) {
2283 def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MEM_SLP_CNTL);
2284 data |= CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK;
2286 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MEM_SLP_CNTL, data);
2290 /* 1 - MGCG_OVERRIDE */
2291 def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGTT_MGCG_OVERRIDE);
2293 data |= (RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK |
2294 RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK |
2295 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK |
2296 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK);
2299 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGTT_MGCG_OVERRIDE, data);
2301 /* 2 - disable MGLS in RLC */
2302 data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_MEM_SLP_CNTL);
2303 if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK) {
2304 data &= ~RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK;
2305 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_MEM_SLP_CNTL, data);
2308 /* 3 - disable MGLS in CP */
2309 data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MEM_SLP_CNTL);
2310 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) {
2311 data &= ~CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK;
2312 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MEM_SLP_CNTL, data);
2319 gfx_v9_4_3_xcc_update_coarse_grain_clock_gating(struct amdgpu_device *adev,
2320 bool enable, int xcc_id)
2324 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)) {
2326 def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGTT_MGCG_OVERRIDE);
2327 /* unset CGCG override */
2328 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGCG_OVERRIDE_MASK;
2329 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS)
2330 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK;
2332 data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK;
2333 /* update CGCG and CGLS override bits */
2335 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGTT_MGCG_OVERRIDE, data);
2337 /* enable cgcg FSM(0x0000363F) */
2338 def = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGCG_CGLS_CTRL);
2341 << RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT) |
2342 RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK;
2343 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS)
2344 data |= (0x000F << RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY__SHIFT) |
2345 RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK;
2347 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGCG_CGLS_CTRL, data);
2349 /* set IDLE_POLL_COUNT(0x00900100) */
2350 def = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_RB_WPTR_POLL_CNTL);
2351 data = (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) |
2352 (0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT);
2354 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_RB_WPTR_POLL_CNTL, data);
2356 def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGCG_CGLS_CTRL);
2357 /* reset CGCG/CGLS bits */
2358 data &= ~(RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK | RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK);
2359 /* disable cgcg and cgls in FSM */
2361 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGCG_CGLS_CTRL, data);
2366 static int gfx_v9_4_3_xcc_update_gfx_clock_gating(struct amdgpu_device *adev,
2367 bool enable, int xcc_id)
2369 amdgpu_gfx_rlc_enter_safe_mode(adev, xcc_id);
2373 gfx_v9_4_3_xcc_update_sram_fgcg(adev, enable, xcc_id);
2374 gfx_v9_4_3_xcc_update_repeater_fgcg(adev, enable, xcc_id);
2376 /* CGCG/CGLS should be enabled after MGCG/MGLS
2377 * === MGCG + MGLS ===
2379 gfx_v9_4_3_xcc_update_medium_grain_clock_gating(adev, enable,
2381 /* === CGCG + CGLS === */
2382 gfx_v9_4_3_xcc_update_coarse_grain_clock_gating(adev, enable,
2385 /* CGCG/CGLS should be disabled before MGCG/MGLS
2386 * === CGCG + CGLS ===
2388 gfx_v9_4_3_xcc_update_coarse_grain_clock_gating(adev, enable,
2390 /* === MGCG + MGLS === */
2391 gfx_v9_4_3_xcc_update_medium_grain_clock_gating(adev, enable,
2395 gfx_v9_4_3_xcc_update_sram_fgcg(adev, enable, xcc_id);
2396 gfx_v9_4_3_xcc_update_repeater_fgcg(adev, enable, xcc_id);
2399 amdgpu_gfx_rlc_exit_safe_mode(adev, xcc_id);
2404 static const struct amdgpu_rlc_funcs gfx_v9_4_3_rlc_funcs = {
2405 .is_rlc_enabled = gfx_v9_4_3_is_rlc_enabled,
2406 .set_safe_mode = gfx_v9_4_3_xcc_set_safe_mode,
2407 .unset_safe_mode = gfx_v9_4_3_xcc_unset_safe_mode,
2408 .init = gfx_v9_4_3_rlc_init,
2409 .resume = gfx_v9_4_3_rlc_resume,
2410 .stop = gfx_v9_4_3_rlc_stop,
2411 .reset = gfx_v9_4_3_rlc_reset,
2412 .start = gfx_v9_4_3_rlc_start,
2413 .update_spm_vmid = gfx_v9_4_3_update_spm_vmid,
2414 .is_rlcg_access_range = gfx_v9_4_3_is_rlcg_access_range,
2417 static int gfx_v9_4_3_set_powergating_state(void *handle,
2418 enum amd_powergating_state state)
2423 static int gfx_v9_4_3_set_clockgating_state(void *handle,
2424 enum amd_clockgating_state state)
2426 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2429 if (amdgpu_sriov_vf(adev))
2432 num_xcc = NUM_XCC(adev->gfx.xcc_mask);
2433 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
2434 case IP_VERSION(9, 4, 3):
2435 for (i = 0; i < num_xcc; i++)
2436 gfx_v9_4_3_xcc_update_gfx_clock_gating(
2437 adev, state == AMD_CG_STATE_GATE, i);
2445 static void gfx_v9_4_3_get_clockgating_state(void *handle, u64 *flags)
2447 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2450 if (amdgpu_sriov_vf(adev))
2453 /* AMD_CG_SUPPORT_GFX_MGCG */
2454 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regRLC_CGTT_MGCG_OVERRIDE));
2455 if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK))
2456 *flags |= AMD_CG_SUPPORT_GFX_MGCG;
2458 /* AMD_CG_SUPPORT_GFX_CGCG */
2459 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regRLC_CGCG_CGLS_CTRL));
2460 if (data & RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK)
2461 *flags |= AMD_CG_SUPPORT_GFX_CGCG;
2463 /* AMD_CG_SUPPORT_GFX_CGLS */
2464 if (data & RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK)
2465 *flags |= AMD_CG_SUPPORT_GFX_CGLS;
2467 /* AMD_CG_SUPPORT_GFX_RLC_LS */
2468 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regRLC_MEM_SLP_CNTL));
2469 if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK)
2470 *flags |= AMD_CG_SUPPORT_GFX_RLC_LS | AMD_CG_SUPPORT_GFX_MGLS;
2472 /* AMD_CG_SUPPORT_GFX_CP_LS */
2473 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regCP_MEM_SLP_CNTL));
2474 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK)
2475 *flags |= AMD_CG_SUPPORT_GFX_CP_LS | AMD_CG_SUPPORT_GFX_MGLS;
2478 static void gfx_v9_4_3_ring_emit_hdp_flush(struct amdgpu_ring *ring)
2480 struct amdgpu_device *adev = ring->adev;
2481 u32 ref_and_mask, reg_mem_engine;
2482 const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio.hdp_flush_reg;
2484 if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) {
2487 ref_and_mask = nbio_hf_reg->ref_and_mask_cp2 << ring->pipe;
2490 ref_and_mask = nbio_hf_reg->ref_and_mask_cp6 << ring->pipe;
2497 ref_and_mask = nbio_hf_reg->ref_and_mask_cp0;
2498 reg_mem_engine = 1; /* pfp */
2501 gfx_v9_4_3_wait_reg_mem(ring, reg_mem_engine, 0, 1,
2502 adev->nbio.funcs->get_hdp_flush_req_offset(adev),
2503 adev->nbio.funcs->get_hdp_flush_done_offset(adev),
2504 ref_and_mask, ref_and_mask, 0x20);
2507 static void gfx_v9_4_3_ring_emit_ib_compute(struct amdgpu_ring *ring,
2508 struct amdgpu_job *job,
2509 struct amdgpu_ib *ib,
2512 unsigned vmid = AMDGPU_JOB_GET_VMID(job);
2513 u32 control = INDIRECT_BUFFER_VALID | ib->length_dw | (vmid << 24);
2515 /* Currently, there is a high possibility to get wave ID mismatch
2516 * between ME and GDS, leading to a hw deadlock, because ME generates
2517 * different wave IDs than the GDS expects. This situation happens
2518 * randomly when at least 5 compute pipes use GDS ordered append.
2519 * The wave IDs generated by ME are also wrong after suspend/resume.
2520 * Those are probably bugs somewhere else in the kernel driver.
2522 * Writing GDS_COMPUTE_MAX_WAVE_ID resets wave ID counters in ME and
2523 * GDS to 0 for this ring (me/pipe).
2525 if (ib->flags & AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID) {
2526 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
2527 amdgpu_ring_write(ring, regGDS_COMPUTE_MAX_WAVE_ID);
2528 amdgpu_ring_write(ring, ring->adev->gds.gds_compute_max_wave_id);
2531 amdgpu_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
2532 BUG_ON(ib->gpu_addr & 0x3); /* Dword align */
2533 amdgpu_ring_write(ring,
2537 lower_32_bits(ib->gpu_addr));
2538 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
2539 amdgpu_ring_write(ring, control);
2542 static void gfx_v9_4_3_ring_emit_fence(struct amdgpu_ring *ring, u64 addr,
2543 u64 seq, unsigned flags)
2545 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
2546 bool int_sel = flags & AMDGPU_FENCE_FLAG_INT;
2547 bool writeback = flags & AMDGPU_FENCE_FLAG_TC_WB_ONLY;
2549 /* RELEASE_MEM - flush caches, send int */
2550 amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 6));
2551 amdgpu_ring_write(ring, ((writeback ? (EOP_TC_WB_ACTION_EN |
2552 EOP_TC_NC_ACTION_EN) :
2553 (EOP_TCL1_ACTION_EN |
2555 EOP_TC_WB_ACTION_EN |
2556 EOP_TC_MD_ACTION_EN)) |
2557 EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) |
2559 amdgpu_ring_write(ring, DATA_SEL(write64bit ? 2 : 1) | INT_SEL(int_sel ? 2 : 0));
2562 * the address should be Qword aligned if 64bit write, Dword
2563 * aligned if only send 32bit data low (discard data high)
2569 amdgpu_ring_write(ring, lower_32_bits(addr));
2570 amdgpu_ring_write(ring, upper_32_bits(addr));
2571 amdgpu_ring_write(ring, lower_32_bits(seq));
2572 amdgpu_ring_write(ring, upper_32_bits(seq));
2573 amdgpu_ring_write(ring, 0);
2576 static void gfx_v9_4_3_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
2578 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
2579 uint32_t seq = ring->fence_drv.sync_seq;
2580 uint64_t addr = ring->fence_drv.gpu_addr;
2582 gfx_v9_4_3_wait_reg_mem(ring, usepfp, 1, 0,
2583 lower_32_bits(addr), upper_32_bits(addr),
2584 seq, 0xffffffff, 4);
2587 static void gfx_v9_4_3_ring_emit_vm_flush(struct amdgpu_ring *ring,
2588 unsigned vmid, uint64_t pd_addr)
2590 amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
2593 static u64 gfx_v9_4_3_ring_get_rptr_compute(struct amdgpu_ring *ring)
2595 return ring->adev->wb.wb[ring->rptr_offs]; /* gfx9 hardware is 32bit rptr */
2598 static u64 gfx_v9_4_3_ring_get_wptr_compute(struct amdgpu_ring *ring)
2602 /* XXX check if swapping is necessary on BE */
2603 if (ring->use_doorbell)
2604 wptr = atomic64_read((atomic64_t *)&ring->adev->wb.wb[ring->wptr_offs]);
2610 static void gfx_v9_4_3_ring_set_wptr_compute(struct amdgpu_ring *ring)
2612 struct amdgpu_device *adev = ring->adev;
2614 /* XXX check if swapping is necessary on BE */
2615 if (ring->use_doorbell) {
2616 atomic64_set((atomic64_t *)&adev->wb.wb[ring->wptr_offs], ring->wptr);
2617 WDOORBELL64(ring->doorbell_index, ring->wptr);
2619 BUG(); /* only DOORBELL method supported on gfx9 now */
2623 static void gfx_v9_4_3_ring_emit_fence_kiq(struct amdgpu_ring *ring, u64 addr,
2624 u64 seq, unsigned int flags)
2626 struct amdgpu_device *adev = ring->adev;
2628 /* we only allocate 32bit for each seq wb address */
2629 BUG_ON(flags & AMDGPU_FENCE_FLAG_64BIT);
2631 /* write fence seq to the "addr" */
2632 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
2633 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
2634 WRITE_DATA_DST_SEL(5) | WR_CONFIRM));
2635 amdgpu_ring_write(ring, lower_32_bits(addr));
2636 amdgpu_ring_write(ring, upper_32_bits(addr));
2637 amdgpu_ring_write(ring, lower_32_bits(seq));
2639 if (flags & AMDGPU_FENCE_FLAG_INT) {
2640 /* set register to trigger INT */
2641 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
2642 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
2643 WRITE_DATA_DST_SEL(0) | WR_CONFIRM));
2644 amdgpu_ring_write(ring, SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regCPC_INT_STATUS));
2645 amdgpu_ring_write(ring, 0);
2646 amdgpu_ring_write(ring, 0x20000000); /* src_id is 178 */
2650 static void gfx_v9_4_3_ring_emit_rreg(struct amdgpu_ring *ring, uint32_t reg,
2651 uint32_t reg_val_offs)
2653 struct amdgpu_device *adev = ring->adev;
2655 amdgpu_ring_write(ring, PACKET3(PACKET3_COPY_DATA, 4));
2656 amdgpu_ring_write(ring, 0 | /* src: register*/
2657 (5 << 8) | /* dst: memory */
2658 (1 << 20)); /* write confirm */
2659 amdgpu_ring_write(ring, reg);
2660 amdgpu_ring_write(ring, 0);
2661 amdgpu_ring_write(ring, lower_32_bits(adev->wb.gpu_addr +
2663 amdgpu_ring_write(ring, upper_32_bits(adev->wb.gpu_addr +
2667 static void gfx_v9_4_3_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg,
2672 switch (ring->funcs->type) {
2673 case AMDGPU_RING_TYPE_GFX:
2674 cmd = WRITE_DATA_ENGINE_SEL(1) | WR_CONFIRM;
2676 case AMDGPU_RING_TYPE_KIQ:
2677 cmd = (1 << 16); /* no inc addr */
2683 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
2684 amdgpu_ring_write(ring, cmd);
2685 amdgpu_ring_write(ring, reg);
2686 amdgpu_ring_write(ring, 0);
2687 amdgpu_ring_write(ring, val);
2690 static void gfx_v9_4_3_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,
2691 uint32_t val, uint32_t mask)
2693 gfx_v9_4_3_wait_reg_mem(ring, 0, 0, 0, reg, 0, val, mask, 0x20);
2696 static void gfx_v9_4_3_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring,
2697 uint32_t reg0, uint32_t reg1,
2698 uint32_t ref, uint32_t mask)
2700 amdgpu_ring_emit_reg_write_reg_wait_helper(ring, reg0, reg1,
2704 static void gfx_v9_4_3_xcc_set_compute_eop_interrupt_state(
2705 struct amdgpu_device *adev, int me, int pipe,
2706 enum amdgpu_interrupt_state state, int xcc_id)
2708 u32 mec_int_cntl, mec_int_cntl_reg;
2711 * amdgpu controls only the first MEC. That's why this function only
2712 * handles the setting of interrupts for this specific MEC. All other
2713 * pipes' interrupts are set by amdkfd.
2719 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regCP_ME1_PIPE0_INT_CNTL);
2722 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regCP_ME1_PIPE1_INT_CNTL);
2725 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regCP_ME1_PIPE2_INT_CNTL);
2728 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regCP_ME1_PIPE3_INT_CNTL);
2731 DRM_DEBUG("invalid pipe %d\n", pipe);
2735 DRM_DEBUG("invalid me %d\n", me);
2740 case AMDGPU_IRQ_STATE_DISABLE:
2741 mec_int_cntl = RREG32(mec_int_cntl_reg);
2742 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,
2743 TIME_STAMP_INT_ENABLE, 0);
2744 WREG32(mec_int_cntl_reg, mec_int_cntl);
2746 case AMDGPU_IRQ_STATE_ENABLE:
2747 mec_int_cntl = RREG32(mec_int_cntl_reg);
2748 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,
2749 TIME_STAMP_INT_ENABLE, 1);
2750 WREG32(mec_int_cntl_reg, mec_int_cntl);
2757 static int gfx_v9_4_3_set_priv_reg_fault_state(struct amdgpu_device *adev,
2758 struct amdgpu_irq_src *source,
2760 enum amdgpu_interrupt_state state)
2764 num_xcc = NUM_XCC(adev->gfx.xcc_mask);
2766 case AMDGPU_IRQ_STATE_DISABLE:
2767 case AMDGPU_IRQ_STATE_ENABLE:
2768 for (i = 0; i < num_xcc; i++)
2769 WREG32_FIELD15_PREREG(GC, GET_INST(GC, i), CP_INT_CNTL_RING0,
2770 PRIV_REG_INT_ENABLE,
2771 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
2780 static int gfx_v9_4_3_set_priv_inst_fault_state(struct amdgpu_device *adev,
2781 struct amdgpu_irq_src *source,
2783 enum amdgpu_interrupt_state state)
2787 num_xcc = NUM_XCC(adev->gfx.xcc_mask);
2789 case AMDGPU_IRQ_STATE_DISABLE:
2790 case AMDGPU_IRQ_STATE_ENABLE:
2791 for (i = 0; i < num_xcc; i++)
2792 WREG32_FIELD15_PREREG(GC, GET_INST(GC, i), CP_INT_CNTL_RING0,
2793 PRIV_INSTR_INT_ENABLE,
2794 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
2803 static int gfx_v9_4_3_set_eop_interrupt_state(struct amdgpu_device *adev,
2804 struct amdgpu_irq_src *src,
2806 enum amdgpu_interrupt_state state)
2810 num_xcc = NUM_XCC(adev->gfx.xcc_mask);
2811 for (i = 0; i < num_xcc; i++) {
2813 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP:
2814 gfx_v9_4_3_xcc_set_compute_eop_interrupt_state(
2815 adev, 1, 0, state, i);
2817 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP:
2818 gfx_v9_4_3_xcc_set_compute_eop_interrupt_state(
2819 adev, 1, 1, state, i);
2821 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP:
2822 gfx_v9_4_3_xcc_set_compute_eop_interrupt_state(
2823 adev, 1, 2, state, i);
2825 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP:
2826 gfx_v9_4_3_xcc_set_compute_eop_interrupt_state(
2827 adev, 1, 3, state, i);
2829 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP:
2830 gfx_v9_4_3_xcc_set_compute_eop_interrupt_state(
2831 adev, 2, 0, state, i);
2833 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP:
2834 gfx_v9_4_3_xcc_set_compute_eop_interrupt_state(
2835 adev, 2, 1, state, i);
2837 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP:
2838 gfx_v9_4_3_xcc_set_compute_eop_interrupt_state(
2839 adev, 2, 2, state, i);
2841 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP:
2842 gfx_v9_4_3_xcc_set_compute_eop_interrupt_state(
2843 adev, 2, 3, state, i);
2853 static int gfx_v9_4_3_eop_irq(struct amdgpu_device *adev,
2854 struct amdgpu_irq_src *source,
2855 struct amdgpu_iv_entry *entry)
2858 u8 me_id, pipe_id, queue_id;
2859 struct amdgpu_ring *ring;
2861 DRM_DEBUG("IH: CP EOP\n");
2862 me_id = (entry->ring_id & 0x0c) >> 2;
2863 pipe_id = (entry->ring_id & 0x03) >> 0;
2864 queue_id = (entry->ring_id & 0x70) >> 4;
2866 xcc_id = gfx_v9_4_3_ih_to_xcc_inst(adev, entry->node_id);
2868 if (xcc_id == -EINVAL)
2875 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
2876 ring = &adev->gfx.compute_ring
2878 xcc_id * adev->gfx.num_compute_rings];
2879 /* Per-queue interrupt is supported for MEC starting from VI.
2880 * The interrupt can only be enabled/disabled per pipe instead of per queue.
2883 if ((ring->me == me_id) && (ring->pipe == pipe_id) && (ring->queue == queue_id))
2884 amdgpu_fence_process(ring);
2891 static void gfx_v9_4_3_fault(struct amdgpu_device *adev,
2892 struct amdgpu_iv_entry *entry)
2894 u8 me_id, pipe_id, queue_id;
2895 struct amdgpu_ring *ring;
2898 me_id = (entry->ring_id & 0x0c) >> 2;
2899 pipe_id = (entry->ring_id & 0x03) >> 0;
2900 queue_id = (entry->ring_id & 0x70) >> 4;
2902 xcc_id = gfx_v9_4_3_ih_to_xcc_inst(adev, entry->node_id);
2904 if (xcc_id == -EINVAL)
2911 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
2912 ring = &adev->gfx.compute_ring
2914 xcc_id * adev->gfx.num_compute_rings];
2915 if (ring->me == me_id && ring->pipe == pipe_id &&
2916 ring->queue == queue_id)
2917 drm_sched_fault(&ring->sched);
2923 static int gfx_v9_4_3_priv_reg_irq(struct amdgpu_device *adev,
2924 struct amdgpu_irq_src *source,
2925 struct amdgpu_iv_entry *entry)
2927 DRM_ERROR("Illegal register access in command stream\n");
2928 gfx_v9_4_3_fault(adev, entry);
2932 static int gfx_v9_4_3_priv_inst_irq(struct amdgpu_device *adev,
2933 struct amdgpu_irq_src *source,
2934 struct amdgpu_iv_entry *entry)
2936 DRM_ERROR("Illegal instruction in command stream\n");
2937 gfx_v9_4_3_fault(adev, entry);
2941 static void gfx_v9_4_3_emit_mem_sync(struct amdgpu_ring *ring)
2943 const unsigned int cp_coher_cntl =
2944 PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_SH_ICACHE_ACTION_ENA(1) |
2945 PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_SH_KCACHE_ACTION_ENA(1) |
2946 PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_TC_ACTION_ENA(1) |
2947 PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_TCL1_ACTION_ENA(1) |
2948 PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_TC_WB_ACTION_ENA(1);
2950 /* ACQUIRE_MEM -make one or more surfaces valid for use by the subsequent operations */
2951 amdgpu_ring_write(ring, PACKET3(PACKET3_ACQUIRE_MEM, 5));
2952 amdgpu_ring_write(ring, cp_coher_cntl); /* CP_COHER_CNTL */
2953 amdgpu_ring_write(ring, 0xffffffff); /* CP_COHER_SIZE */
2954 amdgpu_ring_write(ring, 0xffffff); /* CP_COHER_SIZE_HI */
2955 amdgpu_ring_write(ring, 0); /* CP_COHER_BASE */
2956 amdgpu_ring_write(ring, 0); /* CP_COHER_BASE_HI */
2957 amdgpu_ring_write(ring, 0x0000000A); /* POLL_INTERVAL */
2960 static void gfx_v9_4_3_emit_wave_limit_cs(struct amdgpu_ring *ring,
2961 uint32_t pipe, bool enable)
2963 struct amdgpu_device *adev = ring->adev;
2965 uint32_t wcl_cs_reg;
2967 /* regSPI_WCL_PIPE_PERCENT_CS[0-7]_DEFAULT values are same */
2968 val = enable ? 0x1 : 0x7f;
2972 wcl_cs_reg = SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regSPI_WCL_PIPE_PERCENT_CS0);
2975 wcl_cs_reg = SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regSPI_WCL_PIPE_PERCENT_CS1);
2978 wcl_cs_reg = SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regSPI_WCL_PIPE_PERCENT_CS2);
2981 wcl_cs_reg = SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regSPI_WCL_PIPE_PERCENT_CS3);
2984 DRM_DEBUG("invalid pipe %d\n", pipe);
2988 amdgpu_ring_emit_wreg(ring, wcl_cs_reg, val);
2991 static void gfx_v9_4_3_emit_wave_limit(struct amdgpu_ring *ring, bool enable)
2993 struct amdgpu_device *adev = ring->adev;
2997 /* regSPI_WCL_PIPE_PERCENT_GFX is 7 bit multiplier register to limit
2998 * number of gfx waves. Setting 5 bit will make sure gfx only gets
2999 * around 25% of gpu resources.
3001 val = enable ? 0x1f : 0x07ffffff;
3002 amdgpu_ring_emit_wreg(ring,
3003 SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regSPI_WCL_PIPE_PERCENT_GFX),
3006 /* Restrict waves for normal/low priority compute queues as well
3007 * to get best QoS for high priority compute jobs.
3009 * amdgpu controls only 1st ME(0-3 CS pipes).
3011 for (i = 0; i < adev->gfx.mec.num_pipe_per_mec; i++) {
3012 if (i != ring->pipe)
3013 gfx_v9_4_3_emit_wave_limit_cs(ring, i, enable);
3018 enum amdgpu_gfx_cp_ras_mem_id {
3019 AMDGPU_GFX_CP_MEM1 = 1,
3026 enum amdgpu_gfx_gcea_ras_mem_id {
3027 AMDGPU_GFX_GCEA_IOWR_CMDMEM = 4,
3028 AMDGPU_GFX_GCEA_IORD_CMDMEM,
3029 AMDGPU_GFX_GCEA_GMIWR_CMDMEM,
3030 AMDGPU_GFX_GCEA_GMIRD_CMDMEM,
3031 AMDGPU_GFX_GCEA_DRAMWR_CMDMEM,
3032 AMDGPU_GFX_GCEA_DRAMRD_CMDMEM,
3033 AMDGPU_GFX_GCEA_MAM_DMEM0,
3034 AMDGPU_GFX_GCEA_MAM_DMEM1,
3035 AMDGPU_GFX_GCEA_MAM_DMEM2,
3036 AMDGPU_GFX_GCEA_MAM_DMEM3,
3037 AMDGPU_GFX_GCEA_MAM_AMEM0,
3038 AMDGPU_GFX_GCEA_MAM_AMEM1,
3039 AMDGPU_GFX_GCEA_MAM_AMEM2,
3040 AMDGPU_GFX_GCEA_MAM_AMEM3,
3041 AMDGPU_GFX_GCEA_MAM_AFLUSH_BUFFER,
3042 AMDGPU_GFX_GCEA_WRET_TAGMEM,
3043 AMDGPU_GFX_GCEA_RRET_TAGMEM,
3044 AMDGPU_GFX_GCEA_IOWR_DATAMEM,
3045 AMDGPU_GFX_GCEA_GMIWR_DATAMEM,
3046 AMDGPU_GFX_GCEA_DRAM_DATAMEM,
3049 enum amdgpu_gfx_gc_cane_ras_mem_id {
3050 AMDGPU_GFX_GC_CANE_MEM0 = 0,
3053 enum amdgpu_gfx_gcutcl2_ras_mem_id {
3054 AMDGPU_GFX_GCUTCL2_MEM2P512X95 = 160,
3057 enum amdgpu_gfx_gds_ras_mem_id {
3058 AMDGPU_GFX_GDS_MEM0 = 0,
3061 enum amdgpu_gfx_lds_ras_mem_id {
3062 AMDGPU_GFX_LDS_BANK0 = 0,
3063 AMDGPU_GFX_LDS_BANK1,
3064 AMDGPU_GFX_LDS_BANK2,
3065 AMDGPU_GFX_LDS_BANK3,
3066 AMDGPU_GFX_LDS_BANK4,
3067 AMDGPU_GFX_LDS_BANK5,
3068 AMDGPU_GFX_LDS_BANK6,
3069 AMDGPU_GFX_LDS_BANK7,
3070 AMDGPU_GFX_LDS_BANK8,
3071 AMDGPU_GFX_LDS_BANK9,
3072 AMDGPU_GFX_LDS_BANK10,
3073 AMDGPU_GFX_LDS_BANK11,
3074 AMDGPU_GFX_LDS_BANK12,
3075 AMDGPU_GFX_LDS_BANK13,
3076 AMDGPU_GFX_LDS_BANK14,
3077 AMDGPU_GFX_LDS_BANK15,
3078 AMDGPU_GFX_LDS_BANK16,
3079 AMDGPU_GFX_LDS_BANK17,
3080 AMDGPU_GFX_LDS_BANK18,
3081 AMDGPU_GFX_LDS_BANK19,
3082 AMDGPU_GFX_LDS_BANK20,
3083 AMDGPU_GFX_LDS_BANK21,
3084 AMDGPU_GFX_LDS_BANK22,
3085 AMDGPU_GFX_LDS_BANK23,
3086 AMDGPU_GFX_LDS_BANK24,
3087 AMDGPU_GFX_LDS_BANK25,
3088 AMDGPU_GFX_LDS_BANK26,
3089 AMDGPU_GFX_LDS_BANK27,
3090 AMDGPU_GFX_LDS_BANK28,
3091 AMDGPU_GFX_LDS_BANK29,
3092 AMDGPU_GFX_LDS_BANK30,
3093 AMDGPU_GFX_LDS_BANK31,
3094 AMDGPU_GFX_LDS_SP_BUFFER_A,
3095 AMDGPU_GFX_LDS_SP_BUFFER_B,
3098 enum amdgpu_gfx_rlc_ras_mem_id {
3099 AMDGPU_GFX_RLC_GPMF32 = 1,
3100 AMDGPU_GFX_RLC_RLCVF32,
3101 AMDGPU_GFX_RLC_SCRATCH,
3102 AMDGPU_GFX_RLC_SRM_ARAM,
3103 AMDGPU_GFX_RLC_SRM_DRAM,
3104 AMDGPU_GFX_RLC_TCTAG,
3105 AMDGPU_GFX_RLC_SPM_SE,
3106 AMDGPU_GFX_RLC_SPM_GRBMT,
3109 enum amdgpu_gfx_sp_ras_mem_id {
3110 AMDGPU_GFX_SP_SIMDID0 = 0,
3113 enum amdgpu_gfx_spi_ras_mem_id {
3114 AMDGPU_GFX_SPI_MEM0 = 0,
3115 AMDGPU_GFX_SPI_MEM1,
3116 AMDGPU_GFX_SPI_MEM2,
3117 AMDGPU_GFX_SPI_MEM3,
3120 enum amdgpu_gfx_sqc_ras_mem_id {
3121 AMDGPU_GFX_SQC_INST_CACHE_A = 100,
3122 AMDGPU_GFX_SQC_INST_CACHE_B = 101,
3123 AMDGPU_GFX_SQC_INST_CACHE_TAG_A = 102,
3124 AMDGPU_GFX_SQC_INST_CACHE_TAG_B = 103,
3125 AMDGPU_GFX_SQC_INST_CACHE_MISS_FIFO_A = 104,
3126 AMDGPU_GFX_SQC_INST_CACHE_MISS_FIFO_B = 105,
3127 AMDGPU_GFX_SQC_INST_CACHE_GATCL1_MISS_FIFO_A = 106,
3128 AMDGPU_GFX_SQC_INST_CACHE_GATCL1_MISS_FIFO_B = 107,
3129 AMDGPU_GFX_SQC_DATA_CACHE_A = 200,
3130 AMDGPU_GFX_SQC_DATA_CACHE_B = 201,
3131 AMDGPU_GFX_SQC_DATA_CACHE_TAG_A = 202,
3132 AMDGPU_GFX_SQC_DATA_CACHE_TAG_B = 203,
3133 AMDGPU_GFX_SQC_DATA_CACHE_MISS_FIFO_A = 204,
3134 AMDGPU_GFX_SQC_DATA_CACHE_MISS_FIFO_B = 205,
3135 AMDGPU_GFX_SQC_DATA_CACHE_HIT_FIFO_A = 206,
3136 AMDGPU_GFX_SQC_DATA_CACHE_HIT_FIFO_B = 207,
3137 AMDGPU_GFX_SQC_DIRTY_BIT_A = 208,
3138 AMDGPU_GFX_SQC_DIRTY_BIT_B = 209,
3139 AMDGPU_GFX_SQC_WRITE_DATA_BUFFER_CU0 = 210,
3140 AMDGPU_GFX_SQC_WRITE_DATA_BUFFER_CU1 = 211,
3141 AMDGPU_GFX_SQC_UTCL1_MISS_LFIFO_DATA_CACHE_A = 212,
3142 AMDGPU_GFX_SQC_UTCL1_MISS_LFIFO_DATA_CACHE_B = 213,
3143 AMDGPU_GFX_SQC_UTCL1_MISS_LFIFO_INST_CACHE = 108,
3146 enum amdgpu_gfx_sq_ras_mem_id {
3147 AMDGPU_GFX_SQ_SGPR_MEM0 = 0,
3148 AMDGPU_GFX_SQ_SGPR_MEM1,
3149 AMDGPU_GFX_SQ_SGPR_MEM2,
3150 AMDGPU_GFX_SQ_SGPR_MEM3,
3153 enum amdgpu_gfx_ta_ras_mem_id {
3154 AMDGPU_GFX_TA_FS_AFIFO_RAM_LO = 1,
3155 AMDGPU_GFX_TA_FS_AFIFO_RAM_HI,
3156 AMDGPU_GFX_TA_FS_CFIFO_RAM,
3157 AMDGPU_GFX_TA_FSX_LFIFO,
3158 AMDGPU_GFX_TA_FS_DFIFO_RAM,
3161 enum amdgpu_gfx_tcc_ras_mem_id {
3162 AMDGPU_GFX_TCC_MEM1 = 1,
3165 enum amdgpu_gfx_tca_ras_mem_id {
3166 AMDGPU_GFX_TCA_MEM1 = 1,
3169 enum amdgpu_gfx_tci_ras_mem_id {
3170 AMDGPU_GFX_TCIW_MEM = 1,
3173 enum amdgpu_gfx_tcp_ras_mem_id {
3174 AMDGPU_GFX_TCP_LFIFO0 = 1,
3175 AMDGPU_GFX_TCP_SET0BANK0_RAM,
3176 AMDGPU_GFX_TCP_SET0BANK1_RAM,
3177 AMDGPU_GFX_TCP_SET0BANK2_RAM,
3178 AMDGPU_GFX_TCP_SET0BANK3_RAM,
3179 AMDGPU_GFX_TCP_SET1BANK0_RAM,
3180 AMDGPU_GFX_TCP_SET1BANK1_RAM,
3181 AMDGPU_GFX_TCP_SET1BANK2_RAM,
3182 AMDGPU_GFX_TCP_SET1BANK3_RAM,
3183 AMDGPU_GFX_TCP_SET2BANK0_RAM,
3184 AMDGPU_GFX_TCP_SET2BANK1_RAM,
3185 AMDGPU_GFX_TCP_SET2BANK2_RAM,
3186 AMDGPU_GFX_TCP_SET2BANK3_RAM,
3187 AMDGPU_GFX_TCP_SET3BANK0_RAM,
3188 AMDGPU_GFX_TCP_SET3BANK1_RAM,
3189 AMDGPU_GFX_TCP_SET3BANK2_RAM,
3190 AMDGPU_GFX_TCP_SET3BANK3_RAM,
3191 AMDGPU_GFX_TCP_VM_FIFO,
3192 AMDGPU_GFX_TCP_DB_TAGRAM0,
3193 AMDGPU_GFX_TCP_DB_TAGRAM1,
3194 AMDGPU_GFX_TCP_DB_TAGRAM2,
3195 AMDGPU_GFX_TCP_DB_TAGRAM3,
3196 AMDGPU_GFX_TCP_UTCL1_LFIFO_PROBE0,
3197 AMDGPU_GFX_TCP_UTCL1_LFIFO_PROBE1,
3198 AMDGPU_GFX_TCP_CMD_FIFO,
3201 enum amdgpu_gfx_td_ras_mem_id {
3202 AMDGPU_GFX_TD_UTD_CS_FIFO_MEM = 1,
3203 AMDGPU_GFX_TD_UTD_SS_FIFO_LO_MEM,
3204 AMDGPU_GFX_TD_UTD_SS_FIFO_HI_MEM,
3207 enum amdgpu_gfx_tcx_ras_mem_id {
3208 AMDGPU_GFX_TCX_FIFOD0 = 0,
3209 AMDGPU_GFX_TCX_FIFOD1,
3210 AMDGPU_GFX_TCX_FIFOD2,
3211 AMDGPU_GFX_TCX_FIFOD3,
3212 AMDGPU_GFX_TCX_FIFOD4,
3213 AMDGPU_GFX_TCX_FIFOD5,
3214 AMDGPU_GFX_TCX_FIFOD6,
3215 AMDGPU_GFX_TCX_FIFOD7,
3216 AMDGPU_GFX_TCX_FIFOB0,
3217 AMDGPU_GFX_TCX_FIFOB1,
3218 AMDGPU_GFX_TCX_FIFOB2,
3219 AMDGPU_GFX_TCX_FIFOB3,
3220 AMDGPU_GFX_TCX_FIFOB4,
3221 AMDGPU_GFX_TCX_FIFOB5,
3222 AMDGPU_GFX_TCX_FIFOB6,
3223 AMDGPU_GFX_TCX_FIFOB7,
3224 AMDGPU_GFX_TCX_FIFOA0,
3225 AMDGPU_GFX_TCX_FIFOA1,
3226 AMDGPU_GFX_TCX_FIFOA2,
3227 AMDGPU_GFX_TCX_FIFOA3,
3228 AMDGPU_GFX_TCX_FIFOA4,
3229 AMDGPU_GFX_TCX_FIFOA5,
3230 AMDGPU_GFX_TCX_FIFOA6,
3231 AMDGPU_GFX_TCX_FIFOA7,
3232 AMDGPU_GFX_TCX_CFIFO0,
3233 AMDGPU_GFX_TCX_CFIFO1,
3234 AMDGPU_GFX_TCX_CFIFO2,
3235 AMDGPU_GFX_TCX_CFIFO3,
3236 AMDGPU_GFX_TCX_CFIFO4,
3237 AMDGPU_GFX_TCX_CFIFO5,
3238 AMDGPU_GFX_TCX_CFIFO6,
3239 AMDGPU_GFX_TCX_CFIFO7,
3240 AMDGPU_GFX_TCX_FIFO_ACKB0,
3241 AMDGPU_GFX_TCX_FIFO_ACKB1,
3242 AMDGPU_GFX_TCX_FIFO_ACKB2,
3243 AMDGPU_GFX_TCX_FIFO_ACKB3,
3244 AMDGPU_GFX_TCX_FIFO_ACKB4,
3245 AMDGPU_GFX_TCX_FIFO_ACKB5,
3246 AMDGPU_GFX_TCX_FIFO_ACKB6,
3247 AMDGPU_GFX_TCX_FIFO_ACKB7,
3248 AMDGPU_GFX_TCX_FIFO_ACKD0,
3249 AMDGPU_GFX_TCX_FIFO_ACKD1,
3250 AMDGPU_GFX_TCX_FIFO_ACKD2,
3251 AMDGPU_GFX_TCX_FIFO_ACKD3,
3252 AMDGPU_GFX_TCX_FIFO_ACKD4,
3253 AMDGPU_GFX_TCX_FIFO_ACKD5,
3254 AMDGPU_GFX_TCX_FIFO_ACKD6,
3255 AMDGPU_GFX_TCX_FIFO_ACKD7,
3256 AMDGPU_GFX_TCX_DST_FIFOA0,
3257 AMDGPU_GFX_TCX_DST_FIFOA1,
3258 AMDGPU_GFX_TCX_DST_FIFOA2,
3259 AMDGPU_GFX_TCX_DST_FIFOA3,
3260 AMDGPU_GFX_TCX_DST_FIFOA4,
3261 AMDGPU_GFX_TCX_DST_FIFOA5,
3262 AMDGPU_GFX_TCX_DST_FIFOA6,
3263 AMDGPU_GFX_TCX_DST_FIFOA7,
3264 AMDGPU_GFX_TCX_DST_FIFOB0,
3265 AMDGPU_GFX_TCX_DST_FIFOB1,
3266 AMDGPU_GFX_TCX_DST_FIFOB2,
3267 AMDGPU_GFX_TCX_DST_FIFOB3,
3268 AMDGPU_GFX_TCX_DST_FIFOB4,
3269 AMDGPU_GFX_TCX_DST_FIFOB5,
3270 AMDGPU_GFX_TCX_DST_FIFOB6,
3271 AMDGPU_GFX_TCX_DST_FIFOB7,
3272 AMDGPU_GFX_TCX_DST_FIFOD0,
3273 AMDGPU_GFX_TCX_DST_FIFOD1,
3274 AMDGPU_GFX_TCX_DST_FIFOD2,
3275 AMDGPU_GFX_TCX_DST_FIFOD3,
3276 AMDGPU_GFX_TCX_DST_FIFOD4,
3277 AMDGPU_GFX_TCX_DST_FIFOD5,
3278 AMDGPU_GFX_TCX_DST_FIFOD6,
3279 AMDGPU_GFX_TCX_DST_FIFOD7,
3280 AMDGPU_GFX_TCX_DST_FIFO_ACKB0,
3281 AMDGPU_GFX_TCX_DST_FIFO_ACKB1,
3282 AMDGPU_GFX_TCX_DST_FIFO_ACKB2,
3283 AMDGPU_GFX_TCX_DST_FIFO_ACKB3,
3284 AMDGPU_GFX_TCX_DST_FIFO_ACKB4,
3285 AMDGPU_GFX_TCX_DST_FIFO_ACKB5,
3286 AMDGPU_GFX_TCX_DST_FIFO_ACKB6,
3287 AMDGPU_GFX_TCX_DST_FIFO_ACKB7,
3288 AMDGPU_GFX_TCX_DST_FIFO_ACKD0,
3289 AMDGPU_GFX_TCX_DST_FIFO_ACKD1,
3290 AMDGPU_GFX_TCX_DST_FIFO_ACKD2,
3291 AMDGPU_GFX_TCX_DST_FIFO_ACKD3,
3292 AMDGPU_GFX_TCX_DST_FIFO_ACKD4,
3293 AMDGPU_GFX_TCX_DST_FIFO_ACKD5,
3294 AMDGPU_GFX_TCX_DST_FIFO_ACKD6,
3295 AMDGPU_GFX_TCX_DST_FIFO_ACKD7,
3298 enum amdgpu_gfx_atc_l2_ras_mem_id {
3299 AMDGPU_GFX_ATC_L2_MEM0 = 0,
3302 enum amdgpu_gfx_utcl2_ras_mem_id {
3303 AMDGPU_GFX_UTCL2_MEM0 = 0,
3306 enum amdgpu_gfx_vml2_ras_mem_id {
3307 AMDGPU_GFX_VML2_MEM0 = 0,
3310 enum amdgpu_gfx_vml2_walker_ras_mem_id {
3311 AMDGPU_GFX_VML2_WALKER_MEM0 = 0,
3314 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_cp_mem_list[] = {
3315 {AMDGPU_GFX_CP_MEM1, "CP_MEM1"},
3316 {AMDGPU_GFX_CP_MEM2, "CP_MEM2"},
3317 {AMDGPU_GFX_CP_MEM3, "CP_MEM3"},
3318 {AMDGPU_GFX_CP_MEM4, "CP_MEM4"},
3319 {AMDGPU_GFX_CP_MEM5, "CP_MEM5"},
3322 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_gcea_mem_list[] = {
3323 {AMDGPU_GFX_GCEA_IOWR_CMDMEM, "GCEA_IOWR_CMDMEM"},
3324 {AMDGPU_GFX_GCEA_IORD_CMDMEM, "GCEA_IORD_CMDMEM"},
3325 {AMDGPU_GFX_GCEA_GMIWR_CMDMEM, "GCEA_GMIWR_CMDMEM"},
3326 {AMDGPU_GFX_GCEA_GMIRD_CMDMEM, "GCEA_GMIRD_CMDMEM"},
3327 {AMDGPU_GFX_GCEA_DRAMWR_CMDMEM, "GCEA_DRAMWR_CMDMEM"},
3328 {AMDGPU_GFX_GCEA_DRAMRD_CMDMEM, "GCEA_DRAMRD_CMDMEM"},
3329 {AMDGPU_GFX_GCEA_MAM_DMEM0, "GCEA_MAM_DMEM0"},
3330 {AMDGPU_GFX_GCEA_MAM_DMEM1, "GCEA_MAM_DMEM1"},
3331 {AMDGPU_GFX_GCEA_MAM_DMEM2, "GCEA_MAM_DMEM2"},
3332 {AMDGPU_GFX_GCEA_MAM_DMEM3, "GCEA_MAM_DMEM3"},
3333 {AMDGPU_GFX_GCEA_MAM_AMEM0, "GCEA_MAM_AMEM0"},
3334 {AMDGPU_GFX_GCEA_MAM_AMEM1, "GCEA_MAM_AMEM1"},
3335 {AMDGPU_GFX_GCEA_MAM_AMEM2, "GCEA_MAM_AMEM2"},
3336 {AMDGPU_GFX_GCEA_MAM_AMEM3, "GCEA_MAM_AMEM3"},
3337 {AMDGPU_GFX_GCEA_MAM_AFLUSH_BUFFER, "GCEA_MAM_AFLUSH_BUFFER"},
3338 {AMDGPU_GFX_GCEA_WRET_TAGMEM, "GCEA_WRET_TAGMEM"},
3339 {AMDGPU_GFX_GCEA_RRET_TAGMEM, "GCEA_RRET_TAGMEM"},
3340 {AMDGPU_GFX_GCEA_IOWR_DATAMEM, "GCEA_IOWR_DATAMEM"},
3341 {AMDGPU_GFX_GCEA_GMIWR_DATAMEM, "GCEA_GMIWR_DATAMEM"},
3342 {AMDGPU_GFX_GCEA_DRAM_DATAMEM, "GCEA_DRAM_DATAMEM"},
3345 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_gc_cane_mem_list[] = {
3346 {AMDGPU_GFX_GC_CANE_MEM0, "GC_CANE_MEM0"},
3349 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_gcutcl2_mem_list[] = {
3350 {AMDGPU_GFX_GCUTCL2_MEM2P512X95, "GCUTCL2_MEM2P512X95"},
3353 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_gds_mem_list[] = {
3354 {AMDGPU_GFX_GDS_MEM0, "GDS_MEM"},
3357 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_lds_mem_list[] = {
3358 {AMDGPU_GFX_LDS_BANK0, "LDS_BANK0"},
3359 {AMDGPU_GFX_LDS_BANK1, "LDS_BANK1"},
3360 {AMDGPU_GFX_LDS_BANK2, "LDS_BANK2"},
3361 {AMDGPU_GFX_LDS_BANK3, "LDS_BANK3"},
3362 {AMDGPU_GFX_LDS_BANK4, "LDS_BANK4"},
3363 {AMDGPU_GFX_LDS_BANK5, "LDS_BANK5"},
3364 {AMDGPU_GFX_LDS_BANK6, "LDS_BANK6"},
3365 {AMDGPU_GFX_LDS_BANK7, "LDS_BANK7"},
3366 {AMDGPU_GFX_LDS_BANK8, "LDS_BANK8"},
3367 {AMDGPU_GFX_LDS_BANK9, "LDS_BANK9"},
3368 {AMDGPU_GFX_LDS_BANK10, "LDS_BANK10"},
3369 {AMDGPU_GFX_LDS_BANK11, "LDS_BANK11"},
3370 {AMDGPU_GFX_LDS_BANK12, "LDS_BANK12"},
3371 {AMDGPU_GFX_LDS_BANK13, "LDS_BANK13"},
3372 {AMDGPU_GFX_LDS_BANK14, "LDS_BANK14"},
3373 {AMDGPU_GFX_LDS_BANK15, "LDS_BANK15"},
3374 {AMDGPU_GFX_LDS_BANK16, "LDS_BANK16"},
3375 {AMDGPU_GFX_LDS_BANK17, "LDS_BANK17"},
3376 {AMDGPU_GFX_LDS_BANK18, "LDS_BANK18"},
3377 {AMDGPU_GFX_LDS_BANK19, "LDS_BANK19"},
3378 {AMDGPU_GFX_LDS_BANK20, "LDS_BANK20"},
3379 {AMDGPU_GFX_LDS_BANK21, "LDS_BANK21"},
3380 {AMDGPU_GFX_LDS_BANK22, "LDS_BANK22"},
3381 {AMDGPU_GFX_LDS_BANK23, "LDS_BANK23"},
3382 {AMDGPU_GFX_LDS_BANK24, "LDS_BANK24"},
3383 {AMDGPU_GFX_LDS_BANK25, "LDS_BANK25"},
3384 {AMDGPU_GFX_LDS_BANK26, "LDS_BANK26"},
3385 {AMDGPU_GFX_LDS_BANK27, "LDS_BANK27"},
3386 {AMDGPU_GFX_LDS_BANK28, "LDS_BANK28"},
3387 {AMDGPU_GFX_LDS_BANK29, "LDS_BANK29"},
3388 {AMDGPU_GFX_LDS_BANK30, "LDS_BANK30"},
3389 {AMDGPU_GFX_LDS_BANK31, "LDS_BANK31"},
3390 {AMDGPU_GFX_LDS_SP_BUFFER_A, "LDS_SP_BUFFER_A"},
3391 {AMDGPU_GFX_LDS_SP_BUFFER_B, "LDS_SP_BUFFER_B"},
3394 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_rlc_mem_list[] = {
3395 {AMDGPU_GFX_RLC_GPMF32, "RLC_GPMF32"},
3396 {AMDGPU_GFX_RLC_RLCVF32, "RLC_RLCVF32"},
3397 {AMDGPU_GFX_RLC_SCRATCH, "RLC_SCRATCH"},
3398 {AMDGPU_GFX_RLC_SRM_ARAM, "RLC_SRM_ARAM"},
3399 {AMDGPU_GFX_RLC_SRM_DRAM, "RLC_SRM_DRAM"},
3400 {AMDGPU_GFX_RLC_TCTAG, "RLC_TCTAG"},
3401 {AMDGPU_GFX_RLC_SPM_SE, "RLC_SPM_SE"},
3402 {AMDGPU_GFX_RLC_SPM_GRBMT, "RLC_SPM_GRBMT"},
3405 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_sp_mem_list[] = {
3406 {AMDGPU_GFX_SP_SIMDID0, "SP_SIMDID0"},
3409 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_spi_mem_list[] = {
3410 {AMDGPU_GFX_SPI_MEM0, "SPI_MEM0"},
3411 {AMDGPU_GFX_SPI_MEM1, "SPI_MEM1"},
3412 {AMDGPU_GFX_SPI_MEM2, "SPI_MEM2"},
3413 {AMDGPU_GFX_SPI_MEM3, "SPI_MEM3"},
3416 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_sqc_mem_list[] = {
3417 {AMDGPU_GFX_SQC_INST_CACHE_A, "SQC_INST_CACHE_A"},
3418 {AMDGPU_GFX_SQC_INST_CACHE_B, "SQC_INST_CACHE_B"},
3419 {AMDGPU_GFX_SQC_INST_CACHE_TAG_A, "SQC_INST_CACHE_TAG_A"},
3420 {AMDGPU_GFX_SQC_INST_CACHE_TAG_B, "SQC_INST_CACHE_TAG_B"},
3421 {AMDGPU_GFX_SQC_INST_CACHE_MISS_FIFO_A, "SQC_INST_CACHE_MISS_FIFO_A"},
3422 {AMDGPU_GFX_SQC_INST_CACHE_MISS_FIFO_B, "SQC_INST_CACHE_MISS_FIFO_B"},
3423 {AMDGPU_GFX_SQC_INST_CACHE_GATCL1_MISS_FIFO_A, "SQC_INST_CACHE_GATCL1_MISS_FIFO_A"},
3424 {AMDGPU_GFX_SQC_INST_CACHE_GATCL1_MISS_FIFO_B, "SQC_INST_CACHE_GATCL1_MISS_FIFO_B"},
3425 {AMDGPU_GFX_SQC_DATA_CACHE_A, "SQC_DATA_CACHE_A"},
3426 {AMDGPU_GFX_SQC_DATA_CACHE_B, "SQC_DATA_CACHE_B"},
3427 {AMDGPU_GFX_SQC_DATA_CACHE_TAG_A, "SQC_DATA_CACHE_TAG_A"},
3428 {AMDGPU_GFX_SQC_DATA_CACHE_TAG_B, "SQC_DATA_CACHE_TAG_B"},
3429 {AMDGPU_GFX_SQC_DATA_CACHE_MISS_FIFO_A, "SQC_DATA_CACHE_MISS_FIFO_A"},
3430 {AMDGPU_GFX_SQC_DATA_CACHE_MISS_FIFO_B, "SQC_DATA_CACHE_MISS_FIFO_B"},
3431 {AMDGPU_GFX_SQC_DATA_CACHE_HIT_FIFO_A, "SQC_DATA_CACHE_HIT_FIFO_A"},
3432 {AMDGPU_GFX_SQC_DATA_CACHE_HIT_FIFO_B, "SQC_DATA_CACHE_HIT_FIFO_B"},
3433 {AMDGPU_GFX_SQC_DIRTY_BIT_A, "SQC_DIRTY_BIT_A"},
3434 {AMDGPU_GFX_SQC_DIRTY_BIT_B, "SQC_DIRTY_BIT_B"},
3435 {AMDGPU_GFX_SQC_WRITE_DATA_BUFFER_CU0, "SQC_WRITE_DATA_BUFFER_CU0"},
3436 {AMDGPU_GFX_SQC_WRITE_DATA_BUFFER_CU1, "SQC_WRITE_DATA_BUFFER_CU1"},
3437 {AMDGPU_GFX_SQC_UTCL1_MISS_LFIFO_DATA_CACHE_A, "SQC_UTCL1_MISS_LFIFO_DATA_CACHE_A"},
3438 {AMDGPU_GFX_SQC_UTCL1_MISS_LFIFO_DATA_CACHE_B, "SQC_UTCL1_MISS_LFIFO_DATA_CACHE_B"},
3439 {AMDGPU_GFX_SQC_UTCL1_MISS_LFIFO_INST_CACHE, "SQC_UTCL1_MISS_LFIFO_INST_CACHE"},
3442 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_sq_mem_list[] = {
3443 {AMDGPU_GFX_SQ_SGPR_MEM0, "SQ_SGPR_MEM0"},
3444 {AMDGPU_GFX_SQ_SGPR_MEM1, "SQ_SGPR_MEM1"},
3445 {AMDGPU_GFX_SQ_SGPR_MEM2, "SQ_SGPR_MEM2"},
3446 {AMDGPU_GFX_SQ_SGPR_MEM3, "SQ_SGPR_MEM3"},
3449 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_ta_mem_list[] = {
3450 {AMDGPU_GFX_TA_FS_AFIFO_RAM_LO, "TA_FS_AFIFO_RAM_LO"},
3451 {AMDGPU_GFX_TA_FS_AFIFO_RAM_HI, "TA_FS_AFIFO_RAM_HI"},
3452 {AMDGPU_GFX_TA_FS_CFIFO_RAM, "TA_FS_CFIFO_RAM"},
3453 {AMDGPU_GFX_TA_FSX_LFIFO, "TA_FSX_LFIFO"},
3454 {AMDGPU_GFX_TA_FS_DFIFO_RAM, "TA_FS_DFIFO_RAM"},
3457 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_tcc_mem_list[] = {
3458 {AMDGPU_GFX_TCC_MEM1, "TCC_MEM1"},
3461 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_tca_mem_list[] = {
3462 {AMDGPU_GFX_TCA_MEM1, "TCA_MEM1"},
3465 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_tci_mem_list[] = {
3466 {AMDGPU_GFX_TCIW_MEM, "TCIW_MEM"},
3469 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_tcp_mem_list[] = {
3470 {AMDGPU_GFX_TCP_LFIFO0, "TCP_LFIFO0"},
3471 {AMDGPU_GFX_TCP_SET0BANK0_RAM, "TCP_SET0BANK0_RAM"},
3472 {AMDGPU_GFX_TCP_SET0BANK1_RAM, "TCP_SET0BANK1_RAM"},
3473 {AMDGPU_GFX_TCP_SET0BANK2_RAM, "TCP_SET0BANK2_RAM"},
3474 {AMDGPU_GFX_TCP_SET0BANK3_RAM, "TCP_SET0BANK3_RAM"},
3475 {AMDGPU_GFX_TCP_SET1BANK0_RAM, "TCP_SET1BANK0_RAM"},
3476 {AMDGPU_GFX_TCP_SET1BANK1_RAM, "TCP_SET1BANK1_RAM"},
3477 {AMDGPU_GFX_TCP_SET1BANK2_RAM, "TCP_SET1BANK2_RAM"},
3478 {AMDGPU_GFX_TCP_SET1BANK3_RAM, "TCP_SET1BANK3_RAM"},
3479 {AMDGPU_GFX_TCP_SET2BANK0_RAM, "TCP_SET2BANK0_RAM"},
3480 {AMDGPU_GFX_TCP_SET2BANK1_RAM, "TCP_SET2BANK1_RAM"},
3481 {AMDGPU_GFX_TCP_SET2BANK2_RAM, "TCP_SET2BANK2_RAM"},
3482 {AMDGPU_GFX_TCP_SET2BANK3_RAM, "TCP_SET2BANK3_RAM"},
3483 {AMDGPU_GFX_TCP_SET3BANK0_RAM, "TCP_SET3BANK0_RAM"},
3484 {AMDGPU_GFX_TCP_SET3BANK1_RAM, "TCP_SET3BANK1_RAM"},
3485 {AMDGPU_GFX_TCP_SET3BANK2_RAM, "TCP_SET3BANK2_RAM"},
3486 {AMDGPU_GFX_TCP_SET3BANK3_RAM, "TCP_SET3BANK3_RAM"},
3487 {AMDGPU_GFX_TCP_VM_FIFO, "TCP_VM_FIFO"},
3488 {AMDGPU_GFX_TCP_DB_TAGRAM0, "TCP_DB_TAGRAM0"},
3489 {AMDGPU_GFX_TCP_DB_TAGRAM1, "TCP_DB_TAGRAM1"},
3490 {AMDGPU_GFX_TCP_DB_TAGRAM2, "TCP_DB_TAGRAM2"},
3491 {AMDGPU_GFX_TCP_DB_TAGRAM3, "TCP_DB_TAGRAM3"},
3492 {AMDGPU_GFX_TCP_UTCL1_LFIFO_PROBE0, "TCP_UTCL1_LFIFO_PROBE0"},
3493 {AMDGPU_GFX_TCP_UTCL1_LFIFO_PROBE1, "TCP_UTCL1_LFIFO_PROBE1"},
3494 {AMDGPU_GFX_TCP_CMD_FIFO, "TCP_CMD_FIFO"},
3497 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_td_mem_list[] = {
3498 {AMDGPU_GFX_TD_UTD_CS_FIFO_MEM, "TD_UTD_CS_FIFO_MEM"},
3499 {AMDGPU_GFX_TD_UTD_SS_FIFO_LO_MEM, "TD_UTD_SS_FIFO_LO_MEM"},
3500 {AMDGPU_GFX_TD_UTD_SS_FIFO_HI_MEM, "TD_UTD_SS_FIFO_HI_MEM"},
3503 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_tcx_mem_list[] = {
3504 {AMDGPU_GFX_TCX_FIFOD0, "TCX_FIFOD0"},
3505 {AMDGPU_GFX_TCX_FIFOD1, "TCX_FIFOD1"},
3506 {AMDGPU_GFX_TCX_FIFOD2, "TCX_FIFOD2"},
3507 {AMDGPU_GFX_TCX_FIFOD3, "TCX_FIFOD3"},
3508 {AMDGPU_GFX_TCX_FIFOD4, "TCX_FIFOD4"},
3509 {AMDGPU_GFX_TCX_FIFOD5, "TCX_FIFOD5"},
3510 {AMDGPU_GFX_TCX_FIFOD6, "TCX_FIFOD6"},
3511 {AMDGPU_GFX_TCX_FIFOD7, "TCX_FIFOD7"},
3512 {AMDGPU_GFX_TCX_FIFOB0, "TCX_FIFOB0"},
3513 {AMDGPU_GFX_TCX_FIFOB1, "TCX_FIFOB1"},
3514 {AMDGPU_GFX_TCX_FIFOB2, "TCX_FIFOB2"},
3515 {AMDGPU_GFX_TCX_FIFOB3, "TCX_FIFOB3"},
3516 {AMDGPU_GFX_TCX_FIFOB4, "TCX_FIFOB4"},
3517 {AMDGPU_GFX_TCX_FIFOB5, "TCX_FIFOB5"},
3518 {AMDGPU_GFX_TCX_FIFOB6, "TCX_FIFOB6"},
3519 {AMDGPU_GFX_TCX_FIFOB7, "TCX_FIFOB7"},
3520 {AMDGPU_GFX_TCX_FIFOA0, "TCX_FIFOA0"},
3521 {AMDGPU_GFX_TCX_FIFOA1, "TCX_FIFOA1"},
3522 {AMDGPU_GFX_TCX_FIFOA2, "TCX_FIFOA2"},
3523 {AMDGPU_GFX_TCX_FIFOA3, "TCX_FIFOA3"},
3524 {AMDGPU_GFX_TCX_FIFOA4, "TCX_FIFOA4"},
3525 {AMDGPU_GFX_TCX_FIFOA5, "TCX_FIFOA5"},
3526 {AMDGPU_GFX_TCX_FIFOA6, "TCX_FIFOA6"},
3527 {AMDGPU_GFX_TCX_FIFOA7, "TCX_FIFOA7"},
3528 {AMDGPU_GFX_TCX_CFIFO0, "TCX_CFIFO0"},
3529 {AMDGPU_GFX_TCX_CFIFO1, "TCX_CFIFO1"},
3530 {AMDGPU_GFX_TCX_CFIFO2, "TCX_CFIFO2"},
3531 {AMDGPU_GFX_TCX_CFIFO3, "TCX_CFIFO3"},
3532 {AMDGPU_GFX_TCX_CFIFO4, "TCX_CFIFO4"},
3533 {AMDGPU_GFX_TCX_CFIFO5, "TCX_CFIFO5"},
3534 {AMDGPU_GFX_TCX_CFIFO6, "TCX_CFIFO6"},
3535 {AMDGPU_GFX_TCX_CFIFO7, "TCX_CFIFO7"},
3536 {AMDGPU_GFX_TCX_FIFO_ACKB0, "TCX_FIFO_ACKB0"},
3537 {AMDGPU_GFX_TCX_FIFO_ACKB1, "TCX_FIFO_ACKB1"},
3538 {AMDGPU_GFX_TCX_FIFO_ACKB2, "TCX_FIFO_ACKB2"},
3539 {AMDGPU_GFX_TCX_FIFO_ACKB3, "TCX_FIFO_ACKB3"},
3540 {AMDGPU_GFX_TCX_FIFO_ACKB4, "TCX_FIFO_ACKB4"},
3541 {AMDGPU_GFX_TCX_FIFO_ACKB5, "TCX_FIFO_ACKB5"},
3542 {AMDGPU_GFX_TCX_FIFO_ACKB6, "TCX_FIFO_ACKB6"},
3543 {AMDGPU_GFX_TCX_FIFO_ACKB7, "TCX_FIFO_ACKB7"},
3544 {AMDGPU_GFX_TCX_FIFO_ACKD0, "TCX_FIFO_ACKD0"},
3545 {AMDGPU_GFX_TCX_FIFO_ACKD1, "TCX_FIFO_ACKD1"},
3546 {AMDGPU_GFX_TCX_FIFO_ACKD2, "TCX_FIFO_ACKD2"},
3547 {AMDGPU_GFX_TCX_FIFO_ACKD3, "TCX_FIFO_ACKD3"},
3548 {AMDGPU_GFX_TCX_FIFO_ACKD4, "TCX_FIFO_ACKD4"},
3549 {AMDGPU_GFX_TCX_FIFO_ACKD5, "TCX_FIFO_ACKD5"},
3550 {AMDGPU_GFX_TCX_FIFO_ACKD6, "TCX_FIFO_ACKD6"},
3551 {AMDGPU_GFX_TCX_FIFO_ACKD7, "TCX_FIFO_ACKD7"},
3552 {AMDGPU_GFX_TCX_DST_FIFOA0, "TCX_DST_FIFOA0"},
3553 {AMDGPU_GFX_TCX_DST_FIFOA1, "TCX_DST_FIFOA1"},
3554 {AMDGPU_GFX_TCX_DST_FIFOA2, "TCX_DST_FIFOA2"},
3555 {AMDGPU_GFX_TCX_DST_FIFOA3, "TCX_DST_FIFOA3"},
3556 {AMDGPU_GFX_TCX_DST_FIFOA4, "TCX_DST_FIFOA4"},
3557 {AMDGPU_GFX_TCX_DST_FIFOA5, "TCX_DST_FIFOA5"},
3558 {AMDGPU_GFX_TCX_DST_FIFOA6, "TCX_DST_FIFOA6"},
3559 {AMDGPU_GFX_TCX_DST_FIFOA7, "TCX_DST_FIFOA7"},
3560 {AMDGPU_GFX_TCX_DST_FIFOB0, "TCX_DST_FIFOB0"},
3561 {AMDGPU_GFX_TCX_DST_FIFOB1, "TCX_DST_FIFOB1"},
3562 {AMDGPU_GFX_TCX_DST_FIFOB2, "TCX_DST_FIFOB2"},
3563 {AMDGPU_GFX_TCX_DST_FIFOB3, "TCX_DST_FIFOB3"},
3564 {AMDGPU_GFX_TCX_DST_FIFOB4, "TCX_DST_FIFOB4"},
3565 {AMDGPU_GFX_TCX_DST_FIFOB5, "TCX_DST_FIFOB5"},
3566 {AMDGPU_GFX_TCX_DST_FIFOB6, "TCX_DST_FIFOB6"},
3567 {AMDGPU_GFX_TCX_DST_FIFOB7, "TCX_DST_FIFOB7"},
3568 {AMDGPU_GFX_TCX_DST_FIFOD0, "TCX_DST_FIFOD0"},
3569 {AMDGPU_GFX_TCX_DST_FIFOD1, "TCX_DST_FIFOD1"},
3570 {AMDGPU_GFX_TCX_DST_FIFOD2, "TCX_DST_FIFOD2"},
3571 {AMDGPU_GFX_TCX_DST_FIFOD3, "TCX_DST_FIFOD3"},
3572 {AMDGPU_GFX_TCX_DST_FIFOD4, "TCX_DST_FIFOD4"},
3573 {AMDGPU_GFX_TCX_DST_FIFOD5, "TCX_DST_FIFOD5"},
3574 {AMDGPU_GFX_TCX_DST_FIFOD6, "TCX_DST_FIFOD6"},
3575 {AMDGPU_GFX_TCX_DST_FIFOD7, "TCX_DST_FIFOD7"},
3576 {AMDGPU_GFX_TCX_DST_FIFO_ACKB0, "TCX_DST_FIFO_ACKB0"},
3577 {AMDGPU_GFX_TCX_DST_FIFO_ACKB1, "TCX_DST_FIFO_ACKB1"},
3578 {AMDGPU_GFX_TCX_DST_FIFO_ACKB2, "TCX_DST_FIFO_ACKB2"},
3579 {AMDGPU_GFX_TCX_DST_FIFO_ACKB3, "TCX_DST_FIFO_ACKB3"},
3580 {AMDGPU_GFX_TCX_DST_FIFO_ACKB4, "TCX_DST_FIFO_ACKB4"},
3581 {AMDGPU_GFX_TCX_DST_FIFO_ACKB5, "TCX_DST_FIFO_ACKB5"},
3582 {AMDGPU_GFX_TCX_DST_FIFO_ACKB6, "TCX_DST_FIFO_ACKB6"},
3583 {AMDGPU_GFX_TCX_DST_FIFO_ACKB7, "TCX_DST_FIFO_ACKB7"},
3584 {AMDGPU_GFX_TCX_DST_FIFO_ACKD0, "TCX_DST_FIFO_ACKD0"},
3585 {AMDGPU_GFX_TCX_DST_FIFO_ACKD1, "TCX_DST_FIFO_ACKD1"},
3586 {AMDGPU_GFX_TCX_DST_FIFO_ACKD2, "TCX_DST_FIFO_ACKD2"},
3587 {AMDGPU_GFX_TCX_DST_FIFO_ACKD3, "TCX_DST_FIFO_ACKD3"},
3588 {AMDGPU_GFX_TCX_DST_FIFO_ACKD4, "TCX_DST_FIFO_ACKD4"},
3589 {AMDGPU_GFX_TCX_DST_FIFO_ACKD5, "TCX_DST_FIFO_ACKD5"},
3590 {AMDGPU_GFX_TCX_DST_FIFO_ACKD6, "TCX_DST_FIFO_ACKD6"},
3591 {AMDGPU_GFX_TCX_DST_FIFO_ACKD7, "TCX_DST_FIFO_ACKD7"},
3594 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_atc_l2_mem_list[] = {
3595 {AMDGPU_GFX_ATC_L2_MEM, "ATC_L2_MEM"},
3598 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_utcl2_mem_list[] = {
3599 {AMDGPU_GFX_UTCL2_MEM, "UTCL2_MEM"},
3602 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_vml2_mem_list[] = {
3603 {AMDGPU_GFX_VML2_MEM, "VML2_MEM"},
3606 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_vml2_walker_mem_list[] = {
3607 {AMDGPU_GFX_VML2_WALKER_MEM, "VML2_WALKER_MEM"},
3610 static const struct amdgpu_gfx_ras_mem_id_entry gfx_v9_4_3_ras_mem_list_array[AMDGPU_GFX_MEM_TYPE_NUM] = {
3611 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_cp_mem_list)
3612 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_gcea_mem_list)
3613 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_gc_cane_mem_list)
3614 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_gcutcl2_mem_list)
3615 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_gds_mem_list)
3616 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_lds_mem_list)
3617 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_rlc_mem_list)
3618 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_sp_mem_list)
3619 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_spi_mem_list)
3620 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_sqc_mem_list)
3621 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_sq_mem_list)
3622 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_ta_mem_list)
3623 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_tcc_mem_list)
3624 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_tca_mem_list)
3625 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_tci_mem_list)
3626 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_tcp_mem_list)
3627 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_td_mem_list)
3628 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_tcx_mem_list)
3629 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_atc_l2_mem_list)
3630 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_utcl2_mem_list)
3631 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_vml2_mem_list)
3632 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_vml2_walker_mem_list)
3635 static const struct amdgpu_gfx_ras_reg_entry gfx_v9_4_3_ce_reg_list[] = {
3636 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regRLC_CE_ERR_STATUS_LOW, regRLC_CE_ERR_STATUS_HIGH),
3637 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "RLC"},
3638 AMDGPU_GFX_RLC_MEM, 1},
3639 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regCPC_CE_ERR_STATUS_LO, regCPC_CE_ERR_STATUS_HI),
3640 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "CPC"},
3641 AMDGPU_GFX_CP_MEM, 1},
3642 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regCPF_CE_ERR_STATUS_LO, regCPF_CE_ERR_STATUS_HI),
3643 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "CPF"},
3644 AMDGPU_GFX_CP_MEM, 1},
3645 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regCPG_CE_ERR_STATUS_LO, regCPG_CE_ERR_STATUS_HI),
3646 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "CPG"},
3647 AMDGPU_GFX_CP_MEM, 1},
3648 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regGDS_CE_ERR_STATUS_LO, regGDS_CE_ERR_STATUS_HI),
3649 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "GDS"},
3650 AMDGPU_GFX_GDS_MEM, 1},
3651 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regGC_CANE_CE_ERR_STATUS_LO, regGC_CANE_CE_ERR_STATUS_HI),
3652 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "CANE"},
3653 AMDGPU_GFX_GC_CANE_MEM, 1},
3654 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regSPI_CE_ERR_STATUS_LO, regSPI_CE_ERR_STATUS_HI),
3655 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "SPI"},
3656 AMDGPU_GFX_SPI_MEM, 1},
3657 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regSP0_CE_ERR_STATUS_LO, regSP0_CE_ERR_STATUS_HI),
3658 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "SP0"},
3659 AMDGPU_GFX_SP_MEM, 4},
3660 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regSP1_CE_ERR_STATUS_LO, regSP1_CE_ERR_STATUS_HI),
3661 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "SP1"},
3662 AMDGPU_GFX_SP_MEM, 4},
3663 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regSQ_CE_ERR_STATUS_LO, regSQ_CE_ERR_STATUS_HI),
3664 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "SQ"},
3665 AMDGPU_GFX_SQ_MEM, 4},
3666 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regSQC_CE_EDC_LO, regSQC_CE_EDC_HI),
3667 5, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "SQC"},
3668 AMDGPU_GFX_SQC_MEM, 4},
3669 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTCX_CE_ERR_STATUS_LO, regTCX_CE_ERR_STATUS_HI),
3670 2, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TCX"},
3671 AMDGPU_GFX_TCX_MEM, 1},
3672 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTCC_CE_ERR_STATUS_LO, regTCC_CE_ERR_STATUS_HI),
3673 16, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TCC"},
3674 AMDGPU_GFX_TCC_MEM, 1},
3675 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTA_CE_EDC_LO, regTA_CE_EDC_HI),
3676 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TA"},
3677 AMDGPU_GFX_TA_MEM, 4},
3678 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTCI_CE_EDC_LO_REG, regTCI_CE_EDC_HI_REG),
3679 27, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TCI"},
3680 AMDGPU_GFX_TCI_MEM, 1},
3681 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTCP_CE_EDC_LO_REG, regTCP_CE_EDC_HI_REG),
3682 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TCP"},
3683 AMDGPU_GFX_TCP_MEM, 4},
3684 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTD_CE_EDC_LO, regTD_CE_EDC_HI),
3685 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TD"},
3686 AMDGPU_GFX_TD_MEM, 4},
3687 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regGCEA_CE_ERR_STATUS_LO, regGCEA_CE_ERR_STATUS_HI),
3688 16, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "GCEA"},
3689 AMDGPU_GFX_GCEA_MEM, 1},
3690 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regLDS_CE_ERR_STATUS_LO, regLDS_CE_ERR_STATUS_HI),
3691 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "LDS"},
3692 AMDGPU_GFX_LDS_MEM, 4},
3695 static const struct amdgpu_gfx_ras_reg_entry gfx_v9_4_3_ue_reg_list[] = {
3696 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regRLC_UE_ERR_STATUS_LOW, regRLC_UE_ERR_STATUS_HIGH),
3697 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "RLC"},
3698 AMDGPU_GFX_RLC_MEM, 1},
3699 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regCPC_UE_ERR_STATUS_LO, regCPC_UE_ERR_STATUS_HI),
3700 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "CPC"},
3701 AMDGPU_GFX_CP_MEM, 1},
3702 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regCPF_UE_ERR_STATUS_LO, regCPF_UE_ERR_STATUS_HI),
3703 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "CPF"},
3704 AMDGPU_GFX_CP_MEM, 1},
3705 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regCPG_UE_ERR_STATUS_LO, regCPG_UE_ERR_STATUS_HI),
3706 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "CPG"},
3707 AMDGPU_GFX_CP_MEM, 1},
3708 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regGDS_UE_ERR_STATUS_LO, regGDS_UE_ERR_STATUS_HI),
3709 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "GDS"},
3710 AMDGPU_GFX_GDS_MEM, 1},
3711 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regGC_CANE_UE_ERR_STATUS_LO, regGC_CANE_UE_ERR_STATUS_HI),
3712 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "CANE"},
3713 AMDGPU_GFX_GC_CANE_MEM, 1},
3714 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regSPI_UE_ERR_STATUS_LO, regSPI_UE_ERR_STATUS_HI),
3715 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "SPI"},
3716 AMDGPU_GFX_SPI_MEM, 1},
3717 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regSP0_UE_ERR_STATUS_LO, regSP0_UE_ERR_STATUS_HI),
3718 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "SP0"},
3719 AMDGPU_GFX_SP_MEM, 4},
3720 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regSP1_UE_ERR_STATUS_LO, regSP1_UE_ERR_STATUS_HI),
3721 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "SP1"},
3722 AMDGPU_GFX_SP_MEM, 4},
3723 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regSQ_UE_ERR_STATUS_LO, regSQ_UE_ERR_STATUS_HI),
3724 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "SQ"},
3725 AMDGPU_GFX_SQ_MEM, 4},
3726 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regSQC_UE_EDC_LO, regSQC_UE_EDC_HI),
3727 5, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "SQC"},
3728 AMDGPU_GFX_SQC_MEM, 4},
3729 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTCX_UE_ERR_STATUS_LO, regTCX_UE_ERR_STATUS_HI),
3730 2, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TCX"},
3731 AMDGPU_GFX_TCX_MEM, 1},
3732 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTCC_UE_ERR_STATUS_LO, regTCC_UE_ERR_STATUS_HI),
3733 16, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TCC"},
3734 AMDGPU_GFX_TCC_MEM, 1},
3735 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTA_UE_EDC_LO, regTA_UE_EDC_HI),
3736 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TA"},
3737 AMDGPU_GFX_TA_MEM, 4},
3738 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTCI_UE_EDC_LO_REG, regTCI_UE_EDC_HI_REG),
3739 27, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TCI"},
3740 AMDGPU_GFX_TCI_MEM, 1},
3741 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTCP_UE_EDC_LO_REG, regTCP_UE_EDC_HI_REG),
3742 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TCP"},
3743 AMDGPU_GFX_TCP_MEM, 4},
3744 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTD_UE_EDC_LO, regTD_UE_EDC_HI),
3745 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TD"},
3746 AMDGPU_GFX_TD_MEM, 4},
3747 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTCA_UE_ERR_STATUS_LO, regTCA_UE_ERR_STATUS_HI),
3748 2, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TCA"},
3749 AMDGPU_GFX_TCA_MEM, 1},
3750 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regGCEA_UE_ERR_STATUS_LO, regGCEA_UE_ERR_STATUS_HI),
3751 16, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "GCEA"},
3752 AMDGPU_GFX_GCEA_MEM, 1},
3753 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regLDS_UE_ERR_STATUS_LO, regLDS_UE_ERR_STATUS_HI),
3754 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "LDS"},
3755 AMDGPU_GFX_LDS_MEM, 4},
3758 static void gfx_v9_4_3_inst_query_ras_err_count(struct amdgpu_device *adev,
3759 void *ras_error_status, int xcc_id)
3761 struct ras_err_data *err_data = (struct ras_err_data *)ras_error_status;
3762 unsigned long ce_count = 0, ue_count = 0;
3765 /* NOTE: convert xcc_id to physical XCD ID (XCD0 or XCD1) */
3766 struct amdgpu_smuio_mcm_config_info mcm_info = {
3767 .socket_id = adev->smuio.funcs->get_socket_id(adev),
3768 .die_id = xcc_id & 0x01 ? 1 : 0,
3771 mutex_lock(&adev->grbm_idx_mutex);
3773 for (i = 0; i < ARRAY_SIZE(gfx_v9_4_3_ce_reg_list); i++) {
3774 for (j = 0; j < gfx_v9_4_3_ce_reg_list[i].se_num; j++) {
3775 for (k = 0; k < gfx_v9_4_3_ce_reg_list[i].reg_entry.reg_inst; k++) {
3776 /* no need to select if instance number is 1 */
3777 if (gfx_v9_4_3_ce_reg_list[i].se_num > 1 ||
3778 gfx_v9_4_3_ce_reg_list[i].reg_entry.reg_inst > 1)
3779 gfx_v9_4_3_xcc_select_se_sh(adev, j, 0, k, xcc_id);
3781 amdgpu_ras_inst_query_ras_error_count(adev,
3782 &(gfx_v9_4_3_ce_reg_list[i].reg_entry),
3784 gfx_v9_4_3_ras_mem_list_array[gfx_v9_4_3_ce_reg_list[i].mem_id_type].mem_id_ent,
3785 gfx_v9_4_3_ras_mem_list_array[gfx_v9_4_3_ce_reg_list[i].mem_id_type].size,
3786 GET_INST(GC, xcc_id),
3787 AMDGPU_RAS_ERROR__SINGLE_CORRECTABLE,
3790 amdgpu_ras_inst_query_ras_error_count(adev,
3791 &(gfx_v9_4_3_ue_reg_list[i].reg_entry),
3793 gfx_v9_4_3_ras_mem_list_array[gfx_v9_4_3_ue_reg_list[i].mem_id_type].mem_id_ent,
3794 gfx_v9_4_3_ras_mem_list_array[gfx_v9_4_3_ue_reg_list[i].mem_id_type].size,
3795 GET_INST(GC, xcc_id),
3796 AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE,
3802 gfx_v9_4_3_xcc_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff,
3804 mutex_unlock(&adev->grbm_idx_mutex);
3806 /* the caller should make sure initialize value of
3807 * err_data->ue_count and err_data->ce_count
3809 amdgpu_ras_error_statistic_ue_count(err_data, &mcm_info, ue_count);
3810 amdgpu_ras_error_statistic_ce_count(err_data, &mcm_info, ce_count);
3813 static void gfx_v9_4_3_inst_reset_ras_err_count(struct amdgpu_device *adev,
3814 void *ras_error_status, int xcc_id)
3818 mutex_lock(&adev->grbm_idx_mutex);
3820 for (i = 0; i < ARRAY_SIZE(gfx_v9_4_3_ce_reg_list); i++) {
3821 for (j = 0; j < gfx_v9_4_3_ce_reg_list[i].se_num; j++) {
3822 for (k = 0; k < gfx_v9_4_3_ce_reg_list[i].reg_entry.reg_inst; k++) {
3823 /* no need to select if instance number is 1 */
3824 if (gfx_v9_4_3_ce_reg_list[i].se_num > 1 ||
3825 gfx_v9_4_3_ce_reg_list[i].reg_entry.reg_inst > 1)
3826 gfx_v9_4_3_xcc_select_se_sh(adev, j, 0, k, xcc_id);
3828 amdgpu_ras_inst_reset_ras_error_count(adev,
3829 &(gfx_v9_4_3_ce_reg_list[i].reg_entry),
3831 GET_INST(GC, xcc_id));
3833 amdgpu_ras_inst_reset_ras_error_count(adev,
3834 &(gfx_v9_4_3_ue_reg_list[i].reg_entry),
3836 GET_INST(GC, xcc_id));
3841 gfx_v9_4_3_xcc_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff,
3843 mutex_unlock(&adev->grbm_idx_mutex);
3846 static void gfx_v9_4_3_inst_query_utc_err_status(struct amdgpu_device *adev,
3851 data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regUTCL2_MEM_ECC_STATUS);
3853 dev_warn(adev->dev, "GFX UTCL2 Mem Ecc Status: 0x%x!\n", data);
3854 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regUTCL2_MEM_ECC_STATUS, 0x3);
3857 data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regVML2_MEM_ECC_STATUS);
3859 dev_warn(adev->dev, "GFX VML2 Mem Ecc Status: 0x%x!\n", data);
3860 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regVML2_MEM_ECC_STATUS, 0x3);
3863 data = RREG32_SOC15(GC, GET_INST(GC, xcc_id),
3864 regVML2_WALKER_MEM_ECC_STATUS);
3866 dev_warn(adev->dev, "GFX VML2 Walker Mem Ecc Status: 0x%x!\n", data);
3867 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regVML2_WALKER_MEM_ECC_STATUS,
3872 static void gfx_v9_4_3_log_cu_timeout_status(struct amdgpu_device *adev,
3873 uint32_t status, int xcc_id)
3875 struct amdgpu_cu_info *cu_info = &adev->gfx.cu_info;
3876 uint32_t i, simd, wave;
3877 uint32_t wave_status;
3878 uint32_t wave_pc_lo, wave_pc_hi;
3879 uint32_t wave_exec_lo, wave_exec_hi;
3880 uint32_t wave_inst_dw0, wave_inst_dw1;
3881 uint32_t wave_ib_sts;
3883 for (i = 0; i < 32; i++) {
3884 if (!((i << 1) & status))
3887 simd = i / cu_info->max_waves_per_simd;
3888 wave = i % cu_info->max_waves_per_simd;
3890 wave_status = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_STATUS);
3891 wave_pc_lo = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_PC_LO);
3892 wave_pc_hi = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_PC_HI);
3894 wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_EXEC_LO);
3896 wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_EXEC_HI);
3898 wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_INST_DW0);
3900 wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_INST_DW1);
3901 wave_ib_sts = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_IB_STS);
3905 "\t SIMD %d, Wave %d: status 0x%x, pc 0x%llx, exec 0x%llx, inst 0x%llx, ib_sts 0x%x\n",
3906 simd, wave, wave_status,
3907 ((uint64_t)wave_pc_hi << 32 | wave_pc_lo),
3908 ((uint64_t)wave_exec_hi << 32 | wave_exec_lo),
3909 ((uint64_t)wave_inst_dw1 << 32 | wave_inst_dw0),
3914 static void gfx_v9_4_3_inst_query_sq_timeout_status(struct amdgpu_device *adev,
3917 uint32_t se_idx, sh_idx, cu_idx;
3920 mutex_lock(&adev->grbm_idx_mutex);
3921 for (se_idx = 0; se_idx < adev->gfx.config.max_shader_engines; se_idx++) {
3922 for (sh_idx = 0; sh_idx < adev->gfx.config.max_sh_per_se; sh_idx++) {
3923 for (cu_idx = 0; cu_idx < adev->gfx.config.max_cu_per_sh; cu_idx++) {
3924 gfx_v9_4_3_xcc_select_se_sh(adev, se_idx, sh_idx,
3926 status = RREG32_SOC15(GC, GET_INST(GC, xcc_id),
3927 regSQ_TIMEOUT_STATUS);
3931 "GFX Watchdog Timeout: SE %d, SH %d, CU %d\n",
3932 se_idx, sh_idx, cu_idx);
3933 gfx_v9_4_3_log_cu_timeout_status(
3934 adev, status, xcc_id);
3936 /* clear old status */
3937 WREG32_SOC15(GC, GET_INST(GC, xcc_id),
3938 regSQ_TIMEOUT_STATUS, 0);
3942 gfx_v9_4_3_xcc_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff,
3944 mutex_unlock(&adev->grbm_idx_mutex);
3947 static void gfx_v9_4_3_inst_query_ras_err_status(struct amdgpu_device *adev,
3948 void *ras_error_status, int xcc_id)
3950 gfx_v9_4_3_inst_query_utc_err_status(adev, xcc_id);
3951 gfx_v9_4_3_inst_query_sq_timeout_status(adev, xcc_id);
3954 static void gfx_v9_4_3_inst_reset_utc_err_status(struct amdgpu_device *adev,
3957 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regUTCL2_MEM_ECC_STATUS, 0x3);
3958 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regVML2_MEM_ECC_STATUS, 0x3);
3959 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regVML2_WALKER_MEM_ECC_STATUS, 0x3);
3962 static void gfx_v9_4_3_inst_reset_sq_timeout_status(struct amdgpu_device *adev,
3965 uint32_t se_idx, sh_idx, cu_idx;
3967 mutex_lock(&adev->grbm_idx_mutex);
3968 for (se_idx = 0; se_idx < adev->gfx.config.max_shader_engines; se_idx++) {
3969 for (sh_idx = 0; sh_idx < adev->gfx.config.max_sh_per_se; sh_idx++) {
3970 for (cu_idx = 0; cu_idx < adev->gfx.config.max_cu_per_sh; cu_idx++) {
3971 gfx_v9_4_3_xcc_select_se_sh(adev, se_idx, sh_idx,
3973 WREG32_SOC15(GC, GET_INST(GC, xcc_id),
3974 regSQ_TIMEOUT_STATUS, 0);
3978 gfx_v9_4_3_xcc_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff,
3980 mutex_unlock(&adev->grbm_idx_mutex);
3983 static void gfx_v9_4_3_inst_reset_ras_err_status(struct amdgpu_device *adev,
3984 void *ras_error_status, int xcc_id)
3986 gfx_v9_4_3_inst_reset_utc_err_status(adev, xcc_id);
3987 gfx_v9_4_3_inst_reset_sq_timeout_status(adev, xcc_id);
3990 static void gfx_v9_4_3_inst_enable_watchdog_timer(struct amdgpu_device *adev,
3991 void *ras_error_status, int xcc_id)
3996 data = RREG32_SOC15(GC, GET_INST(GC, 0), regSQ_TIMEOUT_CONFIG);
3997 data = REG_SET_FIELD(data, SQ_TIMEOUT_CONFIG, TIMEOUT_FATAL_DISABLE,
3998 amdgpu_watchdog_timer.timeout_fatal_disable ? 1 : 0);
4000 if (amdgpu_watchdog_timer.timeout_fatal_disable &&
4001 (amdgpu_watchdog_timer.period < 1 ||
4002 amdgpu_watchdog_timer.period > 0x23)) {
4003 dev_warn(adev->dev, "Watchdog period range is 1 to 0x23\n");
4004 amdgpu_watchdog_timer.period = 0x23;
4006 data = REG_SET_FIELD(data, SQ_TIMEOUT_CONFIG, PERIOD_SEL,
4007 amdgpu_watchdog_timer.period);
4009 mutex_lock(&adev->grbm_idx_mutex);
4010 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
4011 gfx_v9_4_3_xcc_select_se_sh(adev, i, 0xffffffff, 0xffffffff, xcc_id);
4012 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regSQ_TIMEOUT_CONFIG, data);
4014 gfx_v9_4_3_xcc_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff,
4016 mutex_unlock(&adev->grbm_idx_mutex);
4019 static void gfx_v9_4_3_query_ras_error_count(struct amdgpu_device *adev,
4020 void *ras_error_status)
4022 amdgpu_gfx_ras_error_func(adev, ras_error_status,
4023 gfx_v9_4_3_inst_query_ras_err_count);
4026 static void gfx_v9_4_3_reset_ras_error_count(struct amdgpu_device *adev)
4028 amdgpu_gfx_ras_error_func(adev, NULL, gfx_v9_4_3_inst_reset_ras_err_count);
4031 static void gfx_v9_4_3_query_ras_error_status(struct amdgpu_device *adev)
4033 amdgpu_gfx_ras_error_func(adev, NULL, gfx_v9_4_3_inst_query_ras_err_status);
4036 static void gfx_v9_4_3_reset_ras_error_status(struct amdgpu_device *adev)
4038 amdgpu_gfx_ras_error_func(adev, NULL, gfx_v9_4_3_inst_reset_ras_err_status);
4041 static void gfx_v9_4_3_enable_watchdog_timer(struct amdgpu_device *adev)
4043 amdgpu_gfx_ras_error_func(adev, NULL, gfx_v9_4_3_inst_enable_watchdog_timer);
4046 static const struct amd_ip_funcs gfx_v9_4_3_ip_funcs = {
4047 .name = "gfx_v9_4_3",
4048 .early_init = gfx_v9_4_3_early_init,
4049 .late_init = gfx_v9_4_3_late_init,
4050 .sw_init = gfx_v9_4_3_sw_init,
4051 .sw_fini = gfx_v9_4_3_sw_fini,
4052 .hw_init = gfx_v9_4_3_hw_init,
4053 .hw_fini = gfx_v9_4_3_hw_fini,
4054 .suspend = gfx_v9_4_3_suspend,
4055 .resume = gfx_v9_4_3_resume,
4056 .is_idle = gfx_v9_4_3_is_idle,
4057 .wait_for_idle = gfx_v9_4_3_wait_for_idle,
4058 .soft_reset = gfx_v9_4_3_soft_reset,
4059 .set_clockgating_state = gfx_v9_4_3_set_clockgating_state,
4060 .set_powergating_state = gfx_v9_4_3_set_powergating_state,
4061 .get_clockgating_state = gfx_v9_4_3_get_clockgating_state,
4064 static const struct amdgpu_ring_funcs gfx_v9_4_3_ring_funcs_compute = {
4065 .type = AMDGPU_RING_TYPE_COMPUTE,
4067 .nop = PACKET3(PACKET3_NOP, 0x3FFF),
4068 .support_64bit_ptrs = true,
4069 .get_rptr = gfx_v9_4_3_ring_get_rptr_compute,
4070 .get_wptr = gfx_v9_4_3_ring_get_wptr_compute,
4071 .set_wptr = gfx_v9_4_3_ring_set_wptr_compute,
4073 20 + /* gfx_v9_4_3_ring_emit_gds_switch */
4074 7 + /* gfx_v9_4_3_ring_emit_hdp_flush */
4075 5 + /* hdp invalidate */
4076 7 + /* gfx_v9_4_3_ring_emit_pipeline_sync */
4077 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 +
4078 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 +
4079 2 + /* gfx_v9_4_3_ring_emit_vm_flush */
4080 8 + 8 + 8 + /* gfx_v9_4_3_ring_emit_fence x3 for user fence, vm fence */
4081 7 + /* gfx_v9_4_3_emit_mem_sync */
4082 5 + /* gfx_v9_4_3_emit_wave_limit for updating regSPI_WCL_PIPE_PERCENT_GFX register */
4083 15, /* for updating 3 regSPI_WCL_PIPE_PERCENT_CS registers */
4084 .emit_ib_size = 7, /* gfx_v9_4_3_ring_emit_ib_compute */
4085 .emit_ib = gfx_v9_4_3_ring_emit_ib_compute,
4086 .emit_fence = gfx_v9_4_3_ring_emit_fence,
4087 .emit_pipeline_sync = gfx_v9_4_3_ring_emit_pipeline_sync,
4088 .emit_vm_flush = gfx_v9_4_3_ring_emit_vm_flush,
4089 .emit_gds_switch = gfx_v9_4_3_ring_emit_gds_switch,
4090 .emit_hdp_flush = gfx_v9_4_3_ring_emit_hdp_flush,
4091 .test_ring = gfx_v9_4_3_ring_test_ring,
4092 .test_ib = gfx_v9_4_3_ring_test_ib,
4093 .insert_nop = amdgpu_ring_insert_nop,
4094 .pad_ib = amdgpu_ring_generic_pad_ib,
4095 .emit_wreg = gfx_v9_4_3_ring_emit_wreg,
4096 .emit_reg_wait = gfx_v9_4_3_ring_emit_reg_wait,
4097 .emit_reg_write_reg_wait = gfx_v9_4_3_ring_emit_reg_write_reg_wait,
4098 .emit_mem_sync = gfx_v9_4_3_emit_mem_sync,
4099 .emit_wave_limit = gfx_v9_4_3_emit_wave_limit,
4102 static const struct amdgpu_ring_funcs gfx_v9_4_3_ring_funcs_kiq = {
4103 .type = AMDGPU_RING_TYPE_KIQ,
4105 .nop = PACKET3(PACKET3_NOP, 0x3FFF),
4106 .support_64bit_ptrs = true,
4107 .get_rptr = gfx_v9_4_3_ring_get_rptr_compute,
4108 .get_wptr = gfx_v9_4_3_ring_get_wptr_compute,
4109 .set_wptr = gfx_v9_4_3_ring_set_wptr_compute,
4111 20 + /* gfx_v9_4_3_ring_emit_gds_switch */
4112 7 + /* gfx_v9_4_3_ring_emit_hdp_flush */
4113 5 + /* hdp invalidate */
4114 7 + /* gfx_v9_4_3_ring_emit_pipeline_sync */
4115 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 +
4116 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 +
4117 2 + /* gfx_v9_4_3_ring_emit_vm_flush */
4118 8 + 8 + 8, /* gfx_v9_4_3_ring_emit_fence_kiq x3 for user fence, vm fence */
4119 .emit_ib_size = 7, /* gfx_v9_4_3_ring_emit_ib_compute */
4120 .emit_fence = gfx_v9_4_3_ring_emit_fence_kiq,
4121 .test_ring = gfx_v9_4_3_ring_test_ring,
4122 .insert_nop = amdgpu_ring_insert_nop,
4123 .pad_ib = amdgpu_ring_generic_pad_ib,
4124 .emit_rreg = gfx_v9_4_3_ring_emit_rreg,
4125 .emit_wreg = gfx_v9_4_3_ring_emit_wreg,
4126 .emit_reg_wait = gfx_v9_4_3_ring_emit_reg_wait,
4127 .emit_reg_write_reg_wait = gfx_v9_4_3_ring_emit_reg_write_reg_wait,
4130 static void gfx_v9_4_3_set_ring_funcs(struct amdgpu_device *adev)
4134 num_xcc = NUM_XCC(adev->gfx.xcc_mask);
4135 for (i = 0; i < num_xcc; i++) {
4136 adev->gfx.kiq[i].ring.funcs = &gfx_v9_4_3_ring_funcs_kiq;
4138 for (j = 0; j < adev->gfx.num_compute_rings; j++)
4139 adev->gfx.compute_ring[j + i * adev->gfx.num_compute_rings].funcs
4140 = &gfx_v9_4_3_ring_funcs_compute;
4144 static const struct amdgpu_irq_src_funcs gfx_v9_4_3_eop_irq_funcs = {
4145 .set = gfx_v9_4_3_set_eop_interrupt_state,
4146 .process = gfx_v9_4_3_eop_irq,
4149 static const struct amdgpu_irq_src_funcs gfx_v9_4_3_priv_reg_irq_funcs = {
4150 .set = gfx_v9_4_3_set_priv_reg_fault_state,
4151 .process = gfx_v9_4_3_priv_reg_irq,
4154 static const struct amdgpu_irq_src_funcs gfx_v9_4_3_priv_inst_irq_funcs = {
4155 .set = gfx_v9_4_3_set_priv_inst_fault_state,
4156 .process = gfx_v9_4_3_priv_inst_irq,
4159 static void gfx_v9_4_3_set_irq_funcs(struct amdgpu_device *adev)
4161 adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST;
4162 adev->gfx.eop_irq.funcs = &gfx_v9_4_3_eop_irq_funcs;
4164 adev->gfx.priv_reg_irq.num_types = 1;
4165 adev->gfx.priv_reg_irq.funcs = &gfx_v9_4_3_priv_reg_irq_funcs;
4167 adev->gfx.priv_inst_irq.num_types = 1;
4168 adev->gfx.priv_inst_irq.funcs = &gfx_v9_4_3_priv_inst_irq_funcs;
4171 static void gfx_v9_4_3_set_rlc_funcs(struct amdgpu_device *adev)
4173 adev->gfx.rlc.funcs = &gfx_v9_4_3_rlc_funcs;
4177 static void gfx_v9_4_3_set_gds_init(struct amdgpu_device *adev)
4179 /* init asci gds info */
4180 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
4181 case IP_VERSION(9, 4, 3):
4182 /* 9.4.3 removed all the GDS internal memory,
4183 * only support GWS opcode in kernel, like barrier
4185 adev->gds.gds_size = 0;
4188 adev->gds.gds_size = 0x10000;
4192 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
4193 case IP_VERSION(9, 4, 3):
4194 /* deprecated for 9.4.3, no usage at all */
4195 adev->gds.gds_compute_max_wave_id = 0;
4198 /* this really depends on the chip */
4199 adev->gds.gds_compute_max_wave_id = 0x7ff;
4203 adev->gds.gws_size = 64;
4204 adev->gds.oa_size = 16;
4207 static void gfx_v9_4_3_set_user_cu_inactive_bitmap(struct amdgpu_device *adev,
4208 u32 bitmap, int xcc_id)
4215 data = bitmap << GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT;
4216 data &= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK;
4218 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regGC_USER_SHADER_ARRAY_CONFIG, data);
4221 static u32 gfx_v9_4_3_get_cu_active_bitmap(struct amdgpu_device *adev, int xcc_id)
4225 data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCC_GC_SHADER_ARRAY_CONFIG);
4226 data |= RREG32_SOC15(GC, GET_INST(GC, xcc_id), regGC_USER_SHADER_ARRAY_CONFIG);
4228 data &= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK;
4229 data >>= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT;
4231 mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_cu_per_sh);
4233 return (~data) & mask;
4236 static int gfx_v9_4_3_get_cu_info(struct amdgpu_device *adev,
4237 struct amdgpu_cu_info *cu_info)
4239 int i, j, k, counter, xcc_id, active_cu_number = 0;
4240 u32 mask, bitmap, ao_bitmap, ao_cu_mask = 0;
4241 unsigned disable_masks[4 * 4];
4243 if (!adev || !cu_info)
4247 * 16 comes from bitmap array size 4*4, and it can cover all gfx9 ASICs
4249 if (adev->gfx.config.max_shader_engines *
4250 adev->gfx.config.max_sh_per_se > 16)
4253 amdgpu_gfx_parse_disable_cu(disable_masks,
4254 adev->gfx.config.max_shader_engines,
4255 adev->gfx.config.max_sh_per_se);
4257 mutex_lock(&adev->grbm_idx_mutex);
4258 for (xcc_id = 0; xcc_id < NUM_XCC(adev->gfx.xcc_mask); xcc_id++) {
4259 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
4260 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
4264 gfx_v9_4_3_xcc_select_se_sh(adev, i, j, 0xffffffff, xcc_id);
4265 gfx_v9_4_3_set_user_cu_inactive_bitmap(
4267 disable_masks[i * adev->gfx.config.max_sh_per_se + j],
4269 bitmap = gfx_v9_4_3_get_cu_active_bitmap(adev, xcc_id);
4271 cu_info->bitmap[xcc_id][i][j] = bitmap;
4273 for (k = 0; k < adev->gfx.config.max_cu_per_sh; k++) {
4274 if (bitmap & mask) {
4275 if (counter < adev->gfx.config.max_cu_per_sh)
4281 active_cu_number += counter;
4283 ao_cu_mask |= (ao_bitmap << (i * 16 + j * 8));
4284 cu_info->ao_cu_bitmap[i][j] = ao_bitmap;
4287 gfx_v9_4_3_xcc_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff,
4290 mutex_unlock(&adev->grbm_idx_mutex);
4292 cu_info->number = active_cu_number;
4293 cu_info->ao_cu_mask = ao_cu_mask;
4294 cu_info->simd_per_cu = NUM_SIMD_PER_CU;
4299 const struct amdgpu_ip_block_version gfx_v9_4_3_ip_block = {
4300 .type = AMD_IP_BLOCK_TYPE_GFX,
4304 .funcs = &gfx_v9_4_3_ip_funcs,
4307 static int gfx_v9_4_3_xcp_resume(void *handle, uint32_t inst_mask)
4309 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4313 /* TODO : Initialize golden regs */
4314 /* gfx_v9_4_3_init_golden_registers(adev); */
4316 tmp_mask = inst_mask;
4317 for_each_inst(i, tmp_mask)
4318 gfx_v9_4_3_xcc_constants_init(adev, i);
4320 if (!amdgpu_sriov_vf(adev)) {
4321 tmp_mask = inst_mask;
4322 for_each_inst(i, tmp_mask) {
4323 r = gfx_v9_4_3_xcc_rlc_resume(adev, i);
4329 tmp_mask = inst_mask;
4330 for_each_inst(i, tmp_mask) {
4331 r = gfx_v9_4_3_xcc_cp_resume(adev, i);
4339 static int gfx_v9_4_3_xcp_suspend(void *handle, uint32_t inst_mask)
4341 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4344 for_each_inst(i, inst_mask)
4345 gfx_v9_4_3_xcc_fini(adev, i);
4350 struct amdgpu_xcp_ip_funcs gfx_v9_4_3_xcp_funcs = {
4351 .suspend = &gfx_v9_4_3_xcp_suspend,
4352 .resume = &gfx_v9_4_3_xcp_resume
4355 struct amdgpu_ras_block_hw_ops gfx_v9_4_3_ras_ops = {
4356 .query_ras_error_count = &gfx_v9_4_3_query_ras_error_count,
4357 .reset_ras_error_count = &gfx_v9_4_3_reset_ras_error_count,
4358 .query_ras_error_status = &gfx_v9_4_3_query_ras_error_status,
4359 .reset_ras_error_status = &gfx_v9_4_3_reset_ras_error_status,
4362 struct amdgpu_gfx_ras gfx_v9_4_3_ras = {
4364 .hw_ops = &gfx_v9_4_3_ras_ops,
4366 .enable_watchdog_timer = &gfx_v9_4_3_enable_watchdog_timer,