drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c

   1 /*
   2  * Copyright 2016 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23 #include <linux/kernel.h>
  24 #include <linux/firmware.h>
  25 #include <drm/drmP.h>
  26 #include "amdgpu.h"
  27 #include "amdgpu_gfx.h"
  28 #include "soc15.h"
  29 #include "soc15d.h"
  30 #include "amdgpu_atomfirmware.h"
  31
  32 #include "gc/gc_9_0_offset.h"
  33 #include "gc/gc_9_0_sh_mask.h"
  34 #include "vega10_enum.h"
  35 #include "hdp/hdp_4_0_offset.h"
  36
  37 #include "soc15_common.h"
  38 #include "clearstate_gfx9.h"
  39 #include "v9_structs.h"
  40
  41 #include "ivsrcid/gfx/irqsrcs_gfx_9_0.h"
  42
  43 #define GFX9_NUM_GFX_RINGS     1
  44 #define GFX9_MEC_HPD_SIZE 4096
  45 #define RLCG_UCODE_LOADING_START_ADDRESS 0x00002000L
  46 #define RLC_SAVE_RESTORE_ADDR_STARTING_OFFSET 0x00000000L
  47
  48 #define mmPWR_MISC_CNTL_STATUS                                  0x0183
  49 #define mmPWR_MISC_CNTL_STATUS_BASE_IDX                         0
  50 #define PWR_MISC_CNTL_STATUS__PWR_GFX_RLC_CGPG_EN__SHIFT        0x0
  51 #define PWR_MISC_CNTL_STATUS__PWR_GFXOFF_STATUS__SHIFT          0x1
  52 #define PWR_MISC_CNTL_STATUS__PWR_GFX_RLC_CGPG_EN_MASK          0x00000001L
  53 #define PWR_MISC_CNTL_STATUS__PWR_GFXOFF_STATUS_MASK            0x00000006L
  54
  55 MODULE_FIRMWARE("amdgpu/vega10_ce.bin");
  56 MODULE_FIRMWARE("amdgpu/vega10_pfp.bin");
  57 MODULE_FIRMWARE("amdgpu/vega10_me.bin");
  58 MODULE_FIRMWARE("amdgpu/vega10_mec.bin");
  59 MODULE_FIRMWARE("amdgpu/vega10_mec2.bin");
  60 MODULE_FIRMWARE("amdgpu/vega10_rlc.bin");
  61
  62 MODULE_FIRMWARE("amdgpu/vega12_ce.bin");
  63 MODULE_FIRMWARE("amdgpu/vega12_pfp.bin");
  64 MODULE_FIRMWARE("amdgpu/vega12_me.bin");
  65 MODULE_FIRMWARE("amdgpu/vega12_mec.bin");
  66 MODULE_FIRMWARE("amdgpu/vega12_mec2.bin");
  67 MODULE_FIRMWARE("amdgpu/vega12_rlc.bin");
  68
  69 MODULE_FIRMWARE("amdgpu/vega20_ce.bin");
  70 MODULE_FIRMWARE("amdgpu/vega20_pfp.bin");
  71 MODULE_FIRMWARE("amdgpu/vega20_me.bin");
  72 MODULE_FIRMWARE("amdgpu/vega20_mec.bin");
  73 MODULE_FIRMWARE("amdgpu/vega20_mec2.bin");
  74 MODULE_FIRMWARE("amdgpu/vega20_rlc.bin");
  75
  76 MODULE_FIRMWARE("amdgpu/raven_ce.bin");
  77 MODULE_FIRMWARE("amdgpu/raven_pfp.bin");
  78 MODULE_FIRMWARE("amdgpu/raven_me.bin");
  79 MODULE_FIRMWARE("amdgpu/raven_mec.bin");
  80 MODULE_FIRMWARE("amdgpu/raven_mec2.bin");
  81 MODULE_FIRMWARE("amdgpu/raven_rlc.bin");
  82
  83 MODULE_FIRMWARE("amdgpu/picasso_ce.bin");
  84 MODULE_FIRMWARE("amdgpu/picasso_pfp.bin");
  85 MODULE_FIRMWARE("amdgpu/picasso_me.bin");
  86 MODULE_FIRMWARE("amdgpu/picasso_mec.bin");
  87 MODULE_FIRMWARE("amdgpu/picasso_mec2.bin");
  88 MODULE_FIRMWARE("amdgpu/picasso_rlc.bin");
  89 MODULE_FIRMWARE("amdgpu/picasso_rlc_am4.bin");
  90
  91 MODULE_FIRMWARE("amdgpu/raven2_ce.bin");
  92 MODULE_FIRMWARE("amdgpu/raven2_pfp.bin");
  93 MODULE_FIRMWARE("amdgpu/raven2_me.bin");
  94 MODULE_FIRMWARE("amdgpu/raven2_mec.bin");
  95 MODULE_FIRMWARE("amdgpu/raven2_mec2.bin");
  96 MODULE_FIRMWARE("amdgpu/raven2_rlc.bin");
  97
  98 static const struct soc15_reg_golden golden_settings_gc_9_0[] =
  99 {
 100         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xf00fffff, 0x00000400),
 101         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0x80000000, 0x80000000),
 102         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_GPU_ID, 0x0000000f, 0x00000000),
 103         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_3, 0x00000003, 0x82400024),
 104         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x00000001),
 105         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000),
 106         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSH_MEM_CONFIG, 0x00001000, 0x00001000),
 107         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_RESOURCE_RESERVE_CU_0, 0x0007ffff, 0x00000800),
 108         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_RESOURCE_RESERVE_CU_1, 0x0007ffff, 0x00000800),
 109         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_RESOURCE_RESERVE_EN_CU_0, 0x01ffffff, 0x0000ff87),
 110         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_RESOURCE_RESERVE_EN_CU_1, 0x01ffffff, 0x0000ff8f),
 111         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQC_CONFIG, 0x03000000, 0x020a2000),
 112         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfffffeef, 0x010b0000),
 113         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_HI, 0xffffffff, 0x4a2c0e68),
 114         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_LO, 0xffffffff, 0xb5d3f197),
 115         SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_CACHE_INVALIDATION, 0x3fff3af3, 0x19200000),
 116         SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_GS_MAX_WAVE_ID, 0x00000fff, 0x000003ff)
 117 };
 118
 119 static const struct soc15_reg_golden golden_settings_gc_9_0_vg10[] =
 120 {
 121         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL, 0x0000f000, 0x00012107),
 122         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_3, 0x30000000, 0x10000000),
 123         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPC_UTCL1_CNTL, 0x08000000, 0x08000080),
 124         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_UTCL1_CNTL, 0x08000000, 0x08000080),
 125         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPG_UTCL1_CNTL, 0x08000000, 0x08000080),
 126         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0xffff77ff, 0x2a114042),
 127         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG_READ, 0xffff77ff, 0x2a114042),
 128         SOC15_REG_GOLDEN_VALUE(GC, 0, mmIA_UTCL1_CNTL, 0x08000000, 0x08000080),
 129         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0x00008000, 0x00048000),
 130         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_GPM_UTCL1_CNTL_0, 0x08000000, 0x08000080),
 131         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_GPM_UTCL1_CNTL_1, 0x08000000, 0x08000080),
 132         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_GPM_UTCL1_CNTL_2, 0x08000000, 0x08000080),
 133         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_PREWALKER_UTCL1_CNTL, 0x08000000, 0x08000080),
 134         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_UTCL1_CNTL, 0x08000000, 0x08000080),
 135         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_UTCL1_CNTL2, 0x00030000, 0x00020000),
 136         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0x0000000f, 0x01000107),
 137         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTD_CNTL, 0x00001800, 0x00000800),
 138         SOC15_REG_GOLDEN_VALUE(GC, 0, mmWD_UTCL1_CNTL, 0x08000000, 0x08000080),
 139         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_MEC1_F32_INT_DIS, 0x00000000, 0x00000800),
 140         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_MEC2_F32_INT_DIS, 0x00000000, 0x00000800),
 141         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_DEBUG, 0x00000000, 0x00008000)
 142 };
 143
 144 static const struct soc15_reg_golden golden_settings_gc_9_0_vg20[] =
 145 {
 146         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_DCC_CONFIG, 0x0f000080, 0x04000080),
 147         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_2, 0x0f000000, 0x0a000000),
 148         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_3, 0x30000000, 0x10000000),
 149         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0xf3e777ff, 0x22014042),
 150         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG_READ, 0xf3e777ff, 0x22014042),
 151         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0x00003e00, 0x00000400),
 152         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0xff840000, 0x04040000),
 153         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_UTCL1_CNTL2, 0x00030000, 0x00030000),
 154         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0xffff010f, 0x01000107),
 155         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0x000b0000, 0x000b0000),
 156         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTD_CNTL, 0x01000000, 0x01000000)
 157 };
 158
 159 static const struct soc15_reg_golden golden_settings_gc_9_1[] =
 160 {
 161         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL, 0xfffdf3cf, 0x00014104),
 162         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPC_UTCL1_CNTL, 0x08000000, 0x08000080),
 163         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_UTCL1_CNTL, 0x08000000, 0x08000080),
 164         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPG_UTCL1_CNTL, 0x08000000, 0x08000080),
 165         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xf00fffff, 0x00000420),
 166         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_GPU_ID, 0x0000000f, 0x00000000),
 167         SOC15_REG_GOLDEN_VALUE(GC, 0, mmIA_UTCL1_CNTL, 0x08000000, 0x08000080),
 168         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_3, 0x00000003, 0x82400024),
 169         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x00000001),
 170         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000),
 171         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_GPM_UTCL1_CNTL_0, 0x08000000, 0x08000080),
 172         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_GPM_UTCL1_CNTL_1, 0x08000000, 0x08000080),
 173         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_GPM_UTCL1_CNTL_2, 0x08000000, 0x08000080),
 174         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_PREWALKER_UTCL1_CNTL, 0x08000000, 0x08000080),
 175         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_UTCL1_CNTL, 0x08000000, 0x08000080),
 176         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfffffeef, 0x010b0000),
 177         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_HI, 0xffffffff, 0x00000000),
 178         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_LO, 0xffffffff, 0x00003120),
 179         SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_CACHE_INVALIDATION, 0x3fff3af3, 0x19200000),
 180         SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_GS_MAX_WAVE_ID, 0x00000fff, 0x000000ff),
 181         SOC15_REG_GOLDEN_VALUE(GC, 0, mmWD_UTCL1_CNTL, 0x08000000, 0x08000080),
 182         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_MEC1_F32_INT_DIS, 0x00000000, 0x00000800),
 183         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_MEC2_F32_INT_DIS, 0x00000000, 0x00000800),
 184         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_DEBUG, 0x00000000, 0x00008000)
 185 };
 186
 187 static const struct soc15_reg_golden golden_settings_gc_9_1_rv1[] =
 188 {
 189         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_3, 0x30000000, 0x10000000),
 190         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0xffff77ff, 0x24000042),
 191         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG_READ, 0xffff77ff, 0x24000042),
 192         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0xffffffff, 0x04048000),
 193         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_MODE_CNTL_1, 0x06000000, 0x06000000),
 194         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_UTCL1_CNTL2, 0x00030000, 0x00020000),
 195         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTD_CNTL, 0x01bd9f33, 0x00000800)
 196 };
 197
 198 static const struct soc15_reg_golden golden_settings_gc_9_1_rv2[] =
 199 {
 200         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_DCC_CONFIG, 0xff7fffff, 0x04000000),
 201         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL, 0xfffdf3cf, 0x00014104),
 202         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_2, 0xff7fffff, 0x0a000000),
 203         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPC_UTCL1_CNTL, 0x7f0fffff, 0x08000080),
 204         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_UTCL1_CNTL, 0xff8fffff, 0x08000080),
 205         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPG_UTCL1_CNTL, 0x7f8fffff, 0x08000080),
 206         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0xffff77ff, 0x26013041),
 207         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG_READ, 0xffff77ff, 0x26013041),
 208         SOC15_REG_GOLDEN_VALUE(GC, 0, mmIA_UTCL1_CNTL, 0x3f8fffff, 0x08000080),
 209         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0xffffffff, 0x04040000),
 210         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_GPM_UTCL1_CNTL_0, 0xff0fffff, 0x08000080),
 211         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_GPM_UTCL1_CNTL_1, 0xff0fffff, 0x08000080),
 212         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_GPM_UTCL1_CNTL_2, 0xff0fffff, 0x08000080),
 213         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_PREWALKER_UTCL1_CNTL, 0xff0fffff, 0x08000080),
 214         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_UTCL1_CNTL, 0xff0fffff, 0x08000080),
 215         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_HI, 0xffffffff, 0x00000000),
 216         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_LO, 0xffffffff, 0x00000010),
 217         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTD_CNTL, 0x01bd9f33, 0x01000000),
 218         SOC15_REG_GOLDEN_VALUE(GC, 0, mmWD_UTCL1_CNTL, 0x3f8fffff, 0x08000080),
 219 };
 220
 221 static const struct soc15_reg_golden golden_settings_gc_9_x_common[] =
 222 {
 223         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_CAM_INDEX, 0xffffffff, 0x00000000),
 224         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_CAM_DATA, 0xffffffff, 0x2544c382)
 225 };
 226
 227 static const struct soc15_reg_golden golden_settings_gc_9_2_1[] =
 228 {
 229         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xf00fffff, 0x00000420),
 230         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_GPU_ID, 0x0000000f, 0x00000000),
 231         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_3, 0x00000003, 0x82400024),
 232         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x00000001),
 233         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000),
 234         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSH_MEM_CONFIG, 0x00001000, 0x00001000),
 235         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_RESOURCE_RESERVE_CU_0, 0x0007ffff, 0x00000800),
 236         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_RESOURCE_RESERVE_CU_1, 0x0007ffff, 0x00000800),
 237         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_RESOURCE_RESERVE_EN_CU_0, 0x01ffffff, 0x0000ff87),
 238         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_RESOURCE_RESERVE_EN_CU_1, 0x01ffffff, 0x0000ff8f),
 239         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQC_CONFIG, 0x03000000, 0x020a2000),
 240         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfffffeef, 0x010b0000),
 241         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_HI, 0xffffffff, 0x4a2c0e68),
 242         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_LO, 0xffffffff, 0xb5d3f197),
 243         SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_CACHE_INVALIDATION, 0x3fff3af3, 0x19200000),
 244         SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_GS_MAX_WAVE_ID, 0x00000fff, 0x000003ff)
 245 };
 246
 247 static const struct soc15_reg_golden golden_settings_gc_9_2_1_vg12[] =
 248 {
 249         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_DCC_CONFIG, 0x00000080, 0x04000080),
 250         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL, 0xfffdf3cf, 0x00014104),
 251         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_2, 0x0f000000, 0x0a000000),
 252         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0xffff77ff, 0x24104041),
 253         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG_READ, 0xffff77ff, 0x24104041),
 254         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0xffffffff, 0x04040000),
 255         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0xffff03ff, 0x01000107),
 256         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_HI, 0xffffffff, 0x00000000),
 257         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_LO, 0xffffffff, 0x76325410),
 258         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTD_CNTL, 0x01bd9f33, 0x01000000),
 259         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_MEC1_F32_INT_DIS, 0x00000000, 0x00000800),
 260         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_MEC2_F32_INT_DIS, 0x00000000, 0x00000800),
 261         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_DEBUG, 0x00000000, 0x00008000)
 262 };
 263
 264 static const u32 GFX_RLC_SRM_INDEX_CNTL_ADDR_OFFSETS[] =
 265 {
 266         mmRLC_SRM_INDEX_CNTL_ADDR_0 - mmRLC_SRM_INDEX_CNTL_ADDR_0,
 267         mmRLC_SRM_INDEX_CNTL_ADDR_1 - mmRLC_SRM_INDEX_CNTL_ADDR_0,
 268         mmRLC_SRM_INDEX_CNTL_ADDR_2 - mmRLC_SRM_INDEX_CNTL_ADDR_0,
 269         mmRLC_SRM_INDEX_CNTL_ADDR_3 - mmRLC_SRM_INDEX_CNTL_ADDR_0,
 270         mmRLC_SRM_INDEX_CNTL_ADDR_4 - mmRLC_SRM_INDEX_CNTL_ADDR_0,
 271         mmRLC_SRM_INDEX_CNTL_ADDR_5 - mmRLC_SRM_INDEX_CNTL_ADDR_0,
 272         mmRLC_SRM_INDEX_CNTL_ADDR_6 - mmRLC_SRM_INDEX_CNTL_ADDR_0,
 273         mmRLC_SRM_INDEX_CNTL_ADDR_7 - mmRLC_SRM_INDEX_CNTL_ADDR_0,
 274 };
 275
 276 static const u32 GFX_RLC_SRM_INDEX_CNTL_DATA_OFFSETS[] =
 277 {
 278         mmRLC_SRM_INDEX_CNTL_DATA_0 - mmRLC_SRM_INDEX_CNTL_DATA_0,
 279         mmRLC_SRM_INDEX_CNTL_DATA_1 - mmRLC_SRM_INDEX_CNTL_DATA_0,
 280         mmRLC_SRM_INDEX_CNTL_DATA_2 - mmRLC_SRM_INDEX_CNTL_DATA_0,
 281         mmRLC_SRM_INDEX_CNTL_DATA_3 - mmRLC_SRM_INDEX_CNTL_DATA_0,
 282         mmRLC_SRM_INDEX_CNTL_DATA_4 - mmRLC_SRM_INDEX_CNTL_DATA_0,
 283         mmRLC_SRM_INDEX_CNTL_DATA_5 - mmRLC_SRM_INDEX_CNTL_DATA_0,
 284         mmRLC_SRM_INDEX_CNTL_DATA_6 - mmRLC_SRM_INDEX_CNTL_DATA_0,
 285         mmRLC_SRM_INDEX_CNTL_DATA_7 - mmRLC_SRM_INDEX_CNTL_DATA_0,
 286 };
 287
 288 #define VEGA10_GB_ADDR_CONFIG_GOLDEN 0x2a114042
 289 #define VEGA12_GB_ADDR_CONFIG_GOLDEN 0x24104041
 290 #define RAVEN_GB_ADDR_CONFIG_GOLDEN 0x24000042
 291 #define RAVEN2_GB_ADDR_CONFIG_GOLDEN 0x26013041
 292
 293 static void gfx_v9_0_set_ring_funcs(struct amdgpu_device *adev);
 294 static void gfx_v9_0_set_irq_funcs(struct amdgpu_device *adev);
 295 static void gfx_v9_0_set_gds_init(struct amdgpu_device *adev);
 296 static void gfx_v9_0_set_rlc_funcs(struct amdgpu_device *adev);
 297 static int gfx_v9_0_get_cu_info(struct amdgpu_device *adev,
 298                                  struct amdgpu_cu_info *cu_info);
 299 static uint64_t gfx_v9_0_get_gpu_clock_counter(struct amdgpu_device *adev);
 300 static void gfx_v9_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, u32 sh_num, u32 instance);
 301 static void gfx_v9_0_ring_emit_de_meta(struct amdgpu_ring *ring);
 302
 303 static void gfx_v9_0_init_golden_registers(struct amdgpu_device *adev)
 304 {
 305         switch (adev->asic_type) {
 306         case CHIP_VEGA10:
 307                 soc15_program_register_sequence(adev,
 308                                                  golden_settings_gc_9_0,
 309                                                  ARRAY_SIZE(golden_settings_gc_9_0));
 310                 soc15_program_register_sequence(adev,
 311                                                  golden_settings_gc_9_0_vg10,
 312                                                  ARRAY_SIZE(golden_settings_gc_9_0_vg10));
 313                 break;
 314         case CHIP_VEGA12:
 315                 soc15_program_register_sequence(adev,
 316                                                 golden_settings_gc_9_2_1,
 317                                                 ARRAY_SIZE(golden_settings_gc_9_2_1));
 318                 soc15_program_register_sequence(adev,
 319                                                 golden_settings_gc_9_2_1_vg12,
 320                                                 ARRAY_SIZE(golden_settings_gc_9_2_1_vg12));
 321                 break;
 322         case CHIP_VEGA20:
 323                 soc15_program_register_sequence(adev,
 324                                                 golden_settings_gc_9_0,
 325                                                 ARRAY_SIZE(golden_settings_gc_9_0));
 326                 soc15_program_register_sequence(adev,
 327                                                 golden_settings_gc_9_0_vg20,
 328                                                 ARRAY_SIZE(golden_settings_gc_9_0_vg20));
 329                 break;
 330         case CHIP_RAVEN:
 331                 soc15_program_register_sequence(adev, golden_settings_gc_9_1,
 332                                                 ARRAY_SIZE(golden_settings_gc_9_1));
 333                 if (adev->rev_id >= 8)
 334                         soc15_program_register_sequence(adev,
 335                                                         golden_settings_gc_9_1_rv2,
 336                                                         ARRAY_SIZE(golden_settings_gc_9_1_rv2));
 337                 else
 338                         soc15_program_register_sequence(adev,
 339                                                         golden_settings_gc_9_1_rv1,
 340                                                         ARRAY_SIZE(golden_settings_gc_9_1_rv1));
 341                 break;
 342         default:
 343                 break;
 344         }
 345
 346         soc15_program_register_sequence(adev, golden_settings_gc_9_x_common,
 347                                         (const u32)ARRAY_SIZE(golden_settings_gc_9_x_common));
 348 }
 349
 350 static void gfx_v9_0_scratch_init(struct amdgpu_device *adev)
 351 {
 352         adev->gfx.scratch.num_reg = 8;
 353         adev->gfx.scratch.reg_base = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG0);
 354         adev->gfx.scratch.free_mask = (1u << adev->gfx.scratch.num_reg) - 1;
 355 }
 356
 357 static void gfx_v9_0_write_data_to_reg(struct amdgpu_ring *ring, int eng_sel,
 358                                        bool wc, uint32_t reg, uint32_t val)
 359 {
 360         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
 361         amdgpu_ring_write(ring, WRITE_DATA_ENGINE_SEL(eng_sel) |
 362                                 WRITE_DATA_DST_SEL(0) |
 363                                 (wc ? WR_CONFIRM : 0));
 364         amdgpu_ring_write(ring, reg);
 365         amdgpu_ring_write(ring, 0);
 366         amdgpu_ring_write(ring, val);
 367 }
 368
 369 static void gfx_v9_0_wait_reg_mem(struct amdgpu_ring *ring, int eng_sel,
 370                                   int mem_space, int opt, uint32_t addr0,
 371                                   uint32_t addr1, uint32_t ref, uint32_t mask,
 372                                   uint32_t inv)
 373 {
 374         amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
 375         amdgpu_ring_write(ring,
 376                                  /* memory (1) or register (0) */
 377                                  (WAIT_REG_MEM_MEM_SPACE(mem_space) |
 378                                  WAIT_REG_MEM_OPERATION(opt) | /* wait */
 379                                  WAIT_REG_MEM_FUNCTION(3) |  /* equal */
 380                                  WAIT_REG_MEM_ENGINE(eng_sel)));
 381
 382         if (mem_space)
 383                 BUG_ON(addr0 & 0x3); /* Dword align */
 384         amdgpu_ring_write(ring, addr0);
 385         amdgpu_ring_write(ring, addr1);
 386         amdgpu_ring_write(ring, ref);
 387         amdgpu_ring_write(ring, mask);
 388         amdgpu_ring_write(ring, inv); /* poll interval */
 389 }
 390
 391 static int gfx_v9_0_ring_test_ring(struct amdgpu_ring *ring)
 392 {
 393         struct amdgpu_device *adev = ring->adev;
 394         uint32_t scratch;
 395         uint32_t tmp = 0;
 396         unsigned i;
 397         int r;
 398
 399         r = amdgpu_gfx_scratch_get(adev, &scratch);
 400         if (r)
 401                 return r;
 402
 403         WREG32(scratch, 0xCAFEDEAD);
 404         r = amdgpu_ring_alloc(ring, 3);
 405         if (r)
 406                 goto error_free_scratch;
 407
 408         amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1));
 409         amdgpu_ring_write(ring, (scratch - PACKET3_SET_UCONFIG_REG_START));
 410         amdgpu_ring_write(ring, 0xDEADBEEF);
 411         amdgpu_ring_commit(ring);
 412
 413         for (i = 0; i < adev->usec_timeout; i++) {
 414                 tmp = RREG32(scratch);
 415                 if (tmp == 0xDEADBEEF)
 416                         break;
 417                 DRM_UDELAY(1);
 418         }
 419
 420         if (i >= adev->usec_timeout)
 421                 r = -ETIMEDOUT;
 422
 423 error_free_scratch:
 424         amdgpu_gfx_scratch_free(adev, scratch);
 425         return r;
 426 }
 427
 428 static int gfx_v9_0_ring_test_ib(struct amdgpu_ring *ring, long timeout)
 429 {
 430         struct amdgpu_device *adev = ring->adev;
 431         struct amdgpu_ib ib;
 432         struct dma_fence *f = NULL;
 433
 434         unsigned index;
 435         uint64_t gpu_addr;
 436         uint32_t tmp;
 437         long r;
 438
 439         r = amdgpu_device_wb_get(adev, &index);
 440         if (r)
 441                 return r;
 442
 443         gpu_addr = adev->wb.gpu_addr + (index * 4);
 444         adev->wb.wb[index] = cpu_to_le32(0xCAFEDEAD);
 445         memset(&ib, 0, sizeof(ib));
 446         r = amdgpu_ib_get(adev, NULL, 16, &ib);
 447         if (r)
 448                 goto err1;
 449
 450         ib.ptr[0] = PACKET3(PACKET3_WRITE_DATA, 3);
 451         ib.ptr[1] = WRITE_DATA_DST_SEL(5) | WR_CONFIRM;
 452         ib.ptr[2] = lower_32_bits(gpu_addr);
 453         ib.ptr[3] = upper_32_bits(gpu_addr);
 454         ib.ptr[4] = 0xDEADBEEF;
 455         ib.length_dw = 5;
 456
 457         r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
 458         if (r)
 459                 goto err2;
 460
 461         r = dma_fence_wait_timeout(f, false, timeout);
 462         if (r == 0) {
 463                 r = -ETIMEDOUT;
 464                 goto err2;
 465         } else if (r < 0) {
 466                 goto err2;
 467         }
 468
 469         tmp = adev->wb.wb[index];
 470         if (tmp == 0xDEADBEEF)
 471                 r = 0;
 472         else
 473                 r = -EINVAL;
 474
 475 err2:
 476         amdgpu_ib_free(adev, &ib, NULL);
 477         dma_fence_put(f);
 478 err1:
 479         amdgpu_device_wb_free(adev, index);
 480         return r;
 481 }
 482
 483
 484 static void gfx_v9_0_free_microcode(struct amdgpu_device *adev)
 485 {
 486         release_firmware(adev->gfx.pfp_fw);
 487         adev->gfx.pfp_fw = NULL;
 488         release_firmware(adev->gfx.me_fw);
 489         adev->gfx.me_fw = NULL;
 490         release_firmware(adev->gfx.ce_fw);
 491         adev->gfx.ce_fw = NULL;
 492         release_firmware(adev->gfx.rlc_fw);
 493         adev->gfx.rlc_fw = NULL;
 494         release_firmware(adev->gfx.mec_fw);
 495         adev->gfx.mec_fw = NULL;
 496         release_firmware(adev->gfx.mec2_fw);
 497         adev->gfx.mec2_fw = NULL;
 498
 499         kfree(adev->gfx.rlc.register_list_format);
 500 }
 501
 502 static void gfx_v9_0_init_rlc_ext_microcode(struct amdgpu_device *adev)
 503 {
 504         const struct rlc_firmware_header_v2_1 *rlc_hdr;
 505
 506         rlc_hdr = (const struct rlc_firmware_header_v2_1 *)adev->gfx.rlc_fw->data;
 507         adev->gfx.rlc_srlc_fw_version = le32_to_cpu(rlc_hdr->save_restore_list_cntl_ucode_ver);
 508         adev->gfx.rlc_srlc_feature_version = le32_to_cpu(rlc_hdr->save_restore_list_cntl_feature_ver);
 509         adev->gfx.rlc.save_restore_list_cntl_size_bytes = le32_to_cpu(rlc_hdr->save_restore_list_cntl_size_bytes);
 510         adev->gfx.rlc.save_restore_list_cntl = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_list_cntl_offset_bytes);
 511         adev->gfx.rlc_srlg_fw_version = le32_to_cpu(rlc_hdr->save_restore_list_gpm_ucode_ver);
 512         adev->gfx.rlc_srlg_feature_version = le32_to_cpu(rlc_hdr->save_restore_list_gpm_feature_ver);
 513         adev->gfx.rlc.save_restore_list_gpm_size_bytes = le32_to_cpu(rlc_hdr->save_restore_list_gpm_size_bytes);
 514         adev->gfx.rlc.save_restore_list_gpm = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_list_gpm_offset_bytes);
 515         adev->gfx.rlc_srls_fw_version = le32_to_cpu(rlc_hdr->save_restore_list_srm_ucode_ver);
 516         adev->gfx.rlc_srls_feature_version = le32_to_cpu(rlc_hdr->save_restore_list_srm_feature_ver);
 517         adev->gfx.rlc.save_restore_list_srm_size_bytes = le32_to_cpu(rlc_hdr->save_restore_list_srm_size_bytes);
 518         adev->gfx.rlc.save_restore_list_srm = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_list_srm_offset_bytes);
 519         adev->gfx.rlc.reg_list_format_direct_reg_list_length =
 520                         le32_to_cpu(rlc_hdr->reg_list_format_direct_reg_list_length);
 521 }
 522
 523 static void gfx_v9_0_check_fw_write_wait(struct amdgpu_device *adev)
 524 {
 525         adev->gfx.me_fw_write_wait = false;
 526         adev->gfx.mec_fw_write_wait = false;
 527
 528         switch (adev->asic_type) {
 529         case CHIP_VEGA10:
 530                 if ((adev->gfx.me_fw_version >= 0x0000009c) &&
 531                     (adev->gfx.me_feature_version >= 42) &&
 532                     (adev->gfx.pfp_fw_version >=  0x000000b1) &&
 533                     (adev->gfx.pfp_feature_version >= 42))
 534                         adev->gfx.me_fw_write_wait = true;
 535
 536                 if ((adev->gfx.mec_fw_version >=  0x00000193) &&
 537                     (adev->gfx.mec_feature_version >= 42))
 538                         adev->gfx.mec_fw_write_wait = true;
 539                 break;
 540         case CHIP_VEGA12:
 541                 if ((adev->gfx.me_fw_version >= 0x0000009c) &&
 542                     (adev->gfx.me_feature_version >= 44) &&
 543                     (adev->gfx.pfp_fw_version >=  0x000000b2) &&
 544                     (adev->gfx.pfp_feature_version >= 44))
 545                         adev->gfx.me_fw_write_wait = true;
 546
 547                 if ((adev->gfx.mec_fw_version >=  0x00000196) &&
 548                     (adev->gfx.mec_feature_version >= 44))
 549                         adev->gfx.mec_fw_write_wait = true;
 550                 break;
 551         case CHIP_VEGA20:
 552                 if ((adev->gfx.me_fw_version >= 0x0000009c) &&
 553                     (adev->gfx.me_feature_version >= 44) &&
 554                     (adev->gfx.pfp_fw_version >=  0x000000b2) &&
 555                     (adev->gfx.pfp_feature_version >= 44))
 556                         adev->gfx.me_fw_write_wait = true;
 557
 558                 if ((adev->gfx.mec_fw_version >=  0x00000197) &&
 559                     (adev->gfx.mec_feature_version >= 44))
 560                         adev->gfx.mec_fw_write_wait = true;
 561                 break;
 562         case CHIP_RAVEN:
 563                 if ((adev->gfx.me_fw_version >= 0x0000009c) &&
 564                     (adev->gfx.me_feature_version >= 42) &&
 565                     (adev->gfx.pfp_fw_version >=  0x000000b1) &&
 566                     (adev->gfx.pfp_feature_version >= 42))
 567                         adev->gfx.me_fw_write_wait = true;
 568
 569                 if ((adev->gfx.mec_fw_version >=  0x00000192) &&
 570                     (adev->gfx.mec_feature_version >= 42))
 571                         adev->gfx.mec_fw_write_wait = true;
 572                 break;
 573         default:
 574                 break;
 575         }
 576 }
 577
 578 static int gfx_v9_0_init_microcode(struct amdgpu_device *adev)
 579 {
 580         const char *chip_name;
 581         char fw_name[30];
 582         int err;
 583         struct amdgpu_firmware_info *info = NULL;
 584         const struct common_firmware_header *header = NULL;
 585         const struct gfx_firmware_header_v1_0 *cp_hdr;
 586         const struct rlc_firmware_header_v2_0 *rlc_hdr;
 587         unsigned int *tmp = NULL;
 588         unsigned int i = 0;
 589         uint16_t version_major;
 590         uint16_t version_minor;
 591
 592         DRM_DEBUG("\n");
 593
 594         switch (adev->asic_type) {
 595         case CHIP_VEGA10:
 596                 chip_name = "vega10";
 597                 break;
 598         case CHIP_VEGA12:
 599                 chip_name = "vega12";
 600                 break;
 601         case CHIP_VEGA20:
 602                 chip_name = "vega20";
 603                 break;
 604         case CHIP_RAVEN:
 605                 if (adev->rev_id >= 8)
 606                         chip_name = "raven2";
 607                 else if (adev->pdev->device == 0x15d8)
 608                         chip_name = "picasso";
 609                 else
 610                         chip_name = "raven";
 611                 break;
 612         default:
 613                 BUG();
 614         }
 615
 616         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_pfp.bin", chip_name);
 617         err = request_firmware(&adev->gfx.pfp_fw, fw_name, adev->dev);
 618         if (err)
 619                 goto out;
 620         err = amdgpu_ucode_validate(adev->gfx.pfp_fw);
 621         if (err)
 622                 goto out;
 623         cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data;
 624         adev->gfx.pfp_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
 625         adev->gfx.pfp_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
 626
 627         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_me.bin", chip_name);
 628         err = request_firmware(&adev->gfx.me_fw, fw_name, adev->dev);
 629         if (err)
 630                 goto out;
 631         err = amdgpu_ucode_validate(adev->gfx.me_fw);
 632         if (err)
 633                 goto out;
 634         cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data;
 635         adev->gfx.me_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
 636         adev->gfx.me_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
 637
 638         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ce.bin", chip_name);
 639         err = request_firmware(&adev->gfx.ce_fw, fw_name, adev->dev);
 640         if (err)
 641                 goto out;
 642         err = amdgpu_ucode_validate(adev->gfx.ce_fw);
 643         if (err)
 644                 goto out;
 645         cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data;
 646         adev->gfx.ce_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
 647         adev->gfx.ce_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
 648
 649         /*
 650          * For Picasso && AM4 SOCKET board, we use picasso_rlc_am4.bin
 651          * instead of picasso_rlc.bin.
 652          * Judgment method:
 653          * PCO AM4: revision >= 0xC8 && revision <= 0xCF
 654          *          or revision >= 0xD8 && revision <= 0xDF
 655          * otherwise is PCO FP5
 656          */
 657         if (!strcmp(chip_name, "picasso") &&
 658                 (((adev->pdev->revision >= 0xC8) && (adev->pdev->revision <= 0xCF)) ||
 659                 ((adev->pdev->revision >= 0xD8) && (adev->pdev->revision <= 0xDF))))
 660                 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_rlc_am4.bin", chip_name);
 661         else
 662                 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_rlc.bin", chip_name);
 663         err = request_firmware(&adev->gfx.rlc_fw, fw_name, adev->dev);
 664         if (err)
 665                 goto out;
 666         err = amdgpu_ucode_validate(adev->gfx.rlc_fw);
 667         rlc_hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data;
 668
 669         version_major = le16_to_cpu(rlc_hdr->header.header_version_major);
 670         version_minor = le16_to_cpu(rlc_hdr->header.header_version_minor);
 671         if (version_major == 2 && version_minor == 1)
 672                 adev->gfx.rlc.is_rlc_v2_1 = true;
 673
 674         adev->gfx.rlc_fw_version = le32_to_cpu(rlc_hdr->header.ucode_version);
 675         adev->gfx.rlc_feature_version = le32_to_cpu(rlc_hdr->ucode_feature_version);
 676         adev->gfx.rlc.save_and_restore_offset =
 677                         le32_to_cpu(rlc_hdr->save_and_restore_offset);
 678         adev->gfx.rlc.clear_state_descriptor_offset =
 679                         le32_to_cpu(rlc_hdr->clear_state_descriptor_offset);
 680         adev->gfx.rlc.avail_scratch_ram_locations =
 681                         le32_to_cpu(rlc_hdr->avail_scratch_ram_locations);
 682         adev->gfx.rlc.reg_restore_list_size =
 683                         le32_to_cpu(rlc_hdr->reg_restore_list_size);
 684         adev->gfx.rlc.reg_list_format_start =
 685                         le32_to_cpu(rlc_hdr->reg_list_format_start);
 686         adev->gfx.rlc.reg_list_format_separate_start =
 687                         le32_to_cpu(rlc_hdr->reg_list_format_separate_start);
 688         adev->gfx.rlc.starting_offsets_start =
 689                         le32_to_cpu(rlc_hdr->starting_offsets_start);
 690         adev->gfx.rlc.reg_list_format_size_bytes =
 691                         le32_to_cpu(rlc_hdr->reg_list_format_size_bytes);
 692         adev->gfx.rlc.reg_list_size_bytes =
 693                         le32_to_cpu(rlc_hdr->reg_list_size_bytes);
 694         adev->gfx.rlc.register_list_format =
 695                         kmalloc(adev->gfx.rlc.reg_list_format_size_bytes +
 696                                 adev->gfx.rlc.reg_list_size_bytes, GFP_KERNEL);
 697         if (!adev->gfx.rlc.register_list_format) {
 698                 err = -ENOMEM;
 699                 goto out;
 700         }
 701
 702         tmp = (unsigned int *)((uintptr_t)rlc_hdr +
 703                         le32_to_cpu(rlc_hdr->reg_list_format_array_offset_bytes));
 704         for (i = 0 ; i < (adev->gfx.rlc.reg_list_format_size_bytes >> 2); i++)
 705                 adev->gfx.rlc.register_list_format[i] = le32_to_cpu(tmp[i]);
 706
 707         adev->gfx.rlc.register_restore = adev->gfx.rlc.register_list_format + i;
 708
 709         tmp = (unsigned int *)((uintptr_t)rlc_hdr +
 710                         le32_to_cpu(rlc_hdr->reg_list_array_offset_bytes));
 711         for (i = 0 ; i < (adev->gfx.rlc.reg_list_size_bytes >> 2); i++)
 712                 adev->gfx.rlc.register_restore[i] = le32_to_cpu(tmp[i]);
 713
 714         if (adev->gfx.rlc.is_rlc_v2_1)
 715                 gfx_v9_0_init_rlc_ext_microcode(adev);
 716
 717         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec.bin", chip_name);
 718         err = request_firmware(&adev->gfx.mec_fw, fw_name, adev->dev);
 719         if (err)
 720                 goto out;
 721         err = amdgpu_ucode_validate(adev->gfx.mec_fw);
 722         if (err)
 723                 goto out;
 724         cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
 725         adev->gfx.mec_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
 726         adev->gfx.mec_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
 727
 728
 729         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec2.bin", chip_name);
 730         err = request_firmware(&adev->gfx.mec2_fw, fw_name, adev->dev);
 731         if (!err) {
 732                 err = amdgpu_ucode_validate(adev->gfx.mec2_fw);
 733                 if (err)
 734                         goto out;
 735                 cp_hdr = (const struct gfx_firmware_header_v1_0 *)
 736                 adev->gfx.mec2_fw->data;
 737                 adev->gfx.mec2_fw_version =
 738                 le32_to_cpu(cp_hdr->header.ucode_version);
 739                 adev->gfx.mec2_feature_version =
 740                 le32_to_cpu(cp_hdr->ucode_feature_version);
 741         } else {
 742                 err = 0;
 743                 adev->gfx.mec2_fw = NULL;
 744         }
 745
 746         if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
 747                 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_PFP];
 748                 info->ucode_id = AMDGPU_UCODE_ID_CP_PFP;
 749                 info->fw = adev->gfx.pfp_fw;
 750                 header = (const struct common_firmware_header *)info->fw->data;
 751                 adev->firmware.fw_size +=
 752                         ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
 753
 754                 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_ME];
 755                 info->ucode_id = AMDGPU_UCODE_ID_CP_ME;
 756                 info->fw = adev->gfx.me_fw;
 757                 header = (const struct common_firmware_header *)info->fw->data;
 758                 adev->firmware.fw_size +=
 759                         ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
 760
 761                 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_CE];
 762                 info->ucode_id = AMDGPU_UCODE_ID_CP_CE;
 763                 info->fw = adev->gfx.ce_fw;
 764                 header = (const struct common_firmware_header *)info->fw->data;
 765                 adev->firmware.fw_size +=
 766                         ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
 767
 768                 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_G];
 769                 info->ucode_id = AMDGPU_UCODE_ID_RLC_G;
 770                 info->fw = adev->gfx.rlc_fw;
 771                 header = (const struct common_firmware_header *)info->fw->data;
 772                 adev->firmware.fw_size +=
 773                         ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
 774
 775                 if (adev->gfx.rlc.is_rlc_v2_1 &&
 776                     adev->gfx.rlc.save_restore_list_cntl_size_bytes &&
 777                     adev->gfx.rlc.save_restore_list_gpm_size_bytes &&
 778                     adev->gfx.rlc.save_restore_list_srm_size_bytes) {
 779                         info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL];
 780                         info->ucode_id = AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL;
 781                         info->fw = adev->gfx.rlc_fw;
 782                         adev->firmware.fw_size +=
 783                                 ALIGN(adev->gfx.rlc.save_restore_list_cntl_size_bytes, PAGE_SIZE);
 784
 785                         info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM];
 786                         info->ucode_id = AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM;
 787                         info->fw = adev->gfx.rlc_fw;
 788                         adev->firmware.fw_size +=
 789                                 ALIGN(adev->gfx.rlc.save_restore_list_gpm_size_bytes, PAGE_SIZE);
 790
 791                         info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM];
 792                         info->ucode_id = AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM;
 793                         info->fw = adev->gfx.rlc_fw;
 794                         adev->firmware.fw_size +=
 795                                 ALIGN(adev->gfx.rlc.save_restore_list_srm_size_bytes, PAGE_SIZE);
 796                 }
 797
 798                 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC1];
 799                 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC1;
 800                 info->fw = adev->gfx.mec_fw;
 801                 header = (const struct common_firmware_header *)info->fw->data;
 802                 cp_hdr = (const struct gfx_firmware_header_v1_0 *)info->fw->data;
 803                 adev->firmware.fw_size +=
 804                         ALIGN(le32_to_cpu(header->ucode_size_bytes) - le32_to_cpu(cp_hdr->jt_size) * 4, PAGE_SIZE);
 805
 806                 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC1_JT];
 807                 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC1_JT;
 808                 info->fw = adev->gfx.mec_fw;
 809                 adev->firmware.fw_size +=
 810                         ALIGN(le32_to_cpu(cp_hdr->jt_size) * 4, PAGE_SIZE);
 811
 812                 if (adev->gfx.mec2_fw) {
 813                         info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC2];
 814                         info->ucode_id = AMDGPU_UCODE_ID_CP_MEC2;
 815                         info->fw = adev->gfx.mec2_fw;
 816                         header = (const struct common_firmware_header *)info->fw->data;
 817                         cp_hdr = (const struct gfx_firmware_header_v1_0 *)info->fw->data;
 818                         adev->firmware.fw_size +=
 819                                 ALIGN(le32_to_cpu(header->ucode_size_bytes) - le32_to_cpu(cp_hdr->jt_size) * 4, PAGE_SIZE);
 820                         info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC2_JT];
 821                         info->ucode_id = AMDGPU_UCODE_ID_CP_MEC2_JT;
 822                         info->fw = adev->gfx.mec2_fw;
 823                         adev->firmware.fw_size +=
 824                                 ALIGN(le32_to_cpu(cp_hdr->jt_size) * 4, PAGE_SIZE);
 825                 }
 826
 827         }
 828
 829 out:
 830         gfx_v9_0_check_fw_write_wait(adev);
 831         if (err) {
 832                 dev_err(adev->dev,
 833                         "gfx9: Failed to load firmware \"%s\"\n",
 834                         fw_name);
 835                 release_firmware(adev->gfx.pfp_fw);
 836                 adev->gfx.pfp_fw = NULL;
 837                 release_firmware(adev->gfx.me_fw);
 838                 adev->gfx.me_fw = NULL;
 839                 release_firmware(adev->gfx.ce_fw);
 840                 adev->gfx.ce_fw = NULL;
 841                 release_firmware(adev->gfx.rlc_fw);
 842                 adev->gfx.rlc_fw = NULL;
 843                 release_firmware(adev->gfx.mec_fw);
 844                 adev->gfx.mec_fw = NULL;
 845                 release_firmware(adev->gfx.mec2_fw);
 846                 adev->gfx.mec2_fw = NULL;
 847         }
 848         return err;
 849 }
 850
 851 static u32 gfx_v9_0_get_csb_size(struct amdgpu_device *adev)
 852 {
 853         u32 count = 0;
 854         const struct cs_section_def *sect = NULL;
 855         const struct cs_extent_def *ext = NULL;
 856
 857         /* begin clear state */
 858         count += 2;
 859         /* context control state */
 860         count += 3;
 861
 862         for (sect = gfx9_cs_data; sect->section != NULL; ++sect) {
 863                 for (ext = sect->section; ext->extent != NULL; ++ext) {
 864                         if (sect->id == SECT_CONTEXT)
 865                                 count += 2 + ext->reg_count;
 866                         else
 867                                 return 0;
 868                 }
 869         }
 870
 871         /* end clear state */
 872         count += 2;
 873         /* clear state */
 874         count += 2;
 875
 876         return count;
 877 }
 878
 879 static void gfx_v9_0_get_csb_buffer(struct amdgpu_device *adev,
 880                                     volatile u32 *buffer)
 881 {
 882         u32 count = 0, i;
 883         const struct cs_section_def *sect = NULL;
 884         const struct cs_extent_def *ext = NULL;
 885
 886         if (adev->gfx.rlc.cs_data == NULL)
 887                 return;
 888         if (buffer == NULL)
 889                 return;
 890
 891         buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));
 892         buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
 893
 894         buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CONTEXT_CONTROL, 1));
 895         buffer[count++] = cpu_to_le32(0x80000000);
 896         buffer[count++] = cpu_to_le32(0x80000000);
 897
 898         for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) {
 899                 for (ext = sect->section; ext->extent != NULL; ++ext) {
 900                         if (sect->id == SECT_CONTEXT) {
 901                                 buffer[count++] =
 902                                         cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count));
 903                                 buffer[count++] = cpu_to_le32(ext->reg_index -
 904                                                 PACKET3_SET_CONTEXT_REG_START);
 905                                 for (i = 0; i < ext->reg_count; i++)
 906                                         buffer[count++] = cpu_to_le32(ext->extent[i]);
 907                         } else {
 908                                 return;
 909                         }
 910                 }
 911         }
 912
 913         buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));
 914         buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_END_CLEAR_STATE);
 915
 916         buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CLEAR_STATE, 0));
 917         buffer[count++] = cpu_to_le32(0);
 918 }
 919
 920 static void gfx_v9_0_init_always_on_cu_mask(struct amdgpu_device *adev)
 921 {
 922         struct amdgpu_cu_info *cu_info = &adev->gfx.cu_info;
 923         uint32_t pg_always_on_cu_num = 2;
 924         uint32_t always_on_cu_num;
 925         uint32_t i, j, k;
 926         uint32_t mask, cu_bitmap, counter;
 927
 928         if (adev->flags & AMD_IS_APU)
 929                 always_on_cu_num = 4;
 930         else if (adev->asic_type == CHIP_VEGA12)
 931                 always_on_cu_num = 8;
 932         else
 933                 always_on_cu_num = 12;
 934
 935         mutex_lock(&adev->grbm_idx_mutex);
 936         for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
 937                 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
 938                         mask = 1;
 939                         cu_bitmap = 0;
 940                         counter = 0;
 941                         gfx_v9_0_select_se_sh(adev, i, j, 0xffffffff);
 942
 943                         for (k = 0; k < adev->gfx.config.max_cu_per_sh; k ++) {
 944                                 if (cu_info->bitmap[i][j] & mask) {
 945                                         if (counter == pg_always_on_cu_num)
 946                                                 WREG32_SOC15(GC, 0, mmRLC_PG_ALWAYS_ON_CU_MASK, cu_bitmap);
 947                                         if (counter < always_on_cu_num)
 948                                                 cu_bitmap |= mask;
 949                                         else
 950                                                 break;
 951                                         counter++;
 952                                 }
 953                                 mask <<= 1;
 954                         }
 955
 956                         WREG32_SOC15(GC, 0, mmRLC_LB_ALWAYS_ACTIVE_CU_MASK, cu_bitmap);
 957                         cu_info->ao_cu_bitmap[i][j] = cu_bitmap;
 958                 }
 959         }
 960         gfx_v9_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
 961         mutex_unlock(&adev->grbm_idx_mutex);
 962 }
 963
 964 static void gfx_v9_0_init_lbpw(struct amdgpu_device *adev)
 965 {
 966         uint32_t data;
 967
 968         /* set mmRLC_LB_THR_CONFIG_1/2/3/4 */
 969         WREG32_SOC15(GC, 0, mmRLC_LB_THR_CONFIG_1, 0x0000007F);
 970         WREG32_SOC15(GC, 0, mmRLC_LB_THR_CONFIG_2, 0x0333A5A7);
 971         WREG32_SOC15(GC, 0, mmRLC_LB_THR_CONFIG_3, 0x00000077);
 972         WREG32_SOC15(GC, 0, mmRLC_LB_THR_CONFIG_4, (0x30 | 0x40 << 8 | 0x02FA << 16));
 973
 974         /* set mmRLC_LB_CNTR_INIT = 0x0000_0000 */
 975         WREG32_SOC15(GC, 0, mmRLC_LB_CNTR_INIT, 0x00000000);
 976
 977         /* set mmRLC_LB_CNTR_MAX = 0x0000_0500 */
 978         WREG32_SOC15(GC, 0, mmRLC_LB_CNTR_MAX, 0x00000500);
 979
 980         mutex_lock(&adev->grbm_idx_mutex);
 981         /* set mmRLC_LB_INIT_CU_MASK thru broadcast mode to enable all SE/SH*/
 982         gfx_v9_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
 983         WREG32_SOC15(GC, 0, mmRLC_LB_INIT_CU_MASK, 0xffffffff);
 984
 985         /* set mmRLC_LB_PARAMS = 0x003F_1006 */
 986         data = REG_SET_FIELD(0, RLC_LB_PARAMS, FIFO_SAMPLES, 0x0003);
 987         data |= REG_SET_FIELD(data, RLC_LB_PARAMS, PG_IDLE_SAMPLES, 0x0010);
 988         data |= REG_SET_FIELD(data, RLC_LB_PARAMS, PG_IDLE_SAMPLE_INTERVAL, 0x033F);
 989         WREG32_SOC15(GC, 0, mmRLC_LB_PARAMS, data);
 990
 991         /* set mmRLC_GPM_GENERAL_7[31-16] = 0x00C0 */
 992         data = RREG32_SOC15(GC, 0, mmRLC_GPM_GENERAL_7);
 993         data &= 0x0000FFFF;
 994         data |= 0x00C00000;
 995         WREG32_SOC15(GC, 0, mmRLC_GPM_GENERAL_7, data);
 996
 997         /*
 998          * RLC_LB_ALWAYS_ACTIVE_CU_MASK = 0xF (4 CUs AON for Raven),
 999          * programmed in gfx_v9_0_init_always_on_cu_mask()
1000          */
1001
1002         /* set RLC_LB_CNTL = 0x8000_0095, 31 bit is reserved,
1003          * but used for RLC_LB_CNTL configuration */
1004         data = RLC_LB_CNTL__LB_CNT_SPIM_ACTIVE_MASK;
1005         data |= REG_SET_FIELD(data, RLC_LB_CNTL, CU_MASK_USED_OFF_HYST, 0x09);
1006         data |= REG_SET_FIELD(data, RLC_LB_CNTL, RESERVED, 0x80000);
1007         WREG32_SOC15(GC, 0, mmRLC_LB_CNTL, data);
1008         mutex_unlock(&adev->grbm_idx_mutex);
1009
1010         gfx_v9_0_init_always_on_cu_mask(adev);
1011 }
1012
1013 static void gfx_v9_4_init_lbpw(struct amdgpu_device *adev)
1014 {
1015         uint32_t data;
1016
1017         /* set mmRLC_LB_THR_CONFIG_1/2/3/4 */
1018         WREG32_SOC15(GC, 0, mmRLC_LB_THR_CONFIG_1, 0x0000007F);
1019         WREG32_SOC15(GC, 0, mmRLC_LB_THR_CONFIG_2, 0x033388F8);
1020         WREG32_SOC15(GC, 0, mmRLC_LB_THR_CONFIG_3, 0x00000077);
1021         WREG32_SOC15(GC, 0, mmRLC_LB_THR_CONFIG_4, (0x10 | 0x27 << 8 | 0x02FA << 16));
1022
1023         /* set mmRLC_LB_CNTR_INIT = 0x0000_0000 */
1024         WREG32_SOC15(GC, 0, mmRLC_LB_CNTR_INIT, 0x00000000);
1025
1026         /* set mmRLC_LB_CNTR_MAX = 0x0000_0500 */
1027         WREG32_SOC15(GC, 0, mmRLC_LB_CNTR_MAX, 0x00000800);
1028
1029         mutex_lock(&adev->grbm_idx_mutex);
1030         /* set mmRLC_LB_INIT_CU_MASK thru broadcast mode to enable all SE/SH*/
1031         gfx_v9_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
1032         WREG32_SOC15(GC, 0, mmRLC_LB_INIT_CU_MASK, 0xffffffff);
1033
1034         /* set mmRLC_LB_PARAMS = 0x003F_1006 */
1035         data = REG_SET_FIELD(0, RLC_LB_PARAMS, FIFO_SAMPLES, 0x0003);
1036         data |= REG_SET_FIELD(data, RLC_LB_PARAMS, PG_IDLE_SAMPLES, 0x0010);
1037         data |= REG_SET_FIELD(data, RLC_LB_PARAMS, PG_IDLE_SAMPLE_INTERVAL, 0x033F);
1038         WREG32_SOC15(GC, 0, mmRLC_LB_PARAMS, data);
1039
1040         /* set mmRLC_GPM_GENERAL_7[31-16] = 0x00C0 */
1041         data = RREG32_SOC15(GC, 0, mmRLC_GPM_GENERAL_7);
1042         data &= 0x0000FFFF;
1043         data |= 0x00C00000;
1044         WREG32_SOC15(GC, 0, mmRLC_GPM_GENERAL_7, data);
1045
1046         /*
1047          * RLC_LB_ALWAYS_ACTIVE_CU_MASK = 0xFFF (12 CUs AON),
1048          * programmed in gfx_v9_0_init_always_on_cu_mask()
1049          */
1050
1051         /* set RLC_LB_CNTL = 0x8000_0095, 31 bit is reserved,
1052          * but used for RLC_LB_CNTL configuration */
1053         data = RLC_LB_CNTL__LB_CNT_SPIM_ACTIVE_MASK;
1054         data |= REG_SET_FIELD(data, RLC_LB_CNTL, CU_MASK_USED_OFF_HYST, 0x09);
1055         data |= REG_SET_FIELD(data, RLC_LB_CNTL, RESERVED, 0x80000);
1056         WREG32_SOC15(GC, 0, mmRLC_LB_CNTL, data);
1057         mutex_unlock(&adev->grbm_idx_mutex);
1058
1059         gfx_v9_0_init_always_on_cu_mask(adev);
1060 }
1061
1062 static void gfx_v9_0_enable_lbpw(struct amdgpu_device *adev, bool enable)
1063 {
1064         WREG32_FIELD15(GC, 0, RLC_LB_CNTL, LOAD_BALANCE_ENABLE, enable ? 1 : 0);
1065 }
1066
1067 static int gfx_v9_0_cp_jump_table_num(struct amdgpu_device *adev)
1068 {
1069         return 5;
1070 }
1071
1072 static int gfx_v9_0_rlc_init(struct amdgpu_device *adev)
1073 {
1074         const struct cs_section_def *cs_data;
1075         int r;
1076
1077         adev->gfx.rlc.cs_data = gfx9_cs_data;
1078
1079         cs_data = adev->gfx.rlc.cs_data;
1080
1081         if (cs_data) {
1082                 /* init clear state block */
1083                 r = amdgpu_gfx_rlc_init_csb(adev);
1084                 if (r)
1085                         return r;
1086         }
1087
1088         if (adev->asic_type == CHIP_RAVEN) {
1089                 /* TODO: double check the cp_table_size for RV */
1090                 adev->gfx.rlc.cp_table_size = ALIGN(96 * 5 * 4, 2048) + (64 * 1024); /* JT + GDS */
1091                 r = amdgpu_gfx_rlc_init_cpt(adev);
1092                 if (r)
1093                         return r;
1094         }
1095
1096         switch (adev->asic_type) {
1097         case CHIP_RAVEN:
1098                 gfx_v9_0_init_lbpw(adev);
1099                 break;
1100         case CHIP_VEGA20:
1101                 gfx_v9_4_init_lbpw(adev);
1102                 break;
1103         default:
1104                 break;
1105         }
1106
1107         return 0;
1108 }
1109
1110 static int gfx_v9_0_csb_vram_pin(struct amdgpu_device *adev)
1111 {
1112         int r;
1113
1114         r = amdgpu_bo_reserve(adev->gfx.rlc.clear_state_obj, false);
1115         if (unlikely(r != 0))
1116                 return r;
1117
1118         r = amdgpu_bo_pin(adev->gfx.rlc.clear_state_obj,
1119                         AMDGPU_GEM_DOMAIN_VRAM);
1120         if (!r)
1121                 adev->gfx.rlc.clear_state_gpu_addr =
1122                         amdgpu_bo_gpu_offset(adev->gfx.rlc.clear_state_obj);
1123
1124         amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj);
1125
1126         return r;
1127 }
1128
1129 static void gfx_v9_0_csb_vram_unpin(struct amdgpu_device *adev)
1130 {
1131         int r;
1132
1133         if (!adev->gfx.rlc.clear_state_obj)
1134                 return;
1135
1136         r = amdgpu_bo_reserve(adev->gfx.rlc.clear_state_obj, true);
1137         if (likely(r == 0)) {
1138                 amdgpu_bo_unpin(adev->gfx.rlc.clear_state_obj);
1139                 amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj);
1140         }
1141 }
1142
1143 static void gfx_v9_0_mec_fini(struct amdgpu_device *adev)
1144 {
1145         amdgpu_bo_free_kernel(&adev->gfx.mec.hpd_eop_obj, NULL, NULL);
1146         amdgpu_bo_free_kernel(&adev->gfx.mec.mec_fw_obj, NULL, NULL);
1147 }
1148
1149 static int gfx_v9_0_mec_init(struct amdgpu_device *adev)
1150 {
1151         int r;
1152         u32 *hpd;
1153         const __le32 *fw_data;
1154         unsigned fw_size;
1155         u32 *fw;
1156         size_t mec_hpd_size;
1157
1158         const struct gfx_firmware_header_v1_0 *mec_hdr;
1159
1160         bitmap_zero(adev->gfx.mec.queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES);
1161
1162         /* take ownership of the relevant compute queues */
1163         amdgpu_gfx_compute_queue_acquire(adev);
1164         mec_hpd_size = adev->gfx.num_compute_rings * GFX9_MEC_HPD_SIZE;
1165
1166         r = amdgpu_bo_create_reserved(adev, mec_hpd_size, PAGE_SIZE,
1167                                       AMDGPU_GEM_DOMAIN_VRAM,
1168                                       &adev->gfx.mec.hpd_eop_obj,
1169                                       &adev->gfx.mec.hpd_eop_gpu_addr,
1170                                       (void **)&hpd);
1171         if (r) {
1172                 dev_warn(adev->dev, "(%d) create HDP EOP bo failed\n", r);
1173                 gfx_v9_0_mec_fini(adev);
1174                 return r;
1175         }
1176
1177         memset(hpd, 0, adev->gfx.mec.hpd_eop_obj->tbo.mem.size);
1178
1179         amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj);
1180         amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj);
1181
1182         mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
1183
1184         fw_data = (const __le32 *)
1185                 (adev->gfx.mec_fw->data +
1186                  le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes));
1187         fw_size = le32_to_cpu(mec_hdr->header.ucode_size_bytes) / 4;
1188
1189         r = amdgpu_bo_create_reserved(adev, mec_hdr->header.ucode_size_bytes,
1190                                       PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,
1191                                       &adev->gfx.mec.mec_fw_obj,
1192                                       &adev->gfx.mec.mec_fw_gpu_addr,
1193                                       (void **)&fw);
1194         if (r) {
1195                 dev_warn(adev->dev, "(%d) create mec firmware bo failed\n", r);
1196                 gfx_v9_0_mec_fini(adev);
1197                 return r;
1198         }
1199
1200         memcpy(fw, fw_data, fw_size);
1201
1202         amdgpu_bo_kunmap(adev->gfx.mec.mec_fw_obj);
1203         amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_obj);
1204
1205         return 0;
1206 }
1207
1208 static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t address)
1209 {
1210         WREG32_SOC15(GC, 0, mmSQ_IND_INDEX,
1211                 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) |
1212                 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) |
1213                 (address << SQ_IND_INDEX__INDEX__SHIFT) |
1214                 (SQ_IND_INDEX__FORCE_READ_MASK));
1215         return RREG32_SOC15(GC, 0, mmSQ_IND_DATA);
1216 }
1217
1218 static void wave_read_regs(struct amdgpu_device *adev, uint32_t simd,
1219                            uint32_t wave, uint32_t thread,
1220                            uint32_t regno, uint32_t num, uint32_t *out)
1221 {
1222         WREG32_SOC15(GC, 0, mmSQ_IND_INDEX,
1223                 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) |
1224                 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) |
1225                 (regno << SQ_IND_INDEX__INDEX__SHIFT) |
1226                 (thread << SQ_IND_INDEX__THREAD_ID__SHIFT) |
1227                 (SQ_IND_INDEX__FORCE_READ_MASK) |
1228                 (SQ_IND_INDEX__AUTO_INCR_MASK));
1229         while (num--)
1230                 *(out++) = RREG32_SOC15(GC, 0, mmSQ_IND_DATA);
1231 }
1232
1233 static void gfx_v9_0_read_wave_data(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t *dst, int *no_fields)
1234 {
1235         /* type 1 wave data */
1236         dst[(*no_fields)++] = 1;
1237         dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_STATUS);
1238         dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_LO);
1239         dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_HI);
1240         dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_LO);
1241         dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_HI);
1242         dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_HW_ID);
1243         dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_INST_DW0);
1244         dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_INST_DW1);
1245         dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_GPR_ALLOC);
1246         dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_LDS_ALLOC);
1247         dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TRAPSTS);
1248         dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_IB_STS);
1249         dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_IB_DBG0);
1250         dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_M0);
1251 }
1252
1253 static void gfx_v9_0_read_wave_sgprs(struct amdgpu_device *adev, uint32_t simd,
1254                                      uint32_t wave, uint32_t start,
1255                                      uint32_t size, uint32_t *dst)
1256 {
1257         wave_read_regs(
1258                 adev, simd, wave, 0,
1259                 start + SQIND_WAVE_SGPRS_OFFSET, size, dst);
1260 }
1261
1262 static void gfx_v9_0_read_wave_vgprs(struct amdgpu_device *adev, uint32_t simd,
1263                                      uint32_t wave, uint32_t thread,
1264                                      uint32_t start, uint32_t size,
1265                                      uint32_t *dst)
1266 {
1267         wave_read_regs(
1268                 adev, simd, wave, thread,
1269                 start + SQIND_WAVE_VGPRS_OFFSET, size, dst);
1270 }
1271
1272 static void gfx_v9_0_select_me_pipe_q(struct amdgpu_device *adev,
1273                                   u32 me, u32 pipe, u32 q)
1274 {
1275         soc15_grbm_select(adev, me, pipe, q, 0);
1276 }
1277
1278 static const struct amdgpu_gfx_funcs gfx_v9_0_gfx_funcs = {
1279         .get_gpu_clock_counter = &gfx_v9_0_get_gpu_clock_counter,
1280         .select_se_sh = &gfx_v9_0_select_se_sh,
1281         .read_wave_data = &gfx_v9_0_read_wave_data,
1282         .read_wave_sgprs = &gfx_v9_0_read_wave_sgprs,
1283         .read_wave_vgprs = &gfx_v9_0_read_wave_vgprs,
1284         .select_me_pipe_q = &gfx_v9_0_select_me_pipe_q
1285 };
1286
1287 static int gfx_v9_0_gpu_early_init(struct amdgpu_device *adev)
1288 {
1289         u32 gb_addr_config;
1290         int err;
1291
1292         adev->gfx.funcs = &gfx_v9_0_gfx_funcs;
1293
1294         switch (adev->asic_type) {
1295         case CHIP_VEGA10:
1296                 adev->gfx.config.max_hw_contexts = 8;
1297                 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
1298                 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
1299                 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
1300                 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0;
1301                 gb_addr_config = VEGA10_GB_ADDR_CONFIG_GOLDEN;
1302                 break;
1303         case CHIP_VEGA12:
1304                 adev->gfx.config.max_hw_contexts = 8;
1305                 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
1306                 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
1307                 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
1308                 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0;
1309                 gb_addr_config = VEGA12_GB_ADDR_CONFIG_GOLDEN;
1310                 DRM_INFO("fix gfx.config for vega12\n");
1311                 break;
1312         case CHIP_VEGA20:
1313                 adev->gfx.config.max_hw_contexts = 8;
1314                 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
1315                 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
1316                 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
1317                 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0;
1318                 gb_addr_config = RREG32_SOC15(GC, 0, mmGB_ADDR_CONFIG);
1319                 gb_addr_config &= ~0xf3e777ff;
1320                 gb_addr_config |= 0x22014042;
1321                 /* check vbios table if gpu info is not available */
1322                 err = amdgpu_atomfirmware_get_gfx_info(adev);
1323                 if (err)
1324                         return err;
1325                 break;
1326         case CHIP_RAVEN:
1327                 adev->gfx.config.max_hw_contexts = 8;
1328                 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
1329                 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
1330                 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
1331                 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0;
1332                 if (adev->rev_id >= 8)
1333                         gb_addr_config = RAVEN2_GB_ADDR_CONFIG_GOLDEN;
1334                 else
1335                         gb_addr_config = RAVEN_GB_ADDR_CONFIG_GOLDEN;
1336                 break;
1337         default:
1338                 BUG();
1339                 break;
1340         }
1341
1342         adev->gfx.config.gb_addr_config = gb_addr_config;
1343
1344         adev->gfx.config.gb_addr_config_fields.num_pipes = 1 <<
1345                         REG_GET_FIELD(
1346                                         adev->gfx.config.gb_addr_config,
1347                                         GB_ADDR_CONFIG,
1348                                         NUM_PIPES);
1349
1350         adev->gfx.config.max_tile_pipes =
1351                 adev->gfx.config.gb_addr_config_fields.num_pipes;
1352
1353         adev->gfx.config.gb_addr_config_fields.num_banks = 1 <<
1354                         REG_GET_FIELD(
1355                                         adev->gfx.config.gb_addr_config,
1356                                         GB_ADDR_CONFIG,
1357                                         NUM_BANKS);
1358         adev->gfx.config.gb_addr_config_fields.max_compress_frags = 1 <<
1359                         REG_GET_FIELD(
1360                                         adev->gfx.config.gb_addr_config,
1361                                         GB_ADDR_CONFIG,
1362                                         MAX_COMPRESSED_FRAGS);
1363         adev->gfx.config.gb_addr_config_fields.num_rb_per_se = 1 <<
1364                         REG_GET_FIELD(
1365                                         adev->gfx.config.gb_addr_config,
1366                                         GB_ADDR_CONFIG,
1367                                         NUM_RB_PER_SE);
1368         adev->gfx.config.gb_addr_config_fields.num_se = 1 <<
1369                         REG_GET_FIELD(
1370                                         adev->gfx.config.gb_addr_config,
1371                                         GB_ADDR_CONFIG,
1372                                         NUM_SHADER_ENGINES);
1373         adev->gfx.config.gb_addr_config_fields.pipe_interleave_size = 1 << (8 +
1374                         REG_GET_FIELD(
1375                                         adev->gfx.config.gb_addr_config,
1376                                         GB_ADDR_CONFIG,
1377                                         PIPE_INTERLEAVE_SIZE));
1378
1379         return 0;
1380 }
1381
1382 static int gfx_v9_0_ngg_create_buf(struct amdgpu_device *adev,
1383                                    struct amdgpu_ngg_buf *ngg_buf,
1384                                    int size_se,
1385                                    int default_size_se)
1386 {
1387         int r;
1388
1389         if (size_se < 0) {
1390                 dev_err(adev->dev, "Buffer size is invalid: %d\n", size_se);
1391                 return -EINVAL;
1392         }
1393         size_se = size_se ? size_se : default_size_se;
1394
1395         ngg_buf->size = size_se * adev->gfx.config.max_shader_engines;
1396         r = amdgpu_bo_create_kernel(adev, ngg_buf->size,
1397                                     PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM,
1398                                     &ngg_buf->bo,
1399                                     &ngg_buf->gpu_addr,
1400                                     NULL);
1401         if (r) {
1402                 dev_err(adev->dev, "(%d) failed to create NGG buffer\n", r);
1403                 return r;
1404         }
1405         ngg_buf->bo_size = amdgpu_bo_size(ngg_buf->bo);
1406
1407         return r;
1408 }
1409
1410 static int gfx_v9_0_ngg_fini(struct amdgpu_device *adev)
1411 {
1412         int i;
1413
1414         for (i = 0; i < NGG_BUF_MAX; i++)
1415                 amdgpu_bo_free_kernel(&adev->gfx.ngg.buf[i].bo,
1416                                       &adev->gfx.ngg.buf[i].gpu_addr,
1417                                       NULL);
1418
1419         memset(&adev->gfx.ngg.buf[0], 0,
1420                         sizeof(struct amdgpu_ngg_buf) * NGG_BUF_MAX);
1421
1422         adev->gfx.ngg.init = false;
1423
1424         return 0;
1425 }
1426
1427 static int gfx_v9_0_ngg_init(struct amdgpu_device *adev)
1428 {
1429         int r;
1430
1431         if (!amdgpu_ngg || adev->gfx.ngg.init == true)
1432                 return 0;
1433
1434         /* GDS reserve memory: 64 bytes alignment */
1435         adev->gfx.ngg.gds_reserve_size = ALIGN(5 * 4, 0x40);
1436         adev->gds.mem.total_size -= adev->gfx.ngg.gds_reserve_size;
1437         adev->gds.mem.gfx_partition_size -= adev->gfx.ngg.gds_reserve_size;
1438         adev->gfx.ngg.gds_reserve_addr = RREG32_SOC15(GC, 0, mmGDS_VMID0_BASE);
1439         adev->gfx.ngg.gds_reserve_addr += RREG32_SOC15(GC, 0, mmGDS_VMID0_SIZE);
1440
1441         /* Primitive Buffer */
1442         r = gfx_v9_0_ngg_create_buf(adev, &adev->gfx.ngg.buf[NGG_PRIM],
1443                                     amdgpu_prim_buf_per_se,
1444                                     64 * 1024);
1445         if (r) {
1446                 dev_err(adev->dev, "Failed to create Primitive Buffer\n");
1447                 goto err;
1448         }
1449
1450         /* Position Buffer */
1451         r = gfx_v9_0_ngg_create_buf(adev, &adev->gfx.ngg.buf[NGG_POS],
1452                                     amdgpu_pos_buf_per_se,
1453                                     256 * 1024);
1454         if (r) {
1455                 dev_err(adev->dev, "Failed to create Position Buffer\n");
1456                 goto err;
1457         }
1458
1459         /* Control Sideband */
1460         r = gfx_v9_0_ngg_create_buf(adev, &adev->gfx.ngg.buf[NGG_CNTL],
1461                                     amdgpu_cntl_sb_buf_per_se,
1462                                     256);
1463         if (r) {
1464                 dev_err(adev->dev, "Failed to create Control Sideband Buffer\n");
1465                 goto err;
1466         }
1467
1468         /* Parameter Cache, not created by default */
1469         if (amdgpu_param_buf_per_se <= 0)
1470                 goto out;
1471
1472         r = gfx_v9_0_ngg_create_buf(adev, &adev->gfx.ngg.buf[NGG_PARAM],
1473                                     amdgpu_param_buf_per_se,
1474                                     512 * 1024);
1475         if (r) {
1476                 dev_err(adev->dev, "Failed to create Parameter Cache\n");
1477                 goto err;
1478         }
1479
1480 out:
1481         adev->gfx.ngg.init = true;
1482         return 0;
1483 err:
1484         gfx_v9_0_ngg_fini(adev);
1485         return r;
1486 }
1487
1488 static int gfx_v9_0_ngg_en(struct amdgpu_device *adev)
1489 {
1490         struct amdgpu_ring *ring = &adev->gfx.gfx_ring[0];
1491         int r;
1492         u32 data, base;
1493
1494         if (!amdgpu_ngg)
1495                 return 0;
1496
1497         /* Program buffer size */
1498         data = REG_SET_FIELD(0, WD_BUF_RESOURCE_1, INDEX_BUF_SIZE,
1499                              adev->gfx.ngg.buf[NGG_PRIM].size >> 8);
1500         data = REG_SET_FIELD(data, WD_BUF_RESOURCE_1, POS_BUF_SIZE,
1501                              adev->gfx.ngg.buf[NGG_POS].size >> 8);
1502         WREG32_SOC15(GC, 0, mmWD_BUF_RESOURCE_1, data);
1503
1504         data = REG_SET_FIELD(0, WD_BUF_RESOURCE_2, CNTL_SB_BUF_SIZE,
1505                              adev->gfx.ngg.buf[NGG_CNTL].size >> 8);
1506         data = REG_SET_FIELD(data, WD_BUF_RESOURCE_2, PARAM_BUF_SIZE,
1507                              adev->gfx.ngg.buf[NGG_PARAM].size >> 10);
1508         WREG32_SOC15(GC, 0, mmWD_BUF_RESOURCE_2, data);
1509
1510         /* Program buffer base address */
1511         base = lower_32_bits(adev->gfx.ngg.buf[NGG_PRIM].gpu_addr);
1512         data = REG_SET_FIELD(0, WD_INDEX_BUF_BASE, BASE, base);
1513         WREG32_SOC15(GC, 0, mmWD_INDEX_BUF_BASE, data);
1514
1515         base = upper_32_bits(adev->gfx.ngg.buf[NGG_PRIM].gpu_addr);
1516         data = REG_SET_FIELD(0, WD_INDEX_BUF_BASE_HI, BASE_HI, base);
1517         WREG32_SOC15(GC, 0, mmWD_INDEX_BUF_BASE_HI, data);
1518
1519         base = lower_32_bits(adev->gfx.ngg.buf[NGG_POS].gpu_addr);
1520         data = REG_SET_FIELD(0, WD_POS_BUF_BASE, BASE, base);
1521         WREG32_SOC15(GC, 0, mmWD_POS_BUF_BASE, data);
1522
1523         base = upper_32_bits(adev->gfx.ngg.buf[NGG_POS].gpu_addr);
1524         data = REG_SET_FIELD(0, WD_POS_BUF_BASE_HI, BASE_HI, base);
1525         WREG32_SOC15(GC, 0, mmWD_POS_BUF_BASE_HI, data);
1526
1527         base = lower_32_bits(adev->gfx.ngg.buf[NGG_CNTL].gpu_addr);
1528         data = REG_SET_FIELD(0, WD_CNTL_SB_BUF_BASE, BASE, base);
1529         WREG32_SOC15(GC, 0, mmWD_CNTL_SB_BUF_BASE, data);
1530
1531         base = upper_32_bits(adev->gfx.ngg.buf[NGG_CNTL].gpu_addr);
1532         data = REG_SET_FIELD(0, WD_CNTL_SB_BUF_BASE_HI, BASE_HI, base);
1533         WREG32_SOC15(GC, 0, mmWD_CNTL_SB_BUF_BASE_HI, data);
1534
1535         /* Clear GDS reserved memory */
1536         r = amdgpu_ring_alloc(ring, 17);
1537         if (r) {
1538                 DRM_ERROR("amdgpu: NGG failed to lock ring %s (%d).\n",
1539                           ring->name, r);
1540                 return r;
1541         }
1542
1543         gfx_v9_0_write_data_to_reg(ring, 0, false,
1544                                    SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_SIZE),
1545                                    (adev->gds.mem.total_size +
1546                                     adev->gfx.ngg.gds_reserve_size));
1547
1548         amdgpu_ring_write(ring, PACKET3(PACKET3_DMA_DATA, 5));
1549         amdgpu_ring_write(ring, (PACKET3_DMA_DATA_CP_SYNC |
1550                                 PACKET3_DMA_DATA_DST_SEL(1) |
1551                                 PACKET3_DMA_DATA_SRC_SEL(2)));
1552         amdgpu_ring_write(ring, 0);
1553         amdgpu_ring_write(ring, 0);
1554         amdgpu_ring_write(ring, adev->gfx.ngg.gds_reserve_addr);
1555         amdgpu_ring_write(ring, 0);
1556         amdgpu_ring_write(ring, PACKET3_DMA_DATA_CMD_RAW_WAIT |
1557                                 adev->gfx.ngg.gds_reserve_size);
1558
1559         gfx_v9_0_write_data_to_reg(ring, 0, false,
1560                                    SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_SIZE), 0);
1561
1562         amdgpu_ring_commit(ring);
1563
1564         return 0;
1565 }
1566
1567 static int gfx_v9_0_compute_ring_init(struct amdgpu_device *adev, int ring_id,
1568                                       int mec, int pipe, int queue)
1569 {
1570         int r;
1571         unsigned irq_type;
1572         struct amdgpu_ring *ring = &adev->gfx.compute_ring[ring_id];
1573
1574         ring = &adev->gfx.compute_ring[ring_id];
1575
1576         /* mec0 is me1 */
1577         ring->me = mec + 1;
1578         ring->pipe = pipe;
1579         ring->queue = queue;
1580
1581         ring->ring_obj = NULL;
1582         ring->use_doorbell = true;
1583         ring->doorbell_index = (adev->doorbell_index.mec_ring0 + ring_id) << 1;
1584         ring->eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr
1585                                 + (ring_id * GFX9_MEC_HPD_SIZE);
1586         sprintf(ring->name, "comp_%d.%d.%d", ring->me, ring->pipe, ring->queue);
1587
1588         irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP
1589                 + ((ring->me - 1) * adev->gfx.mec.num_pipe_per_mec)
1590                 + ring->pipe;
1591
1592         /* type-2 packets are deprecated on MEC, use type-3 instead */
1593         r = amdgpu_ring_init(adev, ring, 1024,
1594                              &adev->gfx.eop_irq, irq_type);
1595         if (r)
1596                 return r;
1597
1598
1599         return 0;
1600 }
1601
1602 static int gfx_v9_0_sw_init(void *handle)
1603 {
1604         int i, j, k, r, ring_id;
1605         struct amdgpu_ring *ring;
1606         struct amdgpu_kiq *kiq;
1607         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1608
1609         switch (adev->asic_type) {
1610         case CHIP_VEGA10:
1611         case CHIP_VEGA12:
1612         case CHIP_VEGA20:
1613         case CHIP_RAVEN:
1614                 adev->gfx.mec.num_mec = 2;
1615                 break;
1616         default:
1617                 adev->gfx.mec.num_mec = 1;
1618                 break;
1619         }
1620
1621         adev->gfx.mec.num_pipe_per_mec = 4;
1622         adev->gfx.mec.num_queue_per_pipe = 8;
1623
1624         /* EOP Event */
1625         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_9_0__SRCID__CP_EOP_INTERRUPT, &adev->gfx.eop_irq);
1626         if (r)
1627                 return r;
1628
1629         /* Privileged reg */
1630         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_9_0__SRCID__CP_PRIV_REG_FAULT,
1631                               &adev->gfx.priv_reg_irq);
1632         if (r)
1633                 return r;
1634
1635         /* Privileged inst */
1636         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_9_0__SRCID__CP_PRIV_INSTR_FAULT,
1637                               &adev->gfx.priv_inst_irq);
1638         if (r)
1639                 return r;
1640
1641         adev->gfx.gfx_current_status = AMDGPU_GFX_NORMAL_MODE;
1642
1643         gfx_v9_0_scratch_init(adev);
1644
1645         r = gfx_v9_0_init_microcode(adev);
1646         if (r) {
1647                 DRM_ERROR("Failed to load gfx firmware!\n");
1648                 return r;
1649         }
1650
1651         r = adev->gfx.rlc.funcs->init(adev);
1652         if (r) {
1653                 DRM_ERROR("Failed to init rlc BOs!\n");
1654                 return r;
1655         }
1656
1657         r = gfx_v9_0_mec_init(adev);
1658         if (r) {
1659                 DRM_ERROR("Failed to init MEC BOs!\n");
1660                 return r;
1661         }
1662
1663         /* set up the gfx ring */
1664         for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
1665                 ring = &adev->gfx.gfx_ring[i];
1666                 ring->ring_obj = NULL;
1667                 if (!i)
1668                         sprintf(ring->name, "gfx");
1669                 else
1670                         sprintf(ring->name, "gfx_%d", i);
1671                 ring->use_doorbell = true;
1672                 ring->doorbell_index = adev->doorbell_index.gfx_ring0 << 1;
1673                 r = amdgpu_ring_init(adev, ring, 1024,
1674                                      &adev->gfx.eop_irq, AMDGPU_CP_IRQ_GFX_EOP);
1675                 if (r)
1676                         return r;
1677         }
1678
1679         /* set up the compute queues - allocate horizontally across pipes */
1680         ring_id = 0;
1681         for (i = 0; i < adev->gfx.mec.num_mec; ++i) {
1682                 for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) {
1683                         for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) {
1684                                 if (!amdgpu_gfx_is_mec_queue_enabled(adev, i, k, j))
1685                                         continue;
1686
1687                                 r = gfx_v9_0_compute_ring_init(adev,
1688                                                                ring_id,
1689                                                                i, k, j);
1690                                 if (r)
1691                                         return r;
1692
1693                                 ring_id++;
1694                         }
1695                 }
1696         }
1697
1698         r = amdgpu_gfx_kiq_init(adev, GFX9_MEC_HPD_SIZE);
1699         if (r) {
1700                 DRM_ERROR("Failed to init KIQ BOs!\n");
1701                 return r;
1702         }
1703
1704         kiq = &adev->gfx.kiq;
1705         r = amdgpu_gfx_kiq_init_ring(adev, &kiq->ring, &kiq->irq);
1706         if (r)
1707                 return r;
1708
1709         /* create MQD for all compute queues as wel as KIQ for SRIOV case */
1710         r = amdgpu_gfx_compute_mqd_sw_init(adev, sizeof(struct v9_mqd_allocation));
1711         if (r)
1712                 return r;
1713
1714         adev->gfx.ce_ram_size = 0x8000;
1715
1716         r = gfx_v9_0_gpu_early_init(adev);
1717         if (r)
1718                 return r;
1719
1720         r = gfx_v9_0_ngg_init(adev);
1721         if (r)
1722                 return r;
1723
1724         return 0;
1725 }
1726
1727
1728 static int gfx_v9_0_sw_fini(void *handle)
1729 {
1730         int i;
1731         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1732
1733         amdgpu_bo_free_kernel(&adev->gds.oa_gfx_bo, NULL, NULL);
1734         amdgpu_bo_free_kernel(&adev->gds.gws_gfx_bo, NULL, NULL);
1735         amdgpu_bo_free_kernel(&adev->gds.gds_gfx_bo, NULL, NULL);
1736
1737         for (i = 0; i < adev->gfx.num_gfx_rings; i++)
1738                 amdgpu_ring_fini(&adev->gfx.gfx_ring[i]);
1739         for (i = 0; i < adev->gfx.num_compute_rings; i++)
1740                 amdgpu_ring_fini(&adev->gfx.compute_ring[i]);
1741
1742         amdgpu_gfx_compute_mqd_sw_fini(adev);
1743         amdgpu_gfx_kiq_free_ring(&adev->gfx.kiq.ring, &adev->gfx.kiq.irq);
1744         amdgpu_gfx_kiq_fini(adev);
1745
1746         gfx_v9_0_mec_fini(adev);
1747         gfx_v9_0_ngg_fini(adev);
1748         amdgpu_bo_free_kernel(&adev->gfx.rlc.clear_state_obj,
1749                                 &adev->gfx.rlc.clear_state_gpu_addr,
1750                                 (void **)&adev->gfx.rlc.cs_ptr);
1751         if (adev->asic_type == CHIP_RAVEN) {
1752                 amdgpu_bo_free_kernel(&adev->gfx.rlc.cp_table_obj,
1753                                 &adev->gfx.rlc.cp_table_gpu_addr,
1754                                 (void **)&adev->gfx.rlc.cp_table_ptr);
1755         }
1756         gfx_v9_0_free_microcode(adev);
1757
1758         return 0;
1759 }
1760
1761
1762 static void gfx_v9_0_tiling_mode_table_init(struct amdgpu_device *adev)
1763 {
1764         /* TODO */
1765 }
1766
1767 static void gfx_v9_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, u32 sh_num, u32 instance)
1768 {
1769         u32 data;
1770
1771         if (instance == 0xffffffff)
1772                 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES, 1);
1773         else
1774                 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_INDEX, instance);
1775
1776         if (se_num == 0xffffffff)
1777                 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_BROADCAST_WRITES, 1);
1778         else
1779                 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num);
1780
1781         if (sh_num == 0xffffffff)
1782                 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_BROADCAST_WRITES, 1);
1783         else
1784                 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_INDEX, sh_num);
1785
1786         WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, data);
1787 }
1788
1789 static u32 gfx_v9_0_get_rb_active_bitmap(struct amdgpu_device *adev)
1790 {
1791         u32 data, mask;
1792
1793         data = RREG32_SOC15(GC, 0, mmCC_RB_BACKEND_DISABLE);
1794         data |= RREG32_SOC15(GC, 0, mmGC_USER_RB_BACKEND_DISABLE);
1795
1796         data &= CC_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK;
1797         data >>= GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT;
1798
1799         mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_backends_per_se /
1800                                          adev->gfx.config.max_sh_per_se);
1801
1802         return (~data) & mask;
1803 }
1804
1805 static void gfx_v9_0_setup_rb(struct amdgpu_device *adev)
1806 {
1807         int i, j;
1808         u32 data;
1809         u32 active_rbs = 0;
1810         u32 rb_bitmap_width_per_sh = adev->gfx.config.max_backends_per_se /
1811                                         adev->gfx.config.max_sh_per_se;
1812
1813         mutex_lock(&adev->grbm_idx_mutex);
1814         for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
1815                 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
1816                         gfx_v9_0_select_se_sh(adev, i, j, 0xffffffff);
1817                         data = gfx_v9_0_get_rb_active_bitmap(adev);
1818                         active_rbs |= data << ((i * adev->gfx.config.max_sh_per_se + j) *
1819                                                rb_bitmap_width_per_sh);
1820                 }
1821         }
1822         gfx_v9_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
1823         mutex_unlock(&adev->grbm_idx_mutex);
1824
1825         adev->gfx.config.backend_enable_mask = active_rbs;
1826         adev->gfx.config.num_rbs = hweight32(active_rbs);
1827 }
1828
1829 #define DEFAULT_SH_MEM_BASES    (0x6000)
1830 #define FIRST_COMPUTE_VMID      (8)
1831 #define LAST_COMPUTE_VMID       (16)
1832 static void gfx_v9_0_init_compute_vmid(struct amdgpu_device *adev)
1833 {
1834         int i;
1835         uint32_t sh_mem_config;
1836         uint32_t sh_mem_bases;
1837
1838         /*
1839          * Configure apertures:
1840          * LDS:         0x60000000'00000000 - 0x60000001'00000000 (4GB)
1841          * Scratch:     0x60000001'00000000 - 0x60000002'00000000 (4GB)
1842          * GPUVM:       0x60010000'00000000 - 0x60020000'00000000 (1TB)
1843          */
1844         sh_mem_bases = DEFAULT_SH_MEM_BASES | (DEFAULT_SH_MEM_BASES << 16);
1845
1846         sh_mem_config = SH_MEM_ADDRESS_MODE_64 |
1847                         SH_MEM_ALIGNMENT_MODE_UNALIGNED <<
1848                         SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT;
1849
1850         mutex_lock(&adev->srbm_mutex);
1851         for (i = FIRST_COMPUTE_VMID; i < LAST_COMPUTE_VMID; i++) {
1852                 soc15_grbm_select(adev, 0, 0, 0, i);
1853                 /* CP and shaders */
1854                 WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, sh_mem_config);
1855                 WREG32_SOC15(GC, 0, mmSH_MEM_BASES, sh_mem_bases);
1856         }
1857         soc15_grbm_select(adev, 0, 0, 0, 0);
1858         mutex_unlock(&adev->srbm_mutex);
1859 }
1860
1861 static void gfx_v9_0_constants_init(struct amdgpu_device *adev)
1862 {
1863         u32 tmp;
1864         int i;
1865
1866         WREG32_FIELD15(GC, 0, GRBM_CNTL, READ_TIMEOUT, 0xff);
1867
1868         gfx_v9_0_tiling_mode_table_init(adev);
1869
1870         gfx_v9_0_setup_rb(adev);
1871         gfx_v9_0_get_cu_info(adev, &adev->gfx.cu_info);
1872         adev->gfx.config.db_debug2 = RREG32_SOC15(GC, 0, mmDB_DEBUG2);
1873
1874         /* XXX SH_MEM regs */
1875         /* where to put LDS, scratch, GPUVM in FSA64 space */
1876         mutex_lock(&adev->srbm_mutex);
1877         for (i = 0; i < adev->vm_manager.id_mgr[AMDGPU_GFXHUB].num_ids; i++) {
1878                 soc15_grbm_select(adev, 0, 0, 0, i);
1879                 /* CP and shaders */
1880                 if (i == 0) {
1881                         tmp = REG_SET_FIELD(0, SH_MEM_CONFIG, ALIGNMENT_MODE,
1882                                             SH_MEM_ALIGNMENT_MODE_UNALIGNED);
1883                         WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, tmp);
1884                         WREG32_SOC15(GC, 0, mmSH_MEM_BASES, 0);
1885                 } else {
1886                         tmp = REG_SET_FIELD(0, SH_MEM_CONFIG, ALIGNMENT_MODE,
1887                                             SH_MEM_ALIGNMENT_MODE_UNALIGNED);
1888                         WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, tmp);
1889                         tmp = REG_SET_FIELD(0, SH_MEM_BASES, PRIVATE_BASE,
1890                                 (adev->gmc.private_aperture_start >> 48));
1891                         tmp = REG_SET_FIELD(tmp, SH_MEM_BASES, SHARED_BASE,
1892                                 (adev->gmc.shared_aperture_start >> 48));
1893                         WREG32_SOC15(GC, 0, mmSH_MEM_BASES, tmp);
1894                 }
1895         }
1896         soc15_grbm_select(adev, 0, 0, 0, 0);
1897
1898         mutex_unlock(&adev->srbm_mutex);
1899
1900         gfx_v9_0_init_compute_vmid(adev);
1901
1902         mutex_lock(&adev->grbm_idx_mutex);
1903         /*
1904          * making sure that the following register writes will be broadcasted
1905          * to all the shaders
1906          */
1907         gfx_v9_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
1908
1909         WREG32_SOC15(GC, 0, mmPA_SC_FIFO_SIZE,
1910                    (adev->gfx.config.sc_prim_fifo_size_frontend <<
1911                         PA_SC_FIFO_SIZE__SC_FRONTEND_PRIM_FIFO_SIZE__SHIFT) |
1912                    (adev->gfx.config.sc_prim_fifo_size_backend <<
1913                         PA_SC_FIFO_SIZE__SC_BACKEND_PRIM_FIFO_SIZE__SHIFT) |
1914                    (adev->gfx.config.sc_hiz_tile_fifo_size <<
1915                         PA_SC_FIFO_SIZE__SC_HIZ_TILE_FIFO_SIZE__SHIFT) |
1916                    (adev->gfx.config.sc_earlyz_tile_fifo_size <<
1917                         PA_SC_FIFO_SIZE__SC_EARLYZ_TILE_FIFO_SIZE__SHIFT));
1918         mutex_unlock(&adev->grbm_idx_mutex);
1919
1920 }
1921
1922 static void gfx_v9_0_wait_for_rlc_serdes(struct amdgpu_device *adev)
1923 {
1924         u32 i, j, k;
1925         u32 mask;
1926
1927         mutex_lock(&adev->grbm_idx_mutex);
1928         for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
1929                 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
1930                         gfx_v9_0_select_se_sh(adev, i, j, 0xffffffff);
1931                         for (k = 0; k < adev->usec_timeout; k++) {
1932                                 if (RREG32_SOC15(GC, 0, mmRLC_SERDES_CU_MASTER_BUSY) == 0)
1933                                         break;
1934                                 udelay(1);
1935                         }
1936                         if (k == adev->usec_timeout) {
1937                                 gfx_v9_0_select_se_sh(adev, 0xffffffff,
1938                                                       0xffffffff, 0xffffffff);
1939                                 mutex_unlock(&adev->grbm_idx_mutex);
1940                                 DRM_INFO("Timeout wait for RLC serdes %u,%u\n",
1941                                          i, j);
1942                                 return;
1943                         }
1944                 }
1945         }
1946         gfx_v9_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
1947         mutex_unlock(&adev->grbm_idx_mutex);
1948
1949         mask = RLC_SERDES_NONCU_MASTER_BUSY__SE_MASTER_BUSY_MASK |
1950                 RLC_SERDES_NONCU_MASTER_BUSY__GC_MASTER_BUSY_MASK |
1951                 RLC_SERDES_NONCU_MASTER_BUSY__TC0_MASTER_BUSY_MASK |
1952                 RLC_SERDES_NONCU_MASTER_BUSY__TC1_MASTER_BUSY_MASK;
1953         for (k = 0; k < adev->usec_timeout; k++) {
1954                 if ((RREG32_SOC15(GC, 0, mmRLC_SERDES_NONCU_MASTER_BUSY) & mask) == 0)
1955                         break;
1956                 udelay(1);
1957         }
1958 }
1959
1960 static void gfx_v9_0_enable_gui_idle_interrupt(struct amdgpu_device *adev,
1961                                                bool enable)
1962 {
1963         u32 tmp = RREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0);
1964
1965         tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE, enable ? 1 : 0);
1966         tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE, enable ? 1 : 0);
1967         tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE, enable ? 1 : 0);
1968         tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, GFX_IDLE_INT_ENABLE, enable ? 1 : 0);
1969
1970         WREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0, tmp);
1971 }
1972
1973 static void gfx_v9_0_init_csb(struct amdgpu_device *adev)
1974 {
1975         /* csib */
1976         WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_CSIB_ADDR_HI),
1977                         adev->gfx.rlc.clear_state_gpu_addr >> 32);
1978         WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_CSIB_ADDR_LO),
1979                         adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc);
1980         WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_CSIB_LENGTH),
1981                         adev->gfx.rlc.clear_state_size);
1982 }
1983
1984 static void gfx_v9_1_parse_ind_reg_list(int *register_list_format,
1985                                 int indirect_offset,
1986                                 int list_size,
1987                                 int *unique_indirect_regs,
1988                                 int unique_indirect_reg_count,
1989                                 int *indirect_start_offsets,
1990                                 int *indirect_start_offsets_count,
1991                                 int max_start_offsets_count)
1992 {
1993         int idx;
1994
1995         for (; indirect_offset < list_size; indirect_offset++) {
1996                 WARN_ON(*indirect_start_offsets_count >= max_start_offsets_count);
1997                 indirect_start_offsets[*indirect_start_offsets_count] = indirect_offset;
1998                 *indirect_start_offsets_count = *indirect_start_offsets_count + 1;
1999
2000                 while (register_list_format[indirect_offset] != 0xFFFFFFFF) {
2001                         indirect_offset += 2;
2002
2003                         /* look for the matching indice */
2004                         for (idx = 0; idx < unique_indirect_reg_count; idx++) {
2005                                 if (unique_indirect_regs[idx] ==
2006                                         register_list_format[indirect_offset] ||
2007                                         !unique_indirect_regs[idx])
2008                                         break;
2009                         }
2010
2011                         BUG_ON(idx >= unique_indirect_reg_count);
2012
2013                         if (!unique_indirect_regs[idx])
2014                                 unique_indirect_regs[idx] = register_list_format[indirect_offset];
2015
2016                         indirect_offset++;
2017                 }
2018         }
2019 }
2020
2021 static int gfx_v9_1_init_rlc_save_restore_list(struct amdgpu_device *adev)
2022 {
2023         int unique_indirect_regs[] = {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0};
2024         int unique_indirect_reg_count = 0;
2025
2026         int indirect_start_offsets[] = {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0};
2027         int indirect_start_offsets_count = 0;
2028
2029         int list_size = 0;
2030         int i = 0, j = 0;
2031         u32 tmp = 0;
2032
2033         u32 *register_list_format =
2034                 kmalloc(adev->gfx.rlc.reg_list_format_size_bytes, GFP_KERNEL);
2035         if (!register_list_format)
2036                 return -ENOMEM;
2037         memcpy(register_list_format, adev->gfx.rlc.register_list_format,
2038                 adev->gfx.rlc.reg_list_format_size_bytes);
2039
2040         /* setup unique_indirect_regs array and indirect_start_offsets array */
2041         unique_indirect_reg_count = ARRAY_SIZE(unique_indirect_regs);
2042         gfx_v9_1_parse_ind_reg_list(register_list_format,
2043                                     adev->gfx.rlc.reg_list_format_direct_reg_list_length,
2044                                     adev->gfx.rlc.reg_list_format_size_bytes >> 2,
2045                                     unique_indirect_regs,
2046                                     unique_indirect_reg_count,
2047                                     indirect_start_offsets,
2048                                     &indirect_start_offsets_count,
2049                                     ARRAY_SIZE(indirect_start_offsets));
2050
2051         /* enable auto inc in case it is disabled */
2052         tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_CNTL));
2053         tmp |= RLC_SRM_CNTL__AUTO_INCR_ADDR_MASK;
2054         WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_CNTL), tmp);
2055
2056         /* write register_restore table to offset 0x0 using RLC_SRM_ARAM_ADDR/DATA */
2057         WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_ARAM_ADDR),
2058                 RLC_SAVE_RESTORE_ADDR_STARTING_OFFSET);
2059         for (i = 0; i < adev->gfx.rlc.reg_list_size_bytes >> 2; i++)
2060                 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_ARAM_DATA),
2061                         adev->gfx.rlc.register_restore[i]);
2062
2063         /* load indirect register */
2064         WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_SCRATCH_ADDR),
2065                 adev->gfx.rlc.reg_list_format_start);
2066
2067         /* direct register portion */
2068         for (i = 0; i < adev->gfx.rlc.reg_list_format_direct_reg_list_length; i++)
2069                 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_SCRATCH_DATA),
2070                         register_list_format[i]);
2071
2072         /* indirect register portion */
2073         while (i < (adev->gfx.rlc.reg_list_format_size_bytes >> 2)) {
2074                 if (register_list_format[i] == 0xFFFFFFFF) {
2075                         WREG32_SOC15(GC, 0, mmRLC_GPM_SCRATCH_DATA, register_list_format[i++]);
2076                         continue;
2077                 }
2078
2079                 WREG32_SOC15(GC, 0, mmRLC_GPM_SCRATCH_DATA, register_list_format[i++]);
2080                 WREG32_SOC15(GC, 0, mmRLC_GPM_SCRATCH_DATA, register_list_format[i++]);
2081
2082                 for (j = 0; j < unique_indirect_reg_count; j++) {
2083                         if (register_list_format[i] == unique_indirect_regs[j]) {
2084                                 WREG32_SOC15(GC, 0, mmRLC_GPM_SCRATCH_DATA, j);
2085                                 break;
2086                         }
2087                 }
2088
2089                 BUG_ON(j >= unique_indirect_reg_count);
2090
2091                 i++;
2092         }
2093
2094         /* set save/restore list size */
2095         list_size = adev->gfx.rlc.reg_list_size_bytes >> 2;
2096         list_size = list_size >> 1;
2097         WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_SCRATCH_ADDR),
2098                 adev->gfx.rlc.reg_restore_list_size);
2099         WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_SCRATCH_DATA), list_size);
2100
2101         /* write the starting offsets to RLC scratch ram */
2102         WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_SCRATCH_ADDR),
2103                 adev->gfx.rlc.starting_offsets_start);
2104         for (i = 0; i < ARRAY_SIZE(indirect_start_offsets); i++)
2105                 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_SCRATCH_DATA),
2106                        indirect_start_offsets[i]);
2107
2108         /* load unique indirect regs*/
2109         for (i = 0; i < ARRAY_SIZE(unique_indirect_regs); i++) {
2110                 if (unique_indirect_regs[i] != 0) {
2111                         WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_INDEX_CNTL_ADDR_0)
2112                                + GFX_RLC_SRM_INDEX_CNTL_ADDR_OFFSETS[i],
2113                                unique_indirect_regs[i] & 0x3FFFF);
2114
2115                         WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_INDEX_CNTL_DATA_0)
2116                                + GFX_RLC_SRM_INDEX_CNTL_DATA_OFFSETS[i],
2117                                unique_indirect_regs[i] >> 20);
2118                 }
2119         }
2120
2121         kfree(register_list_format);
2122         return 0;
2123 }
2124
2125 static void gfx_v9_0_enable_save_restore_machine(struct amdgpu_device *adev)
2126 {
2127         WREG32_FIELD15(GC, 0, RLC_SRM_CNTL, SRM_ENABLE, 1);
2128 }
2129
2130 static void pwr_10_0_gfxip_control_over_cgpg(struct amdgpu_device *adev,
2131                                              bool enable)
2132 {
2133         uint32_t data = 0;
2134         uint32_t default_data = 0;
2135
2136         default_data = data = RREG32(SOC15_REG_OFFSET(PWR, 0, mmPWR_MISC_CNTL_STATUS));
2137         if (enable == true) {
2138                 /* enable GFXIP control over CGPG */
2139                 data |= PWR_MISC_CNTL_STATUS__PWR_GFX_RLC_CGPG_EN_MASK;
2140                 if(default_data != data)
2141                         WREG32(SOC15_REG_OFFSET(PWR, 0, mmPWR_MISC_CNTL_STATUS), data);
2142
2143                 /* update status */
2144                 data &= ~PWR_MISC_CNTL_STATUS__PWR_GFXOFF_STATUS_MASK;
2145                 data |= (2 << PWR_MISC_CNTL_STATUS__PWR_GFXOFF_STATUS__SHIFT);
2146                 if(default_data != data)
2147                         WREG32(SOC15_REG_OFFSET(PWR, 0, mmPWR_MISC_CNTL_STATUS), data);
2148         } else {
2149                 /* restore GFXIP control over GCPG */
2150                 data &= ~PWR_MISC_CNTL_STATUS__PWR_GFX_RLC_CGPG_EN_MASK;
2151                 if(default_data != data)
2152                         WREG32(SOC15_REG_OFFSET(PWR, 0, mmPWR_MISC_CNTL_STATUS), data);
2153         }
2154 }
2155
2156 static void gfx_v9_0_init_gfx_power_gating(struct amdgpu_device *adev)
2157 {
2158         uint32_t data = 0;
2159
2160         if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG |
2161                               AMD_PG_SUPPORT_GFX_SMG |
2162                               AMD_PG_SUPPORT_GFX_DMG)) {
2163                 /* init IDLE_POLL_COUNT = 60 */
2164                 data = RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_RB_WPTR_POLL_CNTL));
2165                 data &= ~CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK;
2166                 data |= (0x60 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT);
2167                 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_RB_WPTR_POLL_CNTL), data);
2168
2169                 /* init RLC PG Delay */
2170                 data = 0;
2171                 data |= (0x10 << RLC_PG_DELAY__POWER_UP_DELAY__SHIFT);
2172                 data |= (0x10 << RLC_PG_DELAY__POWER_DOWN_DELAY__SHIFT);
2173                 data |= (0x10 << RLC_PG_DELAY__CMD_PROPAGATE_DELAY__SHIFT);
2174                 data |= (0x40 << RLC_PG_DELAY__MEM_SLEEP_DELAY__SHIFT);
2175                 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_DELAY), data);
2176
2177                 data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_DELAY_2));
2178                 data &= ~RLC_PG_DELAY_2__SERDES_CMD_DELAY_MASK;
2179                 data |= (0x4 << RLC_PG_DELAY_2__SERDES_CMD_DELAY__SHIFT);
2180                 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_DELAY_2), data);
2181
2182                 data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_DELAY_3));
2183                 data &= ~RLC_PG_DELAY_3__CGCG_ACTIVE_BEFORE_CGPG_MASK;
2184                 data |= (0xff << RLC_PG_DELAY_3__CGCG_ACTIVE_BEFORE_CGPG__SHIFT);
2185                 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_DELAY_3), data);
2186
2187                 data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_AUTO_PG_CTRL));
2188                 data &= ~RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD_MASK;
2189
2190                 /* program GRBM_REG_SAVE_GFX_IDLE_THRESHOLD to 0x55f0 */
2191                 data |= (0x55f0 << RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD__SHIFT);
2192                 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_AUTO_PG_CTRL), data);
2193
2194                 pwr_10_0_gfxip_control_over_cgpg(adev, true);
2195         }
2196 }
2197
2198 static void gfx_v9_0_enable_sck_slow_down_on_power_up(struct amdgpu_device *adev,
2199                                                 bool enable)
2200 {
2201         uint32_t data = 0;
2202         uint32_t default_data = 0;
2203
2204         default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL));
2205         data = REG_SET_FIELD(data, RLC_PG_CNTL,
2206                              SMU_CLK_SLOWDOWN_ON_PU_ENABLE,
2207                              enable ? 1 : 0);
2208         if (default_data != data)
2209                 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data);
2210 }
2211
2212 static void gfx_v9_0_enable_sck_slow_down_on_power_down(struct amdgpu_device *adev,
2213                                                 bool enable)
2214 {
2215         uint32_t data = 0;
2216         uint32_t default_data = 0;
2217
2218         default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL));
2219         data = REG_SET_FIELD(data, RLC_PG_CNTL,
2220                              SMU_CLK_SLOWDOWN_ON_PD_ENABLE,
2221                              enable ? 1 : 0);
2222         if(default_data != data)
2223                 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data);
2224 }
2225
2226 static void gfx_v9_0_enable_cp_power_gating(struct amdgpu_device *adev,
2227                                         bool enable)
2228 {
2229         uint32_t data = 0;
2230         uint32_t default_data = 0;
2231
2232         default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL));
2233         data = REG_SET_FIELD(data, RLC_PG_CNTL,
2234                              CP_PG_DISABLE,
2235                              enable ? 0 : 1);
2236         if(default_data != data)
2237                 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data);
2238 }
2239
2240 static void gfx_v9_0_enable_gfx_cg_power_gating(struct amdgpu_device *adev,
2241                                                 bool enable)
2242 {
2243         uint32_t data, default_data;
2244
2245         default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL));
2246         data = REG_SET_FIELD(data, RLC_PG_CNTL,
2247                              GFX_POWER_GATING_ENABLE,
2248                              enable ? 1 : 0);
2249         if(default_data != data)
2250                 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data);
2251 }
2252
2253 static void gfx_v9_0_enable_gfx_pipeline_powergating(struct amdgpu_device *adev,
2254                                                 bool enable)
2255 {
2256         uint32_t data, default_data;
2257
2258         default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL));
2259         data = REG_SET_FIELD(data, RLC_PG_CNTL,
2260                              GFX_PIPELINE_PG_ENABLE,
2261                              enable ? 1 : 0);
2262         if(default_data != data)
2263                 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data);
2264
2265         if (!enable)
2266                 /* read any GFX register to wake up GFX */
2267                 data = RREG32(SOC15_REG_OFFSET(GC, 0, mmDB_RENDER_CONTROL));
2268 }
2269
2270 static void gfx_v9_0_enable_gfx_static_mg_power_gating(struct amdgpu_device *adev,
2271                                                        bool enable)
2272 {
2273         uint32_t data, default_data;
2274
2275         default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL));
2276         data = REG_SET_FIELD(data, RLC_PG_CNTL,
2277                              STATIC_PER_CU_PG_ENABLE,
2278                              enable ? 1 : 0);
2279         if(default_data != data)
2280                 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data);
2281 }
2282
2283 static void gfx_v9_0_enable_gfx_dynamic_mg_power_gating(struct amdgpu_device *adev,
2284                                                 bool enable)
2285 {
2286         uint32_t data, default_data;
2287
2288         default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL));
2289         data = REG_SET_FIELD(data, RLC_PG_CNTL,
2290                              DYN_PER_CU_PG_ENABLE,
2291                              enable ? 1 : 0);
2292         if(default_data != data)
2293                 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data);
2294 }
2295
2296 static void gfx_v9_0_init_pg(struct amdgpu_device *adev)
2297 {
2298         gfx_v9_0_init_csb(adev);
2299
2300         /*
2301          * Rlc save restore list is workable since v2_1.
2302          * And it's needed by gfxoff feature.
2303          */
2304         if (adev->gfx.rlc.is_rlc_v2_1) {
2305                 gfx_v9_1_init_rlc_save_restore_list(adev);
2306                 gfx_v9_0_enable_save_restore_machine(adev);
2307         }
2308
2309         if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG |
2310                               AMD_PG_SUPPORT_GFX_SMG |
2311                               AMD_PG_SUPPORT_GFX_DMG |
2312                               AMD_PG_SUPPORT_CP |
2313                               AMD_PG_SUPPORT_GDS |
2314                               AMD_PG_SUPPORT_RLC_SMU_HS)) {
2315                 WREG32(mmRLC_JUMP_TABLE_RESTORE,
2316                        adev->gfx.rlc.cp_table_gpu_addr >> 8);
2317                 gfx_v9_0_init_gfx_power_gating(adev);
2318         }
2319 }
2320
2321 void gfx_v9_0_rlc_stop(struct amdgpu_device *adev)
2322 {
2323         WREG32_FIELD15(GC, 0, RLC_CNTL, RLC_ENABLE_F32, 0);
2324         gfx_v9_0_enable_gui_idle_interrupt(adev, false);
2325         gfx_v9_0_wait_for_rlc_serdes(adev);
2326 }
2327
2328 static void gfx_v9_0_rlc_reset(struct amdgpu_device *adev)
2329 {
2330         WREG32_FIELD15(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 1);
2331         udelay(50);
2332         WREG32_FIELD15(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 0);
2333         udelay(50);
2334 }
2335
2336 static void gfx_v9_0_rlc_start(struct amdgpu_device *adev)
2337 {
2338 #ifdef AMDGPU_RLC_DEBUG_RETRY
2339         u32 rlc_ucode_ver;
2340 #endif
2341
2342         WREG32_FIELD15(GC, 0, RLC_CNTL, RLC_ENABLE_F32, 1);
2343
2344         /* carrizo do enable cp interrupt after cp inited */
2345         if (!(adev->flags & AMD_IS_APU))
2346                 gfx_v9_0_enable_gui_idle_interrupt(adev, true);
2347
2348         udelay(50);
2349
2350 #ifdef AMDGPU_RLC_DEBUG_RETRY
2351         /* RLC_GPM_GENERAL_6 : RLC Ucode version */
2352         rlc_ucode_ver = RREG32_SOC15(GC, 0, mmRLC_GPM_GENERAL_6);
2353         if(rlc_ucode_ver == 0x108) {
2354                 DRM_INFO("Using rlc debug ucode. mmRLC_GPM_GENERAL_6 ==0x08%x / fw_ver == %i \n",
2355                                 rlc_ucode_ver, adev->gfx.rlc_fw_version);
2356                 /* RLC_GPM_TIMER_INT_3 : Timer interval in RefCLK cycles,
2357                  * default is 0x9C4 to create a 100us interval */
2358                 WREG32_SOC15(GC, 0, mmRLC_GPM_TIMER_INT_3, 0x9C4);
2359                 /* RLC_GPM_GENERAL_12 : Minimum gap between wptr and rptr
2360                  * to disable the page fault retry interrupts, default is
2361                  * 0x100 (256) */
2362                 WREG32_SOC15(GC, 0, mmRLC_GPM_GENERAL_12, 0x100);
2363         }
2364 #endif
2365 }
2366
2367 static int gfx_v9_0_rlc_load_microcode(struct amdgpu_device *adev)
2368 {
2369         const struct rlc_firmware_header_v2_0 *hdr;
2370         const __le32 *fw_data;
2371         unsigned i, fw_size;
2372
2373         if (!adev->gfx.rlc_fw)
2374                 return -EINVAL;
2375
2376         hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data;
2377         amdgpu_ucode_print_rlc_hdr(&hdr->header);
2378
2379         fw_data = (const __le32 *)(adev->gfx.rlc_fw->data +
2380                            le32_to_cpu(hdr->header.ucode_array_offset_bytes));
2381         fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
2382
2383         WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_ADDR,
2384                         RLCG_UCODE_LOADING_START_ADDRESS);
2385         for (i = 0; i < fw_size; i++)
2386                 WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_DATA, le32_to_cpup(fw_data++));
2387         WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_ADDR, adev->gfx.rlc_fw_version);
2388
2389         return 0;
2390 }
2391
2392 static int gfx_v9_0_rlc_resume(struct amdgpu_device *adev)
2393 {
2394         int r;
2395
2396         if (amdgpu_sriov_vf(adev)) {
2397                 gfx_v9_0_init_csb(adev);
2398                 return 0;
2399         }
2400
2401         adev->gfx.rlc.funcs->stop(adev);
2402
2403         /* disable CG */
2404         WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, 0);
2405
2406         adev->gfx.rlc.funcs->reset(adev);
2407
2408         gfx_v9_0_init_pg(adev);
2409
2410         if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
2411                 /* legacy rlc firmware loading */
2412                 r = gfx_v9_0_rlc_load_microcode(adev);
2413                 if (r)
2414                         return r;
2415         }
2416
2417         switch (adev->asic_type) {
2418         case CHIP_RAVEN:
2419                 if (amdgpu_lbpw == 0)
2420                         gfx_v9_0_enable_lbpw(adev, false);
2421                 else
2422                         gfx_v9_0_enable_lbpw(adev, true);
2423                 break;
2424         case CHIP_VEGA20:
2425                 if (amdgpu_lbpw > 0)
2426                         gfx_v9_0_enable_lbpw(adev, true);
2427                 else
2428                         gfx_v9_0_enable_lbpw(adev, false);
2429                 break;
2430         default:
2431                 break;
2432         }
2433
2434         adev->gfx.rlc.funcs->start(adev);
2435
2436         return 0;
2437 }
2438
2439 static void gfx_v9_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable)
2440 {
2441         int i;
2442         u32 tmp = RREG32_SOC15(GC, 0, mmCP_ME_CNTL);
2443
2444         tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, enable ? 0 : 1);
2445         tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, enable ? 0 : 1);
2446         tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_HALT, enable ? 0 : 1);
2447         if (!enable) {
2448                 for (i = 0; i < adev->gfx.num_gfx_rings; i++)
2449                         adev->gfx.gfx_ring[i].sched.ready = false;
2450         }
2451         WREG32_SOC15(GC, 0, mmCP_ME_CNTL, tmp);
2452         udelay(50);
2453 }
2454
2455 static int gfx_v9_0_cp_gfx_load_microcode(struct amdgpu_device *adev)
2456 {
2457         const struct gfx_firmware_header_v1_0 *pfp_hdr;
2458         const struct gfx_firmware_header_v1_0 *ce_hdr;
2459         const struct gfx_firmware_header_v1_0 *me_hdr;
2460         const __le32 *fw_data;
2461         unsigned i, fw_size;
2462
2463         if (!adev->gfx.me_fw || !adev->gfx.pfp_fw || !adev->gfx.ce_fw)
2464                 return -EINVAL;
2465
2466         pfp_hdr = (const struct gfx_firmware_header_v1_0 *)
2467                 adev->gfx.pfp_fw->data;
2468         ce_hdr = (const struct gfx_firmware_header_v1_0 *)
2469                 adev->gfx.ce_fw->data;
2470         me_hdr = (const struct gfx_firmware_header_v1_0 *)
2471                 adev->gfx.me_fw->data;
2472
2473         amdgpu_ucode_print_gfx_hdr(&pfp_hdr->header);
2474         amdgpu_ucode_print_gfx_hdr(&ce_hdr->header);
2475         amdgpu_ucode_print_gfx_hdr(&me_hdr->header);
2476
2477         gfx_v9_0_cp_gfx_enable(adev, false);
2478
2479         /* PFP */
2480         fw_data = (const __le32 *)
2481                 (adev->gfx.pfp_fw->data +
2482                  le32_to_cpu(pfp_hdr->header.ucode_array_offset_bytes));
2483         fw_size = le32_to_cpu(pfp_hdr->header.ucode_size_bytes) / 4;
2484         WREG32_SOC15(GC, 0, mmCP_PFP_UCODE_ADDR, 0);
2485         for (i = 0; i < fw_size; i++)
2486                 WREG32_SOC15(GC, 0, mmCP_PFP_UCODE_DATA, le32_to_cpup(fw_data++));
2487         WREG32_SOC15(GC, 0, mmCP_PFP_UCODE_ADDR, adev->gfx.pfp_fw_version);
2488
2489         /* CE */
2490         fw_data = (const __le32 *)
2491                 (adev->gfx.ce_fw->data +
2492                  le32_to_cpu(ce_hdr->header.ucode_array_offset_bytes));
2493         fw_size = le32_to_cpu(ce_hdr->header.ucode_size_bytes) / 4;
2494         WREG32_SOC15(GC, 0, mmCP_CE_UCODE_ADDR, 0);
2495         for (i = 0; i < fw_size; i++)
2496                 WREG32_SOC15(GC, 0, mmCP_CE_UCODE_DATA, le32_to_cpup(fw_data++));
2497         WREG32_SOC15(GC, 0, mmCP_CE_UCODE_ADDR, adev->gfx.ce_fw_version);
2498
2499         /* ME */
2500         fw_data = (const __le32 *)
2501                 (adev->gfx.me_fw->data +
2502                  le32_to_cpu(me_hdr->header.ucode_array_offset_bytes));
2503         fw_size = le32_to_cpu(me_hdr->header.ucode_size_bytes) / 4;
2504         WREG32_SOC15(GC, 0, mmCP_ME_RAM_WADDR, 0);
2505         for (i = 0; i < fw_size; i++)
2506                 WREG32_SOC15(GC, 0, mmCP_ME_RAM_DATA, le32_to_cpup(fw_data++));
2507         WREG32_SOC15(GC, 0, mmCP_ME_RAM_WADDR, adev->gfx.me_fw_version);
2508
2509         return 0;
2510 }
2511
2512 static int gfx_v9_0_cp_gfx_start(struct amdgpu_device *adev)
2513 {
2514         struct amdgpu_ring *ring = &adev->gfx.gfx_ring[0];
2515         const struct cs_section_def *sect = NULL;
2516         const struct cs_extent_def *ext = NULL;
2517         int r, i, tmp;
2518
2519         /* init the CP */
2520         WREG32_SOC15(GC, 0, mmCP_MAX_CONTEXT, adev->gfx.config.max_hw_contexts - 1);
2521         WREG32_SOC15(GC, 0, mmCP_DEVICE_ID, 1);
2522
2523         gfx_v9_0_cp_gfx_enable(adev, true);
2524
2525         r = amdgpu_ring_alloc(ring, gfx_v9_0_get_csb_size(adev) + 4 + 3);
2526         if (r) {
2527                 DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r);
2528                 return r;
2529         }
2530
2531         amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
2532         amdgpu_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
2533
2534         amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1));
2535         amdgpu_ring_write(ring, 0x80000000);
2536         amdgpu_ring_write(ring, 0x80000000);
2537
2538         for (sect = gfx9_cs_data; sect->section != NULL; ++sect) {
2539                 for (ext = sect->section; ext->extent != NULL; ++ext) {
2540                         if (sect->id == SECT_CONTEXT) {
2541                                 amdgpu_ring_write(ring,
2542                                        PACKET3(PACKET3_SET_CONTEXT_REG,
2543                                                ext->reg_count));
2544                                 amdgpu_ring_write(ring,
2545                                        ext->reg_index - PACKET3_SET_CONTEXT_REG_START);
2546                                 for (i = 0; i < ext->reg_count; i++)
2547                                         amdgpu_ring_write(ring, ext->extent[i]);
2548                         }
2549                 }
2550         }
2551
2552         amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
2553         amdgpu_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE);
2554
2555         amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));
2556         amdgpu_ring_write(ring, 0);
2557
2558         amdgpu_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2));
2559         amdgpu_ring_write(ring, PACKET3_BASE_INDEX(CE_PARTITION_BASE));
2560         amdgpu_ring_write(ring, 0x8000);
2561         amdgpu_ring_write(ring, 0x8000);
2562
2563         amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG,1));
2564         tmp = (PACKET3_SET_UCONFIG_REG_INDEX_TYPE |
2565                 (SOC15_REG_OFFSET(GC, 0, mmVGT_INDEX_TYPE) - PACKET3_SET_UCONFIG_REG_START));
2566         amdgpu_ring_write(ring, tmp);
2567         amdgpu_ring_write(ring, 0);
2568
2569         amdgpu_ring_commit(ring);
2570
2571         return 0;
2572 }
2573
2574 static int gfx_v9_0_cp_gfx_resume(struct amdgpu_device *adev)
2575 {
2576         struct amdgpu_ring *ring;
2577         u32 tmp;
2578         u32 rb_bufsz;
2579         u64 rb_addr, rptr_addr, wptr_gpu_addr;
2580
2581         /* Set the write pointer delay */
2582         WREG32_SOC15(GC, 0, mmCP_RB_WPTR_DELAY, 0);
2583
2584         /* set the RB to use vmid 0 */
2585         WREG32_SOC15(GC, 0, mmCP_RB_VMID, 0);
2586
2587         /* Set ring buffer size */
2588         ring = &adev->gfx.gfx_ring[0];
2589         rb_bufsz = order_base_2(ring->ring_size / 8);
2590         tmp = REG_SET_FIELD(0, CP_RB0_CNTL, RB_BUFSZ, rb_bufsz);
2591         tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, RB_BLKSZ, rb_bufsz - 2);
2592 #ifdef __BIG_ENDIAN
2593         tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, BUF_SWAP, 1);
2594 #endif
2595         WREG32_SOC15(GC, 0, mmCP_RB0_CNTL, tmp);
2596
2597         /* Initialize the ring buffer's write pointers */
2598         ring->wptr = 0;
2599         WREG32_SOC15(GC, 0, mmCP_RB0_WPTR, lower_32_bits(ring->wptr));
2600         WREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI, upper_32_bits(ring->wptr));
2601
2602         /* set the wb address wether it's enabled or not */
2603         rptr_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
2604         WREG32_SOC15(GC, 0, mmCP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr));
2605         WREG32_SOC15(GC, 0, mmCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & CP_RB_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK);
2606
2607         wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
2608         WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_LO, lower_32_bits(wptr_gpu_addr));
2609         WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI, upper_32_bits(wptr_gpu_addr));
2610
2611         mdelay(1);
2612         WREG32_SOC15(GC, 0, mmCP_RB0_CNTL, tmp);
2613
2614         rb_addr = ring->gpu_addr >> 8;
2615         WREG32_SOC15(GC, 0, mmCP_RB0_BASE, rb_addr);
2616         WREG32_SOC15(GC, 0, mmCP_RB0_BASE_HI, upper_32_bits(rb_addr));
2617
2618         tmp = RREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL);
2619         if (ring->use_doorbell) {
2620                 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
2621                                     DOORBELL_OFFSET, ring->doorbell_index);
2622                 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
2623                                     DOORBELL_EN, 1);
2624         } else {
2625                 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, DOORBELL_EN, 0);
2626         }
2627         WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL, tmp);
2628
2629         tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER,
2630                         DOORBELL_RANGE_LOWER, ring->doorbell_index);
2631         WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_LOWER, tmp);
2632
2633         WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_UPPER,
2634                        CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_MASK);
2635
2636
2637         /* start the ring */
2638         gfx_v9_0_cp_gfx_start(adev);
2639         ring->sched.ready = true;
2640
2641         return 0;
2642 }
2643
2644 static void gfx_v9_0_cp_compute_enable(struct amdgpu_device *adev, bool enable)
2645 {
2646         int i;
2647
2648         if (enable) {
2649                 WREG32_SOC15(GC, 0, mmCP_MEC_CNTL, 0);
2650         } else {
2651                 WREG32_SOC15(GC, 0, mmCP_MEC_CNTL,
2652                         (CP_MEC_CNTL__MEC_ME1_HALT_MASK | CP_MEC_CNTL__MEC_ME2_HALT_MASK));
2653                 for (i = 0; i < adev->gfx.num_compute_rings; i++)
2654                         adev->gfx.compute_ring[i].sched.ready = false;
2655                 adev->gfx.kiq.ring.sched.ready = false;
2656         }
2657         udelay(50);
2658 }
2659
2660 static int gfx_v9_0_cp_compute_load_microcode(struct amdgpu_device *adev)
2661 {
2662         const struct gfx_firmware_header_v1_0 *mec_hdr;
2663         const __le32 *fw_data;
2664         unsigned i;
2665         u32 tmp;
2666
2667         if (!adev->gfx.mec_fw)
2668                 return -EINVAL;
2669
2670         gfx_v9_0_cp_compute_enable(adev, false);
2671
2672         mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
2673         amdgpu_ucode_print_gfx_hdr(&mec_hdr->header);
2674
2675         fw_data = (const __le32 *)
2676                 (adev->gfx.mec_fw->data +
2677                  le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes));
2678         tmp = 0;
2679         tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, VMID, 0);
2680         tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0);
2681         WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_CNTL, tmp);
2682
2683         WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_LO,
2684                 adev->gfx.mec.mec_fw_gpu_addr & 0xFFFFF000);
2685         WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_HI,
2686                 upper_32_bits(adev->gfx.mec.mec_fw_gpu_addr));
2687
2688         /* MEC1 */
2689         WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_ADDR,
2690                          mec_hdr->jt_offset);
2691         for (i = 0; i < mec_hdr->jt_size; i++)
2692                 WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_DATA,
2693                         le32_to_cpup(fw_data + mec_hdr->jt_offset + i));
2694
2695         WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_ADDR,
2696                         adev->gfx.mec_fw_version);
2697         /* Todo : Loading MEC2 firmware is only necessary if MEC2 should run different microcode than MEC1. */
2698
2699         return 0;
2700 }
2701
2702 /* KIQ functions */
2703 static void gfx_v9_0_kiq_setting(struct amdgpu_ring *ring)
2704 {
2705         uint32_t tmp;
2706         struct amdgpu_device *adev = ring->adev;
2707
2708         /* tell RLC which is KIQ queue */
2709         tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS);
2710         tmp &= 0xffffff00;
2711         tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue);
2712         WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS, tmp);
2713         tmp |= 0x80;
2714         WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS, tmp);
2715 }
2716
2717 static int gfx_v9_0_kiq_kcq_enable(struct amdgpu_device *adev)
2718 {
2719         struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring;
2720         uint64_t queue_mask = 0;
2721         int r, i;
2722
2723         for (i = 0; i < AMDGPU_MAX_COMPUTE_QUEUES; ++i) {
2724                 if (!test_bit(i, adev->gfx.mec.queue_bitmap))
2725                         continue;
2726
2727                 /* This situation may be hit in the future if a new HW
2728                  * generation exposes more than 64 queues. If so, the
2729                  * definition of queue_mask needs updating */
2730                 if (WARN_ON(i >= (sizeof(queue_mask)*8))) {
2731                         DRM_ERROR("Invalid KCQ enabled: %d\n", i);
2732                         break;
2733                 }
2734
2735                 queue_mask |= (1ull << i);
2736         }
2737
2738         r = amdgpu_ring_alloc(kiq_ring, (7 * adev->gfx.num_compute_rings) + 8);
2739         if (r) {
2740                 DRM_ERROR("Failed to lock KIQ (%d).\n", r);
2741                 return r;
2742         }
2743
2744         /* set resources */
2745         amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_RESOURCES, 6));
2746         amdgpu_ring_write(kiq_ring, PACKET3_SET_RESOURCES_VMID_MASK(0) |
2747                           PACKET3_SET_RESOURCES_QUEUE_TYPE(0)); /* vmid_mask:0 queue_type:0 (KIQ) */
2748         amdgpu_ring_write(kiq_ring, lower_32_bits(queue_mask)); /* queue mask lo */
2749         amdgpu_ring_write(kiq_ring, upper_32_bits(queue_mask)); /* queue mask hi */
2750         amdgpu_ring_write(kiq_ring, 0); /* gws mask lo */
2751         amdgpu_ring_write(kiq_ring, 0); /* gws mask hi */
2752         amdgpu_ring_write(kiq_ring, 0); /* oac mask */
2753         amdgpu_ring_write(kiq_ring, 0); /* gds heap base:0, gds heap size:0 */
2754         for (i = 0; i < adev->gfx.num_compute_rings; i++) {
2755                 struct amdgpu_ring *ring = &adev->gfx.compute_ring[i];
2756                 uint64_t mqd_addr = amdgpu_bo_gpu_offset(ring->mqd_obj);
2757                 uint64_t wptr_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
2758
2759                 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5));
2760                 /* Q_sel:0, vmid:0, vidmem: 1, engine:0, num_Q:1*/
2761                 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */
2762                                   PACKET3_MAP_QUEUES_QUEUE_SEL(0) | /* Queue_Sel */
2763                                   PACKET3_MAP_QUEUES_VMID(0) | /* VMID */
2764                                   PACKET3_MAP_QUEUES_QUEUE(ring->queue) |
2765                                   PACKET3_MAP_QUEUES_PIPE(ring->pipe) |
2766                                   PACKET3_MAP_QUEUES_ME((ring->me == 1 ? 0 : 1)) |
2767                                   PACKET3_MAP_QUEUES_QUEUE_TYPE(0) | /*queue_type: normal compute queue */
2768                                   PACKET3_MAP_QUEUES_ALLOC_FORMAT(0) | /* alloc format: all_on_one_pipe */
2769                                   PACKET3_MAP_QUEUES_ENGINE_SEL(0) | /* engine_sel: compute */
2770                                   PACKET3_MAP_QUEUES_NUM_QUEUES(1)); /* num_queues: must be 1 */
2771                 amdgpu_ring_write(kiq_ring, PACKET3_MAP_QUEUES_DOORBELL_OFFSET(ring->doorbell_index));
2772                 amdgpu_ring_write(kiq_ring, lower_32_bits(mqd_addr));
2773                 amdgpu_ring_write(kiq_ring, upper_32_bits(mqd_addr));
2774                 amdgpu_ring_write(kiq_ring, lower_32_bits(wptr_addr));
2775                 amdgpu_ring_write(kiq_ring, upper_32_bits(wptr_addr));
2776         }
2777
2778         r = amdgpu_ring_test_helper(kiq_ring);
2779         if (r)
2780                 DRM_ERROR("KCQ enable failed\n");
2781
2782         return r;
2783 }
2784
2785 static int gfx_v9_0_mqd_init(struct amdgpu_ring *ring)
2786 {
2787         struct amdgpu_device *adev = ring->adev;
2788         struct v9_mqd *mqd = ring->mqd_ptr;
2789         uint64_t hqd_gpu_addr, wb_gpu_addr, eop_base_addr;
2790         uint32_t tmp;
2791
2792         mqd->header = 0xC0310800;
2793         mqd->compute_pipelinestat_enable = 0x00000001;
2794         mqd->compute_static_thread_mgmt_se0 = 0xffffffff;
2795         mqd->compute_static_thread_mgmt_se1 = 0xffffffff;
2796         mqd->compute_static_thread_mgmt_se2 = 0xffffffff;
2797         mqd->compute_static_thread_mgmt_se3 = 0xffffffff;
2798         mqd->compute_misc_reserved = 0x00000003;
2799
2800         mqd->dynamic_cu_mask_addr_lo =
2801                 lower_32_bits(ring->mqd_gpu_addr
2802                               + offsetof(struct v9_mqd_allocation, dynamic_cu_mask));
2803         mqd->dynamic_cu_mask_addr_hi =
2804                 upper_32_bits(ring->mqd_gpu_addr
2805                               + offsetof(struct v9_mqd_allocation, dynamic_cu_mask));
2806
2807         eop_base_addr = ring->eop_gpu_addr >> 8;
2808         mqd->cp_hqd_eop_base_addr_lo = eop_base_addr;
2809         mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr);
2810
2811         /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */
2812         tmp = RREG32_SOC15(GC, 0, mmCP_HQD_EOP_CONTROL);
2813         tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE,
2814                         (order_base_2(GFX9_MEC_HPD_SIZE / 4) - 1));
2815
2816         mqd->cp_hqd_eop_control = tmp;
2817
2818         /* enable doorbell? */
2819         tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL);
2820
2821         if (ring->use_doorbell) {
2822                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
2823                                     DOORBELL_OFFSET, ring->doorbell_index);
2824                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
2825                                     DOORBELL_EN, 1);
2826                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
2827                                     DOORBELL_SOURCE, 0);
2828                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
2829                                     DOORBELL_HIT, 0);
2830         } else {
2831                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
2832                                          DOORBELL_EN, 0);
2833         }
2834
2835         mqd->cp_hqd_pq_doorbell_control = tmp;
2836
2837         /* disable the queue if it's active */
2838         ring->wptr = 0;
2839         mqd->cp_hqd_dequeue_request = 0;
2840         mqd->cp_hqd_pq_rptr = 0;
2841         mqd->cp_hqd_pq_wptr_lo = 0;
2842         mqd->cp_hqd_pq_wptr_hi = 0;
2843
2844         /* set the pointer to the MQD */
2845         mqd->cp_mqd_base_addr_lo = ring->mqd_gpu_addr & 0xfffffffc;
2846         mqd->cp_mqd_base_addr_hi = upper_32_bits(ring->mqd_gpu_addr);
2847
2848         /* set MQD vmid to 0 */
2849         tmp = RREG32_SOC15(GC, 0, mmCP_MQD_CONTROL);
2850         tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0);
2851         mqd->cp_mqd_control = tmp;
2852
2853         /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */
2854         hqd_gpu_addr = ring->gpu_addr >> 8;
2855         mqd->cp_hqd_pq_base_lo = hqd_gpu_addr;
2856         mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr);
2857
2858         /* set up the HQD, this is similar to CP_RB0_CNTL */
2859         tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_CONTROL);
2860         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE,
2861                             (order_base_2(ring->ring_size / 4) - 1));
2862         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE,
2863                         ((order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1) << 8));
2864 #ifdef __BIG_ENDIAN
2865         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ENDIAN_SWAP, 1);
2866 #endif
2867         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 0);
2868         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ROQ_PQ_IB_FLIP, 0);
2869         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1);
2870         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1);
2871         mqd->cp_hqd_pq_control = tmp;
2872
2873         /* set the wb address whether it's enabled or not */
2874         wb_gpu_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
2875         mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc;
2876         mqd->cp_hqd_pq_rptr_report_addr_hi =
2877                 upper_32_bits(wb_gpu_addr) & 0xffff;
2878
2879         /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */
2880         wb_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
2881         mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc;
2882         mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff;
2883
2884         tmp = 0;
2885         /* enable the doorbell if requested */
2886         if (ring->use_doorbell) {
2887                 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL);
2888                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
2889                                 DOORBELL_OFFSET, ring->doorbell_index);
2890
2891                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
2892                                          DOORBELL_EN, 1);
2893                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
2894                                          DOORBELL_SOURCE, 0);
2895                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
2896                                          DOORBELL_HIT, 0);
2897         }
2898
2899         mqd->cp_hqd_pq_doorbell_control = tmp;
2900
2901         /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */
2902         ring->wptr = 0;
2903         mqd->cp_hqd_pq_rptr = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR);
2904
2905         /* set the vmid for the queue */
2906         mqd->cp_hqd_vmid = 0;
2907
2908         tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PERSISTENT_STATE);
2909         tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, PRELOAD_SIZE, 0x53);
2910         mqd->cp_hqd_persistent_state = tmp;
2911
2912         /* set MIN_IB_AVAIL_SIZE */
2913         tmp = RREG32_SOC15(GC, 0, mmCP_HQD_IB_CONTROL);
2914         tmp = REG_SET_FIELD(tmp, CP_HQD_IB_CONTROL, MIN_IB_AVAIL_SIZE, 3);
2915         mqd->cp_hqd_ib_control = tmp;
2916
2917         /* activate the queue */
2918         mqd->cp_hqd_active = 1;
2919
2920         return 0;
2921 }
2922
2923 static int gfx_v9_0_kiq_init_register(struct amdgpu_ring *ring)
2924 {
2925         struct amdgpu_device *adev = ring->adev;
2926         struct v9_mqd *mqd = ring->mqd_ptr;
2927         int j;
2928
2929         /* disable wptr polling */
2930         WREG32_FIELD15(GC, 0, CP_PQ_WPTR_POLL_CNTL, EN, 0);
2931
2932         WREG32_SOC15(GC, 0, mmCP_HQD_EOP_BASE_ADDR,
2933                mqd->cp_hqd_eop_base_addr_lo);
2934         WREG32_SOC15(GC, 0, mmCP_HQD_EOP_BASE_ADDR_HI,
2935                mqd->cp_hqd_eop_base_addr_hi);
2936
2937         /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */
2938         WREG32_SOC15(GC, 0, mmCP_HQD_EOP_CONTROL,
2939                mqd->cp_hqd_eop_control);
2940
2941         /* enable doorbell? */
2942         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL,
2943                mqd->cp_hqd_pq_doorbell_control);
2944
2945         /* disable the queue if it's active */
2946         if (RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1) {
2947                 WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST, 1);
2948                 for (j = 0; j < adev->usec_timeout; j++) {
2949                         if (!(RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1))
2950                                 break;
2951                         udelay(1);
2952                 }
2953                 WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST,
2954                        mqd->cp_hqd_dequeue_request);
2955                 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR,
2956                        mqd->cp_hqd_pq_rptr);
2957                 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_LO,
2958                        mqd->cp_hqd_pq_wptr_lo);
2959                 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_HI,
2960                        mqd->cp_hqd_pq_wptr_hi);
2961         }
2962
2963         /* set the pointer to the MQD */
2964         WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR,
2965                mqd->cp_mqd_base_addr_lo);
2966         WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR_HI,
2967                mqd->cp_mqd_base_addr_hi);
2968
2969         /* set MQD vmid to 0 */
2970         WREG32_SOC15(GC, 0, mmCP_MQD_CONTROL,
2971                mqd->cp_mqd_control);
2972
2973         /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */
2974         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_BASE,
2975                mqd->cp_hqd_pq_base_lo);
2976         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_BASE_HI,
2977                mqd->cp_hqd_pq_base_hi);
2978
2979         /* set up the HQD, this is similar to CP_RB0_CNTL */
2980         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_CONTROL,
2981                mqd->cp_hqd_pq_control);
2982
2983         /* set the wb address whether it's enabled or not */
2984         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR_REPORT_ADDR,
2985                                 mqd->cp_hqd_pq_rptr_report_addr_lo);
2986         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI,
2987                                 mqd->cp_hqd_pq_rptr_report_addr_hi);
2988
2989         /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */
2990         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR,
2991                mqd->cp_hqd_pq_wptr_poll_addr_lo);
2992         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR_HI,
2993                mqd->cp_hqd_pq_wptr_poll_addr_hi);
2994
2995         /* enable the doorbell if requested */
2996         if (ring->use_doorbell) {
2997                 WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_LOWER,
2998                                         (adev->doorbell_index.kiq * 2) << 2);
2999                 WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_UPPER,
3000                                         (adev->doorbell_index.userqueue_end * 2) << 2);
3001         }
3002
3003         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL,
3004                mqd->cp_hqd_pq_doorbell_control);
3005
3006         /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */
3007         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_LO,
3008                mqd->cp_hqd_pq_wptr_lo);
3009         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_HI,
3010                mqd->cp_hqd_pq_wptr_hi);
3011
3012         /* set the vmid for the queue */
3013         WREG32_SOC15(GC, 0, mmCP_HQD_VMID, mqd->cp_hqd_vmid);
3014
3015         WREG32_SOC15(GC, 0, mmCP_HQD_PERSISTENT_STATE,
3016                mqd->cp_hqd_persistent_state);
3017
3018         /* activate the queue */
3019         WREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE,
3020                mqd->cp_hqd_active);
3021
3022         if (ring->use_doorbell)
3023                 WREG32_FIELD15(GC, 0, CP_PQ_STATUS, DOORBELL_ENABLE, 1);
3024
3025         return 0;
3026 }
3027
3028 static int gfx_v9_0_kiq_fini_register(struct amdgpu_ring *ring)
3029 {
3030         struct amdgpu_device *adev = ring->adev;
3031         int j;
3032
3033         /* disable the queue if it's active */
3034         if (RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1) {
3035
3036                 WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST, 1);
3037
3038                 for (j = 0; j < adev->usec_timeout; j++) {
3039                         if (!(RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1))
3040                                 break;
3041                         udelay(1);
3042                 }
3043
3044                 if (j == AMDGPU_MAX_USEC_TIMEOUT) {
3045                         DRM_DEBUG("KIQ dequeue request failed.\n");
3046
3047                         /* Manual disable if dequeue request times out */
3048                         WREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE, 0);
3049                 }
3050
3051                 WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST,
3052                       0);
3053         }
3054
3055         WREG32_SOC15(GC, 0, mmCP_HQD_IQ_TIMER, 0);
3056         WREG32_SOC15(GC, 0, mmCP_HQD_IB_CONTROL, 0);
3057         WREG32_SOC15(GC, 0, mmCP_HQD_PERSISTENT_STATE, 0);
3058         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL, 0x40000000);
3059         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL, 0);
3060         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR, 0);
3061         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_HI, 0);
3062         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_LO, 0);
3063
3064         return 0;
3065 }
3066
3067 static int gfx_v9_0_kiq_init_queue(struct amdgpu_ring *ring)
3068 {
3069         struct amdgpu_device *adev = ring->adev;
3070         struct v9_mqd *mqd = ring->mqd_ptr;
3071         int mqd_idx = AMDGPU_MAX_COMPUTE_RINGS;
3072
3073         gfx_v9_0_kiq_setting(ring);
3074
3075         if (adev->in_gpu_reset) { /* for GPU_RESET case */
3076                 /* reset MQD to a clean status */
3077                 if (adev->gfx.mec.mqd_backup[mqd_idx])
3078                         memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(struct v9_mqd_allocation));
3079
3080                 /* reset ring buffer */
3081                 ring->wptr = 0;
3082                 amdgpu_ring_clear_ring(ring);
3083
3084                 mutex_lock(&adev->srbm_mutex);
3085                 soc15_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
3086                 gfx_v9_0_kiq_init_register(ring);
3087                 soc15_grbm_select(adev, 0, 0, 0, 0);
3088                 mutex_unlock(&adev->srbm_mutex);
3089         } else {
3090                 memset((void *)mqd, 0, sizeof(struct v9_mqd_allocation));
3091                 ((struct v9_mqd_allocation *)mqd)->dynamic_cu_mask = 0xFFFFFFFF;
3092                 ((struct v9_mqd_allocation *)mqd)->dynamic_rb_mask = 0xFFFFFFFF;
3093                 mutex_lock(&adev->srbm_mutex);
3094                 soc15_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
3095                 gfx_v9_0_mqd_init(ring);
3096                 gfx_v9_0_kiq_init_register(ring);
3097                 soc15_grbm_select(adev, 0, 0, 0, 0);
3098                 mutex_unlock(&adev->srbm_mutex);
3099
3100                 if (adev->gfx.mec.mqd_backup[mqd_idx])
3101                         memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(struct v9_mqd_allocation));
3102         }
3103
3104         return 0;
3105 }
3106
3107 static int gfx_v9_0_kcq_init_queue(struct amdgpu_ring *ring)
3108 {
3109         struct amdgpu_device *adev = ring->adev;
3110         struct v9_mqd *mqd = ring->mqd_ptr;
3111         int mqd_idx = ring - &adev->gfx.compute_ring[0];
3112
3113         if (!adev->in_gpu_reset && !adev->in_suspend) {
3114                 memset((void *)mqd, 0, sizeof(struct v9_mqd_allocation));
3115                 ((struct v9_mqd_allocation *)mqd)->dynamic_cu_mask = 0xFFFFFFFF;
3116                 ((struct v9_mqd_allocation *)mqd)->dynamic_rb_mask = 0xFFFFFFFF;
3117                 mutex_lock(&adev->srbm_mutex);
3118                 soc15_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
3119                 gfx_v9_0_mqd_init(ring);
3120                 soc15_grbm_select(adev, 0, 0, 0, 0);
3121                 mutex_unlock(&adev->srbm_mutex);
3122
3123                 if (adev->gfx.mec.mqd_backup[mqd_idx])
3124                         memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(struct v9_mqd_allocation));
3125         } else if (adev->in_gpu_reset) { /* for GPU_RESET case */
3126                 /* reset MQD to a clean status */
3127                 if (adev->gfx.mec.mqd_backup[mqd_idx])
3128                         memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(struct v9_mqd_allocation));
3129
3130                 /* reset ring buffer */
3131                 ring->wptr = 0;
3132                 amdgpu_ring_clear_ring(ring);
3133         } else {
3134                 amdgpu_ring_clear_ring(ring);
3135         }
3136
3137         return 0;
3138 }
3139
3140 static int gfx_v9_0_kiq_resume(struct amdgpu_device *adev)
3141 {
3142         struct amdgpu_ring *ring;
3143         int r;
3144
3145         ring = &adev->gfx.kiq.ring;
3146
3147         r = amdgpu_bo_reserve(ring->mqd_obj, false);
3148         if (unlikely(r != 0))
3149                 return r;
3150
3151         r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr);
3152         if (unlikely(r != 0))
3153                 return r;
3154
3155         gfx_v9_0_kiq_init_queue(ring);
3156         amdgpu_bo_kunmap(ring->mqd_obj);
3157         ring->mqd_ptr = NULL;
3158         amdgpu_bo_unreserve(ring->mqd_obj);
3159         ring->sched.ready = true;
3160         return 0;
3161 }
3162
3163 static int gfx_v9_0_kcq_resume(struct amdgpu_device *adev)
3164 {
3165         struct amdgpu_ring *ring = NULL;
3166         int r = 0, i;
3167
3168         gfx_v9_0_cp_compute_enable(adev, true);
3169
3170         for (i = 0; i < adev->gfx.num_compute_rings; i++) {
3171                 ring = &adev->gfx.compute_ring[i];
3172
3173                 r = amdgpu_bo_reserve(ring->mqd_obj, false);
3174                 if (unlikely(r != 0))
3175                         goto done;
3176                 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr);
3177                 if (!r) {
3178                         r = gfx_v9_0_kcq_init_queue(ring);
3179                         amdgpu_bo_kunmap(ring->mqd_obj);
3180                         ring->mqd_ptr = NULL;
3181                 }
3182                 amdgpu_bo_unreserve(ring->mqd_obj);
3183                 if (r)
3184                         goto done;
3185         }
3186
3187         r = gfx_v9_0_kiq_kcq_enable(adev);
3188 done:
3189         return r;
3190 }
3191
3192 static int gfx_v9_0_cp_resume(struct amdgpu_device *adev)
3193 {
3194         int r, i;
3195         struct amdgpu_ring *ring;
3196
3197         if (!(adev->flags & AMD_IS_APU))
3198                 gfx_v9_0_enable_gui_idle_interrupt(adev, false);
3199
3200         if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
3201                 /* legacy firmware loading */
3202                 r = gfx_v9_0_cp_gfx_load_microcode(adev);
3203                 if (r)
3204                         return r;
3205
3206                 r = gfx_v9_0_cp_compute_load_microcode(adev);
3207                 if (r)
3208                         return r;
3209         }
3210
3211         r = gfx_v9_0_kiq_resume(adev);
3212         if (r)
3213                 return r;
3214
3215         r = gfx_v9_0_cp_gfx_resume(adev);
3216         if (r)
3217                 return r;
3218
3219         r = gfx_v9_0_kcq_resume(adev);
3220         if (r)
3221                 return r;
3222
3223         ring = &adev->gfx.gfx_ring[0];
3224         r = amdgpu_ring_test_helper(ring);
3225         if (r)
3226                 return r;
3227
3228         for (i = 0; i < adev->gfx.num_compute_rings; i++) {
3229                 ring = &adev->gfx.compute_ring[i];
3230                 amdgpu_ring_test_helper(ring);
3231         }
3232
3233         gfx_v9_0_enable_gui_idle_interrupt(adev, true);
3234
3235         return 0;
3236 }
3237
3238 static void gfx_v9_0_cp_enable(struct amdgpu_device *adev, bool enable)
3239 {
3240         gfx_v9_0_cp_gfx_enable(adev, enable);
3241         gfx_v9_0_cp_compute_enable(adev, enable);
3242 }
3243
3244 static int gfx_v9_0_hw_init(void *handle)
3245 {
3246         int r;
3247         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3248
3249         gfx_v9_0_init_golden_registers(adev);
3250
3251         gfx_v9_0_constants_init(adev);
3252
3253         r = gfx_v9_0_csb_vram_pin(adev);
3254         if (r)
3255                 return r;
3256
3257         r = adev->gfx.rlc.funcs->resume(adev);
3258         if (r)
3259                 return r;
3260
3261         r = gfx_v9_0_cp_resume(adev);
3262         if (r)
3263                 return r;
3264
3265         r = gfx_v9_0_ngg_en(adev);
3266         if (r)
3267                 return r;
3268
3269         return r;
3270 }
3271
3272 static int gfx_v9_0_kcq_disable(struct amdgpu_device *adev)
3273 {
3274         int r, i;
3275         struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring;
3276
3277         r = amdgpu_ring_alloc(kiq_ring, 6 * adev->gfx.num_compute_rings);
3278         if (r)
3279                 DRM_ERROR("Failed to lock KIQ (%d).\n", r);
3280
3281         for (i = 0; i < adev->gfx.num_compute_rings; i++) {
3282                 struct amdgpu_ring *ring = &adev->gfx.compute_ring[i];
3283
3284                 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_UNMAP_QUEUES, 4));
3285                 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */
3286                                                 PACKET3_UNMAP_QUEUES_ACTION(1) | /* RESET_QUEUES */
3287                                                 PACKET3_UNMAP_QUEUES_QUEUE_SEL(0) |
3288                                                 PACKET3_UNMAP_QUEUES_ENGINE_SEL(0) |
3289                                                 PACKET3_UNMAP_QUEUES_NUM_QUEUES(1));
3290                 amdgpu_ring_write(kiq_ring, PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET0(ring->doorbell_index));
3291                 amdgpu_ring_write(kiq_ring, 0);
3292                 amdgpu_ring_write(kiq_ring, 0);
3293                 amdgpu_ring_write(kiq_ring, 0);
3294         }
3295         r = amdgpu_ring_test_helper(kiq_ring);
3296         if (r)
3297                 DRM_ERROR("KCQ disable failed\n");
3298
3299         return r;
3300 }
3301
3302 static int gfx_v9_0_hw_fini(void *handle)
3303 {
3304         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3305
3306         amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0);
3307         amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0);
3308
3309         /* disable KCQ to avoid CPC touch memory not valid anymore */
3310         gfx_v9_0_kcq_disable(adev);
3311
3312         if (amdgpu_sriov_vf(adev)) {
3313                 gfx_v9_0_cp_gfx_enable(adev, false);
3314                 /* must disable polling for SRIOV when hw finished, otherwise
3315                  * CPC engine may still keep fetching WB address which is already
3316                  * invalid after sw finished and trigger DMAR reading error in
3317                  * hypervisor side.
3318                  */
3319                 WREG32_FIELD15(GC, 0, CP_PQ_WPTR_POLL_CNTL, EN, 0);
3320                 return 0;
3321         }
3322
3323         /* Use deinitialize sequence from CAIL when unbinding device from driver,
3324          * otherwise KIQ is hanging when binding back
3325          */
3326         if (!adev->in_gpu_reset && !adev->in_suspend) {
3327                 mutex_lock(&adev->srbm_mutex);
3328                 soc15_grbm_select(adev, adev->gfx.kiq.ring.me,
3329                                 adev->gfx.kiq.ring.pipe,
3330                                 adev->gfx.kiq.ring.queue, 0);
3331                 gfx_v9_0_kiq_fini_register(&adev->gfx.kiq.ring);
3332                 soc15_grbm_select(adev, 0, 0, 0, 0);
3333                 mutex_unlock(&adev->srbm_mutex);
3334         }
3335
3336         gfx_v9_0_cp_enable(adev, false);
3337         adev->gfx.rlc.funcs->stop(adev);
3338
3339         gfx_v9_0_csb_vram_unpin(adev);
3340
3341         return 0;
3342 }
3343
3344 static int gfx_v9_0_suspend(void *handle)
3345 {
3346         return gfx_v9_0_hw_fini(handle);
3347 }
3348
3349 static int gfx_v9_0_resume(void *handle)
3350 {
3351         return gfx_v9_0_hw_init(handle);
3352 }
3353
3354 static bool gfx_v9_0_is_idle(void *handle)
3355 {
3356         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3357
3358         if (REG_GET_FIELD(RREG32_SOC15(GC, 0, mmGRBM_STATUS),
3359                                 GRBM_STATUS, GUI_ACTIVE))
3360                 return false;
3361         else
3362                 return true;
3363 }
3364
3365 static int gfx_v9_0_wait_for_idle(void *handle)
3366 {
3367         unsigned i;
3368         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3369
3370         for (i = 0; i < adev->usec_timeout; i++) {
3371                 if (gfx_v9_0_is_idle(handle))
3372                         return 0;
3373                 udelay(1);
3374         }
3375         return -ETIMEDOUT;
3376 }
3377
3378 static int gfx_v9_0_soft_reset(void *handle)
3379 {
3380         u32 grbm_soft_reset = 0;
3381         u32 tmp;
3382         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3383
3384         /* GRBM_STATUS */
3385         tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS);
3386         if (tmp & (GRBM_STATUS__PA_BUSY_MASK | GRBM_STATUS__SC_BUSY_MASK |
3387                    GRBM_STATUS__BCI_BUSY_MASK | GRBM_STATUS__SX_BUSY_MASK |
3388                    GRBM_STATUS__TA_BUSY_MASK | GRBM_STATUS__VGT_BUSY_MASK |
3389                    GRBM_STATUS__DB_BUSY_MASK | GRBM_STATUS__CB_BUSY_MASK |
3390                    GRBM_STATUS__GDS_BUSY_MASK | GRBM_STATUS__SPI_BUSY_MASK |
3391                    GRBM_STATUS__IA_BUSY_MASK | GRBM_STATUS__IA_BUSY_NO_DMA_MASK)) {
3392                 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
3393                                                 GRBM_SOFT_RESET, SOFT_RESET_CP, 1);
3394                 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
3395                                                 GRBM_SOFT_RESET, SOFT_RESET_GFX, 1);
3396         }
3397
3398         if (tmp & (GRBM_STATUS__CP_BUSY_MASK | GRBM_STATUS__CP_COHERENCY_BUSY_MASK)) {
3399                 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
3400                                                 GRBM_SOFT_RESET, SOFT_RESET_CP, 1);
3401         }
3402
3403         /* GRBM_STATUS2 */
3404         tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS2);
3405         if (REG_GET_FIELD(tmp, GRBM_STATUS2, RLC_BUSY))
3406                 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
3407                                                 GRBM_SOFT_RESET, SOFT_RESET_RLC, 1);
3408
3409
3410         if (grbm_soft_reset) {
3411                 /* stop the rlc */
3412                 adev->gfx.rlc.funcs->stop(adev);
3413
3414                 /* Disable GFX parsing/prefetching */
3415                 gfx_v9_0_cp_gfx_enable(adev, false);
3416
3417                 /* Disable MEC parsing/prefetching */
3418                 gfx_v9_0_cp_compute_enable(adev, false);
3419
3420                 if (grbm_soft_reset) {
3421                         tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);
3422                         tmp |= grbm_soft_reset;
3423                         dev_info(adev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp);
3424                         WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp);
3425                         tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);
3426
3427                         udelay(50);
3428
3429                         tmp &= ~grbm_soft_reset;
3430                         WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp);
3431                         tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);
3432                 }
3433
3434                 /* Wait a little for things to settle down */
3435                 udelay(50);
3436         }
3437         return 0;
3438 }
3439
3440 static uint64_t gfx_v9_0_get_gpu_clock_counter(struct amdgpu_device *adev)
3441 {
3442         uint64_t clock;
3443
3444         mutex_lock(&adev->gfx.gpu_clock_mutex);
3445         WREG32_SOC15(GC, 0, mmRLC_CAPTURE_GPU_CLOCK_COUNT, 1);
3446         clock = (uint64_t)RREG32_SOC15(GC, 0, mmRLC_GPU_CLOCK_COUNT_LSB) |
3447                 ((uint64_t)RREG32_SOC15(GC, 0, mmRLC_GPU_CLOCK_COUNT_MSB) << 32ULL);
3448         mutex_unlock(&adev->gfx.gpu_clock_mutex);
3449         return clock;
3450 }
3451
3452 static void gfx_v9_0_ring_emit_gds_switch(struct amdgpu_ring *ring,
3453                                           uint32_t vmid,
3454                                           uint32_t gds_base, uint32_t gds_size,
3455                                           uint32_t gws_base, uint32_t gws_size,
3456                                           uint32_t oa_base, uint32_t oa_size)
3457 {
3458         struct amdgpu_device *adev = ring->adev;
3459
3460         /* GDS Base */
3461         gfx_v9_0_write_data_to_reg(ring, 0, false,
3462                                    SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_BASE) + 2 * vmid,
3463                                    gds_base);
3464
3465         /* GDS Size */
3466         gfx_v9_0_write_data_to_reg(ring, 0, false,
3467                                    SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_SIZE) + 2 * vmid,
3468                                    gds_size);
3469
3470         /* GWS */
3471         gfx_v9_0_write_data_to_reg(ring, 0, false,
3472                                    SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID0) + vmid,
3473                                    gws_size << GDS_GWS_VMID0__SIZE__SHIFT | gws_base);
3474
3475         /* OA */
3476         gfx_v9_0_write_data_to_reg(ring, 0, false,
3477                                    SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID0) + vmid,
3478                                    (1 << (oa_size + oa_base)) - (1 << oa_base));
3479 }
3480
3481 static int gfx_v9_0_early_init(void *handle)
3482 {
3483         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3484
3485         adev->gfx.num_gfx_rings = GFX9_NUM_GFX_RINGS;
3486         adev->gfx.num_compute_rings = AMDGPU_MAX_COMPUTE_RINGS;
3487         gfx_v9_0_set_ring_funcs(adev);
3488         gfx_v9_0_set_irq_funcs(adev);
3489         gfx_v9_0_set_gds_init(adev);
3490         gfx_v9_0_set_rlc_funcs(adev);
3491
3492         return 0;
3493 }
3494
3495 static int gfx_v9_0_late_init(void *handle)
3496 {
3497         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3498         int r;
3499
3500         r = amdgpu_irq_get(adev, &adev->gfx.priv_reg_irq, 0);
3501         if (r)
3502                 return r;
3503
3504         r = amdgpu_irq_get(adev, &adev->gfx.priv_inst_irq, 0);
3505         if (r)
3506                 return r;
3507
3508         return 0;
3509 }
3510
3511 static bool gfx_v9_0_is_rlc_enabled(struct amdgpu_device *adev)
3512 {
3513         uint32_t rlc_setting;
3514
3515         /* if RLC is not enabled, do nothing */
3516         rlc_setting = RREG32_SOC15(GC, 0, mmRLC_CNTL);
3517         if (!(rlc_setting & RLC_CNTL__RLC_ENABLE_F32_MASK))
3518                 return false;
3519
3520         return true;
3521 }
3522
3523 static void gfx_v9_0_set_safe_mode(struct amdgpu_device *adev)
3524 {
3525         uint32_t data;
3526         unsigned i;
3527
3528         data = RLC_SAFE_MODE__CMD_MASK;
3529         data |= (1 << RLC_SAFE_MODE__MESSAGE__SHIFT);
3530         WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE, data);
3531
3532         /* wait for RLC_SAFE_MODE */
3533         for (i = 0; i < adev->usec_timeout; i++) {
3534                 if (!REG_GET_FIELD(RREG32_SOC15(GC, 0, mmRLC_SAFE_MODE), RLC_SAFE_MODE, CMD))
3535                         break;
3536                 udelay(1);
3537         }
3538 }
3539
3540 static void gfx_v9_0_unset_safe_mode(struct amdgpu_device *adev)
3541 {
3542         uint32_t data;
3543
3544         data = RLC_SAFE_MODE__CMD_MASK;
3545         WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE, data);
3546 }
3547
3548 static void gfx_v9_0_update_gfx_cg_power_gating(struct amdgpu_device *adev,
3549                                                 bool enable)
3550 {
3551         amdgpu_gfx_rlc_enter_safe_mode(adev);
3552
3553         if ((adev->pg_flags & AMD_PG_SUPPORT_GFX_PG) && enable) {
3554                 gfx_v9_0_enable_gfx_cg_power_gating(adev, true);
3555                 if (adev->pg_flags & AMD_PG_SUPPORT_GFX_PIPELINE)
3556                         gfx_v9_0_enable_gfx_pipeline_powergating(adev, true);
3557         } else {
3558                 gfx_v9_0_enable_gfx_cg_power_gating(adev, false);
3559                 gfx_v9_0_enable_gfx_pipeline_powergating(adev, false);
3560         }
3561
3562         amdgpu_gfx_rlc_exit_safe_mode(adev);
3563 }
3564
3565 static void gfx_v9_0_update_gfx_mg_power_gating(struct amdgpu_device *adev,
3566                                                 bool enable)
3567 {
3568         /* TODO: double check if we need to perform under safe mode */
3569         /* gfx_v9_0_enter_rlc_safe_mode(adev); */
3570
3571         if ((adev->pg_flags & AMD_PG_SUPPORT_GFX_SMG) && enable)
3572                 gfx_v9_0_enable_gfx_static_mg_power_gating(adev, true);
3573         else
3574                 gfx_v9_0_enable_gfx_static_mg_power_gating(adev, false);
3575
3576         if ((adev->pg_flags & AMD_PG_SUPPORT_GFX_DMG) && enable)
3577                 gfx_v9_0_enable_gfx_dynamic_mg_power_gating(adev, true);
3578         else
3579                 gfx_v9_0_enable_gfx_dynamic_mg_power_gating(adev, false);
3580
3581         /* gfx_v9_0_exit_rlc_safe_mode(adev); */
3582 }
3583
3584 static void gfx_v9_0_update_medium_grain_clock_gating(struct amdgpu_device *adev,
3585                                                       bool enable)
3586 {
3587         uint32_t data, def;
3588
3589         /* It is disabled by HW by default */
3590         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) {
3591                 /* 1 - RLC_CGTT_MGCG_OVERRIDE */
3592                 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
3593
3594                 if (adev->asic_type != CHIP_VEGA12)
3595                         data &= ~RLC_CGTT_MGCG_OVERRIDE__CPF_CGTT_SCLK_OVERRIDE_MASK;
3596
3597                 data &= ~(RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK |
3598                           RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK |
3599                           RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK);
3600
3601                 /* only for Vega10 & Raven1 */
3602                 data |= RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK;
3603
3604                 if (def != data)
3605                         WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
3606
3607                 /* MGLS is a global flag to control all MGLS in GFX */
3608                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGLS) {
3609                         /* 2 - RLC memory Light sleep */
3610                         if (adev->cg_flags & AMD_CG_SUPPORT_GFX_RLC_LS) {
3611                                 def = data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL);
3612                                 data |= RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK;
3613                                 if (def != data)
3614                                         WREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL, data);
3615                         }
3616                         /* 3 - CP memory Light sleep */
3617                         if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CP_LS) {
3618                                 def = data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL);
3619                                 data |= CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK;
3620                                 if (def != data)
3621                                         WREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL, data);
3622                         }
3623                 }
3624         } else {
3625                 /* 1 - MGCG_OVERRIDE */
3626                 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
3627
3628                 if (adev->asic_type != CHIP_VEGA12)
3629                         data |= RLC_CGTT_MGCG_OVERRIDE__CPF_CGTT_SCLK_OVERRIDE_MASK;
3630
3631                 data |= (RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK |
3632                          RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK |
3633                          RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK |
3634                          RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK);
3635
3636                 if (def != data)
3637                         WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
3638
3639                 /* 2 - disable MGLS in RLC */
3640                 data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL);
3641                 if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK) {
3642                         data &= ~RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK;
3643                         WREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL, data);
3644                 }
3645
3646                 /* 3 - disable MGLS in CP */
3647                 data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL);
3648                 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) {
3649                         data &= ~CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK;
3650                         WREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL, data);
3651                 }
3652         }
3653 }
3654
3655 static void gfx_v9_0_update_3d_clock_gating(struct amdgpu_device *adev,
3656                                            bool enable)
3657 {
3658         uint32_t data, def;
3659
3660         amdgpu_gfx_rlc_enter_safe_mode(adev);
3661
3662         /* Enable 3D CGCG/CGLS */
3663         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG)) {
3664                 /* write cmd to clear cgcg/cgls ov */
3665                 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
3666                 /* unset CGCG override */
3667                 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_GFX3D_CG_OVERRIDE_MASK;
3668                 /* update CGCG and CGLS override bits */
3669                 if (def != data)
3670                         WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
3671
3672                 /* enable 3Dcgcg FSM(0x0000363f) */
3673                 def = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D);
3674
3675                 data = (0x36 << RLC_CGCG_CGLS_CTRL_3D__CGCG_GFX_IDLE_THRESHOLD__SHIFT) |
3676                         RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK;
3677                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS)
3678                         data |= (0x000F << RLC_CGCG_CGLS_CTRL_3D__CGLS_REP_COMPANSAT_DELAY__SHIFT) |
3679                                 RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK;
3680                 if (def != data)
3681                         WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D, data);
3682
3683                 /* set IDLE_POLL_COUNT(0x00900100) */
3684                 def = RREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL);
3685                 data = (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) |
3686                         (0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT);
3687                 if (def != data)
3688                         WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL, data);
3689         } else {
3690                 /* Disable CGCG/CGLS */
3691                 def = data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D);
3692                 /* disable cgcg, cgls should be disabled */
3693                 data &= ~(RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK |
3694                           RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK);
3695                 /* disable cgcg and cgls in FSM */
3696                 if (def != data)
3697                         WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D, data);
3698         }
3699
3700         amdgpu_gfx_rlc_exit_safe_mode(adev);
3701 }
3702
3703 static void gfx_v9_0_update_coarse_grain_clock_gating(struct amdgpu_device *adev,
3704                                                       bool enable)
3705 {
3706         uint32_t def, data;
3707
3708         amdgpu_gfx_rlc_enter_safe_mode(adev);
3709
3710         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)) {
3711                 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
3712                 /* unset CGCG override */
3713                 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGCG_OVERRIDE_MASK;
3714                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS)
3715                         data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK;
3716                 else
3717                         data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK;
3718                 /* update CGCG and CGLS override bits */
3719                 if (def != data)
3720                         WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
3721
3722                 /* enable cgcg FSM(0x0000363F) */
3723                 def = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL);
3724
3725                 data = (0x36 << RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT) |
3726                         RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK;
3727                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS)
3728                         data |= (0x000F << RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY__SHIFT) |
3729                                 RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK;
3730                 if (def != data)
3731                         WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, data);
3732
3733                 /* set IDLE_POLL_COUNT(0x00900100) */
3734                 def = RREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL);
3735                 data = (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) |
3736                         (0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT);
3737                 if (def != data)
3738                         WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL, data);
3739         } else {
3740                 def = data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL);
3741                 /* reset CGCG/CGLS bits */
3742                 data &= ~(RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK | RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK);
3743                 /* disable cgcg and cgls in FSM */
3744                 if (def != data)
3745                         WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, data);
3746         }
3747
3748         amdgpu_gfx_rlc_exit_safe_mode(adev);
3749 }
3750
3751 static int gfx_v9_0_update_gfx_clock_gating(struct amdgpu_device *adev,
3752                                             bool enable)
3753 {
3754         if (enable) {
3755                 /* CGCG/CGLS should be enabled after MGCG/MGLS
3756                  * ===  MGCG + MGLS ===
3757                  */
3758                 gfx_v9_0_update_medium_grain_clock_gating(adev, enable);
3759                 /* ===  CGCG /CGLS for GFX 3D Only === */
3760                 gfx_v9_0_update_3d_clock_gating(adev, enable);
3761                 /* ===  CGCG + CGLS === */
3762                 gfx_v9_0_update_coarse_grain_clock_gating(adev, enable);
3763         } else {
3764                 /* CGCG/CGLS should be disabled before MGCG/MGLS
3765                  * ===  CGCG + CGLS ===
3766                  */
3767                 gfx_v9_0_update_coarse_grain_clock_gating(adev, enable);
3768                 /* ===  CGCG /CGLS for GFX 3D Only === */
3769                 gfx_v9_0_update_3d_clock_gating(adev, enable);
3770                 /* ===  MGCG + MGLS === */
3771                 gfx_v9_0_update_medium_grain_clock_gating(adev, enable);
3772         }
3773         return 0;
3774 }
3775
3776 static const struct amdgpu_rlc_funcs gfx_v9_0_rlc_funcs = {
3777         .is_rlc_enabled = gfx_v9_0_is_rlc_enabled,
3778         .set_safe_mode = gfx_v9_0_set_safe_mode,
3779         .unset_safe_mode = gfx_v9_0_unset_safe_mode,
3780         .init = gfx_v9_0_rlc_init,
3781         .get_csb_size = gfx_v9_0_get_csb_size,
3782         .get_csb_buffer = gfx_v9_0_get_csb_buffer,
3783         .get_cp_table_num = gfx_v9_0_cp_jump_table_num,
3784         .resume = gfx_v9_0_rlc_resume,
3785         .stop = gfx_v9_0_rlc_stop,
3786         .reset = gfx_v9_0_rlc_reset,
3787         .start = gfx_v9_0_rlc_start
3788 };
3789
3790 static int gfx_v9_0_set_powergating_state(void *handle,
3791                                           enum amd_powergating_state state)
3792 {
3793         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3794         bool enable = (state == AMD_PG_STATE_GATE) ? true : false;
3795
3796         switch (adev->asic_type) {
3797         case CHIP_RAVEN:
3798                 if (!enable) {
3799                         amdgpu_gfx_off_ctrl(adev, false);
3800                         cancel_delayed_work_sync(&adev->gfx.gfx_off_delay_work);
3801                 }
3802                 if (adev->pg_flags & AMD_PG_SUPPORT_RLC_SMU_HS) {
3803                         gfx_v9_0_enable_sck_slow_down_on_power_up(adev, true);
3804                         gfx_v9_0_enable_sck_slow_down_on_power_down(adev, true);
3805                 } else {
3806                         gfx_v9_0_enable_sck_slow_down_on_power_up(adev, false);
3807                         gfx_v9_0_enable_sck_slow_down_on_power_down(adev, false);
3808                 }
3809
3810                 if (adev->pg_flags & AMD_PG_SUPPORT_CP)
3811                         gfx_v9_0_enable_cp_power_gating(adev, true);
3812                 else
3813                         gfx_v9_0_enable_cp_power_gating(adev, false);
3814
3815                 /* update gfx cgpg state */
3816                 gfx_v9_0_update_gfx_cg_power_gating(adev, enable);
3817
3818                 /* update mgcg state */
3819                 gfx_v9_0_update_gfx_mg_power_gating(adev, enable);
3820
3821                 if (enable)
3822                         amdgpu_gfx_off_ctrl(adev, true);
3823                 break;
3824         case CHIP_VEGA12:
3825                 if (!enable) {
3826                         amdgpu_gfx_off_ctrl(adev, false);
3827                         cancel_delayed_work_sync(&adev->gfx.gfx_off_delay_work);
3828                 } else {
3829                         amdgpu_gfx_off_ctrl(adev, true);
3830                 }
3831                 break;
3832         default:
3833                 break;
3834         }
3835
3836         return 0;
3837 }
3838
3839 static int gfx_v9_0_set_clockgating_state(void *handle,
3840                                           enum amd_clockgating_state state)
3841 {
3842         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3843
3844         if (amdgpu_sriov_vf(adev))
3845                 return 0;
3846
3847         switch (adev->asic_type) {
3848         case CHIP_VEGA10:
3849         case CHIP_VEGA12:
3850         case CHIP_VEGA20:
3851         case CHIP_RAVEN:
3852                 gfx_v9_0_update_gfx_clock_gating(adev,
3853                                                  state == AMD_CG_STATE_GATE ? true : false);
3854                 break;
3855         default:
3856                 break;
3857         }
3858         return 0;
3859 }
3860
3861 static void gfx_v9_0_get_clockgating_state(void *handle, u32 *flags)
3862 {
3863         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3864         int data;
3865
3866         if (amdgpu_sriov_vf(adev))
3867                 *flags = 0;
3868
3869         /* AMD_CG_SUPPORT_GFX_MGCG */
3870         data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
3871         if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK))
3872                 *flags |= AMD_CG_SUPPORT_GFX_MGCG;
3873
3874         /* AMD_CG_SUPPORT_GFX_CGCG */
3875         data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL);
3876         if (data & RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK)
3877                 *flags |= AMD_CG_SUPPORT_GFX_CGCG;
3878
3879         /* AMD_CG_SUPPORT_GFX_CGLS */
3880         if (data & RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK)
3881                 *flags |= AMD_CG_SUPPORT_GFX_CGLS;
3882
3883         /* AMD_CG_SUPPORT_GFX_RLC_LS */
3884         data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL);
3885         if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK)
3886                 *flags |= AMD_CG_SUPPORT_GFX_RLC_LS | AMD_CG_SUPPORT_GFX_MGLS;
3887
3888         /* AMD_CG_SUPPORT_GFX_CP_LS */
3889         data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL);
3890         if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK)
3891                 *flags |= AMD_CG_SUPPORT_GFX_CP_LS | AMD_CG_SUPPORT_GFX_MGLS;
3892
3893         /* AMD_CG_SUPPORT_GFX_3D_CGCG */
3894         data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D);
3895         if (data & RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK)
3896                 *flags |= AMD_CG_SUPPORT_GFX_3D_CGCG;
3897
3898         /* AMD_CG_SUPPORT_GFX_3D_CGLS */
3899         if (data & RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK)
3900                 *flags |= AMD_CG_SUPPORT_GFX_3D_CGLS;
3901 }
3902
3903 static u64 gfx_v9_0_ring_get_rptr_gfx(struct amdgpu_ring *ring)
3904 {
3905         return ring->adev->wb.wb[ring->rptr_offs]; /* gfx9 is 32bit rptr*/
3906 }
3907
3908 static u64 gfx_v9_0_ring_get_wptr_gfx(struct amdgpu_ring *ring)
3909 {
3910         struct amdgpu_device *adev = ring->adev;
3911         u64 wptr;
3912
3913         /* XXX check if swapping is necessary on BE */
3914         if (ring->use_doorbell) {
3915                 wptr = atomic64_read((atomic64_t *)&adev->wb.wb[ring->wptr_offs]);
3916         } else {
3917                 wptr = RREG32_SOC15(GC, 0, mmCP_RB0_WPTR);
3918                 wptr += (u64)RREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI) << 32;
3919         }
3920
3921         return wptr;
3922 }
3923
3924 static void gfx_v9_0_ring_set_wptr_gfx(struct amdgpu_ring *ring)
3925 {
3926         struct amdgpu_device *adev = ring->adev;
3927
3928         if (ring->use_doorbell) {
3929                 /* XXX check if swapping is necessary on BE */
3930                 atomic64_set((atomic64_t*)&adev->wb.wb[ring->wptr_offs], ring->wptr);
3931                 WDOORBELL64(ring->doorbell_index, ring->wptr);
3932         } else {
3933                 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR, lower_32_bits(ring->wptr));
3934                 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI, upper_32_bits(ring->wptr));
3935         }
3936 }
3937
3938 static void gfx_v9_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
3939 {
3940         struct amdgpu_device *adev = ring->adev;
3941         u32 ref_and_mask, reg_mem_engine;
3942         const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio_funcs->hdp_flush_reg;
3943
3944         if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) {
3945                 switch (ring->me) {
3946                 case 1:
3947                         ref_and_mask = nbio_hf_reg->ref_and_mask_cp2 << ring->pipe;
3948                         break;
3949                 case 2:
3950                         ref_and_mask = nbio_hf_reg->ref_and_mask_cp6 << ring->pipe;
3951                         break;
3952                 default:
3953                         return;
3954                 }
3955                 reg_mem_engine = 0;
3956         } else {
3957                 ref_and_mask = nbio_hf_reg->ref_and_mask_cp0;
3958                 reg_mem_engine = 1; /* pfp */
3959         }
3960
3961         gfx_v9_0_wait_reg_mem(ring, reg_mem_engine, 0, 1,
3962                               adev->nbio_funcs->get_hdp_flush_req_offset(adev),
3963                               adev->nbio_funcs->get_hdp_flush_done_offset(adev),
3964                               ref_and_mask, ref_and_mask, 0x20);
3965 }
3966
3967 static void gfx_v9_0_ring_emit_ib_gfx(struct amdgpu_ring *ring,
3968                                         struct amdgpu_job *job,
3969                                         struct amdgpu_ib *ib,
3970                                         bool ctx_switch)
3971 {
3972         unsigned vmid = AMDGPU_JOB_GET_VMID(job);
3973         u32 header, control = 0;
3974
3975         if (ib->flags & AMDGPU_IB_FLAG_CE)
3976                 header = PACKET3(PACKET3_INDIRECT_BUFFER_CONST, 2);
3977         else
3978                 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2);
3979
3980         control |= ib->length_dw | (vmid << 24);
3981
3982         if (amdgpu_sriov_vf(ring->adev) && (ib->flags & AMDGPU_IB_FLAG_PREEMPT)) {
3983                 control |= INDIRECT_BUFFER_PRE_ENB(1);
3984
3985                 if (!(ib->flags & AMDGPU_IB_FLAG_CE))
3986                         gfx_v9_0_ring_emit_de_meta(ring);
3987         }
3988
3989         amdgpu_ring_write(ring, header);
3990         BUG_ON(ib->gpu_addr & 0x3); /* Dword align */
3991         amdgpu_ring_write(ring,
3992 #ifdef __BIG_ENDIAN
3993                 (2 << 0) |
3994 #endif
3995                 lower_32_bits(ib->gpu_addr));
3996         amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
3997         amdgpu_ring_write(ring, control);
3998 }
3999
4000 static void gfx_v9_0_ring_emit_ib_compute(struct amdgpu_ring *ring,
4001                                           struct amdgpu_job *job,
4002                                           struct amdgpu_ib *ib,
4003                                           bool ctx_switch)
4004 {
4005         unsigned vmid = AMDGPU_JOB_GET_VMID(job);
4006         u32 control = INDIRECT_BUFFER_VALID | ib->length_dw | (vmid << 24);
4007
4008         amdgpu_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
4009         BUG_ON(ib->gpu_addr & 0x3); /* Dword align */
4010         amdgpu_ring_write(ring,
4011 #ifdef __BIG_ENDIAN
4012                                 (2 << 0) |
4013 #endif
4014                                 lower_32_bits(ib->gpu_addr));
4015         amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
4016         amdgpu_ring_write(ring, control);
4017 }
4018
4019 static void gfx_v9_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr,
4020                                      u64 seq, unsigned flags)
4021 {
4022         bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
4023         bool int_sel = flags & AMDGPU_FENCE_FLAG_INT;
4024         bool writeback = flags & AMDGPU_FENCE_FLAG_TC_WB_ONLY;
4025
4026         /* RELEASE_MEM - flush caches, send int */
4027         amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 6));
4028         amdgpu_ring_write(ring, ((writeback ? (EOP_TC_WB_ACTION_EN |
4029                                                EOP_TC_NC_ACTION_EN) :
4030                                               (EOP_TCL1_ACTION_EN |
4031                                                EOP_TC_ACTION_EN |
4032                                                EOP_TC_WB_ACTION_EN |
4033                                                EOP_TC_MD_ACTION_EN)) |
4034                                  EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) |
4035                                  EVENT_INDEX(5)));
4036         amdgpu_ring_write(ring, DATA_SEL(write64bit ? 2 : 1) | INT_SEL(int_sel ? 2 : 0));
4037
4038         /*
4039          * the address should be Qword aligned if 64bit write, Dword
4040          * aligned if only send 32bit data low (discard data high)
4041          */
4042         if (write64bit)
4043                 BUG_ON(addr & 0x7);
4044         else
4045                 BUG_ON(addr & 0x3);
4046         amdgpu_ring_write(ring, lower_32_bits(addr));
4047         amdgpu_ring_write(ring, upper_32_bits(addr));
4048         amdgpu_ring_write(ring, lower_32_bits(seq));
4049         amdgpu_ring_write(ring, upper_32_bits(seq));
4050         amdgpu_ring_write(ring, 0);
4051 }
4052
4053 static void gfx_v9_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
4054 {
4055         int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
4056         uint32_t seq = ring->fence_drv.sync_seq;
4057         uint64_t addr = ring->fence_drv.gpu_addr;
4058
4059         gfx_v9_0_wait_reg_mem(ring, usepfp, 1, 0,
4060                               lower_32_bits(addr), upper_32_bits(addr),
4061                               seq, 0xffffffff, 4);
4062 }
4063
4064 static void gfx_v9_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
4065                                         unsigned vmid, uint64_t pd_addr)
4066 {
4067         amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
4068
4069         /* compute doesn't have PFP */
4070         if (ring->funcs->type == AMDGPU_RING_TYPE_GFX) {
4071                 /* sync PFP to ME, otherwise we might get invalid PFP reads */
4072                 amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0));
4073                 amdgpu_ring_write(ring, 0x0);
4074         }
4075 }
4076
4077 static u64 gfx_v9_0_ring_get_rptr_compute(struct amdgpu_ring *ring)
4078 {
4079         return ring->adev->wb.wb[ring->rptr_offs]; /* gfx9 hardware is 32bit rptr */
4080 }
4081
4082 static u64 gfx_v9_0_ring_get_wptr_compute(struct amdgpu_ring *ring)
4083 {
4084         u64 wptr;
4085
4086         /* XXX check if swapping is necessary on BE */
4087         if (ring->use_doorbell)
4088                 wptr = atomic64_read((atomic64_t *)&ring->adev->wb.wb[ring->wptr_offs]);
4089         else
4090                 BUG();
4091         return wptr;
4092 }
4093
4094 static void gfx_v9_0_ring_set_pipe_percent(struct amdgpu_ring *ring,
4095                                            bool acquire)
4096 {
4097         struct amdgpu_device *adev = ring->adev;
4098         int pipe_num, tmp, reg;
4099         int pipe_percent = acquire ? SPI_WCL_PIPE_PERCENT_GFX__VALUE_MASK : 0x1;
4100
4101         pipe_num = ring->me * adev->gfx.mec.num_pipe_per_mec + ring->pipe;
4102
4103         /* first me only has 2 entries, GFX and HP3D */
4104         if (ring->me > 0)
4105                 pipe_num -= 2;
4106
4107         reg = SOC15_REG_OFFSET(GC, 0, mmSPI_WCL_PIPE_PERCENT_GFX) + pipe_num;
4108         tmp = RREG32(reg);
4109         tmp = REG_SET_FIELD(tmp, SPI_WCL_PIPE_PERCENT_GFX, VALUE, pipe_percent);
4110         WREG32(reg, tmp);
4111 }
4112
4113 static void gfx_v9_0_pipe_reserve_resources(struct amdgpu_device *adev,
4114                                             struct amdgpu_ring *ring,
4115                                             bool acquire)
4116 {
4117         int i, pipe;
4118         bool reserve;
4119         struct amdgpu_ring *iring;
4120
4121         mutex_lock(&adev->gfx.pipe_reserve_mutex);
4122         pipe = amdgpu_gfx_queue_to_bit(adev, ring->me, ring->pipe, 0);
4123         if (acquire)
4124                 set_bit(pipe, adev->gfx.pipe_reserve_bitmap);
4125         else
4126                 clear_bit(pipe, adev->gfx.pipe_reserve_bitmap);
4127
4128         if (!bitmap_weight(adev->gfx.pipe_reserve_bitmap, AMDGPU_MAX_COMPUTE_QUEUES)) {
4129                 /* Clear all reservations - everyone reacquires all resources */
4130                 for (i = 0; i < adev->gfx.num_gfx_rings; ++i)
4131                         gfx_v9_0_ring_set_pipe_percent(&adev->gfx.gfx_ring[i],
4132                                                        true);
4133
4134                 for (i = 0; i < adev->gfx.num_compute_rings; ++i)
4135                         gfx_v9_0_ring_set_pipe_percent(&adev->gfx.compute_ring[i],
4136                                                        true);
4137         } else {
4138                 /* Lower all pipes without a current reservation */
4139                 for (i = 0; i < adev->gfx.num_gfx_rings; ++i) {
4140                         iring = &adev->gfx.gfx_ring[i];
4141                         pipe = amdgpu_gfx_queue_to_bit(adev,
4142                                                        iring->me,
4143                                                        iring->pipe,
4144                                                        0);
4145                         reserve = test_bit(pipe, adev->gfx.pipe_reserve_bitmap);
4146                         gfx_v9_0_ring_set_pipe_percent(iring, reserve);
4147                 }
4148
4149                 for (i = 0; i < adev->gfx.num_compute_rings; ++i) {
4150                         iring = &adev->gfx.compute_ring[i];
4151                         pipe = amdgpu_gfx_queue_to_bit(adev,
4152                                                        iring->me,
4153                                                        iring->pipe,
4154                                                        0);
4155                         reserve = test_bit(pipe, adev->gfx.pipe_reserve_bitmap);
4156                         gfx_v9_0_ring_set_pipe_percent(iring, reserve);
4157                 }
4158         }
4159
4160         mutex_unlock(&adev->gfx.pipe_reserve_mutex);
4161 }
4162
4163 static void gfx_v9_0_hqd_set_priority(struct amdgpu_device *adev,
4164                                       struct amdgpu_ring *ring,
4165                                       bool acquire)
4166 {
4167         uint32_t pipe_priority = acquire ? 0x2 : 0x0;
4168         uint32_t queue_priority = acquire ? 0xf : 0x0;
4169
4170         mutex_lock(&adev->srbm_mutex);
4171         soc15_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
4172
4173         WREG32_SOC15(GC, 0, mmCP_HQD_PIPE_PRIORITY, pipe_priority);
4174         WREG32_SOC15(GC, 0, mmCP_HQD_QUEUE_PRIORITY, queue_priority);
4175
4176         soc15_grbm_select(adev, 0, 0, 0, 0);
4177         mutex_unlock(&adev->srbm_mutex);
4178 }
4179
4180 static void gfx_v9_0_ring_set_priority_compute(struct amdgpu_ring *ring,
4181                                                enum drm_sched_priority priority)
4182 {
4183         struct amdgpu_device *adev = ring->adev;
4184         bool acquire = priority == DRM_SCHED_PRIORITY_HIGH_HW;
4185
4186         if (ring->funcs->type != AMDGPU_RING_TYPE_COMPUTE)
4187                 return;
4188
4189         gfx_v9_0_hqd_set_priority(adev, ring, acquire);
4190         gfx_v9_0_pipe_reserve_resources(adev, ring, acquire);
4191 }
4192
4193 static void gfx_v9_0_ring_set_wptr_compute(struct amdgpu_ring *ring)
4194 {
4195         struct amdgpu_device *adev = ring->adev;
4196
4197         /* XXX check if swapping is necessary on BE */
4198         if (ring->use_doorbell) {
4199                 atomic64_set((atomic64_t*)&adev->wb.wb[ring->wptr_offs], ring->wptr);
4200                 WDOORBELL64(ring->doorbell_index, ring->wptr);
4201         } else{
4202                 BUG(); /* only DOORBELL method supported on gfx9 now */
4203         }
4204 }
4205
4206 static void gfx_v9_0_ring_emit_fence_kiq(struct amdgpu_ring *ring, u64 addr,
4207                                          u64 seq, unsigned int flags)
4208 {
4209         struct amdgpu_device *adev = ring->adev;
4210
4211         /* we only allocate 32bit for each seq wb address */
4212         BUG_ON(flags & AMDGPU_FENCE_FLAG_64BIT);
4213
4214         /* write fence seq to the "addr" */
4215         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
4216         amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
4217                                  WRITE_DATA_DST_SEL(5) | WR_CONFIRM));
4218         amdgpu_ring_write(ring, lower_32_bits(addr));
4219         amdgpu_ring_write(ring, upper_32_bits(addr));
4220         amdgpu_ring_write(ring, lower_32_bits(seq));
4221
4222         if (flags & AMDGPU_FENCE_FLAG_INT) {
4223                 /* set register to trigger INT */
4224                 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
4225                 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
4226                                          WRITE_DATA_DST_SEL(0) | WR_CONFIRM));
4227                 amdgpu_ring_write(ring, SOC15_REG_OFFSET(GC, 0, mmCPC_INT_STATUS));
4228                 amdgpu_ring_write(ring, 0);
4229                 amdgpu_ring_write(ring, 0x20000000); /* src_id is 178 */
4230         }
4231 }
4232
4233 static void gfx_v9_ring_emit_sb(struct amdgpu_ring *ring)
4234 {
4235         amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
4236         amdgpu_ring_write(ring, 0);
4237 }
4238
4239 static void gfx_v9_0_ring_emit_ce_meta(struct amdgpu_ring *ring)
4240 {
4241         struct v9_ce_ib_state ce_payload = {0};
4242         uint64_t csa_addr;
4243         int cnt;
4244
4245         cnt = (sizeof(ce_payload) >> 2) + 4 - 2;
4246         csa_addr = amdgpu_csa_vaddr(ring->adev);
4247
4248         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt));
4249         amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(2) |
4250                                  WRITE_DATA_DST_SEL(8) |
4251                                  WR_CONFIRM) |
4252                                  WRITE_DATA_CACHE_POLICY(0));
4253         amdgpu_ring_write(ring, lower_32_bits(csa_addr + offsetof(struct v9_gfx_meta_data, ce_payload)));
4254         amdgpu_ring_write(ring, upper_32_bits(csa_addr + offsetof(struct v9_gfx_meta_data, ce_payload)));
4255         amdgpu_ring_write_multiple(ring, (void *)&ce_payload, sizeof(ce_payload) >> 2);
4256 }
4257
4258 static void gfx_v9_0_ring_emit_de_meta(struct amdgpu_ring *ring)
4259 {
4260         struct v9_de_ib_state de_payload = {0};
4261         uint64_t csa_addr, gds_addr;
4262         int cnt;
4263
4264         csa_addr = amdgpu_csa_vaddr(ring->adev);
4265         gds_addr = csa_addr + 4096;
4266         de_payload.gds_backup_addrlo = lower_32_bits(gds_addr);
4267         de_payload.gds_backup_addrhi = upper_32_bits(gds_addr);
4268
4269         cnt = (sizeof(de_payload) >> 2) + 4 - 2;
4270         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt));
4271         amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(1) |
4272                                  WRITE_DATA_DST_SEL(8) |
4273                                  WR_CONFIRM) |
4274                                  WRITE_DATA_CACHE_POLICY(0));
4275         amdgpu_ring_write(ring, lower_32_bits(csa_addr + offsetof(struct v9_gfx_meta_data, de_payload)));
4276         amdgpu_ring_write(ring, upper_32_bits(csa_addr + offsetof(struct v9_gfx_meta_data, de_payload)));
4277         amdgpu_ring_write_multiple(ring, (void *)&de_payload, sizeof(de_payload) >> 2);
4278 }
4279
4280 static void gfx_v9_0_ring_emit_tmz(struct amdgpu_ring *ring, bool start)
4281 {
4282         amdgpu_ring_write(ring, PACKET3(PACKET3_FRAME_CONTROL, 0));
4283         amdgpu_ring_write(ring, FRAME_CMD(start ? 0 : 1)); /* frame_end */
4284 }
4285
4286 static void gfx_v9_ring_emit_cntxcntl(struct amdgpu_ring *ring, uint32_t flags)
4287 {
4288         uint32_t dw2 = 0;
4289
4290         if (amdgpu_sriov_vf(ring->adev))
4291                 gfx_v9_0_ring_emit_ce_meta(ring);
4292
4293         gfx_v9_0_ring_emit_tmz(ring, true);
4294
4295         dw2 |= 0x80000000; /* set load_enable otherwise this package is just NOPs */
4296         if (flags & AMDGPU_HAVE_CTX_SWITCH) {
4297                 /* set load_global_config & load_global_uconfig */
4298                 dw2 |= 0x8001;
4299                 /* set load_cs_sh_regs */
4300                 dw2 |= 0x01000000;
4301                 /* set load_per_context_state & load_gfx_sh_regs for GFX */
4302                 dw2 |= 0x10002;
4303
4304                 /* set load_ce_ram if preamble presented */
4305                 if (AMDGPU_PREAMBLE_IB_PRESENT & flags)
4306                         dw2 |= 0x10000000;
4307         } else {
4308                 /* still load_ce_ram if this is the first time preamble presented
4309                  * although there is no context switch happens.
4310                  */
4311                 if (AMDGPU_PREAMBLE_IB_PRESENT_FIRST & flags)
4312                         dw2 |= 0x10000000;
4313         }
4314
4315         amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1));
4316         amdgpu_ring_write(ring, dw2);
4317         amdgpu_ring_write(ring, 0);
4318 }
4319
4320 static unsigned gfx_v9_0_ring_emit_init_cond_exec(struct amdgpu_ring *ring)
4321 {
4322         unsigned ret;
4323         amdgpu_ring_write(ring, PACKET3(PACKET3_COND_EXEC, 3));
4324         amdgpu_ring_write(ring, lower_32_bits(ring->cond_exe_gpu_addr));
4325         amdgpu_ring_write(ring, upper_32_bits(ring->cond_exe_gpu_addr));
4326         amdgpu_ring_write(ring, 0); /* discard following DWs if *cond_exec_gpu_addr==0 */
4327         ret = ring->wptr & ring->buf_mask;
4328         amdgpu_ring_write(ring, 0x55aa55aa); /* patch dummy value later */
4329         return ret;
4330 }
4331
4332 static void gfx_v9_0_ring_emit_patch_cond_exec(struct amdgpu_ring *ring, unsigned offset)
4333 {
4334         unsigned cur;
4335         BUG_ON(offset > ring->buf_mask);
4336         BUG_ON(ring->ring[offset] != 0x55aa55aa);
4337
4338         cur = (ring->wptr & ring->buf_mask) - 1;
4339         if (likely(cur > offset))
4340                 ring->ring[offset] = cur - offset;
4341         else
4342                 ring->ring[offset] = (ring->ring_size>>2) - offset + cur;
4343 }
4344
4345 static void gfx_v9_0_ring_emit_rreg(struct amdgpu_ring *ring, uint32_t reg)
4346 {
4347         struct amdgpu_device *adev = ring->adev;
4348
4349         amdgpu_ring_write(ring, PACKET3(PACKET3_COPY_DATA, 4));
4350         amdgpu_ring_write(ring, 0 |     /* src: register*/
4351                                 (5 << 8) |      /* dst: memory */
4352                                 (1 << 20));     /* write confirm */
4353         amdgpu_ring_write(ring, reg);
4354         amdgpu_ring_write(ring, 0);
4355         amdgpu_ring_write(ring, lower_32_bits(adev->wb.gpu_addr +
4356                                 adev->virt.reg_val_offs * 4));
4357         amdgpu_ring_write(ring, upper_32_bits(adev->wb.gpu_addr +
4358                                 adev->virt.reg_val_offs * 4));
4359 }
4360
4361 static void gfx_v9_0_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg,
4362                                     uint32_t val)
4363 {
4364         uint32_t cmd = 0;
4365
4366         switch (ring->funcs->type) {
4367         case AMDGPU_RING_TYPE_GFX:
4368                 cmd = WRITE_DATA_ENGINE_SEL(1) | WR_CONFIRM;
4369                 break;
4370         case AMDGPU_RING_TYPE_KIQ:
4371                 cmd = (1 << 16); /* no inc addr */
4372                 break;
4373         default:
4374                 cmd = WR_CONFIRM;
4375                 break;
4376         }
4377         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
4378         amdgpu_ring_write(ring, cmd);
4379         amdgpu_ring_write(ring, reg);
4380         amdgpu_ring_write(ring, 0);
4381         amdgpu_ring_write(ring, val);
4382 }
4383
4384 static void gfx_v9_0_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,
4385                                         uint32_t val, uint32_t mask)
4386 {
4387         gfx_v9_0_wait_reg_mem(ring, 0, 0, 0, reg, 0, val, mask, 0x20);
4388 }
4389
4390 static void gfx_v9_0_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring,
4391                                                   uint32_t reg0, uint32_t reg1,
4392                                                   uint32_t ref, uint32_t mask)
4393 {
4394         int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
4395         struct amdgpu_device *adev = ring->adev;
4396         bool fw_version_ok = (ring->funcs->type == AMDGPU_RING_TYPE_GFX) ?
4397                 adev->gfx.me_fw_write_wait : adev->gfx.mec_fw_write_wait;
4398
4399         if (fw_version_ok)
4400                 gfx_v9_0_wait_reg_mem(ring, usepfp, 0, 1, reg0, reg1,
4401                                       ref, mask, 0x20);
4402         else
4403                 amdgpu_ring_emit_reg_write_reg_wait_helper(ring, reg0, reg1,
4404                                                            ref, mask);
4405 }
4406
4407 static void gfx_v9_0_ring_soft_recovery(struct amdgpu_ring *ring, unsigned vmid)
4408 {
4409         struct amdgpu_device *adev = ring->adev;
4410         uint32_t value = 0;
4411
4412         value = REG_SET_FIELD(value, SQ_CMD, CMD, 0x03);
4413         value = REG_SET_FIELD(value, SQ_CMD, MODE, 0x01);
4414         value = REG_SET_FIELD(value, SQ_CMD, CHECK_VMID, 1);
4415         value = REG_SET_FIELD(value, SQ_CMD, VM_ID, vmid);
4416         WREG32(mmSQ_CMD, value);
4417 }
4418
4419 static void gfx_v9_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev,
4420                                                  enum amdgpu_interrupt_state state)
4421 {
4422         switch (state) {
4423         case AMDGPU_IRQ_STATE_DISABLE:
4424         case AMDGPU_IRQ_STATE_ENABLE:
4425                 WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0,
4426                                TIME_STAMP_INT_ENABLE,
4427                                state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
4428                 break;
4429         default:
4430                 break;
4431         }
4432 }
4433
4434 static void gfx_v9_0_set_compute_eop_interrupt_state(struct amdgpu_device *adev,
4435                                                      int me, int pipe,
4436                                                      enum amdgpu_interrupt_state state)
4437 {
4438         u32 mec_int_cntl, mec_int_cntl_reg;
4439
4440         /*
4441          * amdgpu controls only the first MEC. That's why this function only
4442          * handles the setting of interrupts for this specific MEC. All other
4443          * pipes' interrupts are set by amdkfd.
4444          */
4445
4446         if (me == 1) {
4447                 switch (pipe) {
4448                 case 0:
4449                         mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE0_INT_CNTL);
4450                         break;
4451                 case 1:
4452                         mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE1_INT_CNTL);
4453                         break;
4454                 case 2:
4455                         mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE2_INT_CNTL);
4456                         break;
4457                 case 3:
4458                         mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE3_INT_CNTL);
4459                         break;
4460                 default:
4461                         DRM_DEBUG("invalid pipe %d\n", pipe);
4462                         return;
4463                 }
4464         } else {
4465                 DRM_DEBUG("invalid me %d\n", me);
4466                 return;
4467         }
4468
4469         switch (state) {
4470         case AMDGPU_IRQ_STATE_DISABLE:
4471                 mec_int_cntl = RREG32(mec_int_cntl_reg);
4472                 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,
4473                                              TIME_STAMP_INT_ENABLE, 0);
4474                 WREG32(mec_int_cntl_reg, mec_int_cntl);
4475                 break;
4476         case AMDGPU_IRQ_STATE_ENABLE:
4477                 mec_int_cntl = RREG32(mec_int_cntl_reg);
4478                 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,
4479                                              TIME_STAMP_INT_ENABLE, 1);
4480                 WREG32(mec_int_cntl_reg, mec_int_cntl);
4481                 break;
4482         default:
4483                 break;
4484         }
4485 }
4486
4487 static int gfx_v9_0_set_priv_reg_fault_state(struct amdgpu_device *adev,
4488                                              struct amdgpu_irq_src *source,
4489                                              unsigned type,
4490                                              enum amdgpu_interrupt_state state)
4491 {
4492         switch (state) {
4493         case AMDGPU_IRQ_STATE_DISABLE:
4494         case AMDGPU_IRQ_STATE_ENABLE:
4495                 WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0,
4496                                PRIV_REG_INT_ENABLE,
4497                                state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
4498                 break;
4499         default:
4500                 break;
4501         }
4502
4503         return 0;
4504 }
4505
4506 static int gfx_v9_0_set_priv_inst_fault_state(struct amdgpu_device *adev,
4507                                               struct amdgpu_irq_src *source,
4508                                               unsigned type,
4509                                               enum amdgpu_interrupt_state state)
4510 {
4511         switch (state) {
4512         case AMDGPU_IRQ_STATE_DISABLE:
4513         case AMDGPU_IRQ_STATE_ENABLE:
4514                 WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0,
4515                                PRIV_INSTR_INT_ENABLE,
4516                                state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
4517         default:
4518                 break;
4519         }
4520
4521         return 0;
4522 }
4523
4524 static int gfx_v9_0_set_eop_interrupt_state(struct amdgpu_device *adev,
4525                                             struct amdgpu_irq_src *src,
4526                                             unsigned type,
4527                                             enum amdgpu_interrupt_state state)
4528 {
4529         switch (type) {
4530         case AMDGPU_CP_IRQ_GFX_EOP:
4531                 gfx_v9_0_set_gfx_eop_interrupt_state(adev, state);
4532                 break;
4533         case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP:
4534                 gfx_v9_0_set_compute_eop_interrupt_state(adev, 1, 0, state);
4535                 break;
4536         case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP:
4537                 gfx_v9_0_set_compute_eop_interrupt_state(adev, 1, 1, state);
4538                 break;
4539         case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP:
4540                 gfx_v9_0_set_compute_eop_interrupt_state(adev, 1, 2, state);
4541                 break;
4542         case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP:
4543                 gfx_v9_0_set_compute_eop_interrupt_state(adev, 1, 3, state);
4544                 break;
4545         case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP:
4546                 gfx_v9_0_set_compute_eop_interrupt_state(adev, 2, 0, state);
4547                 break;
4548         case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP:
4549                 gfx_v9_0_set_compute_eop_interrupt_state(adev, 2, 1, state);
4550                 break;
4551         case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP:
4552                 gfx_v9_0_set_compute_eop_interrupt_state(adev, 2, 2, state);
4553                 break;
4554         case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP:
4555                 gfx_v9_0_set_compute_eop_interrupt_state(adev, 2, 3, state);
4556                 break;
4557         default:
4558                 break;
4559         }
4560         return 0;
4561 }
4562
4563 static int gfx_v9_0_eop_irq(struct amdgpu_device *adev,
4564                             struct amdgpu_irq_src *source,
4565                             struct amdgpu_iv_entry *entry)
4566 {
4567         int i;
4568         u8 me_id, pipe_id, queue_id;
4569         struct amdgpu_ring *ring;
4570
4571         DRM_DEBUG("IH: CP EOP\n");
4572         me_id = (entry->ring_id & 0x0c) >> 2;
4573         pipe_id = (entry->ring_id & 0x03) >> 0;
4574         queue_id = (entry->ring_id & 0x70) >> 4;
4575
4576         switch (me_id) {
4577         case 0:
4578                 amdgpu_fence_process(&adev->gfx.gfx_ring[0]);
4579                 break;
4580         case 1:
4581         case 2:
4582                 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
4583                         ring = &adev->gfx.compute_ring[i];
4584                         /* Per-queue interrupt is supported for MEC starting from VI.
4585                           * The interrupt can only be enabled/disabled per pipe instead of per queue.
4586                           */
4587                         if ((ring->me == me_id) && (ring->pipe == pipe_id) && (ring->queue == queue_id))
4588                                 amdgpu_fence_process(ring);
4589                 }
4590                 break;
4591         }
4592         return 0;
4593 }
4594
4595 static void gfx_v9_0_fault(struct amdgpu_device *adev,
4596                            struct amdgpu_iv_entry *entry)
4597 {
4598         u8 me_id, pipe_id, queue_id;
4599         struct amdgpu_ring *ring;
4600         int i;
4601
4602         me_id = (entry->ring_id & 0x0c) >> 2;
4603         pipe_id = (entry->ring_id & 0x03) >> 0;
4604         queue_id = (entry->ring_id & 0x70) >> 4;
4605
4606         switch (me_id) {
4607         case 0:
4608                 drm_sched_fault(&adev->gfx.gfx_ring[0].sched);
4609                 break;
4610         case 1:
4611         case 2:
4612                 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
4613                         ring = &adev->gfx.compute_ring[i];
4614                         if (ring->me == me_id && ring->pipe == pipe_id &&
4615                             ring->queue == queue_id)
4616                                 drm_sched_fault(&ring->sched);
4617                 }
4618                 break;
4619         }
4620 }
4621
4622 static int gfx_v9_0_priv_reg_irq(struct amdgpu_device *adev,
4623                                  struct amdgpu_irq_src *source,
4624                                  struct amdgpu_iv_entry *entry)
4625 {
4626         DRM_ERROR("Illegal register access in command stream\n");
4627         gfx_v9_0_fault(adev, entry);
4628         return 0;
4629 }
4630
4631 static int gfx_v9_0_priv_inst_irq(struct amdgpu_device *adev,
4632                                   struct amdgpu_irq_src *source,
4633                                   struct amdgpu_iv_entry *entry)
4634 {
4635         DRM_ERROR("Illegal instruction in command stream\n");
4636         gfx_v9_0_fault(adev, entry);
4637         return 0;
4638 }
4639
4640 static const struct amd_ip_funcs gfx_v9_0_ip_funcs = {
4641         .name = "gfx_v9_0",
4642         .early_init = gfx_v9_0_early_init,
4643         .late_init = gfx_v9_0_late_init,
4644         .sw_init = gfx_v9_0_sw_init,
4645         .sw_fini = gfx_v9_0_sw_fini,
4646         .hw_init = gfx_v9_0_hw_init,
4647         .hw_fini = gfx_v9_0_hw_fini,
4648         .suspend = gfx_v9_0_suspend,
4649         .resume = gfx_v9_0_resume,
4650         .is_idle = gfx_v9_0_is_idle,
4651         .wait_for_idle = gfx_v9_0_wait_for_idle,
4652         .soft_reset = gfx_v9_0_soft_reset,
4653         .set_clockgating_state = gfx_v9_0_set_clockgating_state,
4654         .set_powergating_state = gfx_v9_0_set_powergating_state,
4655         .get_clockgating_state = gfx_v9_0_get_clockgating_state,
4656 };
4657
4658 static const struct amdgpu_ring_funcs gfx_v9_0_ring_funcs_gfx = {
4659         .type = AMDGPU_RING_TYPE_GFX,
4660         .align_mask = 0xff,
4661         .nop = PACKET3(PACKET3_NOP, 0x3FFF),
4662         .support_64bit_ptrs = true,
4663         .vmhub = AMDGPU_GFXHUB,
4664         .get_rptr = gfx_v9_0_ring_get_rptr_gfx,
4665         .get_wptr = gfx_v9_0_ring_get_wptr_gfx,
4666         .set_wptr = gfx_v9_0_ring_set_wptr_gfx,
4667         .emit_frame_size = /* totally 242 maximum if 16 IBs */
4668                 5 +  /* COND_EXEC */
4669                 7 +  /* PIPELINE_SYNC */
4670                 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 +
4671                 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 +
4672                 2 + /* VM_FLUSH */
4673                 8 +  /* FENCE for VM_FLUSH */
4674                 20 + /* GDS switch */
4675                 4 + /* double SWITCH_BUFFER,
4676                        the first COND_EXEC jump to the place just
4677                            prior to this double SWITCH_BUFFER  */
4678                 5 + /* COND_EXEC */
4679                 7 +      /*     HDP_flush */
4680                 4 +      /*     VGT_flush */
4681                 14 + /* CE_META */
4682                 31 + /* DE_META */
4683                 3 + /* CNTX_CTRL */
4684                 5 + /* HDP_INVL */
4685                 8 + 8 + /* FENCE x2 */
4686                 2, /* SWITCH_BUFFER */
4687         .emit_ib_size = 4, /* gfx_v9_0_ring_emit_ib_gfx */
4688         .emit_ib = gfx_v9_0_ring_emit_ib_gfx,
4689         .emit_fence = gfx_v9_0_ring_emit_fence,
4690         .emit_pipeline_sync = gfx_v9_0_ring_emit_pipeline_sync,
4691         .emit_vm_flush = gfx_v9_0_ring_emit_vm_flush,
4692         .emit_gds_switch = gfx_v9_0_ring_emit_gds_switch,
4693         .emit_hdp_flush = gfx_v9_0_ring_emit_hdp_flush,
4694         .test_ring = gfx_v9_0_ring_test_ring,
4695         .test_ib = gfx_v9_0_ring_test_ib,
4696         .insert_nop = amdgpu_ring_insert_nop,
4697         .pad_ib = amdgpu_ring_generic_pad_ib,
4698         .emit_switch_buffer = gfx_v9_ring_emit_sb,
4699         .emit_cntxcntl = gfx_v9_ring_emit_cntxcntl,
4700         .init_cond_exec = gfx_v9_0_ring_emit_init_cond_exec,
4701         .patch_cond_exec = gfx_v9_0_ring_emit_patch_cond_exec,
4702         .emit_tmz = gfx_v9_0_ring_emit_tmz,
4703         .emit_wreg = gfx_v9_0_ring_emit_wreg,
4704         .emit_reg_wait = gfx_v9_0_ring_emit_reg_wait,
4705         .emit_reg_write_reg_wait = gfx_v9_0_ring_emit_reg_write_reg_wait,
4706         .soft_recovery = gfx_v9_0_ring_soft_recovery,
4707 };
4708
4709 static const struct amdgpu_ring_funcs gfx_v9_0_ring_funcs_compute = {
4710         .type = AMDGPU_RING_TYPE_COMPUTE,
4711         .align_mask = 0xff,
4712         .nop = PACKET3(PACKET3_NOP, 0x3FFF),
4713         .support_64bit_ptrs = true,
4714         .vmhub = AMDGPU_GFXHUB,
4715         .get_rptr = gfx_v9_0_ring_get_rptr_compute,
4716         .get_wptr = gfx_v9_0_ring_get_wptr_compute,
4717         .set_wptr = gfx_v9_0_ring_set_wptr_compute,
4718         .emit_frame_size =
4719                 20 + /* gfx_v9_0_ring_emit_gds_switch */
4720                 7 + /* gfx_v9_0_ring_emit_hdp_flush */
4721                 5 + /* hdp invalidate */
4722                 7 + /* gfx_v9_0_ring_emit_pipeline_sync */
4723                 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 +
4724                 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 +
4725                 2 + /* gfx_v9_0_ring_emit_vm_flush */
4726                 8 + 8 + 8, /* gfx_v9_0_ring_emit_fence x3 for user fence, vm fence */
4727         .emit_ib_size = 4, /* gfx_v9_0_ring_emit_ib_compute */
4728         .emit_ib = gfx_v9_0_ring_emit_ib_compute,
4729         .emit_fence = gfx_v9_0_ring_emit_fence,
4730         .emit_pipeline_sync = gfx_v9_0_ring_emit_pipeline_sync,
4731         .emit_vm_flush = gfx_v9_0_ring_emit_vm_flush,
4732         .emit_gds_switch = gfx_v9_0_ring_emit_gds_switch,
4733         .emit_hdp_flush = gfx_v9_0_ring_emit_hdp_flush,
4734         .test_ring = gfx_v9_0_ring_test_ring,
4735         .test_ib = gfx_v9_0_ring_test_ib,
4736         .insert_nop = amdgpu_ring_insert_nop,
4737         .pad_ib = amdgpu_ring_generic_pad_ib,
4738         .set_priority = gfx_v9_0_ring_set_priority_compute,
4739         .emit_wreg = gfx_v9_0_ring_emit_wreg,
4740         .emit_reg_wait = gfx_v9_0_ring_emit_reg_wait,
4741         .emit_reg_write_reg_wait = gfx_v9_0_ring_emit_reg_write_reg_wait,
4742 };
4743
4744 static const struct amdgpu_ring_funcs gfx_v9_0_ring_funcs_kiq = {
4745         .type = AMDGPU_RING_TYPE_KIQ,
4746         .align_mask = 0xff,
4747         .nop = PACKET3(PACKET3_NOP, 0x3FFF),
4748         .support_64bit_ptrs = true,
4749         .vmhub = AMDGPU_GFXHUB,
4750         .get_rptr = gfx_v9_0_ring_get_rptr_compute,
4751         .get_wptr = gfx_v9_0_ring_get_wptr_compute,
4752         .set_wptr = gfx_v9_0_ring_set_wptr_compute,
4753         .emit_frame_size =
4754                 20 + /* gfx_v9_0_ring_emit_gds_switch */
4755                 7 + /* gfx_v9_0_ring_emit_hdp_flush */
4756                 5 + /* hdp invalidate */
4757                 7 + /* gfx_v9_0_ring_emit_pipeline_sync */
4758                 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 +
4759                 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 +
4760                 2 + /* gfx_v9_0_ring_emit_vm_flush */
4761                 8 + 8 + 8, /* gfx_v9_0_ring_emit_fence_kiq x3 for user fence, vm fence */
4762         .emit_ib_size = 4, /* gfx_v9_0_ring_emit_ib_compute */
4763         .emit_fence = gfx_v9_0_ring_emit_fence_kiq,
4764         .test_ring = gfx_v9_0_ring_test_ring,
4765         .insert_nop = amdgpu_ring_insert_nop,
4766         .pad_ib = amdgpu_ring_generic_pad_ib,
4767         .emit_rreg = gfx_v9_0_ring_emit_rreg,
4768         .emit_wreg = gfx_v9_0_ring_emit_wreg,
4769         .emit_reg_wait = gfx_v9_0_ring_emit_reg_wait,
4770         .emit_reg_write_reg_wait = gfx_v9_0_ring_emit_reg_write_reg_wait,
4771 };
4772
4773 static void gfx_v9_0_set_ring_funcs(struct amdgpu_device *adev)
4774 {
4775         int i;
4776
4777         adev->gfx.kiq.ring.funcs = &gfx_v9_0_ring_funcs_kiq;
4778
4779         for (i = 0; i < adev->gfx.num_gfx_rings; i++)
4780                 adev->gfx.gfx_ring[i].funcs = &gfx_v9_0_ring_funcs_gfx;
4781
4782         for (i = 0; i < adev->gfx.num_compute_rings; i++)
4783                 adev->gfx.compute_ring[i].funcs = &gfx_v9_0_ring_funcs_compute;
4784 }
4785
4786 static const struct amdgpu_irq_src_funcs gfx_v9_0_eop_irq_funcs = {
4787         .set = gfx_v9_0_set_eop_interrupt_state,
4788         .process = gfx_v9_0_eop_irq,
4789 };
4790
4791 static const struct amdgpu_irq_src_funcs gfx_v9_0_priv_reg_irq_funcs = {
4792         .set = gfx_v9_0_set_priv_reg_fault_state,
4793         .process = gfx_v9_0_priv_reg_irq,
4794 };
4795
4796 static const struct amdgpu_irq_src_funcs gfx_v9_0_priv_inst_irq_funcs = {
4797         .set = gfx_v9_0_set_priv_inst_fault_state,
4798         .process = gfx_v9_0_priv_inst_irq,
4799 };
4800
4801 static void gfx_v9_0_set_irq_funcs(struct amdgpu_device *adev)
4802 {
4803         adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST;
4804         adev->gfx.eop_irq.funcs = &gfx_v9_0_eop_irq_funcs;
4805
4806         adev->gfx.priv_reg_irq.num_types = 1;
4807         adev->gfx.priv_reg_irq.funcs = &gfx_v9_0_priv_reg_irq_funcs;
4808
4809         adev->gfx.priv_inst_irq.num_types = 1;
4810         adev->gfx.priv_inst_irq.funcs = &gfx_v9_0_priv_inst_irq_funcs;
4811 }
4812
4813 static void gfx_v9_0_set_rlc_funcs(struct amdgpu_device *adev)
4814 {
4815         switch (adev->asic_type) {
4816         case CHIP_VEGA10:
4817         case CHIP_VEGA12:
4818         case CHIP_VEGA20:
4819         case CHIP_RAVEN:
4820                 adev->gfx.rlc.funcs = &gfx_v9_0_rlc_funcs;
4821                 break;
4822         default:
4823                 break;
4824         }
4825 }
4826
4827 static void gfx_v9_0_set_gds_init(struct amdgpu_device *adev)
4828 {
4829         /* init asci gds info */
4830         switch (adev->asic_type) {
4831         case CHIP_VEGA10:
4832         case CHIP_VEGA12:
4833         case CHIP_VEGA20:
4834                 adev->gds.mem.total_size = 0x10000;
4835                 break;
4836         case CHIP_RAVEN:
4837                 adev->gds.mem.total_size = 0x1000;
4838                 break;
4839         default:
4840                 adev->gds.mem.total_size = 0x10000;
4841                 break;
4842         }
4843
4844         adev->gds.gws.total_size = 64;
4845         adev->gds.oa.total_size = 16;
4846
4847         if (adev->gds.mem.total_size == 64 * 1024) {
4848                 adev->gds.mem.gfx_partition_size = 4096;
4849                 adev->gds.mem.cs_partition_size = 4096;
4850
4851                 adev->gds.gws.gfx_partition_size = 4;
4852                 adev->gds.gws.cs_partition_size = 4;
4853
4854                 adev->gds.oa.gfx_partition_size = 4;
4855                 adev->gds.oa.cs_partition_size = 1;
4856         } else {
4857                 adev->gds.mem.gfx_partition_size = 1024;
4858                 adev->gds.mem.cs_partition_size = 1024;
4859
4860                 adev->gds.gws.gfx_partition_size = 16;
4861                 adev->gds.gws.cs_partition_size = 16;
4862
4863                 adev->gds.oa.gfx_partition_size = 4;
4864                 adev->gds.oa.cs_partition_size = 4;
4865         }
4866 }
4867
4868 static void gfx_v9_0_set_user_cu_inactive_bitmap(struct amdgpu_device *adev,
4869                                                  u32 bitmap)
4870 {
4871         u32 data;
4872
4873         if (!bitmap)
4874                 return;
4875
4876         data = bitmap << GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT;
4877         data &= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK;
4878
4879         WREG32_SOC15(GC, 0, mmGC_USER_SHADER_ARRAY_CONFIG, data);
4880 }
4881
4882 static u32 gfx_v9_0_get_cu_active_bitmap(struct amdgpu_device *adev)
4883 {
4884         u32 data, mask;
4885
4886         data = RREG32_SOC15(GC, 0, mmCC_GC_SHADER_ARRAY_CONFIG);
4887         data |= RREG32_SOC15(GC, 0, mmGC_USER_SHADER_ARRAY_CONFIG);
4888
4889         data &= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK;
4890         data >>= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT;
4891
4892         mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_cu_per_sh);
4893
4894         return (~data) & mask;
4895 }
4896
4897 static int gfx_v9_0_get_cu_info(struct amdgpu_device *adev,
4898                                  struct amdgpu_cu_info *cu_info)
4899 {
4900         int i, j, k, counter, active_cu_number = 0;
4901         u32 mask, bitmap, ao_bitmap, ao_cu_mask = 0;
4902         unsigned disable_masks[4 * 2];
4903
4904         if (!adev || !cu_info)
4905                 return -EINVAL;
4906
4907         amdgpu_gfx_parse_disable_cu(disable_masks, 4, 2);
4908
4909         mutex_lock(&adev->grbm_idx_mutex);
4910         for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
4911                 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
4912                         mask = 1;
4913                         ao_bitmap = 0;
4914                         counter = 0;
4915                         gfx_v9_0_select_se_sh(adev, i, j, 0xffffffff);
4916                         if (i < 4 && j < 2)
4917                                 gfx_v9_0_set_user_cu_inactive_bitmap(
4918                                         adev, disable_masks[i * 2 + j]);
4919                         bitmap = gfx_v9_0_get_cu_active_bitmap(adev);
4920                         cu_info->bitmap[i][j] = bitmap;
4921
4922                         for (k = 0; k < adev->gfx.config.max_cu_per_sh; k ++) {
4923                                 if (bitmap & mask) {
4924                                         if (counter < adev->gfx.config.max_cu_per_sh)
4925                                                 ao_bitmap |= mask;
4926                                         counter ++;
4927                                 }
4928                                 mask <<= 1;
4929                         }
4930                         active_cu_number += counter;
4931                         if (i < 2 && j < 2)
4932                                 ao_cu_mask |= (ao_bitmap << (i * 16 + j * 8));
4933                         cu_info->ao_cu_bitmap[i][j] = ao_bitmap;
4934                 }
4935         }
4936         gfx_v9_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
4937         mutex_unlock(&adev->grbm_idx_mutex);
4938
4939         cu_info->number = active_cu_number;
4940         cu_info->ao_cu_mask = ao_cu_mask;
4941         cu_info->simd_per_cu = NUM_SIMD_PER_CU;
4942
4943         return 0;
4944 }
4945
4946 const struct amdgpu_ip_block_version gfx_v9_0_ip_block =
4947 {
4948         .type = AMD_IP_BLOCK_TYPE_GFX,
4949         .major = 9,
4950         .minor = 0,
4951         .rev = 0,
4952         .funcs = &gfx_v9_0_ip_funcs,
4953 };