drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c

   1 /*
   2  * Copyright 2015 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23 #include <linux/firmware.h>
  24 #include "amdgpu.h"
  25 #include "amdgpu_ih.h"
  26 #include "amdgpu_gfx.h"
  27 #include "amdgpu_ucode.h"
  28 #include "si/clearstate_si.h"
  29 #include "bif/bif_3_0_d.h"
  30 #include "bif/bif_3_0_sh_mask.h"
  31 #include "oss/oss_1_0_d.h"
  32 #include "oss/oss_1_0_sh_mask.h"
  33 #include "gca/gfx_6_0_d.h"
  34 #include "gca/gfx_6_0_sh_mask.h"
  35 #include "gmc/gmc_6_0_d.h"
  36 #include "gmc/gmc_6_0_sh_mask.h"
  37 #include "dce/dce_6_0_d.h"
  38 #include "dce/dce_6_0_sh_mask.h"
  39 #include "gca/gfx_7_2_enum.h"
  40 #include "si_enums.h"
  41
  42 static void gfx_v6_0_set_ring_funcs(struct amdgpu_device *adev);
  43 static void gfx_v6_0_set_irq_funcs(struct amdgpu_device *adev);
  44 static void gfx_v6_0_get_cu_info(struct amdgpu_device *adev);
  45
  46 MODULE_FIRMWARE("radeon/tahiti_pfp.bin");
  47 MODULE_FIRMWARE("radeon/tahiti_me.bin");
  48 MODULE_FIRMWARE("radeon/tahiti_ce.bin");
  49 MODULE_FIRMWARE("radeon/tahiti_rlc.bin");
  50
  51 MODULE_FIRMWARE("radeon/pitcairn_pfp.bin");
  52 MODULE_FIRMWARE("radeon/pitcairn_me.bin");
  53 MODULE_FIRMWARE("radeon/pitcairn_ce.bin");
  54 MODULE_FIRMWARE("radeon/pitcairn_rlc.bin");
  55
  56 MODULE_FIRMWARE("radeon/verde_pfp.bin");
  57 MODULE_FIRMWARE("radeon/verde_me.bin");
  58 MODULE_FIRMWARE("radeon/verde_ce.bin");
  59 MODULE_FIRMWARE("radeon/verde_rlc.bin");
  60
  61 MODULE_FIRMWARE("radeon/oland_pfp.bin");
  62 MODULE_FIRMWARE("radeon/oland_me.bin");
  63 MODULE_FIRMWARE("radeon/oland_ce.bin");
  64 MODULE_FIRMWARE("radeon/oland_rlc.bin");
  65
  66 MODULE_FIRMWARE("radeon/hainan_pfp.bin");
  67 MODULE_FIRMWARE("radeon/hainan_me.bin");
  68 MODULE_FIRMWARE("radeon/hainan_ce.bin");
  69 MODULE_FIRMWARE("radeon/hainan_rlc.bin");
  70
  71 static u32 gfx_v6_0_get_csb_size(struct amdgpu_device *adev);
  72 static void gfx_v6_0_get_csb_buffer(struct amdgpu_device *adev, volatile u32 *buffer);
  73 //static void gfx_v6_0_init_cp_pg_table(struct amdgpu_device *adev);
  74 static void gfx_v6_0_init_pg(struct amdgpu_device *adev);
  75
  76 #define ARRAY_MODE(x)                                   ((x) << GB_TILE_MODE0__ARRAY_MODE__SHIFT)
  77 #define PIPE_CONFIG(x)                                  ((x) << GB_TILE_MODE0__PIPE_CONFIG__SHIFT)
  78 #define TILE_SPLIT(x)                                   ((x) << GB_TILE_MODE0__TILE_SPLIT__SHIFT)
  79 #define MICRO_TILE_MODE(x)                              ((x) << 0)
  80 #define SAMPLE_SPLIT(x)                                 ((x) << GB_TILE_MODE0__SAMPLE_SPLIT__SHIFT)
  81 #define BANK_WIDTH(x)                                   ((x) << 14)
  82 #define BANK_HEIGHT(x)                                  ((x) << 16)
  83 #define MACRO_TILE_ASPECT(x)                            ((x) << 18)
  84 #define NUM_BANKS(x)                                    ((x) << 20)
  85
  86 static const u32 verde_rlc_save_restore_register_list[] =
  87 {
  88         (0x8000 << 16) | (0x98f4 >> 2),
  89         0x00000000,
  90         (0x8040 << 16) | (0x98f4 >> 2),
  91         0x00000000,
  92         (0x8000 << 16) | (0xe80 >> 2),
  93         0x00000000,
  94         (0x8040 << 16) | (0xe80 >> 2),
  95         0x00000000,
  96         (0x8000 << 16) | (0x89bc >> 2),
  97         0x00000000,
  98         (0x8040 << 16) | (0x89bc >> 2),
  99         0x00000000,
 100         (0x8000 << 16) | (0x8c1c >> 2),
 101         0x00000000,
 102         (0x8040 << 16) | (0x8c1c >> 2),
 103         0x00000000,
 104         (0x9c00 << 16) | (0x98f0 >> 2),
 105         0x00000000,
 106         (0x9c00 << 16) | (0xe7c >> 2),
 107         0x00000000,
 108         (0x8000 << 16) | (0x9148 >> 2),
 109         0x00000000,
 110         (0x8040 << 16) | (0x9148 >> 2),
 111         0x00000000,
 112         (0x9c00 << 16) | (0x9150 >> 2),
 113         0x00000000,
 114         (0x9c00 << 16) | (0x897c >> 2),
 115         0x00000000,
 116         (0x9c00 << 16) | (0x8d8c >> 2),
 117         0x00000000,
 118         (0x9c00 << 16) | (0xac54 >> 2),
 119         0X00000000,
 120         0x3,
 121         (0x9c00 << 16) | (0x98f8 >> 2),
 122         0x00000000,
 123         (0x9c00 << 16) | (0x9910 >> 2),
 124         0x00000000,
 125         (0x9c00 << 16) | (0x9914 >> 2),
 126         0x00000000,
 127         (0x9c00 << 16) | (0x9918 >> 2),
 128         0x00000000,
 129         (0x9c00 << 16) | (0x991c >> 2),
 130         0x00000000,
 131         (0x9c00 << 16) | (0x9920 >> 2),
 132         0x00000000,
 133         (0x9c00 << 16) | (0x9924 >> 2),
 134         0x00000000,
 135         (0x9c00 << 16) | (0x9928 >> 2),
 136         0x00000000,
 137         (0x9c00 << 16) | (0x992c >> 2),
 138         0x00000000,
 139         (0x9c00 << 16) | (0x9930 >> 2),
 140         0x00000000,
 141         (0x9c00 << 16) | (0x9934 >> 2),
 142         0x00000000,
 143         (0x9c00 << 16) | (0x9938 >> 2),
 144         0x00000000,
 145         (0x9c00 << 16) | (0x993c >> 2),
 146         0x00000000,
 147         (0x9c00 << 16) | (0x9940 >> 2),
 148         0x00000000,
 149         (0x9c00 << 16) | (0x9944 >> 2),
 150         0x00000000,
 151         (0x9c00 << 16) | (0x9948 >> 2),
 152         0x00000000,
 153         (0x9c00 << 16) | (0x994c >> 2),
 154         0x00000000,
 155         (0x9c00 << 16) | (0x9950 >> 2),
 156         0x00000000,
 157         (0x9c00 << 16) | (0x9954 >> 2),
 158         0x00000000,
 159         (0x9c00 << 16) | (0x9958 >> 2),
 160         0x00000000,
 161         (0x9c00 << 16) | (0x995c >> 2),
 162         0x00000000,
 163         (0x9c00 << 16) | (0x9960 >> 2),
 164         0x00000000,
 165         (0x9c00 << 16) | (0x9964 >> 2),
 166         0x00000000,
 167         (0x9c00 << 16) | (0x9968 >> 2),
 168         0x00000000,
 169         (0x9c00 << 16) | (0x996c >> 2),
 170         0x00000000,
 171         (0x9c00 << 16) | (0x9970 >> 2),
 172         0x00000000,
 173         (0x9c00 << 16) | (0x9974 >> 2),
 174         0x00000000,
 175         (0x9c00 << 16) | (0x9978 >> 2),
 176         0x00000000,
 177         (0x9c00 << 16) | (0x997c >> 2),
 178         0x00000000,
 179         (0x9c00 << 16) | (0x9980 >> 2),
 180         0x00000000,
 181         (0x9c00 << 16) | (0x9984 >> 2),
 182         0x00000000,
 183         (0x9c00 << 16) | (0x9988 >> 2),
 184         0x00000000,
 185         (0x9c00 << 16) | (0x998c >> 2),
 186         0x00000000,
 187         (0x9c00 << 16) | (0x8c00 >> 2),
 188         0x00000000,
 189         (0x9c00 << 16) | (0x8c14 >> 2),
 190         0x00000000,
 191         (0x9c00 << 16) | (0x8c04 >> 2),
 192         0x00000000,
 193         (0x9c00 << 16) | (0x8c08 >> 2),
 194         0x00000000,
 195         (0x8000 << 16) | (0x9b7c >> 2),
 196         0x00000000,
 197         (0x8040 << 16) | (0x9b7c >> 2),
 198         0x00000000,
 199         (0x8000 << 16) | (0xe84 >> 2),
 200         0x00000000,
 201         (0x8040 << 16) | (0xe84 >> 2),
 202         0x00000000,
 203         (0x8000 << 16) | (0x89c0 >> 2),
 204         0x00000000,
 205         (0x8040 << 16) | (0x89c0 >> 2),
 206         0x00000000,
 207         (0x8000 << 16) | (0x914c >> 2),
 208         0x00000000,
 209         (0x8040 << 16) | (0x914c >> 2),
 210         0x00000000,
 211         (0x8000 << 16) | (0x8c20 >> 2),
 212         0x00000000,
 213         (0x8040 << 16) | (0x8c20 >> 2),
 214         0x00000000,
 215         (0x8000 << 16) | (0x9354 >> 2),
 216         0x00000000,
 217         (0x8040 << 16) | (0x9354 >> 2),
 218         0x00000000,
 219         (0x9c00 << 16) | (0x9060 >> 2),
 220         0x00000000,
 221         (0x9c00 << 16) | (0x9364 >> 2),
 222         0x00000000,
 223         (0x9c00 << 16) | (0x9100 >> 2),
 224         0x00000000,
 225         (0x9c00 << 16) | (0x913c >> 2),
 226         0x00000000,
 227         (0x8000 << 16) | (0x90e0 >> 2),
 228         0x00000000,
 229         (0x8000 << 16) | (0x90e4 >> 2),
 230         0x00000000,
 231         (0x8000 << 16) | (0x90e8 >> 2),
 232         0x00000000,
 233         (0x8040 << 16) | (0x90e0 >> 2),
 234         0x00000000,
 235         (0x8040 << 16) | (0x90e4 >> 2),
 236         0x00000000,
 237         (0x8040 << 16) | (0x90e8 >> 2),
 238         0x00000000,
 239         (0x9c00 << 16) | (0x8bcc >> 2),
 240         0x00000000,
 241         (0x9c00 << 16) | (0x8b24 >> 2),
 242         0x00000000,
 243         (0x9c00 << 16) | (0x88c4 >> 2),
 244         0x00000000,
 245         (0x9c00 << 16) | (0x8e50 >> 2),
 246         0x00000000,
 247         (0x9c00 << 16) | (0x8c0c >> 2),
 248         0x00000000,
 249         (0x9c00 << 16) | (0x8e58 >> 2),
 250         0x00000000,
 251         (0x9c00 << 16) | (0x8e5c >> 2),
 252         0x00000000,
 253         (0x9c00 << 16) | (0x9508 >> 2),
 254         0x00000000,
 255         (0x9c00 << 16) | (0x950c >> 2),
 256         0x00000000,
 257         (0x9c00 << 16) | (0x9494 >> 2),
 258         0x00000000,
 259         (0x9c00 << 16) | (0xac0c >> 2),
 260         0x00000000,
 261         (0x9c00 << 16) | (0xac10 >> 2),
 262         0x00000000,
 263         (0x9c00 << 16) | (0xac14 >> 2),
 264         0x00000000,
 265         (0x9c00 << 16) | (0xae00 >> 2),
 266         0x00000000,
 267         (0x9c00 << 16) | (0xac08 >> 2),
 268         0x00000000,
 269         (0x9c00 << 16) | (0x88d4 >> 2),
 270         0x00000000,
 271         (0x9c00 << 16) | (0x88c8 >> 2),
 272         0x00000000,
 273         (0x9c00 << 16) | (0x88cc >> 2),
 274         0x00000000,
 275         (0x9c00 << 16) | (0x89b0 >> 2),
 276         0x00000000,
 277         (0x9c00 << 16) | (0x8b10 >> 2),
 278         0x00000000,
 279         (0x9c00 << 16) | (0x8a14 >> 2),
 280         0x00000000,
 281         (0x9c00 << 16) | (0x9830 >> 2),
 282         0x00000000,
 283         (0x9c00 << 16) | (0x9834 >> 2),
 284         0x00000000,
 285         (0x9c00 << 16) | (0x9838 >> 2),
 286         0x00000000,
 287         (0x9c00 << 16) | (0x9a10 >> 2),
 288         0x00000000,
 289         (0x8000 << 16) | (0x9870 >> 2),
 290         0x00000000,
 291         (0x8000 << 16) | (0x9874 >> 2),
 292         0x00000000,
 293         (0x8001 << 16) | (0x9870 >> 2),
 294         0x00000000,
 295         (0x8001 << 16) | (0x9874 >> 2),
 296         0x00000000,
 297         (0x8040 << 16) | (0x9870 >> 2),
 298         0x00000000,
 299         (0x8040 << 16) | (0x9874 >> 2),
 300         0x00000000,
 301         (0x8041 << 16) | (0x9870 >> 2),
 302         0x00000000,
 303         (0x8041 << 16) | (0x9874 >> 2),
 304         0x00000000,
 305         0x00000000
 306 };
 307
 308 static int gfx_v6_0_init_microcode(struct amdgpu_device *adev)
 309 {
 310         const char *chip_name;
 311         char fw_name[30];
 312         int err;
 313         const struct gfx_firmware_header_v1_0 *cp_hdr;
 314         const struct rlc_firmware_header_v1_0 *rlc_hdr;
 315
 316         DRM_DEBUG("\n");
 317
 318         switch (adev->asic_type) {
 319         case CHIP_TAHITI:
 320                 chip_name = "tahiti";
 321                 break;
 322         case CHIP_PITCAIRN:
 323                 chip_name = "pitcairn";
 324                 break;
 325         case CHIP_VERDE:
 326                 chip_name = "verde";
 327                 break;
 328         case CHIP_OLAND:
 329                 chip_name = "oland";
 330                 break;
 331         case CHIP_HAINAN:
 332                 chip_name = "hainan";
 333                 break;
 334         default: BUG();
 335         }
 336
 337         snprintf(fw_name, sizeof(fw_name), "radeon/%s_pfp.bin", chip_name);
 338         err = request_firmware(&adev->gfx.pfp_fw, fw_name, adev->dev);
 339         if (err)
 340                 goto out;
 341         err = amdgpu_ucode_validate(adev->gfx.pfp_fw);
 342         if (err)
 343                 goto out;
 344         cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data;
 345         adev->gfx.pfp_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
 346         adev->gfx.pfp_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
 347
 348         snprintf(fw_name, sizeof(fw_name), "radeon/%s_me.bin", chip_name);
 349         err = request_firmware(&adev->gfx.me_fw, fw_name, adev->dev);
 350         if (err)
 351                 goto out;
 352         err = amdgpu_ucode_validate(adev->gfx.me_fw);
 353         if (err)
 354                 goto out;
 355         cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data;
 356         adev->gfx.me_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
 357         adev->gfx.me_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
 358
 359         snprintf(fw_name, sizeof(fw_name), "radeon/%s_ce.bin", chip_name);
 360         err = request_firmware(&adev->gfx.ce_fw, fw_name, adev->dev);
 361         if (err)
 362                 goto out;
 363         err = amdgpu_ucode_validate(adev->gfx.ce_fw);
 364         if (err)
 365                 goto out;
 366         cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data;
 367         adev->gfx.ce_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
 368         adev->gfx.ce_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
 369
 370         snprintf(fw_name, sizeof(fw_name), "radeon/%s_rlc.bin", chip_name);
 371         err = request_firmware(&adev->gfx.rlc_fw, fw_name, adev->dev);
 372         if (err)
 373                 goto out;
 374         err = amdgpu_ucode_validate(adev->gfx.rlc_fw);
 375         rlc_hdr = (const struct rlc_firmware_header_v1_0 *)adev->gfx.rlc_fw->data;
 376         adev->gfx.rlc_fw_version = le32_to_cpu(rlc_hdr->header.ucode_version);
 377         adev->gfx.rlc_feature_version = le32_to_cpu(rlc_hdr->ucode_feature_version);
 378
 379 out:
 380         if (err) {
 381                 printk(KERN_ERR
 382                        "gfx6: Failed to load firmware \"%s\"\n",
 383                        fw_name);
 384                 release_firmware(adev->gfx.pfp_fw);
 385                 adev->gfx.pfp_fw = NULL;
 386                 release_firmware(adev->gfx.me_fw);
 387                 adev->gfx.me_fw = NULL;
 388                 release_firmware(adev->gfx.ce_fw);
 389                 adev->gfx.ce_fw = NULL;
 390                 release_firmware(adev->gfx.rlc_fw);
 391                 adev->gfx.rlc_fw = NULL;
 392         }
 393         return err;
 394 }
 395
 396 static void gfx_v6_0_tiling_mode_table_init(struct amdgpu_device *adev)
 397 {
 398         const u32 num_tile_mode_states = 32;
 399         u32 reg_offset, gb_tile_moden, split_equal_to_row_size;
 400
 401         switch (adev->gfx.config.mem_row_size_in_kb) {
 402         case 1:
 403                 split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_1KB;
 404                 break;
 405         case 2:
 406         default:
 407                 split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_2KB;
 408                 break;
 409         case 4:
 410                 split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_4KB;
 411                 break;
 412         }
 413
 414         if (adev->asic_type == CHIP_VERDE) {
 415                 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) {
 416                         switch (reg_offset) {
 417                         case 0:
 418                                 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
 419                                                  ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 420                                                  PIPE_CONFIG(ADDR_SURF_P4_8x16) |
 421                                                  TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
 422                                                  BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 423                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
 424                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
 425                                                  NUM_BANKS(ADDR_SURF_16_BANK));
 426                                 break;
 427                         case 1:
 428                                 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
 429                                                  ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 430                                                  PIPE_CONFIG(ADDR_SURF_P4_8x16) |
 431                                                  TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
 432                                                  BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 433                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
 434                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
 435                                                  NUM_BANKS(ADDR_SURF_16_BANK));
 436                                 break;
 437                         case 2:
 438                                 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
 439                                                  ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 440                                                  PIPE_CONFIG(ADDR_SURF_P4_8x16) |
 441                                                  TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
 442                                                  BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 443                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
 444                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
 445                                                  NUM_BANKS(ADDR_SURF_16_BANK));
 446                                 break;
 447                         case 3:
 448                                 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
 449                                                  ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 450                                                  PIPE_CONFIG(ADDR_SURF_P4_8x16) |
 451                                                  BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 452                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
 453                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
 454                                                  NUM_BANKS(ADDR_SURF_8_BANK) |
 455                                                  TILE_SPLIT(split_equal_to_row_size));
 456                                 break;
 457                         case 4:
 458                                 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
 459                                                  ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
 460                                                  PIPE_CONFIG(ADDR_SURF_P4_8x16));
 461                                 break;
 462                         case 5:
 463                                 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
 464                                                  ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 465                                                  PIPE_CONFIG(ADDR_SURF_P4_8x16) |
 466                                                  TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
 467                                                  BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 468                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
 469                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
 470                                                  NUM_BANKS(ADDR_SURF_4_BANK));
 471                                 break;
 472                         case 6:
 473                                 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
 474                                                  ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 475                                                  PIPE_CONFIG(ADDR_SURF_P4_8x16) |
 476                                                  TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
 477                                                  BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 478                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
 479                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
 480                                                  NUM_BANKS(ADDR_SURF_4_BANK));
 481                                 break;
 482                         case 7:
 483                                 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
 484                                                  ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 485                                                  PIPE_CONFIG(ADDR_SURF_P4_8x16) |
 486                                                  TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
 487                                                  BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 488                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
 489                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
 490                                                  NUM_BANKS(ADDR_SURF_2_BANK));
 491                                 break;
 492                         case 8:
 493                                 gb_tile_moden = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED));
 494                                 break;
 495                         case 9:
 496                                 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
 497                                                  ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
 498                                                  PIPE_CONFIG(ADDR_SURF_P4_8x16));
 499                                 break;
 500                         case 10:
 501                                 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
 502                                                  ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 503                                                  PIPE_CONFIG(ADDR_SURF_P4_8x16) |
 504                                                  TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
 505                                                  BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 506                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
 507                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
 508                                                  NUM_BANKS(ADDR_SURF_16_BANK));
 509                                 break;
 510                         case 11:
 511                                 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
 512                                                  ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 513                                                  PIPE_CONFIG(ADDR_SURF_P4_8x16) |
 514                                                  TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
 515                                                  BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 516                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
 517                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
 518                                                  NUM_BANKS(ADDR_SURF_16_BANK));
 519                                 break;
 520                         case 12:
 521                                 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
 522                                                  ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 523                                                  PIPE_CONFIG(ADDR_SURF_P4_8x16) |
 524                                                  TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
 525                                                  BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 526                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
 527                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
 528                                                  NUM_BANKS(ADDR_SURF_16_BANK));
 529                                 break;
 530                         case 13:
 531                                 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
 532                                                  ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
 533                                                  PIPE_CONFIG(ADDR_SURF_P4_8x16));
 534                                 break;
 535                         case 14:
 536                                 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
 537                                                  ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 538                                                  PIPE_CONFIG(ADDR_SURF_P4_8x16) |
 539                                                  TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
 540                                                  BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 541                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
 542                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
 543                                                  NUM_BANKS(ADDR_SURF_16_BANK));
 544                                 break;
 545                         case 15:
 546                                 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
 547                                                  ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 548                                                  PIPE_CONFIG(ADDR_SURF_P4_8x16) |
 549                                                  TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
 550                                                  BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 551                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
 552                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
 553                                                  NUM_BANKS(ADDR_SURF_16_BANK));
 554                                 break;
 555                         case 16:
 556                                 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
 557                                                  ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 558                                                  PIPE_CONFIG(ADDR_SURF_P4_8x16) |
 559                                                  TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
 560                                                  BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 561                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
 562                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
 563                                                  NUM_BANKS(ADDR_SURF_16_BANK));
 564                                 break;
 565                         case 17:
 566                                 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
 567                                                  ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 568                                                  PIPE_CONFIG(ADDR_SURF_P4_8x16) |
 569                                                  BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 570                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
 571                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
 572                                                  NUM_BANKS(ADDR_SURF_16_BANK) |
 573                                                  TILE_SPLIT(split_equal_to_row_size));
 574                                 break;
 575                         case 18:
 576                                 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
 577                                                  ARRAY_MODE(ARRAY_1D_TILED_THICK) |
 578                                                  PIPE_CONFIG(ADDR_SURF_P4_8x16));
 579                                 break;
 580                         case 19:
 581                                 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
 582                                                  ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
 583                                                  PIPE_CONFIG(ADDR_SURF_P4_8x16) |
 584                                                  BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 585                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
 586                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
 587                                                  NUM_BANKS(ADDR_SURF_16_BANK) |
 588                                                  TILE_SPLIT(split_equal_to_row_size));
 589                                 break;
 590                         case 20:
 591                                 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
 592                                                  ARRAY_MODE(ARRAY_2D_TILED_THICK) |
 593                                                  PIPE_CONFIG(ADDR_SURF_P4_8x16) |
 594                                                  BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 595                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
 596                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
 597                                                  NUM_BANKS(ADDR_SURF_16_BANK) |
 598                                                  TILE_SPLIT(split_equal_to_row_size));
 599                                 break;
 600                         case 21:
 601                                 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
 602                                                  ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 603                                                  PIPE_CONFIG(ADDR_SURF_P4_8x16) |
 604                                                  TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
 605                                                  BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 606                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
 607                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
 608                                                  NUM_BANKS(ADDR_SURF_8_BANK));
 609                                 break;
 610                         case 22:
 611                                 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
 612                                                  ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 613                                                  PIPE_CONFIG(ADDR_SURF_P4_8x16) |
 614                                                  TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
 615                                                  BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 616                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
 617                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
 618                                                  NUM_BANKS(ADDR_SURF_8_BANK));
 619                                 break;
 620                         case 23:
 621                                 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
 622                                                  ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 623                                                  PIPE_CONFIG(ADDR_SURF_P4_8x16) |
 624                                                  TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
 625                                                  BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 626                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
 627                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
 628                                                  NUM_BANKS(ADDR_SURF_4_BANK));
 629                                 break;
 630                         case 24:
 631                                 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
 632                                                  ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 633                                                  PIPE_CONFIG(ADDR_SURF_P4_8x16) |
 634                                                  TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
 635                                                  BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 636                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
 637                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
 638                                                  NUM_BANKS(ADDR_SURF_4_BANK));
 639                                 break;
 640                         case 25:
 641                                 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
 642                                                  ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 643                                                  PIPE_CONFIG(ADDR_SURF_P4_8x16) |
 644                                                  TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
 645                                                  BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 646                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
 647                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
 648                                                  NUM_BANKS(ADDR_SURF_2_BANK));
 649                                 break;
 650                         case 26:
 651                                 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
 652                                                  ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 653                                                  PIPE_CONFIG(ADDR_SURF_P4_8x16) |
 654                                                  TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
 655                                                  BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 656                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
 657                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
 658                                                  NUM_BANKS(ADDR_SURF_2_BANK));
 659                                 break;
 660                         case 27:
 661                                 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
 662                                                  ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 663                                                  PIPE_CONFIG(ADDR_SURF_P4_8x16) |
 664                                                  TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
 665                                                  BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 666                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
 667                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
 668                                                  NUM_BANKS(ADDR_SURF_2_BANK));
 669                                 break;
 670                         case 28:
 671                                 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
 672                                                  ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 673                                                  PIPE_CONFIG(ADDR_SURF_P4_8x16) |
 674                                                  TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
 675                                                  BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 676                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
 677                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
 678                                                  NUM_BANKS(ADDR_SURF_2_BANK));
 679                                 break;
 680                         case 29:
 681                                 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
 682                                                  ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 683                                                  PIPE_CONFIG(ADDR_SURF_P4_8x16) |
 684                                                  TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
 685                                                  BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 686                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
 687                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
 688                                                  NUM_BANKS(ADDR_SURF_2_BANK));
 689                                 break;
 690                         case 30:
 691                                 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
 692                                                  ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 693                                                  PIPE_CONFIG(ADDR_SURF_P4_8x16) |
 694                                                  TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
 695                                                  BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 696                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
 697                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
 698                                                  NUM_BANKS(ADDR_SURF_2_BANK));
 699                                 break;
 700                         default:
 701                                 continue;
 702                         }
 703                         adev->gfx.config.tile_mode_array[reg_offset] = gb_tile_moden;
 704                         WREG32(mmGB_TILE_MODE0 + reg_offset, gb_tile_moden);
 705                 }
 706         } else if (adev->asic_type == CHIP_OLAND ||
 707             adev->asic_type == CHIP_HAINAN) {
 708                 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) {
 709                         switch (reg_offset) {
 710                         case 0:
 711                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 712                                                  MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
 713                                                  PIPE_CONFIG(ADDR_SURF_P4_8x16) |
 714                                                  TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
 715                                                  NUM_BANKS(ADDR_SURF_16_BANK) |
 716                                                  BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 717                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
 718                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));
 719                                 break;
 720                         case 1:
 721                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 722                                                  MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
 723                                                  PIPE_CONFIG(ADDR_SURF_P4_8x16) |
 724                                                  TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
 725                                                  NUM_BANKS(ADDR_SURF_16_BANK) |
 726                                                  BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 727                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
 728                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));
 729                                 break;
 730                         case 2:
 731                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 732                                                  MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
 733                                                  PIPE_CONFIG(ADDR_SURF_P4_8x16) |
 734                                                  TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
 735                                                  NUM_BANKS(ADDR_SURF_16_BANK) |
 736                                                  BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 737                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
 738                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));
 739                                 break;
 740                         case 3:
 741                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 742                                                  MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
 743                                                  PIPE_CONFIG(ADDR_SURF_P4_8x16) |
 744                                                  TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
 745                                                  NUM_BANKS(ADDR_SURF_16_BANK) |
 746                                                  BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 747                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
 748                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));
 749                                 break;
 750                         case 4:
 751                                 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
 752                                                  MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
 753                                                  PIPE_CONFIG(ADDR_SURF_P4_8x16) |
 754                                                  TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
 755                                                  NUM_BANKS(ADDR_SURF_16_BANK) |
 756                                                  BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 757                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
 758                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
 759                                 break;
 760                         case 5:
 761                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 762                                                  MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
 763                                                  PIPE_CONFIG(ADDR_SURF_P4_8x16) |
 764                                                  TILE_SPLIT(split_equal_to_row_size) |
 765                                                  NUM_BANKS(ADDR_SURF_16_BANK) |
 766                                                  BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 767                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
 768                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
 769                                 break;
 770                         case 6:
 771                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 772                                                  MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
 773                                                  PIPE_CONFIG(ADDR_SURF_P4_8x16) |
 774                                                  TILE_SPLIT(split_equal_to_row_size) |
 775                                                  NUM_BANKS(ADDR_SURF_16_BANK) |
 776                                                  BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 777                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
 778                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
 779                                 break;
 780                         case 7:
 781                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 782                                                  MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
 783                                                  PIPE_CONFIG(ADDR_SURF_P4_8x16) |
 784                                                  TILE_SPLIT(split_equal_to_row_size) |
 785                                                  NUM_BANKS(ADDR_SURF_16_BANK) |
 786                                                  BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 787                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
 788                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));
 789                                 break;
 790                         case 8:
 791                                 gb_tile_moden = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
 792                                                  MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
 793                                                  PIPE_CONFIG(ADDR_SURF_P4_8x16) |
 794                                                  TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
 795                                                  NUM_BANKS(ADDR_SURF_16_BANK) |
 796                                                  BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 797                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
 798                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
 799                                 break;
 800                         case 9:
 801                                 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
 802                                                  MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
 803                                                  PIPE_CONFIG(ADDR_SURF_P4_8x16) |
 804                                                  TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
 805                                                  NUM_BANKS(ADDR_SURF_16_BANK) |
 806                                                  BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 807                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
 808                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
 809                                 break;
 810                         case 10:
 811                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 812                                                  MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
 813                                                  PIPE_CONFIG(ADDR_SURF_P4_8x16) |
 814                                                  TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
 815                                                  NUM_BANKS(ADDR_SURF_16_BANK) |
 816                                                  BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 817                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
 818                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));
 819                                 break;
 820                         case 11:
 821                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 822                                                  MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
 823                                                  PIPE_CONFIG(ADDR_SURF_P4_8x16) |
 824                                                  TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
 825                                                  NUM_BANKS(ADDR_SURF_16_BANK) |
 826                                                  BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 827                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
 828                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
 829                                 break;
 830                         case 12:
 831                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 832                                                  MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
 833                                                  PIPE_CONFIG(ADDR_SURF_P4_8x16) |
 834                                                  TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
 835                                                  NUM_BANKS(ADDR_SURF_16_BANK) |
 836                                                  BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 837                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
 838                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
 839                                 break;
 840                         case 13:
 841                                 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
 842                                                  MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
 843                                                  PIPE_CONFIG(ADDR_SURF_P4_8x16) |
 844                                                  TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
 845                                                  NUM_BANKS(ADDR_SURF_16_BANK) |
 846                                                  BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 847                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
 848                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
 849                                 break;
 850                         case 14:
 851                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 852                                                  MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
 853                                                  PIPE_CONFIG(ADDR_SURF_P4_8x16) |
 854                                                  TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
 855                                                  NUM_BANKS(ADDR_SURF_16_BANK) |
 856                                                  BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 857                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
 858                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
 859                                 break;
 860                         case 15:
 861                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 862                                                  MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
 863                                                  PIPE_CONFIG(ADDR_SURF_P4_8x16) |
 864                                                  TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
 865                                                  NUM_BANKS(ADDR_SURF_16_BANK) |
 866                                                  BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 867                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
 868                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
 869                                 break;
 870                         case 16:
 871                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 872                                                  MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
 873                                                  PIPE_CONFIG(ADDR_SURF_P4_8x16) |
 874                                                  TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
 875                                                  NUM_BANKS(ADDR_SURF_16_BANK) |
 876                                                  BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 877                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
 878                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
 879                                 break;
 880                         case 17:
 881                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 882                                                  MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
 883                                                  PIPE_CONFIG(ADDR_SURF_P4_8x16) |
 884                                                  TILE_SPLIT(split_equal_to_row_size) |
 885                                                  NUM_BANKS(ADDR_SURF_16_BANK) |
 886                                                  BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 887                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
 888                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
 889                                 break;
 890                         case 21:
 891                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 892                                                  MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
 893                                                  PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
 894                                                  TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
 895                                                  NUM_BANKS(ADDR_SURF_16_BANK) |
 896                                                  BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
 897                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
 898                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
 899                                 break;
 900                         case 22:
 901                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 902                                                  MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
 903                                                  PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
 904                                                  TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
 905                                                  NUM_BANKS(ADDR_SURF_16_BANK) |
 906                                                  BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 907                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
 908                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));
 909                                 break;
 910                         case 23:
 911                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 912                                                  MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
 913                                                  PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
 914                                                  TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
 915                                                  NUM_BANKS(ADDR_SURF_16_BANK) |
 916                                                  BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 917                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
 918                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
 919                                 break;
 920                         case 24:
 921                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 922                                                  MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
 923                                                  PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
 924                                                  TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
 925                                                  NUM_BANKS(ADDR_SURF_16_BANK) |
 926                                                  BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 927                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
 928                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
 929                                 break;
 930                         case 25:
 931                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 932                                                  MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
 933                                                  PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
 934                                                  TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
 935                                                  NUM_BANKS(ADDR_SURF_8_BANK) |
 936                                                  BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 937                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
 938                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1));
 939                                 break;
 940                         default:
 941                                 gb_tile_moden = 0;
 942                                 break;
 943                         }
 944                         adev->gfx.config.tile_mode_array[reg_offset] = gb_tile_moden;
 945                         WREG32(mmGB_TILE_MODE0 + reg_offset, gb_tile_moden);
 946                 }
 947         } else if ((adev->asic_type == CHIP_TAHITI) || (adev->asic_type == CHIP_PITCAIRN)) {
 948                 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) {
 949                         switch (reg_offset) {
 950                         case 0:
 951                                 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
 952                                                  ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 953                                                  PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
 954                                                  TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
 955                                                  BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 956                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
 957                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
 958                                                  NUM_BANKS(ADDR_SURF_16_BANK));
 959                                 break;
 960                         case 1:
 961                                 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
 962                                                  ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 963                                                  PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
 964                                                  TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
 965                                                  BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 966                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
 967                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
 968                                                  NUM_BANKS(ADDR_SURF_16_BANK));
 969                                 break;
 970                         case 2:
 971                                 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
 972                                                  ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 973                                                  PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
 974                                                  TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
 975                                                  BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 976                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
 977                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
 978                                                  NUM_BANKS(ADDR_SURF_16_BANK));
 979                                 break;
 980                         case 3:
 981                                 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
 982                                                  ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 983                                                  PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
 984                                                  BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 985                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
 986                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
 987                                                  NUM_BANKS(ADDR_SURF_4_BANK) |
 988                                                  TILE_SPLIT(split_equal_to_row_size));
 989                                 break;
 990                         case 4:
 991                                 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
 992                                                  ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
 993                                                  PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16));
 994                                 break;
 995                         case 5:
 996                                 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
 997                                                  ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 998                                                  PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
 999                                                  TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
1000                                                  BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1001                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1002                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1003                                                  NUM_BANKS(ADDR_SURF_2_BANK));
1004                                 break;
1005                         case 6:
1006                                 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
1007                                                  ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1008                                                  PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1009                                                  TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1010                                                  BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1011                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
1012                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1013                                                  NUM_BANKS(ADDR_SURF_2_BANK));
1014                                 break;
1015                         case 7:
1016                                 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
1017                                                  ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1018                                                  PIPE_CONFIG(ADDR_SURF_P4_8x16) |
1019                                                  TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
1020                                                  BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1021                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1022                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1023                                                  NUM_BANKS(ADDR_SURF_2_BANK));
1024                                 break;
1025                         case 8:
1026                                 gb_tile_moden = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED));
1027                                 break;
1028                         case 9:
1029                                 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
1030                                                  ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1031                                                  PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16));
1032                                 break;
1033                         case 10:
1034                                 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
1035                                                  ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1036                                                  PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1037                                                  TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1038                                                  BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1039                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1040                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1041                                                  NUM_BANKS(ADDR_SURF_16_BANK));
1042                                 break;
1043                         case 11:
1044                                 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
1045                                                  ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1046                                                  PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1047                                                  TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1048                                                  BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1049                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1050                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1051                                                  NUM_BANKS(ADDR_SURF_16_BANK));
1052                                 break;
1053                         case 12:
1054                                 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
1055                                                  ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1056                                                  PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1057                                                  TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
1058                                                  BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1059                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1060                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1061                                                  NUM_BANKS(ADDR_SURF_16_BANK));
1062                                 break;
1063                         case 13:
1064                                 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1065                                                  ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1066                                                  PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16));
1067                                 break;
1068                         case 14:
1069                                 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1070                                                  ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1071                                                  PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1072                                                  TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1073                                                  BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1074                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1075                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1076                                                  NUM_BANKS(ADDR_SURF_16_BANK));
1077                                 break;
1078                         case 15:
1079                                 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1080                                                  ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1081                                                  PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1082                                                  TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1083                                                  BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1084                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1085                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1086                                                  NUM_BANKS(ADDR_SURF_16_BANK));
1087                                 break;
1088                         case 16:
1089                                 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1090                                                  ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1091                                                  PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1092                                                  TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
1093                                                  BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1094                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1095                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1096                                                  NUM_BANKS(ADDR_SURF_16_BANK));
1097                                 break;
1098                         case 17:
1099                                 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1100                                                  ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1101                                                  PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1102                                                  BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1103                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1104                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1105                                                  NUM_BANKS(ADDR_SURF_16_BANK) |
1106                                                  TILE_SPLIT(split_equal_to_row_size));
1107                                 break;
1108                         case 18:
1109                                 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1110                                                  ARRAY_MODE(ARRAY_1D_TILED_THICK) |
1111                                                  PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16));
1112                                 break;
1113                         case 19:
1114                                 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1115                                                  ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
1116                                                  PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1117                                                  BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1118                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1119                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1120                                                  NUM_BANKS(ADDR_SURF_16_BANK) |
1121                                                  TILE_SPLIT(split_equal_to_row_size));
1122                                 break;
1123                         case 20:
1124                                 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1125                                                  ARRAY_MODE(ARRAY_2D_TILED_THICK) |
1126                                                  PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1127                                                  BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1128                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1129                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1130                                                  NUM_BANKS(ADDR_SURF_16_BANK) |
1131                                                  TILE_SPLIT(split_equal_to_row_size));
1132                                 break;
1133                         case 21:
1134                                 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1135                                                  ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1136                                                  PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1137                                                  TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1138                                                  BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1139                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
1140                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1141                                                  NUM_BANKS(ADDR_SURF_4_BANK));
1142                                 break;
1143                         case 22:
1144                                 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1145                                                  ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1146                                                  PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1147                                                  TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1148                                                  BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1149                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1150                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1151                                                  NUM_BANKS(ADDR_SURF_4_BANK));
1152                                 break;
1153                         case 23:
1154                                 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1155                                                  ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1156                                                  PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1157                                                  TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1158                                                  BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1159                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
1160                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1161                                                  NUM_BANKS(ADDR_SURF_2_BANK));
1162                                 break;
1163                         case 24:
1164                                 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1165                                                  ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1166                                                  PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1167                                                  TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
1168                                                  BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1169                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1170                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1171                                                  NUM_BANKS(ADDR_SURF_2_BANK));
1172                                 break;
1173                         case 25:
1174                                 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1175                                                  ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1176                                                  PIPE_CONFIG(ADDR_SURF_P4_8x16) |
1177                                                  TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
1178                                                  BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1179                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1180                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1181                                                  NUM_BANKS(ADDR_SURF_2_BANK));
1182                                 break;
1183                         case 26:
1184                                 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1185                                                  ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1186                                                  PIPE_CONFIG(ADDR_SURF_P4_8x16) |
1187                                                  TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
1188                                                  BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1189                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1190                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1191                                                  NUM_BANKS(ADDR_SURF_2_BANK));
1192                                 break;
1193                         case 27:
1194                                 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1195                                                  ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1196                                                  PIPE_CONFIG(ADDR_SURF_P4_8x16) |
1197                                                  TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
1198                                                  BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1199                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1200                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1201                                                  NUM_BANKS(ADDR_SURF_2_BANK));
1202                                 break;
1203                         case 28:
1204                                 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1205                                                  ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1206                                                  PIPE_CONFIG(ADDR_SURF_P4_8x16) |
1207                                                  TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
1208                                                  BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1209                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1210                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1211                                                  NUM_BANKS(ADDR_SURF_2_BANK));
1212                                 break;
1213                         case 29:
1214                                 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1215                                                  ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1216                                                  PIPE_CONFIG(ADDR_SURF_P4_8x16) |
1217                                                  TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
1218                                                  BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1219                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1220                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1221                                                  NUM_BANKS(ADDR_SURF_2_BANK));
1222                                 break;
1223                         case 30:
1224                                 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1225                                                  ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1226                                                  PIPE_CONFIG(ADDR_SURF_P4_8x16) |
1227                                                  TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
1228                                                  BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1229                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1230                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1231                                                  NUM_BANKS(ADDR_SURF_2_BANK));
1232                                 break;
1233                         default:
1234                                 continue;
1235                         }
1236                         adev->gfx.config.tile_mode_array[reg_offset] = gb_tile_moden;
1237                         WREG32(mmGB_TILE_MODE0 + reg_offset, gb_tile_moden);
1238                 }
1239         } else{
1240
1241                 DRM_ERROR("unknown asic: 0x%x\n", adev->asic_type);
1242         }
1243
1244 }
1245
1246 static void gfx_v6_0_select_se_sh(struct amdgpu_device *adev, u32 se_num,
1247                                   u32 sh_num, u32 instance)
1248 {
1249         u32 data;
1250
1251         if (instance == 0xffffffff)
1252                 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES, 1);
1253         else
1254                 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_INDEX, instance);
1255
1256         if ((se_num == 0xffffffff) && (sh_num == 0xffffffff))
1257                 data |= GRBM_GFX_INDEX__SH_BROADCAST_WRITES_MASK |
1258                         GRBM_GFX_INDEX__SE_BROADCAST_WRITES_MASK;
1259         else if (se_num == 0xffffffff)
1260                 data |= GRBM_GFX_INDEX__SE_BROADCAST_WRITES_MASK |
1261                         (sh_num << GRBM_GFX_INDEX__SH_INDEX__SHIFT);
1262         else if (sh_num == 0xffffffff)
1263                 data |= GRBM_GFX_INDEX__SH_BROADCAST_WRITES_MASK |
1264                         (se_num << GRBM_GFX_INDEX__SE_INDEX__SHIFT);
1265         else
1266                 data |= (sh_num << GRBM_GFX_INDEX__SH_INDEX__SHIFT) |
1267                         (se_num << GRBM_GFX_INDEX__SE_INDEX__SHIFT);
1268         WREG32(mmGRBM_GFX_INDEX, data);
1269 }
1270
1271 static u32 gfx_v6_0_create_bitmask(u32 bit_width)
1272 {
1273         return (u32)(((u64)1 << bit_width) - 1);
1274 }
1275
1276 static u32 gfx_v6_0_get_rb_disabled(struct amdgpu_device *adev,
1277                                     u32 max_rb_num_per_se,
1278                                     u32 sh_per_se)
1279 {
1280         u32 data, mask;
1281
1282         data = RREG32(mmCC_RB_BACKEND_DISABLE);
1283         data &= CC_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK;
1284         data |= RREG32(mmGC_USER_RB_BACKEND_DISABLE);
1285
1286         data >>= CC_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT;
1287
1288         mask = gfx_v6_0_create_bitmask(max_rb_num_per_se / sh_per_se);
1289
1290         return data & mask;
1291 }
1292
1293 static void gfx_v6_0_raster_config(struct amdgpu_device *adev, u32 *rconf)
1294 {
1295         switch (adev->asic_type) {
1296         case CHIP_TAHITI:
1297         case CHIP_PITCAIRN:
1298                 *rconf |=
1299                            (2 << PA_SC_RASTER_CONFIG__RB_XSEL2__SHIFT) |
1300                            (1 << PA_SC_RASTER_CONFIG__RB_XSEL__SHIFT) |
1301                            (2 << PA_SC_RASTER_CONFIG__PKR_MAP__SHIFT) |
1302                            (1 << PA_SC_RASTER_CONFIG__PKR_YSEL__SHIFT) |
1303                            (2 << PA_SC_RASTER_CONFIG__SE_MAP__SHIFT) |
1304                            (2 << PA_SC_RASTER_CONFIG__SE_XSEL__SHIFT) |
1305                            (2 << PA_SC_RASTER_CONFIG__SE_YSEL__SHIFT);
1306                 break;
1307         case CHIP_VERDE:
1308                 *rconf |=
1309                            (1 << PA_SC_RASTER_CONFIG__RB_XSEL__SHIFT) |
1310                            (2 << PA_SC_RASTER_CONFIG__PKR_MAP__SHIFT) |
1311                            (1 << PA_SC_RASTER_CONFIG__PKR_YSEL__SHIFT);
1312                 break;
1313         case CHIP_OLAND:
1314                 *rconf |= (1 << PA_SC_RASTER_CONFIG__RB_YSEL__SHIFT);
1315                 break;
1316         case CHIP_HAINAN:
1317                 *rconf |= 0x0;
1318                 break;
1319         default:
1320                 DRM_ERROR("unknown asic: 0x%x\n", adev->asic_type);
1321                 break;
1322         }
1323 }
1324
1325 static void gfx_v6_0_write_harvested_raster_configs(struct amdgpu_device *adev,
1326                                                     u32 raster_config, unsigned rb_mask,
1327                                                     unsigned num_rb)
1328 {
1329         unsigned sh_per_se = max_t(unsigned, adev->gfx.config.max_sh_per_se, 1);
1330         unsigned num_se = max_t(unsigned, adev->gfx.config.max_shader_engines, 1);
1331         unsigned rb_per_pkr = min_t(unsigned, num_rb / num_se / sh_per_se, 2);
1332         unsigned rb_per_se = num_rb / num_se;
1333         unsigned se_mask[4];
1334         unsigned se;
1335
1336         se_mask[0] = ((1 << rb_per_se) - 1) & rb_mask;
1337         se_mask[1] = (se_mask[0] << rb_per_se) & rb_mask;
1338         se_mask[2] = (se_mask[1] << rb_per_se) & rb_mask;
1339         se_mask[3] = (se_mask[2] << rb_per_se) & rb_mask;
1340
1341         WARN_ON(!(num_se == 1 || num_se == 2 || num_se == 4));
1342         WARN_ON(!(sh_per_se == 1 || sh_per_se == 2));
1343         WARN_ON(!(rb_per_pkr == 1 || rb_per_pkr == 2));
1344
1345         for (se = 0; se < num_se; se++) {
1346                 unsigned raster_config_se = raster_config;
1347                 unsigned pkr0_mask = ((1 << rb_per_pkr) - 1) << (se * rb_per_se);
1348                 unsigned pkr1_mask = pkr0_mask << rb_per_pkr;
1349                 int idx = (se / 2) * 2;
1350
1351                 if ((num_se > 1) && (!se_mask[idx] || !se_mask[idx + 1])) {
1352                         raster_config_se &= ~PA_SC_RASTER_CONFIG__SE_MAP_MASK;
1353
1354                         if (!se_mask[idx]) {
1355                                 raster_config_se |= RASTER_CONFIG_SE_MAP_3 << PA_SC_RASTER_CONFIG__SE_MAP__SHIFT;
1356                         } else {
1357                                 raster_config_se |= RASTER_CONFIG_SE_MAP_0 << PA_SC_RASTER_CONFIG__SE_MAP__SHIFT;
1358                         }
1359                 }
1360
1361                 pkr0_mask &= rb_mask;
1362                 pkr1_mask &= rb_mask;
1363                 if (rb_per_se > 2 && (!pkr0_mask || !pkr1_mask)) {
1364                         raster_config_se &= ~PA_SC_RASTER_CONFIG__PKR_MAP_MASK;
1365
1366                         if (!pkr0_mask) {
1367                                 raster_config_se |= RASTER_CONFIG_PKR_MAP_3 << PA_SC_RASTER_CONFIG__PKR_MAP__SHIFT;
1368                         } else {
1369                                 raster_config_se |= RASTER_CONFIG_PKR_MAP_0 << PA_SC_RASTER_CONFIG__PKR_MAP__SHIFT;
1370                         }
1371                 }
1372
1373                 if (rb_per_se >= 2) {
1374                         unsigned rb0_mask = 1 << (se * rb_per_se);
1375                         unsigned rb1_mask = rb0_mask << 1;
1376
1377                         rb0_mask &= rb_mask;
1378                         rb1_mask &= rb_mask;
1379                         if (!rb0_mask || !rb1_mask) {
1380                                 raster_config_se &= ~PA_SC_RASTER_CONFIG__RB_MAP_PKR0_MASK;
1381
1382                                 if (!rb0_mask) {
1383                                         raster_config_se |=
1384                                                 RASTER_CONFIG_RB_MAP_3 << PA_SC_RASTER_CONFIG__RB_MAP_PKR0__SHIFT;
1385                                 } else {
1386                                         raster_config_se |=
1387                                                 RASTER_CONFIG_RB_MAP_0 << PA_SC_RASTER_CONFIG__RB_MAP_PKR0__SHIFT;
1388                                 }
1389                         }
1390
1391                         if (rb_per_se > 2) {
1392                                 rb0_mask = 1 << (se * rb_per_se + rb_per_pkr);
1393                                 rb1_mask = rb0_mask << 1;
1394                                 rb0_mask &= rb_mask;
1395                                 rb1_mask &= rb_mask;
1396                                 if (!rb0_mask || !rb1_mask) {
1397                                         raster_config_se &= ~PA_SC_RASTER_CONFIG__RB_MAP_PKR1_MASK;
1398
1399                                         if (!rb0_mask) {
1400                                                 raster_config_se |=
1401                                                         RASTER_CONFIG_RB_MAP_3 << PA_SC_RASTER_CONFIG__RB_MAP_PKR1__SHIFT;
1402                                         } else {
1403                                                 raster_config_se |=
1404                                                         RASTER_CONFIG_RB_MAP_0 << PA_SC_RASTER_CONFIG__RB_MAP_PKR1__SHIFT;
1405                                         }
1406                                 }
1407                         }
1408                 }
1409
1410                 /* GRBM_GFX_INDEX has a different offset on SI */
1411                 gfx_v6_0_select_se_sh(adev, se, 0xffffffff, 0xffffffff);
1412                 WREG32(mmPA_SC_RASTER_CONFIG, raster_config_se);
1413         }
1414
1415         /* GRBM_GFX_INDEX has a different offset on SI */
1416         gfx_v6_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
1417 }
1418
1419 static void gfx_v6_0_setup_rb(struct amdgpu_device *adev,
1420                               u32 se_num, u32 sh_per_se,
1421                               u32 max_rb_num_per_se)
1422 {
1423         int i, j;
1424         u32 data, mask;
1425         u32 disabled_rbs = 0;
1426         u32 enabled_rbs = 0;
1427         unsigned num_rb_pipes;
1428
1429         mutex_lock(&adev->grbm_idx_mutex);
1430         for (i = 0; i < se_num; i++) {
1431                 for (j = 0; j < sh_per_se; j++) {
1432                         gfx_v6_0_select_se_sh(adev, i, j, 0xffffffff);
1433                         data = gfx_v6_0_get_rb_disabled(adev, max_rb_num_per_se, sh_per_se);
1434                         disabled_rbs |= data << ((i * sh_per_se + j) * 2);
1435                 }
1436         }
1437         gfx_v6_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
1438         mutex_unlock(&adev->grbm_idx_mutex);
1439
1440         mask = 1;
1441         for (i = 0; i < max_rb_num_per_se * se_num; i++) {
1442                 if (!(disabled_rbs & mask))
1443                         enabled_rbs |= mask;
1444                 mask <<= 1;
1445         }
1446
1447         adev->gfx.config.backend_enable_mask = enabled_rbs;
1448         adev->gfx.config.num_rbs = hweight32(enabled_rbs);
1449
1450         num_rb_pipes = min_t(unsigned, adev->gfx.config.max_backends_per_se *
1451                              adev->gfx.config.max_shader_engines, 16);
1452
1453         mutex_lock(&adev->grbm_idx_mutex);
1454         for (i = 0; i < se_num; i++) {
1455                 gfx_v6_0_select_se_sh(adev, i, 0xffffffff, 0xffffffff);
1456                 data = 0;
1457                 for (j = 0; j < sh_per_se; j++) {
1458                         switch (enabled_rbs & 3) {
1459                         case 1:
1460                                 data |= (RASTER_CONFIG_RB_MAP_0 << (i * sh_per_se + j) * 2);
1461                                 break;
1462                         case 2:
1463                                 data |= (RASTER_CONFIG_RB_MAP_3 << (i * sh_per_se + j) * 2);
1464                                 break;
1465                         case 3:
1466                         default:
1467                                 data |= (RASTER_CONFIG_RB_MAP_2 << (i * sh_per_se + j) * 2);
1468                                 break;
1469                         }
1470                         enabled_rbs >>= 2;
1471                 }
1472                 gfx_v6_0_raster_config(adev, &data);
1473
1474                 if (!adev->gfx.config.backend_enable_mask ||
1475                                 adev->gfx.config.num_rbs >= num_rb_pipes)
1476                         WREG32(mmPA_SC_RASTER_CONFIG, data);
1477                 else
1478                         gfx_v6_0_write_harvested_raster_configs(adev, data,
1479                                                                 adev->gfx.config.backend_enable_mask,
1480                                                                 num_rb_pipes);
1481         }
1482         gfx_v6_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
1483         mutex_unlock(&adev->grbm_idx_mutex);
1484 }
1485 /*
1486 static void gmc_v6_0_init_compute_vmid(struct amdgpu_device *adev)
1487 {
1488 }
1489 */
1490
1491 static u32 gfx_v6_0_get_cu_enabled(struct amdgpu_device *adev, u32 cu_per_sh)
1492 {
1493         u32 data, mask;
1494
1495         data = RREG32(mmCC_GC_SHADER_ARRAY_CONFIG);
1496         data &= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK;
1497         data |= RREG32(mmGC_USER_SHADER_ARRAY_CONFIG);
1498
1499         data >>= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT;
1500
1501         mask = gfx_v6_0_create_bitmask(cu_per_sh);
1502
1503         return ~data & mask;
1504 }
1505
1506
1507 static void gfx_v6_0_setup_spi(struct amdgpu_device *adev,
1508                          u32 se_num, u32 sh_per_se,
1509                          u32 cu_per_sh)
1510 {
1511         int i, j, k;
1512         u32 data, mask;
1513         u32 active_cu = 0;
1514
1515         mutex_lock(&adev->grbm_idx_mutex);
1516         for (i = 0; i < se_num; i++) {
1517                 for (j = 0; j < sh_per_se; j++) {
1518                         gfx_v6_0_select_se_sh(adev, i, j, 0xffffffff);
1519                         data = RREG32(mmSPI_STATIC_THREAD_MGMT_3);
1520                         active_cu = gfx_v6_0_get_cu_enabled(adev, cu_per_sh);
1521
1522                         mask = 1;
1523                         for (k = 0; k < 16; k++) {
1524                                 mask <<= k;
1525                                 if (active_cu & mask) {
1526                                         data &= ~mask;
1527                                         WREG32(mmSPI_STATIC_THREAD_MGMT_3, data);
1528                                         break;
1529                                 }
1530                         }
1531                 }
1532         }
1533         gfx_v6_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
1534         mutex_unlock(&adev->grbm_idx_mutex);
1535 }
1536
1537 static void gfx_v6_0_gpu_init(struct amdgpu_device *adev)
1538 {
1539         u32 gb_addr_config = 0;
1540         u32 mc_shared_chmap, mc_arb_ramcfg;
1541         u32 sx_debug_1;
1542         u32 hdp_host_path_cntl;
1543         u32 tmp;
1544
1545         switch (adev->asic_type) {
1546         case CHIP_TAHITI:
1547                 adev->gfx.config.max_shader_engines = 2;
1548                 adev->gfx.config.max_tile_pipes = 12;
1549                 adev->gfx.config.max_cu_per_sh = 8;
1550                 adev->gfx.config.max_sh_per_se = 2;
1551                 adev->gfx.config.max_backends_per_se = 4;
1552                 adev->gfx.config.max_texture_channel_caches = 12;
1553                 adev->gfx.config.max_gprs = 256;
1554                 adev->gfx.config.max_gs_threads = 32;
1555                 adev->gfx.config.max_hw_contexts = 8;
1556
1557                 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
1558                 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
1559                 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
1560                 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
1561                 gb_addr_config = TAHITI_GB_ADDR_CONFIG_GOLDEN;
1562                 break;
1563         case CHIP_PITCAIRN:
1564                 adev->gfx.config.max_shader_engines = 2;
1565                 adev->gfx.config.max_tile_pipes = 8;
1566                 adev->gfx.config.max_cu_per_sh = 5;
1567                 adev->gfx.config.max_sh_per_se = 2;
1568                 adev->gfx.config.max_backends_per_se = 4;
1569                 adev->gfx.config.max_texture_channel_caches = 8;
1570                 adev->gfx.config.max_gprs = 256;
1571                 adev->gfx.config.max_gs_threads = 32;
1572                 adev->gfx.config.max_hw_contexts = 8;
1573
1574                 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
1575                 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
1576                 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
1577                 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
1578                 gb_addr_config = TAHITI_GB_ADDR_CONFIG_GOLDEN;
1579                 break;
1580         case CHIP_VERDE:
1581                 adev->gfx.config.max_shader_engines = 1;
1582                 adev->gfx.config.max_tile_pipes = 4;
1583                 adev->gfx.config.max_cu_per_sh = 5;
1584                 adev->gfx.config.max_sh_per_se = 2;
1585                 adev->gfx.config.max_backends_per_se = 4;
1586                 adev->gfx.config.max_texture_channel_caches = 4;
1587                 adev->gfx.config.max_gprs = 256;
1588                 adev->gfx.config.max_gs_threads = 32;
1589                 adev->gfx.config.max_hw_contexts = 8;
1590
1591                 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
1592                 adev->gfx.config.sc_prim_fifo_size_backend = 0x40;
1593                 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
1594                 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
1595                 gb_addr_config = VERDE_GB_ADDR_CONFIG_GOLDEN;
1596                 break;
1597         case CHIP_OLAND:
1598                 adev->gfx.config.max_shader_engines = 1;
1599                 adev->gfx.config.max_tile_pipes = 4;
1600                 adev->gfx.config.max_cu_per_sh = 6;
1601                 adev->gfx.config.max_sh_per_se = 1;
1602                 adev->gfx.config.max_backends_per_se = 2;
1603                 adev->gfx.config.max_texture_channel_caches = 4;
1604                 adev->gfx.config.max_gprs = 256;
1605                 adev->gfx.config.max_gs_threads = 16;
1606                 adev->gfx.config.max_hw_contexts = 8;
1607
1608                 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
1609                 adev->gfx.config.sc_prim_fifo_size_backend = 0x40;
1610                 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
1611                 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
1612                 gb_addr_config = VERDE_GB_ADDR_CONFIG_GOLDEN;
1613                 break;
1614         case CHIP_HAINAN:
1615                 adev->gfx.config.max_shader_engines = 1;
1616                 adev->gfx.config.max_tile_pipes = 4;
1617                 adev->gfx.config.max_cu_per_sh = 5;
1618                 adev->gfx.config.max_sh_per_se = 1;
1619                 adev->gfx.config.max_backends_per_se = 1;
1620                 adev->gfx.config.max_texture_channel_caches = 2;
1621                 adev->gfx.config.max_gprs = 256;
1622                 adev->gfx.config.max_gs_threads = 16;
1623                 adev->gfx.config.max_hw_contexts = 8;
1624
1625                 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
1626                 adev->gfx.config.sc_prim_fifo_size_backend = 0x40;
1627                 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
1628                 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
1629                 gb_addr_config = HAINAN_GB_ADDR_CONFIG_GOLDEN;
1630                 break;
1631         default:
1632                 BUG();
1633                 break;
1634         }
1635
1636         WREG32(mmGRBM_CNTL, (0xff << GRBM_CNTL__READ_TIMEOUT__SHIFT));
1637         WREG32(mmSRBM_INT_CNTL, 1);
1638         WREG32(mmSRBM_INT_ACK, 1);
1639
1640         WREG32(mmBIF_FB_EN, BIF_FB_EN__FB_READ_EN_MASK | BIF_FB_EN__FB_WRITE_EN_MASK);
1641
1642         mc_shared_chmap = RREG32(mmMC_SHARED_CHMAP);
1643         mc_arb_ramcfg = RREG32(mmMC_ARB_RAMCFG);
1644
1645         adev->gfx.config.num_tile_pipes = adev->gfx.config.max_tile_pipes;
1646         adev->gfx.config.mem_max_burst_length_bytes = 256;
1647         tmp = (mc_arb_ramcfg & MC_ARB_RAMCFG__NOOFCOLS_MASK) >> MC_ARB_RAMCFG__NOOFCOLS__SHIFT;
1648         adev->gfx.config.mem_row_size_in_kb = (4 * (1 << (8 + tmp))) / 1024;
1649         if (adev->gfx.config.mem_row_size_in_kb > 4)
1650                 adev->gfx.config.mem_row_size_in_kb = 4;
1651         adev->gfx.config.shader_engine_tile_size = 32;
1652         adev->gfx.config.num_gpus = 1;
1653         adev->gfx.config.multi_gpu_tile_size = 64;
1654
1655         gb_addr_config &= ~GB_ADDR_CONFIG__ROW_SIZE_MASK;
1656         switch (adev->gfx.config.mem_row_size_in_kb) {
1657         case 1:
1658         default:
1659                 gb_addr_config |= 0 << GB_ADDR_CONFIG__ROW_SIZE__SHIFT;
1660                 break;
1661         case 2:
1662                 gb_addr_config |= 1 << GB_ADDR_CONFIG__ROW_SIZE__SHIFT;
1663                 break;
1664         case 4:
1665                 gb_addr_config |= 2 << GB_ADDR_CONFIG__ROW_SIZE__SHIFT;
1666                 break;
1667         }
1668         adev->gfx.config.gb_addr_config = gb_addr_config;
1669
1670         WREG32(mmGB_ADDR_CONFIG, gb_addr_config);
1671         WREG32(mmDMIF_ADDR_CONFIG, gb_addr_config);
1672         WREG32(mmDMIF_ADDR_CALC, gb_addr_config);
1673         WREG32(mmHDP_ADDR_CONFIG, gb_addr_config);
1674         WREG32(mmDMA_TILING_CONFIG + DMA0_REGISTER_OFFSET, gb_addr_config);
1675         WREG32(mmDMA_TILING_CONFIG + DMA1_REGISTER_OFFSET, gb_addr_config);
1676
1677 #if 0
1678         if (adev->has_uvd) {
1679                 WREG32(mmUVD_UDEC_ADDR_CONFIG, gb_addr_config);
1680                 WREG32(mmUVD_UDEC_DB_ADDR_CONFIG, gb_addr_config);
1681                 WREG32(mmUVD_UDEC_DBW_ADDR_CONFIG, gb_addr_config);
1682         }
1683 #endif
1684         gfx_v6_0_tiling_mode_table_init(adev);
1685
1686         gfx_v6_0_setup_rb(adev, adev->gfx.config.max_shader_engines,
1687                     adev->gfx.config.max_sh_per_se,
1688                     adev->gfx.config.max_backends_per_se);
1689
1690         gfx_v6_0_setup_spi(adev, adev->gfx.config.max_shader_engines,
1691                      adev->gfx.config.max_sh_per_se,
1692                      adev->gfx.config.max_cu_per_sh);
1693
1694         gfx_v6_0_get_cu_info(adev);
1695
1696         WREG32(mmCP_QUEUE_THRESHOLDS, ((0x16 << CP_QUEUE_THRESHOLDS__ROQ_IB1_START__SHIFT) |
1697                                        (0x2b << CP_QUEUE_THRESHOLDS__ROQ_IB2_START__SHIFT)));
1698         WREG32(mmCP_MEQ_THRESHOLDS, (0x30 << CP_MEQ_THRESHOLDS__MEQ1_START__SHIFT) |
1699                                     (0x60 << CP_MEQ_THRESHOLDS__MEQ2_START__SHIFT));
1700
1701         sx_debug_1 = RREG32(mmSX_DEBUG_1);
1702         WREG32(mmSX_DEBUG_1, sx_debug_1);
1703
1704         WREG32(mmSPI_CONFIG_CNTL_1, (4 << SPI_CONFIG_CNTL_1__VTX_DONE_DELAY__SHIFT));
1705
1706         WREG32(mmPA_SC_FIFO_SIZE, ((adev->gfx.config.sc_prim_fifo_size_frontend << PA_SC_FIFO_SIZE__SC_FRONTEND_PRIM_FIFO_SIZE__SHIFT) |
1707                                    (adev->gfx.config.sc_prim_fifo_size_backend << PA_SC_FIFO_SIZE__SC_BACKEND_PRIM_FIFO_SIZE__SHIFT) |
1708                                    (adev->gfx.config.sc_hiz_tile_fifo_size << PA_SC_FIFO_SIZE__SC_HIZ_TILE_FIFO_SIZE__SHIFT) |
1709                                    (adev->gfx.config.sc_earlyz_tile_fifo_size << PA_SC_FIFO_SIZE__SC_EARLYZ_TILE_FIFO_SIZE__SHIFT)));
1710
1711         WREG32(mmVGT_NUM_INSTANCES, 1);
1712         WREG32(mmCP_PERFMON_CNTL, 0);
1713         WREG32(mmSQ_CONFIG, 0);
1714         WREG32(mmPA_SC_FORCE_EOV_MAX_CNTS, ((4095 << PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_CLK_CNT__SHIFT) |
1715                                           (255 << PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_REZ_CNT__SHIFT)));
1716
1717         WREG32(mmVGT_CACHE_INVALIDATION,
1718                 (VC_AND_TC << VGT_CACHE_INVALIDATION__CACHE_INVALIDATION__SHIFT) |
1719                 (ES_AND_GS_AUTO << VGT_CACHE_INVALIDATION__AUTO_INVLD_EN__SHIFT));
1720
1721         WREG32(mmVGT_GS_VERTEX_REUSE, 16);
1722         WREG32(mmPA_SC_LINE_STIPPLE_STATE, 0);
1723
1724         WREG32(mmCB_PERFCOUNTER0_SELECT0, 0);
1725         WREG32(mmCB_PERFCOUNTER0_SELECT1, 0);
1726         WREG32(mmCB_PERFCOUNTER1_SELECT0, 0);
1727         WREG32(mmCB_PERFCOUNTER1_SELECT1, 0);
1728         WREG32(mmCB_PERFCOUNTER2_SELECT0, 0);
1729         WREG32(mmCB_PERFCOUNTER2_SELECT1, 0);
1730         WREG32(mmCB_PERFCOUNTER3_SELECT0, 0);
1731         WREG32(mmCB_PERFCOUNTER3_SELECT1, 0);
1732
1733         hdp_host_path_cntl = RREG32(mmHDP_HOST_PATH_CNTL);
1734         WREG32(mmHDP_HOST_PATH_CNTL, hdp_host_path_cntl);
1735
1736         WREG32(mmPA_CL_ENHANCE, PA_CL_ENHANCE__CLIP_VTX_REORDER_ENA_MASK |
1737                                 (3 << PA_CL_ENHANCE__NUM_CLIP_SEQ__SHIFT));
1738
1739         udelay(50);
1740 }
1741
1742
1743 static void gfx_v6_0_scratch_init(struct amdgpu_device *adev)
1744 {
1745         int i;
1746
1747         adev->gfx.scratch.num_reg = 7;
1748         adev->gfx.scratch.reg_base = mmSCRATCH_REG0;
1749         for (i = 0; i < adev->gfx.scratch.num_reg; i++) {
1750                 adev->gfx.scratch.free[i] = true;
1751                 adev->gfx.scratch.reg[i] = adev->gfx.scratch.reg_base + i;
1752         }
1753 }
1754
1755 static int gfx_v6_0_ring_test_ring(struct amdgpu_ring *ring)
1756 {
1757         struct amdgpu_device *adev = ring->adev;
1758         uint32_t scratch;
1759         uint32_t tmp = 0;
1760         unsigned i;
1761         int r;
1762
1763         r = amdgpu_gfx_scratch_get(adev, &scratch);
1764         if (r) {
1765                 DRM_ERROR("amdgpu: cp failed to get scratch reg (%d).\n", r);
1766                 return r;
1767         }
1768         WREG32(scratch, 0xCAFEDEAD);
1769
1770         r = amdgpu_ring_alloc(ring, 3);
1771         if (r) {
1772                 DRM_ERROR("amdgpu: cp failed to lock ring %d (%d).\n", ring->idx, r);
1773                 amdgpu_gfx_scratch_free(adev, scratch);
1774                 return r;
1775         }
1776         amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
1777         amdgpu_ring_write(ring, (scratch - PACKET3_SET_CONFIG_REG_START));
1778         amdgpu_ring_write(ring, 0xDEADBEEF);
1779         amdgpu_ring_commit(ring);
1780
1781         for (i = 0; i < adev->usec_timeout; i++) {
1782                 tmp = RREG32(scratch);
1783                 if (tmp == 0xDEADBEEF)
1784                         break;
1785                 DRM_UDELAY(1);
1786         }
1787         if (i < adev->usec_timeout) {
1788                 DRM_INFO("ring test on %d succeeded in %d usecs\n", ring->idx, i);
1789         } else {
1790                 DRM_ERROR("amdgpu: ring %d test failed (scratch(0x%04X)=0x%08X)\n",
1791                           ring->idx, scratch, tmp);
1792                 r = -EINVAL;
1793         }
1794         amdgpu_gfx_scratch_free(adev, scratch);
1795         return r;
1796 }
1797
1798 static void gfx_v6_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
1799 {
1800         /* flush hdp cache */
1801         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
1802         amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(1) |
1803                                  WRITE_DATA_DST_SEL(0)));
1804         amdgpu_ring_write(ring, mmHDP_MEM_COHERENCY_FLUSH_CNTL);
1805         amdgpu_ring_write(ring, 0);
1806         amdgpu_ring_write(ring, 0x1);
1807 }
1808
1809 static void gfx_v6_0_ring_emit_vgt_flush(struct amdgpu_ring *ring)
1810 {
1811         amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE, 0));
1812         amdgpu_ring_write(ring, EVENT_TYPE(VGT_FLUSH) |
1813                 EVENT_INDEX(0));
1814 }
1815
1816 /**
1817  * gfx_v6_0_ring_emit_hdp_invalidate - emit an hdp invalidate on the cp
1818  *
1819  * @adev: amdgpu_device pointer
1820  * @ridx: amdgpu ring index
1821  *
1822  * Emits an hdp invalidate on the cp.
1823  */
1824 static void gfx_v6_0_ring_emit_hdp_invalidate(struct amdgpu_ring *ring)
1825 {
1826         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
1827         amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(1) |
1828                                  WRITE_DATA_DST_SEL(0)));
1829         amdgpu_ring_write(ring, mmHDP_DEBUG0);
1830         amdgpu_ring_write(ring, 0);
1831         amdgpu_ring_write(ring, 0x1);
1832 }
1833
1834 static void gfx_v6_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr,
1835                                      u64 seq, unsigned flags)
1836 {
1837         bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
1838         bool int_sel = flags & AMDGPU_FENCE_FLAG_INT;
1839         /* flush read cache over gart */
1840         amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
1841         amdgpu_ring_write(ring, (mmCP_COHER_CNTL2 - PACKET3_SET_CONFIG_REG_START));
1842         amdgpu_ring_write(ring, 0);
1843         amdgpu_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3));
1844         amdgpu_ring_write(ring, PACKET3_TCL1_ACTION_ENA |
1845                           PACKET3_TC_ACTION_ENA |
1846                           PACKET3_SH_KCACHE_ACTION_ENA |
1847                           PACKET3_SH_ICACHE_ACTION_ENA);
1848         amdgpu_ring_write(ring, 0xFFFFFFFF);
1849         amdgpu_ring_write(ring, 0);
1850         amdgpu_ring_write(ring, 10); /* poll interval */
1851         /* EVENT_WRITE_EOP - flush caches, send int */
1852         amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4));
1853         amdgpu_ring_write(ring, EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) | EVENT_INDEX(5));
1854         amdgpu_ring_write(ring, addr & 0xfffffffc);
1855         amdgpu_ring_write(ring, (upper_32_bits(addr) & 0xffff) |
1856                                 ((write64bit ? 2 : 1) << CP_EOP_DONE_DATA_CNTL__DATA_SEL__SHIFT) |
1857                                 ((int_sel ? 2 : 0) << CP_EOP_DONE_DATA_CNTL__INT_SEL__SHIFT));
1858         amdgpu_ring_write(ring, lower_32_bits(seq));
1859         amdgpu_ring_write(ring, upper_32_bits(seq));
1860 }
1861
1862 static void gfx_v6_0_ring_emit_ib(struct amdgpu_ring *ring,
1863                                   struct amdgpu_ib *ib,
1864                                   unsigned vm_id, bool ctx_switch)
1865 {
1866         u32 header, control = 0;
1867
1868         /* insert SWITCH_BUFFER packet before first IB in the ring frame */
1869         if (ctx_switch) {
1870                 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
1871                 amdgpu_ring_write(ring, 0);
1872         }
1873
1874         if (ib->flags & AMDGPU_IB_FLAG_CE)
1875                 header = PACKET3(PACKET3_INDIRECT_BUFFER_CONST, 2);
1876         else
1877                 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2);
1878
1879         control |= ib->length_dw | (vm_id << 24);
1880
1881         amdgpu_ring_write(ring, header);
1882         amdgpu_ring_write(ring,
1883 #ifdef __BIG_ENDIAN
1884                           (2 << 0) |
1885 #endif
1886                           (ib->gpu_addr & 0xFFFFFFFC));
1887         amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFFFF);
1888         amdgpu_ring_write(ring, control);
1889 }
1890
1891 /**
1892  * gfx_v6_0_ring_test_ib - basic ring IB test
1893  *
1894  * @ring: amdgpu_ring structure holding ring information
1895  *
1896  * Allocate an IB and execute it on the gfx ring (SI).
1897  * Provides a basic gfx ring test to verify that IBs are working.
1898  * Returns 0 on success, error on failure.
1899  */
1900 static int gfx_v6_0_ring_test_ib(struct amdgpu_ring *ring, long timeout)
1901 {
1902         struct amdgpu_device *adev = ring->adev;
1903         struct amdgpu_ib ib;
1904         struct dma_fence *f = NULL;
1905         uint32_t scratch;
1906         uint32_t tmp = 0;
1907         long r;
1908
1909         r = amdgpu_gfx_scratch_get(adev, &scratch);
1910         if (r) {
1911                 DRM_ERROR("amdgpu: failed to get scratch reg (%ld).\n", r);
1912                 return r;
1913         }
1914         WREG32(scratch, 0xCAFEDEAD);
1915         memset(&ib, 0, sizeof(ib));
1916         r = amdgpu_ib_get(adev, NULL, 256, &ib);
1917         if (r) {
1918                 DRM_ERROR("amdgpu: failed to get ib (%ld).\n", r);
1919                 goto err1;
1920         }
1921         ib.ptr[0] = PACKET3(PACKET3_SET_CONFIG_REG, 1);
1922         ib.ptr[1] = ((scratch - PACKET3_SET_CONFIG_REG_START));
1923         ib.ptr[2] = 0xDEADBEEF;
1924         ib.length_dw = 3;
1925
1926         r = amdgpu_ib_schedule(ring, 1, &ib, NULL, NULL, &f);
1927         if (r)
1928                 goto err2;
1929
1930         r = dma_fence_wait_timeout(f, false, timeout);
1931         if (r == 0) {
1932                 DRM_ERROR("amdgpu: IB test timed out\n");
1933                 r = -ETIMEDOUT;
1934                 goto err2;
1935         } else if (r < 0) {
1936                 DRM_ERROR("amdgpu: fence wait failed (%ld).\n", r);
1937                 goto err2;
1938         }
1939         tmp = RREG32(scratch);
1940         if (tmp == 0xDEADBEEF) {
1941                 DRM_INFO("ib test on ring %d succeeded\n", ring->idx);
1942                 r = 0;
1943         } else {
1944                 DRM_ERROR("amdgpu: ib test failed (scratch(0x%04X)=0x%08X)\n",
1945                           scratch, tmp);
1946                 r = -EINVAL;
1947         }
1948
1949 err2:
1950         amdgpu_ib_free(adev, &ib, NULL);
1951         dma_fence_put(f);
1952 err1:
1953         amdgpu_gfx_scratch_free(adev, scratch);
1954         return r;
1955 }
1956
1957 static void gfx_v6_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable)
1958 {
1959         int i;
1960         if (enable) {
1961                 WREG32(mmCP_ME_CNTL, 0);
1962         } else {
1963                 WREG32(mmCP_ME_CNTL, (CP_ME_CNTL__ME_HALT_MASK |
1964                                       CP_ME_CNTL__PFP_HALT_MASK |
1965                                       CP_ME_CNTL__CE_HALT_MASK));
1966                 WREG32(mmSCRATCH_UMSK, 0);
1967                 for (i = 0; i < adev->gfx.num_gfx_rings; i++)
1968                         adev->gfx.gfx_ring[i].ready = false;
1969                 for (i = 0; i < adev->gfx.num_compute_rings; i++)
1970                         adev->gfx.compute_ring[i].ready = false;
1971         }
1972         udelay(50);
1973 }
1974
1975 static int gfx_v6_0_cp_gfx_load_microcode(struct amdgpu_device *adev)
1976 {
1977         unsigned i;
1978         const struct gfx_firmware_header_v1_0 *pfp_hdr;
1979         const struct gfx_firmware_header_v1_0 *ce_hdr;
1980         const struct gfx_firmware_header_v1_0 *me_hdr;
1981         const __le32 *fw_data;
1982         u32 fw_size;
1983
1984         if (!adev->gfx.me_fw || !adev->gfx.pfp_fw || !adev->gfx.ce_fw)
1985                 return -EINVAL;
1986
1987         gfx_v6_0_cp_gfx_enable(adev, false);
1988         pfp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data;
1989         ce_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data;
1990         me_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data;
1991
1992         amdgpu_ucode_print_gfx_hdr(&pfp_hdr->header);
1993         amdgpu_ucode_print_gfx_hdr(&ce_hdr->header);
1994         amdgpu_ucode_print_gfx_hdr(&me_hdr->header);
1995
1996         /* PFP */
1997         fw_data = (const __le32 *)
1998                 (adev->gfx.pfp_fw->data + le32_to_cpu(pfp_hdr->header.ucode_array_offset_bytes));
1999         fw_size = le32_to_cpu(pfp_hdr->header.ucode_size_bytes) / 4;
2000         WREG32(mmCP_PFP_UCODE_ADDR, 0);
2001         for (i = 0; i < fw_size; i++)
2002                 WREG32(mmCP_PFP_UCODE_DATA, le32_to_cpup(fw_data++));
2003         WREG32(mmCP_PFP_UCODE_ADDR, 0);
2004
2005         /* CE */
2006         fw_data = (const __le32 *)
2007                 (adev->gfx.ce_fw->data + le32_to_cpu(ce_hdr->header.ucode_array_offset_bytes));
2008         fw_size = le32_to_cpu(ce_hdr->header.ucode_size_bytes) / 4;
2009         WREG32(mmCP_CE_UCODE_ADDR, 0);
2010         for (i = 0; i < fw_size; i++)
2011                 WREG32(mmCP_CE_UCODE_DATA, le32_to_cpup(fw_data++));
2012         WREG32(mmCP_CE_UCODE_ADDR, 0);
2013
2014         /* ME */
2015         fw_data = (const __be32 *)
2016                 (adev->gfx.me_fw->data + le32_to_cpu(me_hdr->header.ucode_array_offset_bytes));
2017         fw_size = le32_to_cpu(me_hdr->header.ucode_size_bytes) / 4;
2018         WREG32(mmCP_ME_RAM_WADDR, 0);
2019         for (i = 0; i < fw_size; i++)
2020                 WREG32(mmCP_ME_RAM_DATA, le32_to_cpup(fw_data++));
2021         WREG32(mmCP_ME_RAM_WADDR, 0);
2022
2023         WREG32(mmCP_PFP_UCODE_ADDR, 0);
2024         WREG32(mmCP_CE_UCODE_ADDR, 0);
2025         WREG32(mmCP_ME_RAM_WADDR, 0);
2026         WREG32(mmCP_ME_RAM_RADDR, 0);
2027         return 0;
2028 }
2029
2030 static int gfx_v6_0_cp_gfx_start(struct amdgpu_device *adev)
2031 {
2032         const struct cs_section_def *sect = NULL;
2033         const struct cs_extent_def *ext = NULL;
2034         struct amdgpu_ring *ring = &adev->gfx.gfx_ring[0];
2035         int r, i;
2036
2037         r = amdgpu_ring_alloc(ring, 7 + 4);
2038         if (r) {
2039                 DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r);
2040                 return r;
2041         }
2042         amdgpu_ring_write(ring, PACKET3(PACKET3_ME_INITIALIZE, 5));
2043         amdgpu_ring_write(ring, 0x1);
2044         amdgpu_ring_write(ring, 0x0);
2045         amdgpu_ring_write(ring, adev->gfx.config.max_hw_contexts - 1);
2046         amdgpu_ring_write(ring, PACKET3_ME_INITIALIZE_DEVICE_ID(1));
2047         amdgpu_ring_write(ring, 0);
2048         amdgpu_ring_write(ring, 0);
2049
2050         amdgpu_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2));
2051         amdgpu_ring_write(ring, PACKET3_BASE_INDEX(CE_PARTITION_BASE));
2052         amdgpu_ring_write(ring, 0xc000);
2053         amdgpu_ring_write(ring, 0xe000);
2054         amdgpu_ring_commit(ring);
2055
2056         gfx_v6_0_cp_gfx_enable(adev, true);
2057
2058         r = amdgpu_ring_alloc(ring, gfx_v6_0_get_csb_size(adev) + 10);
2059         if (r) {
2060                 DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r);
2061                 return r;
2062         }
2063
2064         amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
2065         amdgpu_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
2066
2067         for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) {
2068                 for (ext = sect->section; ext->extent != NULL; ++ext) {
2069                         if (sect->id == SECT_CONTEXT) {
2070                                 amdgpu_ring_write(ring,
2071                                                   PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count));
2072                                 amdgpu_ring_write(ring, ext->reg_index - PACKET3_SET_CONTEXT_REG_START);
2073                                 for (i = 0; i < ext->reg_count; i++)
2074                                         amdgpu_ring_write(ring, ext->extent[i]);
2075                         }
2076                 }
2077         }
2078
2079         amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
2080         amdgpu_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE);
2081
2082         amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));
2083         amdgpu_ring_write(ring, 0);
2084
2085         amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 2));
2086         amdgpu_ring_write(ring, 0x00000316);
2087         amdgpu_ring_write(ring, 0x0000000e);
2088         amdgpu_ring_write(ring, 0x00000010);
2089
2090         amdgpu_ring_commit(ring);
2091
2092         return 0;
2093 }
2094
2095 static int gfx_v6_0_cp_gfx_resume(struct amdgpu_device *adev)
2096 {
2097         struct amdgpu_ring *ring;
2098         u32 tmp;
2099         u32 rb_bufsz;
2100         int r;
2101         u64 rptr_addr;
2102
2103         WREG32(mmCP_SEM_WAIT_TIMER, 0x0);
2104         WREG32(mmCP_SEM_INCOMPLETE_TIMER_CNTL, 0x0);
2105
2106         /* Set the write pointer delay */
2107         WREG32(mmCP_RB_WPTR_DELAY, 0);
2108
2109         WREG32(mmCP_DEBUG, 0);
2110         WREG32(mmSCRATCH_ADDR, 0);
2111
2112         /* ring 0 - compute and gfx */
2113         /* Set ring buffer size */
2114         ring = &adev->gfx.gfx_ring[0];
2115         rb_bufsz = order_base_2(ring->ring_size / 8);
2116         tmp = (order_base_2(AMDGPU_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
2117
2118 #ifdef __BIG_ENDIAN
2119         tmp |= BUF_SWAP_32BIT;
2120 #endif
2121         WREG32(mmCP_RB0_CNTL, tmp);
2122
2123         /* Initialize the ring buffer's read and write pointers */
2124         WREG32(mmCP_RB0_CNTL, tmp | CP_RB0_CNTL__RB_RPTR_WR_ENA_MASK);
2125         ring->wptr = 0;
2126         WREG32(mmCP_RB0_WPTR, ring->wptr);
2127
2128         /* set the wb address whether it's enabled or not */
2129         rptr_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
2130         WREG32(mmCP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr));
2131         WREG32(mmCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 0xFF);
2132
2133         WREG32(mmSCRATCH_UMSK, 0);
2134
2135         mdelay(1);
2136         WREG32(mmCP_RB0_CNTL, tmp);
2137
2138         WREG32(mmCP_RB0_BASE, ring->gpu_addr >> 8);
2139
2140         /* start the rings */
2141         gfx_v6_0_cp_gfx_start(adev);
2142         ring->ready = true;
2143         r = amdgpu_ring_test_ring(ring);
2144         if (r) {
2145                 ring->ready = false;
2146                 return r;
2147         }
2148
2149         return 0;
2150 }
2151
2152 static u32 gfx_v6_0_ring_get_rptr(struct amdgpu_ring *ring)
2153 {
2154         return ring->adev->wb.wb[ring->rptr_offs];
2155 }
2156
2157 static u32 gfx_v6_0_ring_get_wptr(struct amdgpu_ring *ring)
2158 {
2159         struct amdgpu_device *adev = ring->adev;
2160
2161         if (ring == &adev->gfx.gfx_ring[0])
2162                 return RREG32(mmCP_RB0_WPTR);
2163         else if (ring == &adev->gfx.compute_ring[0])
2164                 return RREG32(mmCP_RB1_WPTR);
2165         else if (ring == &adev->gfx.compute_ring[1])
2166                 return RREG32(mmCP_RB2_WPTR);
2167         else
2168                 BUG();
2169 }
2170
2171 static void gfx_v6_0_ring_set_wptr_gfx(struct amdgpu_ring *ring)
2172 {
2173         struct amdgpu_device *adev = ring->adev;
2174
2175         WREG32(mmCP_RB0_WPTR, ring->wptr);
2176         (void)RREG32(mmCP_RB0_WPTR);
2177 }
2178
2179 static void gfx_v6_0_ring_set_wptr_compute(struct amdgpu_ring *ring)
2180 {
2181         struct amdgpu_device *adev = ring->adev;
2182
2183         if (ring == &adev->gfx.compute_ring[0]) {
2184                 WREG32(mmCP_RB1_WPTR, ring->wptr);
2185                 (void)RREG32(mmCP_RB1_WPTR);
2186         } else if (ring == &adev->gfx.compute_ring[1]) {
2187                 WREG32(mmCP_RB2_WPTR, ring->wptr);
2188                 (void)RREG32(mmCP_RB2_WPTR);
2189         } else {
2190                 BUG();
2191         }
2192
2193 }
2194
2195 static int gfx_v6_0_cp_compute_resume(struct amdgpu_device *adev)
2196 {
2197         struct amdgpu_ring *ring;
2198         u32 tmp;
2199         u32 rb_bufsz;
2200         int i, r;
2201         u64 rptr_addr;
2202
2203         /* ring1  - compute only */
2204         /* Set ring buffer size */
2205
2206         ring = &adev->gfx.compute_ring[0];
2207         rb_bufsz = order_base_2(ring->ring_size / 8);
2208         tmp = (order_base_2(AMDGPU_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
2209 #ifdef __BIG_ENDIAN
2210         tmp |= BUF_SWAP_32BIT;
2211 #endif
2212         WREG32(mmCP_RB1_CNTL, tmp);
2213
2214         WREG32(mmCP_RB1_CNTL, tmp | CP_RB1_CNTL__RB_RPTR_WR_ENA_MASK);
2215         ring->wptr = 0;
2216         WREG32(mmCP_RB1_WPTR, ring->wptr);
2217
2218         rptr_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
2219         WREG32(mmCP_RB1_RPTR_ADDR, lower_32_bits(rptr_addr));
2220         WREG32(mmCP_RB1_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 0xFF);
2221
2222         mdelay(1);
2223         WREG32(mmCP_RB1_CNTL, tmp);
2224         WREG32(mmCP_RB1_BASE, ring->gpu_addr >> 8);
2225
2226         ring = &adev->gfx.compute_ring[1];
2227         rb_bufsz = order_base_2(ring->ring_size / 8);
2228         tmp = (order_base_2(AMDGPU_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
2229 #ifdef __BIG_ENDIAN
2230         tmp |= BUF_SWAP_32BIT;
2231 #endif
2232         WREG32(mmCP_RB2_CNTL, tmp);
2233
2234         WREG32(mmCP_RB2_CNTL, tmp | CP_RB2_CNTL__RB_RPTR_WR_ENA_MASK);
2235         ring->wptr = 0;
2236         WREG32(mmCP_RB2_WPTR, ring->wptr);
2237         rptr_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
2238         WREG32(mmCP_RB2_RPTR_ADDR, lower_32_bits(rptr_addr));
2239         WREG32(mmCP_RB2_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 0xFF);
2240
2241         mdelay(1);
2242         WREG32(mmCP_RB2_CNTL, tmp);
2243         WREG32(mmCP_RB2_BASE, ring->gpu_addr >> 8);
2244
2245         adev->gfx.compute_ring[0].ready = false;
2246         adev->gfx.compute_ring[1].ready = false;
2247
2248         for (i = 0; i < 2; i++) {
2249                 r = amdgpu_ring_test_ring(&adev->gfx.compute_ring[i]);
2250                 if (r)
2251                         return r;
2252                 adev->gfx.compute_ring[i].ready = true;
2253         }
2254
2255         return 0;
2256 }
2257
2258 static void gfx_v6_0_cp_enable(struct amdgpu_device *adev, bool enable)
2259 {
2260         gfx_v6_0_cp_gfx_enable(adev, enable);
2261 }
2262
2263 static int gfx_v6_0_cp_load_microcode(struct amdgpu_device *adev)
2264 {
2265         return gfx_v6_0_cp_gfx_load_microcode(adev);
2266 }
2267
2268 static void gfx_v6_0_enable_gui_idle_interrupt(struct amdgpu_device *adev,
2269                                                bool enable)
2270 {
2271         u32 tmp = RREG32(mmCP_INT_CNTL_RING0);
2272         u32 mask;
2273         int i;
2274
2275         if (enable)
2276                 tmp |= (CP_INT_CNTL__CNTX_BUSY_INT_ENABLE_MASK |
2277                         CP_INT_CNTL__CNTX_EMPTY_INT_ENABLE_MASK);
2278         else
2279                 tmp &= ~(CP_INT_CNTL__CNTX_BUSY_INT_ENABLE_MASK |
2280                          CP_INT_CNTL__CNTX_EMPTY_INT_ENABLE_MASK);
2281         WREG32(mmCP_INT_CNTL_RING0, tmp);
2282
2283         if (!enable) {
2284                 /* read a gfx register */
2285                 tmp = RREG32(mmDB_DEPTH_INFO);
2286
2287                 mask = RLC_BUSY_STATUS | GFX_POWER_STATUS | GFX_CLOCK_STATUS | GFX_LS_STATUS;
2288                 for (i = 0; i < adev->usec_timeout; i++) {
2289                         if ((RREG32(mmRLC_STAT) & mask) == (GFX_CLOCK_STATUS | GFX_POWER_STATUS))
2290                                 break;
2291                         udelay(1);
2292                 }
2293         }
2294 }
2295
2296 static int gfx_v6_0_cp_resume(struct amdgpu_device *adev)
2297 {
2298         int r;
2299
2300         gfx_v6_0_enable_gui_idle_interrupt(adev, false);
2301
2302         r = gfx_v6_0_cp_load_microcode(adev);
2303         if (r)
2304                 return r;
2305
2306         r = gfx_v6_0_cp_gfx_resume(adev);
2307         if (r)
2308                 return r;
2309         r = gfx_v6_0_cp_compute_resume(adev);
2310         if (r)
2311                 return r;
2312
2313         gfx_v6_0_enable_gui_idle_interrupt(adev, true);
2314
2315         return 0;
2316 }
2317
2318 static void gfx_v6_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
2319 {
2320         int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
2321         uint32_t seq = ring->fence_drv.sync_seq;
2322         uint64_t addr = ring->fence_drv.gpu_addr;
2323
2324         amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
2325         amdgpu_ring_write(ring, (WAIT_REG_MEM_MEM_SPACE(1) | /* memory */
2326                                  WAIT_REG_MEM_FUNCTION(3) | /* equal */
2327                                  WAIT_REG_MEM_ENGINE(usepfp)));   /* pfp or me */
2328         amdgpu_ring_write(ring, addr & 0xfffffffc);
2329         amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff);
2330         amdgpu_ring_write(ring, seq);
2331         amdgpu_ring_write(ring, 0xffffffff);
2332         amdgpu_ring_write(ring, 4); /* poll interval */
2333
2334         if (usepfp) {
2335                 /* synce CE with ME to prevent CE fetch CEIB before context switch done */
2336                 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
2337                 amdgpu_ring_write(ring, 0);
2338                 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
2339                 amdgpu_ring_write(ring, 0);
2340         }
2341 }
2342
2343 static void gfx_v6_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
2344                                         unsigned vm_id, uint64_t pd_addr)
2345 {
2346         int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
2347
2348         /* write new base address */
2349         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
2350         amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(1) |
2351                                  WRITE_DATA_DST_SEL(0)));
2352         if (vm_id < 8) {
2353                 amdgpu_ring_write(ring, (mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + vm_id ));
2354         } else {
2355                 amdgpu_ring_write(ring, (mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + (vm_id - 8)));
2356         }
2357         amdgpu_ring_write(ring, 0);
2358         amdgpu_ring_write(ring, pd_addr >> 12);
2359
2360         /* bits 0-15 are the VM contexts0-15 */
2361         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
2362         amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(1) |
2363                                  WRITE_DATA_DST_SEL(0)));
2364         amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST);
2365         amdgpu_ring_write(ring, 0);
2366         amdgpu_ring_write(ring, 1 << vm_id);
2367
2368         /* wait for the invalidate to complete */
2369         amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
2370         amdgpu_ring_write(ring, (WAIT_REG_MEM_FUNCTION(0) |  /* always */
2371                                  WAIT_REG_MEM_ENGINE(0))); /* me */
2372         amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST);
2373         amdgpu_ring_write(ring, 0);
2374         amdgpu_ring_write(ring, 0); /* ref */
2375         amdgpu_ring_write(ring, 0); /* mask */
2376         amdgpu_ring_write(ring, 0x20); /* poll interval */
2377
2378         if (usepfp) {
2379                 /* sync PFP to ME, otherwise we might get invalid PFP reads */
2380                 amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0));
2381                 amdgpu_ring_write(ring, 0x0);
2382
2383                 /* synce CE with ME to prevent CE fetch CEIB before context switch done */
2384                 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
2385                 amdgpu_ring_write(ring, 0);
2386                 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
2387                 amdgpu_ring_write(ring, 0);
2388         }
2389 }
2390
2391
2392 static void gfx_v6_0_rlc_fini(struct amdgpu_device *adev)
2393 {
2394         int r;
2395
2396         if (adev->gfx.rlc.save_restore_obj) {
2397                 r = amdgpu_bo_reserve(adev->gfx.rlc.save_restore_obj, false);
2398                 if (unlikely(r != 0))
2399                         dev_warn(adev->dev, "(%d) reserve RLC sr bo failed\n", r);
2400                 amdgpu_bo_unpin(adev->gfx.rlc.save_restore_obj);
2401                 amdgpu_bo_unreserve(adev->gfx.rlc.save_restore_obj);
2402
2403                 amdgpu_bo_unref(&adev->gfx.rlc.save_restore_obj);
2404                 adev->gfx.rlc.save_restore_obj = NULL;
2405         }
2406
2407         if (adev->gfx.rlc.clear_state_obj) {
2408                 r = amdgpu_bo_reserve(adev->gfx.rlc.clear_state_obj, false);
2409                 if (unlikely(r != 0))
2410                         dev_warn(adev->dev, "(%d) reserve RLC c bo failed\n", r);
2411                 amdgpu_bo_unpin(adev->gfx.rlc.clear_state_obj);
2412                 amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj);
2413
2414                 amdgpu_bo_unref(&adev->gfx.rlc.clear_state_obj);
2415                 adev->gfx.rlc.clear_state_obj = NULL;
2416         }
2417
2418         if (adev->gfx.rlc.cp_table_obj) {
2419                 r = amdgpu_bo_reserve(adev->gfx.rlc.cp_table_obj, false);
2420                 if (unlikely(r != 0))
2421                         dev_warn(adev->dev, "(%d) reserve RLC cp table bo failed\n", r);
2422                 amdgpu_bo_unpin(adev->gfx.rlc.cp_table_obj);
2423                 amdgpu_bo_unreserve(adev->gfx.rlc.cp_table_obj);
2424
2425                 amdgpu_bo_unref(&adev->gfx.rlc.cp_table_obj);
2426                 adev->gfx.rlc.cp_table_obj = NULL;
2427         }
2428 }
2429
2430 static int gfx_v6_0_rlc_init(struct amdgpu_device *adev)
2431 {
2432         const u32 *src_ptr;
2433         volatile u32 *dst_ptr;
2434         u32 dws, i;
2435         u64 reg_list_mc_addr;
2436         const struct cs_section_def *cs_data;
2437         int r;
2438
2439         adev->gfx.rlc.reg_list = verde_rlc_save_restore_register_list;
2440         adev->gfx.rlc.reg_list_size =
2441                         (u32)ARRAY_SIZE(verde_rlc_save_restore_register_list);
2442
2443         adev->gfx.rlc.cs_data = si_cs_data;
2444         src_ptr = adev->gfx.rlc.reg_list;
2445         dws = adev->gfx.rlc.reg_list_size;
2446         cs_data = adev->gfx.rlc.cs_data;
2447
2448         if (src_ptr) {
2449                 /* save restore block */
2450                 if (adev->gfx.rlc.save_restore_obj == NULL) {
2451                         r = amdgpu_bo_create(adev, dws * 4, PAGE_SIZE, true,
2452                                              AMDGPU_GEM_DOMAIN_VRAM,
2453                                              AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED,
2454                                              NULL, NULL,
2455                                              &adev->gfx.rlc.save_restore_obj);
2456
2457                         if (r) {
2458                                 dev_warn(adev->dev, "(%d) create RLC sr bo failed\n", r);
2459                                 return r;
2460                         }
2461                 }
2462
2463                 r = amdgpu_bo_reserve(adev->gfx.rlc.save_restore_obj, false);
2464                 if (unlikely(r != 0)) {
2465                         gfx_v6_0_rlc_fini(adev);
2466                         return r;
2467                 }
2468                 r = amdgpu_bo_pin(adev->gfx.rlc.save_restore_obj, AMDGPU_GEM_DOMAIN_VRAM,
2469                                   &adev->gfx.rlc.save_restore_gpu_addr);
2470                 if (r) {
2471                         amdgpu_bo_unreserve(adev->gfx.rlc.save_restore_obj);
2472                         dev_warn(adev->dev, "(%d) pin RLC sr bo failed\n", r);
2473                         gfx_v6_0_rlc_fini(adev);
2474                         return r;
2475                 }
2476
2477                 r = amdgpu_bo_kmap(adev->gfx.rlc.save_restore_obj, (void **)&adev->gfx.rlc.sr_ptr);
2478                 if (r) {
2479                         dev_warn(adev->dev, "(%d) map RLC sr bo failed\n", r);
2480                         gfx_v6_0_rlc_fini(adev);
2481                         return r;
2482                 }
2483                 /* write the sr buffer */
2484                 dst_ptr = adev->gfx.rlc.sr_ptr;
2485                 for (i = 0; i < adev->gfx.rlc.reg_list_size; i++)
2486                         dst_ptr[i] = cpu_to_le32(src_ptr[i]);
2487                 amdgpu_bo_kunmap(adev->gfx.rlc.save_restore_obj);
2488                 amdgpu_bo_unreserve(adev->gfx.rlc.save_restore_obj);
2489         }
2490
2491         if (cs_data) {
2492                 /* clear state block */
2493                 adev->gfx.rlc.clear_state_size = gfx_v6_0_get_csb_size(adev);
2494                 dws = adev->gfx.rlc.clear_state_size + (256 / 4);
2495
2496                 if (adev->gfx.rlc.clear_state_obj == NULL) {
2497                         r = amdgpu_bo_create(adev, dws * 4, PAGE_SIZE, true,
2498                                              AMDGPU_GEM_DOMAIN_VRAM,
2499                                              AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED,
2500                                              NULL, NULL,
2501                                              &adev->gfx.rlc.clear_state_obj);
2502
2503                         if (r) {
2504                                 dev_warn(adev->dev, "(%d) create RLC c bo failed\n", r);
2505                                 gfx_v6_0_rlc_fini(adev);
2506                                 return r;
2507                         }
2508                 }
2509                 r = amdgpu_bo_reserve(adev->gfx.rlc.clear_state_obj, false);
2510                 if (unlikely(r != 0)) {
2511                         gfx_v6_0_rlc_fini(adev);
2512                         return r;
2513                 }
2514                 r = amdgpu_bo_pin(adev->gfx.rlc.clear_state_obj, AMDGPU_GEM_DOMAIN_VRAM,
2515                                   &adev->gfx.rlc.clear_state_gpu_addr);
2516                 if (r) {
2517                         amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj);
2518                         dev_warn(adev->dev, "(%d) pin RLC c bo failed\n", r);
2519                         gfx_v6_0_rlc_fini(adev);
2520                         return r;
2521                 }
2522
2523                 r = amdgpu_bo_kmap(adev->gfx.rlc.clear_state_obj, (void **)&adev->gfx.rlc.cs_ptr);
2524                 if (r) {
2525                         dev_warn(adev->dev, "(%d) map RLC c bo failed\n", r);
2526                         gfx_v6_0_rlc_fini(adev);
2527                         return r;
2528                 }
2529                 /* set up the cs buffer */
2530                 dst_ptr = adev->gfx.rlc.cs_ptr;
2531                 reg_list_mc_addr = adev->gfx.rlc.clear_state_gpu_addr + 256;
2532                 dst_ptr[0] = cpu_to_le32(upper_32_bits(reg_list_mc_addr));
2533                 dst_ptr[1] = cpu_to_le32(lower_32_bits(reg_list_mc_addr));
2534                 dst_ptr[2] = cpu_to_le32(adev->gfx.rlc.clear_state_size);
2535                 gfx_v6_0_get_csb_buffer(adev, &dst_ptr[(256/4)]);
2536                 amdgpu_bo_kunmap(adev->gfx.rlc.clear_state_obj);
2537                 amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj);
2538         }
2539
2540         return 0;
2541 }
2542
2543 static void gfx_v6_0_enable_lbpw(struct amdgpu_device *adev, bool enable)
2544 {
2545         WREG32_FIELD(RLC_LB_CNTL, LOAD_BALANCE_ENABLE, enable ? 1 : 0);
2546
2547         if (!enable) {
2548                 gfx_v6_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
2549                 WREG32(mmSPI_LB_CU_MASK, 0x00ff);
2550         }
2551 }
2552
2553 static void gfx_v6_0_wait_for_rlc_serdes(struct amdgpu_device *adev)
2554 {
2555         int i;
2556
2557         for (i = 0; i < adev->usec_timeout; i++) {
2558                 if (RREG32(mmRLC_SERDES_MASTER_BUSY_0) == 0)
2559                         break;
2560                 udelay(1);
2561         }
2562
2563         for (i = 0; i < adev->usec_timeout; i++) {
2564                 if (RREG32(mmRLC_SERDES_MASTER_BUSY_1) == 0)
2565                         break;
2566                 udelay(1);
2567         }
2568 }
2569
2570 static void gfx_v6_0_update_rlc(struct amdgpu_device *adev, u32 rlc)
2571 {
2572         u32 tmp;
2573
2574         tmp = RREG32(mmRLC_CNTL);
2575         if (tmp != rlc)
2576                 WREG32(mmRLC_CNTL, rlc);
2577 }
2578
2579 static u32 gfx_v6_0_halt_rlc(struct amdgpu_device *adev)
2580 {
2581         u32 data, orig;
2582
2583         orig = data = RREG32(mmRLC_CNTL);
2584
2585         if (data & RLC_CNTL__RLC_ENABLE_F32_MASK) {
2586                 data &= ~RLC_CNTL__RLC_ENABLE_F32_MASK;
2587                 WREG32(mmRLC_CNTL, data);
2588
2589                 gfx_v6_0_wait_for_rlc_serdes(adev);
2590         }
2591
2592         return orig;
2593 }
2594
2595 static void gfx_v6_0_rlc_stop(struct amdgpu_device *adev)
2596 {
2597         WREG32(mmRLC_CNTL, 0);
2598
2599         gfx_v6_0_enable_gui_idle_interrupt(adev, false);
2600         gfx_v6_0_wait_for_rlc_serdes(adev);
2601 }
2602
2603 static void gfx_v6_0_rlc_start(struct amdgpu_device *adev)
2604 {
2605         WREG32(mmRLC_CNTL, RLC_CNTL__RLC_ENABLE_F32_MASK);
2606
2607         gfx_v6_0_enable_gui_idle_interrupt(adev, true);
2608
2609         udelay(50);
2610 }
2611
2612 static void gfx_v6_0_rlc_reset(struct amdgpu_device *adev)
2613 {
2614         WREG32_FIELD(GRBM_SOFT_RESET, SOFT_RESET_RLC, 1);
2615         udelay(50);
2616         WREG32_FIELD(GRBM_SOFT_RESET, SOFT_RESET_RLC, 0);
2617         udelay(50);
2618 }
2619
2620 static bool gfx_v6_0_lbpw_supported(struct amdgpu_device *adev)
2621 {
2622         u32 tmp;
2623
2624         /* Enable LBPW only for DDR3 */
2625         tmp = RREG32(mmMC_SEQ_MISC0);
2626         if ((tmp & 0xF0000000) == 0xB0000000)
2627                 return true;
2628         return false;
2629 }
2630
2631 static void gfx_v6_0_init_cg(struct amdgpu_device *adev)
2632 {
2633 }
2634
2635 static int gfx_v6_0_rlc_resume(struct amdgpu_device *adev)
2636 {
2637         u32 i;
2638         const struct rlc_firmware_header_v1_0 *hdr;
2639         const __le32 *fw_data;
2640         u32 fw_size;
2641
2642
2643         if (!adev->gfx.rlc_fw)
2644                 return -EINVAL;
2645
2646         gfx_v6_0_rlc_stop(adev);
2647         gfx_v6_0_rlc_reset(adev);
2648         gfx_v6_0_init_pg(adev);
2649         gfx_v6_0_init_cg(adev);
2650
2651         WREG32(mmRLC_RL_BASE, 0);
2652         WREG32(mmRLC_RL_SIZE, 0);
2653         WREG32(mmRLC_LB_CNTL, 0);
2654         WREG32(mmRLC_LB_CNTR_MAX, 0xffffffff);
2655         WREG32(mmRLC_LB_CNTR_INIT, 0);
2656         WREG32(mmRLC_LB_INIT_CU_MASK, 0xffffffff);
2657
2658         WREG32(mmRLC_MC_CNTL, 0);
2659         WREG32(mmRLC_UCODE_CNTL, 0);
2660
2661         hdr = (const struct rlc_firmware_header_v1_0 *)adev->gfx.rlc_fw->data;
2662         fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
2663         fw_data = (const __le32 *)
2664                 (adev->gfx.rlc_fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes));
2665
2666         amdgpu_ucode_print_rlc_hdr(&hdr->header);
2667
2668         for (i = 0; i < fw_size; i++) {
2669                 WREG32(mmRLC_UCODE_ADDR, i);
2670                 WREG32(mmRLC_UCODE_DATA, le32_to_cpup(fw_data++));
2671         }
2672         WREG32(mmRLC_UCODE_ADDR, 0);
2673
2674         gfx_v6_0_enable_lbpw(adev, gfx_v6_0_lbpw_supported(adev));
2675         gfx_v6_0_rlc_start(adev);
2676
2677         return 0;
2678 }
2679
2680 static void gfx_v6_0_enable_cgcg(struct amdgpu_device *adev, bool enable)
2681 {
2682         u32 data, orig, tmp;
2683
2684         orig = data = RREG32(mmRLC_CGCG_CGLS_CTRL);
2685
2686         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)) {
2687                 gfx_v6_0_enable_gui_idle_interrupt(adev, true);
2688
2689                 WREG32(mmRLC_GCPM_GENERAL_3, 0x00000080);
2690
2691                 tmp = gfx_v6_0_halt_rlc(adev);
2692
2693                 WREG32(mmRLC_SERDES_WR_MASTER_MASK_0, 0xffffffff);
2694                 WREG32(mmRLC_SERDES_WR_MASTER_MASK_1, 0xffffffff);
2695                 WREG32(mmRLC_SERDES_WR_CTRL, 0x00b000ff);
2696
2697                 gfx_v6_0_wait_for_rlc_serdes(adev);
2698                 gfx_v6_0_update_rlc(adev, tmp);
2699
2700                 WREG32(mmRLC_SERDES_WR_CTRL, 0x007000ff);
2701
2702                 data |= RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK | RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK;
2703         } else {
2704                 gfx_v6_0_enable_gui_idle_interrupt(adev, false);
2705
2706                 RREG32(mmCB_CGTT_SCLK_CTRL);
2707                 RREG32(mmCB_CGTT_SCLK_CTRL);
2708                 RREG32(mmCB_CGTT_SCLK_CTRL);
2709                 RREG32(mmCB_CGTT_SCLK_CTRL);
2710
2711                 data &= ~(RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK | RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK);
2712         }
2713
2714         if (orig != data)
2715                 WREG32(mmRLC_CGCG_CGLS_CTRL, data);
2716
2717 }
2718
2719 static void gfx_v6_0_enable_mgcg(struct amdgpu_device *adev, bool enable)
2720 {
2721
2722         u32 data, orig, tmp = 0;
2723
2724         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) {
2725                 orig = data = RREG32(mmCGTS_SM_CTRL_REG);
2726                 data = 0x96940200;
2727                 if (orig != data)
2728                         WREG32(mmCGTS_SM_CTRL_REG, data);
2729
2730                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CP_LS) {
2731                         orig = data = RREG32(mmCP_MEM_SLP_CNTL);
2732                         data |= CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK;
2733                         if (orig != data)
2734                                 WREG32(mmCP_MEM_SLP_CNTL, data);
2735                 }
2736
2737                 orig = data = RREG32(mmRLC_CGTT_MGCG_OVERRIDE);
2738                 data &= 0xffffffc0;
2739                 if (orig != data)
2740                         WREG32(mmRLC_CGTT_MGCG_OVERRIDE, data);
2741
2742                 tmp = gfx_v6_0_halt_rlc(adev);
2743
2744                 WREG32(mmRLC_SERDES_WR_MASTER_MASK_0, 0xffffffff);
2745                 WREG32(mmRLC_SERDES_WR_MASTER_MASK_1, 0xffffffff);
2746                 WREG32(mmRLC_SERDES_WR_CTRL, 0x00d000ff);
2747
2748                 gfx_v6_0_update_rlc(adev, tmp);
2749         } else {
2750                 orig = data = RREG32(mmRLC_CGTT_MGCG_OVERRIDE);
2751                 data |= 0x00000003;
2752                 if (orig != data)
2753                         WREG32(mmRLC_CGTT_MGCG_OVERRIDE, data);
2754
2755                 data = RREG32(mmCP_MEM_SLP_CNTL);
2756                 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) {
2757                         data &= ~CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK;
2758                         WREG32(mmCP_MEM_SLP_CNTL, data);
2759                 }
2760                 orig = data = RREG32(mmCGTS_SM_CTRL_REG);
2761                 data |= CGTS_SM_CTRL_REG__LS_OVERRIDE_MASK | CGTS_SM_CTRL_REG__OVERRIDE_MASK;
2762                 if (orig != data)
2763                         WREG32(mmCGTS_SM_CTRL_REG, data);
2764
2765                 tmp = gfx_v6_0_halt_rlc(adev);
2766
2767                 WREG32(mmRLC_SERDES_WR_MASTER_MASK_0, 0xffffffff);
2768                 WREG32(mmRLC_SERDES_WR_MASTER_MASK_1, 0xffffffff);
2769                 WREG32(mmRLC_SERDES_WR_CTRL, 0x00e000ff);
2770
2771                 gfx_v6_0_update_rlc(adev, tmp);
2772         }
2773 }
2774 /*
2775 static void gfx_v6_0_update_cg(struct amdgpu_device *adev,
2776                                bool enable)
2777 {
2778         gfx_v6_0_enable_gui_idle_interrupt(adev, false);
2779         if (enable) {
2780                 gfx_v6_0_enable_mgcg(adev, true);
2781                 gfx_v6_0_enable_cgcg(adev, true);
2782         } else {
2783                 gfx_v6_0_enable_cgcg(adev, false);
2784                 gfx_v6_0_enable_mgcg(adev, false);
2785         }
2786         gfx_v6_0_enable_gui_idle_interrupt(adev, true);
2787 }
2788 */
2789
2790 static void gfx_v6_0_enable_sclk_slowdown_on_pu(struct amdgpu_device *adev,
2791                                                 bool enable)
2792 {
2793 }
2794
2795 static void gfx_v6_0_enable_sclk_slowdown_on_pd(struct amdgpu_device *adev,
2796                                                 bool enable)
2797 {
2798 }
2799
2800 static void gfx_v6_0_enable_cp_pg(struct amdgpu_device *adev, bool enable)
2801 {
2802         u32 data, orig;
2803
2804         orig = data = RREG32(mmRLC_PG_CNTL);
2805         if (enable && (adev->pg_flags & AMD_PG_SUPPORT_CP))
2806                 data &= ~0x8000;
2807         else
2808                 data |= 0x8000;
2809         if (orig != data)
2810                 WREG32(mmRLC_PG_CNTL, data);
2811 }
2812
2813 static void gfx_v6_0_enable_gds_pg(struct amdgpu_device *adev, bool enable)
2814 {
2815 }
2816 /*
2817 static void gfx_v6_0_init_cp_pg_table(struct amdgpu_device *adev)
2818 {
2819         const __le32 *fw_data;
2820         volatile u32 *dst_ptr;
2821         int me, i, max_me = 4;
2822         u32 bo_offset = 0;
2823         u32 table_offset, table_size;
2824
2825         if (adev->asic_type == CHIP_KAVERI)
2826                 max_me = 5;
2827
2828         if (adev->gfx.rlc.cp_table_ptr == NULL)
2829                 return;
2830
2831         dst_ptr = adev->gfx.rlc.cp_table_ptr;
2832         for (me = 0; me < max_me; me++) {
2833                 if (me == 0) {
2834                         const struct gfx_firmware_header_v1_0 *hdr =
2835                                 (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data;
2836                         fw_data = (const __le32 *)
2837                                 (adev->gfx.ce_fw->data +
2838                                  le32_to_cpu(hdr->header.ucode_array_offset_bytes));
2839                         table_offset = le32_to_cpu(hdr->jt_offset);
2840                         table_size = le32_to_cpu(hdr->jt_size);
2841                 } else if (me == 1) {
2842                         const struct gfx_firmware_header_v1_0 *hdr =
2843                                 (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data;
2844                         fw_data = (const __le32 *)
2845                                 (adev->gfx.pfp_fw->data +
2846                                  le32_to_cpu(hdr->header.ucode_array_offset_bytes));
2847                         table_offset = le32_to_cpu(hdr->jt_offset);
2848                         table_size = le32_to_cpu(hdr->jt_size);
2849                 } else if (me == 2) {
2850                         const struct gfx_firmware_header_v1_0 *hdr =
2851                                 (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data;
2852                         fw_data = (const __le32 *)
2853                                 (adev->gfx.me_fw->data +
2854                                  le32_to_cpu(hdr->header.ucode_array_offset_bytes));
2855                         table_offset = le32_to_cpu(hdr->jt_offset);
2856                         table_size = le32_to_cpu(hdr->jt_size);
2857                 } else if (me == 3) {
2858                         const struct gfx_firmware_header_v1_0 *hdr =
2859                                 (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
2860                         fw_data = (const __le32 *)
2861                                 (adev->gfx.mec_fw->data +
2862                                  le32_to_cpu(hdr->header.ucode_array_offset_bytes));
2863                         table_offset = le32_to_cpu(hdr->jt_offset);
2864                         table_size = le32_to_cpu(hdr->jt_size);
2865                 } else {
2866                         const struct gfx_firmware_header_v1_0 *hdr =
2867                                 (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec2_fw->data;
2868                         fw_data = (const __le32 *)
2869                                 (adev->gfx.mec2_fw->data +
2870                                  le32_to_cpu(hdr->header.ucode_array_offset_bytes));
2871                         table_offset = le32_to_cpu(hdr->jt_offset);
2872                         table_size = le32_to_cpu(hdr->jt_size);
2873                 }
2874
2875                 for (i = 0; i < table_size; i ++) {
2876                         dst_ptr[bo_offset + i] =
2877                                 cpu_to_le32(le32_to_cpu(fw_data[table_offset + i]));
2878                 }
2879
2880                 bo_offset += table_size;
2881         }
2882 }
2883 */
2884 static void gfx_v6_0_enable_gfx_cgpg(struct amdgpu_device *adev,
2885                                      bool enable)
2886 {
2887         if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG)) {
2888                 WREG32(mmRLC_TTOP_D, RLC_PUD(0x10) | RLC_PDD(0x10) | RLC_TTPD(0x10) | RLC_MSD(0x10));
2889                 WREG32_FIELD(RLC_PG_CNTL, GFX_POWER_GATING_ENABLE, 1);
2890                 WREG32_FIELD(RLC_AUTO_PG_CTRL, AUTO_PG_EN, 1);
2891         } else {
2892                 WREG32_FIELD(RLC_AUTO_PG_CTRL, AUTO_PG_EN, 0);
2893                 (void)RREG32(mmDB_RENDER_CONTROL);
2894         }
2895 }
2896
2897 static u32 gfx_v6_0_get_cu_active_bitmap(struct amdgpu_device *adev,
2898                                          u32 se, u32 sh)
2899 {
2900
2901         u32 mask = 0, tmp, tmp1;
2902         int i;
2903
2904         mutex_lock(&adev->grbm_idx_mutex);
2905         gfx_v6_0_select_se_sh(adev, se, sh, 0xffffffff);
2906         tmp = RREG32(mmCC_GC_SHADER_ARRAY_CONFIG);
2907         tmp1 = RREG32(mmGC_USER_SHADER_ARRAY_CONFIG);
2908         gfx_v6_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
2909         mutex_unlock(&adev->grbm_idx_mutex);
2910
2911         tmp &= 0xffff0000;
2912
2913         tmp |= tmp1;
2914         tmp >>= 16;
2915
2916         for (i = 0; i < adev->gfx.config.max_cu_per_sh; i ++) {
2917                 mask <<= 1;
2918                 mask |= 1;
2919         }
2920
2921         return (~tmp) & mask;
2922 }
2923
2924 static void gfx_v6_0_init_ao_cu_mask(struct amdgpu_device *adev)
2925 {
2926         u32 i, j, k, active_cu_number = 0;
2927
2928         u32 mask, counter, cu_bitmap;
2929         u32 tmp = 0;
2930
2931         for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
2932                 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
2933                         mask = 1;
2934                         cu_bitmap = 0;
2935                         counter  = 0;
2936                         for (k = 0; k < adev->gfx.config.max_cu_per_sh; k++) {
2937                                 if (gfx_v6_0_get_cu_active_bitmap(adev, i, j) & mask) {
2938                                         if (counter < 2)
2939                                                 cu_bitmap |= mask;
2940                                         counter++;
2941                                 }
2942                                 mask <<= 1;
2943                         }
2944
2945                         active_cu_number += counter;
2946                         tmp |= (cu_bitmap << (i * 16 + j * 8));
2947                 }
2948         }
2949
2950         WREG32(mmRLC_PG_AO_CU_MASK, tmp);
2951         WREG32_FIELD(RLC_MAX_PG_CU, MAX_POWERED_UP_CU, active_cu_number);
2952 }
2953
2954 static void gfx_v6_0_enable_gfx_static_mgpg(struct amdgpu_device *adev,
2955                                             bool enable)
2956 {
2957         u32 data, orig;
2958
2959         orig = data = RREG32(mmRLC_PG_CNTL);
2960         if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_SMG))
2961                 data |= RLC_PG_CNTL__STATIC_PER_CU_PG_ENABLE_MASK;
2962         else
2963                 data &= ~RLC_PG_CNTL__STATIC_PER_CU_PG_ENABLE_MASK;
2964         if (orig != data)
2965                 WREG32(mmRLC_PG_CNTL, data);
2966 }
2967
2968 static void gfx_v6_0_enable_gfx_dynamic_mgpg(struct amdgpu_device *adev,
2969                                              bool enable)
2970 {
2971         u32 data, orig;
2972
2973         orig = data = RREG32(mmRLC_PG_CNTL);
2974         if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_DMG))
2975                 data |= RLC_PG_CNTL__DYN_PER_CU_PG_ENABLE_MASK;
2976         else
2977                 data &= ~RLC_PG_CNTL__DYN_PER_CU_PG_ENABLE_MASK;
2978         if (orig != data)
2979                 WREG32(mmRLC_PG_CNTL, data);
2980 }
2981
2982 static void gfx_v6_0_init_gfx_cgpg(struct amdgpu_device *adev)
2983 {
2984         u32 tmp;
2985
2986         WREG32(mmRLC_SAVE_AND_RESTORE_BASE, adev->gfx.rlc.save_restore_gpu_addr >> 8);
2987         WREG32_FIELD(RLC_PG_CNTL, GFX_POWER_GATING_SRC, 1);
2988         WREG32(mmRLC_CLEAR_STATE_RESTORE_BASE, adev->gfx.rlc.clear_state_gpu_addr >> 8);
2989
2990         tmp = RREG32(mmRLC_AUTO_PG_CTRL);
2991         tmp &= ~RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD_MASK;
2992         tmp |= (0x700 << RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD__SHIFT);
2993         tmp &= ~RLC_AUTO_PG_CTRL__PG_AFTER_GRBM_REG_SAVE_THRESHOLD_MASK;
2994         WREG32(mmRLC_AUTO_PG_CTRL, tmp);
2995 }
2996
2997 static void gfx_v6_0_update_gfx_pg(struct amdgpu_device *adev, bool enable)
2998 {
2999         gfx_v6_0_enable_gfx_cgpg(adev, enable);
3000         gfx_v6_0_enable_gfx_static_mgpg(adev, enable);
3001         gfx_v6_0_enable_gfx_dynamic_mgpg(adev, enable);
3002 }
3003
3004 static u32 gfx_v6_0_get_csb_size(struct amdgpu_device *adev)
3005 {
3006         u32 count = 0;
3007         const struct cs_section_def *sect = NULL;
3008         const struct cs_extent_def *ext = NULL;
3009
3010         if (adev->gfx.rlc.cs_data == NULL)
3011                 return 0;
3012
3013         /* begin clear state */
3014         count += 2;
3015         /* context control state */
3016         count += 3;
3017
3018         for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) {
3019                 for (ext = sect->section; ext->extent != NULL; ++ext) {
3020                         if (sect->id == SECT_CONTEXT)
3021                                 count += 2 + ext->reg_count;
3022                         else
3023                                 return 0;
3024                 }
3025         }
3026         /* pa_sc_raster_config */
3027         count += 3;
3028         /* end clear state */
3029         count += 2;
3030         /* clear state */
3031         count += 2;
3032
3033         return count;
3034 }
3035
3036 static void gfx_v6_0_get_csb_buffer(struct amdgpu_device *adev,
3037                                     volatile u32 *buffer)
3038 {
3039         u32 count = 0, i;
3040         const struct cs_section_def *sect = NULL;
3041         const struct cs_extent_def *ext = NULL;
3042
3043         if (adev->gfx.rlc.cs_data == NULL)
3044                 return;
3045         if (buffer == NULL)
3046                 return;
3047
3048         buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));
3049         buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
3050         buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CONTEXT_CONTROL, 1));
3051         buffer[count++] = cpu_to_le32(0x80000000);
3052         buffer[count++] = cpu_to_le32(0x80000000);
3053
3054         for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) {
3055                 for (ext = sect->section; ext->extent != NULL; ++ext) {
3056                         if (sect->id == SECT_CONTEXT) {
3057                                 buffer[count++] =
3058                                         cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count));
3059                                 buffer[count++] = cpu_to_le32(ext->reg_index - 0xa000);
3060                                 for (i = 0; i < ext->reg_count; i++)
3061                                         buffer[count++] = cpu_to_le32(ext->extent[i]);
3062                         } else {
3063                                 return;
3064                         }
3065                 }
3066         }
3067
3068         buffer[count++] = cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, 1));
3069         buffer[count++] = cpu_to_le32(mmPA_SC_RASTER_CONFIG - PACKET3_SET_CONTEXT_REG_START);
3070
3071         switch (adev->asic_type) {
3072         case CHIP_TAHITI:
3073         case CHIP_PITCAIRN:
3074                 buffer[count++] = cpu_to_le32(0x2a00126a);
3075                 break;
3076         case CHIP_VERDE:
3077                 buffer[count++] = cpu_to_le32(0x0000124a);
3078                 break;
3079         case CHIP_OLAND:
3080                 buffer[count++] = cpu_to_le32(0x00000082);
3081                 break;
3082         case CHIP_HAINAN:
3083                 buffer[count++] = cpu_to_le32(0x00000000);
3084                 break;
3085         default:
3086                 buffer[count++] = cpu_to_le32(0x00000000);
3087                 break;
3088         }
3089
3090         buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));
3091         buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_END_CLEAR_STATE);
3092
3093         buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CLEAR_STATE, 0));
3094         buffer[count++] = cpu_to_le32(0);
3095 }
3096
3097 static void gfx_v6_0_init_pg(struct amdgpu_device *adev)
3098 {
3099         if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG |
3100                               AMD_PG_SUPPORT_GFX_SMG |
3101                               AMD_PG_SUPPORT_GFX_DMG |
3102                               AMD_PG_SUPPORT_CP |
3103                               AMD_PG_SUPPORT_GDS |
3104                               AMD_PG_SUPPORT_RLC_SMU_HS)) {
3105                 gfx_v6_0_enable_sclk_slowdown_on_pu(adev, true);
3106                 gfx_v6_0_enable_sclk_slowdown_on_pd(adev, true);
3107                 if (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG) {
3108                         gfx_v6_0_init_gfx_cgpg(adev);
3109                         gfx_v6_0_enable_cp_pg(adev, true);
3110                         gfx_v6_0_enable_gds_pg(adev, true);
3111                 } else {
3112                         WREG32(mmRLC_SAVE_AND_RESTORE_BASE, adev->gfx.rlc.save_restore_gpu_addr >> 8);
3113                         WREG32(mmRLC_CLEAR_STATE_RESTORE_BASE, adev->gfx.rlc.clear_state_gpu_addr >> 8);
3114
3115                 }
3116                 gfx_v6_0_init_ao_cu_mask(adev);
3117                 gfx_v6_0_update_gfx_pg(adev, true);
3118         } else {
3119
3120                 WREG32(mmRLC_SAVE_AND_RESTORE_BASE, adev->gfx.rlc.save_restore_gpu_addr >> 8);
3121                 WREG32(mmRLC_CLEAR_STATE_RESTORE_BASE, adev->gfx.rlc.clear_state_gpu_addr >> 8);
3122         }
3123 }
3124
3125 static void gfx_v6_0_fini_pg(struct amdgpu_device *adev)
3126 {
3127         if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG |
3128                               AMD_PG_SUPPORT_GFX_SMG |
3129                               AMD_PG_SUPPORT_GFX_DMG |
3130                               AMD_PG_SUPPORT_CP |
3131                               AMD_PG_SUPPORT_GDS |
3132                               AMD_PG_SUPPORT_RLC_SMU_HS)) {
3133                 gfx_v6_0_update_gfx_pg(adev, false);
3134                 if (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG) {
3135                         gfx_v6_0_enable_cp_pg(adev, false);
3136                         gfx_v6_0_enable_gds_pg(adev, false);
3137                 }
3138         }
3139 }
3140
3141 static uint64_t gfx_v6_0_get_gpu_clock_counter(struct amdgpu_device *adev)
3142 {
3143         uint64_t clock;
3144
3145         mutex_lock(&adev->gfx.gpu_clock_mutex);
3146         WREG32(mmRLC_CAPTURE_GPU_CLOCK_COUNT, 1);
3147         clock = (uint64_t)RREG32(mmRLC_GPU_CLOCK_COUNT_LSB) |
3148                 ((uint64_t)RREG32(mmRLC_GPU_CLOCK_COUNT_MSB) << 32ULL);
3149         mutex_unlock(&adev->gfx.gpu_clock_mutex);
3150         return clock;
3151 }
3152
3153 static void gfx_v6_ring_emit_cntxcntl(struct amdgpu_ring *ring, uint32_t flags)
3154 {
3155         if (flags & AMDGPU_HAVE_CTX_SWITCH)
3156                 gfx_v6_0_ring_emit_vgt_flush(ring);
3157         amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1));
3158         amdgpu_ring_write(ring, 0x80000000);
3159         amdgpu_ring_write(ring, 0);
3160 }
3161
3162
3163 static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t address)
3164 {
3165         WREG32(mmSQ_IND_INDEX,
3166                 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) |
3167                 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) |
3168                 (address << SQ_IND_INDEX__INDEX__SHIFT) |
3169                 (SQ_IND_INDEX__FORCE_READ_MASK));
3170         return RREG32(mmSQ_IND_DATA);
3171 }
3172
3173 static void wave_read_regs(struct amdgpu_device *adev, uint32_t simd,
3174                            uint32_t wave, uint32_t thread,
3175                            uint32_t regno, uint32_t num, uint32_t *out)
3176 {
3177         WREG32(mmSQ_IND_INDEX,
3178                 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) |
3179                 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) |
3180                 (regno << SQ_IND_INDEX__INDEX__SHIFT) |
3181                 (thread << SQ_IND_INDEX__THREAD_ID__SHIFT) |
3182                 (SQ_IND_INDEX__FORCE_READ_MASK) |
3183                 (SQ_IND_INDEX__AUTO_INCR_MASK));
3184         while (num--)
3185                 *(out++) = RREG32(mmSQ_IND_DATA);
3186 }
3187
3188 static void gfx_v6_0_read_wave_data(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t *dst, int *no_fields)
3189 {
3190         /* type 0 wave data */
3191         dst[(*no_fields)++] = 0;
3192         dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_STATUS);
3193         dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_LO);
3194         dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_HI);
3195         dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_LO);
3196         dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_HI);
3197         dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_HW_ID);
3198         dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_INST_DW0);
3199         dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_INST_DW1);
3200         dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_GPR_ALLOC);
3201         dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_LDS_ALLOC);
3202         dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TRAPSTS);
3203         dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_IB_STS);
3204         dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TBA_LO);
3205         dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TBA_HI);
3206         dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TMA_LO);
3207         dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TMA_HI);
3208         dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_IB_DBG0);
3209         dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_M0);
3210 }
3211
3212 static void gfx_v6_0_read_wave_sgprs(struct amdgpu_device *adev, uint32_t simd,
3213                                      uint32_t wave, uint32_t start,
3214                                      uint32_t size, uint32_t *dst)
3215 {
3216         wave_read_regs(
3217                 adev, simd, wave, 0,
3218                 start + SQIND_WAVE_SGPRS_OFFSET, size, dst);
3219 }
3220
3221 static const struct amdgpu_gfx_funcs gfx_v6_0_gfx_funcs = {
3222         .get_gpu_clock_counter = &gfx_v6_0_get_gpu_clock_counter,
3223         .select_se_sh = &gfx_v6_0_select_se_sh,
3224         .read_wave_data = &gfx_v6_0_read_wave_data,
3225         .read_wave_sgprs = &gfx_v6_0_read_wave_sgprs,
3226 };
3227
3228 static int gfx_v6_0_early_init(void *handle)
3229 {
3230         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3231
3232         adev->gfx.num_gfx_rings = GFX6_NUM_GFX_RINGS;
3233         adev->gfx.num_compute_rings = GFX6_NUM_COMPUTE_RINGS;
3234         adev->gfx.funcs = &gfx_v6_0_gfx_funcs;
3235         gfx_v6_0_set_ring_funcs(adev);
3236         gfx_v6_0_set_irq_funcs(adev);
3237
3238         return 0;
3239 }
3240
3241 static int gfx_v6_0_sw_init(void *handle)
3242 {
3243         struct amdgpu_ring *ring;
3244         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3245         int i, r;
3246
3247         r = amdgpu_irq_add_id(adev, 181, &adev->gfx.eop_irq);
3248         if (r)
3249                 return r;
3250
3251         r = amdgpu_irq_add_id(adev, 184, &adev->gfx.priv_reg_irq);
3252         if (r)
3253                 return r;
3254
3255         r = amdgpu_irq_add_id(adev, 185, &adev->gfx.priv_inst_irq);
3256         if (r)
3257                 return r;
3258
3259         gfx_v6_0_scratch_init(adev);
3260
3261         r = gfx_v6_0_init_microcode(adev);
3262         if (r) {
3263                 DRM_ERROR("Failed to load gfx firmware!\n");
3264                 return r;
3265         }
3266
3267         r = gfx_v6_0_rlc_init(adev);
3268         if (r) {
3269                 DRM_ERROR("Failed to init rlc BOs!\n");
3270                 return r;
3271         }
3272
3273         for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
3274                 ring = &adev->gfx.gfx_ring[i];
3275                 ring->ring_obj = NULL;
3276                 sprintf(ring->name, "gfx");
3277                 r = amdgpu_ring_init(adev, ring, 1024,
3278                                      &adev->gfx.eop_irq, AMDGPU_CP_IRQ_GFX_EOP);
3279                 if (r)
3280                         return r;
3281         }
3282
3283         for (i = 0; i < adev->gfx.num_compute_rings; i++) {
3284                 unsigned irq_type;
3285
3286                 if ((i >= 32) || (i >= AMDGPU_MAX_COMPUTE_RINGS)) {
3287                         DRM_ERROR("Too many (%d) compute rings!\n", i);
3288                         break;
3289                 }
3290                 ring = &adev->gfx.compute_ring[i];
3291                 ring->ring_obj = NULL;
3292                 ring->use_doorbell = false;
3293                 ring->doorbell_index = 0;
3294                 ring->me = 1;
3295                 ring->pipe = i;
3296                 ring->queue = i;
3297                 sprintf(ring->name, "comp %d.%d.%d", ring->me, ring->pipe, ring->queue);
3298                 irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP + ring->pipe;
3299                 r = amdgpu_ring_init(adev, ring, 1024,
3300                                      &adev->gfx.eop_irq, irq_type);
3301                 if (r)
3302                         return r;
3303         }
3304
3305         return r;
3306 }
3307
3308 static int gfx_v6_0_sw_fini(void *handle)
3309 {
3310         int i;
3311         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3312
3313         amdgpu_bo_unref(&adev->gds.oa_gfx_bo);
3314         amdgpu_bo_unref(&adev->gds.gws_gfx_bo);
3315         amdgpu_bo_unref(&adev->gds.gds_gfx_bo);
3316
3317         for (i = 0; i < adev->gfx.num_gfx_rings; i++)
3318                 amdgpu_ring_fini(&adev->gfx.gfx_ring[i]);
3319         for (i = 0; i < adev->gfx.num_compute_rings; i++)
3320                 amdgpu_ring_fini(&adev->gfx.compute_ring[i]);
3321
3322         gfx_v6_0_rlc_fini(adev);
3323
3324         return 0;
3325 }
3326
3327 static int gfx_v6_0_hw_init(void *handle)
3328 {
3329         int r;
3330         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3331
3332         gfx_v6_0_gpu_init(adev);
3333
3334         r = gfx_v6_0_rlc_resume(adev);
3335         if (r)
3336                 return r;
3337
3338         r = gfx_v6_0_cp_resume(adev);
3339         if (r)
3340                 return r;
3341
3342         adev->gfx.ce_ram_size = 0x8000;
3343
3344         return r;
3345 }
3346
3347 static int gfx_v6_0_hw_fini(void *handle)
3348 {
3349         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3350
3351         gfx_v6_0_cp_enable(adev, false);
3352         gfx_v6_0_rlc_stop(adev);
3353         gfx_v6_0_fini_pg(adev);
3354
3355         return 0;
3356 }
3357
3358 static int gfx_v6_0_suspend(void *handle)
3359 {
3360         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3361
3362         return gfx_v6_0_hw_fini(adev);
3363 }
3364
3365 static int gfx_v6_0_resume(void *handle)
3366 {
3367         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3368
3369         return gfx_v6_0_hw_init(adev);
3370 }
3371
3372 static bool gfx_v6_0_is_idle(void *handle)
3373 {
3374         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3375
3376         if (RREG32(mmGRBM_STATUS) & GRBM_STATUS__GUI_ACTIVE_MASK)
3377                 return false;
3378         else
3379                 return true;
3380 }
3381
3382 static int gfx_v6_0_wait_for_idle(void *handle)
3383 {
3384         unsigned i;
3385         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3386
3387         for (i = 0; i < adev->usec_timeout; i++) {
3388                 if (gfx_v6_0_is_idle(handle))
3389                         return 0;
3390                 udelay(1);
3391         }
3392         return -ETIMEDOUT;
3393 }
3394
3395 static int gfx_v6_0_soft_reset(void *handle)
3396 {
3397         return 0;
3398 }
3399
3400 static void gfx_v6_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev,
3401                                                  enum amdgpu_interrupt_state state)
3402 {
3403         u32 cp_int_cntl;
3404
3405         switch (state) {
3406         case AMDGPU_IRQ_STATE_DISABLE:
3407                 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
3408                 cp_int_cntl &= ~CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK;
3409                 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
3410                 break;
3411         case AMDGPU_IRQ_STATE_ENABLE:
3412                 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
3413                 cp_int_cntl |= CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK;
3414                 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
3415                 break;
3416         default:
3417                 break;
3418         }
3419 }
3420
3421 static void gfx_v6_0_set_compute_eop_interrupt_state(struct amdgpu_device *adev,
3422                                                      int ring,
3423                                                      enum amdgpu_interrupt_state state)
3424 {
3425         u32 cp_int_cntl;
3426         switch (state){
3427         case AMDGPU_IRQ_STATE_DISABLE:
3428                 if (ring == 0) {
3429                         cp_int_cntl = RREG32(mmCP_INT_CNTL_RING1);
3430                         cp_int_cntl &= ~CP_INT_CNTL_RING1__TIME_STAMP_INT_ENABLE_MASK;
3431                         WREG32(mmCP_INT_CNTL_RING1, cp_int_cntl);
3432                         break;
3433                 } else {
3434                         cp_int_cntl = RREG32(mmCP_INT_CNTL_RING2);
3435                         cp_int_cntl &= ~CP_INT_CNTL_RING2__TIME_STAMP_INT_ENABLE_MASK;
3436                         WREG32(mmCP_INT_CNTL_RING2, cp_int_cntl);
3437                         break;
3438
3439                 }
3440         case AMDGPU_IRQ_STATE_ENABLE:
3441                 if (ring == 0) {
3442                         cp_int_cntl = RREG32(mmCP_INT_CNTL_RING1);
3443                         cp_int_cntl |= CP_INT_CNTL_RING1__TIME_STAMP_INT_ENABLE_MASK;
3444                         WREG32(mmCP_INT_CNTL_RING1, cp_int_cntl);
3445                         break;
3446                 } else {
3447                         cp_int_cntl = RREG32(mmCP_INT_CNTL_RING2);
3448                         cp_int_cntl |= CP_INT_CNTL_RING2__TIME_STAMP_INT_ENABLE_MASK;
3449                         WREG32(mmCP_INT_CNTL_RING2, cp_int_cntl);
3450                         break;
3451
3452                 }
3453
3454         default:
3455                 BUG();
3456                 break;
3457
3458         }
3459 }
3460
3461 static int gfx_v6_0_set_priv_reg_fault_state(struct amdgpu_device *adev,
3462                                              struct amdgpu_irq_src *src,
3463                                              unsigned type,
3464                                              enum amdgpu_interrupt_state state)
3465 {
3466         u32 cp_int_cntl;
3467
3468         switch (state) {
3469         case AMDGPU_IRQ_STATE_DISABLE:
3470                 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
3471                 cp_int_cntl &= ~CP_INT_CNTL_RING0__PRIV_REG_INT_ENABLE_MASK;
3472                 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
3473                 break;
3474         case AMDGPU_IRQ_STATE_ENABLE:
3475                 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
3476                 cp_int_cntl |= CP_INT_CNTL_RING0__PRIV_REG_INT_ENABLE_MASK;
3477                 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
3478                 break;
3479         default:
3480                 break;
3481         }
3482
3483         return 0;
3484 }
3485
3486 static int gfx_v6_0_set_priv_inst_fault_state(struct amdgpu_device *adev,
3487                                               struct amdgpu_irq_src *src,
3488                                               unsigned type,
3489                                               enum amdgpu_interrupt_state state)
3490 {
3491         u32 cp_int_cntl;
3492
3493         switch (state) {
3494         case AMDGPU_IRQ_STATE_DISABLE:
3495                 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
3496                 cp_int_cntl &= ~CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE_MASK;
3497                 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
3498                 break;
3499         case AMDGPU_IRQ_STATE_ENABLE:
3500                 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
3501                 cp_int_cntl |= CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE_MASK;
3502                 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
3503                 break;
3504         default:
3505                 break;
3506         }
3507
3508         return 0;
3509 }
3510
3511 static int gfx_v6_0_set_eop_interrupt_state(struct amdgpu_device *adev,
3512                                             struct amdgpu_irq_src *src,
3513                                             unsigned type,
3514                                             enum amdgpu_interrupt_state state)
3515 {
3516         switch (type) {
3517         case AMDGPU_CP_IRQ_GFX_EOP:
3518                 gfx_v6_0_set_gfx_eop_interrupt_state(adev, state);
3519                 break;
3520         case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP:
3521                 gfx_v6_0_set_compute_eop_interrupt_state(adev, 0, state);
3522                 break;
3523         case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP:
3524                 gfx_v6_0_set_compute_eop_interrupt_state(adev, 1, state);
3525                 break;
3526         default:
3527                 break;
3528         }
3529         return 0;
3530 }
3531
3532 static int gfx_v6_0_eop_irq(struct amdgpu_device *adev,
3533                             struct amdgpu_irq_src *source,
3534                             struct amdgpu_iv_entry *entry)
3535 {
3536         switch (entry->ring_id) {
3537         case 0:
3538                 amdgpu_fence_process(&adev->gfx.gfx_ring[0]);
3539                 break;
3540         case 1:
3541         case 2:
3542                 amdgpu_fence_process(&adev->gfx.compute_ring[entry->ring_id - 1]);
3543                 break;
3544         default:
3545                 break;
3546         }
3547         return 0;
3548 }
3549
3550 static int gfx_v6_0_priv_reg_irq(struct amdgpu_device *adev,
3551                                  struct amdgpu_irq_src *source,
3552                                  struct amdgpu_iv_entry *entry)
3553 {
3554         DRM_ERROR("Illegal register access in command stream\n");
3555         schedule_work(&adev->reset_work);
3556         return 0;
3557 }
3558
3559 static int gfx_v6_0_priv_inst_irq(struct amdgpu_device *adev,
3560                                   struct amdgpu_irq_src *source,
3561                                   struct amdgpu_iv_entry *entry)
3562 {
3563         DRM_ERROR("Illegal instruction in command stream\n");
3564         schedule_work(&adev->reset_work);
3565         return 0;
3566 }
3567
3568 static int gfx_v6_0_set_clockgating_state(void *handle,
3569                                           enum amd_clockgating_state state)
3570 {
3571         bool gate = false;
3572         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3573
3574         if (state == AMD_CG_STATE_GATE)
3575                 gate = true;
3576
3577         gfx_v6_0_enable_gui_idle_interrupt(adev, false);
3578         if (gate) {
3579                 gfx_v6_0_enable_mgcg(adev, true);
3580                 gfx_v6_0_enable_cgcg(adev, true);
3581         } else {
3582                 gfx_v6_0_enable_cgcg(adev, false);
3583                 gfx_v6_0_enable_mgcg(adev, false);
3584         }
3585         gfx_v6_0_enable_gui_idle_interrupt(adev, true);
3586
3587         return 0;
3588 }
3589
3590 static int gfx_v6_0_set_powergating_state(void *handle,
3591                                           enum amd_powergating_state state)
3592 {
3593         bool gate = false;
3594         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3595
3596         if (state == AMD_PG_STATE_GATE)
3597                 gate = true;
3598
3599         if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG |
3600                               AMD_PG_SUPPORT_GFX_SMG |
3601                               AMD_PG_SUPPORT_GFX_DMG |
3602                               AMD_PG_SUPPORT_CP |
3603                               AMD_PG_SUPPORT_GDS |
3604                               AMD_PG_SUPPORT_RLC_SMU_HS)) {
3605                 gfx_v6_0_update_gfx_pg(adev, gate);
3606                 if (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG) {
3607                         gfx_v6_0_enable_cp_pg(adev, gate);
3608                         gfx_v6_0_enable_gds_pg(adev, gate);
3609                 }
3610         }
3611
3612         return 0;
3613 }
3614
3615 static const struct amd_ip_funcs gfx_v6_0_ip_funcs = {
3616         .name = "gfx_v6_0",
3617         .early_init = gfx_v6_0_early_init,
3618         .late_init = NULL,
3619         .sw_init = gfx_v6_0_sw_init,
3620         .sw_fini = gfx_v6_0_sw_fini,
3621         .hw_init = gfx_v6_0_hw_init,
3622         .hw_fini = gfx_v6_0_hw_fini,
3623         .suspend = gfx_v6_0_suspend,
3624         .resume = gfx_v6_0_resume,
3625         .is_idle = gfx_v6_0_is_idle,
3626         .wait_for_idle = gfx_v6_0_wait_for_idle,
3627         .soft_reset = gfx_v6_0_soft_reset,
3628         .set_clockgating_state = gfx_v6_0_set_clockgating_state,
3629         .set_powergating_state = gfx_v6_0_set_powergating_state,
3630 };
3631
3632 static const struct amdgpu_ring_funcs gfx_v6_0_ring_funcs_gfx = {
3633         .type = AMDGPU_RING_TYPE_GFX,
3634         .align_mask = 0xff,
3635         .nop = 0x80000000,
3636         .get_rptr = gfx_v6_0_ring_get_rptr,
3637         .get_wptr = gfx_v6_0_ring_get_wptr,
3638         .set_wptr = gfx_v6_0_ring_set_wptr_gfx,
3639         .emit_frame_size =
3640                 5 + /* gfx_v6_0_ring_emit_hdp_flush */
3641                 5 + /* gfx_v6_0_ring_emit_hdp_invalidate */
3642                 14 + 14 + 14 + /* gfx_v6_0_ring_emit_fence x3 for user fence, vm fence */
3643                 7 + 4 + /* gfx_v6_0_ring_emit_pipeline_sync */
3644                 17 + 6 + /* gfx_v6_0_ring_emit_vm_flush */
3645                 3 + 2, /* gfx_v6_ring_emit_cntxcntl including vgt flush */
3646         .emit_ib_size = 6, /* gfx_v6_0_ring_emit_ib */
3647         .emit_ib = gfx_v6_0_ring_emit_ib,
3648         .emit_fence = gfx_v6_0_ring_emit_fence,
3649         .emit_pipeline_sync = gfx_v6_0_ring_emit_pipeline_sync,
3650         .emit_vm_flush = gfx_v6_0_ring_emit_vm_flush,
3651         .emit_hdp_flush = gfx_v6_0_ring_emit_hdp_flush,
3652         .emit_hdp_invalidate = gfx_v6_0_ring_emit_hdp_invalidate,
3653         .test_ring = gfx_v6_0_ring_test_ring,
3654         .test_ib = gfx_v6_0_ring_test_ib,
3655         .insert_nop = amdgpu_ring_insert_nop,
3656         .emit_cntxcntl = gfx_v6_ring_emit_cntxcntl,
3657 };
3658
3659 static const struct amdgpu_ring_funcs gfx_v6_0_ring_funcs_compute = {
3660         .type = AMDGPU_RING_TYPE_COMPUTE,
3661         .align_mask = 0xff,
3662         .nop = 0x80000000,
3663         .get_rptr = gfx_v6_0_ring_get_rptr,
3664         .get_wptr = gfx_v6_0_ring_get_wptr,
3665         .set_wptr = gfx_v6_0_ring_set_wptr_compute,
3666         .emit_frame_size =
3667                 5 + /* gfx_v6_0_ring_emit_hdp_flush */
3668                 5 + /* gfx_v6_0_ring_emit_hdp_invalidate */
3669                 7 + /* gfx_v6_0_ring_emit_pipeline_sync */
3670                 17 + /* gfx_v6_0_ring_emit_vm_flush */
3671                 14 + 14 + 14, /* gfx_v6_0_ring_emit_fence x3 for user fence, vm fence */
3672         .emit_ib_size = 6, /* gfx_v6_0_ring_emit_ib */
3673         .emit_ib = gfx_v6_0_ring_emit_ib,
3674         .emit_fence = gfx_v6_0_ring_emit_fence,
3675         .emit_pipeline_sync = gfx_v6_0_ring_emit_pipeline_sync,
3676         .emit_vm_flush = gfx_v6_0_ring_emit_vm_flush,
3677         .emit_hdp_flush = gfx_v6_0_ring_emit_hdp_flush,
3678         .emit_hdp_invalidate = gfx_v6_0_ring_emit_hdp_invalidate,
3679         .test_ring = gfx_v6_0_ring_test_ring,
3680         .test_ib = gfx_v6_0_ring_test_ib,
3681         .insert_nop = amdgpu_ring_insert_nop,
3682 };
3683
3684 static void gfx_v6_0_set_ring_funcs(struct amdgpu_device *adev)
3685 {
3686         int i;
3687
3688         for (i = 0; i < adev->gfx.num_gfx_rings; i++)
3689                 adev->gfx.gfx_ring[i].funcs = &gfx_v6_0_ring_funcs_gfx;
3690         for (i = 0; i < adev->gfx.num_compute_rings; i++)
3691                 adev->gfx.compute_ring[i].funcs = &gfx_v6_0_ring_funcs_compute;
3692 }
3693
3694 static const struct amdgpu_irq_src_funcs gfx_v6_0_eop_irq_funcs = {
3695         .set = gfx_v6_0_set_eop_interrupt_state,
3696         .process = gfx_v6_0_eop_irq,
3697 };
3698
3699 static const struct amdgpu_irq_src_funcs gfx_v6_0_priv_reg_irq_funcs = {
3700         .set = gfx_v6_0_set_priv_reg_fault_state,
3701         .process = gfx_v6_0_priv_reg_irq,
3702 };
3703
3704 static const struct amdgpu_irq_src_funcs gfx_v6_0_priv_inst_irq_funcs = {
3705         .set = gfx_v6_0_set_priv_inst_fault_state,
3706         .process = gfx_v6_0_priv_inst_irq,
3707 };
3708
3709 static void gfx_v6_0_set_irq_funcs(struct amdgpu_device *adev)
3710 {
3711         adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST;
3712         adev->gfx.eop_irq.funcs = &gfx_v6_0_eop_irq_funcs;
3713
3714         adev->gfx.priv_reg_irq.num_types = 1;
3715         adev->gfx.priv_reg_irq.funcs = &gfx_v6_0_priv_reg_irq_funcs;
3716
3717         adev->gfx.priv_inst_irq.num_types = 1;
3718         adev->gfx.priv_inst_irq.funcs = &gfx_v6_0_priv_inst_irq_funcs;
3719 }
3720
3721 static void gfx_v6_0_get_cu_info(struct amdgpu_device *adev)
3722 {
3723         int i, j, k, counter, active_cu_number = 0;
3724         u32 mask, bitmap, ao_bitmap, ao_cu_mask = 0;
3725         struct amdgpu_cu_info *cu_info = &adev->gfx.cu_info;
3726
3727         memset(cu_info, 0, sizeof(*cu_info));
3728
3729         for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
3730                 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
3731                         mask = 1;
3732                         ao_bitmap = 0;
3733                         counter = 0;
3734                         bitmap = gfx_v6_0_get_cu_active_bitmap(adev, i, j);
3735                         cu_info->bitmap[i][j] = bitmap;
3736
3737                         for (k = 0; k < adev->gfx.config.max_cu_per_sh; k ++) {
3738                                 if (bitmap & mask) {
3739                                         if (counter < 2)
3740                                                 ao_bitmap |= mask;
3741                                         counter ++;
3742                                 }
3743                                 mask <<= 1;
3744                         }
3745                         active_cu_number += counter;
3746                         ao_cu_mask |= (ao_bitmap << (i * 16 + j * 8));
3747                 }
3748         }
3749
3750         cu_info->number = active_cu_number;
3751         cu_info->ao_cu_mask = ao_cu_mask;
3752 }
3753
3754 const struct amdgpu_ip_block_version gfx_v6_0_ip_block =
3755 {
3756         .type = AMD_IP_BLOCK_TYPE_GFX,
3757         .major = 6,
3758         .minor = 0,
3759         .rev = 0,
3760         .funcs = &gfx_v6_0_ip_funcs,
3761 };