2 * Copyright 2015 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
23 #include <linux/firmware.h>
24 #include <linux/module.h>
27 #include "amdgpu_ih.h"
28 #include "amdgpu_gfx.h"
29 #include "amdgpu_ucode.h"
30 #include "clearstate_si.h"
31 #include "bif/bif_3_0_d.h"
32 #include "bif/bif_3_0_sh_mask.h"
33 #include "oss/oss_1_0_d.h"
34 #include "oss/oss_1_0_sh_mask.h"
35 #include "gca/gfx_6_0_d.h"
36 #include "gca/gfx_6_0_sh_mask.h"
37 #include "gmc/gmc_6_0_d.h"
38 #include "gmc/gmc_6_0_sh_mask.h"
39 #include "dce/dce_6_0_d.h"
40 #include "dce/dce_6_0_sh_mask.h"
41 #include "gca/gfx_7_2_enum.h"
45 static void gfx_v6_0_set_ring_funcs(struct amdgpu_device *adev);
46 static void gfx_v6_0_set_irq_funcs(struct amdgpu_device *adev);
47 static void gfx_v6_0_get_cu_info(struct amdgpu_device *adev);
49 MODULE_FIRMWARE("amdgpu/tahiti_pfp.bin");
50 MODULE_FIRMWARE("amdgpu/tahiti_me.bin");
51 MODULE_FIRMWARE("amdgpu/tahiti_ce.bin");
52 MODULE_FIRMWARE("amdgpu/tahiti_rlc.bin");
54 MODULE_FIRMWARE("amdgpu/pitcairn_pfp.bin");
55 MODULE_FIRMWARE("amdgpu/pitcairn_me.bin");
56 MODULE_FIRMWARE("amdgpu/pitcairn_ce.bin");
57 MODULE_FIRMWARE("amdgpu/pitcairn_rlc.bin");
59 MODULE_FIRMWARE("amdgpu/verde_pfp.bin");
60 MODULE_FIRMWARE("amdgpu/verde_me.bin");
61 MODULE_FIRMWARE("amdgpu/verde_ce.bin");
62 MODULE_FIRMWARE("amdgpu/verde_rlc.bin");
64 MODULE_FIRMWARE("amdgpu/oland_pfp.bin");
65 MODULE_FIRMWARE("amdgpu/oland_me.bin");
66 MODULE_FIRMWARE("amdgpu/oland_ce.bin");
67 MODULE_FIRMWARE("amdgpu/oland_rlc.bin");
69 MODULE_FIRMWARE("amdgpu/hainan_pfp.bin");
70 MODULE_FIRMWARE("amdgpu/hainan_me.bin");
71 MODULE_FIRMWARE("amdgpu/hainan_ce.bin");
72 MODULE_FIRMWARE("amdgpu/hainan_rlc.bin");
74 static u32 gfx_v6_0_get_csb_size(struct amdgpu_device *adev);
75 static void gfx_v6_0_get_csb_buffer(struct amdgpu_device *adev, volatile u32 *buffer);
76 //static void gfx_v6_0_init_cp_pg_table(struct amdgpu_device *adev);
77 static void gfx_v6_0_init_pg(struct amdgpu_device *adev);
79 #define ARRAY_MODE(x) ((x) << GB_TILE_MODE0__ARRAY_MODE__SHIFT)
80 #define PIPE_CONFIG(x) ((x) << GB_TILE_MODE0__PIPE_CONFIG__SHIFT)
81 #define TILE_SPLIT(x) ((x) << GB_TILE_MODE0__TILE_SPLIT__SHIFT)
82 #define MICRO_TILE_MODE(x) ((x) << 0)
83 #define SAMPLE_SPLIT(x) ((x) << GB_TILE_MODE0__SAMPLE_SPLIT__SHIFT)
84 #define BANK_WIDTH(x) ((x) << 14)
85 #define BANK_HEIGHT(x) ((x) << 16)
86 #define MACRO_TILE_ASPECT(x) ((x) << 18)
87 #define NUM_BANKS(x) ((x) << 20)
89 static const u32 verde_rlc_save_restore_register_list[] =
91 (0x8000 << 16) | (0x98f4 >> 2),
93 (0x8040 << 16) | (0x98f4 >> 2),
95 (0x8000 << 16) | (0xe80 >> 2),
97 (0x8040 << 16) | (0xe80 >> 2),
99 (0x8000 << 16) | (0x89bc >> 2),
101 (0x8040 << 16) | (0x89bc >> 2),
103 (0x8000 << 16) | (0x8c1c >> 2),
105 (0x8040 << 16) | (0x8c1c >> 2),
107 (0x9c00 << 16) | (0x98f0 >> 2),
109 (0x9c00 << 16) | (0xe7c >> 2),
111 (0x8000 << 16) | (0x9148 >> 2),
113 (0x8040 << 16) | (0x9148 >> 2),
115 (0x9c00 << 16) | (0x9150 >> 2),
117 (0x9c00 << 16) | (0x897c >> 2),
119 (0x9c00 << 16) | (0x8d8c >> 2),
121 (0x9c00 << 16) | (0xac54 >> 2),
124 (0x9c00 << 16) | (0x98f8 >> 2),
126 (0x9c00 << 16) | (0x9910 >> 2),
128 (0x9c00 << 16) | (0x9914 >> 2),
130 (0x9c00 << 16) | (0x9918 >> 2),
132 (0x9c00 << 16) | (0x991c >> 2),
134 (0x9c00 << 16) | (0x9920 >> 2),
136 (0x9c00 << 16) | (0x9924 >> 2),
138 (0x9c00 << 16) | (0x9928 >> 2),
140 (0x9c00 << 16) | (0x992c >> 2),
142 (0x9c00 << 16) | (0x9930 >> 2),
144 (0x9c00 << 16) | (0x9934 >> 2),
146 (0x9c00 << 16) | (0x9938 >> 2),
148 (0x9c00 << 16) | (0x993c >> 2),
150 (0x9c00 << 16) | (0x9940 >> 2),
152 (0x9c00 << 16) | (0x9944 >> 2),
154 (0x9c00 << 16) | (0x9948 >> 2),
156 (0x9c00 << 16) | (0x994c >> 2),
158 (0x9c00 << 16) | (0x9950 >> 2),
160 (0x9c00 << 16) | (0x9954 >> 2),
162 (0x9c00 << 16) | (0x9958 >> 2),
164 (0x9c00 << 16) | (0x995c >> 2),
166 (0x9c00 << 16) | (0x9960 >> 2),
168 (0x9c00 << 16) | (0x9964 >> 2),
170 (0x9c00 << 16) | (0x9968 >> 2),
172 (0x9c00 << 16) | (0x996c >> 2),
174 (0x9c00 << 16) | (0x9970 >> 2),
176 (0x9c00 << 16) | (0x9974 >> 2),
178 (0x9c00 << 16) | (0x9978 >> 2),
180 (0x9c00 << 16) | (0x997c >> 2),
182 (0x9c00 << 16) | (0x9980 >> 2),
184 (0x9c00 << 16) | (0x9984 >> 2),
186 (0x9c00 << 16) | (0x9988 >> 2),
188 (0x9c00 << 16) | (0x998c >> 2),
190 (0x9c00 << 16) | (0x8c00 >> 2),
192 (0x9c00 << 16) | (0x8c14 >> 2),
194 (0x9c00 << 16) | (0x8c04 >> 2),
196 (0x9c00 << 16) | (0x8c08 >> 2),
198 (0x8000 << 16) | (0x9b7c >> 2),
200 (0x8040 << 16) | (0x9b7c >> 2),
202 (0x8000 << 16) | (0xe84 >> 2),
204 (0x8040 << 16) | (0xe84 >> 2),
206 (0x8000 << 16) | (0x89c0 >> 2),
208 (0x8040 << 16) | (0x89c0 >> 2),
210 (0x8000 << 16) | (0x914c >> 2),
212 (0x8040 << 16) | (0x914c >> 2),
214 (0x8000 << 16) | (0x8c20 >> 2),
216 (0x8040 << 16) | (0x8c20 >> 2),
218 (0x8000 << 16) | (0x9354 >> 2),
220 (0x8040 << 16) | (0x9354 >> 2),
222 (0x9c00 << 16) | (0x9060 >> 2),
224 (0x9c00 << 16) | (0x9364 >> 2),
226 (0x9c00 << 16) | (0x9100 >> 2),
228 (0x9c00 << 16) | (0x913c >> 2),
230 (0x8000 << 16) | (0x90e0 >> 2),
232 (0x8000 << 16) | (0x90e4 >> 2),
234 (0x8000 << 16) | (0x90e8 >> 2),
236 (0x8040 << 16) | (0x90e0 >> 2),
238 (0x8040 << 16) | (0x90e4 >> 2),
240 (0x8040 << 16) | (0x90e8 >> 2),
242 (0x9c00 << 16) | (0x8bcc >> 2),
244 (0x9c00 << 16) | (0x8b24 >> 2),
246 (0x9c00 << 16) | (0x88c4 >> 2),
248 (0x9c00 << 16) | (0x8e50 >> 2),
250 (0x9c00 << 16) | (0x8c0c >> 2),
252 (0x9c00 << 16) | (0x8e58 >> 2),
254 (0x9c00 << 16) | (0x8e5c >> 2),
256 (0x9c00 << 16) | (0x9508 >> 2),
258 (0x9c00 << 16) | (0x950c >> 2),
260 (0x9c00 << 16) | (0x9494 >> 2),
262 (0x9c00 << 16) | (0xac0c >> 2),
264 (0x9c00 << 16) | (0xac10 >> 2),
266 (0x9c00 << 16) | (0xac14 >> 2),
268 (0x9c00 << 16) | (0xae00 >> 2),
270 (0x9c00 << 16) | (0xac08 >> 2),
272 (0x9c00 << 16) | (0x88d4 >> 2),
274 (0x9c00 << 16) | (0x88c8 >> 2),
276 (0x9c00 << 16) | (0x88cc >> 2),
278 (0x9c00 << 16) | (0x89b0 >> 2),
280 (0x9c00 << 16) | (0x8b10 >> 2),
282 (0x9c00 << 16) | (0x8a14 >> 2),
284 (0x9c00 << 16) | (0x9830 >> 2),
286 (0x9c00 << 16) | (0x9834 >> 2),
288 (0x9c00 << 16) | (0x9838 >> 2),
290 (0x9c00 << 16) | (0x9a10 >> 2),
292 (0x8000 << 16) | (0x9870 >> 2),
294 (0x8000 << 16) | (0x9874 >> 2),
296 (0x8001 << 16) | (0x9870 >> 2),
298 (0x8001 << 16) | (0x9874 >> 2),
300 (0x8040 << 16) | (0x9870 >> 2),
302 (0x8040 << 16) | (0x9874 >> 2),
304 (0x8041 << 16) | (0x9870 >> 2),
306 (0x8041 << 16) | (0x9874 >> 2),
311 static int gfx_v6_0_init_microcode(struct amdgpu_device *adev)
313 const char *chip_name;
316 const struct gfx_firmware_header_v1_0 *cp_hdr;
317 const struct rlc_firmware_header_v1_0 *rlc_hdr;
321 switch (adev->asic_type) {
323 chip_name = "tahiti";
326 chip_name = "pitcairn";
335 chip_name = "hainan";
340 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_pfp.bin", chip_name);
341 err = amdgpu_ucode_request(adev, &adev->gfx.pfp_fw, fw_name);
344 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data;
345 adev->gfx.pfp_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
346 adev->gfx.pfp_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
348 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_me.bin", chip_name);
349 err = amdgpu_ucode_request(adev, &adev->gfx.me_fw, fw_name);
352 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data;
353 adev->gfx.me_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
354 adev->gfx.me_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
356 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ce.bin", chip_name);
357 err = amdgpu_ucode_request(adev, &adev->gfx.ce_fw, fw_name);
360 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data;
361 adev->gfx.ce_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
362 adev->gfx.ce_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
364 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_rlc.bin", chip_name);
365 err = amdgpu_ucode_request(adev, &adev->gfx.rlc_fw, fw_name);
368 rlc_hdr = (const struct rlc_firmware_header_v1_0 *)adev->gfx.rlc_fw->data;
369 adev->gfx.rlc_fw_version = le32_to_cpu(rlc_hdr->header.ucode_version);
370 adev->gfx.rlc_feature_version = le32_to_cpu(rlc_hdr->ucode_feature_version);
374 pr_err("gfx6: Failed to load firmware \"%s\"\n", fw_name);
375 amdgpu_ucode_release(&adev->gfx.pfp_fw);
376 amdgpu_ucode_release(&adev->gfx.me_fw);
377 amdgpu_ucode_release(&adev->gfx.ce_fw);
378 amdgpu_ucode_release(&adev->gfx.rlc_fw);
383 static void gfx_v6_0_tiling_mode_table_init(struct amdgpu_device *adev)
385 const u32 num_tile_mode_states = ARRAY_SIZE(adev->gfx.config.tile_mode_array);
386 u32 reg_offset, split_equal_to_row_size, *tilemode;
388 memset(adev->gfx.config.tile_mode_array, 0, sizeof(adev->gfx.config.tile_mode_array));
389 tilemode = adev->gfx.config.tile_mode_array;
391 switch (adev->gfx.config.mem_row_size_in_kb) {
393 split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_1KB;
397 split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_2KB;
400 split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_4KB;
404 if (adev->asic_type == CHIP_VERDE) {
405 tilemode[0] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
406 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
407 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
408 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
409 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
410 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
411 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
412 NUM_BANKS(ADDR_SURF_16_BANK);
413 tilemode[1] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
414 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
415 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
416 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
417 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
418 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
419 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
420 NUM_BANKS(ADDR_SURF_16_BANK);
421 tilemode[2] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
422 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
423 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
424 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
425 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
426 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
427 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
428 NUM_BANKS(ADDR_SURF_16_BANK);
429 tilemode[3] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
430 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
431 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
432 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
433 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
434 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
435 NUM_BANKS(ADDR_SURF_8_BANK) |
436 TILE_SPLIT(split_equal_to_row_size);
437 tilemode[4] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
438 ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
439 PIPE_CONFIG(ADDR_SURF_P4_8x16);
440 tilemode[5] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
441 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
442 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
443 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
444 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
445 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
446 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
447 NUM_BANKS(ADDR_SURF_4_BANK);
448 tilemode[6] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
449 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
450 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
451 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
452 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
453 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
454 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
455 NUM_BANKS(ADDR_SURF_4_BANK);
456 tilemode[7] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
457 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
458 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
459 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
460 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
461 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
462 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
463 NUM_BANKS(ADDR_SURF_2_BANK);
464 tilemode[8] = ARRAY_MODE(ARRAY_LINEAR_ALIGNED);
465 tilemode[9] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
466 ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
467 PIPE_CONFIG(ADDR_SURF_P4_8x16);
468 tilemode[10] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
469 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
470 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
471 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
472 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
473 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
474 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
475 NUM_BANKS(ADDR_SURF_16_BANK);
476 tilemode[11] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
477 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
478 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
479 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
480 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
481 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
482 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
483 NUM_BANKS(ADDR_SURF_16_BANK);
484 tilemode[12] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
485 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
486 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
487 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
488 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
489 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
490 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
491 NUM_BANKS(ADDR_SURF_16_BANK);
492 tilemode[13] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
493 ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
494 PIPE_CONFIG(ADDR_SURF_P4_8x16);
495 tilemode[14] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
496 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
497 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
498 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
499 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
500 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
501 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
502 NUM_BANKS(ADDR_SURF_16_BANK);
503 tilemode[15] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
504 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
505 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
506 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
507 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
508 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
509 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
510 NUM_BANKS(ADDR_SURF_16_BANK);
511 tilemode[16] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
512 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
513 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
514 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
515 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
516 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
517 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
518 NUM_BANKS(ADDR_SURF_16_BANK);
519 tilemode[17] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
520 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
521 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
522 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
523 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
524 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
525 NUM_BANKS(ADDR_SURF_16_BANK) |
526 TILE_SPLIT(split_equal_to_row_size);
527 tilemode[18] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
528 ARRAY_MODE(ARRAY_1D_TILED_THICK) |
529 PIPE_CONFIG(ADDR_SURF_P4_8x16);
530 tilemode[19] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
531 ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
532 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
533 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
534 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
535 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
536 NUM_BANKS(ADDR_SURF_16_BANK) |
537 TILE_SPLIT(split_equal_to_row_size);
538 tilemode[20] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
539 ARRAY_MODE(ARRAY_2D_TILED_THICK) |
540 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
541 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
542 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
543 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
544 NUM_BANKS(ADDR_SURF_16_BANK) |
545 TILE_SPLIT(split_equal_to_row_size);
546 tilemode[21] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
547 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
548 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
549 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
550 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
551 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
552 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
553 NUM_BANKS(ADDR_SURF_8_BANK);
554 tilemode[22] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
555 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
556 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
557 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
558 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
559 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
560 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
561 NUM_BANKS(ADDR_SURF_8_BANK);
562 tilemode[23] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
563 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
564 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
565 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
566 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
567 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
568 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
569 NUM_BANKS(ADDR_SURF_4_BANK);
570 tilemode[24] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
571 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
572 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
573 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
574 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
575 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
576 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
577 NUM_BANKS(ADDR_SURF_4_BANK);
578 tilemode[25] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
579 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
580 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
581 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
582 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
583 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
584 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
585 NUM_BANKS(ADDR_SURF_2_BANK);
586 tilemode[26] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
587 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
588 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
589 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
590 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
591 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
592 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
593 NUM_BANKS(ADDR_SURF_2_BANK);
594 tilemode[27] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
595 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
596 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
597 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
598 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
599 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
600 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
601 NUM_BANKS(ADDR_SURF_2_BANK);
602 tilemode[28] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
603 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
604 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
605 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
606 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
607 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
608 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
609 NUM_BANKS(ADDR_SURF_2_BANK);
610 tilemode[29] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
611 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
612 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
613 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
614 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
615 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
616 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
617 NUM_BANKS(ADDR_SURF_2_BANK);
618 tilemode[30] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
619 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
620 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
621 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
622 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
623 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
624 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
625 NUM_BANKS(ADDR_SURF_2_BANK);
626 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
627 WREG32(mmGB_TILE_MODE0 + reg_offset, tilemode[reg_offset]);
628 } else if (adev->asic_type == CHIP_OLAND) {
629 tilemode[0] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
630 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
631 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
632 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
633 NUM_BANKS(ADDR_SURF_16_BANK) |
634 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
635 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
636 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4);
637 tilemode[1] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
638 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
639 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
640 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
641 NUM_BANKS(ADDR_SURF_16_BANK) |
642 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
643 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
644 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4);
645 tilemode[2] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
646 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
647 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
648 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
649 NUM_BANKS(ADDR_SURF_16_BANK) |
650 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
651 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
652 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4);
653 tilemode[3] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
654 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
655 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
656 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
657 NUM_BANKS(ADDR_SURF_16_BANK) |
658 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
659 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
660 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4);
661 tilemode[4] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
662 ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
663 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
664 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
665 NUM_BANKS(ADDR_SURF_16_BANK) |
666 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
667 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
668 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2);
669 tilemode[5] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
670 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
671 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
672 TILE_SPLIT(split_equal_to_row_size) |
673 NUM_BANKS(ADDR_SURF_16_BANK) |
674 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
675 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
676 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2);
677 tilemode[6] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
678 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
679 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
680 TILE_SPLIT(split_equal_to_row_size) |
681 NUM_BANKS(ADDR_SURF_16_BANK) |
682 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
683 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
684 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2);
685 tilemode[7] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
686 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
687 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
688 TILE_SPLIT(split_equal_to_row_size) |
689 NUM_BANKS(ADDR_SURF_16_BANK) |
690 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
691 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
692 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4);
693 tilemode[8] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
694 ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
695 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
696 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
697 NUM_BANKS(ADDR_SURF_16_BANK) |
698 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
699 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
700 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2);
701 tilemode[9] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
702 ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
703 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
704 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
705 NUM_BANKS(ADDR_SURF_16_BANK) |
706 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
707 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
708 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2);
709 tilemode[10] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
710 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
711 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
712 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
713 NUM_BANKS(ADDR_SURF_16_BANK) |
714 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
715 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
716 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4);
717 tilemode[11] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
718 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
719 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
720 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
721 NUM_BANKS(ADDR_SURF_16_BANK) |
722 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
723 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
724 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2);
725 tilemode[12] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
726 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
727 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
728 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
729 NUM_BANKS(ADDR_SURF_16_BANK) |
730 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
731 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
732 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2);
733 tilemode[13] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
734 ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
735 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
736 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
737 NUM_BANKS(ADDR_SURF_16_BANK) |
738 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
739 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
740 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2);
741 tilemode[14] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
742 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
743 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
744 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
745 NUM_BANKS(ADDR_SURF_16_BANK) |
746 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
747 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
748 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2);
749 tilemode[15] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
750 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
751 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
752 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
753 NUM_BANKS(ADDR_SURF_16_BANK) |
754 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
755 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
756 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2);
757 tilemode[16] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
758 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
759 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
760 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
761 NUM_BANKS(ADDR_SURF_16_BANK) |
762 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
763 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
764 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2);
765 tilemode[17] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
766 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
767 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
768 TILE_SPLIT(split_equal_to_row_size) |
769 NUM_BANKS(ADDR_SURF_16_BANK) |
770 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
771 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
772 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2);
773 tilemode[18] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
774 ARRAY_MODE(ARRAY_1D_TILED_THICK) |
775 PIPE_CONFIG(ADDR_SURF_P4_8x16);
776 tilemode[19] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
777 ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
778 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
779 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
780 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
781 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
782 NUM_BANKS(ADDR_SURF_16_BANK) |
783 TILE_SPLIT(split_equal_to_row_size);
784 tilemode[20] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
785 ARRAY_MODE(ARRAY_2D_TILED_THICK) |
786 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
787 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
788 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
789 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
790 NUM_BANKS(ADDR_SURF_16_BANK) |
791 TILE_SPLIT(split_equal_to_row_size);
792 tilemode[21] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
793 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
794 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
795 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
796 NUM_BANKS(ADDR_SURF_16_BANK) |
797 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
798 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
799 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2);
800 tilemode[22] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
801 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
802 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
803 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
804 NUM_BANKS(ADDR_SURF_16_BANK) |
805 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
806 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
807 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4);
808 tilemode[23] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
809 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
810 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
811 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
812 NUM_BANKS(ADDR_SURF_16_BANK) |
813 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
814 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
815 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2);
816 tilemode[24] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
817 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
818 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
819 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
820 NUM_BANKS(ADDR_SURF_16_BANK) |
821 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
822 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
823 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2);
824 tilemode[25] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
825 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
826 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
827 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
828 NUM_BANKS(ADDR_SURF_8_BANK) |
829 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
830 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
831 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1);
832 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
833 WREG32(mmGB_TILE_MODE0 + reg_offset, tilemode[reg_offset]);
834 } else if (adev->asic_type == CHIP_HAINAN) {
835 tilemode[0] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
836 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
837 PIPE_CONFIG(ADDR_SURF_P2) |
838 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
839 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
840 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
841 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
842 NUM_BANKS(ADDR_SURF_16_BANK);
843 tilemode[1] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
844 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
845 PIPE_CONFIG(ADDR_SURF_P2) |
846 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
847 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
848 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
849 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
850 NUM_BANKS(ADDR_SURF_16_BANK);
851 tilemode[2] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
852 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
853 PIPE_CONFIG(ADDR_SURF_P2) |
854 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
855 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
856 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
857 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
858 NUM_BANKS(ADDR_SURF_16_BANK);
859 tilemode[3] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
860 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
861 PIPE_CONFIG(ADDR_SURF_P2) |
862 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
863 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
864 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
865 NUM_BANKS(ADDR_SURF_8_BANK) |
866 TILE_SPLIT(split_equal_to_row_size);
867 tilemode[4] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
868 ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
869 PIPE_CONFIG(ADDR_SURF_P2);
870 tilemode[5] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
871 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
872 PIPE_CONFIG(ADDR_SURF_P2) |
873 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
874 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
875 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
876 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
877 NUM_BANKS(ADDR_SURF_8_BANK);
878 tilemode[6] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
879 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
880 PIPE_CONFIG(ADDR_SURF_P2) |
881 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
882 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
883 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
884 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
885 NUM_BANKS(ADDR_SURF_8_BANK);
886 tilemode[7] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
887 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
888 PIPE_CONFIG(ADDR_SURF_P2) |
889 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
890 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
891 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
892 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
893 NUM_BANKS(ADDR_SURF_4_BANK);
894 tilemode[8] = ARRAY_MODE(ARRAY_LINEAR_ALIGNED);
895 tilemode[9] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
896 ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
897 PIPE_CONFIG(ADDR_SURF_P2);
898 tilemode[10] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
899 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
900 PIPE_CONFIG(ADDR_SURF_P2) |
901 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
902 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
903 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
904 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
905 NUM_BANKS(ADDR_SURF_16_BANK);
906 tilemode[11] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
907 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
908 PIPE_CONFIG(ADDR_SURF_P2) |
909 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
910 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
911 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
912 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
913 NUM_BANKS(ADDR_SURF_16_BANK);
914 tilemode[12] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
915 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
916 PIPE_CONFIG(ADDR_SURF_P2) |
917 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
918 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
919 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
920 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
921 NUM_BANKS(ADDR_SURF_16_BANK);
922 tilemode[13] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
923 ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
924 PIPE_CONFIG(ADDR_SURF_P2);
925 tilemode[14] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
926 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
927 PIPE_CONFIG(ADDR_SURF_P2) |
928 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
929 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
930 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
931 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
932 NUM_BANKS(ADDR_SURF_16_BANK);
933 tilemode[15] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
934 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
935 PIPE_CONFIG(ADDR_SURF_P2) |
936 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
937 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
938 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
939 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
940 NUM_BANKS(ADDR_SURF_16_BANK);
941 tilemode[16] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
942 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
943 PIPE_CONFIG(ADDR_SURF_P2) |
944 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
945 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
946 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
947 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
948 NUM_BANKS(ADDR_SURF_16_BANK);
949 tilemode[17] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
950 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
951 PIPE_CONFIG(ADDR_SURF_P2) |
952 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
953 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
954 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
955 NUM_BANKS(ADDR_SURF_16_BANK) |
956 TILE_SPLIT(split_equal_to_row_size);
957 tilemode[18] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
958 ARRAY_MODE(ARRAY_1D_TILED_THICK) |
959 PIPE_CONFIG(ADDR_SURF_P2);
960 tilemode[19] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
961 ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
962 PIPE_CONFIG(ADDR_SURF_P2) |
963 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
964 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
965 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
966 NUM_BANKS(ADDR_SURF_16_BANK) |
967 TILE_SPLIT(split_equal_to_row_size);
968 tilemode[20] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
969 ARRAY_MODE(ARRAY_2D_TILED_THICK) |
970 PIPE_CONFIG(ADDR_SURF_P2) |
971 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
972 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
973 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
974 NUM_BANKS(ADDR_SURF_16_BANK) |
975 TILE_SPLIT(split_equal_to_row_size);
976 tilemode[21] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
977 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
978 PIPE_CONFIG(ADDR_SURF_P2) |
979 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
980 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
981 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
982 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
983 NUM_BANKS(ADDR_SURF_8_BANK);
984 tilemode[22] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
985 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
986 PIPE_CONFIG(ADDR_SURF_P2) |
987 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
988 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
989 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
990 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
991 NUM_BANKS(ADDR_SURF_8_BANK);
992 tilemode[23] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
993 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
994 PIPE_CONFIG(ADDR_SURF_P2) |
995 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
996 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
997 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
998 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
999 NUM_BANKS(ADDR_SURF_8_BANK);
1000 tilemode[24] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1001 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1002 PIPE_CONFIG(ADDR_SURF_P2) |
1003 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
1004 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1005 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1006 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1007 NUM_BANKS(ADDR_SURF_8_BANK);
1008 tilemode[25] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1009 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1010 PIPE_CONFIG(ADDR_SURF_P2) |
1011 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
1012 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1013 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1014 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1015 NUM_BANKS(ADDR_SURF_4_BANK);
1016 tilemode[26] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1017 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1018 PIPE_CONFIG(ADDR_SURF_P2) |
1019 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
1020 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1021 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1022 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1023 NUM_BANKS(ADDR_SURF_4_BANK);
1024 tilemode[27] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1025 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1026 PIPE_CONFIG(ADDR_SURF_P2) |
1027 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
1028 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1029 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1030 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1031 NUM_BANKS(ADDR_SURF_4_BANK);
1032 tilemode[28] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1033 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1034 PIPE_CONFIG(ADDR_SURF_P2) |
1035 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
1036 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1037 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1038 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1039 NUM_BANKS(ADDR_SURF_4_BANK);
1040 tilemode[29] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1041 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1042 PIPE_CONFIG(ADDR_SURF_P2) |
1043 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
1044 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1045 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1046 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1047 NUM_BANKS(ADDR_SURF_4_BANK);
1048 tilemode[30] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1049 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1050 PIPE_CONFIG(ADDR_SURF_P2) |
1051 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
1052 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1053 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1054 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1055 NUM_BANKS(ADDR_SURF_4_BANK);
1056 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
1057 WREG32(mmGB_TILE_MODE0 + reg_offset, tilemode[reg_offset]);
1058 } else if ((adev->asic_type == CHIP_TAHITI) || (adev->asic_type == CHIP_PITCAIRN)) {
1059 tilemode[0] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
1060 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1061 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1062 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
1063 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1064 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1065 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1066 NUM_BANKS(ADDR_SURF_16_BANK);
1067 tilemode[1] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
1068 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1069 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1070 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
1071 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1072 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1073 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1074 NUM_BANKS(ADDR_SURF_16_BANK);
1075 tilemode[2] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
1076 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1077 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1078 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1079 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1080 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1081 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1082 NUM_BANKS(ADDR_SURF_16_BANK);
1083 tilemode[3] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
1084 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1085 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1086 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1087 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1088 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1089 NUM_BANKS(ADDR_SURF_4_BANK) |
1090 TILE_SPLIT(split_equal_to_row_size);
1091 tilemode[4] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
1092 ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1093 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16);
1094 tilemode[5] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
1095 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1096 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1097 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
1098 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1099 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1100 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1101 NUM_BANKS(ADDR_SURF_2_BANK);
1102 tilemode[6] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
1103 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1104 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1105 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1106 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1107 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
1108 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1109 NUM_BANKS(ADDR_SURF_2_BANK);
1110 tilemode[7] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
1111 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1112 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
1113 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
1114 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1115 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1116 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1117 NUM_BANKS(ADDR_SURF_2_BANK);
1118 tilemode[8] = ARRAY_MODE(ARRAY_LINEAR_ALIGNED);
1119 tilemode[9] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
1120 ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1121 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16);
1122 tilemode[10] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
1123 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1124 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1125 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1126 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1127 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1128 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1129 NUM_BANKS(ADDR_SURF_16_BANK);
1130 tilemode[11] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
1131 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1132 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1133 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1134 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1135 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1136 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1137 NUM_BANKS(ADDR_SURF_16_BANK);
1138 tilemode[12] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
1139 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1140 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1141 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
1142 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1143 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1144 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1145 NUM_BANKS(ADDR_SURF_16_BANK);
1146 tilemode[13] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1147 ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1148 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16);
1149 tilemode[14] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1150 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1151 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1152 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1153 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1154 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1155 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1156 NUM_BANKS(ADDR_SURF_16_BANK);
1157 tilemode[15] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1158 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1159 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1160 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1161 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1162 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1163 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1164 NUM_BANKS(ADDR_SURF_16_BANK);
1165 tilemode[16] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1166 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1167 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1168 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
1169 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1170 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1171 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1172 NUM_BANKS(ADDR_SURF_16_BANK);
1173 tilemode[17] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1174 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1175 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1176 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1177 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1178 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1179 NUM_BANKS(ADDR_SURF_16_BANK) |
1180 TILE_SPLIT(split_equal_to_row_size);
1181 tilemode[18] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1182 ARRAY_MODE(ARRAY_1D_TILED_THICK) |
1183 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16);
1184 tilemode[19] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1185 ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
1186 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1187 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1188 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1189 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1190 NUM_BANKS(ADDR_SURF_16_BANK) |
1191 TILE_SPLIT(split_equal_to_row_size);
1192 tilemode[20] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1193 ARRAY_MODE(ARRAY_2D_TILED_THICK) |
1194 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1195 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1196 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1197 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1198 NUM_BANKS(ADDR_SURF_16_BANK) |
1199 TILE_SPLIT(split_equal_to_row_size);
1200 tilemode[21] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1201 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1202 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1203 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1204 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1205 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
1206 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1207 NUM_BANKS(ADDR_SURF_4_BANK);
1208 tilemode[22] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1209 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1210 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1211 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1212 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1213 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1214 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1215 NUM_BANKS(ADDR_SURF_4_BANK);
1216 tilemode[23] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1217 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1218 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1219 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1220 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1221 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
1222 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1223 NUM_BANKS(ADDR_SURF_2_BANK);
1224 tilemode[24] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1225 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1226 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1227 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
1228 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1229 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1230 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1231 NUM_BANKS(ADDR_SURF_2_BANK);
1232 tilemode[25] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1233 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1234 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
1235 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
1236 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1237 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1238 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1239 NUM_BANKS(ADDR_SURF_2_BANK);
1240 tilemode[26] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1241 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1242 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
1243 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
1244 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1245 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1246 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1247 NUM_BANKS(ADDR_SURF_2_BANK);
1248 tilemode[27] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1249 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1250 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
1251 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
1252 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1253 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1254 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1255 NUM_BANKS(ADDR_SURF_2_BANK);
1256 tilemode[28] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1257 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1258 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
1259 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
1260 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1261 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1262 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1263 NUM_BANKS(ADDR_SURF_2_BANK);
1264 tilemode[29] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1265 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1266 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
1267 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
1268 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1269 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1270 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1271 NUM_BANKS(ADDR_SURF_2_BANK);
1272 tilemode[30] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1273 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1274 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
1275 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
1276 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1277 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1278 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1279 NUM_BANKS(ADDR_SURF_2_BANK);
1280 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
1281 WREG32(mmGB_TILE_MODE0 + reg_offset, tilemode[reg_offset]);
1283 DRM_ERROR("unknown asic: 0x%x\n", adev->asic_type);
1287 static void gfx_v6_0_select_se_sh(struct amdgpu_device *adev, u32 se_num,
1288 u32 sh_num, u32 instance, int xcc_id)
1292 if (instance == 0xffffffff)
1293 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES, 1);
1295 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_INDEX, instance);
1297 if ((se_num == 0xffffffff) && (sh_num == 0xffffffff))
1298 data |= GRBM_GFX_INDEX__SH_BROADCAST_WRITES_MASK |
1299 GRBM_GFX_INDEX__SE_BROADCAST_WRITES_MASK;
1300 else if (se_num == 0xffffffff)
1301 data |= GRBM_GFX_INDEX__SE_BROADCAST_WRITES_MASK |
1302 (sh_num << GRBM_GFX_INDEX__SH_INDEX__SHIFT);
1303 else if (sh_num == 0xffffffff)
1304 data |= GRBM_GFX_INDEX__SH_BROADCAST_WRITES_MASK |
1305 (se_num << GRBM_GFX_INDEX__SE_INDEX__SHIFT);
1307 data |= (sh_num << GRBM_GFX_INDEX__SH_INDEX__SHIFT) |
1308 (se_num << GRBM_GFX_INDEX__SE_INDEX__SHIFT);
1309 WREG32(mmGRBM_GFX_INDEX, data);
1312 static u32 gfx_v6_0_get_rb_active_bitmap(struct amdgpu_device *adev)
1316 data = RREG32(mmCC_RB_BACKEND_DISABLE) |
1317 RREG32(mmGC_USER_RB_BACKEND_DISABLE);
1319 data = REG_GET_FIELD(data, GC_USER_RB_BACKEND_DISABLE, BACKEND_DISABLE);
1321 mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_backends_per_se/
1322 adev->gfx.config.max_sh_per_se);
1324 return ~data & mask;
1327 static void gfx_v6_0_raster_config(struct amdgpu_device *adev, u32 *rconf)
1329 switch (adev->asic_type) {
1333 (2 << PA_SC_RASTER_CONFIG__RB_XSEL2__SHIFT) |
1334 (1 << PA_SC_RASTER_CONFIG__RB_XSEL__SHIFT) |
1335 (2 << PA_SC_RASTER_CONFIG__PKR_MAP__SHIFT) |
1336 (1 << PA_SC_RASTER_CONFIG__PKR_YSEL__SHIFT) |
1337 (2 << PA_SC_RASTER_CONFIG__SE_MAP__SHIFT) |
1338 (2 << PA_SC_RASTER_CONFIG__SE_XSEL__SHIFT) |
1339 (2 << PA_SC_RASTER_CONFIG__SE_YSEL__SHIFT);
1343 (1 << PA_SC_RASTER_CONFIG__RB_XSEL__SHIFT) |
1344 (2 << PA_SC_RASTER_CONFIG__PKR_MAP__SHIFT) |
1345 (1 << PA_SC_RASTER_CONFIG__PKR_YSEL__SHIFT);
1348 *rconf |= (1 << PA_SC_RASTER_CONFIG__RB_YSEL__SHIFT);
1354 DRM_ERROR("unknown asic: 0x%x\n", adev->asic_type);
1359 static void gfx_v6_0_write_harvested_raster_configs(struct amdgpu_device *adev,
1360 u32 raster_config, unsigned rb_mask,
1363 unsigned sh_per_se = max_t(unsigned, adev->gfx.config.max_sh_per_se, 1);
1364 unsigned num_se = max_t(unsigned, adev->gfx.config.max_shader_engines, 1);
1365 unsigned rb_per_pkr = min_t(unsigned, num_rb / num_se / sh_per_se, 2);
1366 unsigned rb_per_se = num_rb / num_se;
1367 unsigned se_mask[4];
1370 se_mask[0] = ((1 << rb_per_se) - 1) & rb_mask;
1371 se_mask[1] = (se_mask[0] << rb_per_se) & rb_mask;
1372 se_mask[2] = (se_mask[1] << rb_per_se) & rb_mask;
1373 se_mask[3] = (se_mask[2] << rb_per_se) & rb_mask;
1375 WARN_ON(!(num_se == 1 || num_se == 2 || num_se == 4));
1376 WARN_ON(!(sh_per_se == 1 || sh_per_se == 2));
1377 WARN_ON(!(rb_per_pkr == 1 || rb_per_pkr == 2));
1379 for (se = 0; se < num_se; se++) {
1380 unsigned raster_config_se = raster_config;
1381 unsigned pkr0_mask = ((1 << rb_per_pkr) - 1) << (se * rb_per_se);
1382 unsigned pkr1_mask = pkr0_mask << rb_per_pkr;
1383 int idx = (se / 2) * 2;
1385 if ((num_se > 1) && (!se_mask[idx] || !se_mask[idx + 1])) {
1386 raster_config_se &= ~PA_SC_RASTER_CONFIG__SE_MAP_MASK;
1389 raster_config_se |= RASTER_CONFIG_SE_MAP_3 << PA_SC_RASTER_CONFIG__SE_MAP__SHIFT;
1391 raster_config_se |= RASTER_CONFIG_SE_MAP_0 << PA_SC_RASTER_CONFIG__SE_MAP__SHIFT;
1394 pkr0_mask &= rb_mask;
1395 pkr1_mask &= rb_mask;
1396 if (rb_per_se > 2 && (!pkr0_mask || !pkr1_mask)) {
1397 raster_config_se &= ~PA_SC_RASTER_CONFIG__PKR_MAP_MASK;
1400 raster_config_se |= RASTER_CONFIG_PKR_MAP_3 << PA_SC_RASTER_CONFIG__PKR_MAP__SHIFT;
1402 raster_config_se |= RASTER_CONFIG_PKR_MAP_0 << PA_SC_RASTER_CONFIG__PKR_MAP__SHIFT;
1405 if (rb_per_se >= 2) {
1406 unsigned rb0_mask = 1 << (se * rb_per_se);
1407 unsigned rb1_mask = rb0_mask << 1;
1409 rb0_mask &= rb_mask;
1410 rb1_mask &= rb_mask;
1411 if (!rb0_mask || !rb1_mask) {
1412 raster_config_se &= ~PA_SC_RASTER_CONFIG__RB_MAP_PKR0_MASK;
1416 RASTER_CONFIG_RB_MAP_3 << PA_SC_RASTER_CONFIG__RB_MAP_PKR0__SHIFT;
1419 RASTER_CONFIG_RB_MAP_0 << PA_SC_RASTER_CONFIG__RB_MAP_PKR0__SHIFT;
1422 if (rb_per_se > 2) {
1423 rb0_mask = 1 << (se * rb_per_se + rb_per_pkr);
1424 rb1_mask = rb0_mask << 1;
1425 rb0_mask &= rb_mask;
1426 rb1_mask &= rb_mask;
1427 if (!rb0_mask || !rb1_mask) {
1428 raster_config_se &= ~PA_SC_RASTER_CONFIG__RB_MAP_PKR1_MASK;
1432 RASTER_CONFIG_RB_MAP_3 << PA_SC_RASTER_CONFIG__RB_MAP_PKR1__SHIFT;
1435 RASTER_CONFIG_RB_MAP_0 << PA_SC_RASTER_CONFIG__RB_MAP_PKR1__SHIFT;
1440 /* GRBM_GFX_INDEX has a different offset on SI */
1441 gfx_v6_0_select_se_sh(adev, se, 0xffffffff, 0xffffffff, 0);
1442 WREG32(mmPA_SC_RASTER_CONFIG, raster_config_se);
1445 /* GRBM_GFX_INDEX has a different offset on SI */
1446 gfx_v6_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0);
1449 static void gfx_v6_0_setup_rb(struct amdgpu_device *adev)
1453 u32 raster_config = 0;
1455 u32 rb_bitmap_width_per_sh = adev->gfx.config.max_backends_per_se /
1456 adev->gfx.config.max_sh_per_se;
1457 unsigned num_rb_pipes;
1459 mutex_lock(&adev->grbm_idx_mutex);
1460 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
1461 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
1462 gfx_v6_0_select_se_sh(adev, i, j, 0xffffffff, 0);
1463 data = gfx_v6_0_get_rb_active_bitmap(adev);
1464 active_rbs |= data <<
1465 ((i * adev->gfx.config.max_sh_per_se + j) *
1466 rb_bitmap_width_per_sh);
1469 gfx_v6_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0);
1471 adev->gfx.config.backend_enable_mask = active_rbs;
1472 adev->gfx.config.num_rbs = hweight32(active_rbs);
1474 num_rb_pipes = min_t(unsigned, adev->gfx.config.max_backends_per_se *
1475 adev->gfx.config.max_shader_engines, 16);
1477 gfx_v6_0_raster_config(adev, &raster_config);
1479 if (!adev->gfx.config.backend_enable_mask ||
1480 adev->gfx.config.num_rbs >= num_rb_pipes)
1481 WREG32(mmPA_SC_RASTER_CONFIG, raster_config);
1483 gfx_v6_0_write_harvested_raster_configs(adev, raster_config,
1484 adev->gfx.config.backend_enable_mask,
1487 /* cache the values for userspace */
1488 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
1489 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
1490 gfx_v6_0_select_se_sh(adev, i, j, 0xffffffff, 0);
1491 adev->gfx.config.rb_config[i][j].rb_backend_disable =
1492 RREG32(mmCC_RB_BACKEND_DISABLE);
1493 adev->gfx.config.rb_config[i][j].user_rb_backend_disable =
1494 RREG32(mmGC_USER_RB_BACKEND_DISABLE);
1495 adev->gfx.config.rb_config[i][j].raster_config =
1496 RREG32(mmPA_SC_RASTER_CONFIG);
1499 gfx_v6_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0);
1500 mutex_unlock(&adev->grbm_idx_mutex);
1503 static void gfx_v6_0_set_user_cu_inactive_bitmap(struct amdgpu_device *adev,
1511 data = bitmap << GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT;
1512 data &= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK;
1514 WREG32(mmGC_USER_SHADER_ARRAY_CONFIG, data);
1517 static u32 gfx_v6_0_get_cu_enabled(struct amdgpu_device *adev)
1521 data = RREG32(mmCC_GC_SHADER_ARRAY_CONFIG) |
1522 RREG32(mmGC_USER_SHADER_ARRAY_CONFIG);
1524 mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_cu_per_sh);
1525 return ~REG_GET_FIELD(data, CC_GC_SHADER_ARRAY_CONFIG, INACTIVE_CUS) & mask;
1529 static void gfx_v6_0_setup_spi(struct amdgpu_device *adev)
1535 mutex_lock(&adev->grbm_idx_mutex);
1536 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
1537 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
1538 gfx_v6_0_select_se_sh(adev, i, j, 0xffffffff, 0);
1539 data = RREG32(mmSPI_STATIC_THREAD_MGMT_3);
1540 active_cu = gfx_v6_0_get_cu_enabled(adev);
1543 for (k = 0; k < 16; k++) {
1545 if (active_cu & mask) {
1547 WREG32(mmSPI_STATIC_THREAD_MGMT_3, data);
1553 gfx_v6_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0);
1554 mutex_unlock(&adev->grbm_idx_mutex);
1557 static void gfx_v6_0_config_init(struct amdgpu_device *adev)
1559 adev->gfx.config.double_offchip_lds_buf = 0;
1562 static void gfx_v6_0_constants_init(struct amdgpu_device *adev)
1564 u32 gb_addr_config = 0;
1567 u32 hdp_host_path_cntl;
1570 switch (adev->asic_type) {
1572 adev->gfx.config.max_shader_engines = 2;
1573 adev->gfx.config.max_tile_pipes = 12;
1574 adev->gfx.config.max_cu_per_sh = 8;
1575 adev->gfx.config.max_sh_per_se = 2;
1576 adev->gfx.config.max_backends_per_se = 4;
1577 adev->gfx.config.max_texture_channel_caches = 12;
1578 adev->gfx.config.max_gprs = 256;
1579 adev->gfx.config.max_gs_threads = 32;
1580 adev->gfx.config.max_hw_contexts = 8;
1582 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
1583 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
1584 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
1585 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
1586 gb_addr_config = TAHITI_GB_ADDR_CONFIG_GOLDEN;
1589 adev->gfx.config.max_shader_engines = 2;
1590 adev->gfx.config.max_tile_pipes = 8;
1591 adev->gfx.config.max_cu_per_sh = 5;
1592 adev->gfx.config.max_sh_per_se = 2;
1593 adev->gfx.config.max_backends_per_se = 4;
1594 adev->gfx.config.max_texture_channel_caches = 8;
1595 adev->gfx.config.max_gprs = 256;
1596 adev->gfx.config.max_gs_threads = 32;
1597 adev->gfx.config.max_hw_contexts = 8;
1599 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
1600 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
1601 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
1602 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
1603 gb_addr_config = TAHITI_GB_ADDR_CONFIG_GOLDEN;
1606 adev->gfx.config.max_shader_engines = 1;
1607 adev->gfx.config.max_tile_pipes = 4;
1608 adev->gfx.config.max_cu_per_sh = 5;
1609 adev->gfx.config.max_sh_per_se = 2;
1610 adev->gfx.config.max_backends_per_se = 4;
1611 adev->gfx.config.max_texture_channel_caches = 4;
1612 adev->gfx.config.max_gprs = 256;
1613 adev->gfx.config.max_gs_threads = 32;
1614 adev->gfx.config.max_hw_contexts = 8;
1616 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
1617 adev->gfx.config.sc_prim_fifo_size_backend = 0x40;
1618 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
1619 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
1620 gb_addr_config = VERDE_GB_ADDR_CONFIG_GOLDEN;
1623 adev->gfx.config.max_shader_engines = 1;
1624 adev->gfx.config.max_tile_pipes = 4;
1625 adev->gfx.config.max_cu_per_sh = 6;
1626 adev->gfx.config.max_sh_per_se = 1;
1627 adev->gfx.config.max_backends_per_se = 2;
1628 adev->gfx.config.max_texture_channel_caches = 4;
1629 adev->gfx.config.max_gprs = 256;
1630 adev->gfx.config.max_gs_threads = 16;
1631 adev->gfx.config.max_hw_contexts = 8;
1633 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
1634 adev->gfx.config.sc_prim_fifo_size_backend = 0x40;
1635 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
1636 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
1637 gb_addr_config = VERDE_GB_ADDR_CONFIG_GOLDEN;
1640 adev->gfx.config.max_shader_engines = 1;
1641 adev->gfx.config.max_tile_pipes = 4;
1642 adev->gfx.config.max_cu_per_sh = 5;
1643 adev->gfx.config.max_sh_per_se = 1;
1644 adev->gfx.config.max_backends_per_se = 1;
1645 adev->gfx.config.max_texture_channel_caches = 2;
1646 adev->gfx.config.max_gprs = 256;
1647 adev->gfx.config.max_gs_threads = 16;
1648 adev->gfx.config.max_hw_contexts = 8;
1650 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
1651 adev->gfx.config.sc_prim_fifo_size_backend = 0x40;
1652 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
1653 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
1654 gb_addr_config = HAINAN_GB_ADDR_CONFIG_GOLDEN;
1661 WREG32(mmGRBM_CNTL, (0xff << GRBM_CNTL__READ_TIMEOUT__SHIFT));
1662 WREG32(mmSRBM_INT_CNTL, 1);
1663 WREG32(mmSRBM_INT_ACK, 1);
1665 WREG32(mmBIF_FB_EN, BIF_FB_EN__FB_READ_EN_MASK | BIF_FB_EN__FB_WRITE_EN_MASK);
1667 adev->gfx.config.mc_arb_ramcfg = RREG32(mmMC_ARB_RAMCFG);
1668 mc_arb_ramcfg = adev->gfx.config.mc_arb_ramcfg;
1670 adev->gfx.config.num_tile_pipes = adev->gfx.config.max_tile_pipes;
1671 adev->gfx.config.mem_max_burst_length_bytes = 256;
1672 tmp = (mc_arb_ramcfg & MC_ARB_RAMCFG__NOOFCOLS_MASK) >> MC_ARB_RAMCFG__NOOFCOLS__SHIFT;
1673 adev->gfx.config.mem_row_size_in_kb = (4 * (1 << (8 + tmp))) / 1024;
1674 if (adev->gfx.config.mem_row_size_in_kb > 4)
1675 adev->gfx.config.mem_row_size_in_kb = 4;
1676 adev->gfx.config.shader_engine_tile_size = 32;
1677 adev->gfx.config.num_gpus = 1;
1678 adev->gfx.config.multi_gpu_tile_size = 64;
1680 gb_addr_config &= ~GB_ADDR_CONFIG__ROW_SIZE_MASK;
1681 switch (adev->gfx.config.mem_row_size_in_kb) {
1684 gb_addr_config |= 0 << GB_ADDR_CONFIG__ROW_SIZE__SHIFT;
1687 gb_addr_config |= 1 << GB_ADDR_CONFIG__ROW_SIZE__SHIFT;
1690 gb_addr_config |= 2 << GB_ADDR_CONFIG__ROW_SIZE__SHIFT;
1693 gb_addr_config &= ~GB_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK;
1694 if (adev->gfx.config.max_shader_engines == 2)
1695 gb_addr_config |= 1 << GB_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT;
1696 adev->gfx.config.gb_addr_config = gb_addr_config;
1698 WREG32(mmGB_ADDR_CONFIG, gb_addr_config);
1699 WREG32(mmDMIF_ADDR_CONFIG, gb_addr_config);
1700 WREG32(mmDMIF_ADDR_CALC, gb_addr_config);
1701 WREG32(mmHDP_ADDR_CONFIG, gb_addr_config);
1702 WREG32(mmDMA_TILING_CONFIG + DMA0_REGISTER_OFFSET, gb_addr_config);
1703 WREG32(mmDMA_TILING_CONFIG + DMA1_REGISTER_OFFSET, gb_addr_config);
1706 if (adev->has_uvd) {
1707 WREG32(mmUVD_UDEC_ADDR_CONFIG, gb_addr_config);
1708 WREG32(mmUVD_UDEC_DB_ADDR_CONFIG, gb_addr_config);
1709 WREG32(mmUVD_UDEC_DBW_ADDR_CONFIG, gb_addr_config);
1712 gfx_v6_0_tiling_mode_table_init(adev);
1714 gfx_v6_0_setup_rb(adev);
1716 gfx_v6_0_setup_spi(adev);
1718 gfx_v6_0_get_cu_info(adev);
1719 gfx_v6_0_config_init(adev);
1721 WREG32(mmCP_QUEUE_THRESHOLDS, ((0x16 << CP_QUEUE_THRESHOLDS__ROQ_IB1_START__SHIFT) |
1722 (0x2b << CP_QUEUE_THRESHOLDS__ROQ_IB2_START__SHIFT)));
1723 WREG32(mmCP_MEQ_THRESHOLDS, (0x30 << CP_MEQ_THRESHOLDS__MEQ1_START__SHIFT) |
1724 (0x60 << CP_MEQ_THRESHOLDS__MEQ2_START__SHIFT));
1726 sx_debug_1 = RREG32(mmSX_DEBUG_1);
1727 WREG32(mmSX_DEBUG_1, sx_debug_1);
1729 WREG32(mmSPI_CONFIG_CNTL_1, (4 << SPI_CONFIG_CNTL_1__VTX_DONE_DELAY__SHIFT));
1731 WREG32(mmPA_SC_FIFO_SIZE, ((adev->gfx.config.sc_prim_fifo_size_frontend << PA_SC_FIFO_SIZE__SC_FRONTEND_PRIM_FIFO_SIZE__SHIFT) |
1732 (adev->gfx.config.sc_prim_fifo_size_backend << PA_SC_FIFO_SIZE__SC_BACKEND_PRIM_FIFO_SIZE__SHIFT) |
1733 (adev->gfx.config.sc_hiz_tile_fifo_size << PA_SC_FIFO_SIZE__SC_HIZ_TILE_FIFO_SIZE__SHIFT) |
1734 (adev->gfx.config.sc_earlyz_tile_fifo_size << PA_SC_FIFO_SIZE__SC_EARLYZ_TILE_FIFO_SIZE__SHIFT)));
1736 WREG32(mmVGT_NUM_INSTANCES, 1);
1737 WREG32(mmCP_PERFMON_CNTL, 0);
1738 WREG32(mmSQ_CONFIG, 0);
1739 WREG32(mmPA_SC_FORCE_EOV_MAX_CNTS, ((4095 << PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_CLK_CNT__SHIFT) |
1740 (255 << PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_REZ_CNT__SHIFT)));
1742 WREG32(mmVGT_CACHE_INVALIDATION,
1743 (VC_AND_TC << VGT_CACHE_INVALIDATION__CACHE_INVALIDATION__SHIFT) |
1744 (ES_AND_GS_AUTO << VGT_CACHE_INVALIDATION__AUTO_INVLD_EN__SHIFT));
1746 WREG32(mmVGT_GS_VERTEX_REUSE, 16);
1747 WREG32(mmPA_SC_LINE_STIPPLE_STATE, 0);
1749 WREG32(mmCB_PERFCOUNTER0_SELECT0, 0);
1750 WREG32(mmCB_PERFCOUNTER0_SELECT1, 0);
1751 WREG32(mmCB_PERFCOUNTER1_SELECT0, 0);
1752 WREG32(mmCB_PERFCOUNTER1_SELECT1, 0);
1753 WREG32(mmCB_PERFCOUNTER2_SELECT0, 0);
1754 WREG32(mmCB_PERFCOUNTER2_SELECT1, 0);
1755 WREG32(mmCB_PERFCOUNTER3_SELECT0, 0);
1756 WREG32(mmCB_PERFCOUNTER3_SELECT1, 0);
1758 hdp_host_path_cntl = RREG32(mmHDP_HOST_PATH_CNTL);
1759 WREG32(mmHDP_HOST_PATH_CNTL, hdp_host_path_cntl);
1761 WREG32(mmPA_CL_ENHANCE, PA_CL_ENHANCE__CLIP_VTX_REORDER_ENA_MASK |
1762 (3 << PA_CL_ENHANCE__NUM_CLIP_SEQ__SHIFT));
1767 static int gfx_v6_0_ring_test_ring(struct amdgpu_ring *ring)
1769 struct amdgpu_device *adev = ring->adev;
1774 WREG32(mmSCRATCH_REG0, 0xCAFEDEAD);
1776 r = amdgpu_ring_alloc(ring, 3);
1780 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
1781 amdgpu_ring_write(ring, mmSCRATCH_REG0 - PACKET3_SET_CONFIG_REG_START);
1782 amdgpu_ring_write(ring, 0xDEADBEEF);
1783 amdgpu_ring_commit(ring);
1785 for (i = 0; i < adev->usec_timeout; i++) {
1786 tmp = RREG32(mmSCRATCH_REG0);
1787 if (tmp == 0xDEADBEEF)
1792 if (i >= adev->usec_timeout)
1797 static void gfx_v6_0_ring_emit_vgt_flush(struct amdgpu_ring *ring)
1799 amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE, 0));
1800 amdgpu_ring_write(ring, EVENT_TYPE(VGT_FLUSH) |
1804 static void gfx_v6_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr,
1805 u64 seq, unsigned flags)
1807 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
1808 bool int_sel = flags & AMDGPU_FENCE_FLAG_INT;
1809 /* flush read cache over gart */
1810 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
1811 amdgpu_ring_write(ring, (mmCP_COHER_CNTL2 - PACKET3_SET_CONFIG_REG_START));
1812 amdgpu_ring_write(ring, 0);
1813 amdgpu_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3));
1814 amdgpu_ring_write(ring, PACKET3_TCL1_ACTION_ENA |
1815 PACKET3_TC_ACTION_ENA |
1816 PACKET3_SH_KCACHE_ACTION_ENA |
1817 PACKET3_SH_ICACHE_ACTION_ENA);
1818 amdgpu_ring_write(ring, 0xFFFFFFFF);
1819 amdgpu_ring_write(ring, 0);
1820 amdgpu_ring_write(ring, 10); /* poll interval */
1821 /* EVENT_WRITE_EOP - flush caches, send int */
1822 amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4));
1823 amdgpu_ring_write(ring, EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) | EVENT_INDEX(5));
1824 amdgpu_ring_write(ring, addr & 0xfffffffc);
1825 amdgpu_ring_write(ring, (upper_32_bits(addr) & 0xffff) |
1826 ((write64bit ? 2 : 1) << CP_EOP_DONE_DATA_CNTL__DATA_SEL__SHIFT) |
1827 ((int_sel ? 2 : 0) << CP_EOP_DONE_DATA_CNTL__INT_SEL__SHIFT));
1828 amdgpu_ring_write(ring, lower_32_bits(seq));
1829 amdgpu_ring_write(ring, upper_32_bits(seq));
1832 static void gfx_v6_0_ring_emit_ib(struct amdgpu_ring *ring,
1833 struct amdgpu_job *job,
1834 struct amdgpu_ib *ib,
1837 unsigned vmid = AMDGPU_JOB_GET_VMID(job);
1838 u32 header, control = 0;
1840 /* insert SWITCH_BUFFER packet before first IB in the ring frame */
1841 if (flags & AMDGPU_HAVE_CTX_SWITCH) {
1842 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
1843 amdgpu_ring_write(ring, 0);
1846 if (ib->flags & AMDGPU_IB_FLAG_CE)
1847 header = PACKET3(PACKET3_INDIRECT_BUFFER_CONST, 2);
1849 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2);
1851 control |= ib->length_dw | (vmid << 24);
1853 amdgpu_ring_write(ring, header);
1854 amdgpu_ring_write(ring,
1858 (ib->gpu_addr & 0xFFFFFFFC));
1859 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFFFF);
1860 amdgpu_ring_write(ring, control);
1864 * gfx_v6_0_ring_test_ib - basic ring IB test
1866 * @ring: amdgpu_ring structure holding ring information
1867 * @timeout: timeout value in jiffies, or MAX_SCHEDULE_TIMEOUT
1869 * Allocate an IB and execute it on the gfx ring (SI).
1870 * Provides a basic gfx ring test to verify that IBs are working.
1871 * Returns 0 on success, error on failure.
1873 static int gfx_v6_0_ring_test_ib(struct amdgpu_ring *ring, long timeout)
1875 struct amdgpu_device *adev = ring->adev;
1876 struct dma_fence *f = NULL;
1877 struct amdgpu_ib ib;
1881 WREG32(mmSCRATCH_REG0, 0xCAFEDEAD);
1882 memset(&ib, 0, sizeof(ib));
1883 r = amdgpu_ib_get(adev, NULL, 256, AMDGPU_IB_POOL_DIRECT, &ib);
1887 ib.ptr[0] = PACKET3(PACKET3_SET_CONFIG_REG, 1);
1888 ib.ptr[1] = mmSCRATCH_REG0 - PACKET3_SET_CONFIG_REG_START;
1889 ib.ptr[2] = 0xDEADBEEF;
1892 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
1896 r = dma_fence_wait_timeout(f, false, timeout);
1903 tmp = RREG32(mmSCRATCH_REG0);
1904 if (tmp == 0xDEADBEEF)
1910 amdgpu_ib_free(adev, &ib, NULL);
1915 static void gfx_v6_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable)
1918 WREG32(mmCP_ME_CNTL, 0);
1920 WREG32(mmCP_ME_CNTL, (CP_ME_CNTL__ME_HALT_MASK |
1921 CP_ME_CNTL__PFP_HALT_MASK |
1922 CP_ME_CNTL__CE_HALT_MASK));
1923 WREG32(mmSCRATCH_UMSK, 0);
1928 static int gfx_v6_0_cp_gfx_load_microcode(struct amdgpu_device *adev)
1931 const struct gfx_firmware_header_v1_0 *pfp_hdr;
1932 const struct gfx_firmware_header_v1_0 *ce_hdr;
1933 const struct gfx_firmware_header_v1_0 *me_hdr;
1934 const __le32 *fw_data;
1937 if (!adev->gfx.me_fw || !adev->gfx.pfp_fw || !adev->gfx.ce_fw)
1940 gfx_v6_0_cp_gfx_enable(adev, false);
1941 pfp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data;
1942 ce_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data;
1943 me_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data;
1945 amdgpu_ucode_print_gfx_hdr(&pfp_hdr->header);
1946 amdgpu_ucode_print_gfx_hdr(&ce_hdr->header);
1947 amdgpu_ucode_print_gfx_hdr(&me_hdr->header);
1950 fw_data = (const __le32 *)
1951 (adev->gfx.pfp_fw->data + le32_to_cpu(pfp_hdr->header.ucode_array_offset_bytes));
1952 fw_size = le32_to_cpu(pfp_hdr->header.ucode_size_bytes) / 4;
1953 WREG32(mmCP_PFP_UCODE_ADDR, 0);
1954 for (i = 0; i < fw_size; i++)
1955 WREG32(mmCP_PFP_UCODE_DATA, le32_to_cpup(fw_data++));
1956 WREG32(mmCP_PFP_UCODE_ADDR, 0);
1959 fw_data = (const __le32 *)
1960 (adev->gfx.ce_fw->data + le32_to_cpu(ce_hdr->header.ucode_array_offset_bytes));
1961 fw_size = le32_to_cpu(ce_hdr->header.ucode_size_bytes) / 4;
1962 WREG32(mmCP_CE_UCODE_ADDR, 0);
1963 for (i = 0; i < fw_size; i++)
1964 WREG32(mmCP_CE_UCODE_DATA, le32_to_cpup(fw_data++));
1965 WREG32(mmCP_CE_UCODE_ADDR, 0);
1968 fw_data = (const __be32 *)
1969 (adev->gfx.me_fw->data + le32_to_cpu(me_hdr->header.ucode_array_offset_bytes));
1970 fw_size = le32_to_cpu(me_hdr->header.ucode_size_bytes) / 4;
1971 WREG32(mmCP_ME_RAM_WADDR, 0);
1972 for (i = 0; i < fw_size; i++)
1973 WREG32(mmCP_ME_RAM_DATA, le32_to_cpup(fw_data++));
1974 WREG32(mmCP_ME_RAM_WADDR, 0);
1976 WREG32(mmCP_PFP_UCODE_ADDR, 0);
1977 WREG32(mmCP_CE_UCODE_ADDR, 0);
1978 WREG32(mmCP_ME_RAM_WADDR, 0);
1979 WREG32(mmCP_ME_RAM_RADDR, 0);
1983 static int gfx_v6_0_cp_gfx_start(struct amdgpu_device *adev)
1985 const struct cs_section_def *sect = NULL;
1986 const struct cs_extent_def *ext = NULL;
1987 struct amdgpu_ring *ring = &adev->gfx.gfx_ring[0];
1990 r = amdgpu_ring_alloc(ring, 7 + 4);
1992 DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r);
1995 amdgpu_ring_write(ring, PACKET3(PACKET3_ME_INITIALIZE, 5));
1996 amdgpu_ring_write(ring, 0x1);
1997 amdgpu_ring_write(ring, 0x0);
1998 amdgpu_ring_write(ring, adev->gfx.config.max_hw_contexts - 1);
1999 amdgpu_ring_write(ring, PACKET3_ME_INITIALIZE_DEVICE_ID(1));
2000 amdgpu_ring_write(ring, 0);
2001 amdgpu_ring_write(ring, 0);
2003 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2));
2004 amdgpu_ring_write(ring, PACKET3_BASE_INDEX(CE_PARTITION_BASE));
2005 amdgpu_ring_write(ring, 0xc000);
2006 amdgpu_ring_write(ring, 0xe000);
2007 amdgpu_ring_commit(ring);
2009 gfx_v6_0_cp_gfx_enable(adev, true);
2011 r = amdgpu_ring_alloc(ring, gfx_v6_0_get_csb_size(adev) + 10);
2013 DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r);
2017 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
2018 amdgpu_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
2020 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) {
2021 for (ext = sect->section; ext->extent != NULL; ++ext) {
2022 if (sect->id == SECT_CONTEXT) {
2023 amdgpu_ring_write(ring,
2024 PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count));
2025 amdgpu_ring_write(ring, ext->reg_index - PACKET3_SET_CONTEXT_REG_START);
2026 for (i = 0; i < ext->reg_count; i++)
2027 amdgpu_ring_write(ring, ext->extent[i]);
2032 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
2033 amdgpu_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE);
2035 amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));
2036 amdgpu_ring_write(ring, 0);
2038 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 2));
2039 amdgpu_ring_write(ring, 0x00000316);
2040 amdgpu_ring_write(ring, 0x0000000e);
2041 amdgpu_ring_write(ring, 0x00000010);
2043 amdgpu_ring_commit(ring);
2048 static int gfx_v6_0_cp_gfx_resume(struct amdgpu_device *adev)
2050 struct amdgpu_ring *ring;
2056 WREG32(mmCP_SEM_WAIT_TIMER, 0x0);
2057 WREG32(mmCP_SEM_INCOMPLETE_TIMER_CNTL, 0x0);
2059 /* Set the write pointer delay */
2060 WREG32(mmCP_RB_WPTR_DELAY, 0);
2062 WREG32(mmCP_DEBUG, 0);
2063 WREG32(mmSCRATCH_ADDR, 0);
2065 /* ring 0 - compute and gfx */
2066 /* Set ring buffer size */
2067 ring = &adev->gfx.gfx_ring[0];
2068 rb_bufsz = order_base_2(ring->ring_size / 8);
2069 tmp = (order_base_2(AMDGPU_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
2072 tmp |= BUF_SWAP_32BIT;
2074 WREG32(mmCP_RB0_CNTL, tmp);
2076 /* Initialize the ring buffer's read and write pointers */
2077 WREG32(mmCP_RB0_CNTL, tmp | CP_RB0_CNTL__RB_RPTR_WR_ENA_MASK);
2079 WREG32(mmCP_RB0_WPTR, ring->wptr);
2081 /* set the wb address whether it's enabled or not */
2082 rptr_addr = ring->rptr_gpu_addr;
2083 WREG32(mmCP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr));
2084 WREG32(mmCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 0xFF);
2086 WREG32(mmSCRATCH_UMSK, 0);
2089 WREG32(mmCP_RB0_CNTL, tmp);
2091 WREG32(mmCP_RB0_BASE, ring->gpu_addr >> 8);
2093 /* start the rings */
2094 gfx_v6_0_cp_gfx_start(adev);
2095 r = amdgpu_ring_test_helper(ring);
2102 static u64 gfx_v6_0_ring_get_rptr(struct amdgpu_ring *ring)
2104 return *ring->rptr_cpu_addr;
2107 static u64 gfx_v6_0_ring_get_wptr(struct amdgpu_ring *ring)
2109 struct amdgpu_device *adev = ring->adev;
2111 if (ring == &adev->gfx.gfx_ring[0])
2112 return RREG32(mmCP_RB0_WPTR);
2113 else if (ring == &adev->gfx.compute_ring[0])
2114 return RREG32(mmCP_RB1_WPTR);
2115 else if (ring == &adev->gfx.compute_ring[1])
2116 return RREG32(mmCP_RB2_WPTR);
2121 static void gfx_v6_0_ring_set_wptr_gfx(struct amdgpu_ring *ring)
2123 struct amdgpu_device *adev = ring->adev;
2125 WREG32(mmCP_RB0_WPTR, lower_32_bits(ring->wptr));
2126 (void)RREG32(mmCP_RB0_WPTR);
2129 static void gfx_v6_0_ring_set_wptr_compute(struct amdgpu_ring *ring)
2131 struct amdgpu_device *adev = ring->adev;
2133 if (ring == &adev->gfx.compute_ring[0]) {
2134 WREG32(mmCP_RB1_WPTR, lower_32_bits(ring->wptr));
2135 (void)RREG32(mmCP_RB1_WPTR);
2136 } else if (ring == &adev->gfx.compute_ring[1]) {
2137 WREG32(mmCP_RB2_WPTR, lower_32_bits(ring->wptr));
2138 (void)RREG32(mmCP_RB2_WPTR);
2145 static int gfx_v6_0_cp_compute_resume(struct amdgpu_device *adev)
2147 struct amdgpu_ring *ring;
2153 /* ring1 - compute only */
2154 /* Set ring buffer size */
2156 ring = &adev->gfx.compute_ring[0];
2157 rb_bufsz = order_base_2(ring->ring_size / 8);
2158 tmp = (order_base_2(AMDGPU_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
2160 tmp |= BUF_SWAP_32BIT;
2162 WREG32(mmCP_RB1_CNTL, tmp);
2164 WREG32(mmCP_RB1_CNTL, tmp | CP_RB1_CNTL__RB_RPTR_WR_ENA_MASK);
2166 WREG32(mmCP_RB1_WPTR, ring->wptr);
2168 rptr_addr = ring->rptr_gpu_addr;
2169 WREG32(mmCP_RB1_RPTR_ADDR, lower_32_bits(rptr_addr));
2170 WREG32(mmCP_RB1_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 0xFF);
2173 WREG32(mmCP_RB1_CNTL, tmp);
2174 WREG32(mmCP_RB1_BASE, ring->gpu_addr >> 8);
2176 ring = &adev->gfx.compute_ring[1];
2177 rb_bufsz = order_base_2(ring->ring_size / 8);
2178 tmp = (order_base_2(AMDGPU_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
2180 tmp |= BUF_SWAP_32BIT;
2182 WREG32(mmCP_RB2_CNTL, tmp);
2184 WREG32(mmCP_RB2_CNTL, tmp | CP_RB2_CNTL__RB_RPTR_WR_ENA_MASK);
2186 WREG32(mmCP_RB2_WPTR, ring->wptr);
2187 rptr_addr = ring->rptr_gpu_addr;
2188 WREG32(mmCP_RB2_RPTR_ADDR, lower_32_bits(rptr_addr));
2189 WREG32(mmCP_RB2_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 0xFF);
2192 WREG32(mmCP_RB2_CNTL, tmp);
2193 WREG32(mmCP_RB2_BASE, ring->gpu_addr >> 8);
2196 for (i = 0; i < 2; i++) {
2197 r = amdgpu_ring_test_helper(&adev->gfx.compute_ring[i]);
2205 static void gfx_v6_0_cp_enable(struct amdgpu_device *adev, bool enable)
2207 gfx_v6_0_cp_gfx_enable(adev, enable);
2210 static int gfx_v6_0_cp_load_microcode(struct amdgpu_device *adev)
2212 return gfx_v6_0_cp_gfx_load_microcode(adev);
2215 static void gfx_v6_0_enable_gui_idle_interrupt(struct amdgpu_device *adev,
2218 u32 tmp = RREG32(mmCP_INT_CNTL_RING0);
2223 tmp |= (CP_INT_CNTL__CNTX_BUSY_INT_ENABLE_MASK |
2224 CP_INT_CNTL__CNTX_EMPTY_INT_ENABLE_MASK);
2226 tmp &= ~(CP_INT_CNTL__CNTX_BUSY_INT_ENABLE_MASK |
2227 CP_INT_CNTL__CNTX_EMPTY_INT_ENABLE_MASK);
2228 WREG32(mmCP_INT_CNTL_RING0, tmp);
2231 /* read a gfx register */
2232 tmp = RREG32(mmDB_DEPTH_INFO);
2234 mask = RLC_BUSY_STATUS | GFX_POWER_STATUS | GFX_CLOCK_STATUS | GFX_LS_STATUS;
2235 for (i = 0; i < adev->usec_timeout; i++) {
2236 if ((RREG32(mmRLC_STAT) & mask) == (GFX_CLOCK_STATUS | GFX_POWER_STATUS))
2243 static int gfx_v6_0_cp_resume(struct amdgpu_device *adev)
2247 gfx_v6_0_enable_gui_idle_interrupt(adev, false);
2249 r = gfx_v6_0_cp_load_microcode(adev);
2253 r = gfx_v6_0_cp_gfx_resume(adev);
2256 r = gfx_v6_0_cp_compute_resume(adev);
2260 gfx_v6_0_enable_gui_idle_interrupt(adev, true);
2265 static void gfx_v6_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
2267 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
2268 uint32_t seq = ring->fence_drv.sync_seq;
2269 uint64_t addr = ring->fence_drv.gpu_addr;
2271 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
2272 amdgpu_ring_write(ring, (WAIT_REG_MEM_MEM_SPACE(1) | /* memory */
2273 WAIT_REG_MEM_FUNCTION(3) | /* equal */
2274 WAIT_REG_MEM_ENGINE(usepfp))); /* pfp or me */
2275 amdgpu_ring_write(ring, addr & 0xfffffffc);
2276 amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff);
2277 amdgpu_ring_write(ring, seq);
2278 amdgpu_ring_write(ring, 0xffffffff);
2279 amdgpu_ring_write(ring, 4); /* poll interval */
2282 /* synce CE with ME to prevent CE fetch CEIB before context switch done */
2283 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
2284 amdgpu_ring_write(ring, 0);
2285 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
2286 amdgpu_ring_write(ring, 0);
2290 static void gfx_v6_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
2291 unsigned vmid, uint64_t pd_addr)
2293 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
2295 amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
2297 /* wait for the invalidate to complete */
2298 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
2299 amdgpu_ring_write(ring, (WAIT_REG_MEM_FUNCTION(0) | /* always */
2300 WAIT_REG_MEM_ENGINE(0))); /* me */
2301 amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST);
2302 amdgpu_ring_write(ring, 0);
2303 amdgpu_ring_write(ring, 0); /* ref */
2304 amdgpu_ring_write(ring, 0); /* mask */
2305 amdgpu_ring_write(ring, 0x20); /* poll interval */
2308 /* sync PFP to ME, otherwise we might get invalid PFP reads */
2309 amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0));
2310 amdgpu_ring_write(ring, 0x0);
2312 /* synce CE with ME to prevent CE fetch CEIB before context switch done */
2313 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
2314 amdgpu_ring_write(ring, 0);
2315 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
2316 amdgpu_ring_write(ring, 0);
2320 static void gfx_v6_0_ring_emit_wreg(struct amdgpu_ring *ring,
2321 uint32_t reg, uint32_t val)
2323 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
2325 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
2326 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(usepfp) |
2327 WRITE_DATA_DST_SEL(0)));
2328 amdgpu_ring_write(ring, reg);
2329 amdgpu_ring_write(ring, 0);
2330 amdgpu_ring_write(ring, val);
2333 static int gfx_v6_0_rlc_init(struct amdgpu_device *adev)
2336 volatile u32 *dst_ptr;
2338 u64 reg_list_mc_addr;
2339 const struct cs_section_def *cs_data;
2342 adev->gfx.rlc.reg_list = verde_rlc_save_restore_register_list;
2343 adev->gfx.rlc.reg_list_size =
2344 (u32)ARRAY_SIZE(verde_rlc_save_restore_register_list);
2346 adev->gfx.rlc.cs_data = si_cs_data;
2347 src_ptr = adev->gfx.rlc.reg_list;
2348 dws = adev->gfx.rlc.reg_list_size;
2349 cs_data = adev->gfx.rlc.cs_data;
2352 /* init save restore block */
2353 r = amdgpu_gfx_rlc_init_sr(adev, dws);
2359 /* clear state block */
2360 adev->gfx.rlc.clear_state_size = gfx_v6_0_get_csb_size(adev);
2361 dws = adev->gfx.rlc.clear_state_size + (256 / 4);
2363 r = amdgpu_bo_create_reserved(adev, dws * 4, PAGE_SIZE,
2364 AMDGPU_GEM_DOMAIN_VRAM |
2365 AMDGPU_GEM_DOMAIN_GTT,
2366 &adev->gfx.rlc.clear_state_obj,
2367 &adev->gfx.rlc.clear_state_gpu_addr,
2368 (void **)&adev->gfx.rlc.cs_ptr);
2370 dev_warn(adev->dev, "(%d) create RLC c bo failed\n", r);
2371 amdgpu_gfx_rlc_fini(adev);
2375 /* set up the cs buffer */
2376 dst_ptr = adev->gfx.rlc.cs_ptr;
2377 reg_list_mc_addr = adev->gfx.rlc.clear_state_gpu_addr + 256;
2378 dst_ptr[0] = cpu_to_le32(upper_32_bits(reg_list_mc_addr));
2379 dst_ptr[1] = cpu_to_le32(lower_32_bits(reg_list_mc_addr));
2380 dst_ptr[2] = cpu_to_le32(adev->gfx.rlc.clear_state_size);
2381 gfx_v6_0_get_csb_buffer(adev, &dst_ptr[(256/4)]);
2382 amdgpu_bo_kunmap(adev->gfx.rlc.clear_state_obj);
2383 amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj);
2389 static void gfx_v6_0_enable_lbpw(struct amdgpu_device *adev, bool enable)
2391 WREG32_FIELD(RLC_LB_CNTL, LOAD_BALANCE_ENABLE, enable ? 1 : 0);
2394 gfx_v6_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0);
2395 WREG32(mmSPI_LB_CU_MASK, 0x00ff);
2399 static void gfx_v6_0_wait_for_rlc_serdes(struct amdgpu_device *adev)
2403 for (i = 0; i < adev->usec_timeout; i++) {
2404 if (RREG32(mmRLC_SERDES_MASTER_BUSY_0) == 0)
2409 for (i = 0; i < adev->usec_timeout; i++) {
2410 if (RREG32(mmRLC_SERDES_MASTER_BUSY_1) == 0)
2416 static void gfx_v6_0_update_rlc(struct amdgpu_device *adev, u32 rlc)
2420 tmp = RREG32(mmRLC_CNTL);
2422 WREG32(mmRLC_CNTL, rlc);
2425 static u32 gfx_v6_0_halt_rlc(struct amdgpu_device *adev)
2429 orig = data = RREG32(mmRLC_CNTL);
2431 if (data & RLC_CNTL__RLC_ENABLE_F32_MASK) {
2432 data &= ~RLC_CNTL__RLC_ENABLE_F32_MASK;
2433 WREG32(mmRLC_CNTL, data);
2435 gfx_v6_0_wait_for_rlc_serdes(adev);
2441 static void gfx_v6_0_rlc_stop(struct amdgpu_device *adev)
2443 WREG32(mmRLC_CNTL, 0);
2445 gfx_v6_0_enable_gui_idle_interrupt(adev, false);
2446 gfx_v6_0_wait_for_rlc_serdes(adev);
2449 static void gfx_v6_0_rlc_start(struct amdgpu_device *adev)
2451 WREG32(mmRLC_CNTL, RLC_CNTL__RLC_ENABLE_F32_MASK);
2453 gfx_v6_0_enable_gui_idle_interrupt(adev, true);
2458 static void gfx_v6_0_rlc_reset(struct amdgpu_device *adev)
2460 WREG32_FIELD(GRBM_SOFT_RESET, SOFT_RESET_RLC, 1);
2462 WREG32_FIELD(GRBM_SOFT_RESET, SOFT_RESET_RLC, 0);
2466 static bool gfx_v6_0_lbpw_supported(struct amdgpu_device *adev)
2470 /* Enable LBPW only for DDR3 */
2471 tmp = RREG32(mmMC_SEQ_MISC0);
2472 if ((tmp & 0xF0000000) == 0xB0000000)
2477 static void gfx_v6_0_init_cg(struct amdgpu_device *adev)
2481 static int gfx_v6_0_rlc_resume(struct amdgpu_device *adev)
2484 const struct rlc_firmware_header_v1_0 *hdr;
2485 const __le32 *fw_data;
2489 if (!adev->gfx.rlc_fw)
2492 adev->gfx.rlc.funcs->stop(adev);
2493 adev->gfx.rlc.funcs->reset(adev);
2494 gfx_v6_0_init_pg(adev);
2495 gfx_v6_0_init_cg(adev);
2497 WREG32(mmRLC_RL_BASE, 0);
2498 WREG32(mmRLC_RL_SIZE, 0);
2499 WREG32(mmRLC_LB_CNTL, 0);
2500 WREG32(mmRLC_LB_CNTR_MAX, 0xffffffff);
2501 WREG32(mmRLC_LB_CNTR_INIT, 0);
2502 WREG32(mmRLC_LB_INIT_CU_MASK, 0xffffffff);
2504 WREG32(mmRLC_MC_CNTL, 0);
2505 WREG32(mmRLC_UCODE_CNTL, 0);
2507 hdr = (const struct rlc_firmware_header_v1_0 *)adev->gfx.rlc_fw->data;
2508 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
2509 fw_data = (const __le32 *)
2510 (adev->gfx.rlc_fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes));
2512 amdgpu_ucode_print_rlc_hdr(&hdr->header);
2514 for (i = 0; i < fw_size; i++) {
2515 WREG32(mmRLC_UCODE_ADDR, i);
2516 WREG32(mmRLC_UCODE_DATA, le32_to_cpup(fw_data++));
2518 WREG32(mmRLC_UCODE_ADDR, 0);
2520 gfx_v6_0_enable_lbpw(adev, gfx_v6_0_lbpw_supported(adev));
2521 adev->gfx.rlc.funcs->start(adev);
2526 static void gfx_v6_0_enable_cgcg(struct amdgpu_device *adev, bool enable)
2528 u32 data, orig, tmp;
2530 orig = data = RREG32(mmRLC_CGCG_CGLS_CTRL);
2532 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)) {
2533 gfx_v6_0_enable_gui_idle_interrupt(adev, true);
2535 WREG32(mmRLC_GCPM_GENERAL_3, 0x00000080);
2537 tmp = gfx_v6_0_halt_rlc(adev);
2539 WREG32(mmRLC_SERDES_WR_MASTER_MASK_0, 0xffffffff);
2540 WREG32(mmRLC_SERDES_WR_MASTER_MASK_1, 0xffffffff);
2541 WREG32(mmRLC_SERDES_WR_CTRL, 0x00b000ff);
2543 gfx_v6_0_wait_for_rlc_serdes(adev);
2544 gfx_v6_0_update_rlc(adev, tmp);
2546 WREG32(mmRLC_SERDES_WR_CTRL, 0x007000ff);
2548 data |= RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK | RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK;
2550 gfx_v6_0_enable_gui_idle_interrupt(adev, false);
2552 RREG32(mmCB_CGTT_SCLK_CTRL);
2553 RREG32(mmCB_CGTT_SCLK_CTRL);
2554 RREG32(mmCB_CGTT_SCLK_CTRL);
2555 RREG32(mmCB_CGTT_SCLK_CTRL);
2557 data &= ~(RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK | RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK);
2561 WREG32(mmRLC_CGCG_CGLS_CTRL, data);
2565 static void gfx_v6_0_enable_mgcg(struct amdgpu_device *adev, bool enable)
2568 u32 data, orig, tmp = 0;
2570 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) {
2571 orig = data = RREG32(mmCGTS_SM_CTRL_REG);
2574 WREG32(mmCGTS_SM_CTRL_REG, data);
2576 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CP_LS) {
2577 orig = data = RREG32(mmCP_MEM_SLP_CNTL);
2578 data |= CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK;
2580 WREG32(mmCP_MEM_SLP_CNTL, data);
2583 orig = data = RREG32(mmRLC_CGTT_MGCG_OVERRIDE);
2586 WREG32(mmRLC_CGTT_MGCG_OVERRIDE, data);
2588 tmp = gfx_v6_0_halt_rlc(adev);
2590 WREG32(mmRLC_SERDES_WR_MASTER_MASK_0, 0xffffffff);
2591 WREG32(mmRLC_SERDES_WR_MASTER_MASK_1, 0xffffffff);
2592 WREG32(mmRLC_SERDES_WR_CTRL, 0x00d000ff);
2594 gfx_v6_0_update_rlc(adev, tmp);
2596 orig = data = RREG32(mmRLC_CGTT_MGCG_OVERRIDE);
2599 WREG32(mmRLC_CGTT_MGCG_OVERRIDE, data);
2601 data = RREG32(mmCP_MEM_SLP_CNTL);
2602 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) {
2603 data &= ~CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK;
2604 WREG32(mmCP_MEM_SLP_CNTL, data);
2606 orig = data = RREG32(mmCGTS_SM_CTRL_REG);
2607 data |= CGTS_SM_CTRL_REG__LS_OVERRIDE_MASK | CGTS_SM_CTRL_REG__OVERRIDE_MASK;
2609 WREG32(mmCGTS_SM_CTRL_REG, data);
2611 tmp = gfx_v6_0_halt_rlc(adev);
2613 WREG32(mmRLC_SERDES_WR_MASTER_MASK_0, 0xffffffff);
2614 WREG32(mmRLC_SERDES_WR_MASTER_MASK_1, 0xffffffff);
2615 WREG32(mmRLC_SERDES_WR_CTRL, 0x00e000ff);
2617 gfx_v6_0_update_rlc(adev, tmp);
2621 static void gfx_v6_0_update_cg(struct amdgpu_device *adev,
2624 gfx_v6_0_enable_gui_idle_interrupt(adev, false);
2626 gfx_v6_0_enable_mgcg(adev, true);
2627 gfx_v6_0_enable_cgcg(adev, true);
2629 gfx_v6_0_enable_cgcg(adev, false);
2630 gfx_v6_0_enable_mgcg(adev, false);
2632 gfx_v6_0_enable_gui_idle_interrupt(adev, true);
2636 static void gfx_v6_0_enable_sclk_slowdown_on_pu(struct amdgpu_device *adev,
2641 static void gfx_v6_0_enable_sclk_slowdown_on_pd(struct amdgpu_device *adev,
2646 static void gfx_v6_0_enable_cp_pg(struct amdgpu_device *adev, bool enable)
2650 orig = data = RREG32(mmRLC_PG_CNTL);
2651 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_CP))
2656 WREG32(mmRLC_PG_CNTL, data);
2659 static void gfx_v6_0_enable_gds_pg(struct amdgpu_device *adev, bool enable)
2663 static void gfx_v6_0_init_cp_pg_table(struct amdgpu_device *adev)
2665 const __le32 *fw_data;
2666 volatile u32 *dst_ptr;
2667 int me, i, max_me = 4;
2669 u32 table_offset, table_size;
2671 if (adev->asic_type == CHIP_KAVERI)
2674 if (adev->gfx.rlc.cp_table_ptr == NULL)
2677 dst_ptr = adev->gfx.rlc.cp_table_ptr;
2678 for (me = 0; me < max_me; me++) {
2680 const struct gfx_firmware_header_v1_0 *hdr =
2681 (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data;
2682 fw_data = (const __le32 *)
2683 (adev->gfx.ce_fw->data +
2684 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
2685 table_offset = le32_to_cpu(hdr->jt_offset);
2686 table_size = le32_to_cpu(hdr->jt_size);
2687 } else if (me == 1) {
2688 const struct gfx_firmware_header_v1_0 *hdr =
2689 (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data;
2690 fw_data = (const __le32 *)
2691 (adev->gfx.pfp_fw->data +
2692 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
2693 table_offset = le32_to_cpu(hdr->jt_offset);
2694 table_size = le32_to_cpu(hdr->jt_size);
2695 } else if (me == 2) {
2696 const struct gfx_firmware_header_v1_0 *hdr =
2697 (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data;
2698 fw_data = (const __le32 *)
2699 (adev->gfx.me_fw->data +
2700 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
2701 table_offset = le32_to_cpu(hdr->jt_offset);
2702 table_size = le32_to_cpu(hdr->jt_size);
2703 } else if (me == 3) {
2704 const struct gfx_firmware_header_v1_0 *hdr =
2705 (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
2706 fw_data = (const __le32 *)
2707 (adev->gfx.mec_fw->data +
2708 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
2709 table_offset = le32_to_cpu(hdr->jt_offset);
2710 table_size = le32_to_cpu(hdr->jt_size);
2712 const struct gfx_firmware_header_v1_0 *hdr =
2713 (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec2_fw->data;
2714 fw_data = (const __le32 *)
2715 (adev->gfx.mec2_fw->data +
2716 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
2717 table_offset = le32_to_cpu(hdr->jt_offset);
2718 table_size = le32_to_cpu(hdr->jt_size);
2721 for (i = 0; i < table_size; i ++) {
2722 dst_ptr[bo_offset + i] =
2723 cpu_to_le32(le32_to_cpu(fw_data[table_offset + i]));
2726 bo_offset += table_size;
2730 static void gfx_v6_0_enable_gfx_cgpg(struct amdgpu_device *adev,
2733 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG)) {
2734 WREG32(mmRLC_TTOP_D, RLC_PUD(0x10) | RLC_PDD(0x10) | RLC_TTPD(0x10) | RLC_MSD(0x10));
2735 WREG32_FIELD(RLC_PG_CNTL, GFX_POWER_GATING_ENABLE, 1);
2736 WREG32_FIELD(RLC_AUTO_PG_CTRL, AUTO_PG_EN, 1);
2738 WREG32_FIELD(RLC_AUTO_PG_CTRL, AUTO_PG_EN, 0);
2739 (void)RREG32(mmDB_RENDER_CONTROL);
2743 static void gfx_v6_0_init_ao_cu_mask(struct amdgpu_device *adev)
2747 WREG32(mmRLC_PG_ALWAYS_ON_CU_MASK, adev->gfx.cu_info.ao_cu_mask);
2749 tmp = RREG32(mmRLC_MAX_PG_CU);
2750 tmp &= ~RLC_MAX_PG_CU__MAX_POWERED_UP_CU_MASK;
2751 tmp |= (adev->gfx.cu_info.number << RLC_MAX_PG_CU__MAX_POWERED_UP_CU__SHIFT);
2752 WREG32(mmRLC_MAX_PG_CU, tmp);
2755 static void gfx_v6_0_enable_gfx_static_mgpg(struct amdgpu_device *adev,
2760 orig = data = RREG32(mmRLC_PG_CNTL);
2761 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_SMG))
2762 data |= RLC_PG_CNTL__STATIC_PER_CU_PG_ENABLE_MASK;
2764 data &= ~RLC_PG_CNTL__STATIC_PER_CU_PG_ENABLE_MASK;
2766 WREG32(mmRLC_PG_CNTL, data);
2769 static void gfx_v6_0_enable_gfx_dynamic_mgpg(struct amdgpu_device *adev,
2774 orig = data = RREG32(mmRLC_PG_CNTL);
2775 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_DMG))
2776 data |= RLC_PG_CNTL__DYN_PER_CU_PG_ENABLE_MASK;
2778 data &= ~RLC_PG_CNTL__DYN_PER_CU_PG_ENABLE_MASK;
2780 WREG32(mmRLC_PG_CNTL, data);
2783 static void gfx_v6_0_init_gfx_cgpg(struct amdgpu_device *adev)
2787 WREG32(mmRLC_SAVE_AND_RESTORE_BASE, adev->gfx.rlc.save_restore_gpu_addr >> 8);
2788 WREG32_FIELD(RLC_PG_CNTL, GFX_POWER_GATING_SRC, 1);
2789 WREG32(mmRLC_CLEAR_STATE_RESTORE_BASE, adev->gfx.rlc.clear_state_gpu_addr >> 8);
2791 tmp = RREG32(mmRLC_AUTO_PG_CTRL);
2792 tmp &= ~RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD_MASK;
2793 tmp |= (0x700 << RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD__SHIFT);
2794 tmp &= ~RLC_AUTO_PG_CTRL__PG_AFTER_GRBM_REG_SAVE_THRESHOLD_MASK;
2795 WREG32(mmRLC_AUTO_PG_CTRL, tmp);
2798 static void gfx_v6_0_update_gfx_pg(struct amdgpu_device *adev, bool enable)
2800 gfx_v6_0_enable_gfx_cgpg(adev, enable);
2801 gfx_v6_0_enable_gfx_static_mgpg(adev, enable);
2802 gfx_v6_0_enable_gfx_dynamic_mgpg(adev, enable);
2805 static u32 gfx_v6_0_get_csb_size(struct amdgpu_device *adev)
2808 const struct cs_section_def *sect = NULL;
2809 const struct cs_extent_def *ext = NULL;
2811 if (adev->gfx.rlc.cs_data == NULL)
2814 /* begin clear state */
2816 /* context control state */
2819 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) {
2820 for (ext = sect->section; ext->extent != NULL; ++ext) {
2821 if (sect->id == SECT_CONTEXT)
2822 count += 2 + ext->reg_count;
2827 /* pa_sc_raster_config */
2829 /* end clear state */
2837 static void gfx_v6_0_get_csb_buffer(struct amdgpu_device *adev,
2838 volatile u32 *buffer)
2841 const struct cs_section_def *sect = NULL;
2842 const struct cs_extent_def *ext = NULL;
2844 if (adev->gfx.rlc.cs_data == NULL)
2849 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));
2850 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
2851 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CONTEXT_CONTROL, 1));
2852 buffer[count++] = cpu_to_le32(0x80000000);
2853 buffer[count++] = cpu_to_le32(0x80000000);
2855 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) {
2856 for (ext = sect->section; ext->extent != NULL; ++ext) {
2857 if (sect->id == SECT_CONTEXT) {
2859 cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count));
2860 buffer[count++] = cpu_to_le32(ext->reg_index - 0xa000);
2861 for (i = 0; i < ext->reg_count; i++)
2862 buffer[count++] = cpu_to_le32(ext->extent[i]);
2869 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, 1));
2870 buffer[count++] = cpu_to_le32(mmPA_SC_RASTER_CONFIG - PACKET3_SET_CONTEXT_REG_START);
2871 buffer[count++] = cpu_to_le32(adev->gfx.config.rb_config[0][0].raster_config);
2873 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));
2874 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_END_CLEAR_STATE);
2876 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CLEAR_STATE, 0));
2877 buffer[count++] = cpu_to_le32(0);
2880 static void gfx_v6_0_init_pg(struct amdgpu_device *adev)
2882 if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG |
2883 AMD_PG_SUPPORT_GFX_SMG |
2884 AMD_PG_SUPPORT_GFX_DMG |
2886 AMD_PG_SUPPORT_GDS |
2887 AMD_PG_SUPPORT_RLC_SMU_HS)) {
2888 gfx_v6_0_enable_sclk_slowdown_on_pu(adev, true);
2889 gfx_v6_0_enable_sclk_slowdown_on_pd(adev, true);
2890 if (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG) {
2891 gfx_v6_0_init_gfx_cgpg(adev);
2892 gfx_v6_0_enable_cp_pg(adev, true);
2893 gfx_v6_0_enable_gds_pg(adev, true);
2895 WREG32(mmRLC_SAVE_AND_RESTORE_BASE, adev->gfx.rlc.save_restore_gpu_addr >> 8);
2896 WREG32(mmRLC_CLEAR_STATE_RESTORE_BASE, adev->gfx.rlc.clear_state_gpu_addr >> 8);
2899 gfx_v6_0_init_ao_cu_mask(adev);
2900 gfx_v6_0_update_gfx_pg(adev, true);
2903 WREG32(mmRLC_SAVE_AND_RESTORE_BASE, adev->gfx.rlc.save_restore_gpu_addr >> 8);
2904 WREG32(mmRLC_CLEAR_STATE_RESTORE_BASE, adev->gfx.rlc.clear_state_gpu_addr >> 8);
2908 static void gfx_v6_0_fini_pg(struct amdgpu_device *adev)
2910 if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG |
2911 AMD_PG_SUPPORT_GFX_SMG |
2912 AMD_PG_SUPPORT_GFX_DMG |
2914 AMD_PG_SUPPORT_GDS |
2915 AMD_PG_SUPPORT_RLC_SMU_HS)) {
2916 gfx_v6_0_update_gfx_pg(adev, false);
2917 if (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG) {
2918 gfx_v6_0_enable_cp_pg(adev, false);
2919 gfx_v6_0_enable_gds_pg(adev, false);
2924 static uint64_t gfx_v6_0_get_gpu_clock_counter(struct amdgpu_device *adev)
2928 mutex_lock(&adev->gfx.gpu_clock_mutex);
2929 WREG32(mmRLC_CAPTURE_GPU_CLOCK_COUNT, 1);
2930 clock = (uint64_t)RREG32(mmRLC_GPU_CLOCK_COUNT_LSB) |
2931 ((uint64_t)RREG32(mmRLC_GPU_CLOCK_COUNT_MSB) << 32ULL);
2932 mutex_unlock(&adev->gfx.gpu_clock_mutex);
2936 static void gfx_v6_ring_emit_cntxcntl(struct amdgpu_ring *ring, uint32_t flags)
2938 if (flags & AMDGPU_HAVE_CTX_SWITCH)
2939 gfx_v6_0_ring_emit_vgt_flush(ring);
2940 amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1));
2941 amdgpu_ring_write(ring, 0x80000000);
2942 amdgpu_ring_write(ring, 0);
2946 static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t address)
2948 WREG32(mmSQ_IND_INDEX,
2949 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) |
2950 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) |
2951 (address << SQ_IND_INDEX__INDEX__SHIFT) |
2952 (SQ_IND_INDEX__FORCE_READ_MASK));
2953 return RREG32(mmSQ_IND_DATA);
2956 static void wave_read_regs(struct amdgpu_device *adev, uint32_t simd,
2957 uint32_t wave, uint32_t thread,
2958 uint32_t regno, uint32_t num, uint32_t *out)
2960 WREG32(mmSQ_IND_INDEX,
2961 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) |
2962 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) |
2963 (regno << SQ_IND_INDEX__INDEX__SHIFT) |
2964 (thread << SQ_IND_INDEX__THREAD_ID__SHIFT) |
2965 (SQ_IND_INDEX__FORCE_READ_MASK) |
2966 (SQ_IND_INDEX__AUTO_INCR_MASK));
2968 *(out++) = RREG32(mmSQ_IND_DATA);
2971 static void gfx_v6_0_read_wave_data(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, uint32_t wave, uint32_t *dst, int *no_fields)
2973 /* type 0 wave data */
2974 dst[(*no_fields)++] = 0;
2975 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_STATUS);
2976 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_LO);
2977 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_HI);
2978 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_LO);
2979 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_HI);
2980 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_HW_ID);
2981 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_INST_DW0);
2982 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_INST_DW1);
2983 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_GPR_ALLOC);
2984 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_LDS_ALLOC);
2985 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TRAPSTS);
2986 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_IB_STS);
2987 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TBA_LO);
2988 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TBA_HI);
2989 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TMA_LO);
2990 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TMA_HI);
2991 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_IB_DBG0);
2992 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_M0);
2993 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_MODE);
2996 static void gfx_v6_0_read_wave_sgprs(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd,
2997 uint32_t wave, uint32_t start,
2998 uint32_t size, uint32_t *dst)
3001 adev, simd, wave, 0,
3002 start + SQIND_WAVE_SGPRS_OFFSET, size, dst);
3005 static void gfx_v6_0_select_me_pipe_q(struct amdgpu_device *adev,
3006 u32 me, u32 pipe, u32 q, u32 vm, u32 xcc_id)
3008 DRM_INFO("Not implemented\n");
3011 static const struct amdgpu_gfx_funcs gfx_v6_0_gfx_funcs = {
3012 .get_gpu_clock_counter = &gfx_v6_0_get_gpu_clock_counter,
3013 .select_se_sh = &gfx_v6_0_select_se_sh,
3014 .read_wave_data = &gfx_v6_0_read_wave_data,
3015 .read_wave_sgprs = &gfx_v6_0_read_wave_sgprs,
3016 .select_me_pipe_q = &gfx_v6_0_select_me_pipe_q
3019 static const struct amdgpu_rlc_funcs gfx_v6_0_rlc_funcs = {
3020 .init = gfx_v6_0_rlc_init,
3021 .resume = gfx_v6_0_rlc_resume,
3022 .stop = gfx_v6_0_rlc_stop,
3023 .reset = gfx_v6_0_rlc_reset,
3024 .start = gfx_v6_0_rlc_start
3027 static int gfx_v6_0_early_init(void *handle)
3029 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3031 adev->gfx.xcc_mask = 1;
3032 adev->gfx.num_gfx_rings = GFX6_NUM_GFX_RINGS;
3033 adev->gfx.num_compute_rings = min(amdgpu_gfx_get_num_kcq(adev),
3034 GFX6_NUM_COMPUTE_RINGS);
3035 adev->gfx.funcs = &gfx_v6_0_gfx_funcs;
3036 adev->gfx.rlc.funcs = &gfx_v6_0_rlc_funcs;
3037 gfx_v6_0_set_ring_funcs(adev);
3038 gfx_v6_0_set_irq_funcs(adev);
3043 static int gfx_v6_0_sw_init(void *handle)
3045 struct amdgpu_ring *ring;
3046 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3049 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, 181, &adev->gfx.eop_irq);
3053 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, 184, &adev->gfx.priv_reg_irq);
3057 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, 185, &adev->gfx.priv_inst_irq);
3061 r = gfx_v6_0_init_microcode(adev);
3063 DRM_ERROR("Failed to load gfx firmware!\n");
3067 r = adev->gfx.rlc.funcs->init(adev);
3069 DRM_ERROR("Failed to init rlc BOs!\n");
3073 for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
3074 ring = &adev->gfx.gfx_ring[i];
3075 ring->ring_obj = NULL;
3076 sprintf(ring->name, "gfx");
3077 r = amdgpu_ring_init(adev, ring, 2048,
3079 AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP,
3080 AMDGPU_RING_PRIO_DEFAULT, NULL);
3085 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
3088 if ((i >= 32) || (i >= AMDGPU_MAX_COMPUTE_RINGS)) {
3089 DRM_ERROR("Too many (%d) compute rings!\n", i);
3092 ring = &adev->gfx.compute_ring[i];
3093 ring->ring_obj = NULL;
3094 ring->use_doorbell = false;
3095 ring->doorbell_index = 0;
3099 sprintf(ring->name, "comp_%d.%d.%d", ring->me, ring->pipe, ring->queue);
3100 irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP + ring->pipe;
3101 r = amdgpu_ring_init(adev, ring, 1024,
3102 &adev->gfx.eop_irq, irq_type,
3103 AMDGPU_RING_PRIO_DEFAULT, NULL);
3111 static int gfx_v6_0_sw_fini(void *handle)
3114 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3116 for (i = 0; i < adev->gfx.num_gfx_rings; i++)
3117 amdgpu_ring_fini(&adev->gfx.gfx_ring[i]);
3118 for (i = 0; i < adev->gfx.num_compute_rings; i++)
3119 amdgpu_ring_fini(&adev->gfx.compute_ring[i]);
3121 amdgpu_gfx_rlc_fini(adev);
3126 static int gfx_v6_0_hw_init(void *handle)
3129 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3131 gfx_v6_0_constants_init(adev);
3133 r = adev->gfx.rlc.funcs->resume(adev);
3137 r = gfx_v6_0_cp_resume(adev);
3141 adev->gfx.ce_ram_size = 0x8000;
3146 static int gfx_v6_0_hw_fini(void *handle)
3148 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3150 gfx_v6_0_cp_enable(adev, false);
3151 adev->gfx.rlc.funcs->stop(adev);
3152 gfx_v6_0_fini_pg(adev);
3157 static int gfx_v6_0_suspend(void *handle)
3159 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3161 return gfx_v6_0_hw_fini(adev);
3164 static int gfx_v6_0_resume(void *handle)
3166 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3168 return gfx_v6_0_hw_init(adev);
3171 static bool gfx_v6_0_is_idle(void *handle)
3173 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3175 if (RREG32(mmGRBM_STATUS) & GRBM_STATUS__GUI_ACTIVE_MASK)
3181 static int gfx_v6_0_wait_for_idle(void *handle)
3184 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3186 for (i = 0; i < adev->usec_timeout; i++) {
3187 if (gfx_v6_0_is_idle(handle))
3194 static int gfx_v6_0_soft_reset(void *handle)
3199 static void gfx_v6_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev,
3200 enum amdgpu_interrupt_state state)
3205 case AMDGPU_IRQ_STATE_DISABLE:
3206 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
3207 cp_int_cntl &= ~CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK;
3208 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
3210 case AMDGPU_IRQ_STATE_ENABLE:
3211 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
3212 cp_int_cntl |= CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK;
3213 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
3220 static void gfx_v6_0_set_compute_eop_interrupt_state(struct amdgpu_device *adev,
3222 enum amdgpu_interrupt_state state)
3226 case AMDGPU_IRQ_STATE_DISABLE:
3228 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING1);
3229 cp_int_cntl &= ~CP_INT_CNTL_RING1__TIME_STAMP_INT_ENABLE_MASK;
3230 WREG32(mmCP_INT_CNTL_RING1, cp_int_cntl);
3233 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING2);
3234 cp_int_cntl &= ~CP_INT_CNTL_RING2__TIME_STAMP_INT_ENABLE_MASK;
3235 WREG32(mmCP_INT_CNTL_RING2, cp_int_cntl);
3239 case AMDGPU_IRQ_STATE_ENABLE:
3241 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING1);
3242 cp_int_cntl |= CP_INT_CNTL_RING1__TIME_STAMP_INT_ENABLE_MASK;
3243 WREG32(mmCP_INT_CNTL_RING1, cp_int_cntl);
3246 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING2);
3247 cp_int_cntl |= CP_INT_CNTL_RING2__TIME_STAMP_INT_ENABLE_MASK;
3248 WREG32(mmCP_INT_CNTL_RING2, cp_int_cntl);
3260 static int gfx_v6_0_set_priv_reg_fault_state(struct amdgpu_device *adev,
3261 struct amdgpu_irq_src *src,
3263 enum amdgpu_interrupt_state state)
3268 case AMDGPU_IRQ_STATE_DISABLE:
3269 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
3270 cp_int_cntl &= ~CP_INT_CNTL_RING0__PRIV_REG_INT_ENABLE_MASK;
3271 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
3273 case AMDGPU_IRQ_STATE_ENABLE:
3274 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
3275 cp_int_cntl |= CP_INT_CNTL_RING0__PRIV_REG_INT_ENABLE_MASK;
3276 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
3285 static int gfx_v6_0_set_priv_inst_fault_state(struct amdgpu_device *adev,
3286 struct amdgpu_irq_src *src,
3288 enum amdgpu_interrupt_state state)
3293 case AMDGPU_IRQ_STATE_DISABLE:
3294 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
3295 cp_int_cntl &= ~CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE_MASK;
3296 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
3298 case AMDGPU_IRQ_STATE_ENABLE:
3299 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
3300 cp_int_cntl |= CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE_MASK;
3301 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
3310 static int gfx_v6_0_set_eop_interrupt_state(struct amdgpu_device *adev,
3311 struct amdgpu_irq_src *src,
3313 enum amdgpu_interrupt_state state)
3316 case AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP:
3317 gfx_v6_0_set_gfx_eop_interrupt_state(adev, state);
3319 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP:
3320 gfx_v6_0_set_compute_eop_interrupt_state(adev, 0, state);
3322 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP:
3323 gfx_v6_0_set_compute_eop_interrupt_state(adev, 1, state);
3331 static int gfx_v6_0_eop_irq(struct amdgpu_device *adev,
3332 struct amdgpu_irq_src *source,
3333 struct amdgpu_iv_entry *entry)
3335 switch (entry->ring_id) {
3337 amdgpu_fence_process(&adev->gfx.gfx_ring[0]);
3341 amdgpu_fence_process(&adev->gfx.compute_ring[entry->ring_id - 1]);
3349 static void gfx_v6_0_fault(struct amdgpu_device *adev,
3350 struct amdgpu_iv_entry *entry)
3352 struct amdgpu_ring *ring;
3354 switch (entry->ring_id) {
3356 ring = &adev->gfx.gfx_ring[0];
3360 ring = &adev->gfx.compute_ring[entry->ring_id - 1];
3365 drm_sched_fault(&ring->sched);
3368 static int gfx_v6_0_priv_reg_irq(struct amdgpu_device *adev,
3369 struct amdgpu_irq_src *source,
3370 struct amdgpu_iv_entry *entry)
3372 DRM_ERROR("Illegal register access in command stream\n");
3373 gfx_v6_0_fault(adev, entry);
3377 static int gfx_v6_0_priv_inst_irq(struct amdgpu_device *adev,
3378 struct amdgpu_irq_src *source,
3379 struct amdgpu_iv_entry *entry)
3381 DRM_ERROR("Illegal instruction in command stream\n");
3382 gfx_v6_0_fault(adev, entry);
3386 static int gfx_v6_0_set_clockgating_state(void *handle,
3387 enum amd_clockgating_state state)
3390 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3392 if (state == AMD_CG_STATE_GATE)
3395 gfx_v6_0_enable_gui_idle_interrupt(adev, false);
3397 gfx_v6_0_enable_mgcg(adev, true);
3398 gfx_v6_0_enable_cgcg(adev, true);
3400 gfx_v6_0_enable_cgcg(adev, false);
3401 gfx_v6_0_enable_mgcg(adev, false);
3403 gfx_v6_0_enable_gui_idle_interrupt(adev, true);
3408 static int gfx_v6_0_set_powergating_state(void *handle,
3409 enum amd_powergating_state state)
3412 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3414 if (state == AMD_PG_STATE_GATE)
3417 if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG |
3418 AMD_PG_SUPPORT_GFX_SMG |
3419 AMD_PG_SUPPORT_GFX_DMG |
3421 AMD_PG_SUPPORT_GDS |
3422 AMD_PG_SUPPORT_RLC_SMU_HS)) {
3423 gfx_v6_0_update_gfx_pg(adev, gate);
3424 if (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG) {
3425 gfx_v6_0_enable_cp_pg(adev, gate);
3426 gfx_v6_0_enable_gds_pg(adev, gate);
3433 static void gfx_v6_0_emit_mem_sync(struct amdgpu_ring *ring)
3435 amdgpu_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3));
3436 amdgpu_ring_write(ring, PACKET3_TCL1_ACTION_ENA |
3437 PACKET3_TC_ACTION_ENA |
3438 PACKET3_SH_KCACHE_ACTION_ENA |
3439 PACKET3_SH_ICACHE_ACTION_ENA); /* CP_COHER_CNTL */
3440 amdgpu_ring_write(ring, 0xffffffff); /* CP_COHER_SIZE */
3441 amdgpu_ring_write(ring, 0); /* CP_COHER_BASE */
3442 amdgpu_ring_write(ring, 0x0000000A); /* poll interval */
3445 static const struct amd_ip_funcs gfx_v6_0_ip_funcs = {
3447 .early_init = gfx_v6_0_early_init,
3449 .sw_init = gfx_v6_0_sw_init,
3450 .sw_fini = gfx_v6_0_sw_fini,
3451 .hw_init = gfx_v6_0_hw_init,
3452 .hw_fini = gfx_v6_0_hw_fini,
3453 .suspend = gfx_v6_0_suspend,
3454 .resume = gfx_v6_0_resume,
3455 .is_idle = gfx_v6_0_is_idle,
3456 .wait_for_idle = gfx_v6_0_wait_for_idle,
3457 .soft_reset = gfx_v6_0_soft_reset,
3458 .set_clockgating_state = gfx_v6_0_set_clockgating_state,
3459 .set_powergating_state = gfx_v6_0_set_powergating_state,
3462 static const struct amdgpu_ring_funcs gfx_v6_0_ring_funcs_gfx = {
3463 .type = AMDGPU_RING_TYPE_GFX,
3466 .support_64bit_ptrs = false,
3467 .get_rptr = gfx_v6_0_ring_get_rptr,
3468 .get_wptr = gfx_v6_0_ring_get_wptr,
3469 .set_wptr = gfx_v6_0_ring_set_wptr_gfx,
3471 5 + 5 + /* hdp flush / invalidate */
3472 14 + 14 + 14 + /* gfx_v6_0_ring_emit_fence x3 for user fence, vm fence */
3473 7 + 4 + /* gfx_v6_0_ring_emit_pipeline_sync */
3474 SI_FLUSH_GPU_TLB_NUM_WREG * 5 + 7 + 6 + /* gfx_v6_0_ring_emit_vm_flush */
3475 3 + 2 + /* gfx_v6_ring_emit_cntxcntl including vgt flush */
3476 5, /* SURFACE_SYNC */
3477 .emit_ib_size = 6, /* gfx_v6_0_ring_emit_ib */
3478 .emit_ib = gfx_v6_0_ring_emit_ib,
3479 .emit_fence = gfx_v6_0_ring_emit_fence,
3480 .emit_pipeline_sync = gfx_v6_0_ring_emit_pipeline_sync,
3481 .emit_vm_flush = gfx_v6_0_ring_emit_vm_flush,
3482 .test_ring = gfx_v6_0_ring_test_ring,
3483 .test_ib = gfx_v6_0_ring_test_ib,
3484 .insert_nop = amdgpu_ring_insert_nop,
3485 .emit_cntxcntl = gfx_v6_ring_emit_cntxcntl,
3486 .emit_wreg = gfx_v6_0_ring_emit_wreg,
3487 .emit_mem_sync = gfx_v6_0_emit_mem_sync,
3490 static const struct amdgpu_ring_funcs gfx_v6_0_ring_funcs_compute = {
3491 .type = AMDGPU_RING_TYPE_COMPUTE,
3494 .get_rptr = gfx_v6_0_ring_get_rptr,
3495 .get_wptr = gfx_v6_0_ring_get_wptr,
3496 .set_wptr = gfx_v6_0_ring_set_wptr_compute,
3498 5 + 5 + /* hdp flush / invalidate */
3499 7 + /* gfx_v6_0_ring_emit_pipeline_sync */
3500 SI_FLUSH_GPU_TLB_NUM_WREG * 5 + 7 + /* gfx_v6_0_ring_emit_vm_flush */
3501 14 + 14 + 14 + /* gfx_v6_0_ring_emit_fence x3 for user fence, vm fence */
3502 5, /* SURFACE_SYNC */
3503 .emit_ib_size = 6, /* gfx_v6_0_ring_emit_ib */
3504 .emit_ib = gfx_v6_0_ring_emit_ib,
3505 .emit_fence = gfx_v6_0_ring_emit_fence,
3506 .emit_pipeline_sync = gfx_v6_0_ring_emit_pipeline_sync,
3507 .emit_vm_flush = gfx_v6_0_ring_emit_vm_flush,
3508 .test_ring = gfx_v6_0_ring_test_ring,
3509 .test_ib = gfx_v6_0_ring_test_ib,
3510 .insert_nop = amdgpu_ring_insert_nop,
3511 .emit_wreg = gfx_v6_0_ring_emit_wreg,
3512 .emit_mem_sync = gfx_v6_0_emit_mem_sync,
3515 static void gfx_v6_0_set_ring_funcs(struct amdgpu_device *adev)
3519 for (i = 0; i < adev->gfx.num_gfx_rings; i++)
3520 adev->gfx.gfx_ring[i].funcs = &gfx_v6_0_ring_funcs_gfx;
3521 for (i = 0; i < adev->gfx.num_compute_rings; i++)
3522 adev->gfx.compute_ring[i].funcs = &gfx_v6_0_ring_funcs_compute;
3525 static const struct amdgpu_irq_src_funcs gfx_v6_0_eop_irq_funcs = {
3526 .set = gfx_v6_0_set_eop_interrupt_state,
3527 .process = gfx_v6_0_eop_irq,
3530 static const struct amdgpu_irq_src_funcs gfx_v6_0_priv_reg_irq_funcs = {
3531 .set = gfx_v6_0_set_priv_reg_fault_state,
3532 .process = gfx_v6_0_priv_reg_irq,
3535 static const struct amdgpu_irq_src_funcs gfx_v6_0_priv_inst_irq_funcs = {
3536 .set = gfx_v6_0_set_priv_inst_fault_state,
3537 .process = gfx_v6_0_priv_inst_irq,
3540 static void gfx_v6_0_set_irq_funcs(struct amdgpu_device *adev)
3542 adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST;
3543 adev->gfx.eop_irq.funcs = &gfx_v6_0_eop_irq_funcs;
3545 adev->gfx.priv_reg_irq.num_types = 1;
3546 adev->gfx.priv_reg_irq.funcs = &gfx_v6_0_priv_reg_irq_funcs;
3548 adev->gfx.priv_inst_irq.num_types = 1;
3549 adev->gfx.priv_inst_irq.funcs = &gfx_v6_0_priv_inst_irq_funcs;
3552 static void gfx_v6_0_get_cu_info(struct amdgpu_device *adev)
3554 int i, j, k, counter, active_cu_number = 0;
3555 u32 mask, bitmap, ao_bitmap, ao_cu_mask = 0;
3556 struct amdgpu_cu_info *cu_info = &adev->gfx.cu_info;
3557 unsigned disable_masks[4 * 2];
3560 if (adev->flags & AMD_IS_APU)
3563 ao_cu_num = adev->gfx.config.max_cu_per_sh;
3565 memset(cu_info, 0, sizeof(*cu_info));
3567 amdgpu_gfx_parse_disable_cu(disable_masks, 4, 2);
3569 mutex_lock(&adev->grbm_idx_mutex);
3570 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
3571 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
3575 gfx_v6_0_select_se_sh(adev, i, j, 0xffffffff, 0);
3577 gfx_v6_0_set_user_cu_inactive_bitmap(
3578 adev, disable_masks[i * 2 + j]);
3579 bitmap = gfx_v6_0_get_cu_enabled(adev);
3580 cu_info->bitmap[0][i][j] = bitmap;
3582 for (k = 0; k < adev->gfx.config.max_cu_per_sh; k++) {
3583 if (bitmap & mask) {
3584 if (counter < ao_cu_num)
3590 active_cu_number += counter;
3592 ao_cu_mask |= (ao_bitmap << (i * 16 + j * 8));
3593 cu_info->ao_cu_bitmap[i][j] = ao_bitmap;
3597 gfx_v6_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0);
3598 mutex_unlock(&adev->grbm_idx_mutex);
3600 cu_info->number = active_cu_number;
3601 cu_info->ao_cu_mask = ao_cu_mask;
3604 const struct amdgpu_ip_block_version gfx_v6_0_ip_block =
3606 .type = AMD_IP_BLOCK_TYPE_GFX,
3610 .funcs = &gfx_v6_0_ip_funcs,
projects / linux-2.6-microblaze.git / blob