drivers/gpu/drm/amd/amdgpu/gfx_v11_0_3.c

   1 /*
   2  * Copyright 2023 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #include "amdgpu.h"
  25 #include "soc21.h"
  26 #include "gc/gc_11_0_3_offset.h"
  27 #include "gc/gc_11_0_3_sh_mask.h"
  28 #include "ivsrcid/gfx/irqsrcs_gfx_11_0_0.h"
  29 #include "soc15.h"
  30 #include "soc15d.h"
  31 #include "gfx_v11_0.h"
  32
  33
  34 static int gfx_v11_0_3_rlc_gc_fed_irq(struct amdgpu_device *adev,
  35                                   struct amdgpu_irq_src *source,
  36                                   struct amdgpu_iv_entry *entry)
  37 {
  38         uint32_t rlc_status0 = 0, rlc_status1 = 0;
  39         struct ras_common_if *ras_if = NULL;
  40         struct ras_dispatch_if ih_data = {
  41                 .entry = entry,
  42         };
  43
  44         rlc_status0 = RREG32(SOC15_REG_OFFSET(GC, 0, regRLC_RLCS_FED_STATUS_0));
  45         rlc_status1 = RREG32(SOC15_REG_OFFSET(GC, 0, regRLC_RLCS_FED_STATUS_1));
  46
  47         if (!rlc_status0 && !rlc_status1) {
  48                 dev_warn(adev->dev, "RLC_GC_FED irq is generated, but rlc_status0 and rlc_status1 are empty!\n");
  49                 return 0;
  50         }
  51
  52         /* Use RLC_RLCS_FED_STATUS_0/1 to distinguish FED error block. */
  53         if (REG_GET_FIELD(rlc_status0, RLC_RLCS_FED_STATUS_0, SDMA0_FED_ERR) ||
  54             REG_GET_FIELD(rlc_status0, RLC_RLCS_FED_STATUS_0, SDMA1_FED_ERR))
  55                 ras_if = adev->sdma.ras_if;
  56         else
  57                 ras_if = adev->gfx.ras_if;
  58
  59         if (!ras_if) {
  60                 dev_err(adev->dev, "Gfx or sdma ras block not initialized, rlc_status0:0x%x.\n",
  61                                 rlc_status0);
  62                 return -EINVAL;
  63         }
  64
  65         dev_warn(adev->dev, "RLC %s FED IRQ\n", ras_if->name);
  66
  67         if (!amdgpu_sriov_vf(adev)) {
  68                 ih_data.head = *ras_if;
  69                 amdgpu_ras_interrupt_dispatch(adev, &ih_data);
  70         } else {
  71                 if (adev->virt.ops && adev->virt.ops->ras_poison_handler)
  72                         adev->virt.ops->ras_poison_handler(adev);
  73                 else
  74                         dev_warn(adev->dev,
  75                                 "No ras_poison_handler interface in SRIOV for %s!\n", ras_if->name);
  76         }
  77
  78         return 0;
  79 }
  80
  81 static int gfx_v11_0_3_poison_consumption_handler(struct amdgpu_device *adev,
  82                                         struct amdgpu_iv_entry *entry)
  83 {
  84         /* Workaround: when vmid and pasid are both zero, trigger gpu reset in KGD. */
  85         if (entry && (entry->client_id == SOC21_IH_CLIENTID_GFX) &&
  86             (entry->src_id == GFX_11_0_0__SRCID__RLC_GC_FED_INTERRUPT) &&
  87              !entry->vmid && !entry->pasid) {
  88                 uint32_t rlc_status0 = 0;
  89
  90                 rlc_status0 = RREG32_SOC15(GC, 0, regRLC_RLCS_FED_STATUS_0);
  91
  92                 if (REG_GET_FIELD(rlc_status0, RLC_RLCS_FED_STATUS_0, SDMA0_FED_ERR) ||
  93                     REG_GET_FIELD(rlc_status0, RLC_RLCS_FED_STATUS_0, SDMA1_FED_ERR)) {
  94                         struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
  95
  96                         ras->gpu_reset_flags |= AMDGPU_RAS_GPU_RESET_MODE2_RESET;
  97                 }
  98
  99                 amdgpu_ras_reset_gpu(adev);
 100         }
 101
 102         return 0;
 103 }
 104
 105 struct amdgpu_gfx_ras gfx_v11_0_3_ras = {
 106         .rlc_gc_fed_irq = gfx_v11_0_3_rlc_gc_fed_irq,
 107         .poison_consumption_handler = gfx_v11_0_3_poison_consumption_handler,
 108 };