drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

   1 /*
   2  * Copyright 2019 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #include <linux/delay.h>
  25 #include <linux/kernel.h>
  26 #include <linux/firmware.h>
  27 #include <linux/module.h>
  28 #include <linux/pci.h>
  29 #include "amdgpu.h"
  30 #include "amdgpu_gfx.h"
  31 #include "amdgpu_psp.h"
  32 #include "amdgpu_smu.h"
  33 #include "nv.h"
  34 #include "nvd.h"
  35
  36 #include "gc/gc_10_1_0_offset.h"
  37 #include "gc/gc_10_1_0_sh_mask.h"
  38 #include "smuio/smuio_11_0_0_offset.h"
  39 #include "smuio/smuio_11_0_0_sh_mask.h"
  40 #include "navi10_enum.h"
  41 #include "hdp/hdp_5_0_0_offset.h"
  42 #include "ivsrcid/gfx/irqsrcs_gfx_10_1.h"
  43
  44 #include "soc15.h"
  45 #include "soc15d.h"
  46 #include "soc15_common.h"
  47 #include "clearstate_gfx10.h"
  48 #include "v10_structs.h"
  49 #include "gfx_v10_0.h"
  50 #include "nbio_v2_3.h"
  51
  52 /**
  53  * Navi10 has two graphic rings to share each graphic pipe.
  54  * 1. Primary ring
  55  * 2. Async ring
  56  */
  57 #define GFX10_NUM_GFX_RINGS_NV1X        1
  58 #define GFX10_NUM_GFX_RINGS_Sienna_Cichlid      1
  59 #define GFX10_MEC_HPD_SIZE      2048
  60
  61 #define F32_CE_PROGRAM_RAM_SIZE         65536
  62 #define RLCG_UCODE_LOADING_START_ADDRESS        0x00002000L
  63
  64 #define mmCGTT_GS_NGG_CLK_CTRL  0x5087
  65 #define mmCGTT_GS_NGG_CLK_CTRL_BASE_IDX 1
  66 #define mmCGTT_SPI_RA0_CLK_CTRL 0x507a
  67 #define mmCGTT_SPI_RA0_CLK_CTRL_BASE_IDX 1
  68 #define mmCGTT_SPI_RA1_CLK_CTRL 0x507b
  69 #define mmCGTT_SPI_RA1_CLK_CTRL_BASE_IDX 1
  70
  71 #define GB_ADDR_CONFIG__NUM_PKRS__SHIFT                                                                       0x8
  72 #define GB_ADDR_CONFIG__NUM_PKRS_MASK                                                                         0x00000700L
  73
  74 #define mmCP_MEC_CNTL_Sienna_Cichlid                      0x0f55
  75 #define mmCP_MEC_CNTL_Sienna_Cichlid_BASE_IDX             0
  76 #define mmRLC_SAFE_MODE_Sienna_Cichlid                  0x4ca0
  77 #define mmRLC_SAFE_MODE_Sienna_Cichlid_BASE_IDX         1
  78 #define mmRLC_CP_SCHEDULERS_Sienna_Cichlid              0x4ca1
  79 #define mmRLC_CP_SCHEDULERS_Sienna_Cichlid_BASE_IDX     1
  80 #define mmSPI_CONFIG_CNTL_Sienna_Cichlid                        0x11ec
  81 #define mmSPI_CONFIG_CNTL_Sienna_Cichlid_BASE_IDX               0
  82 #define mmVGT_ESGS_RING_SIZE_Sienna_Cichlid             0x0fc1
  83 #define mmVGT_ESGS_RING_SIZE_Sienna_Cichlid_BASE_IDX    0
  84 #define mmVGT_GSVS_RING_SIZE_Sienna_Cichlid             0x0fc2
  85 #define mmVGT_GSVS_RING_SIZE_Sienna_Cichlid_BASE_IDX    0
  86 #define mmVGT_TF_RING_SIZE_Sienna_Cichlid                       0x0fc3
  87 #define mmVGT_TF_RING_SIZE_Sienna_Cichlid_BASE_IDX      0
  88 #define mmVGT_HS_OFFCHIP_PARAM_Sienna_Cichlid           0x0fc4
  89 #define mmVGT_HS_OFFCHIP_PARAM_Sienna_Cichlid_BASE_IDX  0
  90 #define mmVGT_TF_MEMORY_BASE_Sienna_Cichlid             0x0fc5
  91 #define mmVGT_TF_MEMORY_BASE_Sienna_Cichlid_BASE_IDX    0
  92 #define mmVGT_TF_MEMORY_BASE_HI_Sienna_Cichlid          0x0fc6
  93 #define mmVGT_TF_MEMORY_BASE_HI_Sienna_Cichlid_BASE_IDX 0
  94 #define GRBM_STATUS2__RLC_BUSY_Sienna_Cichlid__SHIFT    0x1a
  95 #define GRBM_STATUS2__RLC_BUSY_Sienna_Cichlid_MASK      0x04000000L
  96 #define CP_RB_DOORBELL_RANGE_LOWER__DOORBELL_RANGE_LOWER_Sienna_Cichlid_MASK    0x00000FFCL
  97 #define CP_RB_DOORBELL_RANGE_LOWER__DOORBELL_RANGE_LOWER_Sienna_Cichlid__SHIFT  0x2
  98 #define CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_Sienna_Cichlid_MASK    0x00000FFCL
  99 #define mmGCR_GENERAL_CNTL_Sienna_Cichlid                       0x1580
 100 #define mmGCR_GENERAL_CNTL_Sienna_Cichlid_BASE_IDX      0
 101
 102 #define mmCP_HYP_PFP_UCODE_ADDR                 0x5814
 103 #define mmCP_HYP_PFP_UCODE_ADDR_BASE_IDX        1
 104 #define mmCP_HYP_PFP_UCODE_DATA                 0x5815
 105 #define mmCP_HYP_PFP_UCODE_DATA_BASE_IDX        1
 106 #define mmCP_HYP_CE_UCODE_ADDR                  0x5818
 107 #define mmCP_HYP_CE_UCODE_ADDR_BASE_IDX         1
 108 #define mmCP_HYP_CE_UCODE_DATA                  0x5819
 109 #define mmCP_HYP_CE_UCODE_DATA_BASE_IDX         1
 110 #define mmCP_HYP_ME_UCODE_ADDR                  0x5816
 111 #define mmCP_HYP_ME_UCODE_ADDR_BASE_IDX         1
 112 #define mmCP_HYP_ME_UCODE_DATA                  0x5817
 113 #define mmCP_HYP_ME_UCODE_DATA_BASE_IDX         1
 114
 115 MODULE_FIRMWARE("amdgpu/navi10_ce.bin");
 116 MODULE_FIRMWARE("amdgpu/navi10_pfp.bin");
 117 MODULE_FIRMWARE("amdgpu/navi10_me.bin");
 118 MODULE_FIRMWARE("amdgpu/navi10_mec.bin");
 119 MODULE_FIRMWARE("amdgpu/navi10_mec2.bin");
 120 MODULE_FIRMWARE("amdgpu/navi10_rlc.bin");
 121
 122 MODULE_FIRMWARE("amdgpu/navi14_ce_wks.bin");
 123 MODULE_FIRMWARE("amdgpu/navi14_pfp_wks.bin");
 124 MODULE_FIRMWARE("amdgpu/navi14_me_wks.bin");
 125 MODULE_FIRMWARE("amdgpu/navi14_mec_wks.bin");
 126 MODULE_FIRMWARE("amdgpu/navi14_mec2_wks.bin");
 127 MODULE_FIRMWARE("amdgpu/navi14_ce.bin");
 128 MODULE_FIRMWARE("amdgpu/navi14_pfp.bin");
 129 MODULE_FIRMWARE("amdgpu/navi14_me.bin");
 130 MODULE_FIRMWARE("amdgpu/navi14_mec.bin");
 131 MODULE_FIRMWARE("amdgpu/navi14_mec2.bin");
 132 MODULE_FIRMWARE("amdgpu/navi14_rlc.bin");
 133
 134 MODULE_FIRMWARE("amdgpu/navi12_ce.bin");
 135 MODULE_FIRMWARE("amdgpu/navi12_pfp.bin");
 136 MODULE_FIRMWARE("amdgpu/navi12_me.bin");
 137 MODULE_FIRMWARE("amdgpu/navi12_mec.bin");
 138 MODULE_FIRMWARE("amdgpu/navi12_mec2.bin");
 139 MODULE_FIRMWARE("amdgpu/navi12_rlc.bin");
 140
 141 MODULE_FIRMWARE("amdgpu/sienna_cichlid_ce.bin");
 142 MODULE_FIRMWARE("amdgpu/sienna_cichlid_pfp.bin");
 143 MODULE_FIRMWARE("amdgpu/sienna_cichlid_me.bin");
 144 MODULE_FIRMWARE("amdgpu/sienna_cichlid_mec.bin");
 145 MODULE_FIRMWARE("amdgpu/sienna_cichlid_mec2.bin");
 146 MODULE_FIRMWARE("amdgpu/sienna_cichlid_rlc.bin");
 147
 148 MODULE_FIRMWARE("amdgpu/navy_flounder_ce.bin");
 149 MODULE_FIRMWARE("amdgpu/navy_flounder_pfp.bin");
 150 MODULE_FIRMWARE("amdgpu/navy_flounder_me.bin");
 151 MODULE_FIRMWARE("amdgpu/navy_flounder_mec.bin");
 152 MODULE_FIRMWARE("amdgpu/navy_flounder_mec2.bin");
 153 MODULE_FIRMWARE("amdgpu/navy_flounder_rlc.bin");
 154
 155 static const struct soc15_reg_golden golden_settings_gc_10_1[] =
 156 {
 157         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0xffffffff, 0x00400014),
 158         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_CPF_CLK_CTRL, 0xfcff8fff, 0xf8000100),
 159         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xcd000000, 0x0d000100),
 160         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQ_CLK_CTRL, 0x60000ff0, 0x60000100),
 161         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQG_CLK_CTRL, 0x40000000, 0x40000100),
 162         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xffff8fff, 0xffff8100),
 163         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_WD_CLK_CTRL, 0xfeff8fff, 0xfeff8100),
 164         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
 165         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_VC5_ENABLE, 0x00000002, 0x00000000),
 166         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0x000007ff, 0x000005ff),
 167         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG, 0x20000000, 0x20000000),
 168         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xffffffff, 0x00000420),
 169         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0x00000200, 0x00000200),
 170         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0x07900000, 0x04900000),
 171         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DFSM_TILES_IN_FLIGHT, 0x0000ffff, 0x0000003f),
 172         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_LAST_OF_BURST_CONFIG, 0xffffffff, 0x03860204),
 173         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff0ffff, 0x00000500),
 174         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PRIV_CONTROL, 0x000007ff, 0x000001fe),
 175         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
 176         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x10321032),
 177         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x02310231),
 178         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
 179         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
 180         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CGTT_SCLK_CTRL, 0x10000000, 0x10000100),
 181         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL2, 0xffffffff, 0x1402002f),
 182         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xffff9fff, 0x00001188),
 183         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
 184         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x08000009),
 185         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0x00400000, 0x04440000),
 186         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0x00000800, 0x00000820),
 187         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000),
 188         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0xffffffff, 0xffff3101),
 189         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0x001f0000, 0x00070104),
 190         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ALU_CLK_CTRL, 0xffffffff, 0xffffffff),
 191         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x00000100, 0x00000130),
 192         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0xffffffff, 0xffffffff),
 193         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
 194         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CNTL, 0x60000010, 0x479c0010),
 195         SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CGTT_CLK_CTRL, 0xfeff0fff, 0x40000100),
 196         SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0x00c00000, 0x00c00000)
 197 };
 198
 199 static const struct soc15_reg_golden golden_settings_gc_10_0_nv10[] =
 200 {
 201         /* Pending on emulation bring up */
 202 };
 203
 204 static const struct soc15_reg_golden golden_settings_gc_rlc_spm_10_0_nv10[] =
 205 {
 206         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xe0000000, 0x0),
 207         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 208         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
 209         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 210         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
 211         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 212         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
 213         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 214         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
 215         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 216         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
 217         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 218         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
 219         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 220         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
 221         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 222         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 223         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 224         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8),
 225         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 226         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
 227         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 228         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc),
 229         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 230         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
 231         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 232         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0),
 233         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 234         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
 235         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 236         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4),
 237         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 238         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
 239         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 240         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
 241         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 242         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
 243         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 244         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
 245         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 246         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
 247         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 248         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
 249         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 250         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
 251         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 252         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
 253         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 254         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
 255         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 256         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
 257         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 258         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
 259         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 260         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
 261         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 262         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
 263         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 264         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
 265         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 266         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
 267         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 268         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
 269         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 270         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
 271         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 272         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
 273         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 274         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
 275         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 276         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0),
 277         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 278         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
 279         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 280         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4),
 281         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 282         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
 283         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 284         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8),
 285         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 286         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 287         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 288         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc),
 289         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 290         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
 291         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 292         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0),
 293         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 294         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 295         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 296         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4),
 297         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 298         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 299         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 300         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90),
 301         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 302         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
 303         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 304         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94),
 305         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 306         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
 307         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 308         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98),
 309         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 310         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
 311         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 312         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c),
 313         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 314         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
 315         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 316         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0),
 317         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 318         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
 319         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 320         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4),
 321         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 322         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
 323         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 324         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8),
 325         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 326         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
 327         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 328         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac),
 329         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 330         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
 331         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 332         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
 333         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 334         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
 335         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 336         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
 337         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 338         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
 339         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 340         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
 341         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 342         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
 343         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 344         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
 345         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 346         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
 347         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 348         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
 349         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 350         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
 351         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 352         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
 353         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 354         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 355         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 356         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
 357         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 358         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
 359         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 360         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
 361         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 362         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
 363         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 364         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
 365         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 366         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
 367         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 368         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
 369         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 370         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
 371         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 372         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
 373         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 374         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
 375         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 376         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
 377         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 378         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
 379         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 380         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
 381         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 382         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
 383         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 384         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
 385         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 386         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
 387         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 388         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
 389         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 390         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
 391         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 392         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
 393         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 394         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
 395         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 396         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
 397         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 398         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
 399         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 400         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
 401         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 402         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
 403         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 404         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
 405         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 406         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
 407         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 408         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
 409         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 410         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
 411         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 412         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
 413         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 414         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
 415         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 416         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
 417         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 418         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
 419         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 420         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
 421         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 422         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
 423         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 424         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c),
 425         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 426         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
 427         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 428         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
 429         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 430         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 431         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 432         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
 433         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 434         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
 435         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 436         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
 437         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 438         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
 439         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 440         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
 441         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 442         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
 443         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 444         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
 445         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 446         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
 447         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 448         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
 449         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 450         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 451         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 452         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
 453         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 454         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 455         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 456         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
 457         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 458         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
 459         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 460         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
 461         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 462         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
 463         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 464         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
 465         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 466         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 467         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 468         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
 469         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 470         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 471         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 472         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
 473         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 474         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
 475         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 476         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
 477         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 478         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
 479         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 480         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
 481         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 482         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 483         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 484         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
 485         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 486         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 487         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 488         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
 489         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 490         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
 491         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 492         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
 493         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 494         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
 495         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 496         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
 497         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 498         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
 499         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 500         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
 501         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 502         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
 503         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 504         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
 505         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 506         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 507         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 508         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
 509         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 510         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 511         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 512         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
 513         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 514         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 515         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 516         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
 517         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 518         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 519         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 520         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
 521         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 522         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 523         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 524         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
 525         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 526         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 527         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 528         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
 529         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 530         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 531         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 532         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
 533         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 534         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 535         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 536         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
 537         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 538         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
 539         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 540         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
 541         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 542         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
 543         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 544         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
 545         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 546         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
 547         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 548         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
 549         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 550         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
 551         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 552         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
 553         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 554         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
 555         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 556         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
 557         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 558         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
 559         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 560         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
 561         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 562         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
 563         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 564         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
 565         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 566         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
 567         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 568         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
 569         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 570         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
 571         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 572         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
 573         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 574         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
 575         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 576         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
 577         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 578         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17),
 579         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 580         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
 581         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 582         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17),
 583         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 584         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
 585         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 586         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 587         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 588         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
 589         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 590         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 591         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 592         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
 593         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 594         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
 595         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 596         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
 597         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 598         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
 599         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 600         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
 601         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 602         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
 603         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 604         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
 605         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 606         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
 607         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 608         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
 609         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 610         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 611         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 612         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
 613         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 614         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 615         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 616         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
 617         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 618         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 619         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 620         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
 621         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 622         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 623         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 624         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
 625         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 626         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
 627         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 628         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
 629         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 630         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
 631         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 632         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
 633         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 634         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
 635         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 636         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
 637         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 638         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
 639         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 640         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
 641         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 642         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 643         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 644         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
 645         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 646         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 647         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 648         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
 649         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 650         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 651         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 652         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
 653         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 654         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 655         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 656         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
 657         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 658         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 659         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 660         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
 661         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 662         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 663         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 664         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
 665         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 666         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 667         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 668         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
 669         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 670         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 671         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 672         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
 673         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 674         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 675         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 676         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
 677         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 678         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 679         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 680         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90),
 681         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 682         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
 683         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 684         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90),
 685         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 686         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
 687         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 688         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94),
 689         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 690         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
 691         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 692         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94),
 693         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 694         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
 695         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 696         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0),
 697         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 698         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
 699         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 700         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0),
 701         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 702         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
 703         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 704         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4),
 705         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 706         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
 707         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 708         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4),
 709         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 710         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
 711         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 712         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98),
 713         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 714         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
 715         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 716         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98),
 717         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 718         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
 719         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 720         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c),
 721         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 722         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
 723         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 724         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c),
 725         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 726         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
 727         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 728         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8),
 729         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 730         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 731         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 732         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8),
 733         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 734         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 735         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 736         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac),
 737         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 738         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 739         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 740         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac),
 741         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 742         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 743         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 744         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8),
 745         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 746         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
 747         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 748         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8),
 749         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 750         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
 751         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 752         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc),
 753         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 754         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
 755         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 756         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc),
 757         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 758         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
 759         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 760         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0),
 761         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 762         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 763         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 764         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0),
 765         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 766         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 767         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 768         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4),
 769         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 770         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 771         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 772         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4),
 773         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 774         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 775         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 776         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0),
 777         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 778         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
 779         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 780         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0),
 781         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 782         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
 783         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 784         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4),
 785         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 786         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 787         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 788         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4),
 789         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 790         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 791         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 792         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0),
 793         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 794         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
 795         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 796         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0),
 797         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 798         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
 799         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 800         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4),
 801         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 802         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
 803         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 804         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4),
 805         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 806         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
 807         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 808         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8),
 809         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 810         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
 811         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 812         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8),
 813         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 814         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
 815         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 816         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc),
 817         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 818         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
 819         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 820         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc),
 821         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 822         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
 823         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 824         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8),
 825         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 826         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 827         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 828         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8),
 829         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 830         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 831         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 832         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec),
 833         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 834         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 835         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 836         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec),
 837         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 838         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 839         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 840         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0),
 841         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 842         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
 843         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 844         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0),
 845         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 846         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
 847         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 848         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4),
 849         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 850         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
 851         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 852         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4),
 853         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 854         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
 855         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 856         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8),
 857         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 858         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 859         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 860         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8),
 861         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 862         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 863         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 864         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xfc),
 865         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 866         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 867         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 868         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xfc),
 869         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 870         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 871         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 872         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100),
 873         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 874         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 875         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 876         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100),
 877         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 878         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 879         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 880         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104),
 881         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 882         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
 883         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 884         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104),
 885         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 886         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
 887         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 888         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0),
 889         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 890         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
 891         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 892         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0),
 893         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 894         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
 895         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 896         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118),
 897         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 898         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
 899         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 900         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118),
 901         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 902         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
 903         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 904         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c),
 905         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 906         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
 907         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 908         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c),
 909         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 910         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
 911         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 912         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120),
 913         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 914         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
 915         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 916         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120),
 917         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 918         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
 919         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 920         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124),
 921         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 922         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
 923         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 924         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124),
 925         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 926         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
 927         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 928         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc),
 929         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 930         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
 931         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 932         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc),
 933         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 934         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
 935         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 936         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110),
 937         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 938         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
 939         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 940         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110),
 941         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 942         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
 943         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 944         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114),
 945         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 946         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
 947         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 948         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114),
 949         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 950         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
 951         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 952         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108),
 953         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 954         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 955         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 956         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108),
 957         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 958         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 959         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 960         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c),
 961         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 962         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 963         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 964         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c),
 965         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 966         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 967         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 968         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8),
 969         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 970         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17),
 971         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 972         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8),
 973         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 974         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17),
 975         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 976         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128),
 977         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 978         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
 979         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 980         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128),
 981         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 982         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
 983         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 984         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c),
 985         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 986         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
 987         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 988         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c),
 989         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 990         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
 991         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 992         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138),
 993         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 994         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
 995         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 996         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138),
 997         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 998         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
 999         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1000         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c),
1001         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1002         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1003         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1004         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c),
1005         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1006         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1007         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1008         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130),
1009         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1010         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1011         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1012         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130),
1013         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1014         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1015         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1016         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134),
1017         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1018         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1019         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1020         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134),
1021         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1022         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1023         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1024         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140),
1025         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1026         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1027         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1028         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140),
1029         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1030         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1031         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1032         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144),
1033         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1034         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
1035         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1036         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144),
1037         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1038         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
1039         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1040         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150),
1041         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1042         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1043         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1044         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150),
1045         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1046         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1047         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1048         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154),
1049         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1050         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
1051         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1052         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154),
1053         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1054         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
1055         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1056         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148),
1057         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1058         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1059         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1060         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148),
1061         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1062         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1063         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1064         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c),
1065         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1066         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
1067         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1068         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c),
1069         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1070         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
1071         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1072         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158),
1073         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1074         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
1075         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1076         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158),
1077         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1078         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
1079         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1080         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c),
1081         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1082         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1083         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1084         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c),
1085         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1086         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1087         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1088         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168),
1089         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1090         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1),
1091         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1092         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168),
1093         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1094         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1),
1095         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1096         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c),
1097         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1098         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
1099         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1100         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c),
1101         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1102         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
1103         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1104         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160),
1105         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1106         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
1107         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1108         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160),
1109         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1110         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
1111         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1112         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164),
1113         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1114         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1115         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1116         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164),
1117         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1118         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1119         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1120         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170),
1121         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1122         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
1123         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1124         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170),
1125         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1126         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
1127         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1128         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174),
1129         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1130         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
1131         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1132         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174),
1133         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1134         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
1135         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1136         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180),
1137         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1138         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
1139         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1140         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180),
1141         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1142         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
1143         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1144         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184),
1145         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1146         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1147         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1148         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184),
1149         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1150         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1151         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1152         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178),
1153         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1154         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
1155         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1156         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178),
1157         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1158         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
1159         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1160         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c),
1161         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1162         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
1163         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1164         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c),
1165         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1166         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
1167         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1168         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188),
1169         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1170         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1171         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1172         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188),
1173         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1174         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1175         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1176         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c),
1177         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1178         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
1179         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1180         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c),
1181         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1182         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
1183         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1184         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198),
1185         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1186         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
1187         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1188         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198),
1189         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1190         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
1191         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1192         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c),
1193         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1194         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
1195         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1196         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c),
1197         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1198         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
1199         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1200         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190),
1201         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1202         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1203         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1204         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190),
1205         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1206         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1207         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1208         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194),
1209         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1210         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
1211         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1212         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194),
1213         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1214         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
1215         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1216         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
1217         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1218         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
1219         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1220         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
1221         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1222         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1223         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1224         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
1225         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1226         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
1227         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1228         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
1229         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1230         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
1231         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1232         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
1233         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1234         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1f),
1235         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1236         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
1237         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1238         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1f),
1239         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1240         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
1241         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1242         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
1243         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1244         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_SAMPLE_SKEW, 0x000000FF, 0x19),
1245         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1246         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_MUXSEL_SKEW, 0x000000FF, 0x20),
1247         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1248         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0x5),
1249         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1250         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0xa),
1251         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1252         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x14),
1253         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1254         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x19),
1255         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1256         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_DESER_START_SKEW, 0x000000FF, 0x33),
1257         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xFFFFFFFF, 0xe0000000)
1258 };
1259
1260 static const struct soc15_reg_golden golden_settings_gc_10_1_1[] =
1261 {
1262         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0xffffffff, 0x003c0014),
1263         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_GS_NGG_CLK_CTRL, 0xffff8fff, 0xffff8100),
1264         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_IA_CLK_CTRL, 0xffff0fff, 0xffff0100),
1265         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xcd000000, 0x0d000100),
1266         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQ_CLK_CTRL, 0xf8ff0fff, 0x60000100),
1267         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQG_CLK_CTRL, 0x40000ff0, 0x40000100),
1268         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xffff8fff, 0xffff8100),
1269         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_WD_CLK_CTRL, 0xffff8fff, 0xffff8100),
1270         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
1271         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_VC5_ENABLE, 0x00000002, 0x00000000),
1272         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0x800007ff, 0x000005ff),
1273         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG, 0xffffffff, 0x20000000),
1274         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xffffffff, 0x00000420),
1275         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0x00000200, 0x00000200),
1276         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x04900000),
1277         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DFSM_TILES_IN_FLIGHT, 0x0000ffff, 0x0000003f),
1278         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_LAST_OF_BURST_CONFIG, 0xffffffff, 0x03860204),
1279         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff0ffff, 0x00000500),
1280         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PRIV_CONTROL, 0x000007ff, 0x000001fe),
1281         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
1282         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffe7),
1283         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffe7),
1284         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CGTT_SCLK_CTRL, 0xffff0fff, 0x10000100),
1285         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL2, 0xffffffff, 0x1402002f),
1286         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xffffbfff, 0x00000188),
1287         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
1288         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x08000009),
1289         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0x00400000, 0x04440000),
1290         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0x00000800, 0x00000820),
1291         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000),
1292         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0xffffffff, 0xffff3101),
1293         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0x001f0000, 0x00070105),
1294         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ALU_CLK_CTRL, 0xffffffff, 0xffffffff),
1295         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x00000133, 0x00000130),
1296         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0xffffffff, 0xffffffff),
1297         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
1298         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CNTL, 0x60000010, 0x479c0010),
1299         SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0x00c00000, 0x00c00000),
1300 };
1301
1302 static const struct soc15_reg_golden golden_settings_gc_10_1_2[] =
1303 {
1304         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0x003e001f, 0x003c0014),
1305         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_GS_NGG_CLK_CTRL, 0xffff8fff, 0xffff8100),
1306         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_IA_CLK_CTRL, 0xffff0fff, 0xffff0100),
1307         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xff7f0fff, 0x0d000100),
1308         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQ_CLK_CTRL, 0xffffcfff, 0x60000100),
1309         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQG_CLK_CTRL, 0xffff0fff, 0x40000100),
1310         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xffff8fff, 0xffff8100),
1311         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_WD_CLK_CTRL, 0xffff8fff, 0xffff8100),
1312         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
1313         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_VC5_ENABLE, 0x00000003, 0x00000000),
1314         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0x800007ff, 0x000005ff),
1315         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG, 0xffffffff, 0x20000000),
1316         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xffffffff, 0x00000420),
1317         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000200),
1318         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x04800000),
1319         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DFSM_TILES_IN_FLIGHT, 0x0000ffff, 0x0000003f),
1320         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_LAST_OF_BURST_CONFIG, 0xffffffff, 0x03860204),
1321         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff0ffff, 0x00000500),
1322         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PRIV_CONTROL, 0x00007fff, 0x000001fe),
1323         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
1324         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x10321032),
1325         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x02310231),
1326         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
1327         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
1328         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CGTT_SCLK_CTRL, 0xffff0fff, 0x10000100),
1329         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL2, 0xffffffff, 0x1402002f),
1330         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xffffbfff, 0x00000188),
1331         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_0, 0xffffffff, 0x842a4c02),
1332         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
1333         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x08000009),
1334         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0xffffffff, 0x04440000),
1335         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0x00000820, 0x00000820),
1336         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000),
1337         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0xffffffff, 0xffff3101),
1338         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ALU_CLK_CTRL, 0xffffffff, 0xffffffff),
1339         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x00000133, 0x00000130),
1340         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0xffffffff, 0xffffffff),
1341         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
1342         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CNTL, 0xffdf80ff, 0x479c0010),
1343         SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffffffff, 0x00800000)
1344 };
1345
1346 static void gfx_v10_rlcg_wreg(struct amdgpu_device *adev, u32 offset, u32 v)
1347 {
1348         static void *scratch_reg0;
1349         static void *scratch_reg1;
1350         static void *scratch_reg2;
1351         static void *scratch_reg3;
1352         static void *spare_int;
1353         static uint32_t grbm_cntl;
1354         static uint32_t grbm_idx;
1355         uint32_t i = 0;
1356         uint32_t retries = 50000;
1357
1358         scratch_reg0 = adev->rmmio + (adev->reg_offset[GC_HWIP][0][mmSCRATCH_REG0_BASE_IDX] + mmSCRATCH_REG0)*4;
1359         scratch_reg1 = adev->rmmio + (adev->reg_offset[GC_HWIP][0][mmSCRATCH_REG1_BASE_IDX] + mmSCRATCH_REG1)*4;
1360         scratch_reg2 = adev->rmmio + (adev->reg_offset[GC_HWIP][0][mmSCRATCH_REG1_BASE_IDX] + mmSCRATCH_REG2)*4;
1361         scratch_reg3 = adev->rmmio + (adev->reg_offset[GC_HWIP][0][mmSCRATCH_REG1_BASE_IDX] + mmSCRATCH_REG3)*4;
1362         spare_int = adev->rmmio + (adev->reg_offset[GC_HWIP][0][mmRLC_SPARE_INT_BASE_IDX] + mmRLC_SPARE_INT)*4;
1363
1364         grbm_cntl = adev->reg_offset[GC_HWIP][0][mmGRBM_GFX_CNTL_BASE_IDX] + mmGRBM_GFX_CNTL;
1365         grbm_idx = adev->reg_offset[GC_HWIP][0][mmGRBM_GFX_INDEX_BASE_IDX] + mmGRBM_GFX_INDEX;
1366
1367         if (amdgpu_sriov_runtime(adev)) {
1368                 pr_err("shouldn't call rlcg write register during runtime\n");
1369                 return;
1370         }
1371
1372         writel(v, scratch_reg0);
1373         writel(offset | 0x80000000, scratch_reg1);
1374         writel(1, spare_int);
1375         for (i = 0; i < retries; i++) {
1376                 u32 tmp;
1377
1378                 tmp = readl(scratch_reg1);
1379                 if (!(tmp & 0x80000000))
1380                         break;
1381
1382                 udelay(10);
1383         }
1384
1385         if (i >= retries)
1386                 pr_err("timeout: rlcg program reg:0x%05x failed !\n", offset);
1387 }
1388
1389 static const struct soc15_reg_golden golden_settings_gc_10_1_nv14[] =
1390 {
1391         /* Pending on emulation bring up */
1392 };
1393
1394 static const struct soc15_reg_golden golden_settings_gc_rlc_spm_10_1_nv14[] =
1395 {
1396         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xE0000000L, 0x0),
1397         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1398         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
1399         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1400         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1401         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1402         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
1403         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1404         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
1405         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1406         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
1407         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1408         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
1409         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1410         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
1411         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1412         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1413         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1414         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
1415         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1416         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1417         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1418         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
1419         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1420         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1421         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1422         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
1423         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1424         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1425         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1426         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
1427         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1428         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1429         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1430         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
1431         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1432         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1433         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1434         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
1435         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1436         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1437         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1438         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
1439         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1440         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1441         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1442         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
1443         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1444         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1445         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1446         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
1447         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1448         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20),
1449         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1450         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
1451         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1452         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
1453         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1454         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
1455         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1456         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1457         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1458         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
1459         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1460         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1461         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1462         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
1463         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1464         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1465         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1466         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
1467         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1468         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1469         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1470         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
1471         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1472         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1473         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1474         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
1475         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1476         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
1477         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1478         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
1479         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1480         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1481         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1482         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
1483         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1484         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1485         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1486         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
1487         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1488         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1489         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1490         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
1491         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1492         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1493         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1494         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
1495         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1496         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
1497         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1498         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
1499         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1500         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
1501         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1502         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
1503         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1504         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
1505         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1506         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
1507         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1508         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
1509         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1510         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
1511         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1512         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
1513         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1514         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
1515         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1516         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
1517         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1518         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
1519         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1520         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
1521         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1522         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
1523         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1524         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
1525         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1526         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
1527         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1528         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
1529         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1530         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
1531         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1532         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
1533         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1534         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c),
1535         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1536         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1537         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1538         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
1539         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1540         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1541         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1542         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
1543         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1544         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1545         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1546         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
1547         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1548         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1549         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1550         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
1551         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1552         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1553         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1554         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
1555         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1556         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
1557         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1558         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
1559         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1560         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1561         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1562         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
1563         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1564         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1565         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1566         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
1567         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1568         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
1569         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1570         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
1571         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1572         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
1573         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1574         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
1575         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1576         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
1577         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1578         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
1579         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1580         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e),
1581         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1582         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
1583         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1584         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e),
1585         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1586         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
1587         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1588         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e),
1589         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1590         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
1591         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1592         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e),
1593         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1594         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
1595         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1596         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20),
1597         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1598         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
1599         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1600         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
1601         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1602         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
1603         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1604         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
1605         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1606         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
1607         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1608         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e),
1609         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1610         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
1611         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1612         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e),
1613         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1614         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
1615         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1616         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
1617         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1618         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
1619         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1620         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1621         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1622         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
1623         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1624         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1625         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1626         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
1627         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1628         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1629         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1630         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
1631         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1632         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1633         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1634         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
1635         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1636         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1637         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1638         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
1639         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1640         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1641         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1642         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
1643         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1644         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1645         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1646         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
1647         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1648         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1649         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1650         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
1651         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1652         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1653         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1654         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
1655         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1656         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1657         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1658         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
1659         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1660         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1661         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1662         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
1663         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1664         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1665         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1666         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90),
1667         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1668         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1669         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1670         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94),
1671         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1672         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
1673         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1674         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0),
1675         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1676         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1677         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1678         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4),
1679         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1680         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1681         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1682         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98),
1683         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1684         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1685         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1686         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c),
1687         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1688         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
1689         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1690         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8),
1691         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1692         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
1693         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1694         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac),
1695         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1696         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1697         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1698         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8),
1699         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1700         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1701         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1702         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc),
1703         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1704         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1705         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1706         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0),
1707         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1708         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
1709         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1710         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4),
1711         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1712         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1713         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1714         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0),
1715         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1716         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1717         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1718         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4),
1719         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1720         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1721         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1722         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0),
1723         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1724         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1725         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1726         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4),
1727         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1728         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1729         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1730         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8),
1731         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1732         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1733         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1734         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc),
1735         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1736         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1737         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1738         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8),
1739         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1740         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1741         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1742         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc),
1743         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1744         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1745         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1746         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8),
1747         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1748         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1749         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1750         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec),
1751         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1752         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1753         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1754         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0),
1755         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1756         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1757         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1758         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe4),
1759         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1760         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1761         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1762         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100),
1763         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1764         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1765         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1766         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104),
1767         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1768         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1769         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1770         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108),
1771         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1772         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1773         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1774         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c),
1775         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1776         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1777         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1778         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110),
1779         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1780         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1781         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1782         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114),
1783         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1784         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1785         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1786         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118),
1787         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1788         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1789         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1790         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c),
1791         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1792         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1793         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1794         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8),
1795         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1796         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17),
1797         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1798         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130),
1799         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1800         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1801         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1802         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134),
1803         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1804         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1805         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1806         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138),
1807         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1808         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1809         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1810         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c),
1811         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1812         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1813         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1814         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4),
1815         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1816         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20),
1817         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1818         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128),
1819         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1820         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1821         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1822         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c),
1823         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1824         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1825         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1826         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120),
1827         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1828         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1829         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1830         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124),
1831         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1832         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1833         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1834         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0),
1835         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1836         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
1837         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1838         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140),
1839         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1840         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1841         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1842         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144),
1843         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1844         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1845         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1846         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150),
1847         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1848         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1849         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1850         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154),
1851         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1852         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1853         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1854         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148),
1855         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1856         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1857         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1858         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c),
1859         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1860         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1861         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1862         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158),
1863         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1864         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1865         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1866         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c),
1867         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1868         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
1869         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1870         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168),
1871         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1872         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1873         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1874         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c),
1875         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1876         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1877         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1878         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160),
1879         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1880         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1881         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1882         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164),
1883         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1884         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
1885         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1886         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170),
1887         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1888         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
1889         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1890         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174),
1891         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1892         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
1893         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1894         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180),
1895         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1896         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1897         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1898         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184),
1899         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1900         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
1901         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1902         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178),
1903         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1904         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
1905         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1906         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c),
1907         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1908         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
1909         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1910         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188),
1911         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1912         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1913         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1914         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c),
1915         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1916         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1917         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1918         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198),
1919         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1920         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1921         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1922         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c),
1923         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1924         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1925         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1926         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190),
1927         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1928         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1929         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1930         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194),
1931         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1932         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1933         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1934         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1a0),
1935         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1936         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1937         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1938         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1a4),
1939         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1940         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1941         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1942         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1b0),
1943         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1944         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1945         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1946         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1b4),
1947         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1948         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1949         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1950         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1a8),
1951         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1952         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1953         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1954         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1ac),
1955         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1956         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1957         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1958         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1b8),
1959         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1960         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1961         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1962         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1bc),
1963         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1964         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
1965         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1966         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c8),
1967         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1968         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1969         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1970         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1cc),
1971         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1972         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1973         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1974         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c0),
1975         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1976         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1977         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1978         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c4),
1979         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1980         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
1981         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1982         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
1983         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1984         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1985         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1986         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
1987         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1988         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1989         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1990         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
1991         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1992         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20),
1993         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1994         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
1995         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1996         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20),
1997         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1998         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
1999         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2000         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
2001         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2002         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_SAMPLE_SKEW, 0x000000FF, 0x26),
2003         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2004         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_MUXSEL_SKEW, 0x000000FF, 0x28),
2005         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2006         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0xf),
2007         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2008         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0x15),
2009         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2010         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x1f),
2011         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2012         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x25),
2013         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2014         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_DESER_START_SKEW, 0x000000FF, 0x3b),
2015         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xFFFFFFFF, 0xe0000000)
2016 };
2017
2018 static const struct soc15_reg_golden golden_settings_gc_10_1_2_nv12[] =
2019 {
2020         /* Pending on emulation bring up */
2021 };
2022
2023 static const struct soc15_reg_golden golden_settings_gc_rlc_spm_10_1_2_nv12[] =
2024 {
2025         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xe0000000L, 0x0),
2026         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2027         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
2028         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2029         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
2030         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2031         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
2032         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2033         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
2034         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2035         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
2036         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2037         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
2038         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2039         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
2040         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2041         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
2042         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2043         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8),
2044         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2045         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2046         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2047         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc),
2048         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2049         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2050         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2051         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0),
2052         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2053         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2054         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2055         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4),
2056         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2057         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2058         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2059         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
2060         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2061         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2062         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2063         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
2064         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2065         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2066         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2067         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
2068         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2069         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2070         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2071         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
2072         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2073         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2074         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2075         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
2076         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2077         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2078         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2079         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
2080         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2081         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2082         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2083         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
2084         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2085         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2086         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2087         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
2088         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2089         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
2090         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2091         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
2092         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2093         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
2094         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2095         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0),
2096         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2097         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
2098         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2099         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4),
2100         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2101         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
2102         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2103         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8),
2104         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2105         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2106         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2107         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc),
2108         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2109         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2110         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2111         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0),
2112         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2113         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2114         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2115         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4),
2116         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2117         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2118         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2119         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90),
2120         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2121         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
2122         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2123         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94),
2124         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2125         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1),
2126         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2127         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98),
2128         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2129         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
2130         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2131         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c),
2132         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2133         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2134         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2135         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0),
2136         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2137         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1),
2138         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2139         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4),
2140         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2141         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2142         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2143         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8),
2144         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2145         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2146         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2147         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac),
2148         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2149         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2150         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2151         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
2152         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2153         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
2154         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2155         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
2156         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2157         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2158         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2159         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
2160         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2161         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
2162         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2163         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
2164         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2165         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2166         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2167         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
2168         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2169         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2170         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2171         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
2172         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2173         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2174         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2175         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
2176         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2177         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
2178         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2179         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
2180         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2181         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2182         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2183         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
2184         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2185         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2186         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2187         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
2188         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2189         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
2190         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2191         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
2192         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2193         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2194         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2195         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
2196         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2197         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
2198         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2199         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
2200         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2201         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
2202         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2203         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
2204         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2205         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2206         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2207         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
2208         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2209         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2210         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2211         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
2212         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2213         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2214         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2215         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
2216         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2217         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
2218         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2219         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
2220         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2221         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2222         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2223         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
2224         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2225         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2226         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2227         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
2228         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2229         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2230         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2231         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
2232         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2233         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2234         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2235         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
2236         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2237         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2238         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2239         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
2240         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2241         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
2242         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2243         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c),
2244         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2245         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
2246         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2247         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
2248         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2249         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2250         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2251         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
2252         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2253         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
2254         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2255         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
2256         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2257         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
2258         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2259         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
2260         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2261         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2262         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2263         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
2264         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2265         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2266         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2267         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
2268         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2269         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2270         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2271         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
2272         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2273         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2274         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2275         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
2276         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2277         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2278         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2279         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
2280         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2281         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2282         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2283         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
2284         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2285         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
2286         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2287         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
2288         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2289         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
2290         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2291         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
2292         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2293         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2294         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2295         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
2296         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2297         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2298         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2299         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
2300         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2301         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
2302         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2303         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
2304         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2305         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
2306         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2307         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
2308         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2309         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2310         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2311         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
2312         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2313         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2314         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2315         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
2316         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2317         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
2318         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2319         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
2320         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2321         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
2322         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2323         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
2324         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2325         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2326         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2327         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
2328         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2329         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2330         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2331         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
2332         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2333         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2334         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2335         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
2336         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2337         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2338         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2339         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
2340         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2341         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2342         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2343         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
2344         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2345         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2346         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2347         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
2348         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2349         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2350         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2351         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
2352         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2353         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2354         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2355         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
2356         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2357         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2358         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2359         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
2360         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2361         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2362         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2363         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
2364         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2365         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2366         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2367         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
2368         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2369         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2370         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2371         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
2372         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2373         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2374         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2375         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
2376         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2377         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2378         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2379         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
2380         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2381         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2382         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2383         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
2384         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2385         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2386         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2387         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
2388         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2389         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2390         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2391         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
2392         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2393         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2394         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2395         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
2396         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2397         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
2398         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2399         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
2400         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2401         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
2402         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2403         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
2404         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2405         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2406         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2407         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
2408         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2409         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2410         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2411         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
2412         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2413         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
2414         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2415         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
2416         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2417         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
2418         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2419         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
2420         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2421         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
2422         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2423         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
2424         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2425         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
2426         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2427         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
2428         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2429         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2430         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2431         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
2432         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2433         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2434         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2435         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
2436         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2437         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2438         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2439         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
2440         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2441         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2442         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2443         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
2444         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2445         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
2446         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2447         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
2448         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2449         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
2450         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2451         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
2452         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2453         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2454         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2455         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
2456         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2457         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2458         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2459         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
2460         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2461         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2462         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2463         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
2464         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2465         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2466         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2467         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
2468         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2469         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2470         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2471         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
2472         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2473         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2474         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2475         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
2476         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2477         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2478         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2479         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
2480         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2481         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2482         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2483         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
2484         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2485         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2486         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2487         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
2488         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2489         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2490         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2491         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
2492         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2493         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2494         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2495         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
2496         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2497         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2498         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2499         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90),
2500         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2501         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
2502         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2503         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90),
2504         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2505         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
2506         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2507         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94),
2508         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2509         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2510         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2511         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94),
2512         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2513         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2514         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2515         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0),
2516         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2517         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2518         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2519         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0),
2520         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2521         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2522         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2523         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4),
2524         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2525         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2526         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2527         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4),
2528         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2529         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2530         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2531         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98),
2532         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2533         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
2534         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2535         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98),
2536         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2537         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
2538         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2539         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c),
2540         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2541         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2542         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2543         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c),
2544         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2545         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2546         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2547         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8),
2548         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2549         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2550         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2551         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8),
2552         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2553         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2554         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2555         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac),
2556         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2557         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2558         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2559         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac),
2560         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2561         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2562         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2563         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8),
2564         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2565         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2566         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2567         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8),
2568         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2569         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2570         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2571         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc),
2572         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2573         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2574         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2575         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc),
2576         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2577         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2578         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2579         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0),
2580         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2581         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2582         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2583         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0),
2584         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2585         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2586         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2587         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4),
2588         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2589         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2590         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2591         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4),
2592         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2593         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2594         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2595         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0),
2596         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2597         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2598         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2599         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0),
2600         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2601         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2602         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2603         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4),
2604         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2605         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2606         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2607         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4),
2608         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2609         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2610         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2611         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0),
2612         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2613         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2614         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2615         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0),
2616         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2617         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2618         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2619         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4),
2620         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2621         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2622         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2623         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4),
2624         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2625         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2626         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2627         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8),
2628         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2629         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2630         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2631         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8),
2632         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2633         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2634         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2635         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc),
2636         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2637         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2638         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2639         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc),
2640         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2641         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2642         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2643         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8),
2644         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2645         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2646         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2647         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8),
2648         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2649         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2650         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2651         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec),
2652         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2653         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
2654         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2655         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec),
2656         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2657         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
2658         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2659         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0),
2660         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2661         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2662         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2663         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0),
2664         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2665         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2666         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2667         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4),
2668         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2669         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2670         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2671         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4),
2672         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2673         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2674         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2675         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8),
2676         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2677         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2678         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2679         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8),
2680         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2681         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2682         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2683         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xfc),
2684         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2685         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17),
2686         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2687         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xfc),
2688         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2689         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17),
2690         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2691         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100),
2692         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2693         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
2694         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2695         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100),
2696         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2697         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
2698         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2699         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104),
2700         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2701         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2702         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2703         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104),
2704         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2705         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2706         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2707         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0),
2708         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2709         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2710         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2711         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0),
2712         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2713         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2714         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2715         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118),
2716         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2717         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2718         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2719         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118),
2720         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2721         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2722         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2723         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c),
2724         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2725         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2726         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2727         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c),
2728         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2729         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2730         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2731         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120),
2732         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2733         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2734         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2735         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120),
2736         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2737         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2738         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2739         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124),
2740         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2741         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2742         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2743         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124),
2744         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2745         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2746         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2747         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc),
2748         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2749         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2750         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2751         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc),
2752         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2753         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2754         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2755         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110),
2756         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2757         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2758         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2759         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110),
2760         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2761         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2762         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2763         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114),
2764         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2765         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2766         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2767         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114),
2768         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2769         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2770         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2771         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108),
2772         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2773         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2774         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2775         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108),
2776         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2777         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2778         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2779         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c),
2780         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2781         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2782         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2783         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c),
2784         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2785         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2786         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2787         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8),
2788         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2789         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
2790         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2791         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8),
2792         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2793         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
2794         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2795         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128),
2796         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2797         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2798         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2799         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128),
2800         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2801         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2802         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2803         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c),
2804         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2805         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2806         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2807         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c),
2808         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2809         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2810         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2811         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138),
2812         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2813         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2814         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2815         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138),
2816         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2817         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2818         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2819         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c),
2820         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2821         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2822         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2823         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c),
2824         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2825         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2826         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2827         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130),
2828         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2829         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2830         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2831         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130),
2832         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2833         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2834         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2835         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134),
2836         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2837         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
2838         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2839         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134),
2840         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2841         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
2842         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2843         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140),
2844         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2845         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2846         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2847         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140),
2848         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2849         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2850         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2851         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144),
2852         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2853         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2854         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2855         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144),
2856         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2857         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2858         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2859         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150),
2860         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2861         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2862         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2863         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150),
2864         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2865         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2866         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2867         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154),
2868         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2869         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2870         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2871         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154),
2872         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2873         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2874         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2875         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148),
2876         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2877         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2878         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2879         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148),
2880         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2881         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2882         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2883         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c),
2884         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2885         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2886         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2887         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c),
2888         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2889         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2890         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2891         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158),
2892         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2893         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
2894         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2895         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158),
2896         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2897         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
2898         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2899         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c),
2900         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2901         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
2902         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2903         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c),
2904         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2905         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
2906         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2907         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168),
2908         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2909         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
2910         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2911         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168),
2912         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2913         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
2914         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2915         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c),
2916         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2917         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
2918         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2919         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c),
2920         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2921         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
2922         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2923         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160),
2924         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2925         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
2926         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2927         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160),
2928         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2929         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
2930         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2931         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164),
2932         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2933         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
2934         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2935         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164),
2936         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2937         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
2938         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2939         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170),
2940         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2941         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2942         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2943         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170),
2944         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2945         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2946         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2947         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174),
2948         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2949         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2950         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2951         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174),
2952         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2953         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2954         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2955         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180),
2956         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2957         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2958         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2959         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180),
2960         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2961         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2962         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2963         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184),
2964         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2965         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2966         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2967         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184),
2968         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2969         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2970         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2971         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178),
2972         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2973         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2974         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2975         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178),
2976         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2977         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2978         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2979         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c),
2980         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2981         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2982         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2983         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c),
2984         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2985         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2986         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2987         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188),
2988         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2989         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2990         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2991         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188),
2992         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2993         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2994         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2995         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c),
2996         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2997         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
2998         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2999         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c),
3000         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3001         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
3002         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3003         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198),
3004         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3005         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
3006         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3007         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198),
3008         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3009         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
3010         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3011         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c),
3012         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3013         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
3014         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3015         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c),
3016         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3017         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
3018         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3019         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190),
3020         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3021         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3022         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3023         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190),
3024         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3025         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3026         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3027         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194),
3028         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3029         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
3030         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3031         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194),
3032         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3033         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
3034         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3035         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
3036         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3037         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
3038         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3039         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
3040         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3041         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
3042         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3043         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
3044         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3045         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
3046         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3047         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
3048         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3049         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
3050         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3051         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
3052         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3053         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1f),
3054         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3055         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
3056         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3057         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1f),
3058         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3059         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
3060         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3061         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
3062         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3063         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_SAMPLE_SKEW, 0x000000FF, 0x1f),
3064         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3065         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_MUXSEL_SKEW, 0x000000FF, 0x22),
3066         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3067         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0x1),
3068         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3069         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0x6),
3070         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3071         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x10),
3072         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3073         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x15),
3074         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3075         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_DESER_START_SKEW, 0x000000FF, 0x35),
3076         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xFFFFFFFF, 0xe0000000)
3077 };
3078
3079 static const struct soc15_reg_golden golden_settings_gc_10_3[] =
3080 {
3081         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_PS_CLK_CTRL, 0xff7f0fff, 0x78000100),
3082         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA0_CLK_CTRL, 0xff7f0fff, 0x30000100),
3083         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA1_CLK_CTRL, 0xff7f0fff, 0x7e000100),
3084         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c000),
3085         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000280),
3086         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000),
3087         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_EXCEPTION_CONTROL, 0x7fff0f1f, 0x00b80000),
3088         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Sienna_Cichlid, 0x1ff1ffff, 0x00000500),
3089         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PC_CNTL, 0x003fffff, 0x00280400),
3090         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
3091         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
3092         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008),
3093         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x10f80988),
3094         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007),
3095         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
3096         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0xffffffbf, 0x00000820),
3097         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0xffffffff, 0x00070104),
3098         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_CONFIG, 0xe07df47f, 0x00180070),
3099         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER0_SELECT, 0xf0f001ff, 0x00000000),
3100         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER1_SELECT, 0xf0f001ff, 0x00000000),
3101         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER10_SELECT, 0xf0f001ff, 0x00000000),
3102         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER11_SELECT, 0xf0f001ff, 0x00000000),
3103         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER12_SELECT, 0xf0f001ff, 0x00000000),
3104         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER13_SELECT, 0xf0f001ff, 0x00000000),
3105         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER14_SELECT, 0xf0f001ff, 0x00000000),
3106         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER15_SELECT, 0xf0f001ff, 0x00000000),
3107         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER2_SELECT, 0xf0f001ff, 0x00000000),
3108         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER3_SELECT, 0xf0f001ff, 0x00000000),
3109         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER4_SELECT, 0xf0f001ff, 0x00000000),
3110         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER5_SELECT, 0xf0f001ff, 0x00000000),
3111         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER6_SELECT, 0xf0f001ff, 0x00000000),
3112         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER7_SELECT, 0xf0f001ff, 0x00000000),
3113         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER8_SELECT, 0xf0f001ff, 0x00000000),
3114         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER9_SELECT, 0xf0f001ff, 0x00000000),
3115         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
3116         SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffbfffff, 0x00a00000)
3117 };
3118
3119 static const struct soc15_reg_golden golden_settings_gc_10_3_sienna_cichlid[] =
3120 {
3121         /* Pending on emulation bring up */
3122 };
3123
3124 static const struct soc15_reg_golden golden_settings_gc_10_3_2[] =
3125 {
3126         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_PS_CLK_CTRL, 0xff7f0fff, 0x78000100),
3127         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA0_CLK_CTRL, 0xff7f0fff, 0x30000100),
3128         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA1_CLK_CTRL, 0xff7f0fff, 0x7e000100),
3129         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c000),
3130         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000280),
3131         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000),
3132         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_EXCEPTION_CONTROL, 0x7fff0f1f, 0x00b80000),
3133         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Sienna_Cichlid, 0x1ff1ffff, 0x00000500),
3134         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PC_CNTL, 0x003fffff, 0x00280400),
3135         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
3136         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
3137         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008),
3138         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x00f80988),
3139         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007),
3140         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
3141         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0xffffffbf, 0x00000820),
3142         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0xffffffff, 0x00070104),
3143         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_START_PHASE, 0x000000ff, 0x00000004),
3144         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_CONFIG, 0xe07df47f, 0x00180070),
3145         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER0_SELECT, 0xf0f001ff, 0x00000000),
3146         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER1_SELECT, 0xf0f001ff, 0x00000000),
3147         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER10_SELECT, 0xf0f001ff, 0x00000000),
3148         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER11_SELECT, 0xf0f001ff, 0x00000000),
3149         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER12_SELECT, 0xf0f001ff, 0x00000000),
3150         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER13_SELECT, 0xf0f001ff, 0x00000000),
3151         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER14_SELECT, 0xf0f001ff, 0x00000000),
3152         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER15_SELECT, 0xf0f001ff, 0x00000000),
3153         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER2_SELECT, 0xf0f001ff, 0x00000000),
3154         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER3_SELECT, 0xf0f001ff, 0x00000000),
3155         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER4_SELECT, 0xf0f001ff, 0x00000000),
3156         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER5_SELECT, 0xf0f001ff, 0x00000000),
3157         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER6_SELECT, 0xf0f001ff, 0x00000000),
3158         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER7_SELECT, 0xf0f001ff, 0x00000000),
3159         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER8_SELECT, 0xf0f001ff, 0x00000000),
3160         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER9_SELECT, 0xf0f001ff, 0x00000000),
3161         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
3162         SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffbfffff, 0x00a00000),
3163         SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_GS_MAX_WAVE_ID, 0x00000fff, 0x000003ff)
3164 };
3165
3166 #define DEFAULT_SH_MEM_CONFIG \
3167         ((SH_MEM_ADDRESS_MODE_64 << SH_MEM_CONFIG__ADDRESS_MODE__SHIFT) | \
3168          (SH_MEM_ALIGNMENT_MODE_UNALIGNED << SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT) | \
3169          (SH_MEM_RETRY_MODE_ALL << SH_MEM_CONFIG__RETRY_MODE__SHIFT) | \
3170          (3 << SH_MEM_CONFIG__INITIAL_INST_PREFETCH__SHIFT))
3171
3172
3173 static void gfx_v10_0_set_ring_funcs(struct amdgpu_device *adev);
3174 static void gfx_v10_0_set_irq_funcs(struct amdgpu_device *adev);
3175 static void gfx_v10_0_set_gds_init(struct amdgpu_device *adev);
3176 static void gfx_v10_0_set_rlc_funcs(struct amdgpu_device *adev);
3177 static int gfx_v10_0_get_cu_info(struct amdgpu_device *adev,
3178                                  struct amdgpu_cu_info *cu_info);
3179 static uint64_t gfx_v10_0_get_gpu_clock_counter(struct amdgpu_device *adev);
3180 static void gfx_v10_0_select_se_sh(struct amdgpu_device *adev, u32 se_num,
3181                                    u32 sh_num, u32 instance);
3182 static u32 gfx_v10_0_get_wgp_active_bitmap_per_sh(struct amdgpu_device *adev);
3183
3184 static int gfx_v10_0_rlc_backdoor_autoload_buffer_init(struct amdgpu_device *adev);
3185 static void gfx_v10_0_rlc_backdoor_autoload_buffer_fini(struct amdgpu_device *adev);
3186 static int gfx_v10_0_rlc_backdoor_autoload_enable(struct amdgpu_device *adev);
3187 static int gfx_v10_0_wait_for_rlc_autoload_complete(struct amdgpu_device *adev);
3188 static void gfx_v10_0_ring_emit_ce_meta(struct amdgpu_ring *ring, bool resume);
3189 static void gfx_v10_0_ring_emit_de_meta(struct amdgpu_ring *ring, bool resume);
3190 static void gfx_v10_0_ring_emit_frame_cntl(struct amdgpu_ring *ring, bool start, bool secure);
3191
3192 static void gfx10_kiq_set_resources(struct amdgpu_ring *kiq_ring, uint64_t queue_mask)
3193 {
3194         amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_RESOURCES, 6));
3195         amdgpu_ring_write(kiq_ring, PACKET3_SET_RESOURCES_VMID_MASK(0) |
3196                           PACKET3_SET_RESOURCES_QUEUE_TYPE(0)); /* vmid_mask:0 queue_type:0 (KIQ) */
3197         amdgpu_ring_write(kiq_ring, lower_32_bits(queue_mask)); /* queue mask lo */
3198         amdgpu_ring_write(kiq_ring, upper_32_bits(queue_mask)); /* queue mask hi */
3199         amdgpu_ring_write(kiq_ring, 0); /* gws mask lo */
3200         amdgpu_ring_write(kiq_ring, 0); /* gws mask hi */
3201         amdgpu_ring_write(kiq_ring, 0); /* oac mask */
3202         amdgpu_ring_write(kiq_ring, 0); /* gds heap base:0, gds heap size:0 */
3203 }
3204
3205 static void gfx10_kiq_map_queues(struct amdgpu_ring *kiq_ring,
3206                                  struct amdgpu_ring *ring)
3207 {
3208         struct amdgpu_device *adev = kiq_ring->adev;
3209         uint64_t mqd_addr = amdgpu_bo_gpu_offset(ring->mqd_obj);
3210         uint64_t wptr_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
3211         uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0;
3212
3213         amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5));
3214         /* Q_sel:0, vmid:0, vidmem: 1, engine:0, num_Q:1*/
3215         amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */
3216                           PACKET3_MAP_QUEUES_QUEUE_SEL(0) | /* Queue_Sel */
3217                           PACKET3_MAP_QUEUES_VMID(0) | /* VMID */
3218                           PACKET3_MAP_QUEUES_QUEUE(ring->queue) |
3219                           PACKET3_MAP_QUEUES_PIPE(ring->pipe) |
3220                           PACKET3_MAP_QUEUES_ME((ring->me == 1 ? 0 : 1)) |
3221                           PACKET3_MAP_QUEUES_QUEUE_TYPE(0) | /*queue_type: normal compute queue */
3222                           PACKET3_MAP_QUEUES_ALLOC_FORMAT(0) | /* alloc format: all_on_one_pipe */
3223                           PACKET3_MAP_QUEUES_ENGINE_SEL(eng_sel) |
3224                           PACKET3_MAP_QUEUES_NUM_QUEUES(1)); /* num_queues: must be 1 */
3225         amdgpu_ring_write(kiq_ring, PACKET3_MAP_QUEUES_DOORBELL_OFFSET(ring->doorbell_index));
3226         amdgpu_ring_write(kiq_ring, lower_32_bits(mqd_addr));
3227         amdgpu_ring_write(kiq_ring, upper_32_bits(mqd_addr));
3228         amdgpu_ring_write(kiq_ring, lower_32_bits(wptr_addr));
3229         amdgpu_ring_write(kiq_ring, upper_32_bits(wptr_addr));
3230 }
3231
3232 static void gfx10_kiq_unmap_queues(struct amdgpu_ring *kiq_ring,
3233                                    struct amdgpu_ring *ring,
3234                                    enum amdgpu_unmap_queues_action action,
3235                                    u64 gpu_addr, u64 seq)
3236 {
3237         uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0;
3238
3239         amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_UNMAP_QUEUES, 4));
3240         amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */
3241                           PACKET3_UNMAP_QUEUES_ACTION(action) |
3242                           PACKET3_UNMAP_QUEUES_QUEUE_SEL(0) |
3243                           PACKET3_UNMAP_QUEUES_ENGINE_SEL(eng_sel) |
3244                           PACKET3_UNMAP_QUEUES_NUM_QUEUES(1));
3245         amdgpu_ring_write(kiq_ring,
3246                   PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET0(ring->doorbell_index));
3247
3248         if (action == PREEMPT_QUEUES_NO_UNMAP) {
3249                 amdgpu_ring_write(kiq_ring, lower_32_bits(gpu_addr));
3250                 amdgpu_ring_write(kiq_ring, upper_32_bits(gpu_addr));
3251                 amdgpu_ring_write(kiq_ring, seq);
3252         } else {
3253                 amdgpu_ring_write(kiq_ring, 0);
3254                 amdgpu_ring_write(kiq_ring, 0);
3255                 amdgpu_ring_write(kiq_ring, 0);
3256         }
3257 }
3258
3259 static void gfx10_kiq_query_status(struct amdgpu_ring *kiq_ring,
3260                                    struct amdgpu_ring *ring,
3261                                    u64 addr,
3262                                    u64 seq)
3263 {
3264         uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0;
3265
3266         amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_QUERY_STATUS, 5));
3267         amdgpu_ring_write(kiq_ring,
3268                           PACKET3_QUERY_STATUS_CONTEXT_ID(0) |
3269                           PACKET3_QUERY_STATUS_INTERRUPT_SEL(0) |
3270                           PACKET3_QUERY_STATUS_COMMAND(2));
3271         amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */
3272                           PACKET3_QUERY_STATUS_DOORBELL_OFFSET(ring->doorbell_index) |
3273                           PACKET3_QUERY_STATUS_ENG_SEL(eng_sel));
3274         amdgpu_ring_write(kiq_ring, lower_32_bits(addr));
3275         amdgpu_ring_write(kiq_ring, upper_32_bits(addr));
3276         amdgpu_ring_write(kiq_ring, lower_32_bits(seq));
3277         amdgpu_ring_write(kiq_ring, upper_32_bits(seq));
3278 }
3279
3280 static void gfx10_kiq_invalidate_tlbs(struct amdgpu_ring *kiq_ring,
3281                                 uint16_t pasid, uint32_t flush_type,
3282                                 bool all_hub)
3283 {
3284         amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_INVALIDATE_TLBS, 0));
3285         amdgpu_ring_write(kiq_ring,
3286                         PACKET3_INVALIDATE_TLBS_DST_SEL(1) |
3287                         PACKET3_INVALIDATE_TLBS_ALL_HUB(all_hub) |
3288                         PACKET3_INVALIDATE_TLBS_PASID(pasid) |
3289                         PACKET3_INVALIDATE_TLBS_FLUSH_TYPE(flush_type));
3290 }
3291
3292 static const struct kiq_pm4_funcs gfx_v10_0_kiq_pm4_funcs = {
3293         .kiq_set_resources = gfx10_kiq_set_resources,
3294         .kiq_map_queues = gfx10_kiq_map_queues,
3295         .kiq_unmap_queues = gfx10_kiq_unmap_queues,
3296         .kiq_query_status = gfx10_kiq_query_status,
3297         .kiq_invalidate_tlbs = gfx10_kiq_invalidate_tlbs,
3298         .set_resources_size = 8,
3299         .map_queues_size = 7,
3300         .unmap_queues_size = 6,
3301         .query_status_size = 7,
3302         .invalidate_tlbs_size = 2,
3303 };
3304
3305 static void gfx_v10_0_set_kiq_pm4_funcs(struct amdgpu_device *adev)
3306 {
3307         adev->gfx.kiq.pmf = &gfx_v10_0_kiq_pm4_funcs;
3308 }
3309
3310 static void gfx_v10_0_init_golden_registers(struct amdgpu_device *adev)
3311 {
3312         switch (adev->asic_type) {
3313         case CHIP_NAVI10:
3314                 soc15_program_register_sequence(adev,
3315                                                 golden_settings_gc_10_1,
3316                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_1));
3317                 soc15_program_register_sequence(adev,
3318                                                 golden_settings_gc_10_0_nv10,
3319                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_0_nv10));
3320                 soc15_program_register_sequence(adev,
3321                                                 golden_settings_gc_rlc_spm_10_0_nv10,
3322                                                 (const u32)ARRAY_SIZE(golden_settings_gc_rlc_spm_10_0_nv10));
3323                 break;
3324         case CHIP_NAVI14:
3325                 soc15_program_register_sequence(adev,
3326                                                 golden_settings_gc_10_1_1,
3327                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_1_1));
3328                 soc15_program_register_sequence(adev,
3329                                                 golden_settings_gc_10_1_nv14,
3330                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_1_nv14));
3331                 soc15_program_register_sequence(adev,
3332                                                 golden_settings_gc_rlc_spm_10_1_nv14,
3333                                                 (const u32)ARRAY_SIZE(golden_settings_gc_rlc_spm_10_1_nv14));
3334                 break;
3335         case CHIP_NAVI12:
3336                 soc15_program_register_sequence(adev,
3337                                                 golden_settings_gc_10_1_2,
3338                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_1_2));
3339                 soc15_program_register_sequence(adev,
3340                                                 golden_settings_gc_10_1_2_nv12,
3341                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_1_2_nv12));
3342                 soc15_program_register_sequence(adev,
3343                                                 golden_settings_gc_rlc_spm_10_1_2_nv12,
3344                                                 (const u32)ARRAY_SIZE(golden_settings_gc_rlc_spm_10_1_2_nv12));
3345                 break;
3346         case CHIP_SIENNA_CICHLID:
3347                 soc15_program_register_sequence(adev,
3348                                                 golden_settings_gc_10_3,
3349                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_3));
3350                 soc15_program_register_sequence(adev,
3351                                                 golden_settings_gc_10_3_sienna_cichlid,
3352                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_sienna_cichlid));
3353                 break;
3354         case CHIP_NAVY_FLOUNDER:
3355                 soc15_program_register_sequence(adev,
3356                                                 golden_settings_gc_10_3_2,
3357                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_2));
3358                 break;
3359
3360         default:
3361                 break;
3362         }
3363 }
3364
3365 static void gfx_v10_0_scratch_init(struct amdgpu_device *adev)
3366 {
3367         adev->gfx.scratch.num_reg = 8;
3368         adev->gfx.scratch.reg_base = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG0);
3369         adev->gfx.scratch.free_mask = (1u << adev->gfx.scratch.num_reg) - 1;
3370 }
3371
3372 static void gfx_v10_0_write_data_to_reg(struct amdgpu_ring *ring, int eng_sel,
3373                                        bool wc, uint32_t reg, uint32_t val)
3374 {
3375         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
3376         amdgpu_ring_write(ring, WRITE_DATA_ENGINE_SEL(eng_sel) |
3377                           WRITE_DATA_DST_SEL(0) | (wc ? WR_CONFIRM : 0));
3378         amdgpu_ring_write(ring, reg);
3379         amdgpu_ring_write(ring, 0);
3380         amdgpu_ring_write(ring, val);
3381 }
3382
3383 static void gfx_v10_0_wait_reg_mem(struct amdgpu_ring *ring, int eng_sel,
3384                                   int mem_space, int opt, uint32_t addr0,
3385                                   uint32_t addr1, uint32_t ref, uint32_t mask,
3386                                   uint32_t inv)
3387 {
3388         amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
3389         amdgpu_ring_write(ring,
3390                           /* memory (1) or register (0) */
3391                           (WAIT_REG_MEM_MEM_SPACE(mem_space) |
3392                            WAIT_REG_MEM_OPERATION(opt) | /* wait */
3393                            WAIT_REG_MEM_FUNCTION(3) |  /* equal */
3394                            WAIT_REG_MEM_ENGINE(eng_sel)));
3395
3396         if (mem_space)
3397                 BUG_ON(addr0 & 0x3); /* Dword align */
3398         amdgpu_ring_write(ring, addr0);
3399         amdgpu_ring_write(ring, addr1);
3400         amdgpu_ring_write(ring, ref);
3401         amdgpu_ring_write(ring, mask);
3402         amdgpu_ring_write(ring, inv); /* poll interval */
3403 }
3404
3405 static int gfx_v10_0_ring_test_ring(struct amdgpu_ring *ring)
3406 {
3407         struct amdgpu_device *adev = ring->adev;
3408         uint32_t scratch;
3409         uint32_t tmp = 0;
3410         unsigned i;
3411         int r;
3412
3413         r = amdgpu_gfx_scratch_get(adev, &scratch);
3414         if (r) {
3415                 DRM_ERROR("amdgpu: cp failed to get scratch reg (%d).\n", r);
3416                 return r;
3417         }
3418
3419         WREG32(scratch, 0xCAFEDEAD);
3420
3421         r = amdgpu_ring_alloc(ring, 3);
3422         if (r) {
3423                 DRM_ERROR("amdgpu: cp failed to lock ring %d (%d).\n",
3424                           ring->idx, r);
3425                 amdgpu_gfx_scratch_free(adev, scratch);
3426                 return r;
3427         }
3428
3429         amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1));
3430         amdgpu_ring_write(ring, (scratch - PACKET3_SET_UCONFIG_REG_START));
3431         amdgpu_ring_write(ring, 0xDEADBEEF);
3432         amdgpu_ring_commit(ring);
3433
3434         for (i = 0; i < adev->usec_timeout; i++) {
3435                 tmp = RREG32(scratch);
3436                 if (tmp == 0xDEADBEEF)
3437                         break;
3438                 if (amdgpu_emu_mode == 1)
3439                         msleep(1);
3440                 else
3441                         udelay(1);
3442         }
3443
3444         if (i >= adev->usec_timeout)
3445                 r = -ETIMEDOUT;
3446
3447         amdgpu_gfx_scratch_free(adev, scratch);
3448
3449         return r;
3450 }
3451
3452 static int gfx_v10_0_ring_test_ib(struct amdgpu_ring *ring, long timeout)
3453 {
3454         struct amdgpu_device *adev = ring->adev;
3455         struct amdgpu_ib ib;
3456         struct dma_fence *f = NULL;
3457         unsigned index;
3458         uint64_t gpu_addr;
3459         uint32_t tmp;
3460         long r;
3461
3462         r = amdgpu_device_wb_get(adev, &index);
3463         if (r)
3464                 return r;
3465
3466         gpu_addr = adev->wb.gpu_addr + (index * 4);
3467         adev->wb.wb[index] = cpu_to_le32(0xCAFEDEAD);
3468         memset(&ib, 0, sizeof(ib));
3469         r = amdgpu_ib_get(adev, NULL, 16,
3470                                         AMDGPU_IB_POOL_DIRECT, &ib);
3471         if (r)
3472                 goto err1;
3473
3474         ib.ptr[0] = PACKET3(PACKET3_WRITE_DATA, 3);
3475         ib.ptr[1] = WRITE_DATA_DST_SEL(5) | WR_CONFIRM;
3476         ib.ptr[2] = lower_32_bits(gpu_addr);
3477         ib.ptr[3] = upper_32_bits(gpu_addr);
3478         ib.ptr[4] = 0xDEADBEEF;
3479         ib.length_dw = 5;
3480
3481         r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
3482         if (r)
3483                 goto err2;
3484
3485         r = dma_fence_wait_timeout(f, false, timeout);
3486         if (r == 0) {
3487                 r = -ETIMEDOUT;
3488                 goto err2;
3489         } else if (r < 0) {
3490                 goto err2;
3491         }
3492
3493         tmp = adev->wb.wb[index];
3494         if (tmp == 0xDEADBEEF)
3495                 r = 0;
3496         else
3497                 r = -EINVAL;
3498 err2:
3499         amdgpu_ib_free(adev, &ib, NULL);
3500         dma_fence_put(f);
3501 err1:
3502         amdgpu_device_wb_free(adev, index);
3503         return r;
3504 }
3505
3506 static void gfx_v10_0_free_microcode(struct amdgpu_device *adev)
3507 {
3508         release_firmware(adev->gfx.pfp_fw);
3509         adev->gfx.pfp_fw = NULL;
3510         release_firmware(adev->gfx.me_fw);
3511         adev->gfx.me_fw = NULL;
3512         release_firmware(adev->gfx.ce_fw);
3513         adev->gfx.ce_fw = NULL;
3514         release_firmware(adev->gfx.rlc_fw);
3515         adev->gfx.rlc_fw = NULL;
3516         release_firmware(adev->gfx.mec_fw);
3517         adev->gfx.mec_fw = NULL;
3518         release_firmware(adev->gfx.mec2_fw);
3519         adev->gfx.mec2_fw = NULL;
3520
3521         kfree(adev->gfx.rlc.register_list_format);
3522 }
3523
3524 static void gfx_v10_0_check_fw_write_wait(struct amdgpu_device *adev)
3525 {
3526         adev->gfx.cp_fw_write_wait = false;
3527
3528         switch (adev->asic_type) {
3529         case CHIP_NAVI10:
3530         case CHIP_NAVI12:
3531         case CHIP_NAVI14:
3532                 if ((adev->gfx.me_fw_version >= 0x00000046) &&
3533                     (adev->gfx.me_feature_version >= 27) &&
3534                     (adev->gfx.pfp_fw_version >= 0x00000068) &&
3535                     (adev->gfx.pfp_feature_version >= 27) &&
3536                     (adev->gfx.mec_fw_version >= 0x0000005b) &&
3537                     (adev->gfx.mec_feature_version >= 27))
3538                         adev->gfx.cp_fw_write_wait = true;
3539                 break;
3540         case CHIP_SIENNA_CICHLID:
3541         case CHIP_NAVY_FLOUNDER:
3542                 adev->gfx.cp_fw_write_wait = true;
3543                 break;
3544         default:
3545                 break;
3546         }
3547
3548         if (adev->gfx.cp_fw_write_wait == false)
3549                 DRM_WARN_ONCE("CP firmware version too old, please update!");
3550 }
3551
3552
3553 static void gfx_v10_0_init_rlc_ext_microcode(struct amdgpu_device *adev)
3554 {
3555         const struct rlc_firmware_header_v2_1 *rlc_hdr;
3556
3557         rlc_hdr = (const struct rlc_firmware_header_v2_1 *)adev->gfx.rlc_fw->data;
3558         adev->gfx.rlc_srlc_fw_version = le32_to_cpu(rlc_hdr->save_restore_list_cntl_ucode_ver);
3559         adev->gfx.rlc_srlc_feature_version = le32_to_cpu(rlc_hdr->save_restore_list_cntl_feature_ver);
3560         adev->gfx.rlc.save_restore_list_cntl_size_bytes = le32_to_cpu(rlc_hdr->save_restore_list_cntl_size_bytes);
3561         adev->gfx.rlc.save_restore_list_cntl = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_list_cntl_offset_bytes);
3562         adev->gfx.rlc_srlg_fw_version = le32_to_cpu(rlc_hdr->save_restore_list_gpm_ucode_ver);
3563         adev->gfx.rlc_srlg_feature_version = le32_to_cpu(rlc_hdr->save_restore_list_gpm_feature_ver);
3564         adev->gfx.rlc.save_restore_list_gpm_size_bytes = le32_to_cpu(rlc_hdr->save_restore_list_gpm_size_bytes);
3565         adev->gfx.rlc.save_restore_list_gpm = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_list_gpm_offset_bytes);
3566         adev->gfx.rlc_srls_fw_version = le32_to_cpu(rlc_hdr->save_restore_list_srm_ucode_ver);
3567         adev->gfx.rlc_srls_feature_version = le32_to_cpu(rlc_hdr->save_restore_list_srm_feature_ver);
3568         adev->gfx.rlc.save_restore_list_srm_size_bytes = le32_to_cpu(rlc_hdr->save_restore_list_srm_size_bytes);
3569         adev->gfx.rlc.save_restore_list_srm = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_list_srm_offset_bytes);
3570         adev->gfx.rlc.reg_list_format_direct_reg_list_length =
3571                         le32_to_cpu(rlc_hdr->reg_list_format_direct_reg_list_length);
3572 }
3573
3574 static bool gfx_v10_0_navi10_gfxoff_should_enable(struct amdgpu_device *adev)
3575 {
3576         bool ret = false;
3577
3578         switch (adev->pdev->revision) {
3579         case 0xc2:
3580         case 0xc3:
3581                 ret = true;
3582                 break;
3583         default:
3584                 ret = false;
3585                 break;
3586         }
3587
3588         return ret ;
3589 }
3590
3591 static void gfx_v10_0_check_gfxoff_flag(struct amdgpu_device *adev)
3592 {
3593         switch (adev->asic_type) {
3594         case CHIP_NAVI10:
3595                 if (!gfx_v10_0_navi10_gfxoff_should_enable(adev))
3596                         adev->pm.pp_feature &= ~PP_GFXOFF_MASK;
3597                 break;
3598         default:
3599                 break;
3600         }
3601 }
3602
3603 static int gfx_v10_0_init_microcode(struct amdgpu_device *adev)
3604 {
3605         const char *chip_name;
3606         char fw_name[40];
3607         char wks[10];
3608         int err;
3609         struct amdgpu_firmware_info *info = NULL;
3610         const struct common_firmware_header *header = NULL;
3611         const struct gfx_firmware_header_v1_0 *cp_hdr;
3612         const struct rlc_firmware_header_v2_0 *rlc_hdr;
3613         unsigned int *tmp = NULL;
3614         unsigned int i = 0;
3615         uint16_t version_major;
3616         uint16_t version_minor;
3617
3618         DRM_DEBUG("\n");
3619
3620         memset(wks, 0, sizeof(wks));
3621         switch (adev->asic_type) {
3622         case CHIP_NAVI10:
3623                 chip_name = "navi10";
3624                 break;
3625         case CHIP_NAVI14:
3626                 chip_name = "navi14";
3627                 if (!(adev->pdev->device == 0x7340 &&
3628                       adev->pdev->revision != 0x00))
3629                         snprintf(wks, sizeof(wks), "_wks");
3630                 break;
3631         case CHIP_NAVI12:
3632                 chip_name = "navi12";
3633                 break;
3634         case CHIP_SIENNA_CICHLID:
3635                 chip_name = "sienna_cichlid";
3636                 break;
3637         case CHIP_NAVY_FLOUNDER:
3638                 chip_name = "navy_flounder";
3639                 break;
3640         default:
3641                 BUG();
3642         }
3643
3644         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_pfp%s.bin", chip_name, wks);
3645         err = request_firmware(&adev->gfx.pfp_fw, fw_name, adev->dev);
3646         if (err)
3647                 goto out;
3648         err = amdgpu_ucode_validate(adev->gfx.pfp_fw);
3649         if (err)
3650                 goto out;
3651         cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data;
3652         adev->gfx.pfp_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
3653         adev->gfx.pfp_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
3654
3655         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_me%s.bin", chip_name, wks);
3656         err = request_firmware(&adev->gfx.me_fw, fw_name, adev->dev);
3657         if (err)
3658                 goto out;
3659         err = amdgpu_ucode_validate(adev->gfx.me_fw);
3660         if (err)
3661                 goto out;
3662         cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data;
3663         adev->gfx.me_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
3664         adev->gfx.me_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
3665
3666         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ce%s.bin", chip_name, wks);
3667         err = request_firmware(&adev->gfx.ce_fw, fw_name, adev->dev);
3668         if (err)
3669                 goto out;
3670         err = amdgpu_ucode_validate(adev->gfx.ce_fw);
3671         if (err)
3672                 goto out;
3673         cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data;
3674         adev->gfx.ce_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
3675         adev->gfx.ce_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
3676
3677         if (!amdgpu_sriov_vf(adev)) {
3678                 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_rlc.bin", chip_name);
3679                 err = request_firmware(&adev->gfx.rlc_fw, fw_name, adev->dev);
3680                 if (err)
3681                         goto out;
3682                 err = amdgpu_ucode_validate(adev->gfx.rlc_fw);
3683                 rlc_hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data;
3684                 version_major = le16_to_cpu(rlc_hdr->header.header_version_major);
3685                 version_minor = le16_to_cpu(rlc_hdr->header.header_version_minor);
3686                 if (version_major == 2 && version_minor == 1)
3687                         adev->gfx.rlc.is_rlc_v2_1 = true;
3688
3689                 adev->gfx.rlc_fw_version = le32_to_cpu(rlc_hdr->header.ucode_version);
3690                 adev->gfx.rlc_feature_version = le32_to_cpu(rlc_hdr->ucode_feature_version);
3691                 adev->gfx.rlc.save_and_restore_offset =
3692                         le32_to_cpu(rlc_hdr->save_and_restore_offset);
3693                 adev->gfx.rlc.clear_state_descriptor_offset =
3694                         le32_to_cpu(rlc_hdr->clear_state_descriptor_offset);
3695                 adev->gfx.rlc.avail_scratch_ram_locations =
3696                         le32_to_cpu(rlc_hdr->avail_scratch_ram_locations);
3697                 adev->gfx.rlc.reg_restore_list_size =
3698                         le32_to_cpu(rlc_hdr->reg_restore_list_size);
3699                 adev->gfx.rlc.reg_list_format_start =
3700                         le32_to_cpu(rlc_hdr->reg_list_format_start);
3701                 adev->gfx.rlc.reg_list_format_separate_start =
3702                         le32_to_cpu(rlc_hdr->reg_list_format_separate_start);
3703                 adev->gfx.rlc.starting_offsets_start =
3704                         le32_to_cpu(rlc_hdr->starting_offsets_start);
3705                 adev->gfx.rlc.reg_list_format_size_bytes =
3706                         le32_to_cpu(rlc_hdr->reg_list_format_size_bytes);
3707                 adev->gfx.rlc.reg_list_size_bytes =
3708                         le32_to_cpu(rlc_hdr->reg_list_size_bytes);
3709                 adev->gfx.rlc.register_list_format =
3710                         kmalloc(adev->gfx.rlc.reg_list_format_size_bytes +
3711                                         adev->gfx.rlc.reg_list_size_bytes, GFP_KERNEL);
3712                 if (!adev->gfx.rlc.register_list_format) {
3713                         err = -ENOMEM;
3714                         goto out;
3715                 }
3716
3717                 tmp = (unsigned int *)((uintptr_t)rlc_hdr +
3718                                                            le32_to_cpu(rlc_hdr->reg_list_format_array_offset_bytes));
3719                 for (i = 0 ; i < (rlc_hdr->reg_list_format_size_bytes >> 2); i++)
3720                         adev->gfx.rlc.register_list_format[i] = le32_to_cpu(tmp[i]);
3721
3722                 adev->gfx.rlc.register_restore = adev->gfx.rlc.register_list_format + i;
3723
3724                 tmp = (unsigned int *)((uintptr_t)rlc_hdr +
3725                                                            le32_to_cpu(rlc_hdr->reg_list_array_offset_bytes));
3726                 for (i = 0 ; i < (rlc_hdr->reg_list_size_bytes >> 2); i++)
3727                         adev->gfx.rlc.register_restore[i] = le32_to_cpu(tmp[i]);
3728
3729                 if (adev->gfx.rlc.is_rlc_v2_1)
3730                         gfx_v10_0_init_rlc_ext_microcode(adev);
3731         }
3732
3733         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec%s.bin", chip_name, wks);
3734         err = request_firmware(&adev->gfx.mec_fw, fw_name, adev->dev);
3735         if (err)
3736                 goto out;
3737         err = amdgpu_ucode_validate(adev->gfx.mec_fw);
3738         if (err)
3739                 goto out;
3740         cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
3741         adev->gfx.mec_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
3742         adev->gfx.mec_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
3743
3744         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec2%s.bin", chip_name, wks);
3745         err = request_firmware(&adev->gfx.mec2_fw, fw_name, adev->dev);
3746         if (!err) {
3747                 err = amdgpu_ucode_validate(adev->gfx.mec2_fw);
3748                 if (err)
3749                         goto out;
3750                 cp_hdr = (const struct gfx_firmware_header_v1_0 *)
3751                 adev->gfx.mec2_fw->data;
3752                 adev->gfx.mec2_fw_version =
3753                 le32_to_cpu(cp_hdr->header.ucode_version);
3754                 adev->gfx.mec2_feature_version =
3755                 le32_to_cpu(cp_hdr->ucode_feature_version);
3756         } else {
3757                 err = 0;
3758                 adev->gfx.mec2_fw = NULL;
3759         }
3760
3761         if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
3762                 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_PFP];
3763                 info->ucode_id = AMDGPU_UCODE_ID_CP_PFP;
3764                 info->fw = adev->gfx.pfp_fw;
3765                 header = (const struct common_firmware_header *)info->fw->data;
3766                 adev->firmware.fw_size +=
3767                         ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
3768
3769                 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_ME];
3770                 info->ucode_id = AMDGPU_UCODE_ID_CP_ME;
3771                 info->fw = adev->gfx.me_fw;
3772                 header = (const struct common_firmware_header *)info->fw->data;
3773                 adev->firmware.fw_size +=
3774                         ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
3775
3776                 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_CE];
3777                 info->ucode_id = AMDGPU_UCODE_ID_CP_CE;
3778                 info->fw = adev->gfx.ce_fw;
3779                 header = (const struct common_firmware_header *)info->fw->data;
3780                 adev->firmware.fw_size +=
3781                         ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
3782
3783                 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_G];
3784                 info->ucode_id = AMDGPU_UCODE_ID_RLC_G;
3785                 info->fw = adev->gfx.rlc_fw;
3786                 if (info->fw) {
3787                         header = (const struct common_firmware_header *)info->fw->data;
3788                         adev->firmware.fw_size +=
3789                                 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
3790                 }
3791                 if (adev->gfx.rlc.is_rlc_v2_1 &&
3792                     adev->gfx.rlc.save_restore_list_cntl_size_bytes &&
3793                     adev->gfx.rlc.save_restore_list_gpm_size_bytes &&
3794                     adev->gfx.rlc.save_restore_list_srm_size_bytes) {
3795                         info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL];
3796                         info->ucode_id = AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL;
3797                         info->fw = adev->gfx.rlc_fw;
3798                         adev->firmware.fw_size +=
3799                                 ALIGN(adev->gfx.rlc.save_restore_list_cntl_size_bytes, PAGE_SIZE);
3800
3801                         info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM];
3802                         info->ucode_id = AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM;
3803                         info->fw = adev->gfx.rlc_fw;
3804                         adev->firmware.fw_size +=
3805                                 ALIGN(adev->gfx.rlc.save_restore_list_gpm_size_bytes, PAGE_SIZE);
3806
3807                         info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM];
3808                         info->ucode_id = AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM;
3809                         info->fw = adev->gfx.rlc_fw;
3810                         adev->firmware.fw_size +=
3811                                 ALIGN(adev->gfx.rlc.save_restore_list_srm_size_bytes, PAGE_SIZE);
3812                 }
3813
3814                 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC1];
3815                 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC1;
3816                 info->fw = adev->gfx.mec_fw;
3817                 header = (const struct common_firmware_header *)info->fw->data;
3818                 cp_hdr = (const struct gfx_firmware_header_v1_0 *)info->fw->data;
3819                 adev->firmware.fw_size +=
3820                         ALIGN(le32_to_cpu(header->ucode_size_bytes) -
3821                               le32_to_cpu(cp_hdr->jt_size) * 4, PAGE_SIZE);
3822
3823                 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC1_JT];
3824                 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC1_JT;
3825                 info->fw = adev->gfx.mec_fw;
3826                 adev->firmware.fw_size +=
3827                         ALIGN(le32_to_cpu(cp_hdr->jt_size) * 4, PAGE_SIZE);
3828
3829                 if (adev->gfx.mec2_fw) {
3830                         info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC2];
3831                         info->ucode_id = AMDGPU_UCODE_ID_CP_MEC2;
3832                         info->fw = adev->gfx.mec2_fw;
3833                         header = (const struct common_firmware_header *)info->fw->data;
3834                         cp_hdr = (const struct gfx_firmware_header_v1_0 *)info->fw->data;
3835                         adev->firmware.fw_size +=
3836                                 ALIGN(le32_to_cpu(header->ucode_size_bytes) -
3837                                       le32_to_cpu(cp_hdr->jt_size) * 4,
3838                                       PAGE_SIZE);
3839                         info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC2_JT];
3840                         info->ucode_id = AMDGPU_UCODE_ID_CP_MEC2_JT;
3841                         info->fw = adev->gfx.mec2_fw;
3842                         adev->firmware.fw_size +=
3843                                 ALIGN(le32_to_cpu(cp_hdr->jt_size) * 4,
3844                                       PAGE_SIZE);
3845                 }
3846         }
3847
3848         gfx_v10_0_check_fw_write_wait(adev);
3849 out:
3850         if (err) {
3851                 dev_err(adev->dev,
3852                         "gfx10: Failed to load firmware \"%s\"\n",
3853                         fw_name);
3854                 release_firmware(adev->gfx.pfp_fw);
3855                 adev->gfx.pfp_fw = NULL;
3856                 release_firmware(adev->gfx.me_fw);
3857                 adev->gfx.me_fw = NULL;
3858                 release_firmware(adev->gfx.ce_fw);
3859                 adev->gfx.ce_fw = NULL;
3860                 release_firmware(adev->gfx.rlc_fw);
3861                 adev->gfx.rlc_fw = NULL;
3862                 release_firmware(adev->gfx.mec_fw);
3863                 adev->gfx.mec_fw = NULL;
3864                 release_firmware(adev->gfx.mec2_fw);
3865                 adev->gfx.mec2_fw = NULL;
3866         }
3867
3868         gfx_v10_0_check_gfxoff_flag(adev);
3869
3870         return err;
3871 }
3872
3873 static u32 gfx_v10_0_get_csb_size(struct amdgpu_device *adev)
3874 {
3875         u32 count = 0;
3876         const struct cs_section_def *sect = NULL;
3877         const struct cs_extent_def *ext = NULL;
3878
3879         /* begin clear state */
3880         count += 2;
3881         /* context control state */
3882         count += 3;
3883
3884         for (sect = gfx10_cs_data; sect->section != NULL; ++sect) {
3885                 for (ext = sect->section; ext->extent != NULL; ++ext) {
3886                         if (sect->id == SECT_CONTEXT)
3887                                 count += 2 + ext->reg_count;
3888                         else
3889                                 return 0;
3890                 }
3891         }
3892
3893         /* set PA_SC_TILE_STEERING_OVERRIDE */
3894         count += 3;
3895         /* end clear state */
3896         count += 2;
3897         /* clear state */
3898         count += 2;
3899
3900         return count;
3901 }
3902
3903 static void gfx_v10_0_get_csb_buffer(struct amdgpu_device *adev,
3904                                     volatile u32 *buffer)
3905 {
3906         u32 count = 0, i;
3907         const struct cs_section_def *sect = NULL;
3908         const struct cs_extent_def *ext = NULL;
3909         int ctx_reg_offset;
3910
3911         if (adev->gfx.rlc.cs_data == NULL)
3912                 return;
3913         if (buffer == NULL)
3914                 return;
3915
3916         buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));
3917         buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
3918
3919         buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CONTEXT_CONTROL, 1));
3920         buffer[count++] = cpu_to_le32(0x80000000);
3921         buffer[count++] = cpu_to_le32(0x80000000);
3922
3923         for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) {
3924                 for (ext = sect->section; ext->extent != NULL; ++ext) {
3925                         if (sect->id == SECT_CONTEXT) {
3926                                 buffer[count++] =
3927                                         cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count));
3928                                 buffer[count++] = cpu_to_le32(ext->reg_index -
3929                                                 PACKET3_SET_CONTEXT_REG_START);
3930                                 for (i = 0; i < ext->reg_count; i++)
3931                                         buffer[count++] = cpu_to_le32(ext->extent[i]);
3932                         } else {
3933                                 return;
3934                         }
3935                 }
3936         }
3937
3938         ctx_reg_offset =
3939                 SOC15_REG_OFFSET(GC, 0, mmPA_SC_TILE_STEERING_OVERRIDE) - PACKET3_SET_CONTEXT_REG_START;
3940         buffer[count++] = cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, 1));
3941         buffer[count++] = cpu_to_le32(ctx_reg_offset);
3942         buffer[count++] = cpu_to_le32(adev->gfx.config.pa_sc_tile_steering_override);
3943
3944         buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));
3945         buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_END_CLEAR_STATE);
3946
3947         buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CLEAR_STATE, 0));
3948         buffer[count++] = cpu_to_le32(0);
3949 }
3950
3951 static void gfx_v10_0_rlc_fini(struct amdgpu_device *adev)
3952 {
3953         /* clear state block */
3954         amdgpu_bo_free_kernel(&adev->gfx.rlc.clear_state_obj,
3955                         &adev->gfx.rlc.clear_state_gpu_addr,
3956                         (void **)&adev->gfx.rlc.cs_ptr);
3957
3958         /* jump table block */
3959         amdgpu_bo_free_kernel(&adev->gfx.rlc.cp_table_obj,
3960                         &adev->gfx.rlc.cp_table_gpu_addr,
3961                         (void **)&adev->gfx.rlc.cp_table_ptr);
3962 }
3963
3964 static int gfx_v10_0_rlc_init(struct amdgpu_device *adev)
3965 {
3966         const struct cs_section_def *cs_data;
3967         int r;
3968
3969         adev->gfx.rlc.cs_data = gfx10_cs_data;
3970
3971         cs_data = adev->gfx.rlc.cs_data;
3972
3973         if (cs_data) {
3974                 /* init clear state block */
3975                 r = amdgpu_gfx_rlc_init_csb(adev);
3976                 if (r)
3977                         return r;
3978         }
3979
3980         /* init spm vmid with 0xf */
3981         if (adev->gfx.rlc.funcs->update_spm_vmid)
3982                 adev->gfx.rlc.funcs->update_spm_vmid(adev, 0xf);
3983
3984         return 0;
3985 }
3986
3987 static void gfx_v10_0_mec_fini(struct amdgpu_device *adev)
3988 {
3989         amdgpu_bo_free_kernel(&adev->gfx.mec.hpd_eop_obj, NULL, NULL);
3990         amdgpu_bo_free_kernel(&adev->gfx.mec.mec_fw_obj, NULL, NULL);
3991 }
3992
3993 static int gfx_v10_0_me_init(struct amdgpu_device *adev)
3994 {
3995         int r;
3996
3997         bitmap_zero(adev->gfx.me.queue_bitmap, AMDGPU_MAX_GFX_QUEUES);
3998
3999         amdgpu_gfx_graphics_queue_acquire(adev);
4000
4001         r = gfx_v10_0_init_microcode(adev);
4002         if (r)
4003                 DRM_ERROR("Failed to load gfx firmware!\n");
4004
4005         return r;
4006 }
4007
4008 static int gfx_v10_0_mec_init(struct amdgpu_device *adev)
4009 {
4010         int r;
4011         u32 *hpd;
4012         const __le32 *fw_data = NULL;
4013         unsigned fw_size;
4014         u32 *fw = NULL;
4015         size_t mec_hpd_size;
4016
4017         const struct gfx_firmware_header_v1_0 *mec_hdr = NULL;
4018
4019         bitmap_zero(adev->gfx.mec.queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES);
4020
4021         /* take ownership of the relevant compute queues */
4022         amdgpu_gfx_compute_queue_acquire(adev);
4023         mec_hpd_size = adev->gfx.num_compute_rings * GFX10_MEC_HPD_SIZE;
4024
4025         r = amdgpu_bo_create_reserved(adev, mec_hpd_size, PAGE_SIZE,
4026                                       AMDGPU_GEM_DOMAIN_GTT,
4027                                       &adev->gfx.mec.hpd_eop_obj,
4028                                       &adev->gfx.mec.hpd_eop_gpu_addr,
4029                                       (void **)&hpd);
4030         if (r) {
4031                 dev_warn(adev->dev, "(%d) create HDP EOP bo failed\n", r);
4032                 gfx_v10_0_mec_fini(adev);
4033                 return r;
4034         }
4035
4036         memset(hpd, 0, mec_hpd_size);
4037
4038         amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj);
4039         amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj);
4040
4041         if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
4042                 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
4043
4044                 fw_data = (const __le32 *) (adev->gfx.mec_fw->data +
4045                          le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes));
4046                 fw_size = le32_to_cpu(mec_hdr->header.ucode_size_bytes);
4047
4048                 r = amdgpu_bo_create_reserved(adev, mec_hdr->header.ucode_size_bytes,
4049                                               PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,
4050                                               &adev->gfx.mec.mec_fw_obj,
4051                                               &adev->gfx.mec.mec_fw_gpu_addr,
4052                                               (void **)&fw);
4053                 if (r) {
4054                         dev_err(adev->dev, "(%d) failed to create mec fw bo\n", r);
4055                         gfx_v10_0_mec_fini(adev);
4056                         return r;
4057                 }
4058
4059                 memcpy(fw, fw_data, fw_size);
4060
4061                 amdgpu_bo_kunmap(adev->gfx.mec.mec_fw_obj);
4062                 amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_obj);
4063         }
4064
4065         return 0;
4066 }
4067
4068 static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t wave, uint32_t address)
4069 {
4070         WREG32_SOC15(GC, 0, mmSQ_IND_INDEX,
4071                 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) |
4072                 (address << SQ_IND_INDEX__INDEX__SHIFT));
4073         return RREG32_SOC15(GC, 0, mmSQ_IND_DATA);
4074 }
4075
4076 static void wave_read_regs(struct amdgpu_device *adev, uint32_t wave,
4077                            uint32_t thread, uint32_t regno,
4078                            uint32_t num, uint32_t *out)
4079 {
4080         WREG32_SOC15(GC, 0, mmSQ_IND_INDEX,
4081                 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) |
4082                 (regno << SQ_IND_INDEX__INDEX__SHIFT) |
4083                 (thread << SQ_IND_INDEX__WORKITEM_ID__SHIFT) |
4084                 (SQ_IND_INDEX__AUTO_INCR_MASK));
4085         while (num--)
4086                 *(out++) = RREG32_SOC15(GC, 0, mmSQ_IND_DATA);
4087 }
4088
4089 static void gfx_v10_0_read_wave_data(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t *dst, int *no_fields)
4090 {
4091         /* in gfx10 the SIMD_ID is specified as part of the INSTANCE
4092          * field when performing a select_se_sh so it should be
4093          * zero here */
4094         WARN_ON(simd != 0);
4095
4096         /* type 2 wave data */
4097         dst[(*no_fields)++] = 2;
4098         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_STATUS);
4099         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_PC_LO);
4100         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_PC_HI);
4101         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXEC_LO);
4102         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXEC_HI);
4103         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_HW_ID1);
4104         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_HW_ID2);
4105         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_INST_DW0);
4106         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_GPR_ALLOC);
4107         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_LDS_ALLOC);
4108         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_TRAPSTS);
4109         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_STS);
4110         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_STS2);
4111         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_DBG1);
4112         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_M0);
4113 }
4114
4115 static void gfx_v10_0_read_wave_sgprs(struct amdgpu_device *adev, uint32_t simd,
4116                                      uint32_t wave, uint32_t start,
4117                                      uint32_t size, uint32_t *dst)
4118 {
4119         WARN_ON(simd != 0);
4120
4121         wave_read_regs(
4122                 adev, wave, 0, start + SQIND_WAVE_SGPRS_OFFSET, size,
4123                 dst);
4124 }
4125
4126 static void gfx_v10_0_read_wave_vgprs(struct amdgpu_device *adev, uint32_t simd,
4127                                       uint32_t wave, uint32_t thread,
4128                                       uint32_t start, uint32_t size,
4129                                       uint32_t *dst)
4130 {
4131         wave_read_regs(
4132                 adev, wave, thread,
4133                 start + SQIND_WAVE_VGPRS_OFFSET, size, dst);
4134 }
4135
4136 static void gfx_v10_0_select_me_pipe_q(struct amdgpu_device *adev,
4137                                                                           u32 me, u32 pipe, u32 q, u32 vm)
4138  {
4139        nv_grbm_select(adev, me, pipe, q, vm);
4140  }
4141
4142
4143 static const struct amdgpu_gfx_funcs gfx_v10_0_gfx_funcs = {
4144         .get_gpu_clock_counter = &gfx_v10_0_get_gpu_clock_counter,
4145         .select_se_sh = &gfx_v10_0_select_se_sh,
4146         .read_wave_data = &gfx_v10_0_read_wave_data,
4147         .read_wave_sgprs = &gfx_v10_0_read_wave_sgprs,
4148         .read_wave_vgprs = &gfx_v10_0_read_wave_vgprs,
4149         .select_me_pipe_q = &gfx_v10_0_select_me_pipe_q,
4150 };
4151
4152 static void gfx_v10_0_gpu_early_init(struct amdgpu_device *adev)
4153 {
4154         u32 gb_addr_config;
4155
4156         adev->gfx.funcs = &gfx_v10_0_gfx_funcs;
4157
4158         switch (adev->asic_type) {
4159         case CHIP_NAVI10:
4160         case CHIP_NAVI14:
4161         case CHIP_NAVI12:
4162                 adev->gfx.config.max_hw_contexts = 8;
4163                 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
4164                 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
4165                 adev->gfx.config.sc_hiz_tile_fifo_size = 0;
4166                 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0;
4167                 gb_addr_config = RREG32_SOC15(GC, 0, mmGB_ADDR_CONFIG);
4168                 break;
4169         case CHIP_SIENNA_CICHLID:
4170         case CHIP_NAVY_FLOUNDER:
4171                 adev->gfx.config.max_hw_contexts = 8;
4172                 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
4173                 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
4174                 adev->gfx.config.sc_hiz_tile_fifo_size = 0;
4175                 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0;
4176                 gb_addr_config = RREG32_SOC15(GC, 0, mmGB_ADDR_CONFIG);
4177                 adev->gfx.config.gb_addr_config_fields.num_pkrs =
4178                         1 << REG_GET_FIELD(gb_addr_config, GB_ADDR_CONFIG, NUM_PKRS);
4179                 break;
4180         default:
4181                 BUG();
4182                 break;
4183         }
4184
4185         adev->gfx.config.gb_addr_config = gb_addr_config;
4186
4187         adev->gfx.config.gb_addr_config_fields.num_pipes = 1 <<
4188                         REG_GET_FIELD(adev->gfx.config.gb_addr_config,
4189                                       GB_ADDR_CONFIG, NUM_PIPES);
4190
4191         adev->gfx.config.max_tile_pipes =
4192                 adev->gfx.config.gb_addr_config_fields.num_pipes;
4193
4194         adev->gfx.config.gb_addr_config_fields.max_compress_frags = 1 <<
4195                         REG_GET_FIELD(adev->gfx.config.gb_addr_config,
4196                                       GB_ADDR_CONFIG, MAX_COMPRESSED_FRAGS);
4197         adev->gfx.config.gb_addr_config_fields.num_rb_per_se = 1 <<
4198                         REG_GET_FIELD(adev->gfx.config.gb_addr_config,
4199                                       GB_ADDR_CONFIG, NUM_RB_PER_SE);
4200         adev->gfx.config.gb_addr_config_fields.num_se = 1 <<
4201                         REG_GET_FIELD(adev->gfx.config.gb_addr_config,
4202                                       GB_ADDR_CONFIG, NUM_SHADER_ENGINES);
4203         adev->gfx.config.gb_addr_config_fields.pipe_interleave_size = 1 << (8 +
4204                         REG_GET_FIELD(adev->gfx.config.gb_addr_config,
4205                                       GB_ADDR_CONFIG, PIPE_INTERLEAVE_SIZE));
4206 }
4207
4208 static int gfx_v10_0_gfx_ring_init(struct amdgpu_device *adev, int ring_id,
4209                                    int me, int pipe, int queue)
4210 {
4211         int r;
4212         struct amdgpu_ring *ring;
4213         unsigned int irq_type;
4214
4215         ring = &adev->gfx.gfx_ring[ring_id];
4216
4217         ring->me = me;
4218         ring->pipe = pipe;
4219         ring->queue = queue;
4220
4221         ring->ring_obj = NULL;
4222         ring->use_doorbell = true;
4223
4224         if (!ring_id)
4225                 ring->doorbell_index = adev->doorbell_index.gfx_ring0 << 1;
4226         else
4227                 ring->doorbell_index = adev->doorbell_index.gfx_ring1 << 1;
4228         sprintf(ring->name, "gfx_%d.%d.%d", ring->me, ring->pipe, ring->queue);
4229
4230         irq_type = AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP + ring->pipe;
4231         r = amdgpu_ring_init(adev, ring, 1024,
4232                              &adev->gfx.eop_irq, irq_type,
4233                              AMDGPU_RING_PRIO_DEFAULT);
4234         if (r)
4235                 return r;
4236         return 0;
4237 }
4238
4239 static int gfx_v10_0_compute_ring_init(struct amdgpu_device *adev, int ring_id,
4240                                        int mec, int pipe, int queue)
4241 {
4242         int r;
4243         unsigned irq_type;
4244         struct amdgpu_ring *ring;
4245         unsigned int hw_prio;
4246
4247         ring = &adev->gfx.compute_ring[ring_id];
4248
4249         /* mec0 is me1 */
4250         ring->me = mec + 1;
4251         ring->pipe = pipe;
4252         ring->queue = queue;
4253
4254         ring->ring_obj = NULL;
4255         ring->use_doorbell = true;
4256         ring->doorbell_index = (adev->doorbell_index.mec_ring0 + ring_id) << 1;
4257         ring->eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr
4258                                 + (ring_id * GFX10_MEC_HPD_SIZE);
4259         sprintf(ring->name, "comp_%d.%d.%d", ring->me, ring->pipe, ring->queue);
4260
4261         irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP
4262                 + ((ring->me - 1) * adev->gfx.mec.num_pipe_per_mec)
4263                 + ring->pipe;
4264         hw_prio = amdgpu_gfx_is_high_priority_compute_queue(adev, ring->queue) ?
4265                         AMDGPU_GFX_PIPE_PRIO_HIGH : AMDGPU_GFX_PIPE_PRIO_NORMAL;
4266         /* type-2 packets are deprecated on MEC, use type-3 instead */
4267         r = amdgpu_ring_init(adev, ring, 1024,
4268                              &adev->gfx.eop_irq, irq_type, hw_prio);
4269         if (r)
4270                 return r;
4271
4272         return 0;
4273 }
4274
4275 static int gfx_v10_0_sw_init(void *handle)
4276 {
4277         int i, j, k, r, ring_id = 0;
4278         struct amdgpu_kiq *kiq;
4279         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4280
4281         switch (adev->asic_type) {
4282         case CHIP_NAVI10:
4283         case CHIP_NAVI14:
4284         case CHIP_NAVI12:
4285                 adev->gfx.me.num_me = 1;
4286                 adev->gfx.me.num_pipe_per_me = 1;
4287                 adev->gfx.me.num_queue_per_pipe = 1;
4288                 adev->gfx.mec.num_mec = 2;
4289                 adev->gfx.mec.num_pipe_per_mec = 4;
4290                 adev->gfx.mec.num_queue_per_pipe = 8;
4291                 break;
4292         case CHIP_SIENNA_CICHLID:
4293         case CHIP_NAVY_FLOUNDER:
4294                 adev->gfx.me.num_me = 1;
4295                 adev->gfx.me.num_pipe_per_me = 1;
4296                 adev->gfx.me.num_queue_per_pipe = 1;
4297                 adev->gfx.mec.num_mec = 2;
4298                 adev->gfx.mec.num_pipe_per_mec = 4;
4299                 adev->gfx.mec.num_queue_per_pipe = 4;
4300                 break;
4301         default:
4302                 adev->gfx.me.num_me = 1;
4303                 adev->gfx.me.num_pipe_per_me = 1;
4304                 adev->gfx.me.num_queue_per_pipe = 1;
4305                 adev->gfx.mec.num_mec = 1;
4306                 adev->gfx.mec.num_pipe_per_mec = 4;
4307                 adev->gfx.mec.num_queue_per_pipe = 8;
4308                 break;
4309         }
4310
4311         /* KIQ event */
4312         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP,
4313                               GFX_10_1__SRCID__CP_IB2_INTERRUPT_PKT,
4314                               &adev->gfx.kiq.irq);
4315         if (r)
4316                 return r;
4317
4318         /* EOP Event */
4319         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP,
4320                               GFX_10_1__SRCID__CP_EOP_INTERRUPT,
4321                               &adev->gfx.eop_irq);
4322         if (r)
4323                 return r;
4324
4325         /* Privileged reg */
4326         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_10_1__SRCID__CP_PRIV_REG_FAULT,
4327                               &adev->gfx.priv_reg_irq);
4328         if (r)
4329                 return r;
4330
4331         /* Privileged inst */
4332         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_10_1__SRCID__CP_PRIV_INSTR_FAULT,
4333                               &adev->gfx.priv_inst_irq);
4334         if (r)
4335                 return r;
4336
4337         adev->gfx.gfx_current_status = AMDGPU_GFX_NORMAL_MODE;
4338
4339         gfx_v10_0_scratch_init(adev);
4340
4341         r = gfx_v10_0_me_init(adev);
4342         if (r)
4343                 return r;
4344
4345         r = gfx_v10_0_rlc_init(adev);
4346         if (r) {
4347                 DRM_ERROR("Failed to init rlc BOs!\n");
4348                 return r;
4349         }
4350
4351         r = gfx_v10_0_mec_init(adev);
4352         if (r) {
4353                 DRM_ERROR("Failed to init MEC BOs!\n");
4354                 return r;
4355         }
4356
4357         /* set up the gfx ring */
4358         for (i = 0; i < adev->gfx.me.num_me; i++) {
4359                 for (j = 0; j < adev->gfx.me.num_queue_per_pipe; j++) {
4360                         for (k = 0; k < adev->gfx.me.num_pipe_per_me; k++) {
4361                                 if (!amdgpu_gfx_is_me_queue_enabled(adev, i, k, j))
4362                                         continue;
4363
4364                                 r = gfx_v10_0_gfx_ring_init(adev, ring_id,
4365                                                             i, k, j);
4366                                 if (r)
4367                                         return r;
4368                                 ring_id++;
4369                         }
4370                 }
4371         }
4372
4373         ring_id = 0;
4374         /* set up the compute queues - allocate horizontally across pipes */
4375         for (i = 0; i < adev->gfx.mec.num_mec; ++i) {
4376                 for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) {
4377                         for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) {
4378                                 if (!amdgpu_gfx_is_mec_queue_enabled(adev, i, k,
4379                                                                      j))
4380                                         continue;
4381
4382                                 r = gfx_v10_0_compute_ring_init(adev, ring_id,
4383                                                                 i, k, j);
4384                                 if (r)
4385                                         return r;
4386
4387                                 ring_id++;
4388                         }
4389                 }
4390         }
4391
4392         r = amdgpu_gfx_kiq_init(adev, GFX10_MEC_HPD_SIZE);
4393         if (r) {
4394                 DRM_ERROR("Failed to init KIQ BOs!\n");
4395                 return r;
4396         }
4397
4398         kiq = &adev->gfx.kiq;
4399         r = amdgpu_gfx_kiq_init_ring(adev, &kiq->ring, &kiq->irq);
4400         if (r)
4401                 return r;
4402
4403         r = amdgpu_gfx_mqd_sw_init(adev, sizeof(struct v10_compute_mqd));
4404         if (r)
4405                 return r;
4406
4407         /* allocate visible FB for rlc auto-loading fw */
4408         if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) {
4409                 r = gfx_v10_0_rlc_backdoor_autoload_buffer_init(adev);
4410                 if (r)
4411                         return r;
4412         }
4413
4414         adev->gfx.ce_ram_size = F32_CE_PROGRAM_RAM_SIZE;
4415
4416         gfx_v10_0_gpu_early_init(adev);
4417
4418         return 0;
4419 }
4420
4421 static void gfx_v10_0_pfp_fini(struct amdgpu_device *adev)
4422 {
4423         amdgpu_bo_free_kernel(&adev->gfx.pfp.pfp_fw_obj,
4424                               &adev->gfx.pfp.pfp_fw_gpu_addr,
4425                               (void **)&adev->gfx.pfp.pfp_fw_ptr);
4426 }
4427
4428 static void gfx_v10_0_ce_fini(struct amdgpu_device *adev)
4429 {
4430         amdgpu_bo_free_kernel(&adev->gfx.ce.ce_fw_obj,
4431                               &adev->gfx.ce.ce_fw_gpu_addr,
4432                               (void **)&adev->gfx.ce.ce_fw_ptr);
4433 }
4434
4435 static void gfx_v10_0_me_fini(struct amdgpu_device *adev)
4436 {
4437         amdgpu_bo_free_kernel(&adev->gfx.me.me_fw_obj,
4438                               &adev->gfx.me.me_fw_gpu_addr,
4439                               (void **)&adev->gfx.me.me_fw_ptr);
4440 }
4441
4442 static int gfx_v10_0_sw_fini(void *handle)
4443 {
4444         int i;
4445         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4446
4447         for (i = 0; i < adev->gfx.num_gfx_rings; i++)
4448                 amdgpu_ring_fini(&adev->gfx.gfx_ring[i]);
4449         for (i = 0; i < adev->gfx.num_compute_rings; i++)
4450                 amdgpu_ring_fini(&adev->gfx.compute_ring[i]);
4451
4452         amdgpu_gfx_mqd_sw_fini(adev);
4453         amdgpu_gfx_kiq_free_ring(&adev->gfx.kiq.ring);
4454         amdgpu_gfx_kiq_fini(adev);
4455
4456         gfx_v10_0_pfp_fini(adev);
4457         gfx_v10_0_ce_fini(adev);
4458         gfx_v10_0_me_fini(adev);
4459         gfx_v10_0_rlc_fini(adev);
4460         gfx_v10_0_mec_fini(adev);
4461
4462         if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO)
4463                 gfx_v10_0_rlc_backdoor_autoload_buffer_fini(adev);
4464
4465         gfx_v10_0_free_microcode(adev);
4466
4467         return 0;
4468 }
4469
4470 static void gfx_v10_0_select_se_sh(struct amdgpu_device *adev, u32 se_num,
4471                                    u32 sh_num, u32 instance)
4472 {
4473         u32 data;
4474
4475         if (instance == 0xffffffff)
4476                 data = REG_SET_FIELD(0, GRBM_GFX_INDEX,
4477                                      INSTANCE_BROADCAST_WRITES, 1);
4478         else
4479                 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_INDEX,
4480                                      instance);
4481
4482         if (se_num == 0xffffffff)
4483                 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_BROADCAST_WRITES,
4484                                      1);
4485         else
4486                 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num);
4487
4488         if (sh_num == 0xffffffff)
4489                 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SA_BROADCAST_WRITES,
4490                                      1);
4491         else
4492                 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SA_INDEX, sh_num);
4493
4494         WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, data);
4495 }
4496
4497 static u32 gfx_v10_0_get_rb_active_bitmap(struct amdgpu_device *adev)
4498 {
4499         u32 data, mask;
4500
4501         data = RREG32_SOC15(GC, 0, mmCC_RB_BACKEND_DISABLE);
4502         data |= RREG32_SOC15(GC, 0, mmGC_USER_RB_BACKEND_DISABLE);
4503
4504         data &= CC_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK;
4505         data >>= GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT;
4506
4507         mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_backends_per_se /
4508                                          adev->gfx.config.max_sh_per_se);
4509
4510         return (~data) & mask;
4511 }
4512
4513 static void gfx_v10_0_setup_rb(struct amdgpu_device *adev)
4514 {
4515         int i, j;
4516         u32 data;
4517         u32 active_rbs = 0;
4518         u32 rb_bitmap_width_per_sh = adev->gfx.config.max_backends_per_se /
4519                                         adev->gfx.config.max_sh_per_se;
4520
4521         mutex_lock(&adev->grbm_idx_mutex);
4522         for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
4523                 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
4524                         gfx_v10_0_select_se_sh(adev, i, j, 0xffffffff);
4525                         data = gfx_v10_0_get_rb_active_bitmap(adev);
4526                         active_rbs |= data << ((i * adev->gfx.config.max_sh_per_se + j) *
4527                                                rb_bitmap_width_per_sh);
4528                 }
4529         }
4530         gfx_v10_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
4531         mutex_unlock(&adev->grbm_idx_mutex);
4532
4533         adev->gfx.config.backend_enable_mask = active_rbs;
4534         adev->gfx.config.num_rbs = hweight32(active_rbs);
4535 }
4536
4537 static u32 gfx_v10_0_init_pa_sc_tile_steering_override(struct amdgpu_device *adev)
4538 {
4539         uint32_t num_sc;
4540         uint32_t enabled_rb_per_sh;
4541         uint32_t active_rb_bitmap;
4542         uint32_t num_rb_per_sc;
4543         uint32_t num_packer_per_sc;
4544         uint32_t pa_sc_tile_steering_override;
4545
4546         /* for ASICs that integrates GFX v10.3
4547          * pa_sc_tile_steering_override should be set to 0 */
4548         if (adev->asic_type == CHIP_SIENNA_CICHLID ||
4549             adev->asic_type == CHIP_NAVY_FLOUNDER)
4550                 return 0;
4551
4552         /* init num_sc */
4553         num_sc = adev->gfx.config.max_shader_engines * adev->gfx.config.max_sh_per_se *
4554                         adev->gfx.config.num_sc_per_sh;
4555         /* init num_rb_per_sc */
4556         active_rb_bitmap = gfx_v10_0_get_rb_active_bitmap(adev);
4557         enabled_rb_per_sh = hweight32(active_rb_bitmap);
4558         num_rb_per_sc = enabled_rb_per_sh / adev->gfx.config.num_sc_per_sh;
4559         /* init num_packer_per_sc */
4560         num_packer_per_sc = adev->gfx.config.num_packer_per_sc;
4561
4562         pa_sc_tile_steering_override = 0;
4563         pa_sc_tile_steering_override |=
4564                 (order_base_2(num_sc) << PA_SC_TILE_STEERING_OVERRIDE__NUM_SC__SHIFT) &
4565                 PA_SC_TILE_STEERING_OVERRIDE__NUM_SC_MASK;
4566         pa_sc_tile_steering_override |=
4567                 (order_base_2(num_rb_per_sc) << PA_SC_TILE_STEERING_OVERRIDE__NUM_RB_PER_SC__SHIFT) &
4568                 PA_SC_TILE_STEERING_OVERRIDE__NUM_RB_PER_SC_MASK;
4569         pa_sc_tile_steering_override |=
4570                 (order_base_2(num_packer_per_sc) << PA_SC_TILE_STEERING_OVERRIDE__NUM_PACKER_PER_SC__SHIFT) &
4571                 PA_SC_TILE_STEERING_OVERRIDE__NUM_PACKER_PER_SC_MASK;
4572
4573         return pa_sc_tile_steering_override;
4574 }
4575
4576 #define DEFAULT_SH_MEM_BASES    (0x6000)
4577
4578 static void gfx_v10_0_init_compute_vmid(struct amdgpu_device *adev)
4579 {
4580         int i;
4581         uint32_t sh_mem_bases;
4582
4583         /*
4584          * Configure apertures:
4585          * LDS:         0x60000000'00000000 - 0x60000001'00000000 (4GB)
4586          * Scratch:     0x60000001'00000000 - 0x60000002'00000000 (4GB)
4587          * GPUVM:       0x60010000'00000000 - 0x60020000'00000000 (1TB)
4588          */
4589         sh_mem_bases = DEFAULT_SH_MEM_BASES | (DEFAULT_SH_MEM_BASES << 16);
4590
4591         mutex_lock(&adev->srbm_mutex);
4592         for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) {
4593                 nv_grbm_select(adev, 0, 0, 0, i);
4594                 /* CP and shaders */
4595                 WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, DEFAULT_SH_MEM_CONFIG);
4596                 WREG32_SOC15(GC, 0, mmSH_MEM_BASES, sh_mem_bases);
4597         }
4598         nv_grbm_select(adev, 0, 0, 0, 0);
4599         mutex_unlock(&adev->srbm_mutex);
4600
4601         /* Initialize all compute VMIDs to have no GDS, GWS, or OA
4602            acccess. These should be enabled by FW for target VMIDs. */
4603         for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) {
4604                 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_BASE, 2 * i, 0);
4605                 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_SIZE, 2 * i, 0);
4606                 WREG32_SOC15_OFFSET(GC, 0, mmGDS_GWS_VMID0, i, 0);
4607                 WREG32_SOC15_OFFSET(GC, 0, mmGDS_OA_VMID0, i, 0);
4608         }
4609 }
4610
4611 static void gfx_v10_0_init_gds_vmid(struct amdgpu_device *adev)
4612 {
4613         int vmid;
4614
4615         /*
4616          * Initialize all compute and user-gfx VMIDs to have no GDS, GWS, or OA
4617          * access. Compute VMIDs should be enabled by FW for target VMIDs,
4618          * the driver can enable them for graphics. VMID0 should maintain
4619          * access so that HWS firmware can save/restore entries.
4620          */
4621         for (vmid = 1; vmid < 16; vmid++) {
4622                 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_BASE, 2 * vmid, 0);
4623                 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_SIZE, 2 * vmid, 0);
4624                 WREG32_SOC15_OFFSET(GC, 0, mmGDS_GWS_VMID0, vmid, 0);
4625                 WREG32_SOC15_OFFSET(GC, 0, mmGDS_OA_VMID0, vmid, 0);
4626         }
4627 }
4628
4629
4630 static void gfx_v10_0_tcp_harvest(struct amdgpu_device *adev)
4631 {
4632         int i, j, k;
4633         int max_wgp_per_sh = adev->gfx.config.max_cu_per_sh >> 1;
4634         u32 tmp, wgp_active_bitmap = 0;
4635         u32 gcrd_targets_disable_tcp = 0;
4636         u32 utcl_invreq_disable = 0;
4637         /*
4638          * GCRD_TARGETS_DISABLE field contains
4639          * for Navi10/Navi12: GL1C=[18:15], SQC=[14:10], TCP=[9:0]
4640          * for Navi14: GL1C=[21:18], SQC=[17:12], TCP=[11:0]
4641          */
4642         u32 gcrd_targets_disable_mask = amdgpu_gfx_create_bitmask(
4643                 2 * max_wgp_per_sh + /* TCP */
4644                 max_wgp_per_sh + /* SQC */
4645                 4); /* GL1C */
4646         /*
4647          * UTCL1_UTCL0_INVREQ_DISABLE field contains
4648          * for Navi10Navi12: SQG=[24], RMI=[23:20], SQC=[19:10], TCP=[9:0]
4649          * for Navi14: SQG=[28], RMI=[27:24], SQC=[23:12], TCP=[11:0]
4650          */
4651         u32 utcl_invreq_disable_mask = amdgpu_gfx_create_bitmask(
4652                 2 * max_wgp_per_sh + /* TCP */
4653                 2 * max_wgp_per_sh + /* SQC */
4654                 4 + /* RMI */
4655                 1); /* SQG */
4656
4657         if (adev->asic_type == CHIP_NAVI10 ||
4658             adev->asic_type == CHIP_NAVI14 ||
4659             adev->asic_type == CHIP_NAVI12) {
4660                 mutex_lock(&adev->grbm_idx_mutex);
4661                 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
4662                         for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
4663                                 gfx_v10_0_select_se_sh(adev, i, j, 0xffffffff);
4664                                 wgp_active_bitmap = gfx_v10_0_get_wgp_active_bitmap_per_sh(adev);
4665                                 /*
4666                                  * Set corresponding TCP bits for the inactive WGPs in
4667                                  * GCRD_SA_TARGETS_DISABLE
4668                                  */
4669                                 gcrd_targets_disable_tcp = 0;
4670                                 /* Set TCP & SQC bits in UTCL1_UTCL0_INVREQ_DISABLE */
4671                                 utcl_invreq_disable = 0;
4672
4673                                 for (k = 0; k < max_wgp_per_sh; k++) {
4674                                         if (!(wgp_active_bitmap & (1 << k))) {
4675                                                 gcrd_targets_disable_tcp |= 3 << (2 * k);
4676                                                 utcl_invreq_disable |= (3 << (2 * k)) |
4677                                                         (3 << (2 * (max_wgp_per_sh + k)));
4678                                         }
4679                                 }
4680
4681                                 tmp = RREG32_SOC15(GC, 0, mmUTCL1_UTCL0_INVREQ_DISABLE);
4682                                 /* only override TCP & SQC bits */
4683                                 tmp &= 0xffffffff << (4 * max_wgp_per_sh);
4684                                 tmp |= (utcl_invreq_disable & utcl_invreq_disable_mask);
4685                                 WREG32_SOC15(GC, 0, mmUTCL1_UTCL0_INVREQ_DISABLE, tmp);
4686
4687                                 tmp = RREG32_SOC15(GC, 0, mmGCRD_SA_TARGETS_DISABLE);
4688                                 /* only override TCP bits */
4689                                 tmp &= 0xffffffff << (2 * max_wgp_per_sh);
4690                                 tmp |= (gcrd_targets_disable_tcp & gcrd_targets_disable_mask);
4691                                 WREG32_SOC15(GC, 0, mmGCRD_SA_TARGETS_DISABLE, tmp);
4692                         }
4693                 }
4694
4695                 gfx_v10_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
4696                 mutex_unlock(&adev->grbm_idx_mutex);
4697         }
4698 }
4699
4700 static void gfx_v10_0_get_tcc_info(struct amdgpu_device *adev)
4701 {
4702         /* TCCs are global (not instanced). */
4703         uint32_t tcc_disable = RREG32_SOC15(GC, 0, mmCGTS_TCC_DISABLE) |
4704                                RREG32_SOC15(GC, 0, mmCGTS_USER_TCC_DISABLE);
4705
4706         adev->gfx.config.tcc_disabled_mask =
4707                 REG_GET_FIELD(tcc_disable, CGTS_TCC_DISABLE, TCC_DISABLE) |
4708                 (REG_GET_FIELD(tcc_disable, CGTS_TCC_DISABLE, HI_TCC_DISABLE) << 16);
4709 }
4710
4711 static void gfx_v10_0_constants_init(struct amdgpu_device *adev)
4712 {
4713         u32 tmp;
4714         int i;
4715
4716         WREG32_FIELD15(GC, 0, GRBM_CNTL, READ_TIMEOUT, 0xff);
4717
4718         gfx_v10_0_setup_rb(adev);
4719         gfx_v10_0_get_cu_info(adev, &adev->gfx.cu_info);
4720         gfx_v10_0_get_tcc_info(adev);
4721         adev->gfx.config.pa_sc_tile_steering_override =
4722                 gfx_v10_0_init_pa_sc_tile_steering_override(adev);
4723
4724         /* XXX SH_MEM regs */
4725         /* where to put LDS, scratch, GPUVM in FSA64 space */
4726         mutex_lock(&adev->srbm_mutex);
4727         for (i = 0; i < adev->vm_manager.id_mgr[AMDGPU_GFXHUB_0].num_ids; i++) {
4728                 nv_grbm_select(adev, 0, 0, 0, i);
4729                 /* CP and shaders */
4730                 WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, DEFAULT_SH_MEM_CONFIG);
4731                 if (i != 0) {
4732                         tmp = REG_SET_FIELD(0, SH_MEM_BASES, PRIVATE_BASE,
4733                                 (adev->gmc.private_aperture_start >> 48));
4734                         tmp = REG_SET_FIELD(tmp, SH_MEM_BASES, SHARED_BASE,
4735                                 (adev->gmc.shared_aperture_start >> 48));
4736                         WREG32_SOC15(GC, 0, mmSH_MEM_BASES, tmp);
4737                 }
4738         }
4739         nv_grbm_select(adev, 0, 0, 0, 0);
4740
4741         mutex_unlock(&adev->srbm_mutex);
4742
4743         gfx_v10_0_init_compute_vmid(adev);
4744         gfx_v10_0_init_gds_vmid(adev);
4745
4746 }
4747
4748 static void gfx_v10_0_enable_gui_idle_interrupt(struct amdgpu_device *adev,
4749                                                bool enable)
4750 {
4751         u32 tmp;
4752
4753         if (amdgpu_sriov_vf(adev))
4754                 return;
4755
4756         tmp = RREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0);
4757
4758         tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE,
4759                             enable ? 1 : 0);
4760         tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE,
4761                             enable ? 1 : 0);
4762         tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE,
4763                             enable ? 1 : 0);
4764         tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, GFX_IDLE_INT_ENABLE,
4765                             enable ? 1 : 0);
4766
4767         WREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0, tmp);
4768 }
4769
4770 static int gfx_v10_0_init_csb(struct amdgpu_device *adev)
4771 {
4772         adev->gfx.rlc.funcs->get_csb_buffer(adev, adev->gfx.rlc.cs_ptr);
4773
4774         /* csib */
4775         if (adev->asic_type == CHIP_NAVI12) {
4776                 WREG32_SOC15_RLC(GC, 0, mmRLC_CSIB_ADDR_HI,
4777                                 adev->gfx.rlc.clear_state_gpu_addr >> 32);
4778                 WREG32_SOC15_RLC(GC, 0, mmRLC_CSIB_ADDR_LO,
4779                                 adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc);
4780                 WREG32_SOC15_RLC(GC, 0, mmRLC_CSIB_LENGTH, adev->gfx.rlc.clear_state_size);
4781         } else {
4782                 WREG32_SOC15(GC, 0, mmRLC_CSIB_ADDR_HI,
4783                                 adev->gfx.rlc.clear_state_gpu_addr >> 32);
4784                 WREG32_SOC15(GC, 0, mmRLC_CSIB_ADDR_LO,
4785                                 adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc);
4786                 WREG32_SOC15(GC, 0, mmRLC_CSIB_LENGTH, adev->gfx.rlc.clear_state_size);
4787         }
4788         return 0;
4789 }
4790
4791 void gfx_v10_0_rlc_stop(struct amdgpu_device *adev)
4792 {
4793         u32 tmp = RREG32_SOC15(GC, 0, mmRLC_CNTL);
4794
4795         tmp = REG_SET_FIELD(tmp, RLC_CNTL, RLC_ENABLE_F32, 0);
4796         WREG32_SOC15(GC, 0, mmRLC_CNTL, tmp);
4797 }
4798
4799 static void gfx_v10_0_rlc_reset(struct amdgpu_device *adev)
4800 {
4801         WREG32_FIELD15(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 1);
4802         udelay(50);
4803         WREG32_FIELD15(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 0);
4804         udelay(50);
4805 }
4806
4807 static void gfx_v10_0_rlc_smu_handshake_cntl(struct amdgpu_device *adev,
4808                                              bool enable)
4809 {
4810         uint32_t rlc_pg_cntl;
4811
4812         rlc_pg_cntl = RREG32_SOC15(GC, 0, mmRLC_PG_CNTL);
4813
4814         if (!enable) {
4815                 /* RLC_PG_CNTL[23] = 0 (default)
4816                  * RLC will wait for handshake acks with SMU
4817                  * GFXOFF will be enabled
4818                  * RLC_PG_CNTL[23] = 1
4819                  * RLC will not issue any message to SMU
4820                  * hence no handshake between SMU & RLC
4821                  * GFXOFF will be disabled
4822                  */
4823                 rlc_pg_cntl |= 0x800000;
4824         } else
4825                 rlc_pg_cntl &= ~0x800000;
4826         WREG32_SOC15(GC, 0, mmRLC_PG_CNTL, rlc_pg_cntl);
4827 }
4828
4829 static void gfx_v10_0_rlc_start(struct amdgpu_device *adev)
4830 {
4831         /* TODO: enable rlc & smu handshake until smu
4832          * and gfxoff feature works as expected */
4833         if (!(amdgpu_pp_feature_mask & PP_GFXOFF_MASK))
4834                 gfx_v10_0_rlc_smu_handshake_cntl(adev, false);
4835
4836         WREG32_FIELD15(GC, 0, RLC_CNTL, RLC_ENABLE_F32, 1);
4837         udelay(50);
4838 }
4839
4840 static void gfx_v10_0_rlc_enable_srm(struct amdgpu_device *adev)
4841 {
4842         uint32_t tmp;
4843
4844         /* enable Save Restore Machine */
4845         tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_CNTL));
4846         tmp |= RLC_SRM_CNTL__AUTO_INCR_ADDR_MASK;
4847         tmp |= RLC_SRM_CNTL__SRM_ENABLE_MASK;
4848         WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_CNTL), tmp);
4849 }
4850
4851 static int gfx_v10_0_rlc_load_microcode(struct amdgpu_device *adev)
4852 {
4853         const struct rlc_firmware_header_v2_0 *hdr;
4854         const __le32 *fw_data;
4855         unsigned i, fw_size;
4856
4857         if (!adev->gfx.rlc_fw)
4858                 return -EINVAL;
4859
4860         hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data;
4861         amdgpu_ucode_print_rlc_hdr(&hdr->header);
4862
4863         fw_data = (const __le32 *)(adev->gfx.rlc_fw->data +
4864                            le32_to_cpu(hdr->header.ucode_array_offset_bytes));
4865         fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
4866
4867         WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_ADDR,
4868                      RLCG_UCODE_LOADING_START_ADDRESS);
4869
4870         for (i = 0; i < fw_size; i++)
4871                 WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_DATA,
4872                              le32_to_cpup(fw_data++));
4873
4874         WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_ADDR, adev->gfx.rlc_fw_version);
4875
4876         return 0;
4877 }
4878
4879 static int gfx_v10_0_rlc_resume(struct amdgpu_device *adev)
4880 {
4881         int r;
4882
4883         if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
4884
4885                 r = gfx_v10_0_wait_for_rlc_autoload_complete(adev);
4886                 if (r)
4887                         return r;
4888
4889                 gfx_v10_0_init_csb(adev);
4890
4891                 if (!amdgpu_sriov_vf(adev)) /* enable RLC SRM */
4892                         gfx_v10_0_rlc_enable_srm(adev);
4893         } else {
4894                 if (amdgpu_sriov_vf(adev)) {
4895                         gfx_v10_0_init_csb(adev);
4896                         return 0;
4897                 }
4898
4899                 adev->gfx.rlc.funcs->stop(adev);
4900
4901                 /* disable CG */
4902                 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, 0);
4903
4904                 /* disable PG */
4905                 WREG32_SOC15(GC, 0, mmRLC_PG_CNTL, 0);
4906
4907                 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
4908                         /* legacy rlc firmware loading */
4909                         r = gfx_v10_0_rlc_load_microcode(adev);
4910                         if (r)
4911                                 return r;
4912                 } else if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) {
4913                         /* rlc backdoor autoload firmware */
4914                         r = gfx_v10_0_rlc_backdoor_autoload_enable(adev);
4915                         if (r)
4916                                 return r;
4917                 }
4918
4919                 gfx_v10_0_init_csb(adev);
4920
4921                 adev->gfx.rlc.funcs->start(adev);
4922
4923                 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) {
4924                         r = gfx_v10_0_wait_for_rlc_autoload_complete(adev);
4925                         if (r)
4926                                 return r;
4927                 }
4928         }
4929         return 0;
4930 }
4931
4932 static struct {
4933         FIRMWARE_ID     id;
4934         unsigned int    offset;
4935         unsigned int    size;
4936 } rlc_autoload_info[FIRMWARE_ID_MAX];
4937
4938 static int gfx_v10_0_parse_rlc_toc(struct amdgpu_device *adev)
4939 {
4940         int ret;
4941         RLC_TABLE_OF_CONTENT *rlc_toc;
4942
4943         ret = amdgpu_bo_create_reserved(adev, adev->psp.toc_bin_size, PAGE_SIZE,
4944                                         AMDGPU_GEM_DOMAIN_GTT,
4945                                         &adev->gfx.rlc.rlc_toc_bo,
4946                                         &adev->gfx.rlc.rlc_toc_gpu_addr,
4947                                         (void **)&adev->gfx.rlc.rlc_toc_buf);
4948         if (ret) {
4949                 dev_err(adev->dev, "(%d) failed to create rlc toc bo\n", ret);
4950                 return ret;
4951         }
4952
4953         /* Copy toc from psp sos fw to rlc toc buffer */
4954         memcpy(adev->gfx.rlc.rlc_toc_buf, adev->psp.toc_start_addr, adev->psp.toc_bin_size);
4955
4956         rlc_toc = (RLC_TABLE_OF_CONTENT *)adev->gfx.rlc.rlc_toc_buf;
4957         while (rlc_toc && (rlc_toc->id > FIRMWARE_ID_INVALID) &&
4958                 (rlc_toc->id < FIRMWARE_ID_MAX)) {
4959                 if ((rlc_toc->id >= FIRMWARE_ID_CP_CE) &&
4960                     (rlc_toc->id <= FIRMWARE_ID_CP_MES)) {
4961                         /* Offset needs 4KB alignment */
4962                         rlc_toc->offset = ALIGN(rlc_toc->offset * 4, PAGE_SIZE);
4963                 }
4964
4965                 rlc_autoload_info[rlc_toc->id].id = rlc_toc->id;
4966                 rlc_autoload_info[rlc_toc->id].offset = rlc_toc->offset * 4;
4967                 rlc_autoload_info[rlc_toc->id].size = rlc_toc->size * 4;
4968
4969                 rlc_toc++;
4970         }
4971
4972         return 0;
4973 }
4974
4975 static uint32_t gfx_v10_0_calc_toc_total_size(struct amdgpu_device *adev)
4976 {
4977         uint32_t total_size = 0;
4978         FIRMWARE_ID id;
4979         int ret;
4980
4981         ret = gfx_v10_0_parse_rlc_toc(adev);
4982         if (ret) {
4983                 dev_err(adev->dev, "failed to parse rlc toc\n");
4984                 return 0;
4985         }
4986
4987         for (id = FIRMWARE_ID_RLC_G_UCODE; id < FIRMWARE_ID_MAX; id++)
4988                 total_size += rlc_autoload_info[id].size;
4989
4990         /* In case the offset in rlc toc ucode is aligned */
4991         if (total_size < rlc_autoload_info[FIRMWARE_ID_MAX-1].offset)
4992                 total_size = rlc_autoload_info[FIRMWARE_ID_MAX-1].offset +
4993                                 rlc_autoload_info[FIRMWARE_ID_MAX-1].size;
4994
4995         return total_size;
4996 }
4997
4998 static int gfx_v10_0_rlc_backdoor_autoload_buffer_init(struct amdgpu_device *adev)
4999 {
5000         int r;
5001         uint32_t total_size;
5002
5003         total_size = gfx_v10_0_calc_toc_total_size(adev);
5004
5005         r = amdgpu_bo_create_reserved(adev, total_size, PAGE_SIZE,
5006                                       AMDGPU_GEM_DOMAIN_GTT,
5007                                       &adev->gfx.rlc.rlc_autoload_bo,
5008                                       &adev->gfx.rlc.rlc_autoload_gpu_addr,
5009                                       (void **)&adev->gfx.rlc.rlc_autoload_ptr);
5010         if (r) {
5011                 dev_err(adev->dev, "(%d) failed to create fw autoload bo\n", r);
5012                 return r;
5013         }
5014
5015         return 0;
5016 }
5017
5018 static void gfx_v10_0_rlc_backdoor_autoload_buffer_fini(struct amdgpu_device *adev)
5019 {
5020         amdgpu_bo_free_kernel(&adev->gfx.rlc.rlc_toc_bo,
5021                               &adev->gfx.rlc.rlc_toc_gpu_addr,
5022                               (void **)&adev->gfx.rlc.rlc_toc_buf);
5023         amdgpu_bo_free_kernel(&adev->gfx.rlc.rlc_autoload_bo,
5024                               &adev->gfx.rlc.rlc_autoload_gpu_addr,
5025                               (void **)&adev->gfx.rlc.rlc_autoload_ptr);
5026 }
5027
5028 static void gfx_v10_0_rlc_backdoor_autoload_copy_ucode(struct amdgpu_device *adev,
5029                                                        FIRMWARE_ID id,
5030                                                        const void *fw_data,
5031                                                        uint32_t fw_size)
5032 {
5033         uint32_t toc_offset;
5034         uint32_t toc_fw_size;
5035         char *ptr = adev->gfx.rlc.rlc_autoload_ptr;
5036
5037         if (id <= FIRMWARE_ID_INVALID || id >= FIRMWARE_ID_MAX)
5038                 return;
5039
5040         toc_offset = rlc_autoload_info[id].offset;
5041         toc_fw_size = rlc_autoload_info[id].size;
5042
5043         if (fw_size == 0)
5044                 fw_size = toc_fw_size;
5045
5046         if (fw_size > toc_fw_size)
5047                 fw_size = toc_fw_size;
5048
5049         memcpy(ptr + toc_offset, fw_data, fw_size);
5050
5051         if (fw_size < toc_fw_size)
5052                 memset(ptr + toc_offset + fw_size, 0, toc_fw_size - fw_size);
5053 }
5054
5055 static void gfx_v10_0_rlc_backdoor_autoload_copy_toc_ucode(struct amdgpu_device *adev)
5056 {
5057         void *data;
5058         uint32_t size;
5059
5060         data = adev->gfx.rlc.rlc_toc_buf;
5061         size = rlc_autoload_info[FIRMWARE_ID_RLC_TOC].size;
5062
5063         gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5064                                                    FIRMWARE_ID_RLC_TOC,
5065                                                    data, size);
5066 }
5067
5068 static void gfx_v10_0_rlc_backdoor_autoload_copy_gfx_ucode(struct amdgpu_device *adev)
5069 {
5070         const __le32 *fw_data;
5071         uint32_t fw_size;
5072         const struct gfx_firmware_header_v1_0 *cp_hdr;
5073         const struct rlc_firmware_header_v2_0 *rlc_hdr;
5074
5075         /* pfp ucode */
5076         cp_hdr = (const struct gfx_firmware_header_v1_0 *)
5077                 adev->gfx.pfp_fw->data;
5078         fw_data = (const __le32 *)(adev->gfx.pfp_fw->data +
5079                 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes));
5080         fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes);
5081         gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5082                                                    FIRMWARE_ID_CP_PFP,
5083                                                    fw_data, fw_size);
5084
5085         /* ce ucode */
5086         cp_hdr = (const struct gfx_firmware_header_v1_0 *)
5087                 adev->gfx.ce_fw->data;
5088         fw_data = (const __le32 *)(adev->gfx.ce_fw->data +
5089                 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes));
5090         fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes);
5091         gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5092                                                    FIRMWARE_ID_CP_CE,
5093                                                    fw_data, fw_size);
5094
5095         /* me ucode */
5096         cp_hdr = (const struct gfx_firmware_header_v1_0 *)
5097                 adev->gfx.me_fw->data;
5098         fw_data = (const __le32 *)(adev->gfx.me_fw->data +
5099                 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes));
5100         fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes);
5101         gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5102                                                    FIRMWARE_ID_CP_ME,
5103                                                    fw_data, fw_size);
5104
5105         /* rlc ucode */
5106         rlc_hdr = (const struct rlc_firmware_header_v2_0 *)
5107                 adev->gfx.rlc_fw->data;
5108         fw_data = (const __le32 *)(adev->gfx.rlc_fw->data +
5109                 le32_to_cpu(rlc_hdr->header.ucode_array_offset_bytes));
5110         fw_size = le32_to_cpu(rlc_hdr->header.ucode_size_bytes);
5111         gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5112                                                    FIRMWARE_ID_RLC_G_UCODE,
5113                                                    fw_data, fw_size);
5114
5115         /* mec1 ucode */
5116         cp_hdr = (const struct gfx_firmware_header_v1_0 *)
5117                 adev->gfx.mec_fw->data;
5118         fw_data = (const __le32 *) (adev->gfx.mec_fw->data +
5119                 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes));
5120         fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes) -
5121                 cp_hdr->jt_size * 4;
5122         gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5123                                                    FIRMWARE_ID_CP_MEC,
5124                                                    fw_data, fw_size);
5125         /* mec2 ucode is not necessary if mec2 ucode is same as mec1 */
5126 }
5127
5128 /* Temporarily put sdma part here */
5129 static void gfx_v10_0_rlc_backdoor_autoload_copy_sdma_ucode(struct amdgpu_device *adev)
5130 {
5131         const __le32 *fw_data;
5132         uint32_t fw_size;
5133         const struct sdma_firmware_header_v1_0 *sdma_hdr;
5134         int i;
5135
5136         for (i = 0; i < adev->sdma.num_instances; i++) {
5137                 sdma_hdr = (const struct sdma_firmware_header_v1_0 *)
5138                         adev->sdma.instance[i].fw->data;
5139                 fw_data = (const __le32 *) (adev->sdma.instance[i].fw->data +
5140                         le32_to_cpu(sdma_hdr->header.ucode_array_offset_bytes));
5141                 fw_size = le32_to_cpu(sdma_hdr->header.ucode_size_bytes);
5142
5143                 if (i == 0) {
5144                         gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5145                                 FIRMWARE_ID_SDMA0_UCODE, fw_data, fw_size);
5146                         gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5147                                 FIRMWARE_ID_SDMA0_JT,
5148                                 (uint32_t *)fw_data +
5149                                 sdma_hdr->jt_offset,
5150                                 sdma_hdr->jt_size * 4);
5151                 } else if (i == 1) {
5152                         gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5153                                 FIRMWARE_ID_SDMA1_UCODE, fw_data, fw_size);
5154                         gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5155                                 FIRMWARE_ID_SDMA1_JT,
5156                                 (uint32_t *)fw_data +
5157                                 sdma_hdr->jt_offset,
5158                                 sdma_hdr->jt_size * 4);
5159                 }
5160         }
5161 }
5162
5163 static int gfx_v10_0_rlc_backdoor_autoload_enable(struct amdgpu_device *adev)
5164 {
5165         uint32_t rlc_g_offset, rlc_g_size, tmp;
5166         uint64_t gpu_addr;
5167
5168         gfx_v10_0_rlc_backdoor_autoload_copy_toc_ucode(adev);
5169         gfx_v10_0_rlc_backdoor_autoload_copy_sdma_ucode(adev);
5170         gfx_v10_0_rlc_backdoor_autoload_copy_gfx_ucode(adev);
5171
5172         rlc_g_offset = rlc_autoload_info[FIRMWARE_ID_RLC_G_UCODE].offset;
5173         rlc_g_size = rlc_autoload_info[FIRMWARE_ID_RLC_G_UCODE].size;
5174         gpu_addr = adev->gfx.rlc.rlc_autoload_gpu_addr + rlc_g_offset;
5175
5176         WREG32_SOC15(GC, 0, mmRLC_HYP_BOOTLOAD_ADDR_HI, upper_32_bits(gpu_addr));
5177         WREG32_SOC15(GC, 0, mmRLC_HYP_BOOTLOAD_ADDR_LO, lower_32_bits(gpu_addr));
5178         WREG32_SOC15(GC, 0, mmRLC_HYP_BOOTLOAD_SIZE, rlc_g_size);
5179
5180         tmp = RREG32_SOC15(GC, 0, mmRLC_HYP_RESET_VECTOR);
5181         if (!(tmp & (RLC_HYP_RESET_VECTOR__COLD_BOOT_EXIT_MASK |
5182                    RLC_HYP_RESET_VECTOR__VDDGFX_EXIT_MASK))) {
5183                 DRM_ERROR("Neither COLD_BOOT_EXIT nor VDDGFX_EXIT is set\n");
5184                 return -EINVAL;
5185         }
5186
5187         tmp = RREG32_SOC15(GC, 0, mmRLC_CNTL);
5188         if (tmp & RLC_CNTL__RLC_ENABLE_F32_MASK) {
5189                 DRM_ERROR("RLC ROM should halt itself\n");
5190                 return -EINVAL;
5191         }
5192
5193         return 0;
5194 }
5195
5196 static int gfx_v10_0_rlc_backdoor_autoload_config_me_cache(struct amdgpu_device *adev)
5197 {
5198         uint32_t usec_timeout = 50000;  /* wait for 50ms */
5199         uint32_t tmp;
5200         int i;
5201         uint64_t addr;
5202
5203         /* Trigger an invalidation of the L1 instruction caches */
5204         tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL);
5205         tmp = REG_SET_FIELD(tmp, CP_ME_IC_OP_CNTL, INVALIDATE_CACHE, 1);
5206         WREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL, tmp);
5207
5208         /* Wait for invalidation complete */
5209         for (i = 0; i < usec_timeout; i++) {
5210                 tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL);
5211                 if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL,
5212                         INVALIDATE_CACHE_COMPLETE))
5213                         break;
5214                 udelay(1);
5215         }
5216
5217         if (i >= usec_timeout) {
5218                 dev_err(adev->dev, "failed to invalidate instruction cache\n");
5219                 return -EINVAL;
5220         }
5221
5222         /* Program me ucode address into intruction cache address register */
5223         addr = adev->gfx.rlc.rlc_autoload_gpu_addr +
5224                 rlc_autoload_info[FIRMWARE_ID_CP_ME].offset;
5225         WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_LO,
5226                         lower_32_bits(addr) & 0xFFFFF000);
5227         WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_HI,
5228                         upper_32_bits(addr));
5229
5230         return 0;
5231 }
5232
5233 static int gfx_v10_0_rlc_backdoor_autoload_config_ce_cache(struct amdgpu_device *adev)
5234 {
5235         uint32_t usec_timeout = 50000;  /* wait for 50ms */
5236         uint32_t tmp;
5237         int i;
5238         uint64_t addr;
5239
5240         /* Trigger an invalidation of the L1 instruction caches */
5241         tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL);
5242         tmp = REG_SET_FIELD(tmp, CP_CE_IC_OP_CNTL, INVALIDATE_CACHE, 1);
5243         WREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL, tmp);
5244
5245         /* Wait for invalidation complete */
5246         for (i = 0; i < usec_timeout; i++) {
5247                 tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL);
5248                 if (1 == REG_GET_FIELD(tmp, CP_CE_IC_OP_CNTL,
5249                         INVALIDATE_CACHE_COMPLETE))
5250                         break;
5251                 udelay(1);
5252         }
5253
5254         if (i >= usec_timeout) {
5255                 dev_err(adev->dev, "failed to invalidate instruction cache\n");
5256                 return -EINVAL;
5257         }
5258
5259         /* Program ce ucode address into intruction cache address register */
5260         addr = adev->gfx.rlc.rlc_autoload_gpu_addr +
5261                 rlc_autoload_info[FIRMWARE_ID_CP_CE].offset;
5262         WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_LO,
5263                         lower_32_bits(addr) & 0xFFFFF000);
5264         WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_HI,
5265                         upper_32_bits(addr));
5266
5267         return 0;
5268 }
5269
5270 static int gfx_v10_0_rlc_backdoor_autoload_config_pfp_cache(struct amdgpu_device *adev)
5271 {
5272         uint32_t usec_timeout = 50000;  /* wait for 50ms */
5273         uint32_t tmp;
5274         int i;
5275         uint64_t addr;
5276
5277         /* Trigger an invalidation of the L1 instruction caches */
5278         tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL);
5279         tmp = REG_SET_FIELD(tmp, CP_PFP_IC_OP_CNTL, INVALIDATE_CACHE, 1);
5280         WREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL, tmp);
5281
5282         /* Wait for invalidation complete */
5283         for (i = 0; i < usec_timeout; i++) {
5284                 tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL);
5285                 if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL,
5286                         INVALIDATE_CACHE_COMPLETE))
5287                         break;
5288                 udelay(1);
5289         }
5290
5291         if (i >= usec_timeout) {
5292                 dev_err(adev->dev, "failed to invalidate instruction cache\n");
5293                 return -EINVAL;
5294         }
5295
5296         /* Program pfp ucode address into intruction cache address register */
5297         addr = adev->gfx.rlc.rlc_autoload_gpu_addr +
5298                 rlc_autoload_info[FIRMWARE_ID_CP_PFP].offset;
5299         WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_LO,
5300                         lower_32_bits(addr) & 0xFFFFF000);
5301         WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_HI,
5302                         upper_32_bits(addr));
5303
5304         return 0;
5305 }
5306
5307 static int gfx_v10_0_rlc_backdoor_autoload_config_mec_cache(struct amdgpu_device *adev)
5308 {
5309         uint32_t usec_timeout = 50000;  /* wait for 50ms */
5310         uint32_t tmp;
5311         int i;
5312         uint64_t addr;
5313
5314         /* Trigger an invalidation of the L1 instruction caches */
5315         tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL);
5316         tmp = REG_SET_FIELD(tmp, CP_CPC_IC_OP_CNTL, INVALIDATE_CACHE, 1);
5317         WREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL, tmp);
5318
5319         /* Wait for invalidation complete */
5320         for (i = 0; i < usec_timeout; i++) {
5321                 tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL);
5322                 if (1 == REG_GET_FIELD(tmp, CP_CPC_IC_OP_CNTL,
5323                         INVALIDATE_CACHE_COMPLETE))
5324                         break;
5325                 udelay(1);
5326         }
5327
5328         if (i >= usec_timeout) {
5329                 dev_err(adev->dev, "failed to invalidate instruction cache\n");
5330                 return -EINVAL;
5331         }
5332
5333         /* Program mec1 ucode address into intruction cache address register */
5334         addr = adev->gfx.rlc.rlc_autoload_gpu_addr +
5335                 rlc_autoload_info[FIRMWARE_ID_CP_MEC].offset;
5336         WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_LO,
5337                         lower_32_bits(addr) & 0xFFFFF000);
5338         WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_HI,
5339                         upper_32_bits(addr));
5340
5341         return 0;
5342 }
5343
5344 static int gfx_v10_0_wait_for_rlc_autoload_complete(struct amdgpu_device *adev)
5345 {
5346         uint32_t cp_status;
5347         uint32_t bootload_status;
5348         int i, r;
5349
5350         for (i = 0; i < adev->usec_timeout; i++) {
5351                 cp_status = RREG32_SOC15(GC, 0, mmCP_STAT);
5352                 bootload_status = RREG32_SOC15(GC, 0, mmRLC_RLCS_BOOTLOAD_STATUS);
5353                 if ((cp_status == 0) &&
5354                     (REG_GET_FIELD(bootload_status,
5355                         RLC_RLCS_BOOTLOAD_STATUS, BOOTLOAD_COMPLETE) == 1)) {
5356                         break;
5357                 }
5358                 udelay(1);
5359         }
5360
5361         if (i >= adev->usec_timeout) {
5362                 dev_err(adev->dev, "rlc autoload: gc ucode autoload timeout\n");
5363                 return -ETIMEDOUT;
5364         }
5365
5366         if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) {
5367                 r = gfx_v10_0_rlc_backdoor_autoload_config_me_cache(adev);
5368                 if (r)
5369                         return r;
5370
5371                 r = gfx_v10_0_rlc_backdoor_autoload_config_ce_cache(adev);
5372                 if (r)
5373                         return r;
5374
5375                 r = gfx_v10_0_rlc_backdoor_autoload_config_pfp_cache(adev);
5376                 if (r)
5377                         return r;
5378
5379                 r = gfx_v10_0_rlc_backdoor_autoload_config_mec_cache(adev);
5380                 if (r)
5381                         return r;
5382         }
5383
5384         return 0;
5385 }
5386
5387 static int gfx_v10_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable)
5388 {
5389         int i;
5390         u32 tmp = RREG32_SOC15(GC, 0, mmCP_ME_CNTL);
5391
5392         tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, enable ? 0 : 1);
5393         tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, enable ? 0 : 1);
5394         tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_HALT, enable ? 0 : 1);
5395
5396         if (adev->asic_type == CHIP_NAVI12) {
5397                 WREG32_SOC15_RLC(GC, 0, mmCP_ME_CNTL, tmp);
5398         } else {
5399                 WREG32_SOC15(GC, 0, mmCP_ME_CNTL, tmp);
5400         }
5401
5402         for (i = 0; i < adev->usec_timeout; i++) {
5403                 if (RREG32_SOC15(GC, 0, mmCP_STAT) == 0)
5404                         break;
5405                 udelay(1);
5406         }
5407
5408         if (i >= adev->usec_timeout)
5409                 DRM_ERROR("failed to %s cp gfx\n", enable ? "unhalt" : "halt");
5410
5411         return 0;
5412 }
5413
5414 static int gfx_v10_0_cp_gfx_load_pfp_microcode(struct amdgpu_device *adev)
5415 {
5416         int r;
5417         const struct gfx_firmware_header_v1_0 *pfp_hdr;
5418         const __le32 *fw_data;
5419         unsigned i, fw_size;
5420         uint32_t tmp;
5421         uint32_t usec_timeout = 50000;  /* wait for 50ms */
5422
5423         pfp_hdr = (const struct gfx_firmware_header_v1_0 *)
5424                 adev->gfx.pfp_fw->data;
5425
5426         amdgpu_ucode_print_gfx_hdr(&pfp_hdr->header);
5427
5428         fw_data = (const __le32 *)(adev->gfx.pfp_fw->data +
5429                 le32_to_cpu(pfp_hdr->header.ucode_array_offset_bytes));
5430         fw_size = le32_to_cpu(pfp_hdr->header.ucode_size_bytes);
5431
5432         r = amdgpu_bo_create_reserved(adev, pfp_hdr->header.ucode_size_bytes,
5433                                       PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,
5434                                       &adev->gfx.pfp.pfp_fw_obj,
5435                                       &adev->gfx.pfp.pfp_fw_gpu_addr,
5436                                       (void **)&adev->gfx.pfp.pfp_fw_ptr);
5437         if (r) {
5438                 dev_err(adev->dev, "(%d) failed to create pfp fw bo\n", r);
5439                 gfx_v10_0_pfp_fini(adev);
5440                 return r;
5441         }
5442
5443         memcpy(adev->gfx.pfp.pfp_fw_ptr, fw_data, fw_size);
5444
5445         amdgpu_bo_kunmap(adev->gfx.pfp.pfp_fw_obj);
5446         amdgpu_bo_unreserve(adev->gfx.pfp.pfp_fw_obj);
5447
5448         /* Trigger an invalidation of the L1 instruction caches */
5449         tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL);
5450         tmp = REG_SET_FIELD(tmp, CP_PFP_IC_OP_CNTL, INVALIDATE_CACHE, 1);
5451         WREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL, tmp);
5452
5453         /* Wait for invalidation complete */
5454         for (i = 0; i < usec_timeout; i++) {
5455                 tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL);
5456                 if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL,
5457                         INVALIDATE_CACHE_COMPLETE))
5458                         break;
5459                 udelay(1);
5460         }
5461
5462         if (i >= usec_timeout) {
5463                 dev_err(adev->dev, "failed to invalidate instruction cache\n");
5464                 return -EINVAL;
5465         }
5466
5467         if (amdgpu_emu_mode == 1)
5468                 adev->nbio.funcs->hdp_flush(adev, NULL);
5469
5470         tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_CNTL);
5471         tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, VMID, 0);
5472         tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, CACHE_POLICY, 0);
5473         tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, EXE_DISABLE, 0);
5474         tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, ADDRESS_CLAMP, 1);
5475         WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_CNTL, tmp);
5476         WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_LO,
5477                 adev->gfx.pfp.pfp_fw_gpu_addr & 0xFFFFF000);
5478         WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_HI,
5479                 upper_32_bits(adev->gfx.pfp.pfp_fw_gpu_addr));
5480
5481         WREG32_SOC15(GC, 0, mmCP_HYP_PFP_UCODE_ADDR, 0);
5482
5483         for (i = 0; i < pfp_hdr->jt_size; i++)
5484                 WREG32_SOC15(GC, 0, mmCP_HYP_PFP_UCODE_DATA,
5485                              le32_to_cpup(fw_data + pfp_hdr->jt_offset + i));
5486
5487         WREG32_SOC15(GC, 0, mmCP_HYP_PFP_UCODE_ADDR, adev->gfx.pfp_fw_version);
5488
5489         return 0;
5490 }
5491
5492 static int gfx_v10_0_cp_gfx_load_ce_microcode(struct amdgpu_device *adev)
5493 {
5494         int r;
5495         const struct gfx_firmware_header_v1_0 *ce_hdr;
5496         const __le32 *fw_data;
5497         unsigned i, fw_size;
5498         uint32_t tmp;
5499         uint32_t usec_timeout = 50000;  /* wait for 50ms */
5500
5501         ce_hdr = (const struct gfx_firmware_header_v1_0 *)
5502                 adev->gfx.ce_fw->data;
5503
5504         amdgpu_ucode_print_gfx_hdr(&ce_hdr->header);
5505
5506         fw_data = (const __le32 *)(adev->gfx.ce_fw->data +
5507                 le32_to_cpu(ce_hdr->header.ucode_array_offset_bytes));
5508         fw_size = le32_to_cpu(ce_hdr->header.ucode_size_bytes);
5509
5510         r = amdgpu_bo_create_reserved(adev, ce_hdr->header.ucode_size_bytes,
5511                                       PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,
5512                                       &adev->gfx.ce.ce_fw_obj,
5513                                       &adev->gfx.ce.ce_fw_gpu_addr,
5514                                       (void **)&adev->gfx.ce.ce_fw_ptr);
5515         if (r) {
5516                 dev_err(adev->dev, "(%d) failed to create ce fw bo\n", r);
5517                 gfx_v10_0_ce_fini(adev);
5518                 return r;
5519         }
5520
5521         memcpy(adev->gfx.ce.ce_fw_ptr, fw_data, fw_size);
5522
5523         amdgpu_bo_kunmap(adev->gfx.ce.ce_fw_obj);
5524         amdgpu_bo_unreserve(adev->gfx.ce.ce_fw_obj);
5525
5526         /* Trigger an invalidation of the L1 instruction caches */
5527         tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL);
5528         tmp = REG_SET_FIELD(tmp, CP_CE_IC_OP_CNTL, INVALIDATE_CACHE, 1);
5529         WREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL, tmp);
5530
5531         /* Wait for invalidation complete */
5532         for (i = 0; i < usec_timeout; i++) {
5533                 tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL);
5534                 if (1 == REG_GET_FIELD(tmp, CP_CE_IC_OP_CNTL,
5535                         INVALIDATE_CACHE_COMPLETE))
5536                         break;
5537                 udelay(1);
5538         }
5539
5540         if (i >= usec_timeout) {
5541                 dev_err(adev->dev, "failed to invalidate instruction cache\n");
5542                 return -EINVAL;
5543         }
5544
5545         if (amdgpu_emu_mode == 1)
5546                 adev->nbio.funcs->hdp_flush(adev, NULL);
5547
5548         tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_CNTL);
5549         tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, VMID, 0);
5550         tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, CACHE_POLICY, 0);
5551         tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, EXE_DISABLE, 0);
5552         tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, ADDRESS_CLAMP, 1);
5553         WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_LO,
5554                 adev->gfx.ce.ce_fw_gpu_addr & 0xFFFFF000);
5555         WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_HI,
5556                 upper_32_bits(adev->gfx.ce.ce_fw_gpu_addr));
5557
5558         WREG32_SOC15(GC, 0, mmCP_HYP_CE_UCODE_ADDR, 0);
5559
5560         for (i = 0; i < ce_hdr->jt_size; i++)
5561                 WREG32_SOC15(GC, 0, mmCP_HYP_CE_UCODE_DATA,
5562                              le32_to_cpup(fw_data + ce_hdr->jt_offset + i));
5563
5564         WREG32_SOC15(GC, 0, mmCP_HYP_CE_UCODE_ADDR, adev->gfx.ce_fw_version);
5565
5566         return 0;
5567 }
5568
5569 static int gfx_v10_0_cp_gfx_load_me_microcode(struct amdgpu_device *adev)
5570 {
5571         int r;
5572         const struct gfx_firmware_header_v1_0 *me_hdr;
5573         const __le32 *fw_data;
5574         unsigned i, fw_size;
5575         uint32_t tmp;
5576         uint32_t usec_timeout = 50000;  /* wait for 50ms */
5577
5578         me_hdr = (const struct gfx_firmware_header_v1_0 *)
5579                 adev->gfx.me_fw->data;
5580
5581         amdgpu_ucode_print_gfx_hdr(&me_hdr->header);
5582
5583         fw_data = (const __le32 *)(adev->gfx.me_fw->data +
5584                 le32_to_cpu(me_hdr->header.ucode_array_offset_bytes));
5585         fw_size = le32_to_cpu(me_hdr->header.ucode_size_bytes);
5586
5587         r = amdgpu_bo_create_reserved(adev, me_hdr->header.ucode_size_bytes,
5588                                       PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,
5589                                       &adev->gfx.me.me_fw_obj,
5590                                       &adev->gfx.me.me_fw_gpu_addr,
5591                                       (void **)&adev->gfx.me.me_fw_ptr);
5592         if (r) {
5593                 dev_err(adev->dev, "(%d) failed to create me fw bo\n", r);
5594                 gfx_v10_0_me_fini(adev);
5595                 return r;
5596         }
5597
5598         memcpy(adev->gfx.me.me_fw_ptr, fw_data, fw_size);
5599
5600         amdgpu_bo_kunmap(adev->gfx.me.me_fw_obj);
5601         amdgpu_bo_unreserve(adev->gfx.me.me_fw_obj);
5602
5603         /* Trigger an invalidation of the L1 instruction caches */
5604         tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL);
5605         tmp = REG_SET_FIELD(tmp, CP_ME_IC_OP_CNTL, INVALIDATE_CACHE, 1);
5606         WREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL, tmp);
5607
5608         /* Wait for invalidation complete */
5609         for (i = 0; i < usec_timeout; i++) {
5610                 tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL);
5611                 if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL,
5612                         INVALIDATE_CACHE_COMPLETE))
5613                         break;
5614                 udelay(1);
5615         }
5616
5617         if (i >= usec_timeout) {
5618                 dev_err(adev->dev, "failed to invalidate instruction cache\n");
5619                 return -EINVAL;
5620         }
5621
5622         if (amdgpu_emu_mode == 1)
5623                 adev->nbio.funcs->hdp_flush(adev, NULL);
5624
5625         tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_CNTL);
5626         tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, VMID, 0);
5627         tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, CACHE_POLICY, 0);
5628         tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, EXE_DISABLE, 0);
5629         tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, ADDRESS_CLAMP, 1);
5630         WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_LO,
5631                 adev->gfx.me.me_fw_gpu_addr & 0xFFFFF000);
5632         WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_HI,
5633                 upper_32_bits(adev->gfx.me.me_fw_gpu_addr));
5634
5635         WREG32_SOC15(GC, 0, mmCP_HYP_ME_UCODE_ADDR, 0);
5636
5637         for (i = 0; i < me_hdr->jt_size; i++)
5638                 WREG32_SOC15(GC, 0, mmCP_HYP_ME_UCODE_DATA,
5639                              le32_to_cpup(fw_data + me_hdr->jt_offset + i));
5640
5641         WREG32_SOC15(GC, 0, mmCP_HYP_ME_UCODE_ADDR, adev->gfx.me_fw_version);
5642
5643         return 0;
5644 }
5645
5646 static int gfx_v10_0_cp_gfx_load_microcode(struct amdgpu_device *adev)
5647 {
5648         int r;
5649
5650         if (!adev->gfx.me_fw || !adev->gfx.pfp_fw || !adev->gfx.ce_fw)
5651                 return -EINVAL;
5652
5653         gfx_v10_0_cp_gfx_enable(adev, false);
5654
5655         r = gfx_v10_0_cp_gfx_load_pfp_microcode(adev);
5656         if (r) {
5657                 dev_err(adev->dev, "(%d) failed to load pfp fw\n", r);
5658                 return r;
5659         }
5660
5661         r = gfx_v10_0_cp_gfx_load_ce_microcode(adev);
5662         if (r) {
5663                 dev_err(adev->dev, "(%d) failed to load ce fw\n", r);
5664                 return r;
5665         }
5666
5667         r = gfx_v10_0_cp_gfx_load_me_microcode(adev);
5668         if (r) {
5669                 dev_err(adev->dev, "(%d) failed to load me fw\n", r);
5670                 return r;
5671         }
5672
5673         return 0;
5674 }
5675
5676 static int gfx_v10_0_cp_gfx_start(struct amdgpu_device *adev)
5677 {
5678         struct amdgpu_ring *ring;
5679         const struct cs_section_def *sect = NULL;
5680         const struct cs_extent_def *ext = NULL;
5681         int r, i;
5682         int ctx_reg_offset;
5683
5684         /* init the CP */
5685         WREG32_SOC15(GC, 0, mmCP_MAX_CONTEXT,
5686                      adev->gfx.config.max_hw_contexts - 1);
5687         WREG32_SOC15(GC, 0, mmCP_DEVICE_ID, 1);
5688
5689         gfx_v10_0_cp_gfx_enable(adev, true);
5690
5691         ring = &adev->gfx.gfx_ring[0];
5692         r = amdgpu_ring_alloc(ring, gfx_v10_0_get_csb_size(adev) + 4);
5693         if (r) {
5694                 DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r);
5695                 return r;
5696         }
5697
5698         amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
5699         amdgpu_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
5700
5701         amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1));
5702         amdgpu_ring_write(ring, 0x80000000);
5703         amdgpu_ring_write(ring, 0x80000000);
5704
5705         for (sect = gfx10_cs_data; sect->section != NULL; ++sect) {
5706                 for (ext = sect->section; ext->extent != NULL; ++ext) {
5707                         if (sect->id == SECT_CONTEXT) {
5708                                 amdgpu_ring_write(ring,
5709                                                   PACKET3(PACKET3_SET_CONTEXT_REG,
5710                                                           ext->reg_count));
5711                                 amdgpu_ring_write(ring, ext->reg_index -
5712                                                   PACKET3_SET_CONTEXT_REG_START);
5713                                 for (i = 0; i < ext->reg_count; i++)
5714                                         amdgpu_ring_write(ring, ext->extent[i]);
5715                         }
5716                 }
5717         }
5718
5719         ctx_reg_offset =
5720                 SOC15_REG_OFFSET(GC, 0, mmPA_SC_TILE_STEERING_OVERRIDE) - PACKET3_SET_CONTEXT_REG_START;
5721         amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
5722         amdgpu_ring_write(ring, ctx_reg_offset);
5723         amdgpu_ring_write(ring, adev->gfx.config.pa_sc_tile_steering_override);
5724
5725         amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
5726         amdgpu_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE);
5727
5728         amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));
5729         amdgpu_ring_write(ring, 0);
5730
5731         amdgpu_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2));
5732         amdgpu_ring_write(ring, PACKET3_BASE_INDEX(CE_PARTITION_BASE));
5733         amdgpu_ring_write(ring, 0x8000);
5734         amdgpu_ring_write(ring, 0x8000);
5735
5736         amdgpu_ring_commit(ring);
5737
5738         /* submit cs packet to copy state 0 to next available state */
5739         if (adev->gfx.num_gfx_rings > 1) {
5740                 /* maximum supported gfx ring is 2 */
5741                 ring = &adev->gfx.gfx_ring[1];
5742                 r = amdgpu_ring_alloc(ring, 2);
5743                 if (r) {
5744                         DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r);
5745                         return r;
5746                 }
5747
5748                 amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));
5749                 amdgpu_ring_write(ring, 0);
5750
5751                 amdgpu_ring_commit(ring);
5752         }
5753         return 0;
5754 }
5755
5756 static void gfx_v10_0_cp_gfx_switch_pipe(struct amdgpu_device *adev,
5757                                          CP_PIPE_ID pipe)
5758 {
5759         u32 tmp;
5760
5761         tmp = RREG32_SOC15(GC, 0, mmGRBM_GFX_CNTL);
5762         tmp = REG_SET_FIELD(tmp, GRBM_GFX_CNTL, PIPEID, pipe);
5763
5764         WREG32_SOC15(GC, 0, mmGRBM_GFX_CNTL, tmp);
5765 }
5766
5767 static void gfx_v10_0_cp_gfx_set_doorbell(struct amdgpu_device *adev,
5768                                           struct amdgpu_ring *ring)
5769 {
5770         u32 tmp;
5771
5772         tmp = RREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL);
5773         if (ring->use_doorbell) {
5774                 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
5775                                     DOORBELL_OFFSET, ring->doorbell_index);
5776                 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
5777                                     DOORBELL_EN, 1);
5778         } else {
5779                 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
5780                                     DOORBELL_EN, 0);
5781         }
5782         WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL, tmp);
5783         switch (adev->asic_type) {
5784         case CHIP_SIENNA_CICHLID:
5785         case CHIP_NAVY_FLOUNDER:
5786                 tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER,
5787                                     DOORBELL_RANGE_LOWER_Sienna_Cichlid, ring->doorbell_index);
5788                 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_LOWER, tmp);
5789
5790                 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_UPPER,
5791                              CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_Sienna_Cichlid_MASK);
5792                 break;
5793         default:
5794                 tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER,
5795                                     DOORBELL_RANGE_LOWER, ring->doorbell_index);
5796                 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_LOWER, tmp);
5797
5798                 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_UPPER,
5799                              CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_MASK);
5800                 break;
5801         }
5802 }
5803
5804 static int gfx_v10_0_cp_gfx_resume(struct amdgpu_device *adev)
5805 {
5806         struct amdgpu_ring *ring;
5807         u32 tmp;
5808         u32 rb_bufsz;
5809         u64 rb_addr, rptr_addr, wptr_gpu_addr;
5810         u32 i;
5811
5812         /* Set the write pointer delay */
5813         WREG32_SOC15(GC, 0, mmCP_RB_WPTR_DELAY, 0);
5814
5815         /* set the RB to use vmid 0 */
5816         WREG32_SOC15(GC, 0, mmCP_RB_VMID, 0);
5817
5818         /* Init gfx ring 0 for pipe 0 */
5819         mutex_lock(&adev->srbm_mutex);
5820         gfx_v10_0_cp_gfx_switch_pipe(adev, PIPE_ID0);
5821
5822         /* Set ring buffer size */
5823         ring = &adev->gfx.gfx_ring[0];
5824         rb_bufsz = order_base_2(ring->ring_size / 8);
5825         tmp = REG_SET_FIELD(0, CP_RB0_CNTL, RB_BUFSZ, rb_bufsz);
5826         tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, RB_BLKSZ, rb_bufsz - 2);
5827 #ifdef __BIG_ENDIAN
5828         tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, BUF_SWAP, 1);
5829 #endif
5830         WREG32_SOC15(GC, 0, mmCP_RB0_CNTL, tmp);
5831
5832         /* Initialize the ring buffer's write pointers */
5833         ring->wptr = 0;
5834         WREG32_SOC15(GC, 0, mmCP_RB0_WPTR, lower_32_bits(ring->wptr));
5835         WREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI, upper_32_bits(ring->wptr));
5836
5837         /* set the wb address wether it's enabled or not */
5838         rptr_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
5839         WREG32_SOC15(GC, 0, mmCP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr));
5840         WREG32_SOC15(GC, 0, mmCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) &
5841                      CP_RB_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK);
5842
5843         wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
5844         WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_LO,
5845                      lower_32_bits(wptr_gpu_addr));
5846         WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI,
5847                      upper_32_bits(wptr_gpu_addr));
5848
5849         mdelay(1);
5850         WREG32_SOC15(GC, 0, mmCP_RB0_CNTL, tmp);
5851
5852         rb_addr = ring->gpu_addr >> 8;
5853         WREG32_SOC15(GC, 0, mmCP_RB0_BASE, rb_addr);
5854         WREG32_SOC15(GC, 0, mmCP_RB0_BASE_HI, upper_32_bits(rb_addr));
5855
5856         WREG32_SOC15(GC, 0, mmCP_RB_ACTIVE, 1);
5857
5858         gfx_v10_0_cp_gfx_set_doorbell(adev, ring);
5859         mutex_unlock(&adev->srbm_mutex);
5860
5861         /* Init gfx ring 1 for pipe 1 */
5862         if (adev->gfx.num_gfx_rings > 1) {
5863                 mutex_lock(&adev->srbm_mutex);
5864                 gfx_v10_0_cp_gfx_switch_pipe(adev, PIPE_ID1);
5865                 /* maximum supported gfx ring is 2 */
5866                 ring = &adev->gfx.gfx_ring[1];
5867                 rb_bufsz = order_base_2(ring->ring_size / 8);
5868                 tmp = REG_SET_FIELD(0, CP_RB1_CNTL, RB_BUFSZ, rb_bufsz);
5869                 tmp = REG_SET_FIELD(tmp, CP_RB1_CNTL, RB_BLKSZ, rb_bufsz - 2);
5870                 WREG32_SOC15(GC, 0, mmCP_RB1_CNTL, tmp);
5871                 /* Initialize the ring buffer's write pointers */
5872                 ring->wptr = 0;
5873                 WREG32_SOC15(GC, 0, mmCP_RB1_WPTR, lower_32_bits(ring->wptr));
5874                 WREG32_SOC15(GC, 0, mmCP_RB1_WPTR_HI, upper_32_bits(ring->wptr));
5875                 /* Set the wb address wether it's enabled or not */
5876                 rptr_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
5877                 WREG32_SOC15(GC, 0, mmCP_RB1_RPTR_ADDR, lower_32_bits(rptr_addr));
5878                 WREG32_SOC15(GC, 0, mmCP_RB1_RPTR_ADDR_HI, upper_32_bits(rptr_addr) &
5879                              CP_RB1_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK);
5880                 wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
5881                 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_LO,
5882                              lower_32_bits(wptr_gpu_addr));
5883                 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI,
5884                              upper_32_bits(wptr_gpu_addr));
5885
5886                 mdelay(1);
5887                 WREG32_SOC15(GC, 0, mmCP_RB1_CNTL, tmp);
5888
5889                 rb_addr = ring->gpu_addr >> 8;
5890                 WREG32_SOC15(GC, 0, mmCP_RB1_BASE, rb_addr);
5891                 WREG32_SOC15(GC, 0, mmCP_RB1_BASE_HI, upper_32_bits(rb_addr));
5892                 WREG32_SOC15(GC, 0, mmCP_RB1_ACTIVE, 1);
5893
5894                 gfx_v10_0_cp_gfx_set_doorbell(adev, ring);
5895                 mutex_unlock(&adev->srbm_mutex);
5896         }
5897         /* Switch to pipe 0 */
5898         mutex_lock(&adev->srbm_mutex);
5899         gfx_v10_0_cp_gfx_switch_pipe(adev, PIPE_ID0);
5900         mutex_unlock(&adev->srbm_mutex);
5901
5902         /* start the ring */
5903         gfx_v10_0_cp_gfx_start(adev);
5904
5905         for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
5906                 ring = &adev->gfx.gfx_ring[i];
5907                 ring->sched.ready = true;
5908         }
5909
5910         return 0;
5911 }
5912
5913 static void gfx_v10_0_cp_compute_enable(struct amdgpu_device *adev, bool enable)
5914 {
5915         if (enable) {
5916                 switch (adev->asic_type) {
5917                 case CHIP_SIENNA_CICHLID:
5918                 case CHIP_NAVY_FLOUNDER:
5919                         WREG32_SOC15(GC, 0, mmCP_MEC_CNTL_Sienna_Cichlid, 0);
5920                         break;
5921                 default:
5922                         WREG32_SOC15(GC, 0, mmCP_MEC_CNTL, 0);
5923                         break;
5924                 }
5925         } else {
5926                 switch (adev->asic_type) {
5927                 case CHIP_SIENNA_CICHLID:
5928                 case CHIP_NAVY_FLOUNDER:
5929                         WREG32_SOC15(GC, 0, mmCP_MEC_CNTL_Sienna_Cichlid,
5930                                      (CP_MEC_CNTL__MEC_ME1_HALT_MASK |
5931                                       CP_MEC_CNTL__MEC_ME2_HALT_MASK));
5932                         break;
5933                 default:
5934                         WREG32_SOC15(GC, 0, mmCP_MEC_CNTL,
5935                                      (CP_MEC_CNTL__MEC_ME1_HALT_MASK |
5936                                       CP_MEC_CNTL__MEC_ME2_HALT_MASK));
5937                         break;
5938                 }
5939                 adev->gfx.kiq.ring.sched.ready = false;
5940         }
5941         udelay(50);
5942 }
5943
5944 static int gfx_v10_0_cp_compute_load_microcode(struct amdgpu_device *adev)
5945 {
5946         const struct gfx_firmware_header_v1_0 *mec_hdr;
5947         const __le32 *fw_data;
5948         unsigned i;
5949         u32 tmp;
5950         u32 usec_timeout = 50000; /* Wait for 50 ms */
5951
5952         if (!adev->gfx.mec_fw)
5953                 return -EINVAL;
5954
5955         gfx_v10_0_cp_compute_enable(adev, false);
5956
5957         mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
5958         amdgpu_ucode_print_gfx_hdr(&mec_hdr->header);
5959
5960         fw_data = (const __le32 *)
5961                 (adev->gfx.mec_fw->data +
5962                  le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes));
5963
5964         /* Trigger an invalidation of the L1 instruction caches */
5965         tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL);
5966         tmp = REG_SET_FIELD(tmp, CP_CPC_IC_OP_CNTL, INVALIDATE_CACHE, 1);
5967         WREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL, tmp);
5968
5969         /* Wait for invalidation complete */
5970         for (i = 0; i < usec_timeout; i++) {
5971                 tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL);
5972                 if (1 == REG_GET_FIELD(tmp, CP_CPC_IC_OP_CNTL,
5973                                        INVALIDATE_CACHE_COMPLETE))
5974                         break;
5975                 udelay(1);
5976         }
5977
5978         if (i >= usec_timeout) {
5979                 dev_err(adev->dev, "failed to invalidate instruction cache\n");
5980                 return -EINVAL;
5981         }
5982
5983         if (amdgpu_emu_mode == 1)
5984                 adev->nbio.funcs->hdp_flush(adev, NULL);
5985
5986         tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_CNTL);
5987         tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0);
5988         tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, EXE_DISABLE, 0);
5989         tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, ADDRESS_CLAMP, 1);
5990         WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_CNTL, tmp);
5991
5992         WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_LO, adev->gfx.mec.mec_fw_gpu_addr &
5993                      0xFFFFF000);
5994         WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_HI,
5995                      upper_32_bits(adev->gfx.mec.mec_fw_gpu_addr));
5996
5997         /* MEC1 */
5998         WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_ADDR, 0);
5999
6000         for (i = 0; i < mec_hdr->jt_size; i++)
6001                 WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_DATA,
6002                              le32_to_cpup(fw_data + mec_hdr->jt_offset + i));
6003
6004         WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_ADDR, adev->gfx.mec_fw_version);
6005
6006         /*
6007          * TODO: Loading MEC2 firmware is only necessary if MEC2 should run
6008          * different microcode than MEC1.
6009          */
6010
6011         return 0;
6012 }
6013
6014 static void gfx_v10_0_kiq_setting(struct amdgpu_ring *ring)
6015 {
6016         uint32_t tmp;
6017         struct amdgpu_device *adev = ring->adev;
6018
6019         /* tell RLC which is KIQ queue */
6020         switch (adev->asic_type) {
6021         case CHIP_SIENNA_CICHLID:
6022         case CHIP_NAVY_FLOUNDER:
6023                 tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS_Sienna_Cichlid);
6024                 tmp &= 0xffffff00;
6025                 tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue);
6026                 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS_Sienna_Cichlid, tmp);
6027                 tmp |= 0x80;
6028                 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS_Sienna_Cichlid, tmp);
6029                 break;
6030         default:
6031                 tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS);
6032                 tmp &= 0xffffff00;
6033                 tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue);
6034                 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS, tmp);
6035                 tmp |= 0x80;
6036                 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS, tmp);
6037                 break;
6038         }
6039 }
6040
6041 static int gfx_v10_0_gfx_mqd_init(struct amdgpu_ring *ring)
6042 {
6043         struct amdgpu_device *adev = ring->adev;
6044         struct v10_gfx_mqd *mqd = ring->mqd_ptr;
6045         uint64_t hqd_gpu_addr, wb_gpu_addr;
6046         uint32_t tmp;
6047         uint32_t rb_bufsz;
6048
6049         /* set up gfx hqd wptr */
6050         mqd->cp_gfx_hqd_wptr = 0;
6051         mqd->cp_gfx_hqd_wptr_hi = 0;
6052
6053         /* set the pointer to the MQD */
6054         mqd->cp_mqd_base_addr = ring->mqd_gpu_addr & 0xfffffffc;
6055         mqd->cp_mqd_base_addr_hi = upper_32_bits(ring->mqd_gpu_addr);
6056
6057         /* set up mqd control */
6058         tmp = RREG32_SOC15(GC, 0, mmCP_GFX_MQD_CONTROL);
6059         tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, VMID, 0);
6060         tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, PRIV_STATE, 1);
6061         tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, CACHE_POLICY, 0);
6062         mqd->cp_gfx_mqd_control = tmp;
6063
6064         /* set up gfx_hqd_vimd with 0x0 to indicate the ring buffer's vmid */
6065         tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_VMID);
6066         tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_VMID, VMID, 0);
6067         mqd->cp_gfx_hqd_vmid = 0;
6068
6069         /* set up default queue priority level
6070          * 0x0 = low priority, 0x1 = high priority */
6071         tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_QUEUE_PRIORITY);
6072         tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_QUEUE_PRIORITY, PRIORITY_LEVEL, 0);
6073         mqd->cp_gfx_hqd_queue_priority = tmp;
6074
6075         /* set up time quantum */
6076         tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_QUANTUM);
6077         tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_QUANTUM, QUANTUM_EN, 1);
6078         mqd->cp_gfx_hqd_quantum = tmp;
6079
6080         /* set up gfx hqd base. this is similar as CP_RB_BASE */
6081         hqd_gpu_addr = ring->gpu_addr >> 8;
6082         mqd->cp_gfx_hqd_base = hqd_gpu_addr;
6083         mqd->cp_gfx_hqd_base_hi = upper_32_bits(hqd_gpu_addr);
6084
6085         /* set up hqd_rptr_addr/_hi, similar as CP_RB_RPTR */
6086         wb_gpu_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
6087         mqd->cp_gfx_hqd_rptr_addr = wb_gpu_addr & 0xfffffffc;
6088         mqd->cp_gfx_hqd_rptr_addr_hi =
6089                 upper_32_bits(wb_gpu_addr) & 0xffff;
6090
6091         /* set up rb_wptr_poll addr */
6092         wb_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
6093         mqd->cp_rb_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc;
6094         mqd->cp_rb_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff;
6095
6096         /* set up the gfx_hqd_control, similar as CP_RB0_CNTL */
6097         rb_bufsz = order_base_2(ring->ring_size / 4) - 1;
6098         tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_CNTL);
6099         tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_BUFSZ, rb_bufsz);
6100         tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_BLKSZ, rb_bufsz - 2);
6101 #ifdef __BIG_ENDIAN
6102         tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, BUF_SWAP, 1);
6103 #endif
6104         mqd->cp_gfx_hqd_cntl = tmp;
6105
6106         /* set up cp_doorbell_control */
6107         tmp = RREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL);
6108         if (ring->use_doorbell) {
6109                 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
6110                                     DOORBELL_OFFSET, ring->doorbell_index);
6111                 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
6112                                     DOORBELL_EN, 1);
6113         } else
6114                 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
6115                                     DOORBELL_EN, 0);
6116         mqd->cp_rb_doorbell_control = tmp;
6117
6118         /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */
6119         ring->wptr = 0;
6120         mqd->cp_gfx_hqd_rptr = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_RPTR);
6121
6122         /* active the queue */
6123         mqd->cp_gfx_hqd_active = 1;
6124
6125         return 0;
6126 }
6127
6128 #ifdef BRING_UP_DEBUG
6129 static int gfx_v10_0_gfx_queue_init_register(struct amdgpu_ring *ring)
6130 {
6131         struct amdgpu_device *adev = ring->adev;
6132         struct v10_gfx_mqd *mqd = ring->mqd_ptr;
6133
6134         /* set mmCP_GFX_HQD_WPTR/_HI to 0 */
6135         WREG32_SOC15(GC, 0, mmCP_GFX_HQD_WPTR, mqd->cp_gfx_hqd_wptr);
6136         WREG32_SOC15(GC, 0, mmCP_GFX_HQD_WPTR_HI, mqd->cp_gfx_hqd_wptr_hi);
6137
6138         /* set GFX_MQD_BASE */
6139         WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR, mqd->cp_mqd_base_addr);
6140         WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR_HI, mqd->cp_mqd_base_addr_hi);
6141
6142         /* set GFX_MQD_CONTROL */
6143         WREG32_SOC15(GC, 0, mmCP_GFX_MQD_CONTROL, mqd->cp_gfx_mqd_control);
6144
6145         /* set GFX_HQD_VMID to 0 */
6146         WREG32_SOC15(GC, 0, mmCP_GFX_HQD_VMID, mqd->cp_gfx_hqd_vmid);
6147
6148         WREG32_SOC15(GC, 0, mmCP_GFX_HQD_QUEUE_PRIORITY,
6149                         mqd->cp_gfx_hqd_queue_priority);
6150         WREG32_SOC15(GC, 0, mmCP_GFX_HQD_QUANTUM, mqd->cp_gfx_hqd_quantum);
6151
6152         /* set GFX_HQD_BASE, similar as CP_RB_BASE */
6153         WREG32_SOC15(GC, 0, mmCP_GFX_HQD_BASE, mqd->cp_gfx_hqd_base);
6154         WREG32_SOC15(GC, 0, mmCP_GFX_HQD_BASE_HI, mqd->cp_gfx_hqd_base_hi);
6155
6156         /* set GFX_HQD_RPTR_ADDR, similar as CP_RB_RPTR */
6157         WREG32_SOC15(GC, 0, mmCP_GFX_HQD_RPTR_ADDR, mqd->cp_gfx_hqd_rptr_addr);
6158         WREG32_SOC15(GC, 0, mmCP_GFX_HQD_RPTR_ADDR_HI, mqd->cp_gfx_hqd_rptr_addr_hi);
6159
6160         /* set GFX_HQD_CNTL, similar as CP_RB_CNTL */
6161         WREG32_SOC15(GC, 0, mmCP_GFX_HQD_CNTL, mqd->cp_gfx_hqd_cntl);
6162
6163         /* set RB_WPTR_POLL_ADDR */
6164         WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_LO, mqd->cp_rb_wptr_poll_addr_lo);
6165         WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI, mqd->cp_rb_wptr_poll_addr_hi);
6166
6167         /* set RB_DOORBELL_CONTROL */
6168         WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL, mqd->cp_rb_doorbell_control);
6169
6170         /* active the queue */
6171         WREG32_SOC15(GC, 0, mmCP_GFX_HQD_ACTIVE, mqd->cp_gfx_hqd_active);
6172
6173         return 0;
6174 }
6175 #endif
6176
6177 static int gfx_v10_0_gfx_init_queue(struct amdgpu_ring *ring)
6178 {
6179         struct amdgpu_device *adev = ring->adev;
6180         struct v10_gfx_mqd *mqd = ring->mqd_ptr;
6181         int mqd_idx = ring - &adev->gfx.gfx_ring[0];
6182
6183         if (!adev->in_gpu_reset && !adev->in_suspend) {
6184                 memset((void *)mqd, 0, sizeof(*mqd));
6185                 mutex_lock(&adev->srbm_mutex);
6186                 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
6187                 gfx_v10_0_gfx_mqd_init(ring);
6188 #ifdef BRING_UP_DEBUG
6189                 gfx_v10_0_gfx_queue_init_register(ring);
6190 #endif
6191                 nv_grbm_select(adev, 0, 0, 0, 0);
6192                 mutex_unlock(&adev->srbm_mutex);
6193                 if (adev->gfx.me.mqd_backup[mqd_idx])
6194                         memcpy(adev->gfx.me.mqd_backup[mqd_idx], mqd, sizeof(*mqd));
6195         } else if (adev->in_gpu_reset) {
6196                 /* reset mqd with the backup copy */
6197                 if (adev->gfx.me.mqd_backup[mqd_idx])
6198                         memcpy(mqd, adev->gfx.me.mqd_backup[mqd_idx], sizeof(*mqd));
6199                 /* reset the ring */
6200                 ring->wptr = 0;
6201                 adev->wb.wb[ring->wptr_offs] = 0;
6202                 amdgpu_ring_clear_ring(ring);
6203 #ifdef BRING_UP_DEBUG
6204                 mutex_lock(&adev->srbm_mutex);
6205                 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
6206                 gfx_v10_0_gfx_queue_init_register(ring);
6207                 nv_grbm_select(adev, 0, 0, 0, 0);
6208                 mutex_unlock(&adev->srbm_mutex);
6209 #endif
6210         } else {
6211                 amdgpu_ring_clear_ring(ring);
6212         }
6213
6214         return 0;
6215 }
6216
6217 #ifndef BRING_UP_DEBUG
6218 static int gfx_v10_0_kiq_enable_kgq(struct amdgpu_device *adev)
6219 {
6220         struct amdgpu_kiq *kiq = &adev->gfx.kiq;
6221         struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring;
6222         int r, i;
6223
6224         if (!kiq->pmf || !kiq->pmf->kiq_map_queues)
6225                 return -EINVAL;
6226
6227         r = amdgpu_ring_alloc(kiq_ring, kiq->pmf->map_queues_size *
6228                                         adev->gfx.num_gfx_rings);
6229         if (r) {
6230                 DRM_ERROR("Failed to lock KIQ (%d).\n", r);
6231                 return r;
6232         }
6233
6234         for (i = 0; i < adev->gfx.num_gfx_rings; i++)
6235                 kiq->pmf->kiq_map_queues(kiq_ring, &adev->gfx.gfx_ring[i]);
6236
6237         return amdgpu_ring_test_helper(kiq_ring);
6238 }
6239 #endif
6240
6241 static int gfx_v10_0_cp_async_gfx_ring_resume(struct amdgpu_device *adev)
6242 {
6243         int r, i;
6244         struct amdgpu_ring *ring;
6245
6246         for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
6247                 ring = &adev->gfx.gfx_ring[i];
6248
6249                 r = amdgpu_bo_reserve(ring->mqd_obj, false);
6250                 if (unlikely(r != 0))
6251                         goto done;
6252
6253                 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr);
6254                 if (!r) {
6255                         r = gfx_v10_0_gfx_init_queue(ring);
6256                         amdgpu_bo_kunmap(ring->mqd_obj);
6257                         ring->mqd_ptr = NULL;
6258                 }
6259                 amdgpu_bo_unreserve(ring->mqd_obj);
6260                 if (r)
6261                         goto done;
6262         }
6263 #ifndef BRING_UP_DEBUG
6264         r = gfx_v10_0_kiq_enable_kgq(adev);
6265         if (r)
6266                 goto done;
6267 #endif
6268         r = gfx_v10_0_cp_gfx_start(adev);
6269         if (r)
6270                 goto done;
6271
6272         for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
6273                 ring = &adev->gfx.gfx_ring[i];
6274                 ring->sched.ready = true;
6275         }
6276 done:
6277         return r;
6278 }
6279
6280 static void gfx_v10_0_compute_mqd_set_priority(struct amdgpu_ring *ring, struct v10_compute_mqd *mqd)
6281 {
6282         struct amdgpu_device *adev = ring->adev;
6283
6284         if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) {
6285                 if (amdgpu_gfx_is_high_priority_compute_queue(adev, ring->queue)) {
6286                         mqd->cp_hqd_pipe_priority = AMDGPU_GFX_PIPE_PRIO_HIGH;
6287                         mqd->cp_hqd_queue_priority =
6288                                 AMDGPU_GFX_QUEUE_PRIORITY_MAXIMUM;
6289                 }
6290         }
6291 }
6292
6293 static int gfx_v10_0_compute_mqd_init(struct amdgpu_ring *ring)
6294 {
6295         struct amdgpu_device *adev = ring->adev;
6296         struct v10_compute_mqd *mqd = ring->mqd_ptr;
6297         uint64_t hqd_gpu_addr, wb_gpu_addr, eop_base_addr;
6298         uint32_t tmp;
6299
6300         mqd->header = 0xC0310800;
6301         mqd->compute_pipelinestat_enable = 0x00000001;
6302         mqd->compute_static_thread_mgmt_se0 = 0xffffffff;
6303         mqd->compute_static_thread_mgmt_se1 = 0xffffffff;
6304         mqd->compute_static_thread_mgmt_se2 = 0xffffffff;
6305         mqd->compute_static_thread_mgmt_se3 = 0xffffffff;
6306         mqd->compute_misc_reserved = 0x00000003;
6307
6308         eop_base_addr = ring->eop_gpu_addr >> 8;
6309         mqd->cp_hqd_eop_base_addr_lo = eop_base_addr;
6310         mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr);
6311
6312         /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */
6313         tmp = RREG32_SOC15(GC, 0, mmCP_HQD_EOP_CONTROL);
6314         tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE,
6315                         (order_base_2(GFX10_MEC_HPD_SIZE / 4) - 1));
6316
6317         mqd->cp_hqd_eop_control = tmp;
6318
6319         /* enable doorbell? */
6320         tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL);
6321
6322         if (ring->use_doorbell) {
6323                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
6324                                     DOORBELL_OFFSET, ring->doorbell_index);
6325                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
6326                                     DOORBELL_EN, 1);
6327                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
6328                                     DOORBELL_SOURCE, 0);
6329                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
6330                                     DOORBELL_HIT, 0);
6331         } else {
6332                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
6333                                     DOORBELL_EN, 0);
6334         }
6335
6336         mqd->cp_hqd_pq_doorbell_control = tmp;
6337
6338         /* disable the queue if it's active */
6339         ring->wptr = 0;
6340         mqd->cp_hqd_dequeue_request = 0;
6341         mqd->cp_hqd_pq_rptr = 0;
6342         mqd->cp_hqd_pq_wptr_lo = 0;
6343         mqd->cp_hqd_pq_wptr_hi = 0;
6344
6345         /* set the pointer to the MQD */
6346         mqd->cp_mqd_base_addr_lo = ring->mqd_gpu_addr & 0xfffffffc;
6347         mqd->cp_mqd_base_addr_hi = upper_32_bits(ring->mqd_gpu_addr);
6348
6349         /* set MQD vmid to 0 */
6350         tmp = RREG32_SOC15(GC, 0, mmCP_MQD_CONTROL);
6351         tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0);
6352         mqd->cp_mqd_control = tmp;
6353
6354         /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */
6355         hqd_gpu_addr = ring->gpu_addr >> 8;
6356         mqd->cp_hqd_pq_base_lo = hqd_gpu_addr;
6357         mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr);
6358
6359         /* set up the HQD, this is similar to CP_RB0_CNTL */
6360         tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_CONTROL);
6361         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE,
6362                             (order_base_2(ring->ring_size / 4) - 1));
6363         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE,
6364                             ((order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1) << 8));
6365 #ifdef __BIG_ENDIAN
6366         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ENDIAN_SWAP, 1);
6367 #endif
6368         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 0);
6369         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, TUNNEL_DISPATCH, 0);
6370         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1);
6371         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1);
6372         mqd->cp_hqd_pq_control = tmp;
6373
6374         /* set the wb address whether it's enabled or not */
6375         wb_gpu_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
6376         mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc;
6377         mqd->cp_hqd_pq_rptr_report_addr_hi =
6378                 upper_32_bits(wb_gpu_addr) & 0xffff;
6379
6380         /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */
6381         wb_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
6382         mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc;
6383         mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff;
6384
6385         tmp = 0;
6386         /* enable the doorbell if requested */
6387         if (ring->use_doorbell) {
6388                 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL);
6389                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
6390                                 DOORBELL_OFFSET, ring->doorbell_index);
6391
6392                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
6393                                     DOORBELL_EN, 1);
6394                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
6395                                     DOORBELL_SOURCE, 0);
6396                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
6397                                     DOORBELL_HIT, 0);
6398         }
6399
6400         mqd->cp_hqd_pq_doorbell_control = tmp;
6401
6402         /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */
6403         ring->wptr = 0;
6404         mqd->cp_hqd_pq_rptr = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR);
6405
6406         /* set the vmid for the queue */
6407         mqd->cp_hqd_vmid = 0;
6408
6409         tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PERSISTENT_STATE);
6410         tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, PRELOAD_SIZE, 0x53);
6411         mqd->cp_hqd_persistent_state = tmp;
6412
6413         /* set MIN_IB_AVAIL_SIZE */
6414         tmp = RREG32_SOC15(GC, 0, mmCP_HQD_IB_CONTROL);
6415         tmp = REG_SET_FIELD(tmp, CP_HQD_IB_CONTROL, MIN_IB_AVAIL_SIZE, 3);
6416         mqd->cp_hqd_ib_control = tmp;
6417
6418         /* set static priority for a compute queue/ring */
6419         gfx_v10_0_compute_mqd_set_priority(ring, mqd);
6420
6421         /* map_queues packet doesn't need activate the queue,
6422          * so only kiq need set this field.
6423          */
6424         if (ring->funcs->type == AMDGPU_RING_TYPE_KIQ)
6425                 mqd->cp_hqd_active = 1;
6426
6427         return 0;
6428 }
6429
6430 static int gfx_v10_0_kiq_init_register(struct amdgpu_ring *ring)
6431 {
6432         struct amdgpu_device *adev = ring->adev;
6433         struct v10_compute_mqd *mqd = ring->mqd_ptr;
6434         int j;
6435
6436         /* disable wptr polling */
6437         WREG32_FIELD15(GC, 0, CP_PQ_WPTR_POLL_CNTL, EN, 0);
6438
6439         /* write the EOP addr */
6440         WREG32_SOC15(GC, 0, mmCP_HQD_EOP_BASE_ADDR,
6441                mqd->cp_hqd_eop_base_addr_lo);
6442         WREG32_SOC15(GC, 0, mmCP_HQD_EOP_BASE_ADDR_HI,
6443                mqd->cp_hqd_eop_base_addr_hi);
6444
6445         /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */
6446         WREG32_SOC15(GC, 0, mmCP_HQD_EOP_CONTROL,
6447                mqd->cp_hqd_eop_control);
6448
6449         /* enable doorbell? */
6450         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL,
6451                mqd->cp_hqd_pq_doorbell_control);
6452
6453         /* disable the queue if it's active */
6454         if (RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1) {
6455                 WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST, 1);
6456                 for (j = 0; j < adev->usec_timeout; j++) {
6457                         if (!(RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1))
6458                                 break;
6459                         udelay(1);
6460                 }
6461                 WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST,
6462                        mqd->cp_hqd_dequeue_request);
6463                 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR,
6464                        mqd->cp_hqd_pq_rptr);
6465                 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_LO,
6466                        mqd->cp_hqd_pq_wptr_lo);
6467                 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_HI,
6468                        mqd->cp_hqd_pq_wptr_hi);
6469         }
6470
6471         /* set the pointer to the MQD */
6472         WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR,
6473                mqd->cp_mqd_base_addr_lo);
6474         WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR_HI,
6475                mqd->cp_mqd_base_addr_hi);
6476
6477         /* set MQD vmid to 0 */
6478         WREG32_SOC15(GC, 0, mmCP_MQD_CONTROL,
6479                mqd->cp_mqd_control);
6480
6481         /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */
6482         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_BASE,
6483                mqd->cp_hqd_pq_base_lo);
6484         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_BASE_HI,
6485                mqd->cp_hqd_pq_base_hi);
6486
6487         /* set up the HQD, this is similar to CP_RB0_CNTL */
6488         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_CONTROL,
6489                mqd->cp_hqd_pq_control);
6490
6491         /* set the wb address whether it's enabled or not */
6492         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR_REPORT_ADDR,
6493                 mqd->cp_hqd_pq_rptr_report_addr_lo);
6494         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI,
6495                 mqd->cp_hqd_pq_rptr_report_addr_hi);
6496
6497         /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */
6498         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR,
6499                mqd->cp_hqd_pq_wptr_poll_addr_lo);
6500         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR_HI,
6501                mqd->cp_hqd_pq_wptr_poll_addr_hi);
6502
6503         /* enable the doorbell if requested */
6504         if (ring->use_doorbell) {
6505                 WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_LOWER,
6506                         (adev->doorbell_index.kiq * 2) << 2);
6507                 WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_UPPER,
6508                         (adev->doorbell_index.userqueue_end * 2) << 2);
6509         }
6510
6511         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL,
6512                mqd->cp_hqd_pq_doorbell_control);
6513
6514         /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */
6515         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_LO,
6516                mqd->cp_hqd_pq_wptr_lo);
6517         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_HI,
6518                mqd->cp_hqd_pq_wptr_hi);
6519
6520         /* set the vmid for the queue */
6521         WREG32_SOC15(GC, 0, mmCP_HQD_VMID, mqd->cp_hqd_vmid);
6522
6523         WREG32_SOC15(GC, 0, mmCP_HQD_PERSISTENT_STATE,
6524                mqd->cp_hqd_persistent_state);
6525
6526         /* activate the queue */
6527         WREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE,
6528                mqd->cp_hqd_active);
6529
6530         if (ring->use_doorbell)
6531                 WREG32_FIELD15(GC, 0, CP_PQ_STATUS, DOORBELL_ENABLE, 1);
6532
6533         return 0;
6534 }
6535
6536 static int gfx_v10_0_kiq_init_queue(struct amdgpu_ring *ring)
6537 {
6538         struct amdgpu_device *adev = ring->adev;
6539         struct v10_compute_mqd *mqd = ring->mqd_ptr;
6540         int mqd_idx = AMDGPU_MAX_COMPUTE_RINGS;
6541
6542         gfx_v10_0_kiq_setting(ring);
6543
6544         if (adev->in_gpu_reset) { /* for GPU_RESET case */
6545                 /* reset MQD to a clean status */
6546                 if (adev->gfx.mec.mqd_backup[mqd_idx])
6547                         memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(*mqd));
6548
6549                 /* reset ring buffer */
6550                 ring->wptr = 0;
6551                 amdgpu_ring_clear_ring(ring);
6552
6553                 mutex_lock(&adev->srbm_mutex);
6554                 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
6555                 gfx_v10_0_kiq_init_register(ring);
6556                 nv_grbm_select(adev, 0, 0, 0, 0);
6557                 mutex_unlock(&adev->srbm_mutex);
6558         } else {
6559                 memset((void *)mqd, 0, sizeof(*mqd));
6560                 mutex_lock(&adev->srbm_mutex);
6561                 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
6562                 gfx_v10_0_compute_mqd_init(ring);
6563                 gfx_v10_0_kiq_init_register(ring);
6564                 nv_grbm_select(adev, 0, 0, 0, 0);
6565                 mutex_unlock(&adev->srbm_mutex);
6566
6567                 if (adev->gfx.mec.mqd_backup[mqd_idx])
6568                         memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(*mqd));
6569         }
6570
6571         return 0;
6572 }
6573
6574 static int gfx_v10_0_kcq_init_queue(struct amdgpu_ring *ring)
6575 {
6576         struct amdgpu_device *adev = ring->adev;
6577         struct v10_compute_mqd *mqd = ring->mqd_ptr;
6578         int mqd_idx = ring - &adev->gfx.compute_ring[0];
6579
6580         if (!adev->in_gpu_reset && !adev->in_suspend) {
6581                 memset((void *)mqd, 0, sizeof(*mqd));
6582                 mutex_lock(&adev->srbm_mutex);
6583                 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
6584                 gfx_v10_0_compute_mqd_init(ring);
6585                 nv_grbm_select(adev, 0, 0, 0, 0);
6586                 mutex_unlock(&adev->srbm_mutex);
6587
6588                 if (adev->gfx.mec.mqd_backup[mqd_idx])
6589                         memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(*mqd));
6590         } else if (adev->in_gpu_reset) { /* for GPU_RESET case */
6591                 /* reset MQD to a clean status */
6592                 if (adev->gfx.mec.mqd_backup[mqd_idx])
6593                         memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(*mqd));
6594
6595                 /* reset ring buffer */
6596                 ring->wptr = 0;
6597                 atomic64_set((atomic64_t *)&adev->wb.wb[ring->wptr_offs], 0);
6598                 amdgpu_ring_clear_ring(ring);
6599         } else {
6600                 amdgpu_ring_clear_ring(ring);
6601         }
6602
6603         return 0;
6604 }
6605
6606 static int gfx_v10_0_kiq_resume(struct amdgpu_device *adev)
6607 {
6608         struct amdgpu_ring *ring;
6609         int r;
6610
6611         ring = &adev->gfx.kiq.ring;
6612
6613         r = amdgpu_bo_reserve(ring->mqd_obj, false);
6614         if (unlikely(r != 0))
6615                 return r;
6616
6617         r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr);
6618         if (unlikely(r != 0))
6619                 return r;
6620
6621         gfx_v10_0_kiq_init_queue(ring);
6622         amdgpu_bo_kunmap(ring->mqd_obj);
6623         ring->mqd_ptr = NULL;
6624         amdgpu_bo_unreserve(ring->mqd_obj);
6625         ring->sched.ready = true;
6626         return 0;
6627 }
6628
6629 static int gfx_v10_0_kcq_resume(struct amdgpu_device *adev)
6630 {
6631         struct amdgpu_ring *ring = NULL;
6632         int r = 0, i;
6633
6634         gfx_v10_0_cp_compute_enable(adev, true);
6635
6636         for (i = 0; i < adev->gfx.num_compute_rings; i++) {
6637                 ring = &adev->gfx.compute_ring[i];
6638
6639                 r = amdgpu_bo_reserve(ring->mqd_obj, false);
6640                 if (unlikely(r != 0))
6641                         goto done;
6642                 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr);
6643                 if (!r) {
6644                         r = gfx_v10_0_kcq_init_queue(ring);
6645                         amdgpu_bo_kunmap(ring->mqd_obj);
6646                         ring->mqd_ptr = NULL;
6647                 }
6648                 amdgpu_bo_unreserve(ring->mqd_obj);
6649                 if (r)
6650                         goto done;
6651         }
6652
6653         r = amdgpu_gfx_enable_kcq(adev);
6654 done:
6655         return r;
6656 }
6657
6658 static int gfx_v10_0_cp_resume(struct amdgpu_device *adev)
6659 {
6660         int r, i;
6661         struct amdgpu_ring *ring;
6662
6663         if (!(adev->flags & AMD_IS_APU))
6664                 gfx_v10_0_enable_gui_idle_interrupt(adev, false);
6665
6666         if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
6667                 /* legacy firmware loading */
6668                 r = gfx_v10_0_cp_gfx_load_microcode(adev);
6669                 if (r)
6670                         return r;
6671
6672                 r = gfx_v10_0_cp_compute_load_microcode(adev);
6673                 if (r)
6674                         return r;
6675         }
6676
6677         r = gfx_v10_0_kiq_resume(adev);
6678         if (r)
6679                 return r;
6680
6681         r = gfx_v10_0_kcq_resume(adev);
6682         if (r)
6683                 return r;
6684
6685         if (!amdgpu_async_gfx_ring) {
6686                 r = gfx_v10_0_cp_gfx_resume(adev);
6687                 if (r)
6688                         return r;
6689         } else {
6690                 r = gfx_v10_0_cp_async_gfx_ring_resume(adev);
6691                 if (r)
6692                         return r;
6693         }
6694
6695         for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
6696                 ring = &adev->gfx.gfx_ring[i];
6697                 r = amdgpu_ring_test_helper(ring);
6698                 if (r)
6699                         return r;
6700         }
6701
6702         for (i = 0; i < adev->gfx.num_compute_rings; i++) {
6703                 ring = &adev->gfx.compute_ring[i];
6704                 r = amdgpu_ring_test_helper(ring);
6705                 if (r)
6706                         return r;
6707         }
6708
6709         return 0;
6710 }
6711
6712 static void gfx_v10_0_cp_enable(struct amdgpu_device *adev, bool enable)
6713 {
6714         gfx_v10_0_cp_gfx_enable(adev, enable);
6715         gfx_v10_0_cp_compute_enable(adev, enable);
6716 }
6717
6718 static bool gfx_v10_0_check_grbm_cam_remapping(struct amdgpu_device *adev)
6719 {
6720         uint32_t data, pattern = 0xDEADBEEF;
6721
6722         /* check if mmVGT_ESGS_RING_SIZE_UMD
6723          * has been remapped to mmVGT_ESGS_RING_SIZE */
6724         switch (adev->asic_type) {
6725         case CHIP_SIENNA_CICHLID:
6726         case CHIP_NAVY_FLOUNDER:
6727                 data = RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid);
6728                 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid, 0);
6729                 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_UMD, pattern);
6730
6731                 if (RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid) == pattern) {
6732                         WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_UMD , data);
6733                         return true;
6734                 } else {
6735                         WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid, data);
6736                         return false;
6737                 }
6738                 break;
6739         default:
6740                 data = RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE);
6741                 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE, 0);
6742                 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_UMD, pattern);
6743
6744                 if (RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE) == pattern) {
6745                         WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_UMD, data);
6746                         return true;
6747                 } else {
6748                         WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE, data);
6749                         return false;
6750                 }
6751                 break;
6752         }
6753 }
6754
6755 static void gfx_v10_0_setup_grbm_cam_remapping(struct amdgpu_device *adev)
6756 {
6757         uint32_t data;
6758
6759         /* initialize cam_index to 0
6760          * index will auto-inc after each data writting */
6761         WREG32_SOC15(GC, 0, mmGRBM_CAM_INDEX, 0);
6762
6763         switch (adev->asic_type) {
6764         case CHIP_SIENNA_CICHLID:
6765         case CHIP_NAVY_FLOUNDER:
6766                 /* mmVGT_TF_RING_SIZE_UMD -> mmVGT_TF_RING_SIZE */
6767                 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE_UMD) <<
6768                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
6769                        (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE_Sienna_Cichlid) <<
6770                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
6771                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
6772                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
6773
6774                 /* mmVGT_TF_MEMORY_BASE_UMD -> mmVGT_TF_MEMORY_BASE */
6775                 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_UMD) <<
6776                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
6777                        (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_Sienna_Cichlid) <<
6778                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
6779                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
6780                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
6781
6782                 /* mmVGT_TF_MEMORY_BASE_HI_UMD -> mmVGT_TF_MEMORY_BASE_HI */
6783                 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI_UMD) <<
6784                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
6785                        (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI_Sienna_Cichlid) <<
6786                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
6787                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
6788                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
6789
6790                 /* mmVGT_HS_OFFCHIP_PARAM_UMD -> mmVGT_HS_OFFCHIP_PARAM */
6791                 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM_UMD) <<
6792                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
6793                        (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM_Sienna_Cichlid) <<
6794                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
6795                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
6796                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
6797
6798                 /* mmVGT_ESGS_RING_SIZE_UMD -> mmVGT_ESGS_RING_SIZE */
6799                 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE_UMD) <<
6800                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
6801                        (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid) <<
6802                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
6803                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
6804                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
6805
6806                 /* mmVGT_GSVS_RING_SIZE_UMD -> mmVGT_GSVS_RING_SIZE */
6807                 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE_UMD) <<
6808                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
6809                        (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE_Sienna_Cichlid) <<
6810                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
6811                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
6812                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
6813
6814                 /* mmSPI_CONFIG_CNTL_REMAP -> mmSPI_CONFIG_CNTL */
6815                 data = (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL_REMAP) <<
6816                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
6817                        (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL_Sienna_Cichlid) <<
6818                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
6819                 break;
6820         default:
6821                 /* mmVGT_TF_RING_SIZE_UMD -> mmVGT_TF_RING_SIZE */
6822                 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE_UMD) <<
6823                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
6824                        (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE) <<
6825                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
6826                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
6827                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
6828
6829                 /* mmVGT_TF_MEMORY_BASE_UMD -> mmVGT_TF_MEMORY_BASE */
6830                 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_UMD) <<
6831                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
6832                        (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE) <<
6833                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
6834                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
6835                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
6836
6837                 /* mmVGT_TF_MEMORY_BASE_HI_UMD -> mmVGT_TF_MEMORY_BASE_HI */
6838                 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI_UMD) <<
6839                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
6840                        (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI) <<
6841                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
6842                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
6843                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
6844
6845                 /* mmVGT_HS_OFFCHIP_PARAM_UMD -> mmVGT_HS_OFFCHIP_PARAM */
6846                 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM_UMD) <<
6847                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
6848                        (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM) <<
6849                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
6850                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
6851                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
6852
6853                 /* mmVGT_ESGS_RING_SIZE_UMD -> mmVGT_ESGS_RING_SIZE */
6854                 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE_UMD) <<
6855                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
6856                        (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE) <<
6857                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
6858                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
6859                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
6860
6861                 /* mmVGT_GSVS_RING_SIZE_UMD -> mmVGT_GSVS_RING_SIZE */
6862                 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE_UMD) <<
6863                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
6864                        (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE) <<
6865                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
6866                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
6867                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
6868
6869                 /* mmSPI_CONFIG_CNTL_REMAP -> mmSPI_CONFIG_CNTL */
6870                 data = (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL_REMAP) <<
6871                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
6872                        (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL) <<
6873                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
6874                 break;
6875         }
6876
6877         WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
6878         WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
6879 }
6880
6881 static int gfx_v10_0_hw_init(void *handle)
6882 {
6883         int r;
6884         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
6885
6886         if (!amdgpu_emu_mode)
6887                 gfx_v10_0_init_golden_registers(adev);
6888
6889         if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
6890                 /**
6891                  * For gfx 10, rlc firmware loading relies on smu firmware is
6892                  * loaded firstly, so in direct type, it has to load smc ucode
6893                  * here before rlc.
6894                  */
6895                 if (adev->smu.ppt_funcs != NULL) {
6896                         r = smu_load_microcode(&adev->smu);
6897                         if (r)
6898                                 return r;
6899
6900                         r = smu_check_fw_status(&adev->smu);
6901                         if (r) {
6902                                 pr_err("SMC firmware status is not correct\n");
6903                                 return r;
6904                         }
6905                 }
6906         }
6907
6908         /* if GRBM CAM not remapped, set up the remapping */
6909         if (!gfx_v10_0_check_grbm_cam_remapping(adev))
6910                 gfx_v10_0_setup_grbm_cam_remapping(adev);
6911
6912         gfx_v10_0_constants_init(adev);
6913
6914         r = gfx_v10_0_rlc_resume(adev);
6915         if (r)
6916                 return r;
6917
6918         /*
6919          * init golden registers and rlc resume may override some registers,
6920          * reconfig them here
6921          */
6922         gfx_v10_0_tcp_harvest(adev);
6923
6924         r = gfx_v10_0_cp_resume(adev);
6925         if (r)
6926                 return r;
6927
6928         return r;
6929 }
6930
6931 #ifndef BRING_UP_DEBUG
6932 static int gfx_v10_0_kiq_disable_kgq(struct amdgpu_device *adev)
6933 {
6934         struct amdgpu_kiq *kiq = &adev->gfx.kiq;
6935         struct amdgpu_ring *kiq_ring = &kiq->ring;
6936         int i;
6937
6938         if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues)
6939                 return -EINVAL;
6940
6941         if (amdgpu_ring_alloc(kiq_ring, kiq->pmf->unmap_queues_size *
6942                                         adev->gfx.num_gfx_rings))
6943                 return -ENOMEM;
6944
6945         for (i = 0; i < adev->gfx.num_gfx_rings; i++)
6946                 kiq->pmf->kiq_unmap_queues(kiq_ring, &adev->gfx.gfx_ring[i],
6947                                            PREEMPT_QUEUES, 0, 0);
6948
6949         return amdgpu_ring_test_helper(kiq_ring);
6950 }
6951 #endif
6952
6953 static int gfx_v10_0_hw_fini(void *handle)
6954 {
6955         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
6956         int r;
6957         uint32_t tmp;
6958
6959         amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0);
6960         amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0);
6961 #ifndef BRING_UP_DEBUG
6962         if (amdgpu_async_gfx_ring) {
6963                 r = gfx_v10_0_kiq_disable_kgq(adev);
6964                 if (r)
6965                         DRM_ERROR("KGQ disable failed\n");
6966         }
6967 #endif
6968         if (amdgpu_gfx_disable_kcq(adev))
6969                 DRM_ERROR("KCQ disable failed\n");
6970         if (amdgpu_sriov_vf(adev)) {
6971                 gfx_v10_0_cp_gfx_enable(adev, false);
6972                 /* Program KIQ position of RLC_CP_SCHEDULERS during destroy */
6973                 tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS);
6974                 tmp &= 0xffffff00;
6975                 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS, tmp);
6976
6977                 return 0;
6978         }
6979         gfx_v10_0_cp_enable(adev, false);
6980         gfx_v10_0_enable_gui_idle_interrupt(adev, false);
6981
6982         return 0;
6983 }
6984
6985 static int gfx_v10_0_suspend(void *handle)
6986 {
6987         return gfx_v10_0_hw_fini(handle);
6988 }
6989
6990 static int gfx_v10_0_resume(void *handle)
6991 {
6992         return gfx_v10_0_hw_init(handle);
6993 }
6994
6995 static bool gfx_v10_0_is_idle(void *handle)
6996 {
6997         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
6998
6999         if (REG_GET_FIELD(RREG32_SOC15(GC, 0, mmGRBM_STATUS),
7000                                 GRBM_STATUS, GUI_ACTIVE))
7001                 return false;
7002         else
7003                 return true;
7004 }
7005
7006 static int gfx_v10_0_wait_for_idle(void *handle)
7007 {
7008         unsigned i;
7009         u32 tmp;
7010         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7011
7012         for (i = 0; i < adev->usec_timeout; i++) {
7013                 /* read MC_STATUS */
7014                 tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS) &
7015                         GRBM_STATUS__GUI_ACTIVE_MASK;
7016
7017                 if (!REG_GET_FIELD(tmp, GRBM_STATUS, GUI_ACTIVE))
7018                         return 0;
7019                 udelay(1);
7020         }
7021         return -ETIMEDOUT;
7022 }
7023
7024 static int gfx_v10_0_soft_reset(void *handle)
7025 {
7026         u32 grbm_soft_reset = 0;
7027         u32 tmp;
7028         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7029
7030         /* GRBM_STATUS */
7031         tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS);
7032         if (tmp & (GRBM_STATUS__PA_BUSY_MASK | GRBM_STATUS__SC_BUSY_MASK |
7033                    GRBM_STATUS__BCI_BUSY_MASK | GRBM_STATUS__SX_BUSY_MASK |
7034                    GRBM_STATUS__TA_BUSY_MASK | GRBM_STATUS__DB_BUSY_MASK |
7035                    GRBM_STATUS__CB_BUSY_MASK | GRBM_STATUS__GDS_BUSY_MASK |
7036                    GRBM_STATUS__SPI_BUSY_MASK | GRBM_STATUS__GE_BUSY_NO_DMA_MASK
7037                    | GRBM_STATUS__BCI_BUSY_MASK)) {
7038                 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
7039                                                 GRBM_SOFT_RESET, SOFT_RESET_CP,
7040                                                 1);
7041                 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
7042                                                 GRBM_SOFT_RESET, SOFT_RESET_GFX,
7043                                                 1);
7044         }
7045
7046         if (tmp & (GRBM_STATUS__CP_BUSY_MASK | GRBM_STATUS__CP_COHERENCY_BUSY_MASK)) {
7047                 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
7048                                                 GRBM_SOFT_RESET, SOFT_RESET_CP,
7049                                                 1);
7050         }
7051
7052         /* GRBM_STATUS2 */
7053         tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS2);
7054         switch (adev->asic_type) {
7055         case CHIP_SIENNA_CICHLID:
7056         case CHIP_NAVY_FLOUNDER:
7057                 if (REG_GET_FIELD(tmp, GRBM_STATUS2, RLC_BUSY_Sienna_Cichlid))
7058                         grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
7059                                                         GRBM_SOFT_RESET,
7060                                                         SOFT_RESET_RLC,
7061                                                         1);
7062                 break;
7063         default:
7064                 if (REG_GET_FIELD(tmp, GRBM_STATUS2, RLC_BUSY))
7065                         grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
7066                                                         GRBM_SOFT_RESET,
7067                                                         SOFT_RESET_RLC,
7068                                                         1);
7069                 break;
7070         }
7071
7072         if (grbm_soft_reset) {
7073                 /* stop the rlc */
7074                 gfx_v10_0_rlc_stop(adev);
7075
7076                 /* Disable GFX parsing/prefetching */
7077                 gfx_v10_0_cp_gfx_enable(adev, false);
7078
7079                 /* Disable MEC parsing/prefetching */
7080                 gfx_v10_0_cp_compute_enable(adev, false);
7081
7082                 if (grbm_soft_reset) {
7083                         tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);
7084                         tmp |= grbm_soft_reset;
7085                         dev_info(adev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp);
7086                         WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp);
7087                         tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);
7088
7089                         udelay(50);
7090
7091                         tmp &= ~grbm_soft_reset;
7092                         WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp);
7093                         tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);
7094                 }
7095
7096                 /* Wait a little for things to settle down */
7097                 udelay(50);
7098         }
7099         return 0;
7100 }
7101
7102 static uint64_t gfx_v10_0_get_gpu_clock_counter(struct amdgpu_device *adev)
7103 {
7104         uint64_t clock;
7105
7106         amdgpu_gfx_off_ctrl(adev, false);
7107         mutex_lock(&adev->gfx.gpu_clock_mutex);
7108         clock = (uint64_t)RREG32_SOC15(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER) |
7109                 ((uint64_t)RREG32_SOC15(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER) << 32ULL);
7110         mutex_unlock(&adev->gfx.gpu_clock_mutex);
7111         amdgpu_gfx_off_ctrl(adev, true);
7112         return clock;
7113 }
7114
7115 static void gfx_v10_0_ring_emit_gds_switch(struct amdgpu_ring *ring,
7116                                            uint32_t vmid,
7117                                            uint32_t gds_base, uint32_t gds_size,
7118                                            uint32_t gws_base, uint32_t gws_size,
7119                                            uint32_t oa_base, uint32_t oa_size)
7120 {
7121         struct amdgpu_device *adev = ring->adev;
7122
7123         /* GDS Base */
7124         gfx_v10_0_write_data_to_reg(ring, 0, false,
7125                                     SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_BASE) + 2 * vmid,
7126                                     gds_base);
7127
7128         /* GDS Size */
7129         gfx_v10_0_write_data_to_reg(ring, 0, false,
7130                                     SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_SIZE) + 2 * vmid,
7131                                     gds_size);
7132
7133         /* GWS */
7134         gfx_v10_0_write_data_to_reg(ring, 0, false,
7135                                     SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID0) + vmid,
7136                                     gws_size << GDS_GWS_VMID0__SIZE__SHIFT | gws_base);
7137
7138         /* OA */
7139         gfx_v10_0_write_data_to_reg(ring, 0, false,
7140                                     SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID0) + vmid,
7141                                     (1 << (oa_size + oa_base)) - (1 << oa_base));
7142 }
7143
7144 static int gfx_v10_0_early_init(void *handle)
7145 {
7146         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7147
7148         switch (adev->asic_type) {
7149         case CHIP_NAVI10:
7150         case CHIP_NAVI14:
7151         case CHIP_NAVI12:
7152                 adev->gfx.num_gfx_rings = GFX10_NUM_GFX_RINGS_NV1X;
7153                 break;
7154         case CHIP_SIENNA_CICHLID:
7155         case CHIP_NAVY_FLOUNDER:
7156                 adev->gfx.num_gfx_rings = GFX10_NUM_GFX_RINGS_Sienna_Cichlid;
7157                 break;
7158         default:
7159                 break;
7160         }
7161
7162         adev->gfx.num_compute_rings = AMDGPU_MAX_COMPUTE_RINGS;
7163
7164         gfx_v10_0_set_kiq_pm4_funcs(adev);
7165         gfx_v10_0_set_ring_funcs(adev);
7166         gfx_v10_0_set_irq_funcs(adev);
7167         gfx_v10_0_set_gds_init(adev);
7168         gfx_v10_0_set_rlc_funcs(adev);
7169
7170         return 0;
7171 }
7172
7173 static int gfx_v10_0_late_init(void *handle)
7174 {
7175         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7176         int r;
7177
7178         r = amdgpu_irq_get(adev, &adev->gfx.priv_reg_irq, 0);
7179         if (r)
7180                 return r;
7181
7182         r = amdgpu_irq_get(adev, &adev->gfx.priv_inst_irq, 0);
7183         if (r)
7184                 return r;
7185
7186         return 0;
7187 }
7188
7189 static bool gfx_v10_0_is_rlc_enabled(struct amdgpu_device *adev)
7190 {
7191         uint32_t rlc_cntl;
7192
7193         /* if RLC is not enabled, do nothing */
7194         rlc_cntl = RREG32_SOC15(GC, 0, mmRLC_CNTL);
7195         return (REG_GET_FIELD(rlc_cntl, RLC_CNTL, RLC_ENABLE_F32)) ? true : false;
7196 }
7197
7198 static void gfx_v10_0_set_safe_mode(struct amdgpu_device *adev)
7199 {
7200         uint32_t data;
7201         unsigned i;
7202
7203         data = RLC_SAFE_MODE__CMD_MASK;
7204         data |= (1 << RLC_SAFE_MODE__MESSAGE__SHIFT);
7205
7206         switch (adev->asic_type) {
7207         case CHIP_SIENNA_CICHLID:
7208         case CHIP_NAVY_FLOUNDER:
7209                 WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE_Sienna_Cichlid, data);
7210
7211                 /* wait for RLC_SAFE_MODE */
7212                 for (i = 0; i < adev->usec_timeout; i++) {
7213                         if (!REG_GET_FIELD(RREG32_SOC15(GC, 0, mmRLC_SAFE_MODE_Sienna_Cichlid),
7214                                            RLC_SAFE_MODE, CMD))
7215                                 break;
7216                         udelay(1);
7217                 }
7218                 break;
7219         default:
7220                 WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE, data);
7221
7222                 /* wait for RLC_SAFE_MODE */
7223                 for (i = 0; i < adev->usec_timeout; i++) {
7224                         if (!REG_GET_FIELD(RREG32_SOC15(GC, 0, mmRLC_SAFE_MODE),
7225                                            RLC_SAFE_MODE, CMD))
7226                                 break;
7227                         udelay(1);
7228                 }
7229                 break;
7230         }
7231 }
7232
7233 static void gfx_v10_0_unset_safe_mode(struct amdgpu_device *adev)
7234 {
7235         uint32_t data;
7236
7237         data = RLC_SAFE_MODE__CMD_MASK;
7238         switch (adev->asic_type) {
7239         case CHIP_SIENNA_CICHLID:
7240         case CHIP_NAVY_FLOUNDER:
7241                 WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE_Sienna_Cichlid, data);
7242                 break;
7243         default:
7244                 WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE, data);
7245                 break;
7246         }
7247 }
7248
7249 static void gfx_v10_0_update_medium_grain_clock_gating(struct amdgpu_device *adev,
7250                                                       bool enable)
7251 {
7252         uint32_t data, def;
7253
7254         /* It is disabled by HW by default */
7255         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) {
7256                 /* 0 - Disable some blocks' MGCG */
7257                 WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, 0xe0000000);
7258                 WREG32_SOC15(GC, 0, mmCGTT_WD_CLK_CTRL, 0xff000000);
7259                 WREG32_SOC15(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xff000000);
7260                 WREG32_SOC15(GC, 0, mmCGTT_IA_CLK_CTRL, 0xff000000);
7261
7262                 /* 1 - RLC_CGTT_MGCG_OVERRIDE */
7263                 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
7264                 data &= ~(RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK |
7265                           RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK |
7266                           RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK |
7267                           RLC_CGTT_MGCG_OVERRIDE__ENABLE_CGTS_LEGACY_MASK);
7268
7269                 if (def != data)
7270                         WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
7271
7272                 /* MGLS is a global flag to control all MGLS in GFX */
7273                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGLS) {
7274                         /* 2 - RLC memory Light sleep */
7275                         if (adev->cg_flags & AMD_CG_SUPPORT_GFX_RLC_LS) {
7276                                 def = data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL);
7277                                 data |= RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK;
7278                                 if (def != data)
7279                                         WREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL, data);
7280                         }
7281                         /* 3 - CP memory Light sleep */
7282                         if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CP_LS) {
7283                                 def = data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL);
7284                                 data |= CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK;
7285                                 if (def != data)
7286                                         WREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL, data);
7287                         }
7288                 }
7289         } else {
7290                 /* 1 - MGCG_OVERRIDE */
7291                 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
7292                 data |= (RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK |
7293                          RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK |
7294                          RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK |
7295                          RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK);
7296                 if (def != data)
7297                         WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
7298
7299                 /* 2 - disable MGLS in CP */
7300                 data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL);
7301                 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) {
7302                         data &= ~CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK;
7303                         WREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL, data);
7304                 }
7305
7306                 /* 3 - disable MGLS in RLC */
7307                 data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL);
7308                 if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK) {
7309                         data &= ~RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK;
7310                         WREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL, data);
7311                 }
7312
7313         }
7314 }
7315
7316 static void gfx_v10_0_update_3d_clock_gating(struct amdgpu_device *adev,
7317                                            bool enable)
7318 {
7319         uint32_t data, def;
7320
7321         /* Enable 3D CGCG/CGLS */
7322         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG)) {
7323                 /* write cmd to clear cgcg/cgls ov */
7324                 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
7325                 /* unset CGCG override */
7326                 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_GFX3D_CG_OVERRIDE_MASK;
7327                 /* update CGCG and CGLS override bits */
7328                 if (def != data)
7329                         WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
7330                 /* enable 3Dcgcg FSM(0x0000363f) */
7331                 def = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D);
7332                 data = (0x36 << RLC_CGCG_CGLS_CTRL_3D__CGCG_GFX_IDLE_THRESHOLD__SHIFT) |
7333                         RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK;
7334                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS)
7335                         data |= (0x000F << RLC_CGCG_CGLS_CTRL_3D__CGLS_REP_COMPANSAT_DELAY__SHIFT) |
7336                                 RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK;
7337                 if (def != data)
7338                         WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D, data);
7339
7340                 /* set IDLE_POLL_COUNT(0x00900100) */
7341                 def = RREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL);
7342                 data = (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) |
7343                         (0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT);
7344                 if (def != data)
7345                         WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL, data);
7346         } else {
7347                 /* Disable CGCG/CGLS */
7348                 def = data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D);
7349                 /* disable cgcg, cgls should be disabled */
7350                 data &= ~(RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK |
7351                           RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK);
7352                 /* disable cgcg and cgls in FSM */
7353                 if (def != data)
7354                         WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D, data);
7355         }
7356 }
7357
7358 static void gfx_v10_0_update_coarse_grain_clock_gating(struct amdgpu_device *adev,
7359                                                       bool enable)
7360 {
7361         uint32_t def, data;
7362
7363         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)) {
7364                 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
7365                 /* unset CGCG override */
7366                 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGCG_OVERRIDE_MASK;
7367                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS)
7368                         data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK;
7369                 else
7370                         data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK;
7371                 /* update CGCG and CGLS override bits */
7372                 if (def != data)
7373                         WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
7374
7375                 /* enable cgcg FSM(0x0000363F) */
7376                 def = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL);
7377                 data = (0x36 << RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT) |
7378                         RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK;
7379                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS)
7380                         data |= (0x000F << RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY__SHIFT) |
7381                                 RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK;
7382                 if (def != data)
7383                         WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, data);
7384
7385                 /* set IDLE_POLL_COUNT(0x00900100) */
7386                 def = RREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL);
7387                 data = (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) |
7388                         (0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT);
7389                 if (def != data)
7390                         WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL, data);
7391         } else {
7392                 def = data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL);
7393                 /* reset CGCG/CGLS bits */
7394                 data &= ~(RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK | RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK);
7395                 /* disable cgcg and cgls in FSM */
7396                 if (def != data)
7397                         WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, data);
7398         }
7399 }
7400
7401 static int gfx_v10_0_update_gfx_clock_gating(struct amdgpu_device *adev,
7402                                             bool enable)
7403 {
7404         amdgpu_gfx_rlc_enter_safe_mode(adev);
7405
7406         if (enable) {
7407                 /* CGCG/CGLS should be enabled after MGCG/MGLS
7408                  * ===  MGCG + MGLS ===
7409                  */
7410                 gfx_v10_0_update_medium_grain_clock_gating(adev, enable);
7411                 /* ===  CGCG /CGLS for GFX 3D Only === */
7412                 gfx_v10_0_update_3d_clock_gating(adev, enable);
7413                 /* ===  CGCG + CGLS === */
7414                 gfx_v10_0_update_coarse_grain_clock_gating(adev, enable);
7415         } else {
7416                 /* CGCG/CGLS should be disabled before MGCG/MGLS
7417                  * ===  CGCG + CGLS ===
7418                  */
7419                 gfx_v10_0_update_coarse_grain_clock_gating(adev, enable);
7420                 /* ===  CGCG /CGLS for GFX 3D Only === */
7421                 gfx_v10_0_update_3d_clock_gating(adev, enable);
7422                 /* ===  MGCG + MGLS === */
7423                 gfx_v10_0_update_medium_grain_clock_gating(adev, enable);
7424         }
7425
7426         if (adev->cg_flags &
7427             (AMD_CG_SUPPORT_GFX_MGCG |
7428              AMD_CG_SUPPORT_GFX_CGLS |
7429              AMD_CG_SUPPORT_GFX_CGCG |
7430              AMD_CG_SUPPORT_GFX_CGLS |
7431              AMD_CG_SUPPORT_GFX_3D_CGCG |
7432              AMD_CG_SUPPORT_GFX_3D_CGLS))
7433                 gfx_v10_0_enable_gui_idle_interrupt(adev, enable);
7434
7435         amdgpu_gfx_rlc_exit_safe_mode(adev);
7436
7437         return 0;
7438 }
7439
7440 static void gfx_v10_0_update_spm_vmid(struct amdgpu_device *adev, unsigned vmid)
7441 {
7442         u32 reg, data;
7443
7444         reg = SOC15_REG_OFFSET(GC, 0, mmRLC_SPM_MC_CNTL);
7445         if (amdgpu_sriov_is_pp_one_vf(adev))
7446                 data = RREG32_NO_KIQ(reg);
7447         else
7448                 data = RREG32(reg);
7449
7450         data &= ~RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK;
7451         data |= (vmid & RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK) << RLC_SPM_MC_CNTL__RLC_SPM_VMID__SHIFT;
7452
7453         if (amdgpu_sriov_is_pp_one_vf(adev))
7454                 WREG32_SOC15_NO_KIQ(GC, 0, mmRLC_SPM_MC_CNTL, data);
7455         else
7456                 WREG32_SOC15(GC, 0, mmRLC_SPM_MC_CNTL, data);
7457 }
7458
7459 static bool gfx_v10_0_check_rlcg_range(struct amdgpu_device *adev,
7460                                         uint32_t offset,
7461                                         struct soc15_reg_rlcg *entries, int arr_size)
7462 {
7463         int i;
7464         uint32_t reg;
7465
7466         if (!entries)
7467                 return false;
7468
7469         for (i = 0; i < arr_size; i++) {
7470                 const struct soc15_reg_rlcg *entry;
7471
7472                 entry = &entries[i];
7473                 reg = adev->reg_offset[entry->hwip][entry->instance][entry->segment] + entry->reg;
7474                 if (offset == reg)
7475                         return true;
7476         }
7477
7478         return false;
7479 }
7480
7481 static bool gfx_v10_0_is_rlcg_access_range(struct amdgpu_device *adev, u32 offset)
7482 {
7483         return gfx_v10_0_check_rlcg_range(adev, offset, NULL, 0);
7484 }
7485
7486 static const struct amdgpu_rlc_funcs gfx_v10_0_rlc_funcs = {
7487         .is_rlc_enabled = gfx_v10_0_is_rlc_enabled,
7488         .set_safe_mode = gfx_v10_0_set_safe_mode,
7489         .unset_safe_mode = gfx_v10_0_unset_safe_mode,
7490         .init = gfx_v10_0_rlc_init,
7491         .get_csb_size = gfx_v10_0_get_csb_size,
7492         .get_csb_buffer = gfx_v10_0_get_csb_buffer,
7493         .resume = gfx_v10_0_rlc_resume,
7494         .stop = gfx_v10_0_rlc_stop,
7495         .reset = gfx_v10_0_rlc_reset,
7496         .start = gfx_v10_0_rlc_start,
7497         .update_spm_vmid = gfx_v10_0_update_spm_vmid,
7498 };
7499
7500 static const struct amdgpu_rlc_funcs gfx_v10_0_rlc_funcs_sriov = {
7501         .is_rlc_enabled = gfx_v10_0_is_rlc_enabled,
7502         .set_safe_mode = gfx_v10_0_set_safe_mode,
7503         .unset_safe_mode = gfx_v10_0_unset_safe_mode,
7504         .init = gfx_v10_0_rlc_init,
7505         .get_csb_size = gfx_v10_0_get_csb_size,
7506         .get_csb_buffer = gfx_v10_0_get_csb_buffer,
7507         .resume = gfx_v10_0_rlc_resume,
7508         .stop = gfx_v10_0_rlc_stop,
7509         .reset = gfx_v10_0_rlc_reset,
7510         .start = gfx_v10_0_rlc_start,
7511         .update_spm_vmid = gfx_v10_0_update_spm_vmid,
7512         .rlcg_wreg = gfx_v10_rlcg_wreg,
7513         .is_rlcg_access_range = gfx_v10_0_is_rlcg_access_range,
7514 };
7515
7516 static int gfx_v10_0_set_powergating_state(void *handle,
7517                                           enum amd_powergating_state state)
7518 {
7519         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7520         bool enable = (state == AMD_PG_STATE_GATE);
7521
7522         if (amdgpu_sriov_vf(adev))
7523                 return 0;
7524
7525         switch (adev->asic_type) {
7526         case CHIP_NAVI10:
7527         case CHIP_NAVI14:
7528         case CHIP_NAVI12:
7529         case CHIP_SIENNA_CICHLID:
7530         case CHIP_NAVY_FLOUNDER:
7531                 amdgpu_gfx_off_ctrl(adev, enable);
7532                 break;
7533         default:
7534                 break;
7535         }
7536         return 0;
7537 }
7538
7539 static int gfx_v10_0_set_clockgating_state(void *handle,
7540                                           enum amd_clockgating_state state)
7541 {
7542         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7543
7544         if (amdgpu_sriov_vf(adev))
7545                 return 0;
7546
7547         switch (adev->asic_type) {
7548         case CHIP_NAVI10:
7549         case CHIP_NAVI14:
7550         case CHIP_NAVI12:
7551         case CHIP_SIENNA_CICHLID:
7552         case CHIP_NAVY_FLOUNDER:
7553                 gfx_v10_0_update_gfx_clock_gating(adev,
7554                                                  state == AMD_CG_STATE_GATE);
7555                 break;
7556         default:
7557                 break;
7558         }
7559         return 0;
7560 }
7561
7562 static void gfx_v10_0_get_clockgating_state(void *handle, u32 *flags)
7563 {
7564         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7565         int data;
7566
7567         /* AMD_CG_SUPPORT_GFX_MGCG */
7568         data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE));
7569         if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK))
7570                 *flags |= AMD_CG_SUPPORT_GFX_MGCG;
7571
7572         /* AMD_CG_SUPPORT_GFX_CGCG */
7573         data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGCG_CGLS_CTRL));
7574         if (data & RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK)
7575                 *flags |= AMD_CG_SUPPORT_GFX_CGCG;
7576
7577         /* AMD_CG_SUPPORT_GFX_CGLS */
7578         if (data & RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK)
7579                 *flags |= AMD_CG_SUPPORT_GFX_CGLS;
7580
7581         /* AMD_CG_SUPPORT_GFX_RLC_LS */
7582         data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_MEM_SLP_CNTL));
7583         if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK)
7584                 *flags |= AMD_CG_SUPPORT_GFX_RLC_LS | AMD_CG_SUPPORT_GFX_MGLS;
7585
7586         /* AMD_CG_SUPPORT_GFX_CP_LS */
7587         data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmCP_MEM_SLP_CNTL));
7588         if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK)
7589                 *flags |= AMD_CG_SUPPORT_GFX_CP_LS | AMD_CG_SUPPORT_GFX_MGLS;
7590
7591         /* AMD_CG_SUPPORT_GFX_3D_CGCG */
7592         data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D));
7593         if (data & RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK)
7594                 *flags |= AMD_CG_SUPPORT_GFX_3D_CGCG;
7595
7596         /* AMD_CG_SUPPORT_GFX_3D_CGLS */
7597         if (data & RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK)
7598                 *flags |= AMD_CG_SUPPORT_GFX_3D_CGLS;
7599 }
7600
7601 static u64 gfx_v10_0_ring_get_rptr_gfx(struct amdgpu_ring *ring)
7602 {
7603         return ring->adev->wb.wb[ring->rptr_offs]; /* gfx10 is 32bit rptr*/
7604 }
7605
7606 static u64 gfx_v10_0_ring_get_wptr_gfx(struct amdgpu_ring *ring)
7607 {
7608         struct amdgpu_device *adev = ring->adev;
7609         u64 wptr;
7610
7611         /* XXX check if swapping is necessary on BE */
7612         if (ring->use_doorbell) {
7613                 wptr = atomic64_read((atomic64_t *)&adev->wb.wb[ring->wptr_offs]);
7614         } else {
7615                 wptr = RREG32_SOC15(GC, 0, mmCP_RB0_WPTR);
7616                 wptr += (u64)RREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI) << 32;
7617         }
7618
7619         return wptr;
7620 }
7621
7622 static void gfx_v10_0_ring_set_wptr_gfx(struct amdgpu_ring *ring)
7623 {
7624         struct amdgpu_device *adev = ring->adev;
7625
7626         if (ring->use_doorbell) {
7627                 /* XXX check if swapping is necessary on BE */
7628                 atomic64_set((atomic64_t *)&adev->wb.wb[ring->wptr_offs], ring->wptr);
7629                 WDOORBELL64(ring->doorbell_index, ring->wptr);
7630         } else {
7631                 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR, lower_32_bits(ring->wptr));
7632                 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI, upper_32_bits(ring->wptr));
7633         }
7634 }
7635
7636 static u64 gfx_v10_0_ring_get_rptr_compute(struct amdgpu_ring *ring)
7637 {
7638         return ring->adev->wb.wb[ring->rptr_offs]; /* gfx10 hardware is 32bit rptr */
7639 }
7640
7641 static u64 gfx_v10_0_ring_get_wptr_compute(struct amdgpu_ring *ring)
7642 {
7643         u64 wptr;
7644
7645         /* XXX check if swapping is necessary on BE */
7646         if (ring->use_doorbell)
7647                 wptr = atomic64_read((atomic64_t *)&ring->adev->wb.wb[ring->wptr_offs]);
7648         else
7649                 BUG();
7650         return wptr;
7651 }
7652
7653 static void gfx_v10_0_ring_set_wptr_compute(struct amdgpu_ring *ring)
7654 {
7655         struct amdgpu_device *adev = ring->adev;
7656
7657         /* XXX check if swapping is necessary on BE */
7658         if (ring->use_doorbell) {
7659                 atomic64_set((atomic64_t *)&adev->wb.wb[ring->wptr_offs], ring->wptr);
7660                 WDOORBELL64(ring->doorbell_index, ring->wptr);
7661         } else {
7662                 BUG(); /* only DOORBELL method supported on gfx10 now */
7663         }
7664 }
7665
7666 static void gfx_v10_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
7667 {
7668         struct amdgpu_device *adev = ring->adev;
7669         u32 ref_and_mask, reg_mem_engine;
7670         const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio.hdp_flush_reg;
7671
7672         if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) {
7673                 switch (ring->me) {
7674                 case 1:
7675                         ref_and_mask = nbio_hf_reg->ref_and_mask_cp2 << ring->pipe;
7676                         break;
7677                 case 2:
7678                         ref_and_mask = nbio_hf_reg->ref_and_mask_cp6 << ring->pipe;
7679                         break;
7680                 default:
7681                         return;
7682                 }
7683                 reg_mem_engine = 0;
7684         } else {
7685                 ref_and_mask = nbio_hf_reg->ref_and_mask_cp0;
7686                 reg_mem_engine = 1; /* pfp */
7687         }
7688
7689         gfx_v10_0_wait_reg_mem(ring, reg_mem_engine, 0, 1,
7690                                adev->nbio.funcs->get_hdp_flush_req_offset(adev),
7691                                adev->nbio.funcs->get_hdp_flush_done_offset(adev),
7692                                ref_and_mask, ref_and_mask, 0x20);
7693 }
7694
7695 static void gfx_v10_0_ring_emit_ib_gfx(struct amdgpu_ring *ring,
7696                                        struct amdgpu_job *job,
7697                                        struct amdgpu_ib *ib,
7698                                        uint32_t flags)
7699 {
7700         unsigned vmid = AMDGPU_JOB_GET_VMID(job);
7701         u32 header, control = 0;
7702
7703         if (ib->flags & AMDGPU_IB_FLAG_CE)
7704                 header = PACKET3(PACKET3_INDIRECT_BUFFER_CNST, 2);
7705         else
7706                 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2);
7707
7708         control |= ib->length_dw | (vmid << 24);
7709
7710         if ((amdgpu_sriov_vf(ring->adev) || amdgpu_mcbp) && (ib->flags & AMDGPU_IB_FLAG_PREEMPT)) {
7711                 control |= INDIRECT_BUFFER_PRE_ENB(1);
7712
7713                 if (flags & AMDGPU_IB_PREEMPTED)
7714                         control |= INDIRECT_BUFFER_PRE_RESUME(1);
7715
7716                 if (!(ib->flags & AMDGPU_IB_FLAG_CE) && vmid)
7717                         gfx_v10_0_ring_emit_de_meta(ring,
7718                                     (!amdgpu_sriov_vf(ring->adev) && flags & AMDGPU_IB_PREEMPTED) ? true : false);
7719         }
7720
7721         amdgpu_ring_write(ring, header);
7722         BUG_ON(ib->gpu_addr & 0x3); /* Dword align */
7723         amdgpu_ring_write(ring,
7724 #ifdef __BIG_ENDIAN
7725                 (2 << 0) |
7726 #endif
7727                 lower_32_bits(ib->gpu_addr));
7728         amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
7729         amdgpu_ring_write(ring, control);
7730 }
7731
7732 static void gfx_v10_0_ring_emit_ib_compute(struct amdgpu_ring *ring,
7733                                            struct amdgpu_job *job,
7734                                            struct amdgpu_ib *ib,
7735                                            uint32_t flags)
7736 {
7737         unsigned vmid = AMDGPU_JOB_GET_VMID(job);
7738         u32 control = INDIRECT_BUFFER_VALID | ib->length_dw | (vmid << 24);
7739
7740         /* Currently, there is a high possibility to get wave ID mismatch
7741          * between ME and GDS, leading to a hw deadlock, because ME generates
7742          * different wave IDs than the GDS expects. This situation happens
7743          * randomly when at least 5 compute pipes use GDS ordered append.
7744          * The wave IDs generated by ME are also wrong after suspend/resume.
7745          * Those are probably bugs somewhere else in the kernel driver.
7746          *
7747          * Writing GDS_COMPUTE_MAX_WAVE_ID resets wave ID counters in ME and
7748          * GDS to 0 for this ring (me/pipe).
7749          */
7750         if (ib->flags & AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID) {
7751                 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
7752                 amdgpu_ring_write(ring, mmGDS_COMPUTE_MAX_WAVE_ID);
7753                 amdgpu_ring_write(ring, ring->adev->gds.gds_compute_max_wave_id);
7754         }
7755
7756         amdgpu_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
7757         BUG_ON(ib->gpu_addr & 0x3); /* Dword align */
7758         amdgpu_ring_write(ring,
7759 #ifdef __BIG_ENDIAN
7760                                 (2 << 0) |
7761 #endif
7762                                 lower_32_bits(ib->gpu_addr));
7763         amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
7764         amdgpu_ring_write(ring, control);
7765 }
7766
7767 static void gfx_v10_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr,
7768                                      u64 seq, unsigned flags)
7769 {
7770         bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
7771         bool int_sel = flags & AMDGPU_FENCE_FLAG_INT;
7772
7773         /* RELEASE_MEM - flush caches, send int */
7774         amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 6));
7775         amdgpu_ring_write(ring, (PACKET3_RELEASE_MEM_GCR_SEQ |
7776                                  PACKET3_RELEASE_MEM_GCR_GL2_WB |
7777                                  PACKET3_RELEASE_MEM_GCR_GLM_INV | /* must be set with GLM_WB */
7778                                  PACKET3_RELEASE_MEM_GCR_GLM_WB |
7779                                  PACKET3_RELEASE_MEM_CACHE_POLICY(3) |
7780                                  PACKET3_RELEASE_MEM_EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) |
7781                                  PACKET3_RELEASE_MEM_EVENT_INDEX(5)));
7782         amdgpu_ring_write(ring, (PACKET3_RELEASE_MEM_DATA_SEL(write64bit ? 2 : 1) |
7783                                  PACKET3_RELEASE_MEM_INT_SEL(int_sel ? 2 : 0)));
7784
7785         /*
7786          * the address should be Qword aligned if 64bit write, Dword
7787          * aligned if only send 32bit data low (discard data high)
7788          */
7789         if (write64bit)
7790                 BUG_ON(addr & 0x7);
7791         else
7792                 BUG_ON(addr & 0x3);
7793         amdgpu_ring_write(ring, lower_32_bits(addr));
7794         amdgpu_ring_write(ring, upper_32_bits(addr));
7795         amdgpu_ring_write(ring, lower_32_bits(seq));
7796         amdgpu_ring_write(ring, upper_32_bits(seq));
7797         amdgpu_ring_write(ring, 0);
7798 }
7799
7800 static void gfx_v10_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
7801 {
7802         int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
7803         uint32_t seq = ring->fence_drv.sync_seq;
7804         uint64_t addr = ring->fence_drv.gpu_addr;
7805
7806         gfx_v10_0_wait_reg_mem(ring, usepfp, 1, 0, lower_32_bits(addr),
7807                                upper_32_bits(addr), seq, 0xffffffff, 4);
7808 }
7809
7810 static void gfx_v10_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
7811                                          unsigned vmid, uint64_t pd_addr)
7812 {
7813         amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
7814
7815         /* compute doesn't have PFP */
7816         if (ring->funcs->type == AMDGPU_RING_TYPE_GFX) {
7817                 /* sync PFP to ME, otherwise we might get invalid PFP reads */
7818                 amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0));
7819                 amdgpu_ring_write(ring, 0x0);
7820         }
7821 }
7822
7823 static void gfx_v10_0_ring_emit_fence_kiq(struct amdgpu_ring *ring, u64 addr,
7824                                           u64 seq, unsigned int flags)
7825 {
7826         struct amdgpu_device *adev = ring->adev;
7827
7828         /* we only allocate 32bit for each seq wb address */
7829         BUG_ON(flags & AMDGPU_FENCE_FLAG_64BIT);
7830
7831         /* write fence seq to the "addr" */
7832         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
7833         amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
7834                                  WRITE_DATA_DST_SEL(5) | WR_CONFIRM));
7835         amdgpu_ring_write(ring, lower_32_bits(addr));
7836         amdgpu_ring_write(ring, upper_32_bits(addr));
7837         amdgpu_ring_write(ring, lower_32_bits(seq));
7838
7839         if (flags & AMDGPU_FENCE_FLAG_INT) {
7840                 /* set register to trigger INT */
7841                 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
7842                 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
7843                                          WRITE_DATA_DST_SEL(0) | WR_CONFIRM));
7844                 amdgpu_ring_write(ring, SOC15_REG_OFFSET(GC, 0, mmCPC_INT_STATUS));
7845                 amdgpu_ring_write(ring, 0);
7846                 amdgpu_ring_write(ring, 0x20000000); /* src_id is 178 */
7847         }
7848 }
7849
7850 static void gfx_v10_0_ring_emit_sb(struct amdgpu_ring *ring)
7851 {
7852         amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
7853         amdgpu_ring_write(ring, 0);
7854 }
7855
7856 static void gfx_v10_0_ring_emit_cntxcntl(struct amdgpu_ring *ring,
7857                                          uint32_t flags)
7858 {
7859         uint32_t dw2 = 0;
7860
7861         if (amdgpu_mcbp || amdgpu_sriov_vf(ring->adev))
7862                 gfx_v10_0_ring_emit_ce_meta(ring,
7863                                     (!amdgpu_sriov_vf(ring->adev) && flags & AMDGPU_IB_PREEMPTED) ? true : false);
7864
7865         dw2 |= 0x80000000; /* set load_enable otherwise this package is just NOPs */
7866         if (flags & AMDGPU_HAVE_CTX_SWITCH) {
7867                 /* set load_global_config & load_global_uconfig */
7868                 dw2 |= 0x8001;
7869                 /* set load_cs_sh_regs */
7870                 dw2 |= 0x01000000;
7871                 /* set load_per_context_state & load_gfx_sh_regs for GFX */
7872                 dw2 |= 0x10002;
7873
7874                 /* set load_ce_ram if preamble presented */
7875                 if (AMDGPU_PREAMBLE_IB_PRESENT & flags)
7876                         dw2 |= 0x10000000;
7877         } else {
7878                 /* still load_ce_ram if this is the first time preamble presented
7879                  * although there is no context switch happens.
7880                  */
7881                 if (AMDGPU_PREAMBLE_IB_PRESENT_FIRST & flags)
7882                         dw2 |= 0x10000000;
7883         }
7884
7885         amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1));
7886         amdgpu_ring_write(ring, dw2);
7887         amdgpu_ring_write(ring, 0);
7888 }
7889
7890 static unsigned gfx_v10_0_ring_emit_init_cond_exec(struct amdgpu_ring *ring)
7891 {
7892         unsigned ret;
7893
7894         amdgpu_ring_write(ring, PACKET3(PACKET3_COND_EXEC, 3));
7895         amdgpu_ring_write(ring, lower_32_bits(ring->cond_exe_gpu_addr));
7896         amdgpu_ring_write(ring, upper_32_bits(ring->cond_exe_gpu_addr));
7897         amdgpu_ring_write(ring, 0); /* discard following DWs if *cond_exec_gpu_addr==0 */
7898         ret = ring->wptr & ring->buf_mask;
7899         amdgpu_ring_write(ring, 0x55aa55aa); /* patch dummy value later */
7900
7901         return ret;
7902 }
7903
7904 static void gfx_v10_0_ring_emit_patch_cond_exec(struct amdgpu_ring *ring, unsigned offset)
7905 {
7906         unsigned cur;
7907         BUG_ON(offset > ring->buf_mask);
7908         BUG_ON(ring->ring[offset] != 0x55aa55aa);
7909
7910         cur = (ring->wptr - 1) & ring->buf_mask;
7911         if (likely(cur > offset))
7912                 ring->ring[offset] = cur - offset;
7913         else
7914                 ring->ring[offset] = (ring->buf_mask + 1) - offset + cur;
7915 }
7916
7917 static int gfx_v10_0_ring_preempt_ib(struct amdgpu_ring *ring)
7918 {
7919         int i, r = 0;
7920         struct amdgpu_device *adev = ring->adev;
7921         struct amdgpu_kiq *kiq = &adev->gfx.kiq;
7922         struct amdgpu_ring *kiq_ring = &kiq->ring;
7923         unsigned long flags;
7924
7925         if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues)
7926                 return -EINVAL;
7927
7928         spin_lock_irqsave(&kiq->ring_lock, flags);
7929
7930         if (amdgpu_ring_alloc(kiq_ring, kiq->pmf->unmap_queues_size)) {
7931                 spin_unlock_irqrestore(&kiq->ring_lock, flags);
7932                 return -ENOMEM;
7933         }
7934
7935         /* assert preemption condition */
7936         amdgpu_ring_set_preempt_cond_exec(ring, false);
7937
7938         /* assert IB preemption, emit the trailing fence */
7939         kiq->pmf->kiq_unmap_queues(kiq_ring, ring, PREEMPT_QUEUES_NO_UNMAP,
7940                                    ring->trail_fence_gpu_addr,
7941                                    ++ring->trail_seq);
7942         amdgpu_ring_commit(kiq_ring);
7943
7944         spin_unlock_irqrestore(&kiq->ring_lock, flags);
7945
7946         /* poll the trailing fence */
7947         for (i = 0; i < adev->usec_timeout; i++) {
7948                 if (ring->trail_seq ==
7949                     le32_to_cpu(*(ring->trail_fence_cpu_addr)))
7950                         break;
7951                 udelay(1);
7952         }
7953
7954         if (i >= adev->usec_timeout) {
7955                 r = -EINVAL;
7956                 DRM_ERROR("ring %d failed to preempt ib\n", ring->idx);
7957         }
7958
7959         /* deassert preemption condition */
7960         amdgpu_ring_set_preempt_cond_exec(ring, true);
7961         return r;
7962 }
7963
7964 static void gfx_v10_0_ring_emit_ce_meta(struct amdgpu_ring *ring, bool resume)
7965 {
7966         struct amdgpu_device *adev = ring->adev;
7967         struct v10_ce_ib_state ce_payload = {0};
7968         uint64_t csa_addr;
7969         int cnt;
7970
7971         cnt = (sizeof(ce_payload) >> 2) + 4 - 2;
7972         csa_addr = amdgpu_csa_vaddr(ring->adev);
7973
7974         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt));
7975         amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(2) |
7976                                  WRITE_DATA_DST_SEL(8) |
7977                                  WR_CONFIRM) |
7978                                  WRITE_DATA_CACHE_POLICY(0));
7979         amdgpu_ring_write(ring, lower_32_bits(csa_addr +
7980                               offsetof(struct v10_gfx_meta_data, ce_payload)));
7981         amdgpu_ring_write(ring, upper_32_bits(csa_addr +
7982                               offsetof(struct v10_gfx_meta_data, ce_payload)));
7983
7984         if (resume)
7985                 amdgpu_ring_write_multiple(ring, adev->virt.csa_cpu_addr +
7986                                            offsetof(struct v10_gfx_meta_data,
7987                                                     ce_payload),
7988                                            sizeof(ce_payload) >> 2);
7989         else
7990                 amdgpu_ring_write_multiple(ring, (void *)&ce_payload,
7991                                            sizeof(ce_payload) >> 2);
7992 }
7993
7994 static void gfx_v10_0_ring_emit_de_meta(struct amdgpu_ring *ring, bool resume)
7995 {
7996         struct amdgpu_device *adev = ring->adev;
7997         struct v10_de_ib_state de_payload = {0};
7998         uint64_t csa_addr, gds_addr;
7999         int cnt;
8000
8001         csa_addr = amdgpu_csa_vaddr(ring->adev);
8002         gds_addr = ALIGN(csa_addr + AMDGPU_CSA_SIZE - adev->gds.gds_size,
8003                          PAGE_SIZE);
8004         de_payload.gds_backup_addrlo = lower_32_bits(gds_addr);
8005         de_payload.gds_backup_addrhi = upper_32_bits(gds_addr);
8006
8007         cnt = (sizeof(de_payload) >> 2) + 4 - 2;
8008         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt));
8009         amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(1) |
8010                                  WRITE_DATA_DST_SEL(8) |
8011                                  WR_CONFIRM) |
8012                                  WRITE_DATA_CACHE_POLICY(0));
8013         amdgpu_ring_write(ring, lower_32_bits(csa_addr +
8014                               offsetof(struct v10_gfx_meta_data, de_payload)));
8015         amdgpu_ring_write(ring, upper_32_bits(csa_addr +
8016                               offsetof(struct v10_gfx_meta_data, de_payload)));
8017
8018         if (resume)
8019                 amdgpu_ring_write_multiple(ring, adev->virt.csa_cpu_addr +
8020                                            offsetof(struct v10_gfx_meta_data,
8021                                                     de_payload),
8022                                            sizeof(de_payload) >> 2);
8023         else
8024                 amdgpu_ring_write_multiple(ring, (void *)&de_payload,
8025                                            sizeof(de_payload) >> 2);
8026 }
8027
8028 static void gfx_v10_0_ring_emit_frame_cntl(struct amdgpu_ring *ring, bool start,
8029                                     bool secure)
8030 {
8031         uint32_t v = secure ? FRAME_TMZ : 0;
8032
8033         amdgpu_ring_write(ring, PACKET3(PACKET3_FRAME_CONTROL, 0));
8034         amdgpu_ring_write(ring, v | FRAME_CMD(start ? 0 : 1));
8035 }
8036
8037 static void gfx_v10_0_ring_emit_rreg(struct amdgpu_ring *ring, uint32_t reg,
8038                                      uint32_t reg_val_offs)
8039 {
8040         struct amdgpu_device *adev = ring->adev;
8041
8042         amdgpu_ring_write(ring, PACKET3(PACKET3_COPY_DATA, 4));
8043         amdgpu_ring_write(ring, 0 |     /* src: register*/
8044                                 (5 << 8) |      /* dst: memory */
8045                                 (1 << 20));     /* write confirm */
8046         amdgpu_ring_write(ring, reg);
8047         amdgpu_ring_write(ring, 0);
8048         amdgpu_ring_write(ring, lower_32_bits(adev->wb.gpu_addr +
8049                                 reg_val_offs * 4));
8050         amdgpu_ring_write(ring, upper_32_bits(adev->wb.gpu_addr +
8051                                 reg_val_offs * 4));
8052 }
8053
8054 static void gfx_v10_0_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg,
8055                                    uint32_t val)
8056 {
8057         uint32_t cmd = 0;
8058
8059         switch (ring->funcs->type) {
8060         case AMDGPU_RING_TYPE_GFX:
8061                 cmd = WRITE_DATA_ENGINE_SEL(1) | WR_CONFIRM;
8062                 break;
8063         case AMDGPU_RING_TYPE_KIQ:
8064                 cmd = (1 << 16); /* no inc addr */
8065                 break;
8066         default:
8067                 cmd = WR_CONFIRM;
8068                 break;
8069         }
8070         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
8071         amdgpu_ring_write(ring, cmd);
8072         amdgpu_ring_write(ring, reg);
8073         amdgpu_ring_write(ring, 0);
8074         amdgpu_ring_write(ring, val);
8075 }
8076
8077 static void gfx_v10_0_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,
8078                                         uint32_t val, uint32_t mask)
8079 {
8080         gfx_v10_0_wait_reg_mem(ring, 0, 0, 0, reg, 0, val, mask, 0x20);
8081 }
8082
8083 static void gfx_v10_0_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring,
8084                                                    uint32_t reg0, uint32_t reg1,
8085                                                    uint32_t ref, uint32_t mask)
8086 {
8087         int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
8088         struct amdgpu_device *adev = ring->adev;
8089         bool fw_version_ok = false;
8090
8091         fw_version_ok = adev->gfx.cp_fw_write_wait;
8092
8093         if (fw_version_ok)
8094                 gfx_v10_0_wait_reg_mem(ring, usepfp, 0, 1, reg0, reg1,
8095                                        ref, mask, 0x20);
8096         else
8097                 amdgpu_ring_emit_reg_write_reg_wait_helper(ring, reg0, reg1,
8098                                                            ref, mask);
8099 }
8100
8101 static void gfx_v10_0_ring_soft_recovery(struct amdgpu_ring *ring,
8102                                          unsigned vmid)
8103 {
8104         struct amdgpu_device *adev = ring->adev;
8105         uint32_t value = 0;
8106
8107         value = REG_SET_FIELD(value, SQ_CMD, CMD, 0x03);
8108         value = REG_SET_FIELD(value, SQ_CMD, MODE, 0x01);
8109         value = REG_SET_FIELD(value, SQ_CMD, CHECK_VMID, 1);
8110         value = REG_SET_FIELD(value, SQ_CMD, VM_ID, vmid);
8111         WREG32_SOC15(GC, 0, mmSQ_CMD, value);
8112 }
8113
8114 static void
8115 gfx_v10_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev,
8116                                       uint32_t me, uint32_t pipe,
8117                                       enum amdgpu_interrupt_state state)
8118 {
8119         uint32_t cp_int_cntl, cp_int_cntl_reg;
8120
8121         if (!me) {
8122                 switch (pipe) {
8123                 case 0:
8124                         cp_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_INT_CNTL_RING0);
8125                         break;
8126                 case 1:
8127                         cp_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_INT_CNTL_RING1);
8128                         break;
8129                 default:
8130                         DRM_DEBUG("invalid pipe %d\n", pipe);
8131                         return;
8132                 }
8133         } else {
8134                 DRM_DEBUG("invalid me %d\n", me);
8135                 return;
8136         }
8137
8138         switch (state) {
8139         case AMDGPU_IRQ_STATE_DISABLE:
8140                 cp_int_cntl = RREG32(cp_int_cntl_reg);
8141                 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
8142                                             TIME_STAMP_INT_ENABLE, 0);
8143                 WREG32(cp_int_cntl_reg, cp_int_cntl);
8144                 break;
8145         case AMDGPU_IRQ_STATE_ENABLE:
8146                 cp_int_cntl = RREG32(cp_int_cntl_reg);
8147                 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
8148                                             TIME_STAMP_INT_ENABLE, 1);
8149                 WREG32(cp_int_cntl_reg, cp_int_cntl);
8150                 break;
8151         default:
8152                 break;
8153         }
8154 }
8155
8156 static void gfx_v10_0_set_compute_eop_interrupt_state(struct amdgpu_device *adev,
8157                                                      int me, int pipe,
8158                                                      enum amdgpu_interrupt_state state)
8159 {
8160         u32 mec_int_cntl, mec_int_cntl_reg;
8161
8162         /*
8163          * amdgpu controls only the first MEC. That's why this function only
8164          * handles the setting of interrupts for this specific MEC. All other
8165          * pipes' interrupts are set by amdkfd.
8166          */
8167
8168         if (me == 1) {
8169                 switch (pipe) {
8170                 case 0:
8171                         mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE0_INT_CNTL);
8172                         break;
8173                 case 1:
8174                         mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE1_INT_CNTL);
8175                         break;
8176                 case 2:
8177                         mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE2_INT_CNTL);
8178                         break;
8179                 case 3:
8180                         mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE3_INT_CNTL);
8181                         break;
8182                 default:
8183                         DRM_DEBUG("invalid pipe %d\n", pipe);
8184                         return;
8185                 }
8186         } else {
8187                 DRM_DEBUG("invalid me %d\n", me);
8188                 return;
8189         }
8190
8191         switch (state) {
8192         case AMDGPU_IRQ_STATE_DISABLE:
8193                 mec_int_cntl = RREG32(mec_int_cntl_reg);
8194                 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,
8195                                              TIME_STAMP_INT_ENABLE, 0);
8196                 WREG32(mec_int_cntl_reg, mec_int_cntl);
8197                 break;
8198         case AMDGPU_IRQ_STATE_ENABLE:
8199                 mec_int_cntl = RREG32(mec_int_cntl_reg);
8200                 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,
8201                                              TIME_STAMP_INT_ENABLE, 1);
8202                 WREG32(mec_int_cntl_reg, mec_int_cntl);
8203                 break;
8204         default:
8205                 break;
8206         }
8207 }
8208
8209 static int gfx_v10_0_set_eop_interrupt_state(struct amdgpu_device *adev,
8210                                             struct amdgpu_irq_src *src,
8211                                             unsigned type,
8212                                             enum amdgpu_interrupt_state state)
8213 {
8214         switch (type) {
8215         case AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP:
8216                 gfx_v10_0_set_gfx_eop_interrupt_state(adev, 0, 0, state);
8217                 break;
8218         case AMDGPU_CP_IRQ_GFX_ME0_PIPE1_EOP:
8219                 gfx_v10_0_set_gfx_eop_interrupt_state(adev, 0, 1, state);
8220                 break;
8221         case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP:
8222                 gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 0, state);
8223                 break;
8224         case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP:
8225                 gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 1, state);
8226                 break;
8227         case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP:
8228                 gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 2, state);
8229                 break;
8230         case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP:
8231                 gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 3, state);
8232                 break;
8233         case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP:
8234                 gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 0, state);
8235                 break;
8236         case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP:
8237                 gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 1, state);
8238                 break;
8239         case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP:
8240                 gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 2, state);
8241                 break;
8242         case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP:
8243                 gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 3, state);
8244                 break;
8245         default:
8246                 break;
8247         }
8248         return 0;
8249 }
8250
8251 static int gfx_v10_0_eop_irq(struct amdgpu_device *adev,
8252                              struct amdgpu_irq_src *source,
8253                              struct amdgpu_iv_entry *entry)
8254 {
8255         int i;
8256         u8 me_id, pipe_id, queue_id;
8257         struct amdgpu_ring *ring;
8258
8259         DRM_DEBUG("IH: CP EOP\n");
8260         me_id = (entry->ring_id & 0x0c) >> 2;
8261         pipe_id = (entry->ring_id & 0x03) >> 0;
8262         queue_id = (entry->ring_id & 0x70) >> 4;
8263
8264         switch (me_id) {
8265         case 0:
8266                 if (pipe_id == 0)
8267                         amdgpu_fence_process(&adev->gfx.gfx_ring[0]);
8268                 else
8269                         amdgpu_fence_process(&adev->gfx.gfx_ring[1]);
8270                 break;
8271         case 1:
8272         case 2:
8273                 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
8274                         ring = &adev->gfx.compute_ring[i];
8275                         /* Per-queue interrupt is supported for MEC starting from VI.
8276                           * The interrupt can only be enabled/disabled per pipe instead of per queue.
8277                           */
8278                         if ((ring->me == me_id) && (ring->pipe == pipe_id) && (ring->queue == queue_id))
8279                                 amdgpu_fence_process(ring);
8280                 }
8281                 break;
8282         }
8283         return 0;
8284 }
8285
8286 static int gfx_v10_0_set_priv_reg_fault_state(struct amdgpu_device *adev,
8287                                               struct amdgpu_irq_src *source,
8288                                               unsigned type,
8289                                               enum amdgpu_interrupt_state state)
8290 {
8291         switch (state) {
8292         case AMDGPU_IRQ_STATE_DISABLE:
8293         case AMDGPU_IRQ_STATE_ENABLE:
8294                 WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0,
8295                                PRIV_REG_INT_ENABLE,
8296                                state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
8297                 break;
8298         default:
8299                 break;
8300         }
8301
8302         return 0;
8303 }
8304
8305 static int gfx_v10_0_set_priv_inst_fault_state(struct amdgpu_device *adev,
8306                                                struct amdgpu_irq_src *source,
8307                                                unsigned type,
8308                                                enum amdgpu_interrupt_state state)
8309 {
8310         switch (state) {
8311         case AMDGPU_IRQ_STATE_DISABLE:
8312         case AMDGPU_IRQ_STATE_ENABLE:
8313                 WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0,
8314                                PRIV_INSTR_INT_ENABLE,
8315                                state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
8316         default:
8317                 break;
8318         }
8319
8320         return 0;
8321 }
8322
8323 static void gfx_v10_0_handle_priv_fault(struct amdgpu_device *adev,
8324                                         struct amdgpu_iv_entry *entry)
8325 {
8326         u8 me_id, pipe_id, queue_id;
8327         struct amdgpu_ring *ring;
8328         int i;
8329
8330         me_id = (entry->ring_id & 0x0c) >> 2;
8331         pipe_id = (entry->ring_id & 0x03) >> 0;
8332         queue_id = (entry->ring_id & 0x70) >> 4;
8333
8334         switch (me_id) {
8335         case 0:
8336                 for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
8337                         ring = &adev->gfx.gfx_ring[i];
8338                         /* we only enabled 1 gfx queue per pipe for now */
8339                         if (ring->me == me_id && ring->pipe == pipe_id)
8340                                 drm_sched_fault(&ring->sched);
8341                 }
8342                 break;
8343         case 1:
8344         case 2:
8345                 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
8346                         ring = &adev->gfx.compute_ring[i];
8347                         if (ring->me == me_id && ring->pipe == pipe_id &&
8348                             ring->queue == queue_id)
8349                                 drm_sched_fault(&ring->sched);
8350                 }
8351                 break;
8352         default:
8353                 BUG();
8354         }
8355 }
8356
8357 static int gfx_v10_0_priv_reg_irq(struct amdgpu_device *adev,
8358                                   struct amdgpu_irq_src *source,
8359                                   struct amdgpu_iv_entry *entry)
8360 {
8361         DRM_ERROR("Illegal register access in command stream\n");
8362         gfx_v10_0_handle_priv_fault(adev, entry);
8363         return 0;
8364 }
8365
8366 static int gfx_v10_0_priv_inst_irq(struct amdgpu_device *adev,
8367                                    struct amdgpu_irq_src *source,
8368                                    struct amdgpu_iv_entry *entry)
8369 {
8370         DRM_ERROR("Illegal instruction in command stream\n");
8371         gfx_v10_0_handle_priv_fault(adev, entry);
8372         return 0;
8373 }
8374
8375 static int gfx_v10_0_kiq_set_interrupt_state(struct amdgpu_device *adev,
8376                                              struct amdgpu_irq_src *src,
8377                                              unsigned int type,
8378                                              enum amdgpu_interrupt_state state)
8379 {
8380         uint32_t tmp, target;
8381         struct amdgpu_ring *ring = &(adev->gfx.kiq.ring);
8382
8383         if (ring->me == 1)
8384                 target = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE0_INT_CNTL);
8385         else
8386                 target = SOC15_REG_OFFSET(GC, 0, mmCP_ME2_PIPE0_INT_CNTL);
8387         target += ring->pipe;
8388
8389         switch (type) {
8390         case AMDGPU_CP_KIQ_IRQ_DRIVER0:
8391                 if (state == AMDGPU_IRQ_STATE_DISABLE) {
8392                         tmp = RREG32_SOC15(GC, 0, mmCPC_INT_CNTL);
8393                         tmp = REG_SET_FIELD(tmp, CPC_INT_CNTL,
8394                                             GENERIC2_INT_ENABLE, 0);
8395                         WREG32_SOC15(GC, 0, mmCPC_INT_CNTL, tmp);
8396
8397                         tmp = RREG32(target);
8398                         tmp = REG_SET_FIELD(tmp, CP_ME2_PIPE0_INT_CNTL,
8399                                             GENERIC2_INT_ENABLE, 0);
8400                         WREG32(target, tmp);
8401                 } else {
8402                         tmp = RREG32_SOC15(GC, 0, mmCPC_INT_CNTL);
8403                         tmp = REG_SET_FIELD(tmp, CPC_INT_CNTL,
8404                                             GENERIC2_INT_ENABLE, 1);
8405                         WREG32_SOC15(GC, 0, mmCPC_INT_CNTL, tmp);
8406
8407                         tmp = RREG32(target);
8408                         tmp = REG_SET_FIELD(tmp, CP_ME2_PIPE0_INT_CNTL,
8409                                             GENERIC2_INT_ENABLE, 1);
8410                         WREG32(target, tmp);
8411                 }
8412                 break;
8413         default:
8414                 BUG(); /* kiq only support GENERIC2_INT now */
8415                 break;
8416         }
8417         return 0;
8418 }
8419
8420 static int gfx_v10_0_kiq_irq(struct amdgpu_device *adev,
8421                              struct amdgpu_irq_src *source,
8422                              struct amdgpu_iv_entry *entry)
8423 {
8424         u8 me_id, pipe_id, queue_id;
8425         struct amdgpu_ring *ring = &(adev->gfx.kiq.ring);
8426
8427         me_id = (entry->ring_id & 0x0c) >> 2;
8428         pipe_id = (entry->ring_id & 0x03) >> 0;
8429         queue_id = (entry->ring_id & 0x70) >> 4;
8430         DRM_DEBUG("IH: CPC GENERIC2_INT, me:%d, pipe:%d, queue:%d\n",
8431                    me_id, pipe_id, queue_id);
8432
8433         amdgpu_fence_process(ring);
8434         return 0;
8435 }
8436
8437 static void gfx_v10_0_emit_mem_sync(struct amdgpu_ring *ring)
8438 {
8439         const unsigned int gcr_cntl =
8440                         PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_INV(1) |
8441                         PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_WB(1) |
8442                         PACKET3_ACQUIRE_MEM_GCR_CNTL_GLM_INV(1) |
8443                         PACKET3_ACQUIRE_MEM_GCR_CNTL_GLM_WB(1) |
8444                         PACKET3_ACQUIRE_MEM_GCR_CNTL_GL1_INV(1) |
8445                         PACKET3_ACQUIRE_MEM_GCR_CNTL_GLV_INV(1) |
8446                         PACKET3_ACQUIRE_MEM_GCR_CNTL_GLK_INV(1) |
8447                         PACKET3_ACQUIRE_MEM_GCR_CNTL_GLI_INV(1);
8448
8449         /* ACQUIRE_MEM - make one or more surfaces valid for use by the subsequent operations */
8450         amdgpu_ring_write(ring, PACKET3(PACKET3_ACQUIRE_MEM, 6));
8451         amdgpu_ring_write(ring, 0); /* CP_COHER_CNTL */
8452         amdgpu_ring_write(ring, 0xffffffff);  /* CP_COHER_SIZE */
8453         amdgpu_ring_write(ring, 0xffffff);  /* CP_COHER_SIZE_HI */
8454         amdgpu_ring_write(ring, 0); /* CP_COHER_BASE */
8455         amdgpu_ring_write(ring, 0);  /* CP_COHER_BASE_HI */
8456         amdgpu_ring_write(ring, 0x0000000A); /* POLL_INTERVAL */
8457         amdgpu_ring_write(ring, gcr_cntl); /* GCR_CNTL */
8458 }
8459
8460 static const struct amd_ip_funcs gfx_v10_0_ip_funcs = {
8461         .name = "gfx_v10_0",
8462         .early_init = gfx_v10_0_early_init,
8463         .late_init = gfx_v10_0_late_init,
8464         .sw_init = gfx_v10_0_sw_init,
8465         .sw_fini = gfx_v10_0_sw_fini,
8466         .hw_init = gfx_v10_0_hw_init,
8467         .hw_fini = gfx_v10_0_hw_fini,
8468         .suspend = gfx_v10_0_suspend,
8469         .resume = gfx_v10_0_resume,
8470         .is_idle = gfx_v10_0_is_idle,
8471         .wait_for_idle = gfx_v10_0_wait_for_idle,
8472         .soft_reset = gfx_v10_0_soft_reset,
8473         .set_clockgating_state = gfx_v10_0_set_clockgating_state,
8474         .set_powergating_state = gfx_v10_0_set_powergating_state,
8475         .get_clockgating_state = gfx_v10_0_get_clockgating_state,
8476 };
8477
8478 static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_gfx = {
8479         .type = AMDGPU_RING_TYPE_GFX,
8480         .align_mask = 0xff,
8481         .nop = PACKET3(PACKET3_NOP, 0x3FFF),
8482         .support_64bit_ptrs = true,
8483         .vmhub = AMDGPU_GFXHUB_0,
8484         .get_rptr = gfx_v10_0_ring_get_rptr_gfx,
8485         .get_wptr = gfx_v10_0_ring_get_wptr_gfx,
8486         .set_wptr = gfx_v10_0_ring_set_wptr_gfx,
8487         .emit_frame_size = /* totally 242 maximum if 16 IBs */
8488                 5 + /* COND_EXEC */
8489                 7 + /* PIPELINE_SYNC */
8490                 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 +
8491                 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 +
8492                 2 + /* VM_FLUSH */
8493                 8 + /* FENCE for VM_FLUSH */
8494                 20 + /* GDS switch */
8495                 4 + /* double SWITCH_BUFFER,
8496                      * the first COND_EXEC jump to the place
8497                      * just prior to this double SWITCH_BUFFER
8498                      */
8499                 5 + /* COND_EXEC */
8500                 7 + /* HDP_flush */
8501                 4 + /* VGT_flush */
8502                 14 + /* CE_META */
8503                 31 + /* DE_META */
8504                 3 + /* CNTX_CTRL */
8505                 5 + /* HDP_INVL */
8506                 8 + 8 + /* FENCE x2 */
8507                 2 + /* SWITCH_BUFFER */
8508                 8, /* gfx_v10_0_emit_mem_sync */
8509         .emit_ib_size = 4, /* gfx_v10_0_ring_emit_ib_gfx */
8510         .emit_ib = gfx_v10_0_ring_emit_ib_gfx,
8511         .emit_fence = gfx_v10_0_ring_emit_fence,
8512         .emit_pipeline_sync = gfx_v10_0_ring_emit_pipeline_sync,
8513         .emit_vm_flush = gfx_v10_0_ring_emit_vm_flush,
8514         .emit_gds_switch = gfx_v10_0_ring_emit_gds_switch,
8515         .emit_hdp_flush = gfx_v10_0_ring_emit_hdp_flush,
8516         .test_ring = gfx_v10_0_ring_test_ring,
8517         .test_ib = gfx_v10_0_ring_test_ib,
8518         .insert_nop = amdgpu_ring_insert_nop,
8519         .pad_ib = amdgpu_ring_generic_pad_ib,
8520         .emit_switch_buffer = gfx_v10_0_ring_emit_sb,
8521         .emit_cntxcntl = gfx_v10_0_ring_emit_cntxcntl,
8522         .init_cond_exec = gfx_v10_0_ring_emit_init_cond_exec,
8523         .patch_cond_exec = gfx_v10_0_ring_emit_patch_cond_exec,
8524         .preempt_ib = gfx_v10_0_ring_preempt_ib,
8525         .emit_frame_cntl = gfx_v10_0_ring_emit_frame_cntl,
8526         .emit_wreg = gfx_v10_0_ring_emit_wreg,
8527         .emit_reg_wait = gfx_v10_0_ring_emit_reg_wait,
8528         .emit_reg_write_reg_wait = gfx_v10_0_ring_emit_reg_write_reg_wait,
8529         .soft_recovery = gfx_v10_0_ring_soft_recovery,
8530         .emit_mem_sync = gfx_v10_0_emit_mem_sync,
8531 };
8532
8533 static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_compute = {
8534         .type = AMDGPU_RING_TYPE_COMPUTE,
8535         .align_mask = 0xff,
8536         .nop = PACKET3(PACKET3_NOP, 0x3FFF),
8537         .support_64bit_ptrs = true,
8538         .vmhub = AMDGPU_GFXHUB_0,
8539         .get_rptr = gfx_v10_0_ring_get_rptr_compute,
8540         .get_wptr = gfx_v10_0_ring_get_wptr_compute,
8541         .set_wptr = gfx_v10_0_ring_set_wptr_compute,
8542         .emit_frame_size =
8543                 20 + /* gfx_v10_0_ring_emit_gds_switch */
8544                 7 + /* gfx_v10_0_ring_emit_hdp_flush */
8545                 5 + /* hdp invalidate */
8546                 7 + /* gfx_v10_0_ring_emit_pipeline_sync */
8547                 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 +
8548                 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 +
8549                 2 + /* gfx_v10_0_ring_emit_vm_flush */
8550                 8 + 8 + 8 + /* gfx_v10_0_ring_emit_fence x3 for user fence, vm fence */
8551                 8, /* gfx_v10_0_emit_mem_sync */
8552         .emit_ib_size = 7, /* gfx_v10_0_ring_emit_ib_compute */
8553         .emit_ib = gfx_v10_0_ring_emit_ib_compute,
8554         .emit_fence = gfx_v10_0_ring_emit_fence,
8555         .emit_pipeline_sync = gfx_v10_0_ring_emit_pipeline_sync,
8556         .emit_vm_flush = gfx_v10_0_ring_emit_vm_flush,
8557         .emit_gds_switch = gfx_v10_0_ring_emit_gds_switch,
8558         .emit_hdp_flush = gfx_v10_0_ring_emit_hdp_flush,
8559         .test_ring = gfx_v10_0_ring_test_ring,
8560         .test_ib = gfx_v10_0_ring_test_ib,
8561         .insert_nop = amdgpu_ring_insert_nop,
8562         .pad_ib = amdgpu_ring_generic_pad_ib,
8563         .emit_wreg = gfx_v10_0_ring_emit_wreg,
8564         .emit_reg_wait = gfx_v10_0_ring_emit_reg_wait,
8565         .emit_reg_write_reg_wait = gfx_v10_0_ring_emit_reg_write_reg_wait,
8566         .emit_mem_sync = gfx_v10_0_emit_mem_sync,
8567 };
8568
8569 static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_kiq = {
8570         .type = AMDGPU_RING_TYPE_KIQ,
8571         .align_mask = 0xff,
8572         .nop = PACKET3(PACKET3_NOP, 0x3FFF),
8573         .support_64bit_ptrs = true,
8574         .vmhub = AMDGPU_GFXHUB_0,
8575         .get_rptr = gfx_v10_0_ring_get_rptr_compute,
8576         .get_wptr = gfx_v10_0_ring_get_wptr_compute,
8577         .set_wptr = gfx_v10_0_ring_set_wptr_compute,
8578         .emit_frame_size =
8579                 20 + /* gfx_v10_0_ring_emit_gds_switch */
8580                 7 + /* gfx_v10_0_ring_emit_hdp_flush */
8581                 5 + /*hdp invalidate */
8582                 7 + /* gfx_v10_0_ring_emit_pipeline_sync */
8583                 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 +
8584                 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 +
8585                 2 + /* gfx_v10_0_ring_emit_vm_flush */
8586                 8 + 8 + 8, /* gfx_v10_0_ring_emit_fence_kiq x3 for user fence, vm fence */
8587         .emit_ib_size = 7, /* gfx_v10_0_ring_emit_ib_compute */
8588         .emit_ib = gfx_v10_0_ring_emit_ib_compute,
8589         .emit_fence = gfx_v10_0_ring_emit_fence_kiq,
8590         .test_ring = gfx_v10_0_ring_test_ring,
8591         .test_ib = gfx_v10_0_ring_test_ib,
8592         .insert_nop = amdgpu_ring_insert_nop,
8593         .pad_ib = amdgpu_ring_generic_pad_ib,
8594         .emit_rreg = gfx_v10_0_ring_emit_rreg,
8595         .emit_wreg = gfx_v10_0_ring_emit_wreg,
8596         .emit_reg_wait = gfx_v10_0_ring_emit_reg_wait,
8597         .emit_reg_write_reg_wait = gfx_v10_0_ring_emit_reg_write_reg_wait,
8598 };
8599
8600 static void gfx_v10_0_set_ring_funcs(struct amdgpu_device *adev)
8601 {
8602         int i;
8603
8604         adev->gfx.kiq.ring.funcs = &gfx_v10_0_ring_funcs_kiq;
8605
8606         for (i = 0; i < adev->gfx.num_gfx_rings; i++)
8607                 adev->gfx.gfx_ring[i].funcs = &gfx_v10_0_ring_funcs_gfx;
8608
8609         for (i = 0; i < adev->gfx.num_compute_rings; i++)
8610                 adev->gfx.compute_ring[i].funcs = &gfx_v10_0_ring_funcs_compute;
8611 }
8612
8613 static const struct amdgpu_irq_src_funcs gfx_v10_0_eop_irq_funcs = {
8614         .set = gfx_v10_0_set_eop_interrupt_state,
8615         .process = gfx_v10_0_eop_irq,
8616 };
8617
8618 static const struct amdgpu_irq_src_funcs gfx_v10_0_priv_reg_irq_funcs = {
8619         .set = gfx_v10_0_set_priv_reg_fault_state,
8620         .process = gfx_v10_0_priv_reg_irq,
8621 };
8622
8623 static const struct amdgpu_irq_src_funcs gfx_v10_0_priv_inst_irq_funcs = {
8624         .set = gfx_v10_0_set_priv_inst_fault_state,
8625         .process = gfx_v10_0_priv_inst_irq,
8626 };
8627
8628 static const struct amdgpu_irq_src_funcs gfx_v10_0_kiq_irq_funcs = {
8629         .set = gfx_v10_0_kiq_set_interrupt_state,
8630         .process = gfx_v10_0_kiq_irq,
8631 };
8632
8633 static void gfx_v10_0_set_irq_funcs(struct amdgpu_device *adev)
8634 {
8635         adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST;
8636         adev->gfx.eop_irq.funcs = &gfx_v10_0_eop_irq_funcs;
8637
8638         adev->gfx.kiq.irq.num_types = AMDGPU_CP_KIQ_IRQ_LAST;
8639         adev->gfx.kiq.irq.funcs = &gfx_v10_0_kiq_irq_funcs;
8640
8641         adev->gfx.priv_reg_irq.num_types = 1;
8642         adev->gfx.priv_reg_irq.funcs = &gfx_v10_0_priv_reg_irq_funcs;
8643
8644         adev->gfx.priv_inst_irq.num_types = 1;
8645         adev->gfx.priv_inst_irq.funcs = &gfx_v10_0_priv_inst_irq_funcs;
8646 }
8647
8648 static void gfx_v10_0_set_rlc_funcs(struct amdgpu_device *adev)
8649 {
8650         switch (adev->asic_type) {
8651         case CHIP_NAVI10:
8652         case CHIP_NAVI14:
8653         case CHIP_SIENNA_CICHLID:
8654         case CHIP_NAVY_FLOUNDER:
8655                 adev->gfx.rlc.funcs = &gfx_v10_0_rlc_funcs;
8656                 break;
8657         case CHIP_NAVI12:
8658                 adev->gfx.rlc.funcs = &gfx_v10_0_rlc_funcs_sriov;
8659                 break;
8660         default:
8661                 break;
8662         }
8663 }
8664
8665 static void gfx_v10_0_set_gds_init(struct amdgpu_device *adev)
8666 {
8667         unsigned total_cu = adev->gfx.config.max_cu_per_sh *
8668                             adev->gfx.config.max_sh_per_se *
8669                             adev->gfx.config.max_shader_engines;
8670
8671         adev->gds.gds_size = 0x10000;
8672         adev->gds.gds_compute_max_wave_id = total_cu * 32 - 1;
8673         adev->gds.gws_size = 64;
8674         adev->gds.oa_size = 16;
8675 }
8676
8677 static void gfx_v10_0_set_user_wgp_inactive_bitmap_per_sh(struct amdgpu_device *adev,
8678                                                           u32 bitmap)
8679 {
8680         u32 data;
8681
8682         if (!bitmap)
8683                 return;
8684
8685         data = bitmap << GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT;
8686         data &= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK;
8687
8688         WREG32_SOC15(GC, 0, mmGC_USER_SHADER_ARRAY_CONFIG, data);
8689 }
8690
8691 static u32 gfx_v10_0_get_wgp_active_bitmap_per_sh(struct amdgpu_device *adev)
8692 {
8693         u32 data, wgp_bitmask;
8694         data = RREG32_SOC15(GC, 0, mmCC_GC_SHADER_ARRAY_CONFIG);
8695         data |= RREG32_SOC15(GC, 0, mmGC_USER_SHADER_ARRAY_CONFIG);
8696
8697         data &= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK;
8698         data >>= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT;
8699
8700         wgp_bitmask =
8701                 amdgpu_gfx_create_bitmask(adev->gfx.config.max_cu_per_sh >> 1);
8702
8703         return (~data) & wgp_bitmask;
8704 }
8705
8706 static u32 gfx_v10_0_get_cu_active_bitmap_per_sh(struct amdgpu_device *adev)
8707 {
8708         u32 wgp_idx, wgp_active_bitmap;
8709         u32 cu_bitmap_per_wgp, cu_active_bitmap;
8710
8711         wgp_active_bitmap = gfx_v10_0_get_wgp_active_bitmap_per_sh(adev);
8712         cu_active_bitmap = 0;
8713
8714         for (wgp_idx = 0; wgp_idx < 16; wgp_idx++) {
8715                 /* if there is one WGP enabled, it means 2 CUs will be enabled */
8716                 cu_bitmap_per_wgp = 3 << (2 * wgp_idx);
8717                 if (wgp_active_bitmap & (1 << wgp_idx))
8718                         cu_active_bitmap |= cu_bitmap_per_wgp;
8719         }
8720
8721         return cu_active_bitmap;
8722 }
8723
8724 static int gfx_v10_0_get_cu_info(struct amdgpu_device *adev,
8725                                  struct amdgpu_cu_info *cu_info)
8726 {
8727         int i, j, k, counter, active_cu_number = 0;
8728         u32 mask, bitmap, ao_bitmap, ao_cu_mask = 0;
8729         unsigned disable_masks[4 * 2];
8730
8731         if (!adev || !cu_info)
8732                 return -EINVAL;
8733
8734         amdgpu_gfx_parse_disable_cu(disable_masks, 4, 2);
8735
8736         mutex_lock(&adev->grbm_idx_mutex);
8737         for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
8738                 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
8739                         mask = 1;
8740                         ao_bitmap = 0;
8741                         counter = 0;
8742                         gfx_v10_0_select_se_sh(adev, i, j, 0xffffffff);
8743                         if (i < 4 && j < 2)
8744                                 gfx_v10_0_set_user_wgp_inactive_bitmap_per_sh(
8745                                         adev, disable_masks[i * 2 + j]);
8746                         bitmap = gfx_v10_0_get_cu_active_bitmap_per_sh(adev);
8747                         cu_info->bitmap[i][j] = bitmap;
8748
8749                         for (k = 0; k < adev->gfx.config.max_cu_per_sh; k++) {
8750                                 if (bitmap & mask) {
8751                                         if (counter < adev->gfx.config.max_cu_per_sh)
8752                                                 ao_bitmap |= mask;
8753                                         counter++;
8754                                 }
8755                                 mask <<= 1;
8756                         }
8757                         active_cu_number += counter;
8758                         if (i < 2 && j < 2)
8759                                 ao_cu_mask |= (ao_bitmap << (i * 16 + j * 8));
8760                         cu_info->ao_cu_bitmap[i][j] = ao_bitmap;
8761                 }
8762         }
8763         gfx_v10_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
8764         mutex_unlock(&adev->grbm_idx_mutex);
8765
8766         cu_info->number = active_cu_number;
8767         cu_info->ao_cu_mask = ao_cu_mask;
8768         cu_info->simd_per_cu = NUM_SIMD_PER_CU;
8769
8770         return 0;
8771 }
8772
8773 const struct amdgpu_ip_block_version gfx_v10_0_ip_block =
8774 {
8775         .type = AMD_IP_BLOCK_TYPE_GFX,
8776         .major = 10,
8777         .minor = 0,
8778         .rev = 0,
8779         .funcs = &gfx_v10_0_ip_funcs,
8780 };