drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

   1 /*
   2  * Copyright 2019 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #include <linux/delay.h>
  25 #include <linux/kernel.h>
  26 #include <linux/firmware.h>
  27 #include <linux/module.h>
  28 #include <linux/pci.h>
  29 #include "amdgpu.h"
  30 #include "amdgpu_gfx.h"
  31 #include "amdgpu_psp.h"
  32 #include "nv.h"
  33 #include "nvd.h"
  34
  35 #include "gc/gc_10_1_0_offset.h"
  36 #include "gc/gc_10_1_0_sh_mask.h"
  37 #include "smuio/smuio_11_0_0_offset.h"
  38 #include "smuio/smuio_11_0_0_sh_mask.h"
  39 #include "navi10_enum.h"
  40 #include "ivsrcid/gfx/irqsrcs_gfx_10_1.h"
  41
  42 #include "soc15.h"
  43 #include "soc15d.h"
  44 #include "soc15_common.h"
  45 #include "clearstate_gfx10.h"
  46 #include "v10_structs.h"
  47 #include "gfx_v10_0.h"
  48 #include "nbio_v2_3.h"
  49
  50 /**
  51  * Navi10 has two graphic rings to share each graphic pipe.
  52  * 1. Primary ring
  53  * 2. Async ring
  54  */
  55 #define GFX10_NUM_GFX_RINGS_NV1X        1
  56 #define GFX10_NUM_GFX_RINGS_Sienna_Cichlid      1
  57 #define GFX10_MEC_HPD_SIZE      2048
  58
  59 #define F32_CE_PROGRAM_RAM_SIZE         65536
  60 #define RLCG_UCODE_LOADING_START_ADDRESS        0x00002000L
  61
  62 #define mmCGTT_GS_NGG_CLK_CTRL  0x5087
  63 #define mmCGTT_GS_NGG_CLK_CTRL_BASE_IDX 1
  64 #define mmCGTT_SPI_RA0_CLK_CTRL 0x507a
  65 #define mmCGTT_SPI_RA0_CLK_CTRL_BASE_IDX 1
  66 #define mmCGTT_SPI_RA1_CLK_CTRL 0x507b
  67 #define mmCGTT_SPI_RA1_CLK_CTRL_BASE_IDX 1
  68
  69 #define GB_ADDR_CONFIG__NUM_PKRS__SHIFT                                                                       0x8
  70 #define GB_ADDR_CONFIG__NUM_PKRS_MASK                                                                         0x00000700L
  71
  72 #define mmCGTS_TCC_DISABLE_gc_10_3                 0x5006
  73 #define mmCGTS_TCC_DISABLE_gc_10_3_BASE_IDX        1
  74 #define mmCGTS_USER_TCC_DISABLE_gc_10_3            0x5007
  75 #define mmCGTS_USER_TCC_DISABLE_gc_10_3_BASE_IDX   1
  76
  77 #define mmCP_MEC_CNTL_Sienna_Cichlid                      0x0f55
  78 #define mmCP_MEC_CNTL_Sienna_Cichlid_BASE_IDX             0
  79 #define mmRLC_SAFE_MODE_Sienna_Cichlid                  0x4ca0
  80 #define mmRLC_SAFE_MODE_Sienna_Cichlid_BASE_IDX         1
  81 #define mmRLC_CP_SCHEDULERS_Sienna_Cichlid              0x4ca1
  82 #define mmRLC_CP_SCHEDULERS_Sienna_Cichlid_BASE_IDX     1
  83 #define mmSPI_CONFIG_CNTL_Sienna_Cichlid                        0x11ec
  84 #define mmSPI_CONFIG_CNTL_Sienna_Cichlid_BASE_IDX               0
  85 #define mmVGT_ESGS_RING_SIZE_Sienna_Cichlid             0x0fc1
  86 #define mmVGT_ESGS_RING_SIZE_Sienna_Cichlid_BASE_IDX    0
  87 #define mmVGT_GSVS_RING_SIZE_Sienna_Cichlid             0x0fc2
  88 #define mmVGT_GSVS_RING_SIZE_Sienna_Cichlid_BASE_IDX    0
  89 #define mmVGT_TF_RING_SIZE_Sienna_Cichlid                       0x0fc3
  90 #define mmVGT_TF_RING_SIZE_Sienna_Cichlid_BASE_IDX      0
  91 #define mmVGT_HS_OFFCHIP_PARAM_Sienna_Cichlid           0x0fc4
  92 #define mmVGT_HS_OFFCHIP_PARAM_Sienna_Cichlid_BASE_IDX  0
  93 #define mmVGT_TF_MEMORY_BASE_Sienna_Cichlid             0x0fc5
  94 #define mmVGT_TF_MEMORY_BASE_Sienna_Cichlid_BASE_IDX    0
  95 #define mmVGT_TF_MEMORY_BASE_HI_Sienna_Cichlid          0x0fc6
  96 #define mmVGT_TF_MEMORY_BASE_HI_Sienna_Cichlid_BASE_IDX 0
  97 #define GRBM_STATUS2__RLC_BUSY_Sienna_Cichlid__SHIFT    0x1a
  98 #define GRBM_STATUS2__RLC_BUSY_Sienna_Cichlid_MASK      0x04000000L
  99 #define CP_RB_DOORBELL_RANGE_LOWER__DOORBELL_RANGE_LOWER_Sienna_Cichlid_MASK    0x00000FFCL
 100 #define CP_RB_DOORBELL_RANGE_LOWER__DOORBELL_RANGE_LOWER_Sienna_Cichlid__SHIFT  0x2
 101 #define CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_Sienna_Cichlid_MASK    0x00000FFCL
 102 #define mmGCR_GENERAL_CNTL_Sienna_Cichlid                       0x1580
 103 #define mmGCR_GENERAL_CNTL_Sienna_Cichlid_BASE_IDX      0
 104
 105 #define mmGOLDEN_TSC_COUNT_UPPER_Vangogh                0x0025
 106 #define mmGOLDEN_TSC_COUNT_UPPER_Vangogh_BASE_IDX       1
 107 #define mmGOLDEN_TSC_COUNT_LOWER_Vangogh                0x0026
 108 #define mmGOLDEN_TSC_COUNT_LOWER_Vangogh_BASE_IDX       1
 109 #define mmSPI_CONFIG_CNTL_1_Vangogh              0x2441
 110 #define mmSPI_CONFIG_CNTL_1_Vangogh_BASE_IDX     1
 111 #define mmVGT_TF_MEMORY_BASE_HI_Vangogh          0x2261
 112 #define mmVGT_TF_MEMORY_BASE_HI_Vangogh_BASE_IDX 1
 113 #define mmVGT_HS_OFFCHIP_PARAM_Vangogh           0x224f
 114 #define mmVGT_HS_OFFCHIP_PARAM_Vangogh_BASE_IDX  1
 115 #define mmVGT_TF_RING_SIZE_Vangogh               0x224e
 116 #define mmVGT_TF_RING_SIZE_Vangogh_BASE_IDX      1
 117 #define mmVGT_GSVS_RING_SIZE_Vangogh             0x2241
 118 #define mmVGT_GSVS_RING_SIZE_Vangogh_BASE_IDX    1
 119 #define mmVGT_TF_MEMORY_BASE_Vangogh             0x2250
 120 #define mmVGT_TF_MEMORY_BASE_Vangogh_BASE_IDX    1
 121 #define mmVGT_ESGS_RING_SIZE_Vangogh             0x2240
 122 #define mmVGT_ESGS_RING_SIZE_Vangogh_BASE_IDX    1
 123 #define mmSPI_CONFIG_CNTL_Vangogh                0x2440
 124 #define mmSPI_CONFIG_CNTL_Vangogh_BASE_IDX       1
 125 #define mmGCR_GENERAL_CNTL_Vangogh               0x1580
 126 #define mmGCR_GENERAL_CNTL_Vangogh_BASE_IDX      0
 127 #define RLC_PG_DELAY_3__CGCG_ACTIVE_BEFORE_CGPG_MASK_Vangogh   0x0000FFFFL
 128
 129 #define mmCP_HYP_PFP_UCODE_ADDR                 0x5814
 130 #define mmCP_HYP_PFP_UCODE_ADDR_BASE_IDX        1
 131 #define mmCP_HYP_PFP_UCODE_DATA                 0x5815
 132 #define mmCP_HYP_PFP_UCODE_DATA_BASE_IDX        1
 133 #define mmCP_HYP_CE_UCODE_ADDR                  0x5818
 134 #define mmCP_HYP_CE_UCODE_ADDR_BASE_IDX         1
 135 #define mmCP_HYP_CE_UCODE_DATA                  0x5819
 136 #define mmCP_HYP_CE_UCODE_DATA_BASE_IDX         1
 137 #define mmCP_HYP_ME_UCODE_ADDR                  0x5816
 138 #define mmCP_HYP_ME_UCODE_ADDR_BASE_IDX         1
 139 #define mmCP_HYP_ME_UCODE_DATA                  0x5817
 140 #define mmCP_HYP_ME_UCODE_DATA_BASE_IDX         1
 141
 142 #define mmCPG_PSP_DEBUG                         0x5c10
 143 #define mmCPG_PSP_DEBUG_BASE_IDX                1
 144 #define mmCPC_PSP_DEBUG                         0x5c11
 145 #define mmCPC_PSP_DEBUG_BASE_IDX                1
 146 #define CPC_PSP_DEBUG__GPA_OVERRIDE_MASK        0x00000008L
 147 #define CPG_PSP_DEBUG__GPA_OVERRIDE_MASK        0x00000008L
 148
 149 //CC_GC_SA_UNIT_DISABLE
 150 #define mmCC_GC_SA_UNIT_DISABLE                 0x0fe9
 151 #define mmCC_GC_SA_UNIT_DISABLE_BASE_IDX        0
 152 #define CC_GC_SA_UNIT_DISABLE__SA_DISABLE__SHIFT        0x8
 153 #define CC_GC_SA_UNIT_DISABLE__SA_DISABLE_MASK          0x0000FF00L
 154 //GC_USER_SA_UNIT_DISABLE
 155 #define mmGC_USER_SA_UNIT_DISABLE               0x0fea
 156 #define mmGC_USER_SA_UNIT_DISABLE_BASE_IDX      0
 157 #define GC_USER_SA_UNIT_DISABLE__SA_DISABLE__SHIFT      0x8
 158 #define GC_USER_SA_UNIT_DISABLE__SA_DISABLE_MASK        0x0000FF00L
 159 //PA_SC_ENHANCE_3
 160 #define mmPA_SC_ENHANCE_3                       0x1085
 161 #define mmPA_SC_ENHANCE_3_BASE_IDX              0
 162 #define PA_SC_ENHANCE_3__FORCE_PBB_WORKLOAD_MODE_TO_ZERO__SHIFT 0x3
 163 #define PA_SC_ENHANCE_3__FORCE_PBB_WORKLOAD_MODE_TO_ZERO_MASK   0x00000008L
 164
 165 #define mmCGTT_SPI_CS_CLK_CTRL                  0x507c
 166 #define mmCGTT_SPI_CS_CLK_CTRL_BASE_IDX         1
 167
 168 #define mmGCUTCL2_CGTT_CLK_CTRL_Sienna_Cichlid          0x16f3
 169 #define mmGCUTCL2_CGTT_CLK_CTRL_Sienna_Cichlid_BASE_IDX 0
 170 #define mmGCVM_L2_CGTT_CLK_CTRL_Sienna_Cichlid          0x15db
 171 #define mmGCVM_L2_CGTT_CLK_CTRL_Sienna_Cichlid_BASE_IDX 0
 172
 173 #define mmGC_THROTTLE_CTRL_Sienna_Cichlid              0x2030
 174 #define mmGC_THROTTLE_CTRL_Sienna_Cichlid_BASE_IDX     0
 175
 176 #define GFX_RLCG_GC_WRITE_OLD   (0x8 << 28)
 177 #define GFX_RLCG_GC_WRITE       (0x0 << 28)
 178 #define GFX_RLCG_GC_READ        (0x1 << 28)
 179 #define GFX_RLCG_MMHUB_WRITE    (0x2 << 28)
 180
 181 MODULE_FIRMWARE("amdgpu/navi10_ce.bin");
 182 MODULE_FIRMWARE("amdgpu/navi10_pfp.bin");
 183 MODULE_FIRMWARE("amdgpu/navi10_me.bin");
 184 MODULE_FIRMWARE("amdgpu/navi10_mec.bin");
 185 MODULE_FIRMWARE("amdgpu/navi10_mec2.bin");
 186 MODULE_FIRMWARE("amdgpu/navi10_rlc.bin");
 187
 188 MODULE_FIRMWARE("amdgpu/navi14_ce_wks.bin");
 189 MODULE_FIRMWARE("amdgpu/navi14_pfp_wks.bin");
 190 MODULE_FIRMWARE("amdgpu/navi14_me_wks.bin");
 191 MODULE_FIRMWARE("amdgpu/navi14_mec_wks.bin");
 192 MODULE_FIRMWARE("amdgpu/navi14_mec2_wks.bin");
 193 MODULE_FIRMWARE("amdgpu/navi14_ce.bin");
 194 MODULE_FIRMWARE("amdgpu/navi14_pfp.bin");
 195 MODULE_FIRMWARE("amdgpu/navi14_me.bin");
 196 MODULE_FIRMWARE("amdgpu/navi14_mec.bin");
 197 MODULE_FIRMWARE("amdgpu/navi14_mec2.bin");
 198 MODULE_FIRMWARE("amdgpu/navi14_rlc.bin");
 199
 200 MODULE_FIRMWARE("amdgpu/navi12_ce.bin");
 201 MODULE_FIRMWARE("amdgpu/navi12_pfp.bin");
 202 MODULE_FIRMWARE("amdgpu/navi12_me.bin");
 203 MODULE_FIRMWARE("amdgpu/navi12_mec.bin");
 204 MODULE_FIRMWARE("amdgpu/navi12_mec2.bin");
 205 MODULE_FIRMWARE("amdgpu/navi12_rlc.bin");
 206
 207 MODULE_FIRMWARE("amdgpu/sienna_cichlid_ce.bin");
 208 MODULE_FIRMWARE("amdgpu/sienna_cichlid_pfp.bin");
 209 MODULE_FIRMWARE("amdgpu/sienna_cichlid_me.bin");
 210 MODULE_FIRMWARE("amdgpu/sienna_cichlid_mec.bin");
 211 MODULE_FIRMWARE("amdgpu/sienna_cichlid_mec2.bin");
 212 MODULE_FIRMWARE("amdgpu/sienna_cichlid_rlc.bin");
 213
 214 MODULE_FIRMWARE("amdgpu/navy_flounder_ce.bin");
 215 MODULE_FIRMWARE("amdgpu/navy_flounder_pfp.bin");
 216 MODULE_FIRMWARE("amdgpu/navy_flounder_me.bin");
 217 MODULE_FIRMWARE("amdgpu/navy_flounder_mec.bin");
 218 MODULE_FIRMWARE("amdgpu/navy_flounder_mec2.bin");
 219 MODULE_FIRMWARE("amdgpu/navy_flounder_rlc.bin");
 220
 221 MODULE_FIRMWARE("amdgpu/vangogh_ce.bin");
 222 MODULE_FIRMWARE("amdgpu/vangogh_pfp.bin");
 223 MODULE_FIRMWARE("amdgpu/vangogh_me.bin");
 224 MODULE_FIRMWARE("amdgpu/vangogh_mec.bin");
 225 MODULE_FIRMWARE("amdgpu/vangogh_mec2.bin");
 226 MODULE_FIRMWARE("amdgpu/vangogh_rlc.bin");
 227
 228 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_ce.bin");
 229 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_pfp.bin");
 230 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_me.bin");
 231 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_mec.bin");
 232 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_mec2.bin");
 233 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_rlc.bin");
 234
 235 MODULE_FIRMWARE("amdgpu/beige_goby_ce.bin");
 236 MODULE_FIRMWARE("amdgpu/beige_goby_pfp.bin");
 237 MODULE_FIRMWARE("amdgpu/beige_goby_me.bin");
 238 MODULE_FIRMWARE("amdgpu/beige_goby_mec.bin");
 239 MODULE_FIRMWARE("amdgpu/beige_goby_mec2.bin");
 240 MODULE_FIRMWARE("amdgpu/beige_goby_rlc.bin");
 241
 242 static const struct soc15_reg_golden golden_settings_gc_10_1[] =
 243 {
 244         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0xffffffff, 0x00400014),
 245         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_CPF_CLK_CTRL, 0xfcff8fff, 0xf8000100),
 246         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xcd000000, 0x0d000100),
 247         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQ_CLK_CTRL, 0x60000ff0, 0x60000100),
 248         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQG_CLK_CTRL, 0x40000000, 0x40000100),
 249         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xffff8fff, 0xffff8100),
 250         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_WD_CLK_CTRL, 0xfeff8fff, 0xfeff8100),
 251         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
 252         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_VC5_ENABLE, 0x00000002, 0x00000000),
 253         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0x000007ff, 0x000005ff),
 254         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG, 0x20000000, 0x20000000),
 255         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xffffffff, 0x00000420),
 256         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0x00000200, 0x00000200),
 257         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0x07900000, 0x04900000),
 258         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DFSM_TILES_IN_FLIGHT, 0x0000ffff, 0x0000003f),
 259         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_LAST_OF_BURST_CONFIG, 0xffffffff, 0x03860204),
 260         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff0ffff, 0x00000500),
 261         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PRIV_CONTROL, 0x000007ff, 0x000001fe),
 262         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
 263         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x10321032),
 264         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x02310231),
 265         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
 266         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
 267         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CGTT_SCLK_CTRL, 0x10000000, 0x10000100),
 268         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL2, 0xffffffff, 0x1402002f),
 269         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xffff9fff, 0x00001188),
 270         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
 271         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x08000009),
 272         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0x00400000, 0x04440000),
 273         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0x00000800, 0x00000820),
 274         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000),
 275         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0xffffffff, 0xffff3101),
 276         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0x001f0000, 0x00070104),
 277         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ALU_CLK_CTRL, 0xffffffff, 0xffffffff),
 278         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x00000100, 0x00000130),
 279         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0xffffffff, 0xffffffff),
 280         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
 281         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CNTL, 0x60000010, 0x479c0010),
 282         SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CGTT_CLK_CTRL, 0xfeff0fff, 0x40000100),
 283         SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0x00c00000, 0x00c00000)
 284 };
 285
 286 static const struct soc15_reg_golden golden_settings_gc_10_0_nv10[] =
 287 {
 288         /* Pending on emulation bring up */
 289 };
 290
 291 static const struct soc15_reg_golden golden_settings_gc_rlc_spm_10_0_nv10[] =
 292 {
 293         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xe0000000, 0x0),
 294         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 295         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
 296         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 297         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
 298         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 299         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
 300         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 301         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
 302         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 303         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
 304         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 305         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
 306         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 307         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
 308         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 309         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 310         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 311         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8),
 312         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 313         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
 314         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 315         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc),
 316         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 317         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
 318         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 319         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0),
 320         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 321         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
 322         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 323         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4),
 324         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 325         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
 326         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 327         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
 328         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 329         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
 330         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 331         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
 332         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 333         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
 334         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 335         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
 336         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 337         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
 338         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 339         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
 340         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 341         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
 342         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 343         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
 344         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 345         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
 346         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 347         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
 348         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 349         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
 350         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 351         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
 352         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 353         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
 354         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 355         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
 356         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 357         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
 358         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 359         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
 360         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 361         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
 362         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 363         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0),
 364         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 365         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
 366         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 367         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4),
 368         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 369         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
 370         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 371         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8),
 372         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 373         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 374         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 375         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc),
 376         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 377         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
 378         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 379         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0),
 380         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 381         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 382         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 383         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4),
 384         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 385         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 386         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 387         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90),
 388         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 389         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
 390         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 391         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94),
 392         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 393         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
 394         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 395         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98),
 396         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 397         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
 398         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 399         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c),
 400         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 401         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
 402         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 403         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0),
 404         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 405         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
 406         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 407         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4),
 408         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 409         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
 410         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 411         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8),
 412         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 413         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
 414         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 415         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac),
 416         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 417         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
 418         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 419         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
 420         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 421         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
 422         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 423         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
 424         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 425         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
 426         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 427         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
 428         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 429         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
 430         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 431         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
 432         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 433         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
 434         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 435         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
 436         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 437         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
 438         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 439         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
 440         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 441         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 442         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 443         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
 444         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 445         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
 446         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 447         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
 448         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 449         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
 450         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 451         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
 452         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 453         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
 454         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 455         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
 456         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 457         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
 458         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 459         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
 460         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 461         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
 462         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 463         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
 464         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 465         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
 466         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 467         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
 468         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 469         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
 470         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 471         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
 472         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 473         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
 474         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 475         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
 476         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 477         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
 478         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 479         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
 480         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 481         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
 482         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 483         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
 484         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 485         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
 486         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 487         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
 488         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 489         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
 490         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 491         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
 492         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 493         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
 494         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 495         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
 496         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 497         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
 498         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 499         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
 500         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 501         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
 502         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 503         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
 504         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 505         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
 506         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 507         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
 508         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 509         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
 510         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 511         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c),
 512         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 513         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
 514         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 515         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
 516         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 517         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 518         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 519         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
 520         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 521         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
 522         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 523         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
 524         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 525         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
 526         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 527         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
 528         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 529         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
 530         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 531         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
 532         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 533         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
 534         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 535         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
 536         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 537         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 538         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 539         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
 540         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 541         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 542         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 543         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
 544         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 545         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
 546         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 547         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
 548         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 549         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
 550         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 551         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
 552         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 553         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 554         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 555         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
 556         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 557         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 558         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 559         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
 560         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 561         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
 562         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 563         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
 564         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 565         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
 566         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 567         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
 568         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 569         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 570         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 571         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
 572         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 573         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 574         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 575         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
 576         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 577         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
 578         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 579         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
 580         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 581         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
 582         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 583         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
 584         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 585         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
 586         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 587         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
 588         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 589         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
 590         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 591         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
 592         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 593         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 594         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 595         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
 596         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 597         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 598         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 599         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
 600         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 601         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 602         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 603         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
 604         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 605         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 606         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 607         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
 608         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 609         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 610         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 611         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
 612         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 613         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 614         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 615         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
 616         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 617         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 618         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 619         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
 620         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 621         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 622         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 623         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
 624         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 625         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
 626         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 627         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
 628         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 629         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
 630         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 631         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
 632         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 633         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
 634         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 635         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
 636         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 637         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
 638         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 639         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
 640         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 641         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
 642         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 643         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
 644         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 645         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
 646         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 647         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
 648         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 649         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
 650         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 651         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
 652         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 653         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
 654         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 655         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
 656         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 657         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
 658         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 659         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
 660         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 661         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
 662         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 663         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
 664         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 665         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17),
 666         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 667         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
 668         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 669         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17),
 670         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 671         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
 672         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 673         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 674         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 675         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
 676         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 677         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 678         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 679         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
 680         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 681         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
 682         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 683         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
 684         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 685         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
 686         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 687         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
 688         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 689         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
 690         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 691         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
 692         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 693         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
 694         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 695         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
 696         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 697         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 698         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 699         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
 700         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 701         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 702         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 703         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
 704         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 705         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 706         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 707         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
 708         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 709         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 710         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 711         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
 712         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 713         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
 714         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 715         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
 716         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 717         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
 718         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 719         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
 720         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 721         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
 722         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 723         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
 724         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 725         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
 726         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 727         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
 728         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 729         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 730         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 731         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
 732         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 733         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 734         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 735         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
 736         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 737         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 738         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 739         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
 740         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 741         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 742         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 743         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
 744         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 745         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 746         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 747         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
 748         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 749         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 750         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 751         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
 752         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 753         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 754         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 755         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
 756         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 757         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 758         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 759         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
 760         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 761         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 762         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 763         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
 764         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 765         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 766         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 767         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90),
 768         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 769         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
 770         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 771         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90),
 772         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 773         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
 774         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 775         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94),
 776         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 777         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
 778         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 779         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94),
 780         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 781         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
 782         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 783         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0),
 784         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 785         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
 786         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 787         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0),
 788         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 789         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
 790         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 791         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4),
 792         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 793         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
 794         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 795         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4),
 796         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 797         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
 798         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 799         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98),
 800         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 801         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
 802         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 803         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98),
 804         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 805         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
 806         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 807         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c),
 808         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 809         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
 810         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 811         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c),
 812         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 813         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
 814         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 815         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8),
 816         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 817         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 818         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 819         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8),
 820         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 821         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 822         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 823         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac),
 824         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 825         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 826         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 827         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac),
 828         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 829         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 830         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 831         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8),
 832         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 833         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
 834         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 835         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8),
 836         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 837         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
 838         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 839         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc),
 840         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 841         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
 842         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 843         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc),
 844         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 845         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
 846         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 847         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0),
 848         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 849         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 850         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 851         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0),
 852         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 853         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 854         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 855         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4),
 856         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 857         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 858         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 859         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4),
 860         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 861         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 862         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 863         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0),
 864         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 865         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
 866         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 867         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0),
 868         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 869         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
 870         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 871         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4),
 872         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 873         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 874         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 875         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4),
 876         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 877         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 878         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 879         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0),
 880         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 881         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
 882         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 883         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0),
 884         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 885         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
 886         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 887         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4),
 888         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 889         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
 890         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 891         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4),
 892         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 893         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
 894         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 895         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8),
 896         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 897         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
 898         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 899         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8),
 900         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 901         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
 902         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 903         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc),
 904         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 905         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
 906         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 907         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc),
 908         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 909         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
 910         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 911         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8),
 912         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 913         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 914         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 915         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8),
 916         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 917         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 918         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 919         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec),
 920         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 921         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 922         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 923         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec),
 924         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 925         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 926         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 927         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0),
 928         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 929         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
 930         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 931         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0),
 932         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 933         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
 934         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 935         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4),
 936         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 937         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
 938         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 939         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4),
 940         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 941         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
 942         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 943         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8),
 944         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 945         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 946         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 947         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8),
 948         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 949         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 950         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 951         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xfc),
 952         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 953         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 954         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 955         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xfc),
 956         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 957         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 958         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 959         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100),
 960         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 961         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 962         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 963         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100),
 964         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 965         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 966         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 967         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104),
 968         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 969         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
 970         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 971         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104),
 972         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 973         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
 974         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 975         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0),
 976         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 977         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
 978         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 979         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0),
 980         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 981         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
 982         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 983         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118),
 984         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 985         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
 986         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 987         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118),
 988         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 989         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
 990         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 991         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c),
 992         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 993         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
 994         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 995         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c),
 996         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 997         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
 998         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 999         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120),
1000         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1001         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
1002         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1003         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120),
1004         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1005         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
1006         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1007         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124),
1008         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1009         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
1010         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1011         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124),
1012         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1013         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
1014         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1015         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc),
1016         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1017         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
1018         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1019         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc),
1020         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1021         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
1022         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1023         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110),
1024         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1025         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1026         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1027         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110),
1028         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1029         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1030         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1031         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114),
1032         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1033         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1034         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1035         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114),
1036         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1037         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1038         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1039         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108),
1040         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1041         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1042         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1043         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108),
1044         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1045         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1046         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1047         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c),
1048         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1049         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1050         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1051         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c),
1052         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1053         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1054         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1055         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8),
1056         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1057         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17),
1058         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1059         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8),
1060         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1061         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17),
1062         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1063         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128),
1064         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1065         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
1066         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1067         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128),
1068         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1069         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
1070         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1071         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c),
1072         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1073         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1074         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1075         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c),
1076         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1077         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1078         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1079         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138),
1080         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1081         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1082         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1083         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138),
1084         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1085         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1086         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1087         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c),
1088         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1089         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1090         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1091         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c),
1092         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1093         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1094         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1095         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130),
1096         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1097         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1098         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1099         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130),
1100         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1101         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1102         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1103         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134),
1104         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1105         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1106         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1107         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134),
1108         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1109         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1110         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1111         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140),
1112         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1113         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1114         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1115         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140),
1116         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1117         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1118         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1119         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144),
1120         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1121         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
1122         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1123         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144),
1124         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1125         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
1126         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1127         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150),
1128         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1129         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1130         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1131         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150),
1132         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1133         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1134         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1135         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154),
1136         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1137         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
1138         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1139         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154),
1140         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1141         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
1142         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1143         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148),
1144         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1145         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1146         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1147         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148),
1148         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1149         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1150         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1151         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c),
1152         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1153         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
1154         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1155         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c),
1156         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1157         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
1158         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1159         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158),
1160         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1161         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
1162         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1163         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158),
1164         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1165         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
1166         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1167         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c),
1168         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1169         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1170         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1171         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c),
1172         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1173         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1174         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1175         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168),
1176         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1177         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1),
1178         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1179         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168),
1180         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1181         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1),
1182         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1183         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c),
1184         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1185         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
1186         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1187         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c),
1188         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1189         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
1190         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1191         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160),
1192         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1193         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
1194         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1195         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160),
1196         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1197         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
1198         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1199         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164),
1200         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1201         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1202         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1203         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164),
1204         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1205         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1206         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1207         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170),
1208         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1209         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
1210         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1211         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170),
1212         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1213         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
1214         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1215         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174),
1216         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1217         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
1218         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1219         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174),
1220         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1221         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
1222         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1223         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180),
1224         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1225         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
1226         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1227         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180),
1228         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1229         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
1230         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1231         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184),
1232         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1233         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1234         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1235         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184),
1236         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1237         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1238         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1239         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178),
1240         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1241         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
1242         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1243         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178),
1244         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1245         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
1246         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1247         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c),
1248         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1249         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
1250         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1251         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c),
1252         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1253         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
1254         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1255         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188),
1256         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1257         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1258         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1259         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188),
1260         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1261         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1262         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1263         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c),
1264         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1265         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
1266         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1267         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c),
1268         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1269         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
1270         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1271         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198),
1272         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1273         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
1274         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1275         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198),
1276         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1277         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
1278         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1279         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c),
1280         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1281         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
1282         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1283         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c),
1284         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1285         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
1286         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1287         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190),
1288         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1289         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1290         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1291         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190),
1292         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1293         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1294         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1295         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194),
1296         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1297         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
1298         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1299         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194),
1300         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1301         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
1302         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1303         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
1304         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1305         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
1306         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1307         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
1308         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1309         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1310         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1311         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
1312         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1313         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
1314         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1315         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
1316         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1317         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
1318         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1319         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
1320         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1321         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1f),
1322         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1323         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
1324         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1325         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1f),
1326         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1327         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
1328         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1329         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
1330         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1331         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_SAMPLE_SKEW, 0x000000FF, 0x19),
1332         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1333         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_MUXSEL_SKEW, 0x000000FF, 0x20),
1334         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1335         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0x5),
1336         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1337         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0xa),
1338         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1339         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x14),
1340         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1341         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x19),
1342         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1343         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_DESER_START_SKEW, 0x000000FF, 0x33),
1344         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xFFFFFFFF, 0xe0000000)
1345 };
1346
1347 static const struct soc15_reg_golden golden_settings_gc_10_1_1[] =
1348 {
1349         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0xffffffff, 0x003c0014),
1350         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_GS_NGG_CLK_CTRL, 0xffff8fff, 0xffff8100),
1351         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_IA_CLK_CTRL, 0xffff0fff, 0xffff0100),
1352         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xcd000000, 0x0d000100),
1353         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQ_CLK_CTRL, 0xf8ff0fff, 0x60000100),
1354         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQG_CLK_CTRL, 0x40000ff0, 0x40000100),
1355         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xffff8fff, 0xffff8100),
1356         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_WD_CLK_CTRL, 0xffff8fff, 0xffff8100),
1357         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
1358         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_VC5_ENABLE, 0x00000002, 0x00000000),
1359         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0x800007ff, 0x000005ff),
1360         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG, 0xffffffff, 0x20000000),
1361         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xffffffff, 0x00000420),
1362         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0x00000200, 0x00000200),
1363         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x04900000),
1364         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DFSM_TILES_IN_FLIGHT, 0x0000ffff, 0x0000003f),
1365         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_LAST_OF_BURST_CONFIG, 0xffffffff, 0x03860204),
1366         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff0ffff, 0x00000500),
1367         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PRIV_CONTROL, 0x000007ff, 0x000001fe),
1368         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
1369         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffe7),
1370         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffe7),
1371         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CGTT_SCLK_CTRL, 0xffff0fff, 0x10000100),
1372         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL2, 0xffffffff, 0x1402002f),
1373         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xffffbfff, 0x00000188),
1374         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
1375         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x08000009),
1376         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0x00400000, 0x04440000),
1377         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0x00000800, 0x00000820),
1378         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000),
1379         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0xffffffff, 0xffff3101),
1380         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0x001f0000, 0x00070105),
1381         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ALU_CLK_CTRL, 0xffffffff, 0xffffffff),
1382         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x00000133, 0x00000130),
1383         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0xffffffff, 0xffffffff),
1384         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
1385         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CNTL, 0x60000010, 0x479c0010),
1386         SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0x00c00000, 0x00c00000),
1387 };
1388
1389 static const struct soc15_reg_golden golden_settings_gc_10_1_2[] =
1390 {
1391         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0x003e001f, 0x003c0014),
1392         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_GS_NGG_CLK_CTRL, 0xffff8fff, 0xffff8100),
1393         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_IA_CLK_CTRL, 0xffff0fff, 0xffff0100),
1394         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xff7f0fff, 0x0d000100),
1395         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQ_CLK_CTRL, 0xffffcfff, 0x60000100),
1396         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQG_CLK_CTRL, 0xffff0fff, 0x40000100),
1397         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xffff8fff, 0xffff8100),
1398         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_WD_CLK_CTRL, 0xffff8fff, 0xffff8100),
1399         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
1400         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_VC5_ENABLE, 0x00000003, 0x00000000),
1401         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0x800007ff, 0x000005ff),
1402         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG, 0xffffffff, 0x20000000),
1403         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xffffffff, 0x00000420),
1404         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000200),
1405         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x04800000),
1406         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DFSM_TILES_IN_FLIGHT, 0x0000ffff, 0x0000003f),
1407         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_LAST_OF_BURST_CONFIG, 0xffffffff, 0x03860204),
1408         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff0ffff, 0x00000500),
1409         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PRIV_CONTROL, 0x00007fff, 0x000001fe),
1410         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
1411         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x10321032),
1412         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x02310231),
1413         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
1414         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
1415         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CGTT_SCLK_CTRL, 0xffff0fff, 0x10000100),
1416         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL2, 0xffffffff, 0x1402002f),
1417         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xffffbfff, 0x00000188),
1418         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_0, 0xffffffff, 0x842a4c02),
1419         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
1420         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x08000009),
1421         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0xffffffff, 0x04440000),
1422         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0x00000820, 0x00000820),
1423         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000),
1424         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0xffffffff, 0xffff3101),
1425         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ALU_CLK_CTRL, 0xffffffff, 0xffffffff),
1426         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x00000133, 0x00000130),
1427         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0xffffffff, 0xffffffff),
1428         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
1429         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CNTL, 0xffdf80ff, 0x479c0010),
1430         SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffffffff, 0x00800000)
1431 };
1432
1433 static bool gfx_v10_is_rlcg_rw(struct amdgpu_device *adev, u32 offset, uint32_t *flag, bool write)
1434 {
1435         /* always programed by rlcg, only for gc */
1436         if (offset == SOC15_REG_OFFSET(GC, 0, mmRLC_CSIB_ADDR_HI) ||
1437             offset == SOC15_REG_OFFSET(GC, 0, mmRLC_CSIB_ADDR_LO) ||
1438             offset == SOC15_REG_OFFSET(GC, 0, mmRLC_CSIB_LENGTH) ||
1439             offset == SOC15_REG_OFFSET(GC, 0, mmGRBM_GFX_CNTL) ||
1440             offset == SOC15_REG_OFFSET(GC, 0, mmGRBM_GFX_INDEX) ||
1441             offset == SOC15_REG_OFFSET(GC, 0, mmCP_ME_CNTL)) {
1442                 if (!amdgpu_sriov_reg_indirect_gc(adev))
1443                         *flag = GFX_RLCG_GC_WRITE_OLD;
1444                 else
1445                         *flag = write ? GFX_RLCG_GC_WRITE : GFX_RLCG_GC_READ;
1446
1447                 return true;
1448         }
1449
1450         /* currently support gc read/write, mmhub write */
1451         if (offset >= SOC15_REG_OFFSET(GC, 0, mmSDMA0_DEC_START) &&
1452             offset <= SOC15_REG_OFFSET(GC, 0, mmRLC_GTS_OFFSET_MSB)) {
1453                 if (amdgpu_sriov_reg_indirect_gc(adev))
1454                         *flag = write ? GFX_RLCG_GC_WRITE : GFX_RLCG_GC_READ;
1455                 else
1456                         return false;
1457         } else {
1458                 if (amdgpu_sriov_reg_indirect_mmhub(adev))
1459                         *flag = GFX_RLCG_MMHUB_WRITE;
1460                 else
1461                         return false;
1462         }
1463
1464         return true;
1465 }
1466
1467 static u32 gfx_v10_rlcg_rw(struct amdgpu_device *adev, u32 offset, u32 v, uint32_t flag)
1468 {
1469         static void *scratch_reg0;
1470         static void *scratch_reg1;
1471         static void *scratch_reg2;
1472         static void *scratch_reg3;
1473         static void *spare_int;
1474         static uint32_t grbm_cntl;
1475         static uint32_t grbm_idx;
1476         uint32_t i = 0;
1477         uint32_t retries = 50000;
1478         u32 ret = 0;
1479
1480         scratch_reg0 = adev->rmmio +
1481                        (adev->reg_offset[GC_HWIP][0][mmSCRATCH_REG0_BASE_IDX] + mmSCRATCH_REG0) * 4;
1482         scratch_reg1 = adev->rmmio +
1483                        (adev->reg_offset[GC_HWIP][0][mmSCRATCH_REG1_BASE_IDX] + mmSCRATCH_REG1) * 4;
1484         scratch_reg2 = adev->rmmio +
1485                        (adev->reg_offset[GC_HWIP][0][mmSCRATCH_REG0_BASE_IDX] + mmSCRATCH_REG2) * 4;
1486         scratch_reg3 = adev->rmmio +
1487                        (adev->reg_offset[GC_HWIP][0][mmSCRATCH_REG1_BASE_IDX] + mmSCRATCH_REG3) * 4;
1488         spare_int = adev->rmmio +
1489                     (adev->reg_offset[GC_HWIP][0][mmRLC_SPARE_INT_BASE_IDX] + mmRLC_SPARE_INT) * 4;
1490
1491         grbm_cntl = adev->reg_offset[GC_HWIP][0][mmGRBM_GFX_CNTL_BASE_IDX] + mmGRBM_GFX_CNTL;
1492         grbm_idx = adev->reg_offset[GC_HWIP][0][mmGRBM_GFX_INDEX_BASE_IDX] + mmGRBM_GFX_INDEX;
1493
1494         if (offset == grbm_cntl || offset == grbm_idx) {
1495                 if (offset  == grbm_cntl)
1496                         writel(v, scratch_reg2);
1497                 else if (offset == grbm_idx)
1498                         writel(v, scratch_reg3);
1499
1500                 writel(v, ((void __iomem *)adev->rmmio) + (offset * 4));
1501         } else {
1502                 writel(v, scratch_reg0);
1503                 writel(offset | flag, scratch_reg1);
1504                 writel(1, spare_int);
1505                 for (i = 0; i < retries; i++) {
1506                         u32 tmp;
1507
1508                         tmp = readl(scratch_reg1);
1509                         if (!(tmp & flag))
1510                                 break;
1511
1512                         udelay(10);
1513                 }
1514
1515                 if (i >= retries)
1516                         pr_err("timeout: rlcg program reg:0x%05x failed !\n", offset);
1517         }
1518
1519         ret = readl(scratch_reg0);
1520
1521         return ret;
1522 }
1523
1524 static void gfx_v10_rlcg_wreg(struct amdgpu_device *adev, u32 offset, u32 value, u32 flag)
1525 {
1526         uint32_t rlcg_flag;
1527
1528         if (amdgpu_sriov_fullaccess(adev) &&
1529             gfx_v10_is_rlcg_rw(adev, offset, &rlcg_flag, 1)) {
1530                 gfx_v10_rlcg_rw(adev, offset, value, rlcg_flag);
1531
1532                 return;
1533         }
1534         if (flag & AMDGPU_REGS_NO_KIQ)
1535                 WREG32_NO_KIQ(offset, value);
1536         else
1537                 WREG32(offset, value);
1538 }
1539
1540 static u32 gfx_v10_rlcg_rreg(struct amdgpu_device *adev, u32 offset, u32 flag)
1541 {
1542         uint32_t rlcg_flag;
1543
1544         if (amdgpu_sriov_fullaccess(adev) &&
1545             gfx_v10_is_rlcg_rw(adev, offset, &rlcg_flag, 0))
1546                 return gfx_v10_rlcg_rw(adev, offset, 0, rlcg_flag);
1547
1548         if (flag & AMDGPU_REGS_NO_KIQ)
1549                 return RREG32_NO_KIQ(offset);
1550         else
1551                 return RREG32(offset);
1552
1553         return 0;
1554 }
1555
1556 static const struct soc15_reg_golden golden_settings_gc_10_1_nv14[] =
1557 {
1558         /* Pending on emulation bring up */
1559 };
1560
1561 static const struct soc15_reg_golden golden_settings_gc_rlc_spm_10_1_nv14[] =
1562 {
1563         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xE0000000L, 0x0),
1564         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1565         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
1566         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1567         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1568         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1569         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
1570         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1571         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
1572         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1573         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
1574         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1575         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
1576         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1577         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
1578         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1579         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1580         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1581         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
1582         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1583         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1584         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1585         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
1586         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1587         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1588         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1589         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
1590         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1591         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1592         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1593         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
1594         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1595         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1596         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1597         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
1598         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1599         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1600         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1601         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
1602         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1603         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1604         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1605         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
1606         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1607         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1608         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1609         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
1610         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1611         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1612         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1613         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
1614         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1615         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20),
1616         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1617         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
1618         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1619         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
1620         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1621         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
1622         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1623         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1624         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1625         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
1626         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1627         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1628         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1629         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
1630         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1631         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1632         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1633         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
1634         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1635         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1636         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1637         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
1638         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1639         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1640         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1641         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
1642         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1643         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
1644         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1645         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
1646         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1647         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1648         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1649         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
1650         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1651         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1652         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1653         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
1654         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1655         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1656         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1657         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
1658         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1659         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1660         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1661         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
1662         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1663         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
1664         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1665         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
1666         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1667         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
1668         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1669         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
1670         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1671         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
1672         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1673         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
1674         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1675         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
1676         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1677         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
1678         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1679         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
1680         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1681         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
1682         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1683         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
1684         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1685         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
1686         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1687         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
1688         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1689         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
1690         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1691         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
1692         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1693         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
1694         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1695         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
1696         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1697         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
1698         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1699         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
1700         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1701         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c),
1702         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1703         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1704         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1705         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
1706         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1707         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1708         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1709         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
1710         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1711         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1712         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1713         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
1714         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1715         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1716         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1717         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
1718         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1719         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1720         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1721         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
1722         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1723         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
1724         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1725         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
1726         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1727         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1728         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1729         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
1730         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1731         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1732         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1733         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
1734         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1735         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
1736         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1737         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
1738         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1739         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
1740         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1741         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
1742         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1743         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
1744         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1745         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
1746         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1747         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e),
1748         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1749         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
1750         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1751         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e),
1752         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1753         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
1754         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1755         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e),
1756         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1757         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
1758         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1759         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e),
1760         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1761         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
1762         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1763         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20),
1764         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1765         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
1766         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1767         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
1768         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1769         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
1770         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1771         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
1772         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1773         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
1774         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1775         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e),
1776         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1777         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
1778         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1779         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e),
1780         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1781         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
1782         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1783         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
1784         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1785         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
1786         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1787         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1788         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1789         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
1790         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1791         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1792         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1793         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
1794         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1795         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1796         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1797         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
1798         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1799         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1800         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1801         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
1802         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1803         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1804         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1805         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
1806         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1807         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1808         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1809         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
1810         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1811         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1812         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1813         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
1814         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1815         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1816         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1817         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
1818         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1819         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1820         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1821         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
1822         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1823         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1824         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1825         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
1826         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1827         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1828         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1829         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
1830         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1831         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1832         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1833         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90),
1834         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1835         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1836         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1837         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94),
1838         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1839         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
1840         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1841         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0),
1842         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1843         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1844         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1845         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4),
1846         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1847         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1848         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1849         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98),
1850         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1851         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1852         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1853         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c),
1854         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1855         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
1856         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1857         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8),
1858         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1859         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
1860         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1861         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac),
1862         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1863         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1864         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1865         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8),
1866         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1867         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1868         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1869         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc),
1870         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1871         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1872         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1873         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0),
1874         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1875         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
1876         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1877         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4),
1878         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1879         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1880         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1881         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0),
1882         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1883         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1884         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1885         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4),
1886         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1887         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1888         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1889         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0),
1890         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1891         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1892         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1893         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4),
1894         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1895         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1896         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1897         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8),
1898         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1899         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1900         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1901         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc),
1902         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1903         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1904         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1905         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8),
1906         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1907         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1908         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1909         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc),
1910         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1911         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1912         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1913         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8),
1914         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1915         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1916         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1917         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec),
1918         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1919         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1920         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1921         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0),
1922         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1923         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1924         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1925         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe4),
1926         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1927         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1928         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1929         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100),
1930         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1931         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1932         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1933         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104),
1934         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1935         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1936         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1937         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108),
1938         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1939         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1940         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1941         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c),
1942         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1943         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1944         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1945         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110),
1946         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1947         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1948         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1949         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114),
1950         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1951         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1952         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1953         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118),
1954         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1955         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1956         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1957         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c),
1958         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1959         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1960         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1961         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8),
1962         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1963         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17),
1964         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1965         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130),
1966         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1967         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1968         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1969         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134),
1970         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1971         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1972         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1973         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138),
1974         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1975         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1976         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1977         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c),
1978         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1979         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1980         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1981         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4),
1982         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1983         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20),
1984         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1985         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128),
1986         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1987         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1988         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1989         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c),
1990         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1991         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1992         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1993         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120),
1994         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1995         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1996         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1997         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124),
1998         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1999         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
2000         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2001         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0),
2002         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2003         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2004         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2005         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140),
2006         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2007         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2008         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2009         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144),
2010         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2011         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
2012         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2013         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150),
2014         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2015         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2016         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2017         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154),
2018         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2019         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2020         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2021         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148),
2022         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2023         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2024         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2025         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c),
2026         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2027         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
2028         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2029         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158),
2030         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2031         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
2032         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2033         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c),
2034         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2035         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2036         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2037         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168),
2038         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2039         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2040         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2041         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c),
2042         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2043         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
2044         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2045         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160),
2046         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2047         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
2048         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2049         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164),
2050         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2051         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2052         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2053         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170),
2054         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2055         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2056         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2057         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174),
2058         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2059         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
2060         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2061         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180),
2062         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2063         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
2064         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2065         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184),
2066         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2067         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
2068         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2069         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178),
2070         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2071         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2072         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2073         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c),
2074         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2075         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
2076         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2077         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188),
2078         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2079         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
2080         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2081         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c),
2082         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2083         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2084         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2085         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198),
2086         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2087         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2088         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2089         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c),
2090         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2091         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2092         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2093         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190),
2094         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2095         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
2096         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2097         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194),
2098         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2099         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2100         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2101         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1a0),
2102         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2103         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2104         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2105         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1a4),
2106         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2107         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
2108         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2109         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1b0),
2110         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2111         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2112         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2113         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1b4),
2114         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2115         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2116         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2117         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1a8),
2118         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2119         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2120         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2121         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1ac),
2122         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2123         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
2124         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2125         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1b8),
2126         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2127         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
2128         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2129         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1bc),
2130         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2131         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2132         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2133         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c8),
2134         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2135         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
2136         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2137         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1cc),
2138         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2139         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
2140         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2141         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c0),
2142         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2143         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
2144         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2145         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c4),
2146         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2147         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2148         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2149         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
2150         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2151         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2152         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2153         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
2154         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2155         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2156         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2157         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
2158         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2159         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20),
2160         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2161         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
2162         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2163         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20),
2164         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2165         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
2166         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2167         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
2168         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2169         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_SAMPLE_SKEW, 0x000000FF, 0x26),
2170         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2171         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_MUXSEL_SKEW, 0x000000FF, 0x28),
2172         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2173         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0xf),
2174         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2175         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0x15),
2176         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2177         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x1f),
2178         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2179         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x25),
2180         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2181         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_DESER_START_SKEW, 0x000000FF, 0x3b),
2182         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xFFFFFFFF, 0xe0000000)
2183 };
2184
2185 static const struct soc15_reg_golden golden_settings_gc_10_1_2_nv12[] =
2186 {
2187         /* Pending on emulation bring up */
2188 };
2189
2190 static const struct soc15_reg_golden golden_settings_gc_rlc_spm_10_1_2_nv12[] =
2191 {
2192         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xe0000000L, 0x0),
2193         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2194         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
2195         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2196         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
2197         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2198         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
2199         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2200         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
2201         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2202         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
2203         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2204         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
2205         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2206         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
2207         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2208         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
2209         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2210         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8),
2211         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2212         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2213         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2214         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc),
2215         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2216         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2217         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2218         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0),
2219         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2220         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2221         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2222         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4),
2223         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2224         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2225         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2226         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
2227         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2228         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2229         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2230         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
2231         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2232         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2233         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2234         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
2235         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2236         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2237         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2238         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
2239         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2240         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2241         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2242         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
2243         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2244         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2245         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2246         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
2247         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2248         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2249         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2250         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
2251         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2252         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2253         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2254         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
2255         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2256         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
2257         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2258         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
2259         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2260         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
2261         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2262         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0),
2263         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2264         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
2265         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2266         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4),
2267         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2268         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
2269         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2270         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8),
2271         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2272         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2273         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2274         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc),
2275         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2276         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2277         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2278         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0),
2279         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2280         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2281         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2282         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4),
2283         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2284         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2285         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2286         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90),
2287         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2288         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
2289         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2290         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94),
2291         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2292         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1),
2293         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2294         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98),
2295         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2296         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
2297         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2298         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c),
2299         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2300         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2301         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2302         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0),
2303         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2304         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1),
2305         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2306         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4),
2307         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2308         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2309         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2310         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8),
2311         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2312         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2313         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2314         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac),
2315         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2316         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2317         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2318         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
2319         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2320         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
2321         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2322         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
2323         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2324         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2325         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2326         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
2327         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2328         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
2329         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2330         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
2331         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2332         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2333         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2334         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
2335         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2336         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2337         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2338         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
2339         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2340         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2341         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2342         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
2343         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2344         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
2345         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2346         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
2347         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2348         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2349         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2350         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
2351         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2352         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2353         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2354         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
2355         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2356         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
2357         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2358         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
2359         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2360         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2361         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2362         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
2363         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2364         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
2365         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2366         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
2367         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2368         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
2369         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2370         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
2371         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2372         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2373         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2374         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
2375         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2376         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2377         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2378         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
2379         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2380         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2381         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2382         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
2383         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2384         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
2385         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2386         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
2387         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2388         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2389         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2390         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
2391         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2392         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2393         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2394         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
2395         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2396         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2397         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2398         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
2399         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2400         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2401         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2402         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
2403         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2404         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2405         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2406         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
2407         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2408         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
2409         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2410         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c),
2411         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2412         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
2413         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2414         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
2415         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2416         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2417         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2418         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
2419         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2420         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
2421         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2422         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
2423         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2424         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
2425         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2426         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
2427         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2428         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2429         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2430         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
2431         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2432         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2433         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2434         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
2435         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2436         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2437         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2438         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
2439         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2440         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2441         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2442         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
2443         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2444         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2445         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2446         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
2447         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2448         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2449         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2450         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
2451         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2452         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
2453         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2454         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
2455         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2456         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
2457         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2458         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
2459         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2460         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2461         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2462         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
2463         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2464         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2465         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2466         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
2467         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2468         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
2469         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2470         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
2471         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2472         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
2473         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2474         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
2475         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2476         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2477         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2478         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
2479         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2480         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2481         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2482         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
2483         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2484         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
2485         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2486         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
2487         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2488         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
2489         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2490         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
2491         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2492         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2493         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2494         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
2495         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2496         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2497         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2498         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
2499         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2500         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2501         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2502         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
2503         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2504         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2505         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2506         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
2507         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2508         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2509         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2510         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
2511         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2512         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2513         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2514         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
2515         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2516         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2517         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2518         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
2519         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2520         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2521         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2522         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
2523         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2524         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2525         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2526         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
2527         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2528         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2529         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2530         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
2531         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2532         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2533         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2534         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
2535         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2536         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2537         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2538         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
2539         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2540         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2541         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2542         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
2543         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2544         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2545         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2546         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
2547         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2548         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2549         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2550         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
2551         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2552         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2553         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2554         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
2555         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2556         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2557         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2558         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
2559         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2560         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2561         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2562         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
2563         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2564         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
2565         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2566         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
2567         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2568         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
2569         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2570         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
2571         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2572         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2573         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2574         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
2575         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2576         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2577         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2578         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
2579         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2580         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
2581         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2582         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
2583         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2584         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
2585         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2586         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
2587         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2588         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
2589         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2590         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
2591         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2592         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
2593         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2594         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
2595         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2596         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2597         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2598         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
2599         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2600         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2601         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2602         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
2603         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2604         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2605         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2606         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
2607         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2608         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2609         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2610         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
2611         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2612         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
2613         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2614         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
2615         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2616         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
2617         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2618         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
2619         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2620         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2621         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2622         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
2623         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2624         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2625         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2626         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
2627         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2628         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2629         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2630         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
2631         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2632         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2633         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2634         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
2635         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2636         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2637         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2638         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
2639         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2640         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2641         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2642         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
2643         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2644         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2645         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2646         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
2647         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2648         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2649         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2650         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
2651         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2652         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2653         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2654         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
2655         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2656         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2657         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2658         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
2659         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2660         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2661         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2662         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
2663         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2664         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2665         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2666         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90),
2667         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2668         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
2669         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2670         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90),
2671         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2672         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
2673         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2674         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94),
2675         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2676         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2677         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2678         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94),
2679         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2680         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2681         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2682         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0),
2683         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2684         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2685         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2686         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0),
2687         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2688         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2689         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2690         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4),
2691         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2692         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2693         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2694         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4),
2695         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2696         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2697         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2698         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98),
2699         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2700         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
2701         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2702         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98),
2703         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2704         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
2705         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2706         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c),
2707         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2708         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2709         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2710         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c),
2711         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2712         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2713         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2714         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8),
2715         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2716         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2717         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2718         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8),
2719         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2720         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2721         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2722         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac),
2723         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2724         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2725         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2726         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac),
2727         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2728         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2729         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2730         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8),
2731         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2732         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2733         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2734         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8),
2735         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2736         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2737         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2738         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc),
2739         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2740         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2741         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2742         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc),
2743         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2744         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2745         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2746         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0),
2747         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2748         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2749         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2750         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0),
2751         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2752         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2753         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2754         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4),
2755         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2756         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2757         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2758         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4),
2759         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2760         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2761         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2762         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0),
2763         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2764         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2765         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2766         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0),
2767         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2768         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2769         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2770         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4),
2771         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2772         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2773         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2774         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4),
2775         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2776         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2777         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2778         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0),
2779         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2780         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2781         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2782         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0),
2783         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2784         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2785         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2786         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4),
2787         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2788         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2789         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2790         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4),
2791         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2792         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2793         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2794         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8),
2795         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2796         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2797         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2798         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8),
2799         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2800         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2801         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2802         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc),
2803         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2804         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2805         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2806         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc),
2807         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2808         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2809         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2810         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8),
2811         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2812         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2813         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2814         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8),
2815         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2816         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2817         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2818         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec),
2819         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2820         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
2821         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2822         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec),
2823         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2824         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
2825         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2826         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0),
2827         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2828         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2829         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2830         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0),
2831         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2832         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2833         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2834         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4),
2835         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2836         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2837         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2838         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4),
2839         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2840         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2841         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2842         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8),
2843         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2844         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2845         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2846         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8),
2847         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2848         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2849         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2850         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xfc),
2851         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2852         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17),
2853         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2854         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xfc),
2855         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2856         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17),
2857         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2858         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100),
2859         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2860         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
2861         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2862         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100),
2863         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2864         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
2865         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2866         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104),
2867         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2868         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2869         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2870         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104),
2871         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2872         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2873         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2874         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0),
2875         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2876         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2877         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2878         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0),
2879         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2880         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2881         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2882         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118),
2883         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2884         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2885         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2886         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118),
2887         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2888         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2889         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2890         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c),
2891         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2892         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2893         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2894         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c),
2895         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2896         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2897         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2898         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120),
2899         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2900         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2901         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2902         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120),
2903         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2904         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2905         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2906         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124),
2907         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2908         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2909         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2910         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124),
2911         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2912         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2913         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2914         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc),
2915         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2916         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2917         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2918         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc),
2919         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2920         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2921         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2922         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110),
2923         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2924         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2925         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2926         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110),
2927         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2928         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2929         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2930         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114),
2931         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2932         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2933         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2934         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114),
2935         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2936         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2937         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2938         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108),
2939         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2940         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2941         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2942         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108),
2943         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2944         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2945         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2946         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c),
2947         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2948         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2949         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2950         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c),
2951         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2952         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2953         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2954         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8),
2955         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2956         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
2957         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2958         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8),
2959         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2960         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
2961         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2962         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128),
2963         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2964         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2965         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2966         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128),
2967         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2968         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2969         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2970         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c),
2971         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2972         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2973         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2974         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c),
2975         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2976         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2977         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2978         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138),
2979         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2980         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2981         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2982         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138),
2983         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2984         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2985         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2986         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c),
2987         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2988         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2989         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2990         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c),
2991         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2992         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2993         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2994         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130),
2995         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2996         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2997         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2998         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130),
2999         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3000         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
3001         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3002         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134),
3003         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3004         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
3005         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3006         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134),
3007         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3008         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
3009         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3010         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140),
3011         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3012         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3013         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3014         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140),
3015         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3016         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3017         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3018         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144),
3019         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3020         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
3021         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3022         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144),
3023         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3024         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
3025         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3026         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150),
3027         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3028         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3029         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3030         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150),
3031         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3032         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3033         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3034         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154),
3035         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3036         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
3037         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3038         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154),
3039         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3040         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
3041         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3042         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148),
3043         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3044         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3045         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3046         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148),
3047         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3048         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3049         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3050         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c),
3051         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3052         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
3053         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3054         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c),
3055         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3056         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
3057         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3058         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158),
3059         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3060         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
3061         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3062         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158),
3063         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3064         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
3065         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3066         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c),
3067         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3068         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
3069         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3070         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c),
3071         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3072         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
3073         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3074         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168),
3075         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3076         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
3077         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3078         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168),
3079         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3080         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
3081         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3082         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c),
3083         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3084         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
3085         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3086         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c),
3087         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3088         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
3089         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3090         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160),
3091         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3092         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
3093         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3094         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160),
3095         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3096         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
3097         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3098         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164),
3099         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3100         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
3101         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3102         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164),
3103         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3104         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
3105         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3106         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170),
3107         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3108         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
3109         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3110         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170),
3111         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3112         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
3113         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3114         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174),
3115         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3116         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3117         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3118         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174),
3119         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3120         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3121         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3122         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180),
3123         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3124         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
3125         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3126         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180),
3127         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3128         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
3129         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3130         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184),
3131         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3132         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3133         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3134         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184),
3135         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3136         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3137         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3138         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178),
3139         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3140         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
3141         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3142         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178),
3143         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3144         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
3145         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3146         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c),
3147         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3148         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3149         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3150         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c),
3151         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3152         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3153         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3154         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188),
3155         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3156         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3157         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3158         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188),
3159         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3160         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3161         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3162         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c),
3163         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3164         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
3165         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3166         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c),
3167         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3168         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
3169         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3170         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198),
3171         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3172         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
3173         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3174         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198),
3175         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3176         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
3177         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3178         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c),
3179         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3180         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
3181         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3182         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c),
3183         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3184         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
3185         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3186         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190),
3187         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3188         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3189         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3190         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190),
3191         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3192         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3193         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3194         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194),
3195         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3196         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
3197         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3198         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194),
3199         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3200         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
3201         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3202         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
3203         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3204         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
3205         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3206         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
3207         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3208         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
3209         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3210         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
3211         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3212         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
3213         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3214         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
3215         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3216         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
3217         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3218         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
3219         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3220         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1f),
3221         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3222         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
3223         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3224         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1f),
3225         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3226         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
3227         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3228         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
3229         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3230         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_SAMPLE_SKEW, 0x000000FF, 0x1f),
3231         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3232         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_MUXSEL_SKEW, 0x000000FF, 0x22),
3233         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3234         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0x1),
3235         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3236         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0x6),
3237         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3238         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x10),
3239         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3240         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x15),
3241         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3242         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_DESER_START_SKEW, 0x000000FF, 0x35),
3243         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xFFFFFFFF, 0xe0000000)
3244 };
3245
3246 static const struct soc15_reg_golden golden_settings_gc_10_3[] =
3247 {
3248         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0x78000000, 0x78000100),
3249         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_PS_CLK_CTRL, 0xff7f0fff, 0x78000100),
3250         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA0_CLK_CTRL, 0xff7f0fff, 0x30000100),
3251         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA1_CLK_CTRL, 0xff7f0fff, 0x7e000100),
3252         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c000),
3253         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000280),
3254         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000),
3255         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_EXCEPTION_CONTROL, 0x7fff0f1f, 0x00b80000),
3256         SOC15_REG_GOLDEN_VALUE(GC, 0 ,mmGCEA_SDP_TAG_RESERVE0, 0xffffffff, 0x10100100),
3257         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCEA_SDP_TAG_RESERVE1, 0xffffffff, 0x17000088),
3258         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Sienna_Cichlid, 0x1ff1ffff, 0x00000500),
3259         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCUTCL2_CGTT_CLK_CTRL_Sienna_Cichlid, 0xff000000, 0xff008080),
3260         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCVM_L2_CGTT_CLK_CTRL_Sienna_Cichlid, 0xff000000, 0xff008080),
3261         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PC_CNTL, 0x003fffff, 0x00280400),
3262         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
3263         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
3264         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008),
3265         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x10f80988),
3266         SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG,  0x00000020, 0x00000020),
3267         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007),
3268         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
3269         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0xffffffbf, 0x00000820),
3270         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0xffffffff, 0x00070104),
3271         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_CONFIG, 0xe07df47f, 0x00180070),
3272         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER0_SELECT, 0xf0f001ff, 0x00000000),
3273         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER1_SELECT, 0xf0f001ff, 0x00000000),
3274         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER10_SELECT, 0xf0f001ff, 0x00000000),
3275         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER11_SELECT, 0xf0f001ff, 0x00000000),
3276         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER12_SELECT, 0xf0f001ff, 0x00000000),
3277         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER13_SELECT, 0xf0f001ff, 0x00000000),
3278         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER14_SELECT, 0xf0f001ff, 0x00000000),
3279         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER15_SELECT, 0xf0f001ff, 0x00000000),
3280         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER2_SELECT, 0xf0f001ff, 0x00000000),
3281         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER3_SELECT, 0xf0f001ff, 0x00000000),
3282         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER4_SELECT, 0xf0f001ff, 0x00000000),
3283         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER5_SELECT, 0xf0f001ff, 0x00000000),
3284         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER6_SELECT, 0xf0f001ff, 0x00000000),
3285         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER7_SELECT, 0xf0f001ff, 0x00000000),
3286         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER8_SELECT, 0xf0f001ff, 0x00000000),
3287         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER9_SELECT, 0xf0f001ff, 0x00000000),
3288         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
3289         SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffbfffff, 0x00a00000)
3290 };
3291
3292 static const struct soc15_reg_golden golden_settings_gc_10_3_sienna_cichlid[] =
3293 {
3294         /* Pending on emulation bring up */
3295 };
3296
3297 static const struct soc15_reg_golden golden_settings_gc_10_3_2[] =
3298 {
3299         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0xff7f0fff, 0x78000100),
3300         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_PS_CLK_CTRL, 0xff7f0fff, 0x78000100),
3301         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA0_CLK_CTRL, 0xff7f0fff, 0x30000100),
3302         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA1_CLK_CTRL, 0xff7f0fff, 0x7e000100),
3303         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c000),
3304         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000280),
3305         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000),
3306         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_EXCEPTION_CONTROL, 0x7fff0f1f, 0x00b80000),
3307         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Sienna_Cichlid, 0x1ff1ffff, 0x00000500),
3308         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCUTCL2_CGTT_CLK_CTRL_Sienna_Cichlid, 0xffffffff, 0xff008080),
3309         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCVM_L2_CGTT_CLK_CTRL_Sienna_Cichlid, 0xffff8fff, 0xff008080),
3310         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PC_CNTL, 0x003fffff, 0x00280400),
3311         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
3312         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
3313         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008),
3314         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x00f80988),
3315         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007),
3316         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
3317         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0xffffffbf, 0x00000820),
3318         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0xffffffff, 0x00070104),
3319         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_START_PHASE, 0x000000ff, 0x00000004),
3320         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_CONFIG, 0xe07df47f, 0x00180070),
3321         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER0_SELECT, 0xf0f001ff, 0x00000000),
3322         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER1_SELECT, 0xf0f001ff, 0x00000000),
3323         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER10_SELECT, 0xf0f001ff, 0x00000000),
3324         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER11_SELECT, 0xf0f001ff, 0x00000000),
3325         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER12_SELECT, 0xf0f001ff, 0x00000000),
3326         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER13_SELECT, 0xf0f001ff, 0x00000000),
3327         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER14_SELECT, 0xf0f001ff, 0x00000000),
3328         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER15_SELECT, 0xf0f001ff, 0x00000000),
3329         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER2_SELECT, 0xf0f001ff, 0x00000000),
3330         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER3_SELECT, 0xf0f001ff, 0x00000000),
3331         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER4_SELECT, 0xf0f001ff, 0x00000000),
3332         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER5_SELECT, 0xf0f001ff, 0x00000000),
3333         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER6_SELECT, 0xf0f001ff, 0x00000000),
3334         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER7_SELECT, 0xf0f001ff, 0x00000000),
3335         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER8_SELECT, 0xf0f001ff, 0x00000000),
3336         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER9_SELECT, 0xf0f001ff, 0x00000000),
3337         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
3338         SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffbfffff, 0x00a00000),
3339         SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_GS_MAX_WAVE_ID, 0x00000fff, 0x000003ff),
3340
3341         /* This is not in GDB yet. Don't remove it. It fixes a GPU hang on Navy Flounder. */
3342         SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG,  0x00000020, 0x00000020),
3343 };
3344
3345 static const struct soc15_reg_golden golden_settings_gc_10_3_vangogh[] =
3346 {
3347         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA0_CLK_CTRL, 0xff7f0fff, 0x30000100),
3348         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA1_CLK_CTRL, 0xff7f0fff, 0x7e000100),
3349         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0x000000ff, 0x000000e4),
3350         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000200),
3351         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000),
3352         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_EXCEPTION_CONTROL, 0x7fff0f1f, 0x00b80000),
3353         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0x0c1807ff, 0x00000142),
3354         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Vangogh, 0x1ff1ffff, 0x00000500),
3355         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0x000000ff, 0x000000e4),
3356         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x32103210),
3357         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x32103210),
3358         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xfffffff3),
3359         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xfffffff3),
3360         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008),
3361         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x00f80988),
3362         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007),
3363         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
3364         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0xffffffbf, 0x00000020),
3365         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1_Vangogh, 0xffffffff, 0x00070103),
3366         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQG_CONFIG, 0x000017ff, 0x00001000),
3367         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
3368         SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffffffff, 0x00400000),
3369         SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_GS_MAX_WAVE_ID, 0x00000fff, 0x000000ff),
3370
3371         /* This is not in GDB yet. Don't remove it. It fixes a GPU hang on VanGogh. */
3372         SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG,  0x00000020, 0x00000020),
3373 };
3374
3375 static const struct soc15_reg_golden golden_settings_gc_10_3_4[] =
3376 {
3377         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0x78000000, 0x78000100),
3378         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA0_CLK_CTRL, 0x30000000, 0x30000100),
3379         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA1_CLK_CTRL, 0x7e000000, 0x7e000100),
3380         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c000),
3381         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0x00000280, 0x00000280),
3382         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0x07800000, 0x00800000),
3383         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Sienna_Cichlid, 0x00001d00, 0x00000500),
3384         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PC_CNTL, 0x003c0000, 0x00280400),
3385         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
3386         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
3387         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0x40000000, 0x580f1008),
3388         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0x00040000, 0x00f80988),
3389         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0x01000000, 0x01200007),
3390         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
3391         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0x00000800, 0x00000820),
3392         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_CONFIG, 0x0000001f, 0x00180070),
3393         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER0_SELECT, 0xf0f001ff, 0x00000000),
3394         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER1_SELECT, 0xf0f001ff, 0x00000000),
3395         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER10_SELECT, 0xf0f001ff, 0x00000000),
3396         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER11_SELECT, 0xf0f001ff, 0x00000000),
3397         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER12_SELECT, 0xf0f001ff, 0x00000000),
3398         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER13_SELECT, 0xf0f001ff, 0x00000000),
3399         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER14_SELECT, 0xf0f001ff, 0x00000000),
3400         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER15_SELECT, 0xf0f001ff, 0x00000000),
3401         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER2_SELECT, 0xf0f001ff, 0x00000000),
3402         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER3_SELECT, 0xf0f001ff, 0x00000000),
3403         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER4_SELECT, 0xf0f001ff, 0x00000000),
3404         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER5_SELECT, 0xf0f001ff, 0x00000000),
3405         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER6_SELECT, 0xf0f001ff, 0x00000000),
3406         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER7_SELECT, 0xf0f001ff, 0x00000000),
3407         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER8_SELECT, 0xf0f001ff, 0x00000000),
3408         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER9_SELECT, 0xf0f001ff, 0x00000000),
3409         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0x01030000, 0x01030000),
3410         SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0x03a00000, 0x00a00000),
3411         SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG,  0x00000020, 0x00000020)
3412 };
3413
3414 #define DEFAULT_SH_MEM_CONFIG \
3415         ((SH_MEM_ADDRESS_MODE_64 << SH_MEM_CONFIG__ADDRESS_MODE__SHIFT) | \
3416          (SH_MEM_ALIGNMENT_MODE_UNALIGNED << SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT) | \
3417          (SH_MEM_RETRY_MODE_ALL << SH_MEM_CONFIG__RETRY_MODE__SHIFT) | \
3418          (3 << SH_MEM_CONFIG__INITIAL_INST_PREFETCH__SHIFT))
3419
3420
3421 static void gfx_v10_0_set_ring_funcs(struct amdgpu_device *adev);
3422 static void gfx_v10_0_set_irq_funcs(struct amdgpu_device *adev);
3423 static void gfx_v10_0_set_gds_init(struct amdgpu_device *adev);
3424 static void gfx_v10_0_set_rlc_funcs(struct amdgpu_device *adev);
3425 static int gfx_v10_0_get_cu_info(struct amdgpu_device *adev,
3426                                  struct amdgpu_cu_info *cu_info);
3427 static uint64_t gfx_v10_0_get_gpu_clock_counter(struct amdgpu_device *adev);
3428 static void gfx_v10_0_select_se_sh(struct amdgpu_device *adev, u32 se_num,
3429                                    u32 sh_num, u32 instance);
3430 static u32 gfx_v10_0_get_wgp_active_bitmap_per_sh(struct amdgpu_device *adev);
3431
3432 static int gfx_v10_0_rlc_backdoor_autoload_buffer_init(struct amdgpu_device *adev);
3433 static void gfx_v10_0_rlc_backdoor_autoload_buffer_fini(struct amdgpu_device *adev);
3434 static int gfx_v10_0_rlc_backdoor_autoload_enable(struct amdgpu_device *adev);
3435 static int gfx_v10_0_wait_for_rlc_autoload_complete(struct amdgpu_device *adev);
3436 static void gfx_v10_0_ring_emit_ce_meta(struct amdgpu_ring *ring, bool resume);
3437 static void gfx_v10_0_ring_emit_de_meta(struct amdgpu_ring *ring, bool resume);
3438 static void gfx_v10_0_ring_emit_frame_cntl(struct amdgpu_ring *ring, bool start, bool secure);
3439 static u32 gfx_v10_3_get_disabled_sa(struct amdgpu_device *adev);
3440 static void gfx_v10_3_program_pbb_mode(struct amdgpu_device *adev);
3441 static void gfx_v10_3_set_power_brake_sequence(struct amdgpu_device *adev);
3442
3443 static void gfx10_kiq_set_resources(struct amdgpu_ring *kiq_ring, uint64_t queue_mask)
3444 {
3445         amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_RESOURCES, 6));
3446         amdgpu_ring_write(kiq_ring, PACKET3_SET_RESOURCES_VMID_MASK(0) |
3447                           PACKET3_SET_RESOURCES_QUEUE_TYPE(0)); /* vmid_mask:0 queue_type:0 (KIQ) */
3448         amdgpu_ring_write(kiq_ring, lower_32_bits(queue_mask)); /* queue mask lo */
3449         amdgpu_ring_write(kiq_ring, upper_32_bits(queue_mask)); /* queue mask hi */
3450         amdgpu_ring_write(kiq_ring, 0); /* gws mask lo */
3451         amdgpu_ring_write(kiq_ring, 0); /* gws mask hi */
3452         amdgpu_ring_write(kiq_ring, 0); /* oac mask */
3453         amdgpu_ring_write(kiq_ring, 0); /* gds heap base:0, gds heap size:0 */
3454 }
3455
3456 static void gfx10_kiq_map_queues(struct amdgpu_ring *kiq_ring,
3457                                  struct amdgpu_ring *ring)
3458 {
3459         struct amdgpu_device *adev = kiq_ring->adev;
3460         uint64_t mqd_addr = amdgpu_bo_gpu_offset(ring->mqd_obj);
3461         uint64_t wptr_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
3462         uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0;
3463
3464         amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5));
3465         /* Q_sel:0, vmid:0, vidmem: 1, engine:0, num_Q:1*/
3466         amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */
3467                           PACKET3_MAP_QUEUES_QUEUE_SEL(0) | /* Queue_Sel */
3468                           PACKET3_MAP_QUEUES_VMID(0) | /* VMID */
3469                           PACKET3_MAP_QUEUES_QUEUE(ring->queue) |
3470                           PACKET3_MAP_QUEUES_PIPE(ring->pipe) |
3471                           PACKET3_MAP_QUEUES_ME((ring->me == 1 ? 0 : 1)) |
3472                           PACKET3_MAP_QUEUES_QUEUE_TYPE(0) | /*queue_type: normal compute queue */
3473                           PACKET3_MAP_QUEUES_ALLOC_FORMAT(0) | /* alloc format: all_on_one_pipe */
3474                           PACKET3_MAP_QUEUES_ENGINE_SEL(eng_sel) |
3475                           PACKET3_MAP_QUEUES_NUM_QUEUES(1)); /* num_queues: must be 1 */
3476         amdgpu_ring_write(kiq_ring, PACKET3_MAP_QUEUES_DOORBELL_OFFSET(ring->doorbell_index));
3477         amdgpu_ring_write(kiq_ring, lower_32_bits(mqd_addr));
3478         amdgpu_ring_write(kiq_ring, upper_32_bits(mqd_addr));
3479         amdgpu_ring_write(kiq_ring, lower_32_bits(wptr_addr));
3480         amdgpu_ring_write(kiq_ring, upper_32_bits(wptr_addr));
3481 }
3482
3483 static void gfx10_kiq_unmap_queues(struct amdgpu_ring *kiq_ring,
3484                                    struct amdgpu_ring *ring,
3485                                    enum amdgpu_unmap_queues_action action,
3486                                    u64 gpu_addr, u64 seq)
3487 {
3488         uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0;
3489
3490         amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_UNMAP_QUEUES, 4));
3491         amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */
3492                           PACKET3_UNMAP_QUEUES_ACTION(action) |
3493                           PACKET3_UNMAP_QUEUES_QUEUE_SEL(0) |
3494                           PACKET3_UNMAP_QUEUES_ENGINE_SEL(eng_sel) |
3495                           PACKET3_UNMAP_QUEUES_NUM_QUEUES(1));
3496         amdgpu_ring_write(kiq_ring,
3497                   PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET0(ring->doorbell_index));
3498
3499         if (action == PREEMPT_QUEUES_NO_UNMAP) {
3500                 amdgpu_ring_write(kiq_ring, lower_32_bits(gpu_addr));
3501                 amdgpu_ring_write(kiq_ring, upper_32_bits(gpu_addr));
3502                 amdgpu_ring_write(kiq_ring, seq);
3503         } else {
3504                 amdgpu_ring_write(kiq_ring, 0);
3505                 amdgpu_ring_write(kiq_ring, 0);
3506                 amdgpu_ring_write(kiq_ring, 0);
3507         }
3508 }
3509
3510 static void gfx10_kiq_query_status(struct amdgpu_ring *kiq_ring,
3511                                    struct amdgpu_ring *ring,
3512                                    u64 addr,
3513                                    u64 seq)
3514 {
3515         uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0;
3516
3517         amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_QUERY_STATUS, 5));
3518         amdgpu_ring_write(kiq_ring,
3519                           PACKET3_QUERY_STATUS_CONTEXT_ID(0) |
3520                           PACKET3_QUERY_STATUS_INTERRUPT_SEL(0) |
3521                           PACKET3_QUERY_STATUS_COMMAND(2));
3522         amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */
3523                           PACKET3_QUERY_STATUS_DOORBELL_OFFSET(ring->doorbell_index) |
3524                           PACKET3_QUERY_STATUS_ENG_SEL(eng_sel));
3525         amdgpu_ring_write(kiq_ring, lower_32_bits(addr));
3526         amdgpu_ring_write(kiq_ring, upper_32_bits(addr));
3527         amdgpu_ring_write(kiq_ring, lower_32_bits(seq));
3528         amdgpu_ring_write(kiq_ring, upper_32_bits(seq));
3529 }
3530
3531 static void gfx10_kiq_invalidate_tlbs(struct amdgpu_ring *kiq_ring,
3532                                 uint16_t pasid, uint32_t flush_type,
3533                                 bool all_hub)
3534 {
3535         amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_INVALIDATE_TLBS, 0));
3536         amdgpu_ring_write(kiq_ring,
3537                         PACKET3_INVALIDATE_TLBS_DST_SEL(1) |
3538                         PACKET3_INVALIDATE_TLBS_ALL_HUB(all_hub) |
3539                         PACKET3_INVALIDATE_TLBS_PASID(pasid) |
3540                         PACKET3_INVALIDATE_TLBS_FLUSH_TYPE(flush_type));
3541 }
3542
3543 static const struct kiq_pm4_funcs gfx_v10_0_kiq_pm4_funcs = {
3544         .kiq_set_resources = gfx10_kiq_set_resources,
3545         .kiq_map_queues = gfx10_kiq_map_queues,
3546         .kiq_unmap_queues = gfx10_kiq_unmap_queues,
3547         .kiq_query_status = gfx10_kiq_query_status,
3548         .kiq_invalidate_tlbs = gfx10_kiq_invalidate_tlbs,
3549         .set_resources_size = 8,
3550         .map_queues_size = 7,
3551         .unmap_queues_size = 6,
3552         .query_status_size = 7,
3553         .invalidate_tlbs_size = 2,
3554 };
3555
3556 static void gfx_v10_0_set_kiq_pm4_funcs(struct amdgpu_device *adev)
3557 {
3558         adev->gfx.kiq.pmf = &gfx_v10_0_kiq_pm4_funcs;
3559 }
3560
3561 static void gfx_v10_0_init_spm_golden_registers(struct amdgpu_device *adev)
3562 {
3563         switch (adev->asic_type) {
3564         case CHIP_NAVI10:
3565                 soc15_program_register_sequence(adev,
3566                                                 golden_settings_gc_rlc_spm_10_0_nv10,
3567                                                 (const u32)ARRAY_SIZE(golden_settings_gc_rlc_spm_10_0_nv10));
3568                 break;
3569         case CHIP_NAVI14:
3570                 soc15_program_register_sequence(adev,
3571                                                 golden_settings_gc_rlc_spm_10_1_nv14,
3572                                                 (const u32)ARRAY_SIZE(golden_settings_gc_rlc_spm_10_1_nv14));
3573                 break;
3574         case CHIP_NAVI12:
3575                 soc15_program_register_sequence(adev,
3576                                                 golden_settings_gc_rlc_spm_10_1_2_nv12,
3577                                                 (const u32)ARRAY_SIZE(golden_settings_gc_rlc_spm_10_1_2_nv12));
3578                 break;
3579         default:
3580                 break;
3581         }
3582 }
3583
3584 static void gfx_v10_0_init_golden_registers(struct amdgpu_device *adev)
3585 {
3586         switch (adev->asic_type) {
3587         case CHIP_NAVI10:
3588                 soc15_program_register_sequence(adev,
3589                                                 golden_settings_gc_10_1,
3590                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_1));
3591                 soc15_program_register_sequence(adev,
3592                                                 golden_settings_gc_10_0_nv10,
3593                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_0_nv10));
3594                 break;
3595         case CHIP_NAVI14:
3596                 soc15_program_register_sequence(adev,
3597                                                 golden_settings_gc_10_1_1,
3598                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_1_1));
3599                 soc15_program_register_sequence(adev,
3600                                                 golden_settings_gc_10_1_nv14,
3601                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_1_nv14));
3602                 break;
3603         case CHIP_NAVI12:
3604                 soc15_program_register_sequence(adev,
3605                                                 golden_settings_gc_10_1_2,
3606                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_1_2));
3607                 soc15_program_register_sequence(adev,
3608                                                 golden_settings_gc_10_1_2_nv12,
3609                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_1_2_nv12));
3610                 break;
3611         case CHIP_SIENNA_CICHLID:
3612                 soc15_program_register_sequence(adev,
3613                                                 golden_settings_gc_10_3,
3614                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_3));
3615                 soc15_program_register_sequence(adev,
3616                                                 golden_settings_gc_10_3_sienna_cichlid,
3617                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_sienna_cichlid));
3618                 break;
3619         case CHIP_NAVY_FLOUNDER:
3620                 soc15_program_register_sequence(adev,
3621                                                 golden_settings_gc_10_3_2,
3622                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_2));
3623                 break;
3624         case CHIP_VANGOGH:
3625                 soc15_program_register_sequence(adev,
3626                                                 golden_settings_gc_10_3_vangogh,
3627                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_vangogh));
3628                 break;
3629         case CHIP_DIMGREY_CAVEFISH:
3630                 soc15_program_register_sequence(adev,
3631                                                 golden_settings_gc_10_3_4,
3632                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_4));
3633                 break;
3634         default:
3635                 break;
3636         }
3637         gfx_v10_0_init_spm_golden_registers(adev);
3638 }
3639
3640 static void gfx_v10_0_scratch_init(struct amdgpu_device *adev)
3641 {
3642         adev->gfx.scratch.num_reg = 8;
3643         adev->gfx.scratch.reg_base = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG0);
3644         adev->gfx.scratch.free_mask = (1u << adev->gfx.scratch.num_reg) - 1;
3645 }
3646
3647 static void gfx_v10_0_write_data_to_reg(struct amdgpu_ring *ring, int eng_sel,
3648                                        bool wc, uint32_t reg, uint32_t val)
3649 {
3650         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
3651         amdgpu_ring_write(ring, WRITE_DATA_ENGINE_SEL(eng_sel) |
3652                           WRITE_DATA_DST_SEL(0) | (wc ? WR_CONFIRM : 0));
3653         amdgpu_ring_write(ring, reg);
3654         amdgpu_ring_write(ring, 0);
3655         amdgpu_ring_write(ring, val);
3656 }
3657
3658 static void gfx_v10_0_wait_reg_mem(struct amdgpu_ring *ring, int eng_sel,
3659                                   int mem_space, int opt, uint32_t addr0,
3660                                   uint32_t addr1, uint32_t ref, uint32_t mask,
3661                                   uint32_t inv)
3662 {
3663         amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
3664         amdgpu_ring_write(ring,
3665                           /* memory (1) or register (0) */
3666                           (WAIT_REG_MEM_MEM_SPACE(mem_space) |
3667                            WAIT_REG_MEM_OPERATION(opt) | /* wait */
3668                            WAIT_REG_MEM_FUNCTION(3) |  /* equal */
3669                            WAIT_REG_MEM_ENGINE(eng_sel)));
3670
3671         if (mem_space)
3672                 BUG_ON(addr0 & 0x3); /* Dword align */
3673         amdgpu_ring_write(ring, addr0);
3674         amdgpu_ring_write(ring, addr1);
3675         amdgpu_ring_write(ring, ref);
3676         amdgpu_ring_write(ring, mask);
3677         amdgpu_ring_write(ring, inv); /* poll interval */
3678 }
3679
3680 static int gfx_v10_0_ring_test_ring(struct amdgpu_ring *ring)
3681 {
3682         struct amdgpu_device *adev = ring->adev;
3683         uint32_t scratch;
3684         uint32_t tmp = 0;
3685         unsigned i;
3686         int r;
3687
3688         r = amdgpu_gfx_scratch_get(adev, &scratch);
3689         if (r) {
3690                 DRM_ERROR("amdgpu: cp failed to get scratch reg (%d).\n", r);
3691                 return r;
3692         }
3693
3694         WREG32(scratch, 0xCAFEDEAD);
3695
3696         r = amdgpu_ring_alloc(ring, 3);
3697         if (r) {
3698                 DRM_ERROR("amdgpu: cp failed to lock ring %d (%d).\n",
3699                           ring->idx, r);
3700                 amdgpu_gfx_scratch_free(adev, scratch);
3701                 return r;
3702         }
3703
3704         amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1));
3705         amdgpu_ring_write(ring, (scratch - PACKET3_SET_UCONFIG_REG_START));
3706         amdgpu_ring_write(ring, 0xDEADBEEF);
3707         amdgpu_ring_commit(ring);
3708
3709         for (i = 0; i < adev->usec_timeout; i++) {
3710                 tmp = RREG32(scratch);
3711                 if (tmp == 0xDEADBEEF)
3712                         break;
3713                 if (amdgpu_emu_mode == 1)
3714                         msleep(1);
3715                 else
3716                         udelay(1);
3717         }
3718
3719         if (i >= adev->usec_timeout)
3720                 r = -ETIMEDOUT;
3721
3722         amdgpu_gfx_scratch_free(adev, scratch);
3723
3724         return r;
3725 }
3726
3727 static int gfx_v10_0_ring_test_ib(struct amdgpu_ring *ring, long timeout)
3728 {
3729         struct amdgpu_device *adev = ring->adev;
3730         struct amdgpu_ib ib;
3731         struct dma_fence *f = NULL;
3732         unsigned index;
3733         uint64_t gpu_addr;
3734         uint32_t tmp;
3735         long r;
3736
3737         r = amdgpu_device_wb_get(adev, &index);
3738         if (r)
3739                 return r;
3740
3741         gpu_addr = adev->wb.gpu_addr + (index * 4);
3742         adev->wb.wb[index] = cpu_to_le32(0xCAFEDEAD);
3743         memset(&ib, 0, sizeof(ib));
3744         r = amdgpu_ib_get(adev, NULL, 16,
3745                                         AMDGPU_IB_POOL_DIRECT, &ib);
3746         if (r)
3747                 goto err1;
3748
3749         ib.ptr[0] = PACKET3(PACKET3_WRITE_DATA, 3);
3750         ib.ptr[1] = WRITE_DATA_DST_SEL(5) | WR_CONFIRM;
3751         ib.ptr[2] = lower_32_bits(gpu_addr);
3752         ib.ptr[3] = upper_32_bits(gpu_addr);
3753         ib.ptr[4] = 0xDEADBEEF;
3754         ib.length_dw = 5;
3755
3756         r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
3757         if (r)
3758                 goto err2;
3759
3760         r = dma_fence_wait_timeout(f, false, timeout);
3761         if (r == 0) {
3762                 r = -ETIMEDOUT;
3763                 goto err2;
3764         } else if (r < 0) {
3765                 goto err2;
3766         }
3767
3768         tmp = adev->wb.wb[index];
3769         if (tmp == 0xDEADBEEF)
3770                 r = 0;
3771         else
3772                 r = -EINVAL;
3773 err2:
3774         amdgpu_ib_free(adev, &ib, NULL);
3775         dma_fence_put(f);
3776 err1:
3777         amdgpu_device_wb_free(adev, index);
3778         return r;
3779 }
3780
3781 static void gfx_v10_0_free_microcode(struct amdgpu_device *adev)
3782 {
3783         release_firmware(adev->gfx.pfp_fw);
3784         adev->gfx.pfp_fw = NULL;
3785         release_firmware(adev->gfx.me_fw);
3786         adev->gfx.me_fw = NULL;
3787         release_firmware(adev->gfx.ce_fw);
3788         adev->gfx.ce_fw = NULL;
3789         release_firmware(adev->gfx.rlc_fw);
3790         adev->gfx.rlc_fw = NULL;
3791         release_firmware(adev->gfx.mec_fw);
3792         adev->gfx.mec_fw = NULL;
3793         release_firmware(adev->gfx.mec2_fw);
3794         adev->gfx.mec2_fw = NULL;
3795
3796         kfree(adev->gfx.rlc.register_list_format);
3797 }
3798
3799 static void gfx_v10_0_check_fw_write_wait(struct amdgpu_device *adev)
3800 {
3801         adev->gfx.cp_fw_write_wait = false;
3802
3803         switch (adev->asic_type) {
3804         case CHIP_NAVI10:
3805         case CHIP_NAVI12:
3806         case CHIP_NAVI14:
3807                 if ((adev->gfx.me_fw_version >= 0x00000046) &&
3808                     (adev->gfx.me_feature_version >= 27) &&
3809                     (adev->gfx.pfp_fw_version >= 0x00000068) &&
3810                     (adev->gfx.pfp_feature_version >= 27) &&
3811                     (adev->gfx.mec_fw_version >= 0x0000005b) &&
3812                     (adev->gfx.mec_feature_version >= 27))
3813                         adev->gfx.cp_fw_write_wait = true;
3814                 break;
3815         case CHIP_SIENNA_CICHLID:
3816         case CHIP_NAVY_FLOUNDER:
3817         case CHIP_VANGOGH:
3818         case CHIP_DIMGREY_CAVEFISH:
3819                 adev->gfx.cp_fw_write_wait = true;
3820                 break;
3821         default:
3822                 break;
3823         }
3824
3825         if (!adev->gfx.cp_fw_write_wait)
3826                 DRM_WARN_ONCE("CP firmware version too old, please update!");
3827 }
3828
3829
3830 static void gfx_v10_0_init_rlc_ext_microcode(struct amdgpu_device *adev)
3831 {
3832         const struct rlc_firmware_header_v2_1 *rlc_hdr;
3833
3834         rlc_hdr = (const struct rlc_firmware_header_v2_1 *)adev->gfx.rlc_fw->data;
3835         adev->gfx.rlc_srlc_fw_version = le32_to_cpu(rlc_hdr->save_restore_list_cntl_ucode_ver);
3836         adev->gfx.rlc_srlc_feature_version = le32_to_cpu(rlc_hdr->save_restore_list_cntl_feature_ver);
3837         adev->gfx.rlc.save_restore_list_cntl_size_bytes = le32_to_cpu(rlc_hdr->save_restore_list_cntl_size_bytes);
3838         adev->gfx.rlc.save_restore_list_cntl = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_list_cntl_offset_bytes);
3839         adev->gfx.rlc_srlg_fw_version = le32_to_cpu(rlc_hdr->save_restore_list_gpm_ucode_ver);
3840         adev->gfx.rlc_srlg_feature_version = le32_to_cpu(rlc_hdr->save_restore_list_gpm_feature_ver);
3841         adev->gfx.rlc.save_restore_list_gpm_size_bytes = le32_to_cpu(rlc_hdr->save_restore_list_gpm_size_bytes);
3842         adev->gfx.rlc.save_restore_list_gpm = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_list_gpm_offset_bytes);
3843         adev->gfx.rlc_srls_fw_version = le32_to_cpu(rlc_hdr->save_restore_list_srm_ucode_ver);
3844         adev->gfx.rlc_srls_feature_version = le32_to_cpu(rlc_hdr->save_restore_list_srm_feature_ver);
3845         adev->gfx.rlc.save_restore_list_srm_size_bytes = le32_to_cpu(rlc_hdr->save_restore_list_srm_size_bytes);
3846         adev->gfx.rlc.save_restore_list_srm = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_list_srm_offset_bytes);
3847         adev->gfx.rlc.reg_list_format_direct_reg_list_length =
3848                         le32_to_cpu(rlc_hdr->reg_list_format_direct_reg_list_length);
3849 }
3850
3851 static void gfx_v10_0_init_rlc_iram_dram_microcode(struct amdgpu_device *adev)
3852 {
3853         const struct rlc_firmware_header_v2_2 *rlc_hdr;
3854
3855         rlc_hdr = (const struct rlc_firmware_header_v2_2 *)adev->gfx.rlc_fw->data;
3856         adev->gfx.rlc.rlc_iram_ucode_size_bytes = le32_to_cpu(rlc_hdr->rlc_iram_ucode_size_bytes);
3857         adev->gfx.rlc.rlc_iram_ucode = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->rlc_iram_ucode_offset_bytes);
3858         adev->gfx.rlc.rlc_dram_ucode_size_bytes = le32_to_cpu(rlc_hdr->rlc_dram_ucode_size_bytes);
3859         adev->gfx.rlc.rlc_dram_ucode = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->rlc_dram_ucode_offset_bytes);
3860 }
3861
3862 static bool gfx_v10_0_navi10_gfxoff_should_enable(struct amdgpu_device *adev)
3863 {
3864         bool ret = false;
3865
3866         switch (adev->pdev->revision) {
3867         case 0xc2:
3868         case 0xc3:
3869                 ret = true;
3870                 break;
3871         default:
3872                 ret = false;
3873                 break;
3874         }
3875
3876         return ret ;
3877 }
3878
3879 static void gfx_v10_0_check_gfxoff_flag(struct amdgpu_device *adev)
3880 {
3881         switch (adev->asic_type) {
3882         case CHIP_NAVI10:
3883                 if (!gfx_v10_0_navi10_gfxoff_should_enable(adev))
3884                         adev->pm.pp_feature &= ~PP_GFXOFF_MASK;
3885                 break;
3886         default:
3887                 break;
3888         }
3889 }
3890
3891 static int gfx_v10_0_init_microcode(struct amdgpu_device *adev)
3892 {
3893         const char *chip_name;
3894         char fw_name[40];
3895         char wks[10];
3896         int err;
3897         struct amdgpu_firmware_info *info = NULL;
3898         const struct common_firmware_header *header = NULL;
3899         const struct gfx_firmware_header_v1_0 *cp_hdr;
3900         const struct rlc_firmware_header_v2_0 *rlc_hdr;
3901         unsigned int *tmp = NULL;
3902         unsigned int i = 0;
3903         uint16_t version_major;
3904         uint16_t version_minor;
3905
3906         DRM_DEBUG("\n");
3907
3908         memset(wks, 0, sizeof(wks));
3909         switch (adev->asic_type) {
3910         case CHIP_NAVI10:
3911                 chip_name = "navi10";
3912                 break;
3913         case CHIP_NAVI14:
3914                 chip_name = "navi14";
3915                 if (!(adev->pdev->device == 0x7340 &&
3916                       adev->pdev->revision != 0x00))
3917                         snprintf(wks, sizeof(wks), "_wks");
3918                 break;
3919         case CHIP_NAVI12:
3920                 chip_name = "navi12";
3921                 break;
3922         case CHIP_SIENNA_CICHLID:
3923                 chip_name = "sienna_cichlid";
3924                 break;
3925         case CHIP_NAVY_FLOUNDER:
3926                 chip_name = "navy_flounder";
3927                 break;
3928         case CHIP_VANGOGH:
3929                 chip_name = "vangogh";
3930                 break;
3931         case CHIP_DIMGREY_CAVEFISH:
3932                 chip_name = "dimgrey_cavefish";
3933                 break;
3934         case CHIP_BEIGE_GOBY:
3935                 chip_name = "beige_goby";
3936                 break;
3937         default:
3938                 BUG();
3939         }
3940
3941         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_pfp%s.bin", chip_name, wks);
3942         err = request_firmware(&adev->gfx.pfp_fw, fw_name, adev->dev);
3943         if (err)
3944                 goto out;
3945         err = amdgpu_ucode_validate(adev->gfx.pfp_fw);
3946         if (err)
3947                 goto out;
3948         cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data;
3949         adev->gfx.pfp_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
3950         adev->gfx.pfp_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
3951
3952         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_me%s.bin", chip_name, wks);
3953         err = request_firmware(&adev->gfx.me_fw, fw_name, adev->dev);
3954         if (err)
3955                 goto out;
3956         err = amdgpu_ucode_validate(adev->gfx.me_fw);
3957         if (err)
3958                 goto out;
3959         cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data;
3960         adev->gfx.me_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
3961         adev->gfx.me_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
3962
3963         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ce%s.bin", chip_name, wks);
3964         err = request_firmware(&adev->gfx.ce_fw, fw_name, adev->dev);
3965         if (err)
3966                 goto out;
3967         err = amdgpu_ucode_validate(adev->gfx.ce_fw);
3968         if (err)
3969                 goto out;
3970         cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data;
3971         adev->gfx.ce_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
3972         adev->gfx.ce_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
3973
3974         if (!amdgpu_sriov_vf(adev)) {
3975                 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_rlc.bin", chip_name);
3976                 err = request_firmware(&adev->gfx.rlc_fw, fw_name, adev->dev);
3977                 if (err)
3978                         goto out;
3979                 err = amdgpu_ucode_validate(adev->gfx.rlc_fw);
3980                 rlc_hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data;
3981                 version_major = le16_to_cpu(rlc_hdr->header.header_version_major);
3982                 version_minor = le16_to_cpu(rlc_hdr->header.header_version_minor);
3983
3984                 adev->gfx.rlc_fw_version = le32_to_cpu(rlc_hdr->header.ucode_version);
3985                 adev->gfx.rlc_feature_version = le32_to_cpu(rlc_hdr->ucode_feature_version);
3986                 adev->gfx.rlc.save_and_restore_offset =
3987                         le32_to_cpu(rlc_hdr->save_and_restore_offset);
3988                 adev->gfx.rlc.clear_state_descriptor_offset =
3989                         le32_to_cpu(rlc_hdr->clear_state_descriptor_offset);
3990                 adev->gfx.rlc.avail_scratch_ram_locations =
3991                         le32_to_cpu(rlc_hdr->avail_scratch_ram_locations);
3992                 adev->gfx.rlc.reg_restore_list_size =
3993                         le32_to_cpu(rlc_hdr->reg_restore_list_size);
3994                 adev->gfx.rlc.reg_list_format_start =
3995                         le32_to_cpu(rlc_hdr->reg_list_format_start);
3996                 adev->gfx.rlc.reg_list_format_separate_start =
3997                         le32_to_cpu(rlc_hdr->reg_list_format_separate_start);
3998                 adev->gfx.rlc.starting_offsets_start =
3999                         le32_to_cpu(rlc_hdr->starting_offsets_start);
4000                 adev->gfx.rlc.reg_list_format_size_bytes =
4001                         le32_to_cpu(rlc_hdr->reg_list_format_size_bytes);
4002                 adev->gfx.rlc.reg_list_size_bytes =
4003                         le32_to_cpu(rlc_hdr->reg_list_size_bytes);
4004                 adev->gfx.rlc.register_list_format =
4005                         kmalloc(adev->gfx.rlc.reg_list_format_size_bytes +
4006                                         adev->gfx.rlc.reg_list_size_bytes, GFP_KERNEL);
4007                 if (!adev->gfx.rlc.register_list_format) {
4008                         err = -ENOMEM;
4009                         goto out;
4010                 }
4011
4012                 tmp = (unsigned int *)((uintptr_t)rlc_hdr +
4013                                                            le32_to_cpu(rlc_hdr->reg_list_format_array_offset_bytes));
4014                 for (i = 0 ; i < (rlc_hdr->reg_list_format_size_bytes >> 2); i++)
4015                         adev->gfx.rlc.register_list_format[i] = le32_to_cpu(tmp[i]);
4016
4017                 adev->gfx.rlc.register_restore = adev->gfx.rlc.register_list_format + i;
4018
4019                 tmp = (unsigned int *)((uintptr_t)rlc_hdr +
4020                                                            le32_to_cpu(rlc_hdr->reg_list_array_offset_bytes));
4021                 for (i = 0 ; i < (rlc_hdr->reg_list_size_bytes >> 2); i++)
4022                         adev->gfx.rlc.register_restore[i] = le32_to_cpu(tmp[i]);
4023
4024                 if (version_major == 2) {
4025                         if (version_minor >= 1)
4026                                 gfx_v10_0_init_rlc_ext_microcode(adev);
4027                         if (version_minor == 2)
4028                                 gfx_v10_0_init_rlc_iram_dram_microcode(adev);
4029                 }
4030         }
4031
4032         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec%s.bin", chip_name, wks);
4033         err = request_firmware(&adev->gfx.mec_fw, fw_name, adev->dev);
4034         if (err)
4035                 goto out;
4036         err = amdgpu_ucode_validate(adev->gfx.mec_fw);
4037         if (err)
4038                 goto out;
4039         cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
4040         adev->gfx.mec_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
4041         adev->gfx.mec_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
4042
4043         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec2%s.bin", chip_name, wks);
4044         err = request_firmware(&adev->gfx.mec2_fw, fw_name, adev->dev);
4045         if (!err) {
4046                 err = amdgpu_ucode_validate(adev->gfx.mec2_fw);
4047                 if (err)
4048                         goto out;
4049                 cp_hdr = (const struct gfx_firmware_header_v1_0 *)
4050                 adev->gfx.mec2_fw->data;
4051                 adev->gfx.mec2_fw_version =
4052                 le32_to_cpu(cp_hdr->header.ucode_version);
4053                 adev->gfx.mec2_feature_version =
4054                 le32_to_cpu(cp_hdr->ucode_feature_version);
4055         } else {
4056                 err = 0;
4057                 adev->gfx.mec2_fw = NULL;
4058         }
4059
4060         if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
4061                 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_PFP];
4062                 info->ucode_id = AMDGPU_UCODE_ID_CP_PFP;
4063                 info->fw = adev->gfx.pfp_fw;
4064                 header = (const struct common_firmware_header *)info->fw->data;
4065                 adev->firmware.fw_size +=
4066                         ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
4067
4068                 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_ME];
4069                 info->ucode_id = AMDGPU_UCODE_ID_CP_ME;
4070                 info->fw = adev->gfx.me_fw;
4071                 header = (const struct common_firmware_header *)info->fw->data;
4072                 adev->firmware.fw_size +=
4073                         ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
4074
4075                 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_CE];
4076                 info->ucode_id = AMDGPU_UCODE_ID_CP_CE;
4077                 info->fw = adev->gfx.ce_fw;
4078                 header = (const struct common_firmware_header *)info->fw->data;
4079                 adev->firmware.fw_size +=
4080                         ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
4081
4082                 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_G];
4083                 info->ucode_id = AMDGPU_UCODE_ID_RLC_G;
4084                 info->fw = adev->gfx.rlc_fw;
4085                 if (info->fw) {
4086                         header = (const struct common_firmware_header *)info->fw->data;
4087                         adev->firmware.fw_size +=
4088                                 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
4089                 }
4090                 if (adev->gfx.rlc.save_restore_list_cntl_size_bytes &&
4091                     adev->gfx.rlc.save_restore_list_gpm_size_bytes &&
4092                     adev->gfx.rlc.save_restore_list_srm_size_bytes) {
4093                         info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL];
4094                         info->ucode_id = AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL;
4095                         info->fw = adev->gfx.rlc_fw;
4096                         adev->firmware.fw_size +=
4097                                 ALIGN(adev->gfx.rlc.save_restore_list_cntl_size_bytes, PAGE_SIZE);
4098
4099                         info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM];
4100                         info->ucode_id = AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM;
4101                         info->fw = adev->gfx.rlc_fw;
4102                         adev->firmware.fw_size +=
4103                                 ALIGN(adev->gfx.rlc.save_restore_list_gpm_size_bytes, PAGE_SIZE);
4104
4105                         info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM];
4106                         info->ucode_id = AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM;
4107                         info->fw = adev->gfx.rlc_fw;
4108                         adev->firmware.fw_size +=
4109                                 ALIGN(adev->gfx.rlc.save_restore_list_srm_size_bytes, PAGE_SIZE);
4110
4111                         if (adev->gfx.rlc.rlc_iram_ucode_size_bytes &&
4112                             adev->gfx.rlc.rlc_dram_ucode_size_bytes) {
4113                                 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_IRAM];
4114                                 info->ucode_id = AMDGPU_UCODE_ID_RLC_IRAM;
4115                                 info->fw = adev->gfx.rlc_fw;
4116                                 adev->firmware.fw_size +=
4117                                         ALIGN(adev->gfx.rlc.rlc_iram_ucode_size_bytes, PAGE_SIZE);
4118
4119                                 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_DRAM];
4120                                 info->ucode_id = AMDGPU_UCODE_ID_RLC_DRAM;
4121                                 info->fw = adev->gfx.rlc_fw;
4122                                 adev->firmware.fw_size +=
4123                                         ALIGN(adev->gfx.rlc.rlc_dram_ucode_size_bytes, PAGE_SIZE);
4124                         }
4125                 }
4126
4127                 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC1];
4128                 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC1;
4129                 info->fw = adev->gfx.mec_fw;
4130                 header = (const struct common_firmware_header *)info->fw->data;
4131                 cp_hdr = (const struct gfx_firmware_header_v1_0 *)info->fw->data;
4132                 adev->firmware.fw_size +=
4133                         ALIGN(le32_to_cpu(header->ucode_size_bytes) -
4134                               le32_to_cpu(cp_hdr->jt_size) * 4, PAGE_SIZE);
4135
4136                 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC1_JT];
4137                 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC1_JT;
4138                 info->fw = adev->gfx.mec_fw;
4139                 adev->firmware.fw_size +=
4140                         ALIGN(le32_to_cpu(cp_hdr->jt_size) * 4, PAGE_SIZE);
4141
4142                 if (adev->gfx.mec2_fw) {
4143                         info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC2];
4144                         info->ucode_id = AMDGPU_UCODE_ID_CP_MEC2;
4145                         info->fw = adev->gfx.mec2_fw;
4146                         header = (const struct common_firmware_header *)info->fw->data;
4147                         cp_hdr = (const struct gfx_firmware_header_v1_0 *)info->fw->data;
4148                         adev->firmware.fw_size +=
4149                                 ALIGN(le32_to_cpu(header->ucode_size_bytes) -
4150                                       le32_to_cpu(cp_hdr->jt_size) * 4,
4151                                       PAGE_SIZE);
4152                         info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC2_JT];
4153                         info->ucode_id = AMDGPU_UCODE_ID_CP_MEC2_JT;
4154                         info->fw = adev->gfx.mec2_fw;
4155                         adev->firmware.fw_size +=
4156                                 ALIGN(le32_to_cpu(cp_hdr->jt_size) * 4,
4157                                       PAGE_SIZE);
4158                 }
4159         }
4160
4161         gfx_v10_0_check_fw_write_wait(adev);
4162 out:
4163         if (err) {
4164                 dev_err(adev->dev,
4165                         "gfx10: Failed to load firmware \"%s\"\n",
4166                         fw_name);
4167                 release_firmware(adev->gfx.pfp_fw);
4168                 adev->gfx.pfp_fw = NULL;
4169                 release_firmware(adev->gfx.me_fw);
4170                 adev->gfx.me_fw = NULL;
4171                 release_firmware(adev->gfx.ce_fw);
4172                 adev->gfx.ce_fw = NULL;
4173                 release_firmware(adev->gfx.rlc_fw);
4174                 adev->gfx.rlc_fw = NULL;
4175                 release_firmware(adev->gfx.mec_fw);
4176                 adev->gfx.mec_fw = NULL;
4177                 release_firmware(adev->gfx.mec2_fw);
4178                 adev->gfx.mec2_fw = NULL;
4179         }
4180
4181         gfx_v10_0_check_gfxoff_flag(adev);
4182
4183         return err;
4184 }
4185
4186 static u32 gfx_v10_0_get_csb_size(struct amdgpu_device *adev)
4187 {
4188         u32 count = 0;
4189         const struct cs_section_def *sect = NULL;
4190         const struct cs_extent_def *ext = NULL;
4191
4192         /* begin clear state */
4193         count += 2;
4194         /* context control state */
4195         count += 3;
4196
4197         for (sect = gfx10_cs_data; sect->section != NULL; ++sect) {
4198                 for (ext = sect->section; ext->extent != NULL; ++ext) {
4199                         if (sect->id == SECT_CONTEXT)
4200                                 count += 2 + ext->reg_count;
4201                         else
4202                                 return 0;
4203                 }
4204         }
4205
4206         /* set PA_SC_TILE_STEERING_OVERRIDE */
4207         count += 3;
4208         /* end clear state */
4209         count += 2;
4210         /* clear state */
4211         count += 2;
4212
4213         return count;
4214 }
4215
4216 static void gfx_v10_0_get_csb_buffer(struct amdgpu_device *adev,
4217                                     volatile u32 *buffer)
4218 {
4219         u32 count = 0, i;
4220         const struct cs_section_def *sect = NULL;
4221         const struct cs_extent_def *ext = NULL;
4222         int ctx_reg_offset;
4223
4224         if (adev->gfx.rlc.cs_data == NULL)
4225                 return;
4226         if (buffer == NULL)
4227                 return;
4228
4229         buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));
4230         buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
4231
4232         buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CONTEXT_CONTROL, 1));
4233         buffer[count++] = cpu_to_le32(0x80000000);
4234         buffer[count++] = cpu_to_le32(0x80000000);
4235
4236         for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) {
4237                 for (ext = sect->section; ext->extent != NULL; ++ext) {
4238                         if (sect->id == SECT_CONTEXT) {
4239                                 buffer[count++] =
4240                                         cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count));
4241                                 buffer[count++] = cpu_to_le32(ext->reg_index -
4242                                                 PACKET3_SET_CONTEXT_REG_START);
4243                                 for (i = 0; i < ext->reg_count; i++)
4244                                         buffer[count++] = cpu_to_le32(ext->extent[i]);
4245                         } else {
4246                                 return;
4247                         }
4248                 }
4249         }
4250
4251         ctx_reg_offset =
4252                 SOC15_REG_OFFSET(GC, 0, mmPA_SC_TILE_STEERING_OVERRIDE) - PACKET3_SET_CONTEXT_REG_START;
4253         buffer[count++] = cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, 1));
4254         buffer[count++] = cpu_to_le32(ctx_reg_offset);
4255         buffer[count++] = cpu_to_le32(adev->gfx.config.pa_sc_tile_steering_override);
4256
4257         buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));
4258         buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_END_CLEAR_STATE);
4259
4260         buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CLEAR_STATE, 0));
4261         buffer[count++] = cpu_to_le32(0);
4262 }
4263
4264 static void gfx_v10_0_rlc_fini(struct amdgpu_device *adev)
4265 {
4266         /* clear state block */
4267         amdgpu_bo_free_kernel(&adev->gfx.rlc.clear_state_obj,
4268                         &adev->gfx.rlc.clear_state_gpu_addr,
4269                         (void **)&adev->gfx.rlc.cs_ptr);
4270
4271         /* jump table block */
4272         amdgpu_bo_free_kernel(&adev->gfx.rlc.cp_table_obj,
4273                         &adev->gfx.rlc.cp_table_gpu_addr,
4274                         (void **)&adev->gfx.rlc.cp_table_ptr);
4275 }
4276
4277 static int gfx_v10_0_rlc_init(struct amdgpu_device *adev)
4278 {
4279         const struct cs_section_def *cs_data;
4280         int r;
4281
4282         adev->gfx.rlc.cs_data = gfx10_cs_data;
4283
4284         cs_data = adev->gfx.rlc.cs_data;
4285
4286         if (cs_data) {
4287                 /* init clear state block */
4288                 r = amdgpu_gfx_rlc_init_csb(adev);
4289                 if (r)
4290                         return r;
4291         }
4292
4293         /* init spm vmid with 0xf */
4294         if (adev->gfx.rlc.funcs->update_spm_vmid)
4295                 adev->gfx.rlc.funcs->update_spm_vmid(adev, 0xf);
4296
4297         return 0;
4298 }
4299
4300 static void gfx_v10_0_mec_fini(struct amdgpu_device *adev)
4301 {
4302         amdgpu_bo_free_kernel(&adev->gfx.mec.hpd_eop_obj, NULL, NULL);
4303         amdgpu_bo_free_kernel(&adev->gfx.mec.mec_fw_obj, NULL, NULL);
4304 }
4305
4306 static int gfx_v10_0_me_init(struct amdgpu_device *adev)
4307 {
4308         int r;
4309
4310         bitmap_zero(adev->gfx.me.queue_bitmap, AMDGPU_MAX_GFX_QUEUES);
4311
4312         amdgpu_gfx_graphics_queue_acquire(adev);
4313
4314         r = gfx_v10_0_init_microcode(adev);
4315         if (r)
4316                 DRM_ERROR("Failed to load gfx firmware!\n");
4317
4318         return r;
4319 }
4320
4321 static int gfx_v10_0_mec_init(struct amdgpu_device *adev)
4322 {
4323         int r;
4324         u32 *hpd;
4325         const __le32 *fw_data = NULL;
4326         unsigned fw_size;
4327         u32 *fw = NULL;
4328         size_t mec_hpd_size;
4329
4330         const struct gfx_firmware_header_v1_0 *mec_hdr = NULL;
4331
4332         bitmap_zero(adev->gfx.mec.queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES);
4333
4334         /* take ownership of the relevant compute queues */
4335         amdgpu_gfx_compute_queue_acquire(adev);
4336         mec_hpd_size = adev->gfx.num_compute_rings * GFX10_MEC_HPD_SIZE;
4337
4338         if (mec_hpd_size) {
4339                 r = amdgpu_bo_create_reserved(adev, mec_hpd_size, PAGE_SIZE,
4340                                               AMDGPU_GEM_DOMAIN_GTT,
4341                                               &adev->gfx.mec.hpd_eop_obj,
4342                                               &adev->gfx.mec.hpd_eop_gpu_addr,
4343                                               (void **)&hpd);
4344                 if (r) {
4345                         dev_warn(adev->dev, "(%d) create HDP EOP bo failed\n", r);
4346                         gfx_v10_0_mec_fini(adev);
4347                         return r;
4348                 }
4349
4350                 memset(hpd, 0, mec_hpd_size);
4351
4352                 amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj);
4353                 amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj);
4354         }
4355
4356         if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
4357                 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
4358
4359                 fw_data = (const __le32 *) (adev->gfx.mec_fw->data +
4360                          le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes));
4361                 fw_size = le32_to_cpu(mec_hdr->header.ucode_size_bytes);
4362
4363                 r = amdgpu_bo_create_reserved(adev, mec_hdr->header.ucode_size_bytes,
4364                                               PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,
4365                                               &adev->gfx.mec.mec_fw_obj,
4366                                               &adev->gfx.mec.mec_fw_gpu_addr,
4367                                               (void **)&fw);
4368                 if (r) {
4369                         dev_err(adev->dev, "(%d) failed to create mec fw bo\n", r);
4370                         gfx_v10_0_mec_fini(adev);
4371                         return r;
4372                 }
4373
4374                 memcpy(fw, fw_data, fw_size);
4375
4376                 amdgpu_bo_kunmap(adev->gfx.mec.mec_fw_obj);
4377                 amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_obj);
4378         }
4379
4380         return 0;
4381 }
4382
4383 static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t wave, uint32_t address)
4384 {
4385         WREG32_SOC15(GC, 0, mmSQ_IND_INDEX,
4386                 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) |
4387                 (address << SQ_IND_INDEX__INDEX__SHIFT));
4388         return RREG32_SOC15(GC, 0, mmSQ_IND_DATA);
4389 }
4390
4391 static void wave_read_regs(struct amdgpu_device *adev, uint32_t wave,
4392                            uint32_t thread, uint32_t regno,
4393                            uint32_t num, uint32_t *out)
4394 {
4395         WREG32_SOC15(GC, 0, mmSQ_IND_INDEX,
4396                 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) |
4397                 (regno << SQ_IND_INDEX__INDEX__SHIFT) |
4398                 (thread << SQ_IND_INDEX__WORKITEM_ID__SHIFT) |
4399                 (SQ_IND_INDEX__AUTO_INCR_MASK));
4400         while (num--)
4401                 *(out++) = RREG32_SOC15(GC, 0, mmSQ_IND_DATA);
4402 }
4403
4404 static void gfx_v10_0_read_wave_data(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t *dst, int *no_fields)
4405 {
4406         /* in gfx10 the SIMD_ID is specified as part of the INSTANCE
4407          * field when performing a select_se_sh so it should be
4408          * zero here */
4409         WARN_ON(simd != 0);
4410
4411         /* type 2 wave data */
4412         dst[(*no_fields)++] = 2;
4413         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_STATUS);
4414         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_PC_LO);
4415         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_PC_HI);
4416         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXEC_LO);
4417         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXEC_HI);
4418         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_HW_ID1);
4419         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_HW_ID2);
4420         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_INST_DW0);
4421         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_GPR_ALLOC);
4422         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_LDS_ALLOC);
4423         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_TRAPSTS);
4424         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_STS);
4425         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_STS2);
4426         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_DBG1);
4427         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_M0);
4428 }
4429
4430 static void gfx_v10_0_read_wave_sgprs(struct amdgpu_device *adev, uint32_t simd,
4431                                      uint32_t wave, uint32_t start,
4432                                      uint32_t size, uint32_t *dst)
4433 {
4434         WARN_ON(simd != 0);
4435
4436         wave_read_regs(
4437                 adev, wave, 0, start + SQIND_WAVE_SGPRS_OFFSET, size,
4438                 dst);
4439 }
4440
4441 static void gfx_v10_0_read_wave_vgprs(struct amdgpu_device *adev, uint32_t simd,
4442                                       uint32_t wave, uint32_t thread,
4443                                       uint32_t start, uint32_t size,
4444                                       uint32_t *dst)
4445 {
4446         wave_read_regs(
4447                 adev, wave, thread,
4448                 start + SQIND_WAVE_VGPRS_OFFSET, size, dst);
4449 }
4450
4451 static void gfx_v10_0_select_me_pipe_q(struct amdgpu_device *adev,
4452                                        u32 me, u32 pipe, u32 q, u32 vm)
4453 {
4454         nv_grbm_select(adev, me, pipe, q, vm);
4455 }
4456
4457 static void gfx_v10_0_update_perfmon_mgcg(struct amdgpu_device *adev,
4458                                           bool enable)
4459 {
4460         uint32_t data, def;
4461
4462         data = def = RREG32_SOC15(GC, 0, mmRLC_PERFMON_CLK_CNTL);
4463
4464         if (enable)
4465                 data |= RLC_PERFMON_CLK_CNTL__PERFMON_CLOCK_STATE_MASK;
4466         else
4467                 data &= ~RLC_PERFMON_CLK_CNTL__PERFMON_CLOCK_STATE_MASK;
4468
4469         if (data != def)
4470                 WREG32_SOC15(GC, 0, mmRLC_PERFMON_CLK_CNTL, data);
4471 }
4472
4473 static const struct amdgpu_gfx_funcs gfx_v10_0_gfx_funcs = {
4474         .get_gpu_clock_counter = &gfx_v10_0_get_gpu_clock_counter,
4475         .select_se_sh = &gfx_v10_0_select_se_sh,
4476         .read_wave_data = &gfx_v10_0_read_wave_data,
4477         .read_wave_sgprs = &gfx_v10_0_read_wave_sgprs,
4478         .read_wave_vgprs = &gfx_v10_0_read_wave_vgprs,
4479         .select_me_pipe_q = &gfx_v10_0_select_me_pipe_q,
4480         .init_spm_golden = &gfx_v10_0_init_spm_golden_registers,
4481         .update_perfmon_mgcg = &gfx_v10_0_update_perfmon_mgcg,
4482 };
4483
4484 static void gfx_v10_0_gpu_early_init(struct amdgpu_device *adev)
4485 {
4486         u32 gb_addr_config;
4487
4488         adev->gfx.funcs = &gfx_v10_0_gfx_funcs;
4489
4490         switch (adev->asic_type) {
4491         case CHIP_NAVI10:
4492         case CHIP_NAVI14:
4493         case CHIP_NAVI12:
4494                 adev->gfx.config.max_hw_contexts = 8;
4495                 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
4496                 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
4497                 adev->gfx.config.sc_hiz_tile_fifo_size = 0;
4498                 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0;
4499                 gb_addr_config = RREG32_SOC15(GC, 0, mmGB_ADDR_CONFIG);
4500                 break;
4501         case CHIP_SIENNA_CICHLID:
4502         case CHIP_NAVY_FLOUNDER:
4503         case CHIP_VANGOGH:
4504         case CHIP_DIMGREY_CAVEFISH:
4505         case CHIP_BEIGE_GOBY:
4506                 adev->gfx.config.max_hw_contexts = 8;
4507                 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
4508                 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
4509                 adev->gfx.config.sc_hiz_tile_fifo_size = 0;
4510                 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0;
4511                 gb_addr_config = RREG32_SOC15(GC, 0, mmGB_ADDR_CONFIG);
4512                 adev->gfx.config.gb_addr_config_fields.num_pkrs =
4513                         1 << REG_GET_FIELD(gb_addr_config, GB_ADDR_CONFIG, NUM_PKRS);
4514                 break;
4515         default:
4516                 BUG();
4517                 break;
4518         }
4519
4520         adev->gfx.config.gb_addr_config = gb_addr_config;
4521
4522         adev->gfx.config.gb_addr_config_fields.num_pipes = 1 <<
4523                         REG_GET_FIELD(adev->gfx.config.gb_addr_config,
4524                                       GB_ADDR_CONFIG, NUM_PIPES);
4525
4526         adev->gfx.config.max_tile_pipes =
4527                 adev->gfx.config.gb_addr_config_fields.num_pipes;
4528
4529         adev->gfx.config.gb_addr_config_fields.max_compress_frags = 1 <<
4530                         REG_GET_FIELD(adev->gfx.config.gb_addr_config,
4531                                       GB_ADDR_CONFIG, MAX_COMPRESSED_FRAGS);
4532         adev->gfx.config.gb_addr_config_fields.num_rb_per_se = 1 <<
4533                         REG_GET_FIELD(adev->gfx.config.gb_addr_config,
4534                                       GB_ADDR_CONFIG, NUM_RB_PER_SE);
4535         adev->gfx.config.gb_addr_config_fields.num_se = 1 <<
4536                         REG_GET_FIELD(adev->gfx.config.gb_addr_config,
4537                                       GB_ADDR_CONFIG, NUM_SHADER_ENGINES);
4538         adev->gfx.config.gb_addr_config_fields.pipe_interleave_size = 1 << (8 +
4539                         REG_GET_FIELD(adev->gfx.config.gb_addr_config,
4540                                       GB_ADDR_CONFIG, PIPE_INTERLEAVE_SIZE));
4541 }
4542
4543 static int gfx_v10_0_gfx_ring_init(struct amdgpu_device *adev, int ring_id,
4544                                    int me, int pipe, int queue)
4545 {
4546         int r;
4547         struct amdgpu_ring *ring;
4548         unsigned int irq_type;
4549
4550         ring = &adev->gfx.gfx_ring[ring_id];
4551
4552         ring->me = me;
4553         ring->pipe = pipe;
4554         ring->queue = queue;
4555
4556         ring->ring_obj = NULL;
4557         ring->use_doorbell = true;
4558
4559         if (!ring_id)
4560                 ring->doorbell_index = adev->doorbell_index.gfx_ring0 << 1;
4561         else
4562                 ring->doorbell_index = adev->doorbell_index.gfx_ring1 << 1;
4563         sprintf(ring->name, "gfx_%d.%d.%d", ring->me, ring->pipe, ring->queue);
4564
4565         irq_type = AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP + ring->pipe;
4566         r = amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, irq_type,
4567                              AMDGPU_RING_PRIO_DEFAULT, NULL);
4568         if (r)
4569                 return r;
4570         return 0;
4571 }
4572
4573 static int gfx_v10_0_compute_ring_init(struct amdgpu_device *adev, int ring_id,
4574                                        int mec, int pipe, int queue)
4575 {
4576         int r;
4577         unsigned irq_type;
4578         struct amdgpu_ring *ring;
4579         unsigned int hw_prio;
4580
4581         ring = &adev->gfx.compute_ring[ring_id];
4582
4583         /* mec0 is me1 */
4584         ring->me = mec + 1;
4585         ring->pipe = pipe;
4586         ring->queue = queue;
4587
4588         ring->ring_obj = NULL;
4589         ring->use_doorbell = true;
4590         ring->doorbell_index = (adev->doorbell_index.mec_ring0 + ring_id) << 1;
4591         ring->eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr
4592                                 + (ring_id * GFX10_MEC_HPD_SIZE);
4593         sprintf(ring->name, "comp_%d.%d.%d", ring->me, ring->pipe, ring->queue);
4594
4595         irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP
4596                 + ((ring->me - 1) * adev->gfx.mec.num_pipe_per_mec)
4597                 + ring->pipe;
4598         hw_prio = amdgpu_gfx_is_high_priority_compute_queue(adev, ring) ?
4599                         AMDGPU_GFX_PIPE_PRIO_HIGH : AMDGPU_GFX_PIPE_PRIO_NORMAL;
4600         /* type-2 packets are deprecated on MEC, use type-3 instead */
4601         r = amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, irq_type,
4602                              hw_prio, NULL);
4603         if (r)
4604                 return r;
4605
4606         return 0;
4607 }
4608
4609 static int gfx_v10_0_sw_init(void *handle)
4610 {
4611         int i, j, k, r, ring_id = 0;
4612         struct amdgpu_kiq *kiq;
4613         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4614
4615         switch (adev->asic_type) {
4616         case CHIP_NAVI10:
4617         case CHIP_NAVI14:
4618         case CHIP_NAVI12:
4619                 adev->gfx.me.num_me = 1;
4620                 adev->gfx.me.num_pipe_per_me = 1;
4621                 adev->gfx.me.num_queue_per_pipe = 1;
4622                 adev->gfx.mec.num_mec = 2;
4623                 adev->gfx.mec.num_pipe_per_mec = 4;
4624                 adev->gfx.mec.num_queue_per_pipe = 8;
4625                 break;
4626         case CHIP_SIENNA_CICHLID:
4627         case CHIP_NAVY_FLOUNDER:
4628         case CHIP_VANGOGH:
4629         case CHIP_DIMGREY_CAVEFISH:
4630         case CHIP_BEIGE_GOBY:
4631                 adev->gfx.me.num_me = 1;
4632                 adev->gfx.me.num_pipe_per_me = 1;
4633                 adev->gfx.me.num_queue_per_pipe = 1;
4634                 adev->gfx.mec.num_mec = 2;
4635                 adev->gfx.mec.num_pipe_per_mec = 4;
4636                 adev->gfx.mec.num_queue_per_pipe = 4;
4637                 break;
4638         default:
4639                 adev->gfx.me.num_me = 1;
4640                 adev->gfx.me.num_pipe_per_me = 1;
4641                 adev->gfx.me.num_queue_per_pipe = 1;
4642                 adev->gfx.mec.num_mec = 1;
4643                 adev->gfx.mec.num_pipe_per_mec = 4;
4644                 adev->gfx.mec.num_queue_per_pipe = 8;
4645                 break;
4646         }
4647
4648         /* KIQ event */
4649         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP,
4650                               GFX_10_1__SRCID__CP_IB2_INTERRUPT_PKT,
4651                               &adev->gfx.kiq.irq);
4652         if (r)
4653                 return r;
4654
4655         /* EOP Event */
4656         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP,
4657                               GFX_10_1__SRCID__CP_EOP_INTERRUPT,
4658                               &adev->gfx.eop_irq);
4659         if (r)
4660                 return r;
4661
4662         /* Privileged reg */
4663         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_10_1__SRCID__CP_PRIV_REG_FAULT,
4664                               &adev->gfx.priv_reg_irq);
4665         if (r)
4666                 return r;
4667
4668         /* Privileged inst */
4669         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_10_1__SRCID__CP_PRIV_INSTR_FAULT,
4670                               &adev->gfx.priv_inst_irq);
4671         if (r)
4672                 return r;
4673
4674         adev->gfx.gfx_current_status = AMDGPU_GFX_NORMAL_MODE;
4675
4676         gfx_v10_0_scratch_init(adev);
4677
4678         r = gfx_v10_0_me_init(adev);
4679         if (r)
4680                 return r;
4681
4682         r = gfx_v10_0_rlc_init(adev);
4683         if (r) {
4684                 DRM_ERROR("Failed to init rlc BOs!\n");
4685                 return r;
4686         }
4687
4688         r = gfx_v10_0_mec_init(adev);
4689         if (r) {
4690                 DRM_ERROR("Failed to init MEC BOs!\n");
4691                 return r;
4692         }
4693
4694         /* set up the gfx ring */
4695         for (i = 0; i < adev->gfx.me.num_me; i++) {
4696                 for (j = 0; j < adev->gfx.me.num_queue_per_pipe; j++) {
4697                         for (k = 0; k < adev->gfx.me.num_pipe_per_me; k++) {
4698                                 if (!amdgpu_gfx_is_me_queue_enabled(adev, i, k, j))
4699                                         continue;
4700
4701                                 r = gfx_v10_0_gfx_ring_init(adev, ring_id,
4702                                                             i, k, j);
4703                                 if (r)
4704                                         return r;
4705                                 ring_id++;
4706                         }
4707                 }
4708         }
4709
4710         ring_id = 0;
4711         /* set up the compute queues - allocate horizontally across pipes */
4712         for (i = 0; i < adev->gfx.mec.num_mec; ++i) {
4713                 for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) {
4714                         for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) {
4715                                 if (!amdgpu_gfx_is_mec_queue_enabled(adev, i, k,
4716                                                                      j))
4717                                         continue;
4718
4719                                 r = gfx_v10_0_compute_ring_init(adev, ring_id,
4720                                                                 i, k, j);
4721                                 if (r)
4722                                         return r;
4723
4724                                 ring_id++;
4725                         }
4726                 }
4727         }
4728
4729         r = amdgpu_gfx_kiq_init(adev, GFX10_MEC_HPD_SIZE);
4730         if (r) {
4731                 DRM_ERROR("Failed to init KIQ BOs!\n");
4732                 return r;
4733         }
4734
4735         kiq = &adev->gfx.kiq;
4736         r = amdgpu_gfx_kiq_init_ring(adev, &kiq->ring, &kiq->irq);
4737         if (r)
4738                 return r;
4739
4740         r = amdgpu_gfx_mqd_sw_init(adev, sizeof(struct v10_compute_mqd));
4741         if (r)
4742                 return r;
4743
4744         /* allocate visible FB for rlc auto-loading fw */
4745         if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) {
4746                 r = gfx_v10_0_rlc_backdoor_autoload_buffer_init(adev);
4747                 if (r)
4748                         return r;
4749         }
4750
4751         adev->gfx.ce_ram_size = F32_CE_PROGRAM_RAM_SIZE;
4752
4753         gfx_v10_0_gpu_early_init(adev);
4754
4755         return 0;
4756 }
4757
4758 static void gfx_v10_0_pfp_fini(struct amdgpu_device *adev)
4759 {
4760         amdgpu_bo_free_kernel(&adev->gfx.pfp.pfp_fw_obj,
4761                               &adev->gfx.pfp.pfp_fw_gpu_addr,
4762                               (void **)&adev->gfx.pfp.pfp_fw_ptr);
4763 }
4764
4765 static void gfx_v10_0_ce_fini(struct amdgpu_device *adev)
4766 {
4767         amdgpu_bo_free_kernel(&adev->gfx.ce.ce_fw_obj,
4768                               &adev->gfx.ce.ce_fw_gpu_addr,
4769                               (void **)&adev->gfx.ce.ce_fw_ptr);
4770 }
4771
4772 static void gfx_v10_0_me_fini(struct amdgpu_device *adev)
4773 {
4774         amdgpu_bo_free_kernel(&adev->gfx.me.me_fw_obj,
4775                               &adev->gfx.me.me_fw_gpu_addr,
4776                               (void **)&adev->gfx.me.me_fw_ptr);
4777 }
4778
4779 static int gfx_v10_0_sw_fini(void *handle)
4780 {
4781         int i;
4782         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4783
4784         for (i = 0; i < adev->gfx.num_gfx_rings; i++)
4785                 amdgpu_ring_fini(&adev->gfx.gfx_ring[i]);
4786         for (i = 0; i < adev->gfx.num_compute_rings; i++)
4787                 amdgpu_ring_fini(&adev->gfx.compute_ring[i]);
4788
4789         amdgpu_gfx_mqd_sw_fini(adev);
4790         amdgpu_gfx_kiq_free_ring(&adev->gfx.kiq.ring);
4791         amdgpu_gfx_kiq_fini(adev);
4792
4793         gfx_v10_0_pfp_fini(adev);
4794         gfx_v10_0_ce_fini(adev);
4795         gfx_v10_0_me_fini(adev);
4796         gfx_v10_0_rlc_fini(adev);
4797         gfx_v10_0_mec_fini(adev);
4798
4799         if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO)
4800                 gfx_v10_0_rlc_backdoor_autoload_buffer_fini(adev);
4801
4802         gfx_v10_0_free_microcode(adev);
4803
4804         return 0;
4805 }
4806
4807 static void gfx_v10_0_select_se_sh(struct amdgpu_device *adev, u32 se_num,
4808                                    u32 sh_num, u32 instance)
4809 {
4810         u32 data;
4811
4812         if (instance == 0xffffffff)
4813                 data = REG_SET_FIELD(0, GRBM_GFX_INDEX,
4814                                      INSTANCE_BROADCAST_WRITES, 1);
4815         else
4816                 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_INDEX,
4817                                      instance);
4818
4819         if (se_num == 0xffffffff)
4820                 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_BROADCAST_WRITES,
4821                                      1);
4822         else
4823                 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num);
4824
4825         if (sh_num == 0xffffffff)
4826                 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SA_BROADCAST_WRITES,
4827                                      1);
4828         else
4829                 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SA_INDEX, sh_num);
4830
4831         WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, data);
4832 }
4833
4834 static u32 gfx_v10_0_get_rb_active_bitmap(struct amdgpu_device *adev)
4835 {
4836         u32 data, mask;
4837
4838         data = RREG32_SOC15(GC, 0, mmCC_RB_BACKEND_DISABLE);
4839         data |= RREG32_SOC15(GC, 0, mmGC_USER_RB_BACKEND_DISABLE);
4840
4841         data &= CC_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK;
4842         data >>= GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT;
4843
4844         mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_backends_per_se /
4845                                          adev->gfx.config.max_sh_per_se);
4846
4847         return (~data) & mask;
4848 }
4849
4850 static void gfx_v10_0_setup_rb(struct amdgpu_device *adev)
4851 {
4852         int i, j;
4853         u32 data;
4854         u32 active_rbs = 0;
4855         u32 bitmap;
4856         u32 rb_bitmap_width_per_sh = adev->gfx.config.max_backends_per_se /
4857                                         adev->gfx.config.max_sh_per_se;
4858
4859         mutex_lock(&adev->grbm_idx_mutex);
4860         for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
4861                 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
4862                         bitmap = i * adev->gfx.config.max_sh_per_se + j;
4863                         if ((adev->asic_type == CHIP_SIENNA_CICHLID) &&
4864                             ((gfx_v10_3_get_disabled_sa(adev) >> bitmap) & 1))
4865                                 continue;
4866                         gfx_v10_0_select_se_sh(adev, i, j, 0xffffffff);
4867                         data = gfx_v10_0_get_rb_active_bitmap(adev);
4868                         active_rbs |= data << ((i * adev->gfx.config.max_sh_per_se + j) *
4869                                                rb_bitmap_width_per_sh);
4870                 }
4871         }
4872         gfx_v10_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
4873         mutex_unlock(&adev->grbm_idx_mutex);
4874
4875         adev->gfx.config.backend_enable_mask = active_rbs;
4876         adev->gfx.config.num_rbs = hweight32(active_rbs);
4877 }
4878
4879 static u32 gfx_v10_0_init_pa_sc_tile_steering_override(struct amdgpu_device *adev)
4880 {
4881         uint32_t num_sc;
4882         uint32_t enabled_rb_per_sh;
4883         uint32_t active_rb_bitmap;
4884         uint32_t num_rb_per_sc;
4885         uint32_t num_packer_per_sc;
4886         uint32_t pa_sc_tile_steering_override;
4887
4888         /* for ASICs that integrates GFX v10.3
4889          * pa_sc_tile_steering_override should be set to 0 */
4890         if (adev->asic_type >= CHIP_SIENNA_CICHLID)
4891                 return 0;
4892
4893         /* init num_sc */
4894         num_sc = adev->gfx.config.max_shader_engines * adev->gfx.config.max_sh_per_se *
4895                         adev->gfx.config.num_sc_per_sh;
4896         /* init num_rb_per_sc */
4897         active_rb_bitmap = gfx_v10_0_get_rb_active_bitmap(adev);
4898         enabled_rb_per_sh = hweight32(active_rb_bitmap);
4899         num_rb_per_sc = enabled_rb_per_sh / adev->gfx.config.num_sc_per_sh;
4900         /* init num_packer_per_sc */
4901         num_packer_per_sc = adev->gfx.config.num_packer_per_sc;
4902
4903         pa_sc_tile_steering_override = 0;
4904         pa_sc_tile_steering_override |=
4905                 (order_base_2(num_sc) << PA_SC_TILE_STEERING_OVERRIDE__NUM_SC__SHIFT) &
4906                 PA_SC_TILE_STEERING_OVERRIDE__NUM_SC_MASK;
4907         pa_sc_tile_steering_override |=
4908                 (order_base_2(num_rb_per_sc) << PA_SC_TILE_STEERING_OVERRIDE__NUM_RB_PER_SC__SHIFT) &
4909                 PA_SC_TILE_STEERING_OVERRIDE__NUM_RB_PER_SC_MASK;
4910         pa_sc_tile_steering_override |=
4911                 (order_base_2(num_packer_per_sc) << PA_SC_TILE_STEERING_OVERRIDE__NUM_PACKER_PER_SC__SHIFT) &
4912                 PA_SC_TILE_STEERING_OVERRIDE__NUM_PACKER_PER_SC_MASK;
4913
4914         return pa_sc_tile_steering_override;
4915 }
4916
4917 #define DEFAULT_SH_MEM_BASES    (0x6000)
4918
4919 static void gfx_v10_0_init_compute_vmid(struct amdgpu_device *adev)
4920 {
4921         int i;
4922         uint32_t sh_mem_bases;
4923
4924         /*
4925          * Configure apertures:
4926          * LDS:         0x60000000'00000000 - 0x60000001'00000000 (4GB)
4927          * Scratch:     0x60000001'00000000 - 0x60000002'00000000 (4GB)
4928          * GPUVM:       0x60010000'00000000 - 0x60020000'00000000 (1TB)
4929          */
4930         sh_mem_bases = DEFAULT_SH_MEM_BASES | (DEFAULT_SH_MEM_BASES << 16);
4931
4932         mutex_lock(&adev->srbm_mutex);
4933         for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) {
4934                 nv_grbm_select(adev, 0, 0, 0, i);
4935                 /* CP and shaders */
4936                 WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, DEFAULT_SH_MEM_CONFIG);
4937                 WREG32_SOC15(GC, 0, mmSH_MEM_BASES, sh_mem_bases);
4938         }
4939         nv_grbm_select(adev, 0, 0, 0, 0);
4940         mutex_unlock(&adev->srbm_mutex);
4941
4942         /* Initialize all compute VMIDs to have no GDS, GWS, or OA
4943            acccess. These should be enabled by FW for target VMIDs. */
4944         for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) {
4945                 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_BASE, 2 * i, 0);
4946                 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_SIZE, 2 * i, 0);
4947                 WREG32_SOC15_OFFSET(GC, 0, mmGDS_GWS_VMID0, i, 0);
4948                 WREG32_SOC15_OFFSET(GC, 0, mmGDS_OA_VMID0, i, 0);
4949         }
4950 }
4951
4952 static void gfx_v10_0_init_gds_vmid(struct amdgpu_device *adev)
4953 {
4954         int vmid;
4955
4956         /*
4957          * Initialize all compute and user-gfx VMIDs to have no GDS, GWS, or OA
4958          * access. Compute VMIDs should be enabled by FW for target VMIDs,
4959          * the driver can enable them for graphics. VMID0 should maintain
4960          * access so that HWS firmware can save/restore entries.
4961          */
4962         for (vmid = 1; vmid < AMDGPU_NUM_VMID; vmid++) {
4963                 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_BASE, 2 * vmid, 0);
4964                 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_SIZE, 2 * vmid, 0);
4965                 WREG32_SOC15_OFFSET(GC, 0, mmGDS_GWS_VMID0, vmid, 0);
4966                 WREG32_SOC15_OFFSET(GC, 0, mmGDS_OA_VMID0, vmid, 0);
4967         }
4968 }
4969
4970
4971 static void gfx_v10_0_tcp_harvest(struct amdgpu_device *adev)
4972 {
4973         int i, j, k;
4974         int max_wgp_per_sh = adev->gfx.config.max_cu_per_sh >> 1;
4975         u32 tmp, wgp_active_bitmap = 0;
4976         u32 gcrd_targets_disable_tcp = 0;
4977         u32 utcl_invreq_disable = 0;
4978         /*
4979          * GCRD_TARGETS_DISABLE field contains
4980          * for Navi10/Navi12: GL1C=[18:15], SQC=[14:10], TCP=[9:0]
4981          * for Navi14: GL1C=[21:18], SQC=[17:12], TCP=[11:0]
4982          */
4983         u32 gcrd_targets_disable_mask = amdgpu_gfx_create_bitmask(
4984                 2 * max_wgp_per_sh + /* TCP */
4985                 max_wgp_per_sh + /* SQC */
4986                 4); /* GL1C */
4987         /*
4988          * UTCL1_UTCL0_INVREQ_DISABLE field contains
4989          * for Navi10Navi12: SQG=[24], RMI=[23:20], SQC=[19:10], TCP=[9:0]
4990          * for Navi14: SQG=[28], RMI=[27:24], SQC=[23:12], TCP=[11:0]
4991          */
4992         u32 utcl_invreq_disable_mask = amdgpu_gfx_create_bitmask(
4993                 2 * max_wgp_per_sh + /* TCP */
4994                 2 * max_wgp_per_sh + /* SQC */
4995                 4 + /* RMI */
4996                 1); /* SQG */
4997
4998         if (adev->asic_type == CHIP_NAVI10 ||
4999             adev->asic_type == CHIP_NAVI14 ||
5000             adev->asic_type == CHIP_NAVI12) {
5001                 mutex_lock(&adev->grbm_idx_mutex);
5002                 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
5003                         for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
5004                                 gfx_v10_0_select_se_sh(adev, i, j, 0xffffffff);
5005                                 wgp_active_bitmap = gfx_v10_0_get_wgp_active_bitmap_per_sh(adev);
5006                                 /*
5007                                  * Set corresponding TCP bits for the inactive WGPs in
5008                                  * GCRD_SA_TARGETS_DISABLE
5009                                  */
5010                                 gcrd_targets_disable_tcp = 0;
5011                                 /* Set TCP & SQC bits in UTCL1_UTCL0_INVREQ_DISABLE */
5012                                 utcl_invreq_disable = 0;
5013
5014                                 for (k = 0; k < max_wgp_per_sh; k++) {
5015                                         if (!(wgp_active_bitmap & (1 << k))) {
5016                                                 gcrd_targets_disable_tcp |= 3 << (2 * k);
5017                                                 utcl_invreq_disable |= (3 << (2 * k)) |
5018                                                         (3 << (2 * (max_wgp_per_sh + k)));
5019                                         }
5020                                 }
5021
5022                                 tmp = RREG32_SOC15(GC, 0, mmUTCL1_UTCL0_INVREQ_DISABLE);
5023                                 /* only override TCP & SQC bits */
5024                                 tmp &= 0xffffffff << (4 * max_wgp_per_sh);
5025                                 tmp |= (utcl_invreq_disable & utcl_invreq_disable_mask);
5026                                 WREG32_SOC15(GC, 0, mmUTCL1_UTCL0_INVREQ_DISABLE, tmp);
5027
5028                                 tmp = RREG32_SOC15(GC, 0, mmGCRD_SA_TARGETS_DISABLE);
5029                                 /* only override TCP bits */
5030                                 tmp &= 0xffffffff << (2 * max_wgp_per_sh);
5031                                 tmp |= (gcrd_targets_disable_tcp & gcrd_targets_disable_mask);
5032                                 WREG32_SOC15(GC, 0, mmGCRD_SA_TARGETS_DISABLE, tmp);
5033                         }
5034                 }
5035
5036                 gfx_v10_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
5037                 mutex_unlock(&adev->grbm_idx_mutex);
5038         }
5039 }
5040
5041 static void gfx_v10_0_get_tcc_info(struct amdgpu_device *adev)
5042 {
5043         /* TCCs are global (not instanced). */
5044         uint32_t tcc_disable;
5045
5046         if (adev->asic_type >= CHIP_SIENNA_CICHLID) {
5047                 tcc_disable = RREG32_SOC15(GC, 0, mmCGTS_TCC_DISABLE_gc_10_3) |
5048                               RREG32_SOC15(GC, 0, mmCGTS_USER_TCC_DISABLE_gc_10_3);
5049         } else {
5050                 tcc_disable = RREG32_SOC15(GC, 0, mmCGTS_TCC_DISABLE) |
5051                               RREG32_SOC15(GC, 0, mmCGTS_USER_TCC_DISABLE);
5052         }
5053
5054         adev->gfx.config.tcc_disabled_mask =
5055                 REG_GET_FIELD(tcc_disable, CGTS_TCC_DISABLE, TCC_DISABLE) |
5056                 (REG_GET_FIELD(tcc_disable, CGTS_TCC_DISABLE, HI_TCC_DISABLE) << 16);
5057 }
5058
5059 static void gfx_v10_0_constants_init(struct amdgpu_device *adev)
5060 {
5061         u32 tmp;
5062         int i;
5063
5064         WREG32_FIELD15(GC, 0, GRBM_CNTL, READ_TIMEOUT, 0xff);
5065
5066         gfx_v10_0_setup_rb(adev);
5067         gfx_v10_0_get_cu_info(adev, &adev->gfx.cu_info);
5068         gfx_v10_0_get_tcc_info(adev);
5069         adev->gfx.config.pa_sc_tile_steering_override =
5070                 gfx_v10_0_init_pa_sc_tile_steering_override(adev);
5071
5072         /* XXX SH_MEM regs */
5073         /* where to put LDS, scratch, GPUVM in FSA64 space */
5074         mutex_lock(&adev->srbm_mutex);
5075         for (i = 0; i < adev->vm_manager.id_mgr[AMDGPU_GFXHUB_0].num_ids; i++) {
5076                 nv_grbm_select(adev, 0, 0, 0, i);
5077                 /* CP and shaders */
5078                 WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, DEFAULT_SH_MEM_CONFIG);
5079                 if (i != 0) {
5080                         tmp = REG_SET_FIELD(0, SH_MEM_BASES, PRIVATE_BASE,
5081                                 (adev->gmc.private_aperture_start >> 48));
5082                         tmp = REG_SET_FIELD(tmp, SH_MEM_BASES, SHARED_BASE,
5083                                 (adev->gmc.shared_aperture_start >> 48));
5084                         WREG32_SOC15(GC, 0, mmSH_MEM_BASES, tmp);
5085                 }
5086         }
5087         nv_grbm_select(adev, 0, 0, 0, 0);
5088
5089         mutex_unlock(&adev->srbm_mutex);
5090
5091         gfx_v10_0_init_compute_vmid(adev);
5092         gfx_v10_0_init_gds_vmid(adev);
5093
5094 }
5095
5096 static void gfx_v10_0_enable_gui_idle_interrupt(struct amdgpu_device *adev,
5097                                                bool enable)
5098 {
5099         u32 tmp;
5100
5101         if (amdgpu_sriov_vf(adev))
5102                 return;
5103
5104         tmp = RREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0);
5105
5106         tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE,
5107                             enable ? 1 : 0);
5108         tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE,
5109                             enable ? 1 : 0);
5110         tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE,
5111                             enable ? 1 : 0);
5112         tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, GFX_IDLE_INT_ENABLE,
5113                             enable ? 1 : 0);
5114
5115         WREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0, tmp);
5116 }
5117
5118 static int gfx_v10_0_init_csb(struct amdgpu_device *adev)
5119 {
5120         adev->gfx.rlc.funcs->get_csb_buffer(adev, adev->gfx.rlc.cs_ptr);
5121
5122         /* csib */
5123         if (adev->asic_type == CHIP_NAVI12) {
5124                 WREG32_SOC15_RLC(GC, 0, mmRLC_CSIB_ADDR_HI,
5125                                 adev->gfx.rlc.clear_state_gpu_addr >> 32);
5126                 WREG32_SOC15_RLC(GC, 0, mmRLC_CSIB_ADDR_LO,
5127                                 adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc);
5128                 WREG32_SOC15_RLC(GC, 0, mmRLC_CSIB_LENGTH, adev->gfx.rlc.clear_state_size);
5129         } else {
5130                 WREG32_SOC15(GC, 0, mmRLC_CSIB_ADDR_HI,
5131                                 adev->gfx.rlc.clear_state_gpu_addr >> 32);
5132                 WREG32_SOC15(GC, 0, mmRLC_CSIB_ADDR_LO,
5133                                 adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc);
5134                 WREG32_SOC15(GC, 0, mmRLC_CSIB_LENGTH, adev->gfx.rlc.clear_state_size);
5135         }
5136         return 0;
5137 }
5138
5139 static void gfx_v10_0_rlc_stop(struct amdgpu_device *adev)
5140 {
5141         u32 tmp = RREG32_SOC15(GC, 0, mmRLC_CNTL);
5142
5143         tmp = REG_SET_FIELD(tmp, RLC_CNTL, RLC_ENABLE_F32, 0);
5144         WREG32_SOC15(GC, 0, mmRLC_CNTL, tmp);
5145 }
5146
5147 static void gfx_v10_0_rlc_reset(struct amdgpu_device *adev)
5148 {
5149         WREG32_FIELD15(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 1);
5150         udelay(50);
5151         WREG32_FIELD15(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 0);
5152         udelay(50);
5153 }
5154
5155 static void gfx_v10_0_rlc_smu_handshake_cntl(struct amdgpu_device *adev,
5156                                              bool enable)
5157 {
5158         uint32_t rlc_pg_cntl;
5159
5160         rlc_pg_cntl = RREG32_SOC15(GC, 0, mmRLC_PG_CNTL);
5161
5162         if (!enable) {
5163                 /* RLC_PG_CNTL[23] = 0 (default)
5164                  * RLC will wait for handshake acks with SMU
5165                  * GFXOFF will be enabled
5166                  * RLC_PG_CNTL[23] = 1
5167                  * RLC will not issue any message to SMU
5168                  * hence no handshake between SMU & RLC
5169                  * GFXOFF will be disabled
5170                  */
5171                 rlc_pg_cntl |= 0x800000;
5172         } else
5173                 rlc_pg_cntl &= ~0x800000;
5174         WREG32_SOC15(GC, 0, mmRLC_PG_CNTL, rlc_pg_cntl);
5175 }
5176
5177 static void gfx_v10_0_rlc_start(struct amdgpu_device *adev)
5178 {
5179         /* TODO: enable rlc & smu handshake until smu
5180          * and gfxoff feature works as expected */
5181         if (!(amdgpu_pp_feature_mask & PP_GFXOFF_MASK))
5182                 gfx_v10_0_rlc_smu_handshake_cntl(adev, false);
5183
5184         WREG32_FIELD15(GC, 0, RLC_CNTL, RLC_ENABLE_F32, 1);
5185         udelay(50);
5186 }
5187
5188 static void gfx_v10_0_rlc_enable_srm(struct amdgpu_device *adev)
5189 {
5190         uint32_t tmp;
5191
5192         /* enable Save Restore Machine */
5193         tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_CNTL));
5194         tmp |= RLC_SRM_CNTL__AUTO_INCR_ADDR_MASK;
5195         tmp |= RLC_SRM_CNTL__SRM_ENABLE_MASK;
5196         WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_CNTL), tmp);
5197 }
5198
5199 static int gfx_v10_0_rlc_load_microcode(struct amdgpu_device *adev)
5200 {
5201         const struct rlc_firmware_header_v2_0 *hdr;
5202         const __le32 *fw_data;
5203         unsigned i, fw_size;
5204
5205         if (!adev->gfx.rlc_fw)
5206                 return -EINVAL;
5207
5208         hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data;
5209         amdgpu_ucode_print_rlc_hdr(&hdr->header);
5210
5211         fw_data = (const __le32 *)(adev->gfx.rlc_fw->data +
5212                            le32_to_cpu(hdr->header.ucode_array_offset_bytes));
5213         fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
5214
5215         WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_ADDR,
5216                      RLCG_UCODE_LOADING_START_ADDRESS);
5217
5218         for (i = 0; i < fw_size; i++)
5219                 WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_DATA,
5220                              le32_to_cpup(fw_data++));
5221
5222         WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_ADDR, adev->gfx.rlc_fw_version);
5223
5224         return 0;
5225 }
5226
5227 static int gfx_v10_0_rlc_resume(struct amdgpu_device *adev)
5228 {
5229         int r;
5230
5231         if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
5232
5233                 r = gfx_v10_0_wait_for_rlc_autoload_complete(adev);
5234                 if (r)
5235                         return r;
5236
5237                 gfx_v10_0_init_csb(adev);
5238
5239                 if (!amdgpu_sriov_vf(adev)) /* enable RLC SRM */
5240                         gfx_v10_0_rlc_enable_srm(adev);
5241         } else {
5242                 if (amdgpu_sriov_vf(adev)) {
5243                         gfx_v10_0_init_csb(adev);
5244                         return 0;
5245                 }
5246
5247                 adev->gfx.rlc.funcs->stop(adev);
5248
5249                 /* disable CG */
5250                 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, 0);
5251
5252                 /* disable PG */
5253                 WREG32_SOC15(GC, 0, mmRLC_PG_CNTL, 0);
5254
5255                 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
5256                         /* legacy rlc firmware loading */
5257                         r = gfx_v10_0_rlc_load_microcode(adev);
5258                         if (r)
5259                                 return r;
5260                 } else if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) {
5261                         /* rlc backdoor autoload firmware */
5262                         r = gfx_v10_0_rlc_backdoor_autoload_enable(adev);
5263                         if (r)
5264                                 return r;
5265                 }
5266
5267                 gfx_v10_0_init_csb(adev);
5268
5269                 adev->gfx.rlc.funcs->start(adev);
5270
5271                 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) {
5272                         r = gfx_v10_0_wait_for_rlc_autoload_complete(adev);
5273                         if (r)
5274                                 return r;
5275                 }
5276         }
5277         return 0;
5278 }
5279
5280 static struct {
5281         FIRMWARE_ID     id;
5282         unsigned int    offset;
5283         unsigned int    size;
5284 } rlc_autoload_info[FIRMWARE_ID_MAX];
5285
5286 static int gfx_v10_0_parse_rlc_toc(struct amdgpu_device *adev)
5287 {
5288         int ret;
5289         RLC_TABLE_OF_CONTENT *rlc_toc;
5290
5291         ret = amdgpu_bo_create_reserved(adev, adev->psp.toc_bin_size, PAGE_SIZE,
5292                                         AMDGPU_GEM_DOMAIN_GTT,
5293                                         &adev->gfx.rlc.rlc_toc_bo,
5294                                         &adev->gfx.rlc.rlc_toc_gpu_addr,
5295                                         (void **)&adev->gfx.rlc.rlc_toc_buf);
5296         if (ret) {
5297                 dev_err(adev->dev, "(%d) failed to create rlc toc bo\n", ret);
5298                 return ret;
5299         }
5300
5301         /* Copy toc from psp sos fw to rlc toc buffer */
5302         memcpy(adev->gfx.rlc.rlc_toc_buf, adev->psp.toc_start_addr, adev->psp.toc_bin_size);
5303
5304         rlc_toc = (RLC_TABLE_OF_CONTENT *)adev->gfx.rlc.rlc_toc_buf;
5305         while (rlc_toc && (rlc_toc->id > FIRMWARE_ID_INVALID) &&
5306                 (rlc_toc->id < FIRMWARE_ID_MAX)) {
5307                 if ((rlc_toc->id >= FIRMWARE_ID_CP_CE) &&
5308                     (rlc_toc->id <= FIRMWARE_ID_CP_MES)) {
5309                         /* Offset needs 4KB alignment */
5310                         rlc_toc->offset = ALIGN(rlc_toc->offset * 4, PAGE_SIZE);
5311                 }
5312
5313                 rlc_autoload_info[rlc_toc->id].id = rlc_toc->id;
5314                 rlc_autoload_info[rlc_toc->id].offset = rlc_toc->offset * 4;
5315                 rlc_autoload_info[rlc_toc->id].size = rlc_toc->size * 4;
5316
5317                 rlc_toc++;
5318         }
5319
5320         return 0;
5321 }
5322
5323 static uint32_t gfx_v10_0_calc_toc_total_size(struct amdgpu_device *adev)
5324 {
5325         uint32_t total_size = 0;
5326         FIRMWARE_ID id;
5327         int ret;
5328
5329         ret = gfx_v10_0_parse_rlc_toc(adev);
5330         if (ret) {
5331                 dev_err(adev->dev, "failed to parse rlc toc\n");
5332                 return 0;
5333         }
5334
5335         for (id = FIRMWARE_ID_RLC_G_UCODE; id < FIRMWARE_ID_MAX; id++)
5336                 total_size += rlc_autoload_info[id].size;
5337
5338         /* In case the offset in rlc toc ucode is aligned */
5339         if (total_size < rlc_autoload_info[FIRMWARE_ID_MAX-1].offset)
5340                 total_size = rlc_autoload_info[FIRMWARE_ID_MAX-1].offset +
5341                                 rlc_autoload_info[FIRMWARE_ID_MAX-1].size;
5342
5343         return total_size;
5344 }
5345
5346 static int gfx_v10_0_rlc_backdoor_autoload_buffer_init(struct amdgpu_device *adev)
5347 {
5348         int r;
5349         uint32_t total_size;
5350
5351         total_size = gfx_v10_0_calc_toc_total_size(adev);
5352
5353         r = amdgpu_bo_create_reserved(adev, total_size, PAGE_SIZE,
5354                                       AMDGPU_GEM_DOMAIN_GTT,
5355                                       &adev->gfx.rlc.rlc_autoload_bo,
5356                                       &adev->gfx.rlc.rlc_autoload_gpu_addr,
5357                                       (void **)&adev->gfx.rlc.rlc_autoload_ptr);
5358         if (r) {
5359                 dev_err(adev->dev, "(%d) failed to create fw autoload bo\n", r);
5360                 return r;
5361         }
5362
5363         return 0;
5364 }
5365
5366 static void gfx_v10_0_rlc_backdoor_autoload_buffer_fini(struct amdgpu_device *adev)
5367 {
5368         amdgpu_bo_free_kernel(&adev->gfx.rlc.rlc_toc_bo,
5369                               &adev->gfx.rlc.rlc_toc_gpu_addr,
5370                               (void **)&adev->gfx.rlc.rlc_toc_buf);
5371         amdgpu_bo_free_kernel(&adev->gfx.rlc.rlc_autoload_bo,
5372                               &adev->gfx.rlc.rlc_autoload_gpu_addr,
5373                               (void **)&adev->gfx.rlc.rlc_autoload_ptr);
5374 }
5375
5376 static void gfx_v10_0_rlc_backdoor_autoload_copy_ucode(struct amdgpu_device *adev,
5377                                                        FIRMWARE_ID id,
5378                                                        const void *fw_data,
5379                                                        uint32_t fw_size)
5380 {
5381         uint32_t toc_offset;
5382         uint32_t toc_fw_size;
5383         char *ptr = adev->gfx.rlc.rlc_autoload_ptr;
5384
5385         if (id <= FIRMWARE_ID_INVALID || id >= FIRMWARE_ID_MAX)
5386                 return;
5387
5388         toc_offset = rlc_autoload_info[id].offset;
5389         toc_fw_size = rlc_autoload_info[id].size;
5390
5391         if (fw_size == 0)
5392                 fw_size = toc_fw_size;
5393
5394         if (fw_size > toc_fw_size)
5395                 fw_size = toc_fw_size;
5396
5397         memcpy(ptr + toc_offset, fw_data, fw_size);
5398
5399         if (fw_size < toc_fw_size)
5400                 memset(ptr + toc_offset + fw_size, 0, toc_fw_size - fw_size);
5401 }
5402
5403 static void gfx_v10_0_rlc_backdoor_autoload_copy_toc_ucode(struct amdgpu_device *adev)
5404 {
5405         void *data;
5406         uint32_t size;
5407
5408         data = adev->gfx.rlc.rlc_toc_buf;
5409         size = rlc_autoload_info[FIRMWARE_ID_RLC_TOC].size;
5410
5411         gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5412                                                    FIRMWARE_ID_RLC_TOC,
5413                                                    data, size);
5414 }
5415
5416 static void gfx_v10_0_rlc_backdoor_autoload_copy_gfx_ucode(struct amdgpu_device *adev)
5417 {
5418         const __le32 *fw_data;
5419         uint32_t fw_size;
5420         const struct gfx_firmware_header_v1_0 *cp_hdr;
5421         const struct rlc_firmware_header_v2_0 *rlc_hdr;
5422
5423         /* pfp ucode */
5424         cp_hdr = (const struct gfx_firmware_header_v1_0 *)
5425                 adev->gfx.pfp_fw->data;
5426         fw_data = (const __le32 *)(adev->gfx.pfp_fw->data +
5427                 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes));
5428         fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes);
5429         gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5430                                                    FIRMWARE_ID_CP_PFP,
5431                                                    fw_data, fw_size);
5432
5433         /* ce ucode */
5434         cp_hdr = (const struct gfx_firmware_header_v1_0 *)
5435                 adev->gfx.ce_fw->data;
5436         fw_data = (const __le32 *)(adev->gfx.ce_fw->data +
5437                 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes));
5438         fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes);
5439         gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5440                                                    FIRMWARE_ID_CP_CE,
5441                                                    fw_data, fw_size);
5442
5443         /* me ucode */
5444         cp_hdr = (const struct gfx_firmware_header_v1_0 *)
5445                 adev->gfx.me_fw->data;
5446         fw_data = (const __le32 *)(adev->gfx.me_fw->data +
5447                 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes));
5448         fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes);
5449         gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5450                                                    FIRMWARE_ID_CP_ME,
5451                                                    fw_data, fw_size);
5452
5453         /* rlc ucode */
5454         rlc_hdr = (const struct rlc_firmware_header_v2_0 *)
5455                 adev->gfx.rlc_fw->data;
5456         fw_data = (const __le32 *)(adev->gfx.rlc_fw->data +
5457                 le32_to_cpu(rlc_hdr->header.ucode_array_offset_bytes));
5458         fw_size = le32_to_cpu(rlc_hdr->header.ucode_size_bytes);
5459         gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5460                                                    FIRMWARE_ID_RLC_G_UCODE,
5461                                                    fw_data, fw_size);
5462
5463         /* mec1 ucode */
5464         cp_hdr = (const struct gfx_firmware_header_v1_0 *)
5465                 adev->gfx.mec_fw->data;
5466         fw_data = (const __le32 *) (adev->gfx.mec_fw->data +
5467                 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes));
5468         fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes) -
5469                 cp_hdr->jt_size * 4;
5470         gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5471                                                    FIRMWARE_ID_CP_MEC,
5472                                                    fw_data, fw_size);
5473         /* mec2 ucode is not necessary if mec2 ucode is same as mec1 */
5474 }
5475
5476 /* Temporarily put sdma part here */
5477 static void gfx_v10_0_rlc_backdoor_autoload_copy_sdma_ucode(struct amdgpu_device *adev)
5478 {
5479         const __le32 *fw_data;
5480         uint32_t fw_size;
5481         const struct sdma_firmware_header_v1_0 *sdma_hdr;
5482         int i;
5483
5484         for (i = 0; i < adev->sdma.num_instances; i++) {
5485                 sdma_hdr = (const struct sdma_firmware_header_v1_0 *)
5486                         adev->sdma.instance[i].fw->data;
5487                 fw_data = (const __le32 *) (adev->sdma.instance[i].fw->data +
5488                         le32_to_cpu(sdma_hdr->header.ucode_array_offset_bytes));
5489                 fw_size = le32_to_cpu(sdma_hdr->header.ucode_size_bytes);
5490
5491                 if (i == 0) {
5492                         gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5493                                 FIRMWARE_ID_SDMA0_UCODE, fw_data, fw_size);
5494                         gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5495                                 FIRMWARE_ID_SDMA0_JT,
5496                                 (uint32_t *)fw_data +
5497                                 sdma_hdr->jt_offset,
5498                                 sdma_hdr->jt_size * 4);
5499                 } else if (i == 1) {
5500                         gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5501                                 FIRMWARE_ID_SDMA1_UCODE, fw_data, fw_size);
5502                         gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5503                                 FIRMWARE_ID_SDMA1_JT,
5504                                 (uint32_t *)fw_data +
5505                                 sdma_hdr->jt_offset,
5506                                 sdma_hdr->jt_size * 4);
5507                 }
5508         }
5509 }
5510
5511 static int gfx_v10_0_rlc_backdoor_autoload_enable(struct amdgpu_device *adev)
5512 {
5513         uint32_t rlc_g_offset, rlc_g_size, tmp;
5514         uint64_t gpu_addr;
5515
5516         gfx_v10_0_rlc_backdoor_autoload_copy_toc_ucode(adev);
5517         gfx_v10_0_rlc_backdoor_autoload_copy_sdma_ucode(adev);
5518         gfx_v10_0_rlc_backdoor_autoload_copy_gfx_ucode(adev);
5519
5520         rlc_g_offset = rlc_autoload_info[FIRMWARE_ID_RLC_G_UCODE].offset;
5521         rlc_g_size = rlc_autoload_info[FIRMWARE_ID_RLC_G_UCODE].size;
5522         gpu_addr = adev->gfx.rlc.rlc_autoload_gpu_addr + rlc_g_offset;
5523
5524         WREG32_SOC15(GC, 0, mmRLC_HYP_BOOTLOAD_ADDR_HI, upper_32_bits(gpu_addr));
5525         WREG32_SOC15(GC, 0, mmRLC_HYP_BOOTLOAD_ADDR_LO, lower_32_bits(gpu_addr));
5526         WREG32_SOC15(GC, 0, mmRLC_HYP_BOOTLOAD_SIZE, rlc_g_size);
5527
5528         tmp = RREG32_SOC15(GC, 0, mmRLC_HYP_RESET_VECTOR);
5529         if (!(tmp & (RLC_HYP_RESET_VECTOR__COLD_BOOT_EXIT_MASK |
5530                    RLC_HYP_RESET_VECTOR__VDDGFX_EXIT_MASK))) {
5531                 DRM_ERROR("Neither COLD_BOOT_EXIT nor VDDGFX_EXIT is set\n");
5532                 return -EINVAL;
5533         }
5534
5535         tmp = RREG32_SOC15(GC, 0, mmRLC_CNTL);
5536         if (tmp & RLC_CNTL__RLC_ENABLE_F32_MASK) {
5537                 DRM_ERROR("RLC ROM should halt itself\n");
5538                 return -EINVAL;
5539         }
5540
5541         return 0;
5542 }
5543
5544 static int gfx_v10_0_rlc_backdoor_autoload_config_me_cache(struct amdgpu_device *adev)
5545 {
5546         uint32_t usec_timeout = 50000;  /* wait for 50ms */
5547         uint32_t tmp;
5548         int i;
5549         uint64_t addr;
5550
5551         /* Trigger an invalidation of the L1 instruction caches */
5552         tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL);
5553         tmp = REG_SET_FIELD(tmp, CP_ME_IC_OP_CNTL, INVALIDATE_CACHE, 1);
5554         WREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL, tmp);
5555
5556         /* Wait for invalidation complete */
5557         for (i = 0; i < usec_timeout; i++) {
5558                 tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL);
5559                 if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL,
5560                         INVALIDATE_CACHE_COMPLETE))
5561                         break;
5562                 udelay(1);
5563         }
5564
5565         if (i >= usec_timeout) {
5566                 dev_err(adev->dev, "failed to invalidate instruction cache\n");
5567                 return -EINVAL;
5568         }
5569
5570         /* Program me ucode address into intruction cache address register */
5571         addr = adev->gfx.rlc.rlc_autoload_gpu_addr +
5572                 rlc_autoload_info[FIRMWARE_ID_CP_ME].offset;
5573         WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_LO,
5574                         lower_32_bits(addr) & 0xFFFFF000);
5575         WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_HI,
5576                         upper_32_bits(addr));
5577
5578         return 0;
5579 }
5580
5581 static int gfx_v10_0_rlc_backdoor_autoload_config_ce_cache(struct amdgpu_device *adev)
5582 {
5583         uint32_t usec_timeout = 50000;  /* wait for 50ms */
5584         uint32_t tmp;
5585         int i;
5586         uint64_t addr;
5587
5588         /* Trigger an invalidation of the L1 instruction caches */
5589         tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL);
5590         tmp = REG_SET_FIELD(tmp, CP_CE_IC_OP_CNTL, INVALIDATE_CACHE, 1);
5591         WREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL, tmp);
5592
5593         /* Wait for invalidation complete */
5594         for (i = 0; i < usec_timeout; i++) {
5595                 tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL);
5596                 if (1 == REG_GET_FIELD(tmp, CP_CE_IC_OP_CNTL,
5597                         INVALIDATE_CACHE_COMPLETE))
5598                         break;
5599                 udelay(1);
5600         }
5601
5602         if (i >= usec_timeout) {
5603                 dev_err(adev->dev, "failed to invalidate instruction cache\n");
5604                 return -EINVAL;
5605         }
5606
5607         /* Program ce ucode address into intruction cache address register */
5608         addr = adev->gfx.rlc.rlc_autoload_gpu_addr +
5609                 rlc_autoload_info[FIRMWARE_ID_CP_CE].offset;
5610         WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_LO,
5611                         lower_32_bits(addr) & 0xFFFFF000);
5612         WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_HI,
5613                         upper_32_bits(addr));
5614
5615         return 0;
5616 }
5617
5618 static int gfx_v10_0_rlc_backdoor_autoload_config_pfp_cache(struct amdgpu_device *adev)
5619 {
5620         uint32_t usec_timeout = 50000;  /* wait for 50ms */
5621         uint32_t tmp;
5622         int i;
5623         uint64_t addr;
5624
5625         /* Trigger an invalidation of the L1 instruction caches */
5626         tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL);
5627         tmp = REG_SET_FIELD(tmp, CP_PFP_IC_OP_CNTL, INVALIDATE_CACHE, 1);
5628         WREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL, tmp);
5629
5630         /* Wait for invalidation complete */
5631         for (i = 0; i < usec_timeout; i++) {
5632                 tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL);
5633                 if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL,
5634                         INVALIDATE_CACHE_COMPLETE))
5635                         break;
5636                 udelay(1);
5637         }
5638
5639         if (i >= usec_timeout) {
5640                 dev_err(adev->dev, "failed to invalidate instruction cache\n");
5641                 return -EINVAL;
5642         }
5643
5644         /* Program pfp ucode address into intruction cache address register */
5645         addr = adev->gfx.rlc.rlc_autoload_gpu_addr +
5646                 rlc_autoload_info[FIRMWARE_ID_CP_PFP].offset;
5647         WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_LO,
5648                         lower_32_bits(addr) & 0xFFFFF000);
5649         WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_HI,
5650                         upper_32_bits(addr));
5651
5652         return 0;
5653 }
5654
5655 static int gfx_v10_0_rlc_backdoor_autoload_config_mec_cache(struct amdgpu_device *adev)
5656 {
5657         uint32_t usec_timeout = 50000;  /* wait for 50ms */
5658         uint32_t tmp;
5659         int i;
5660         uint64_t addr;
5661
5662         /* Trigger an invalidation of the L1 instruction caches */
5663         tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL);
5664         tmp = REG_SET_FIELD(tmp, CP_CPC_IC_OP_CNTL, INVALIDATE_CACHE, 1);
5665         WREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL, tmp);
5666
5667         /* Wait for invalidation complete */
5668         for (i = 0; i < usec_timeout; i++) {
5669                 tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL);
5670                 if (1 == REG_GET_FIELD(tmp, CP_CPC_IC_OP_CNTL,
5671                         INVALIDATE_CACHE_COMPLETE))
5672                         break;
5673                 udelay(1);
5674         }
5675
5676         if (i >= usec_timeout) {
5677                 dev_err(adev->dev, "failed to invalidate instruction cache\n");
5678                 return -EINVAL;
5679         }
5680
5681         /* Program mec1 ucode address into intruction cache address register */
5682         addr = adev->gfx.rlc.rlc_autoload_gpu_addr +
5683                 rlc_autoload_info[FIRMWARE_ID_CP_MEC].offset;
5684         WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_LO,
5685                         lower_32_bits(addr) & 0xFFFFF000);
5686         WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_HI,
5687                         upper_32_bits(addr));
5688
5689         return 0;
5690 }
5691
5692 static int gfx_v10_0_wait_for_rlc_autoload_complete(struct amdgpu_device *adev)
5693 {
5694         uint32_t cp_status;
5695         uint32_t bootload_status;
5696         int i, r;
5697
5698         for (i = 0; i < adev->usec_timeout; i++) {
5699                 cp_status = RREG32_SOC15(GC, 0, mmCP_STAT);
5700                 bootload_status = RREG32_SOC15(GC, 0, mmRLC_RLCS_BOOTLOAD_STATUS);
5701                 if ((cp_status == 0) &&
5702                     (REG_GET_FIELD(bootload_status,
5703                         RLC_RLCS_BOOTLOAD_STATUS, BOOTLOAD_COMPLETE) == 1)) {
5704                         break;
5705                 }
5706                 udelay(1);
5707         }
5708
5709         if (i >= adev->usec_timeout) {
5710                 dev_err(adev->dev, "rlc autoload: gc ucode autoload timeout\n");
5711                 return -ETIMEDOUT;
5712         }
5713
5714         if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) {
5715                 r = gfx_v10_0_rlc_backdoor_autoload_config_me_cache(adev);
5716                 if (r)
5717                         return r;
5718
5719                 r = gfx_v10_0_rlc_backdoor_autoload_config_ce_cache(adev);
5720                 if (r)
5721                         return r;
5722
5723                 r = gfx_v10_0_rlc_backdoor_autoload_config_pfp_cache(adev);
5724                 if (r)
5725                         return r;
5726
5727                 r = gfx_v10_0_rlc_backdoor_autoload_config_mec_cache(adev);
5728                 if (r)
5729                         return r;
5730         }
5731
5732         return 0;
5733 }
5734
5735 static int gfx_v10_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable)
5736 {
5737         int i;
5738         u32 tmp = RREG32_SOC15(GC, 0, mmCP_ME_CNTL);
5739
5740         tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, enable ? 0 : 1);
5741         tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, enable ? 0 : 1);
5742         tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_HALT, enable ? 0 : 1);
5743
5744         if (adev->asic_type == CHIP_NAVI12) {
5745                 WREG32_SOC15_RLC(GC, 0, mmCP_ME_CNTL, tmp);
5746         } else {
5747                 WREG32_SOC15(GC, 0, mmCP_ME_CNTL, tmp);
5748         }
5749
5750         for (i = 0; i < adev->usec_timeout; i++) {
5751                 if (RREG32_SOC15(GC, 0, mmCP_STAT) == 0)
5752                         break;
5753                 udelay(1);
5754         }
5755
5756         if (i >= adev->usec_timeout)
5757                 DRM_ERROR("failed to %s cp gfx\n", enable ? "unhalt" : "halt");
5758
5759         return 0;
5760 }
5761
5762 static int gfx_v10_0_cp_gfx_load_pfp_microcode(struct amdgpu_device *adev)
5763 {
5764         int r;
5765         const struct gfx_firmware_header_v1_0 *pfp_hdr;
5766         const __le32 *fw_data;
5767         unsigned i, fw_size;
5768         uint32_t tmp;
5769         uint32_t usec_timeout = 50000;  /* wait for 50ms */
5770
5771         pfp_hdr = (const struct gfx_firmware_header_v1_0 *)
5772                 adev->gfx.pfp_fw->data;
5773
5774         amdgpu_ucode_print_gfx_hdr(&pfp_hdr->header);
5775
5776         fw_data = (const __le32 *)(adev->gfx.pfp_fw->data +
5777                 le32_to_cpu(pfp_hdr->header.ucode_array_offset_bytes));
5778         fw_size = le32_to_cpu(pfp_hdr->header.ucode_size_bytes);
5779
5780         r = amdgpu_bo_create_reserved(adev, pfp_hdr->header.ucode_size_bytes,
5781                                       PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,
5782                                       &adev->gfx.pfp.pfp_fw_obj,
5783                                       &adev->gfx.pfp.pfp_fw_gpu_addr,
5784                                       (void **)&adev->gfx.pfp.pfp_fw_ptr);
5785         if (r) {
5786                 dev_err(adev->dev, "(%d) failed to create pfp fw bo\n", r);
5787                 gfx_v10_0_pfp_fini(adev);
5788                 return r;
5789         }
5790
5791         memcpy(adev->gfx.pfp.pfp_fw_ptr, fw_data, fw_size);
5792
5793         amdgpu_bo_kunmap(adev->gfx.pfp.pfp_fw_obj);
5794         amdgpu_bo_unreserve(adev->gfx.pfp.pfp_fw_obj);
5795
5796         /* Trigger an invalidation of the L1 instruction caches */
5797         tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL);
5798         tmp = REG_SET_FIELD(tmp, CP_PFP_IC_OP_CNTL, INVALIDATE_CACHE, 1);
5799         WREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL, tmp);
5800
5801         /* Wait for invalidation complete */
5802         for (i = 0; i < usec_timeout; i++) {
5803                 tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL);
5804                 if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL,
5805                         INVALIDATE_CACHE_COMPLETE))
5806                         break;
5807                 udelay(1);
5808         }
5809
5810         if (i >= usec_timeout) {
5811                 dev_err(adev->dev, "failed to invalidate instruction cache\n");
5812                 return -EINVAL;
5813         }
5814
5815         if (amdgpu_emu_mode == 1)
5816                 adev->hdp.funcs->flush_hdp(adev, NULL);
5817
5818         tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_CNTL);
5819         tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, VMID, 0);
5820         tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, CACHE_POLICY, 0);
5821         tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, EXE_DISABLE, 0);
5822         tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, ADDRESS_CLAMP, 1);
5823         WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_CNTL, tmp);
5824         WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_LO,
5825                 adev->gfx.pfp.pfp_fw_gpu_addr & 0xFFFFF000);
5826         WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_HI,
5827                 upper_32_bits(adev->gfx.pfp.pfp_fw_gpu_addr));
5828
5829         WREG32_SOC15(GC, 0, mmCP_HYP_PFP_UCODE_ADDR, 0);
5830
5831         for (i = 0; i < pfp_hdr->jt_size; i++)
5832                 WREG32_SOC15(GC, 0, mmCP_HYP_PFP_UCODE_DATA,
5833                              le32_to_cpup(fw_data + pfp_hdr->jt_offset + i));
5834
5835         WREG32_SOC15(GC, 0, mmCP_HYP_PFP_UCODE_ADDR, adev->gfx.pfp_fw_version);
5836
5837         return 0;
5838 }
5839
5840 static int gfx_v10_0_cp_gfx_load_ce_microcode(struct amdgpu_device *adev)
5841 {
5842         int r;
5843         const struct gfx_firmware_header_v1_0 *ce_hdr;
5844         const __le32 *fw_data;
5845         unsigned i, fw_size;
5846         uint32_t tmp;
5847         uint32_t usec_timeout = 50000;  /* wait for 50ms */
5848
5849         ce_hdr = (const struct gfx_firmware_header_v1_0 *)
5850                 adev->gfx.ce_fw->data;
5851
5852         amdgpu_ucode_print_gfx_hdr(&ce_hdr->header);
5853
5854         fw_data = (const __le32 *)(adev->gfx.ce_fw->data +
5855                 le32_to_cpu(ce_hdr->header.ucode_array_offset_bytes));
5856         fw_size = le32_to_cpu(ce_hdr->header.ucode_size_bytes);
5857
5858         r = amdgpu_bo_create_reserved(adev, ce_hdr->header.ucode_size_bytes,
5859                                       PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,
5860                                       &adev->gfx.ce.ce_fw_obj,
5861                                       &adev->gfx.ce.ce_fw_gpu_addr,
5862                                       (void **)&adev->gfx.ce.ce_fw_ptr);
5863         if (r) {
5864                 dev_err(adev->dev, "(%d) failed to create ce fw bo\n", r);
5865                 gfx_v10_0_ce_fini(adev);
5866                 return r;
5867         }
5868
5869         memcpy(adev->gfx.ce.ce_fw_ptr, fw_data, fw_size);
5870
5871         amdgpu_bo_kunmap(adev->gfx.ce.ce_fw_obj);
5872         amdgpu_bo_unreserve(adev->gfx.ce.ce_fw_obj);
5873
5874         /* Trigger an invalidation of the L1 instruction caches */
5875         tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL);
5876         tmp = REG_SET_FIELD(tmp, CP_CE_IC_OP_CNTL, INVALIDATE_CACHE, 1);
5877         WREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL, tmp);
5878
5879         /* Wait for invalidation complete */
5880         for (i = 0; i < usec_timeout; i++) {
5881                 tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL);
5882                 if (1 == REG_GET_FIELD(tmp, CP_CE_IC_OP_CNTL,
5883                         INVALIDATE_CACHE_COMPLETE))
5884                         break;
5885                 udelay(1);
5886         }
5887
5888         if (i >= usec_timeout) {
5889                 dev_err(adev->dev, "failed to invalidate instruction cache\n");
5890                 return -EINVAL;
5891         }
5892
5893         if (amdgpu_emu_mode == 1)
5894                 adev->hdp.funcs->flush_hdp(adev, NULL);
5895
5896         tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_CNTL);
5897         tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, VMID, 0);
5898         tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, CACHE_POLICY, 0);
5899         tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, EXE_DISABLE, 0);
5900         tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, ADDRESS_CLAMP, 1);
5901         WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_LO,
5902                 adev->gfx.ce.ce_fw_gpu_addr & 0xFFFFF000);
5903         WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_HI,
5904                 upper_32_bits(adev->gfx.ce.ce_fw_gpu_addr));
5905
5906         WREG32_SOC15(GC, 0, mmCP_HYP_CE_UCODE_ADDR, 0);
5907
5908         for (i = 0; i < ce_hdr->jt_size; i++)
5909                 WREG32_SOC15(GC, 0, mmCP_HYP_CE_UCODE_DATA,
5910                              le32_to_cpup(fw_data + ce_hdr->jt_offset + i));
5911
5912         WREG32_SOC15(GC, 0, mmCP_HYP_CE_UCODE_ADDR, adev->gfx.ce_fw_version);
5913
5914         return 0;
5915 }
5916
5917 static int gfx_v10_0_cp_gfx_load_me_microcode(struct amdgpu_device *adev)
5918 {
5919         int r;
5920         const struct gfx_firmware_header_v1_0 *me_hdr;
5921         const __le32 *fw_data;
5922         unsigned i, fw_size;
5923         uint32_t tmp;
5924         uint32_t usec_timeout = 50000;  /* wait for 50ms */
5925
5926         me_hdr = (const struct gfx_firmware_header_v1_0 *)
5927                 adev->gfx.me_fw->data;
5928
5929         amdgpu_ucode_print_gfx_hdr(&me_hdr->header);
5930
5931         fw_data = (const __le32 *)(adev->gfx.me_fw->data +
5932                 le32_to_cpu(me_hdr->header.ucode_array_offset_bytes));
5933         fw_size = le32_to_cpu(me_hdr->header.ucode_size_bytes);
5934
5935         r = amdgpu_bo_create_reserved(adev, me_hdr->header.ucode_size_bytes,
5936                                       PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,
5937                                       &adev->gfx.me.me_fw_obj,
5938                                       &adev->gfx.me.me_fw_gpu_addr,
5939                                       (void **)&adev->gfx.me.me_fw_ptr);
5940         if (r) {
5941                 dev_err(adev->dev, "(%d) failed to create me fw bo\n", r);
5942                 gfx_v10_0_me_fini(adev);
5943                 return r;
5944         }
5945
5946         memcpy(adev->gfx.me.me_fw_ptr, fw_data, fw_size);
5947
5948         amdgpu_bo_kunmap(adev->gfx.me.me_fw_obj);
5949         amdgpu_bo_unreserve(adev->gfx.me.me_fw_obj);
5950
5951         /* Trigger an invalidation of the L1 instruction caches */
5952         tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL);
5953         tmp = REG_SET_FIELD(tmp, CP_ME_IC_OP_CNTL, INVALIDATE_CACHE, 1);
5954         WREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL, tmp);
5955
5956         /* Wait for invalidation complete */
5957         for (i = 0; i < usec_timeout; i++) {
5958                 tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL);
5959                 if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL,
5960                         INVALIDATE_CACHE_COMPLETE))
5961                         break;
5962                 udelay(1);
5963         }
5964
5965         if (i >= usec_timeout) {
5966                 dev_err(adev->dev, "failed to invalidate instruction cache\n");
5967                 return -EINVAL;
5968         }
5969
5970         if (amdgpu_emu_mode == 1)
5971                 adev->hdp.funcs->flush_hdp(adev, NULL);
5972
5973         tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_CNTL);
5974         tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, VMID, 0);
5975         tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, CACHE_POLICY, 0);
5976         tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, EXE_DISABLE, 0);
5977         tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, ADDRESS_CLAMP, 1);
5978         WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_LO,
5979                 adev->gfx.me.me_fw_gpu_addr & 0xFFFFF000);
5980         WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_HI,
5981                 upper_32_bits(adev->gfx.me.me_fw_gpu_addr));
5982
5983         WREG32_SOC15(GC, 0, mmCP_HYP_ME_UCODE_ADDR, 0);
5984
5985         for (i = 0; i < me_hdr->jt_size; i++)
5986                 WREG32_SOC15(GC, 0, mmCP_HYP_ME_UCODE_DATA,
5987                              le32_to_cpup(fw_data + me_hdr->jt_offset + i));
5988
5989         WREG32_SOC15(GC, 0, mmCP_HYP_ME_UCODE_ADDR, adev->gfx.me_fw_version);
5990
5991         return 0;
5992 }
5993
5994 static int gfx_v10_0_cp_gfx_load_microcode(struct amdgpu_device *adev)
5995 {
5996         int r;
5997
5998         if (!adev->gfx.me_fw || !adev->gfx.pfp_fw || !adev->gfx.ce_fw)
5999                 return -EINVAL;
6000
6001         gfx_v10_0_cp_gfx_enable(adev, false);
6002
6003         r = gfx_v10_0_cp_gfx_load_pfp_microcode(adev);
6004         if (r) {
6005                 dev_err(adev->dev, "(%d) failed to load pfp fw\n", r);
6006                 return r;
6007         }
6008
6009         r = gfx_v10_0_cp_gfx_load_ce_microcode(adev);
6010         if (r) {
6011                 dev_err(adev->dev, "(%d) failed to load ce fw\n", r);
6012                 return r;
6013         }
6014
6015         r = gfx_v10_0_cp_gfx_load_me_microcode(adev);
6016         if (r) {
6017                 dev_err(adev->dev, "(%d) failed to load me fw\n", r);
6018                 return r;
6019         }
6020
6021         return 0;
6022 }
6023
6024 static int gfx_v10_0_cp_gfx_start(struct amdgpu_device *adev)
6025 {
6026         struct amdgpu_ring *ring;
6027         const struct cs_section_def *sect = NULL;
6028         const struct cs_extent_def *ext = NULL;
6029         int r, i;
6030         int ctx_reg_offset;
6031
6032         /* init the CP */
6033         WREG32_SOC15(GC, 0, mmCP_MAX_CONTEXT,
6034                      adev->gfx.config.max_hw_contexts - 1);
6035         WREG32_SOC15(GC, 0, mmCP_DEVICE_ID, 1);
6036
6037         gfx_v10_0_cp_gfx_enable(adev, true);
6038
6039         ring = &adev->gfx.gfx_ring[0];
6040         r = amdgpu_ring_alloc(ring, gfx_v10_0_get_csb_size(adev) + 4);
6041         if (r) {
6042                 DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r);
6043                 return r;
6044         }
6045
6046         amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
6047         amdgpu_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
6048
6049         amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1));
6050         amdgpu_ring_write(ring, 0x80000000);
6051         amdgpu_ring_write(ring, 0x80000000);
6052
6053         for (sect = gfx10_cs_data; sect->section != NULL; ++sect) {
6054                 for (ext = sect->section; ext->extent != NULL; ++ext) {
6055                         if (sect->id == SECT_CONTEXT) {
6056                                 amdgpu_ring_write(ring,
6057                                                   PACKET3(PACKET3_SET_CONTEXT_REG,
6058                                                           ext->reg_count));
6059                                 amdgpu_ring_write(ring, ext->reg_index -
6060                                                   PACKET3_SET_CONTEXT_REG_START);
6061                                 for (i = 0; i < ext->reg_count; i++)
6062                                         amdgpu_ring_write(ring, ext->extent[i]);
6063                         }
6064                 }
6065         }
6066
6067         ctx_reg_offset =
6068                 SOC15_REG_OFFSET(GC, 0, mmPA_SC_TILE_STEERING_OVERRIDE) - PACKET3_SET_CONTEXT_REG_START;
6069         amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
6070         amdgpu_ring_write(ring, ctx_reg_offset);
6071         amdgpu_ring_write(ring, adev->gfx.config.pa_sc_tile_steering_override);
6072
6073         amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
6074         amdgpu_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE);
6075
6076         amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));
6077         amdgpu_ring_write(ring, 0);
6078
6079         amdgpu_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2));
6080         amdgpu_ring_write(ring, PACKET3_BASE_INDEX(CE_PARTITION_BASE));
6081         amdgpu_ring_write(ring, 0x8000);
6082         amdgpu_ring_write(ring, 0x8000);
6083
6084         amdgpu_ring_commit(ring);
6085
6086         /* submit cs packet to copy state 0 to next available state */
6087         if (adev->gfx.num_gfx_rings > 1) {
6088                 /* maximum supported gfx ring is 2 */
6089                 ring = &adev->gfx.gfx_ring[1];
6090                 r = amdgpu_ring_alloc(ring, 2);
6091                 if (r) {
6092                         DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r);
6093                         return r;
6094                 }
6095
6096                 amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));
6097                 amdgpu_ring_write(ring, 0);
6098
6099                 amdgpu_ring_commit(ring);
6100         }
6101         return 0;
6102 }
6103
6104 static void gfx_v10_0_cp_gfx_switch_pipe(struct amdgpu_device *adev,
6105                                          CP_PIPE_ID pipe)
6106 {
6107         u32 tmp;
6108
6109         tmp = RREG32_SOC15(GC, 0, mmGRBM_GFX_CNTL);
6110         tmp = REG_SET_FIELD(tmp, GRBM_GFX_CNTL, PIPEID, pipe);
6111
6112         WREG32_SOC15(GC, 0, mmGRBM_GFX_CNTL, tmp);
6113 }
6114
6115 static void gfx_v10_0_cp_gfx_set_doorbell(struct amdgpu_device *adev,
6116                                           struct amdgpu_ring *ring)
6117 {
6118         u32 tmp;
6119
6120         if (!amdgpu_async_gfx_ring) {
6121                 tmp = RREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL);
6122                 if (ring->use_doorbell) {
6123                         tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
6124                                                 DOORBELL_OFFSET, ring->doorbell_index);
6125                         tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
6126                                                 DOORBELL_EN, 1);
6127                 } else {
6128                         tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
6129                                                 DOORBELL_EN, 0);
6130                 }
6131                 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL, tmp);
6132         }
6133         switch (adev->asic_type) {
6134         case CHIP_SIENNA_CICHLID:
6135         case CHIP_NAVY_FLOUNDER:
6136         case CHIP_VANGOGH:
6137         case CHIP_DIMGREY_CAVEFISH:
6138                 tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER,
6139                                     DOORBELL_RANGE_LOWER_Sienna_Cichlid, ring->doorbell_index);
6140                 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_LOWER, tmp);
6141
6142                 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_UPPER,
6143                              CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_Sienna_Cichlid_MASK);
6144                 break;
6145         default:
6146                 tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER,
6147                                     DOORBELL_RANGE_LOWER, ring->doorbell_index);
6148                 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_LOWER, tmp);
6149
6150                 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_UPPER,
6151                              CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_MASK);
6152                 break;
6153         }
6154 }
6155
6156 static int gfx_v10_0_cp_gfx_resume(struct amdgpu_device *adev)
6157 {
6158         struct amdgpu_ring *ring;
6159         u32 tmp;
6160         u32 rb_bufsz;
6161         u64 rb_addr, rptr_addr, wptr_gpu_addr;
6162         u32 i;
6163
6164         /* Set the write pointer delay */
6165         WREG32_SOC15(GC, 0, mmCP_RB_WPTR_DELAY, 0);
6166
6167         /* set the RB to use vmid 0 */
6168         WREG32_SOC15(GC, 0, mmCP_RB_VMID, 0);
6169
6170         /* Init gfx ring 0 for pipe 0 */
6171         mutex_lock(&adev->srbm_mutex);
6172         gfx_v10_0_cp_gfx_switch_pipe(adev, PIPE_ID0);
6173
6174         /* Set ring buffer size */
6175         ring = &adev->gfx.gfx_ring[0];
6176         rb_bufsz = order_base_2(ring->ring_size / 8);
6177         tmp = REG_SET_FIELD(0, CP_RB0_CNTL, RB_BUFSZ, rb_bufsz);
6178         tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, RB_BLKSZ, rb_bufsz - 2);
6179 #ifdef __BIG_ENDIAN
6180         tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, BUF_SWAP, 1);
6181 #endif
6182         WREG32_SOC15(GC, 0, mmCP_RB0_CNTL, tmp);
6183
6184         /* Initialize the ring buffer's write pointers */
6185         ring->wptr = 0;
6186         WREG32_SOC15(GC, 0, mmCP_RB0_WPTR, lower_32_bits(ring->wptr));
6187         WREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI, upper_32_bits(ring->wptr));
6188
6189         /* set the wb address wether it's enabled or not */
6190         rptr_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
6191         WREG32_SOC15(GC, 0, mmCP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr));
6192         WREG32_SOC15(GC, 0, mmCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) &
6193                      CP_RB_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK);
6194
6195         wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
6196         WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_LO,
6197                      lower_32_bits(wptr_gpu_addr));
6198         WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI,
6199                      upper_32_bits(wptr_gpu_addr));
6200
6201         mdelay(1);
6202         WREG32_SOC15(GC, 0, mmCP_RB0_CNTL, tmp);
6203
6204         rb_addr = ring->gpu_addr >> 8;
6205         WREG32_SOC15(GC, 0, mmCP_RB0_BASE, rb_addr);
6206         WREG32_SOC15(GC, 0, mmCP_RB0_BASE_HI, upper_32_bits(rb_addr));
6207
6208         WREG32_SOC15(GC, 0, mmCP_RB_ACTIVE, 1);
6209
6210         gfx_v10_0_cp_gfx_set_doorbell(adev, ring);
6211         mutex_unlock(&adev->srbm_mutex);
6212
6213         /* Init gfx ring 1 for pipe 1 */
6214         if (adev->gfx.num_gfx_rings > 1) {
6215                 mutex_lock(&adev->srbm_mutex);
6216                 gfx_v10_0_cp_gfx_switch_pipe(adev, PIPE_ID1);
6217                 /* maximum supported gfx ring is 2 */
6218                 ring = &adev->gfx.gfx_ring[1];
6219                 rb_bufsz = order_base_2(ring->ring_size / 8);
6220                 tmp = REG_SET_FIELD(0, CP_RB1_CNTL, RB_BUFSZ, rb_bufsz);
6221                 tmp = REG_SET_FIELD(tmp, CP_RB1_CNTL, RB_BLKSZ, rb_bufsz - 2);
6222                 WREG32_SOC15(GC, 0, mmCP_RB1_CNTL, tmp);
6223                 /* Initialize the ring buffer's write pointers */
6224                 ring->wptr = 0;
6225                 WREG32_SOC15(GC, 0, mmCP_RB1_WPTR, lower_32_bits(ring->wptr));
6226                 WREG32_SOC15(GC, 0, mmCP_RB1_WPTR_HI, upper_32_bits(ring->wptr));
6227                 /* Set the wb address wether it's enabled or not */
6228                 rptr_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
6229                 WREG32_SOC15(GC, 0, mmCP_RB1_RPTR_ADDR, lower_32_bits(rptr_addr));
6230                 WREG32_SOC15(GC, 0, mmCP_RB1_RPTR_ADDR_HI, upper_32_bits(rptr_addr) &
6231                              CP_RB1_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK);
6232                 wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
6233                 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_LO,
6234                              lower_32_bits(wptr_gpu_addr));
6235                 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI,
6236                              upper_32_bits(wptr_gpu_addr));
6237
6238                 mdelay(1);
6239                 WREG32_SOC15(GC, 0, mmCP_RB1_CNTL, tmp);
6240
6241                 rb_addr = ring->gpu_addr >> 8;
6242                 WREG32_SOC15(GC, 0, mmCP_RB1_BASE, rb_addr);
6243                 WREG32_SOC15(GC, 0, mmCP_RB1_BASE_HI, upper_32_bits(rb_addr));
6244                 WREG32_SOC15(GC, 0, mmCP_RB1_ACTIVE, 1);
6245
6246                 gfx_v10_0_cp_gfx_set_doorbell(adev, ring);
6247                 mutex_unlock(&adev->srbm_mutex);
6248         }
6249         /* Switch to pipe 0 */
6250         mutex_lock(&adev->srbm_mutex);
6251         gfx_v10_0_cp_gfx_switch_pipe(adev, PIPE_ID0);
6252         mutex_unlock(&adev->srbm_mutex);
6253
6254         /* start the ring */
6255         gfx_v10_0_cp_gfx_start(adev);
6256
6257         for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
6258                 ring = &adev->gfx.gfx_ring[i];
6259                 ring->sched.ready = true;
6260         }
6261
6262         return 0;
6263 }
6264
6265 static void gfx_v10_0_cp_compute_enable(struct amdgpu_device *adev, bool enable)
6266 {
6267         if (enable) {
6268                 switch (adev->asic_type) {
6269                 case CHIP_SIENNA_CICHLID:
6270                 case CHIP_NAVY_FLOUNDER:
6271                 case CHIP_VANGOGH:
6272                 case CHIP_DIMGREY_CAVEFISH:
6273                         WREG32_SOC15(GC, 0, mmCP_MEC_CNTL_Sienna_Cichlid, 0);
6274                         break;
6275                 default:
6276                         WREG32_SOC15(GC, 0, mmCP_MEC_CNTL, 0);
6277                         break;
6278                 }
6279         } else {
6280                 switch (adev->asic_type) {
6281                 case CHIP_SIENNA_CICHLID:
6282                 case CHIP_NAVY_FLOUNDER:
6283                 case CHIP_VANGOGH:
6284                 case CHIP_DIMGREY_CAVEFISH:
6285                         WREG32_SOC15(GC, 0, mmCP_MEC_CNTL_Sienna_Cichlid,
6286                                      (CP_MEC_CNTL__MEC_ME1_HALT_MASK |
6287                                       CP_MEC_CNTL__MEC_ME2_HALT_MASK));
6288                         break;
6289                 default:
6290                         WREG32_SOC15(GC, 0, mmCP_MEC_CNTL,
6291                                      (CP_MEC_CNTL__MEC_ME1_HALT_MASK |
6292                                       CP_MEC_CNTL__MEC_ME2_HALT_MASK));
6293                         break;
6294                 }
6295                 adev->gfx.kiq.ring.sched.ready = false;
6296         }
6297         udelay(50);
6298 }
6299
6300 static int gfx_v10_0_cp_compute_load_microcode(struct amdgpu_device *adev)
6301 {
6302         const struct gfx_firmware_header_v1_0 *mec_hdr;
6303         const __le32 *fw_data;
6304         unsigned i;
6305         u32 tmp;
6306         u32 usec_timeout = 50000; /* Wait for 50 ms */
6307
6308         if (!adev->gfx.mec_fw)
6309                 return -EINVAL;
6310
6311         gfx_v10_0_cp_compute_enable(adev, false);
6312
6313         mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
6314         amdgpu_ucode_print_gfx_hdr(&mec_hdr->header);
6315
6316         fw_data = (const __le32 *)
6317                 (adev->gfx.mec_fw->data +
6318                  le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes));
6319
6320         /* Trigger an invalidation of the L1 instruction caches */
6321         tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL);
6322         tmp = REG_SET_FIELD(tmp, CP_CPC_IC_OP_CNTL, INVALIDATE_CACHE, 1);
6323         WREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL, tmp);
6324
6325         /* Wait for invalidation complete */
6326         for (i = 0; i < usec_timeout; i++) {
6327                 tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL);
6328                 if (1 == REG_GET_FIELD(tmp, CP_CPC_IC_OP_CNTL,
6329                                        INVALIDATE_CACHE_COMPLETE))
6330                         break;
6331                 udelay(1);
6332         }
6333
6334         if (i >= usec_timeout) {
6335                 dev_err(adev->dev, "failed to invalidate instruction cache\n");
6336                 return -EINVAL;
6337         }
6338
6339         if (amdgpu_emu_mode == 1)
6340                 adev->hdp.funcs->flush_hdp(adev, NULL);
6341
6342         tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_CNTL);
6343         tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0);
6344         tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, EXE_DISABLE, 0);
6345         tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, ADDRESS_CLAMP, 1);
6346         WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_CNTL, tmp);
6347
6348         WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_LO, adev->gfx.mec.mec_fw_gpu_addr &
6349                      0xFFFFF000);
6350         WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_HI,
6351                      upper_32_bits(adev->gfx.mec.mec_fw_gpu_addr));
6352
6353         /* MEC1 */
6354         WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_ADDR, 0);
6355
6356         for (i = 0; i < mec_hdr->jt_size; i++)
6357                 WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_DATA,
6358                              le32_to_cpup(fw_data + mec_hdr->jt_offset + i));
6359
6360         WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_ADDR, adev->gfx.mec_fw_version);
6361
6362         /*
6363          * TODO: Loading MEC2 firmware is only necessary if MEC2 should run
6364          * different microcode than MEC1.
6365          */
6366
6367         return 0;
6368 }
6369
6370 static void gfx_v10_0_kiq_setting(struct amdgpu_ring *ring)
6371 {
6372         uint32_t tmp;
6373         struct amdgpu_device *adev = ring->adev;
6374
6375         /* tell RLC which is KIQ queue */
6376         switch (adev->asic_type) {
6377         case CHIP_SIENNA_CICHLID:
6378         case CHIP_NAVY_FLOUNDER:
6379         case CHIP_VANGOGH:
6380         case CHIP_DIMGREY_CAVEFISH:
6381                 tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS_Sienna_Cichlid);
6382                 tmp &= 0xffffff00;
6383                 tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue);
6384                 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS_Sienna_Cichlid, tmp);
6385                 tmp |= 0x80;
6386                 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS_Sienna_Cichlid, tmp);
6387                 break;
6388         default:
6389                 tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS);
6390                 tmp &= 0xffffff00;
6391                 tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue);
6392                 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS, tmp);
6393                 tmp |= 0x80;
6394                 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS, tmp);
6395                 break;
6396         }
6397 }
6398
6399 static int gfx_v10_0_gfx_mqd_init(struct amdgpu_ring *ring)
6400 {
6401         struct amdgpu_device *adev = ring->adev;
6402         struct v10_gfx_mqd *mqd = ring->mqd_ptr;
6403         uint64_t hqd_gpu_addr, wb_gpu_addr;
6404         uint32_t tmp;
6405         uint32_t rb_bufsz;
6406
6407         /* set up gfx hqd wptr */
6408         mqd->cp_gfx_hqd_wptr = 0;
6409         mqd->cp_gfx_hqd_wptr_hi = 0;
6410
6411         /* set the pointer to the MQD */
6412         mqd->cp_mqd_base_addr = ring->mqd_gpu_addr & 0xfffffffc;
6413         mqd->cp_mqd_base_addr_hi = upper_32_bits(ring->mqd_gpu_addr);
6414
6415         /* set up mqd control */
6416         tmp = RREG32_SOC15(GC, 0, mmCP_GFX_MQD_CONTROL);
6417         tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, VMID, 0);
6418         tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, PRIV_STATE, 1);
6419         tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, CACHE_POLICY, 0);
6420         mqd->cp_gfx_mqd_control = tmp;
6421
6422         /* set up gfx_hqd_vimd with 0x0 to indicate the ring buffer's vmid */
6423         tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_VMID);
6424         tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_VMID, VMID, 0);
6425         mqd->cp_gfx_hqd_vmid = 0;
6426
6427         /* set up default queue priority level
6428          * 0x0 = low priority, 0x1 = high priority */
6429         tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_QUEUE_PRIORITY);
6430         tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_QUEUE_PRIORITY, PRIORITY_LEVEL, 0);
6431         mqd->cp_gfx_hqd_queue_priority = tmp;
6432
6433         /* set up time quantum */
6434         tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_QUANTUM);
6435         tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_QUANTUM, QUANTUM_EN, 1);
6436         mqd->cp_gfx_hqd_quantum = tmp;
6437
6438         /* set up gfx hqd base. this is similar as CP_RB_BASE */
6439         hqd_gpu_addr = ring->gpu_addr >> 8;
6440         mqd->cp_gfx_hqd_base = hqd_gpu_addr;
6441         mqd->cp_gfx_hqd_base_hi = upper_32_bits(hqd_gpu_addr);
6442
6443         /* set up hqd_rptr_addr/_hi, similar as CP_RB_RPTR */
6444         wb_gpu_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
6445         mqd->cp_gfx_hqd_rptr_addr = wb_gpu_addr & 0xfffffffc;
6446         mqd->cp_gfx_hqd_rptr_addr_hi =
6447                 upper_32_bits(wb_gpu_addr) & 0xffff;
6448
6449         /* set up rb_wptr_poll addr */
6450         wb_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
6451         mqd->cp_rb_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc;
6452         mqd->cp_rb_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff;
6453
6454         /* set up the gfx_hqd_control, similar as CP_RB0_CNTL */
6455         rb_bufsz = order_base_2(ring->ring_size / 4) - 1;
6456         tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_CNTL);
6457         tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_BUFSZ, rb_bufsz);
6458         tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_BLKSZ, rb_bufsz - 2);
6459 #ifdef __BIG_ENDIAN
6460         tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, BUF_SWAP, 1);
6461 #endif
6462         mqd->cp_gfx_hqd_cntl = tmp;
6463
6464         /* set up cp_doorbell_control */
6465         tmp = RREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL);
6466         if (ring->use_doorbell) {
6467                 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
6468                                     DOORBELL_OFFSET, ring->doorbell_index);
6469                 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
6470                                     DOORBELL_EN, 1);
6471         } else
6472                 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
6473                                     DOORBELL_EN, 0);
6474         mqd->cp_rb_doorbell_control = tmp;
6475
6476         /*if there are 2 gfx rings, set the lower doorbell range of the first ring,
6477          *otherwise the range of the second ring will override the first ring */
6478         if (ring->doorbell_index == adev->doorbell_index.gfx_ring0 << 1)
6479                 gfx_v10_0_cp_gfx_set_doorbell(adev, ring);
6480
6481         /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */
6482         ring->wptr = 0;
6483         mqd->cp_gfx_hqd_rptr = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_RPTR);
6484
6485         /* active the queue */
6486         mqd->cp_gfx_hqd_active = 1;
6487
6488         return 0;
6489 }
6490
6491 #ifdef BRING_UP_DEBUG
6492 static int gfx_v10_0_gfx_queue_init_register(struct amdgpu_ring *ring)
6493 {
6494         struct amdgpu_device *adev = ring->adev;
6495         struct v10_gfx_mqd *mqd = ring->mqd_ptr;
6496
6497         /* set mmCP_GFX_HQD_WPTR/_HI to 0 */
6498         WREG32_SOC15(GC, 0, mmCP_GFX_HQD_WPTR, mqd->cp_gfx_hqd_wptr);
6499         WREG32_SOC15(GC, 0, mmCP_GFX_HQD_WPTR_HI, mqd->cp_gfx_hqd_wptr_hi);
6500
6501         /* set GFX_MQD_BASE */
6502         WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR, mqd->cp_mqd_base_addr);
6503         WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR_HI, mqd->cp_mqd_base_addr_hi);
6504
6505         /* set GFX_MQD_CONTROL */
6506         WREG32_SOC15(GC, 0, mmCP_GFX_MQD_CONTROL, mqd->cp_gfx_mqd_control);
6507
6508         /* set GFX_HQD_VMID to 0 */
6509         WREG32_SOC15(GC, 0, mmCP_GFX_HQD_VMID, mqd->cp_gfx_hqd_vmid);
6510
6511         WREG32_SOC15(GC, 0, mmCP_GFX_HQD_QUEUE_PRIORITY,
6512                         mqd->cp_gfx_hqd_queue_priority);
6513         WREG32_SOC15(GC, 0, mmCP_GFX_HQD_QUANTUM, mqd->cp_gfx_hqd_quantum);
6514
6515         /* set GFX_HQD_BASE, similar as CP_RB_BASE */
6516         WREG32_SOC15(GC, 0, mmCP_GFX_HQD_BASE, mqd->cp_gfx_hqd_base);
6517         WREG32_SOC15(GC, 0, mmCP_GFX_HQD_BASE_HI, mqd->cp_gfx_hqd_base_hi);
6518
6519         /* set GFX_HQD_RPTR_ADDR, similar as CP_RB_RPTR */
6520         WREG32_SOC15(GC, 0, mmCP_GFX_HQD_RPTR_ADDR, mqd->cp_gfx_hqd_rptr_addr);
6521         WREG32_SOC15(GC, 0, mmCP_GFX_HQD_RPTR_ADDR_HI, mqd->cp_gfx_hqd_rptr_addr_hi);
6522
6523         /* set GFX_HQD_CNTL, similar as CP_RB_CNTL */
6524         WREG32_SOC15(GC, 0, mmCP_GFX_HQD_CNTL, mqd->cp_gfx_hqd_cntl);
6525
6526         /* set RB_WPTR_POLL_ADDR */
6527         WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_LO, mqd->cp_rb_wptr_poll_addr_lo);
6528         WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI, mqd->cp_rb_wptr_poll_addr_hi);
6529
6530         /* set RB_DOORBELL_CONTROL */
6531         WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL, mqd->cp_rb_doorbell_control);
6532
6533         /* active the queue */
6534         WREG32_SOC15(GC, 0, mmCP_GFX_HQD_ACTIVE, mqd->cp_gfx_hqd_active);
6535
6536         return 0;
6537 }
6538 #endif
6539
6540 static int gfx_v10_0_gfx_init_queue(struct amdgpu_ring *ring)
6541 {
6542         struct amdgpu_device *adev = ring->adev;
6543         struct v10_gfx_mqd *mqd = ring->mqd_ptr;
6544         int mqd_idx = ring - &adev->gfx.gfx_ring[0];
6545
6546         if (!amdgpu_in_reset(adev) && !adev->in_suspend) {
6547                 memset((void *)mqd, 0, sizeof(*mqd));
6548                 mutex_lock(&adev->srbm_mutex);
6549                 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
6550                 gfx_v10_0_gfx_mqd_init(ring);
6551 #ifdef BRING_UP_DEBUG
6552                 gfx_v10_0_gfx_queue_init_register(ring);
6553 #endif
6554                 nv_grbm_select(adev, 0, 0, 0, 0);
6555                 mutex_unlock(&adev->srbm_mutex);
6556                 if (adev->gfx.me.mqd_backup[mqd_idx])
6557                         memcpy(adev->gfx.me.mqd_backup[mqd_idx], mqd, sizeof(*mqd));
6558         } else if (amdgpu_in_reset(adev)) {
6559                 /* reset mqd with the backup copy */
6560                 if (adev->gfx.me.mqd_backup[mqd_idx])
6561                         memcpy(mqd, adev->gfx.me.mqd_backup[mqd_idx], sizeof(*mqd));
6562                 /* reset the ring */
6563                 ring->wptr = 0;
6564                 adev->wb.wb[ring->wptr_offs] = 0;
6565                 amdgpu_ring_clear_ring(ring);
6566 #ifdef BRING_UP_DEBUG
6567                 mutex_lock(&adev->srbm_mutex);
6568                 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
6569                 gfx_v10_0_gfx_queue_init_register(ring);
6570                 nv_grbm_select(adev, 0, 0, 0, 0);
6571                 mutex_unlock(&adev->srbm_mutex);
6572 #endif
6573         } else {
6574                 amdgpu_ring_clear_ring(ring);
6575         }
6576
6577         return 0;
6578 }
6579
6580 #ifndef BRING_UP_DEBUG
6581 static int gfx_v10_0_kiq_enable_kgq(struct amdgpu_device *adev)
6582 {
6583         struct amdgpu_kiq *kiq = &adev->gfx.kiq;
6584         struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring;
6585         int r, i;
6586
6587         if (!kiq->pmf || !kiq->pmf->kiq_map_queues)
6588                 return -EINVAL;
6589
6590         r = amdgpu_ring_alloc(kiq_ring, kiq->pmf->map_queues_size *
6591                                         adev->gfx.num_gfx_rings);
6592         if (r) {
6593                 DRM_ERROR("Failed to lock KIQ (%d).\n", r);
6594                 return r;
6595         }
6596
6597         for (i = 0; i < adev->gfx.num_gfx_rings; i++)
6598                 kiq->pmf->kiq_map_queues(kiq_ring, &adev->gfx.gfx_ring[i]);
6599
6600         return amdgpu_ring_test_helper(kiq_ring);
6601 }
6602 #endif
6603
6604 static int gfx_v10_0_cp_async_gfx_ring_resume(struct amdgpu_device *adev)
6605 {
6606         int r, i;
6607         struct amdgpu_ring *ring;
6608
6609         for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
6610                 ring = &adev->gfx.gfx_ring[i];
6611
6612                 r = amdgpu_bo_reserve(ring->mqd_obj, false);
6613                 if (unlikely(r != 0))
6614                         goto done;
6615
6616                 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr);
6617                 if (!r) {
6618                         r = gfx_v10_0_gfx_init_queue(ring);
6619                         amdgpu_bo_kunmap(ring->mqd_obj);
6620                         ring->mqd_ptr = NULL;
6621                 }
6622                 amdgpu_bo_unreserve(ring->mqd_obj);
6623                 if (r)
6624                         goto done;
6625         }
6626 #ifndef BRING_UP_DEBUG
6627         r = gfx_v10_0_kiq_enable_kgq(adev);
6628         if (r)
6629                 goto done;
6630 #endif
6631         r = gfx_v10_0_cp_gfx_start(adev);
6632         if (r)
6633                 goto done;
6634
6635         for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
6636                 ring = &adev->gfx.gfx_ring[i];
6637                 ring->sched.ready = true;
6638         }
6639 done:
6640         return r;
6641 }
6642
6643 static void gfx_v10_0_compute_mqd_set_priority(struct amdgpu_ring *ring, struct v10_compute_mqd *mqd)
6644 {
6645         struct amdgpu_device *adev = ring->adev;
6646
6647         if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) {
6648                 if (amdgpu_gfx_is_high_priority_compute_queue(adev, ring)) {
6649                         mqd->cp_hqd_pipe_priority = AMDGPU_GFX_PIPE_PRIO_HIGH;
6650                         mqd->cp_hqd_queue_priority =
6651                                 AMDGPU_GFX_QUEUE_PRIORITY_MAXIMUM;
6652                 }
6653         }
6654 }
6655
6656 static int gfx_v10_0_compute_mqd_init(struct amdgpu_ring *ring)
6657 {
6658         struct amdgpu_device *adev = ring->adev;
6659         struct v10_compute_mqd *mqd = ring->mqd_ptr;
6660         uint64_t hqd_gpu_addr, wb_gpu_addr, eop_base_addr;
6661         uint32_t tmp;
6662
6663         mqd->header = 0xC0310800;
6664         mqd->compute_pipelinestat_enable = 0x00000001;
6665         mqd->compute_static_thread_mgmt_se0 = 0xffffffff;
6666         mqd->compute_static_thread_mgmt_se1 = 0xffffffff;
6667         mqd->compute_static_thread_mgmt_se2 = 0xffffffff;
6668         mqd->compute_static_thread_mgmt_se3 = 0xffffffff;
6669         mqd->compute_misc_reserved = 0x00000003;
6670
6671         eop_base_addr = ring->eop_gpu_addr >> 8;
6672         mqd->cp_hqd_eop_base_addr_lo = eop_base_addr;
6673         mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr);
6674
6675         /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */
6676         tmp = RREG32_SOC15(GC, 0, mmCP_HQD_EOP_CONTROL);
6677         tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE,
6678                         (order_base_2(GFX10_MEC_HPD_SIZE / 4) - 1));
6679
6680         mqd->cp_hqd_eop_control = tmp;
6681
6682         /* enable doorbell? */
6683         tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL);
6684
6685         if (ring->use_doorbell) {
6686                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
6687                                     DOORBELL_OFFSET, ring->doorbell_index);
6688                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
6689                                     DOORBELL_EN, 1);
6690                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
6691                                     DOORBELL_SOURCE, 0);
6692                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
6693                                     DOORBELL_HIT, 0);
6694         } else {
6695                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
6696                                     DOORBELL_EN, 0);
6697         }
6698
6699         mqd->cp_hqd_pq_doorbell_control = tmp;
6700
6701         /* disable the queue if it's active */
6702         ring->wptr = 0;
6703         mqd->cp_hqd_dequeue_request = 0;
6704         mqd->cp_hqd_pq_rptr = 0;
6705         mqd->cp_hqd_pq_wptr_lo = 0;
6706         mqd->cp_hqd_pq_wptr_hi = 0;
6707
6708         /* set the pointer to the MQD */
6709         mqd->cp_mqd_base_addr_lo = ring->mqd_gpu_addr & 0xfffffffc;
6710         mqd->cp_mqd_base_addr_hi = upper_32_bits(ring->mqd_gpu_addr);
6711
6712         /* set MQD vmid to 0 */
6713         tmp = RREG32_SOC15(GC, 0, mmCP_MQD_CONTROL);
6714         tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0);
6715         mqd->cp_mqd_control = tmp;
6716
6717         /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */
6718         hqd_gpu_addr = ring->gpu_addr >> 8;
6719         mqd->cp_hqd_pq_base_lo = hqd_gpu_addr;
6720         mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr);
6721
6722         /* set up the HQD, this is similar to CP_RB0_CNTL */
6723         tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_CONTROL);
6724         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE,
6725                             (order_base_2(ring->ring_size / 4) - 1));
6726         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE,
6727                             ((order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1) << 8));
6728 #ifdef __BIG_ENDIAN
6729         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ENDIAN_SWAP, 1);
6730 #endif
6731         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 0);
6732         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, TUNNEL_DISPATCH, 0);
6733         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1);
6734         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1);
6735         mqd->cp_hqd_pq_control = tmp;
6736
6737         /* set the wb address whether it's enabled or not */
6738         wb_gpu_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
6739         mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc;
6740         mqd->cp_hqd_pq_rptr_report_addr_hi =
6741                 upper_32_bits(wb_gpu_addr) & 0xffff;
6742
6743         /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */
6744         wb_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
6745         mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc;
6746         mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff;
6747
6748         tmp = 0;
6749         /* enable the doorbell if requested */
6750         if (ring->use_doorbell) {
6751                 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL);
6752                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
6753                                 DOORBELL_OFFSET, ring->doorbell_index);
6754
6755                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
6756                                     DOORBELL_EN, 1);
6757                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
6758                                     DOORBELL_SOURCE, 0);
6759                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
6760                                     DOORBELL_HIT, 0);
6761         }
6762
6763         mqd->cp_hqd_pq_doorbell_control = tmp;
6764
6765         /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */
6766         ring->wptr = 0;
6767         mqd->cp_hqd_pq_rptr = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR);
6768
6769         /* set the vmid for the queue */
6770         mqd->cp_hqd_vmid = 0;
6771
6772         tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PERSISTENT_STATE);
6773         tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, PRELOAD_SIZE, 0x53);
6774         mqd->cp_hqd_persistent_state = tmp;
6775
6776         /* set MIN_IB_AVAIL_SIZE */
6777         tmp = RREG32_SOC15(GC, 0, mmCP_HQD_IB_CONTROL);
6778         tmp = REG_SET_FIELD(tmp, CP_HQD_IB_CONTROL, MIN_IB_AVAIL_SIZE, 3);
6779         mqd->cp_hqd_ib_control = tmp;
6780
6781         /* set static priority for a compute queue/ring */
6782         gfx_v10_0_compute_mqd_set_priority(ring, mqd);
6783
6784         /* map_queues packet doesn't need activate the queue,
6785          * so only kiq need set this field.
6786          */
6787         if (ring->funcs->type == AMDGPU_RING_TYPE_KIQ)
6788                 mqd->cp_hqd_active = 1;
6789
6790         return 0;
6791 }
6792
6793 static int gfx_v10_0_kiq_init_register(struct amdgpu_ring *ring)
6794 {
6795         struct amdgpu_device *adev = ring->adev;
6796         struct v10_compute_mqd *mqd = ring->mqd_ptr;
6797         int j;
6798
6799         /* inactivate the queue */
6800         if (amdgpu_sriov_vf(adev))
6801                 WREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE, 0);
6802
6803         /* disable wptr polling */
6804         WREG32_FIELD15(GC, 0, CP_PQ_WPTR_POLL_CNTL, EN, 0);
6805
6806         /* write the EOP addr */
6807         WREG32_SOC15(GC, 0, mmCP_HQD_EOP_BASE_ADDR,
6808                mqd->cp_hqd_eop_base_addr_lo);
6809         WREG32_SOC15(GC, 0, mmCP_HQD_EOP_BASE_ADDR_HI,
6810                mqd->cp_hqd_eop_base_addr_hi);
6811
6812         /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */
6813         WREG32_SOC15(GC, 0, mmCP_HQD_EOP_CONTROL,
6814                mqd->cp_hqd_eop_control);
6815
6816         /* enable doorbell? */
6817         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL,
6818                mqd->cp_hqd_pq_doorbell_control);
6819
6820         /* disable the queue if it's active */
6821         if (RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1) {
6822                 WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST, 1);
6823                 for (j = 0; j < adev->usec_timeout; j++) {
6824                         if (!(RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1))
6825                                 break;
6826                         udelay(1);
6827                 }
6828                 WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST,
6829                        mqd->cp_hqd_dequeue_request);
6830                 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR,
6831                        mqd->cp_hqd_pq_rptr);
6832                 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_LO,
6833                        mqd->cp_hqd_pq_wptr_lo);
6834                 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_HI,
6835                        mqd->cp_hqd_pq_wptr_hi);
6836         }
6837
6838         /* set the pointer to the MQD */
6839         WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR,
6840                mqd->cp_mqd_base_addr_lo);
6841         WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR_HI,
6842                mqd->cp_mqd_base_addr_hi);
6843
6844         /* set MQD vmid to 0 */
6845         WREG32_SOC15(GC, 0, mmCP_MQD_CONTROL,
6846                mqd->cp_mqd_control);
6847
6848         /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */
6849         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_BASE,
6850                mqd->cp_hqd_pq_base_lo);
6851         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_BASE_HI,
6852                mqd->cp_hqd_pq_base_hi);
6853
6854         /* set up the HQD, this is similar to CP_RB0_CNTL */
6855         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_CONTROL,
6856                mqd->cp_hqd_pq_control);
6857
6858         /* set the wb address whether it's enabled or not */
6859         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR_REPORT_ADDR,
6860                 mqd->cp_hqd_pq_rptr_report_addr_lo);
6861         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI,
6862                 mqd->cp_hqd_pq_rptr_report_addr_hi);
6863
6864         /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */
6865         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR,
6866                mqd->cp_hqd_pq_wptr_poll_addr_lo);
6867         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR_HI,
6868                mqd->cp_hqd_pq_wptr_poll_addr_hi);
6869
6870         /* enable the doorbell if requested */
6871         if (ring->use_doorbell) {
6872                 WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_LOWER,
6873                         (adev->doorbell_index.kiq * 2) << 2);
6874                 WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_UPPER,
6875                         (adev->doorbell_index.userqueue_end * 2) << 2);
6876         }
6877
6878         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL,
6879                mqd->cp_hqd_pq_doorbell_control);
6880
6881         /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */
6882         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_LO,
6883                mqd->cp_hqd_pq_wptr_lo);
6884         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_HI,
6885                mqd->cp_hqd_pq_wptr_hi);
6886
6887         /* set the vmid for the queue */
6888         WREG32_SOC15(GC, 0, mmCP_HQD_VMID, mqd->cp_hqd_vmid);
6889
6890         WREG32_SOC15(GC, 0, mmCP_HQD_PERSISTENT_STATE,
6891                mqd->cp_hqd_persistent_state);
6892
6893         /* activate the queue */
6894         WREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE,
6895                mqd->cp_hqd_active);
6896
6897         if (ring->use_doorbell)
6898                 WREG32_FIELD15(GC, 0, CP_PQ_STATUS, DOORBELL_ENABLE, 1);
6899
6900         return 0;
6901 }
6902
6903 static int gfx_v10_0_kiq_init_queue(struct amdgpu_ring *ring)
6904 {
6905         struct amdgpu_device *adev = ring->adev;
6906         struct v10_compute_mqd *mqd = ring->mqd_ptr;
6907         int mqd_idx = AMDGPU_MAX_COMPUTE_RINGS;
6908
6909         gfx_v10_0_kiq_setting(ring);
6910
6911         if (amdgpu_in_reset(adev)) { /* for GPU_RESET case */
6912                 /* reset MQD to a clean status */
6913                 if (adev->gfx.mec.mqd_backup[mqd_idx])
6914                         memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(*mqd));
6915
6916                 /* reset ring buffer */
6917                 ring->wptr = 0;
6918                 amdgpu_ring_clear_ring(ring);
6919
6920                 mutex_lock(&adev->srbm_mutex);
6921                 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
6922                 gfx_v10_0_kiq_init_register(ring);
6923                 nv_grbm_select(adev, 0, 0, 0, 0);
6924                 mutex_unlock(&adev->srbm_mutex);
6925         } else {
6926                 memset((void *)mqd, 0, sizeof(*mqd));
6927                 mutex_lock(&adev->srbm_mutex);
6928                 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
6929                 gfx_v10_0_compute_mqd_init(ring);
6930                 gfx_v10_0_kiq_init_register(ring);
6931                 nv_grbm_select(adev, 0, 0, 0, 0);
6932                 mutex_unlock(&adev->srbm_mutex);
6933
6934                 if (adev->gfx.mec.mqd_backup[mqd_idx])
6935                         memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(*mqd));
6936         }
6937
6938         return 0;
6939 }
6940
6941 static int gfx_v10_0_kcq_init_queue(struct amdgpu_ring *ring)
6942 {
6943         struct amdgpu_device *adev = ring->adev;
6944         struct v10_compute_mqd *mqd = ring->mqd_ptr;
6945         int mqd_idx = ring - &adev->gfx.compute_ring[0];
6946
6947         if (!amdgpu_in_reset(adev) && !adev->in_suspend) {
6948                 memset((void *)mqd, 0, sizeof(*mqd));
6949                 mutex_lock(&adev->srbm_mutex);
6950                 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
6951                 gfx_v10_0_compute_mqd_init(ring);
6952                 nv_grbm_select(adev, 0, 0, 0, 0);
6953                 mutex_unlock(&adev->srbm_mutex);
6954
6955                 if (adev->gfx.mec.mqd_backup[mqd_idx])
6956                         memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(*mqd));
6957         } else if (amdgpu_in_reset(adev)) { /* for GPU_RESET case */
6958                 /* reset MQD to a clean status */
6959                 if (adev->gfx.mec.mqd_backup[mqd_idx])
6960                         memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(*mqd));
6961
6962                 /* reset ring buffer */
6963                 ring->wptr = 0;
6964                 atomic64_set((atomic64_t *)&adev->wb.wb[ring->wptr_offs], 0);
6965                 amdgpu_ring_clear_ring(ring);
6966         } else {
6967                 amdgpu_ring_clear_ring(ring);
6968         }
6969
6970         return 0;
6971 }
6972
6973 static int gfx_v10_0_kiq_resume(struct amdgpu_device *adev)
6974 {
6975         struct amdgpu_ring *ring;
6976         int r;
6977
6978         ring = &adev->gfx.kiq.ring;
6979
6980         r = amdgpu_bo_reserve(ring->mqd_obj, false);
6981         if (unlikely(r != 0))
6982                 return r;
6983
6984         r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr);
6985         if (unlikely(r != 0))
6986                 return r;
6987
6988         gfx_v10_0_kiq_init_queue(ring);
6989         amdgpu_bo_kunmap(ring->mqd_obj);
6990         ring->mqd_ptr = NULL;
6991         amdgpu_bo_unreserve(ring->mqd_obj);
6992         ring->sched.ready = true;
6993         return 0;
6994 }
6995
6996 static int gfx_v10_0_kcq_resume(struct amdgpu_device *adev)
6997 {
6998         struct amdgpu_ring *ring = NULL;
6999         int r = 0, i;
7000
7001         gfx_v10_0_cp_compute_enable(adev, true);
7002
7003         for (i = 0; i < adev->gfx.num_compute_rings; i++) {
7004                 ring = &adev->gfx.compute_ring[i];
7005
7006                 r = amdgpu_bo_reserve(ring->mqd_obj, false);
7007                 if (unlikely(r != 0))
7008                         goto done;
7009                 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr);
7010                 if (!r) {
7011                         r = gfx_v10_0_kcq_init_queue(ring);
7012                         amdgpu_bo_kunmap(ring->mqd_obj);
7013                         ring->mqd_ptr = NULL;
7014                 }
7015                 amdgpu_bo_unreserve(ring->mqd_obj);
7016                 if (r)
7017                         goto done;
7018         }
7019
7020         r = amdgpu_gfx_enable_kcq(adev);
7021 done:
7022         return r;
7023 }
7024
7025 static int gfx_v10_0_cp_resume(struct amdgpu_device *adev)
7026 {
7027         int r, i;
7028         struct amdgpu_ring *ring;
7029
7030         if (!(adev->flags & AMD_IS_APU))
7031                 gfx_v10_0_enable_gui_idle_interrupt(adev, false);
7032
7033         if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
7034                 /* legacy firmware loading */
7035                 r = gfx_v10_0_cp_gfx_load_microcode(adev);
7036                 if (r)
7037                         return r;
7038
7039                 r = gfx_v10_0_cp_compute_load_microcode(adev);
7040                 if (r)
7041                         return r;
7042         }
7043
7044         r = gfx_v10_0_kiq_resume(adev);
7045         if (r)
7046                 return r;
7047
7048         r = gfx_v10_0_kcq_resume(adev);
7049         if (r)
7050                 return r;
7051
7052         if (!amdgpu_async_gfx_ring) {
7053                 r = gfx_v10_0_cp_gfx_resume(adev);
7054                 if (r)
7055                         return r;
7056         } else {
7057                 r = gfx_v10_0_cp_async_gfx_ring_resume(adev);
7058                 if (r)
7059                         return r;
7060         }
7061
7062         for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
7063                 ring = &adev->gfx.gfx_ring[i];
7064                 r = amdgpu_ring_test_helper(ring);
7065                 if (r)
7066                         return r;
7067         }
7068
7069         for (i = 0; i < adev->gfx.num_compute_rings; i++) {
7070                 ring = &adev->gfx.compute_ring[i];
7071                 r = amdgpu_ring_test_helper(ring);
7072                 if (r)
7073                         return r;
7074         }
7075
7076         return 0;
7077 }
7078
7079 static void gfx_v10_0_cp_enable(struct amdgpu_device *adev, bool enable)
7080 {
7081         gfx_v10_0_cp_gfx_enable(adev, enable);
7082         gfx_v10_0_cp_compute_enable(adev, enable);
7083 }
7084
7085 static bool gfx_v10_0_check_grbm_cam_remapping(struct amdgpu_device *adev)
7086 {
7087         uint32_t data, pattern = 0xDEADBEEF;
7088
7089         /* check if mmVGT_ESGS_RING_SIZE_UMD
7090          * has been remapped to mmVGT_ESGS_RING_SIZE */
7091         switch (adev->asic_type) {
7092         case CHIP_SIENNA_CICHLID:
7093         case CHIP_NAVY_FLOUNDER:
7094         case CHIP_DIMGREY_CAVEFISH:
7095                 data = RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid);
7096                 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid, 0);
7097                 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_UMD, pattern);
7098
7099                 if (RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid) == pattern) {
7100                         WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_UMD , data);
7101                         return true;
7102                 } else {
7103                         WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid, data);
7104                         return false;
7105                 }
7106                 break;
7107         case CHIP_VANGOGH:
7108                 return true;
7109         default:
7110                 data = RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE);
7111                 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE, 0);
7112                 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_UMD, pattern);
7113
7114                 if (RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE) == pattern) {
7115                         WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_UMD, data);
7116                         return true;
7117                 } else {
7118                         WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE, data);
7119                         return false;
7120                 }
7121                 break;
7122         }
7123 }
7124
7125 static void gfx_v10_0_setup_grbm_cam_remapping(struct amdgpu_device *adev)
7126 {
7127         uint32_t data;
7128
7129         if (amdgpu_sriov_vf(adev))
7130                 return;
7131
7132         /* initialize cam_index to 0
7133          * index will auto-inc after each data writting */
7134         WREG32_SOC15(GC, 0, mmGRBM_CAM_INDEX, 0);
7135
7136         switch (adev->asic_type) {
7137         case CHIP_SIENNA_CICHLID:
7138         case CHIP_NAVY_FLOUNDER:
7139         case CHIP_VANGOGH:
7140         case CHIP_DIMGREY_CAVEFISH:
7141                 /* mmVGT_TF_RING_SIZE_UMD -> mmVGT_TF_RING_SIZE */
7142                 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE_UMD) <<
7143                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7144                        (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE_Sienna_Cichlid) <<
7145                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7146                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7147                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7148
7149                 /* mmVGT_TF_MEMORY_BASE_UMD -> mmVGT_TF_MEMORY_BASE */
7150                 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_UMD) <<
7151                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7152                        (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_Sienna_Cichlid) <<
7153                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7154                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7155                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7156
7157                 /* mmVGT_TF_MEMORY_BASE_HI_UMD -> mmVGT_TF_MEMORY_BASE_HI */
7158                 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI_UMD) <<
7159                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7160                        (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI_Sienna_Cichlid) <<
7161                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7162                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7163                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7164
7165                 /* mmVGT_HS_OFFCHIP_PARAM_UMD -> mmVGT_HS_OFFCHIP_PARAM */
7166                 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM_UMD) <<
7167                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7168                        (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM_Sienna_Cichlid) <<
7169                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7170                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7171                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7172
7173                 /* mmVGT_ESGS_RING_SIZE_UMD -> mmVGT_ESGS_RING_SIZE */
7174                 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE_UMD) <<
7175                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7176                        (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid) <<
7177                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7178                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7179                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7180
7181                 /* mmVGT_GSVS_RING_SIZE_UMD -> mmVGT_GSVS_RING_SIZE */
7182                 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE_UMD) <<
7183                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7184                        (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE_Sienna_Cichlid) <<
7185                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7186                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7187                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7188
7189                 /* mmSPI_CONFIG_CNTL_REMAP -> mmSPI_CONFIG_CNTL */
7190                 data = (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL_REMAP) <<
7191                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7192                        (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL_Sienna_Cichlid) <<
7193                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7194                 break;
7195         default:
7196                 /* mmVGT_TF_RING_SIZE_UMD -> mmVGT_TF_RING_SIZE */
7197                 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE_UMD) <<
7198                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7199                        (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE) <<
7200                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7201                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7202                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7203
7204                 /* mmVGT_TF_MEMORY_BASE_UMD -> mmVGT_TF_MEMORY_BASE */
7205                 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_UMD) <<
7206                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7207                        (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE) <<
7208                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7209                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7210                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7211
7212                 /* mmVGT_TF_MEMORY_BASE_HI_UMD -> mmVGT_TF_MEMORY_BASE_HI */
7213                 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI_UMD) <<
7214                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7215                        (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI) <<
7216                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7217                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7218                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7219
7220                 /* mmVGT_HS_OFFCHIP_PARAM_UMD -> mmVGT_HS_OFFCHIP_PARAM */
7221                 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM_UMD) <<
7222                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7223                        (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM) <<
7224                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7225                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7226                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7227
7228                 /* mmVGT_ESGS_RING_SIZE_UMD -> mmVGT_ESGS_RING_SIZE */
7229                 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE_UMD) <<
7230                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7231                        (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE) <<
7232                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7233                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7234                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7235
7236                 /* mmVGT_GSVS_RING_SIZE_UMD -> mmVGT_GSVS_RING_SIZE */
7237                 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE_UMD) <<
7238                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7239                        (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE) <<
7240                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7241                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7242                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7243
7244                 /* mmSPI_CONFIG_CNTL_REMAP -> mmSPI_CONFIG_CNTL */
7245                 data = (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL_REMAP) <<
7246                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7247                        (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL) <<
7248                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7249                 break;
7250         }
7251
7252         WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7253         WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7254 }
7255
7256 static void gfx_v10_0_disable_gpa_mode(struct amdgpu_device *adev)
7257 {
7258         uint32_t data;
7259         data = RREG32_SOC15(GC, 0, mmCPC_PSP_DEBUG);
7260         data |= CPC_PSP_DEBUG__GPA_OVERRIDE_MASK;
7261         WREG32_SOC15(GC, 0, mmCPC_PSP_DEBUG, data);
7262
7263         data = RREG32_SOC15(GC, 0, mmCPG_PSP_DEBUG);
7264         data |= CPG_PSP_DEBUG__GPA_OVERRIDE_MASK;
7265         WREG32_SOC15(GC, 0, mmCPG_PSP_DEBUG, data);
7266 }
7267
7268 static int gfx_v10_0_hw_init(void *handle)
7269 {
7270         int r;
7271         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7272
7273         if (!amdgpu_emu_mode)
7274                 gfx_v10_0_init_golden_registers(adev);
7275
7276         if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
7277                 /**
7278                  * For gfx 10, rlc firmware loading relies on smu firmware is
7279                  * loaded firstly, so in direct type, it has to load smc ucode
7280                  * here before rlc.
7281                  */
7282                 if (!(adev->flags & AMD_IS_APU)) {
7283                         r = amdgpu_pm_load_smu_firmware(adev, NULL);
7284                         if (r)
7285                                 return r;
7286                 }
7287                 gfx_v10_0_disable_gpa_mode(adev);
7288         }
7289
7290         /* if GRBM CAM not remapped, set up the remapping */
7291         if (!gfx_v10_0_check_grbm_cam_remapping(adev))
7292                 gfx_v10_0_setup_grbm_cam_remapping(adev);
7293
7294         gfx_v10_0_constants_init(adev);
7295
7296         r = gfx_v10_0_rlc_resume(adev);
7297         if (r)
7298                 return r;
7299
7300         /*
7301          * init golden registers and rlc resume may override some registers,
7302          * reconfig them here
7303          */
7304         gfx_v10_0_tcp_harvest(adev);
7305
7306         r = gfx_v10_0_cp_resume(adev);
7307         if (r)
7308                 return r;
7309
7310         if (adev->asic_type == CHIP_SIENNA_CICHLID)
7311                 gfx_v10_3_program_pbb_mode(adev);
7312
7313         if (adev->asic_type >= CHIP_SIENNA_CICHLID)
7314                 gfx_v10_3_set_power_brake_sequence(adev);
7315
7316         return r;
7317 }
7318
7319 #ifndef BRING_UP_DEBUG
7320 static int gfx_v10_0_kiq_disable_kgq(struct amdgpu_device *adev)
7321 {
7322         struct amdgpu_kiq *kiq = &adev->gfx.kiq;
7323         struct amdgpu_ring *kiq_ring = &kiq->ring;
7324         int i;
7325
7326         if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues)
7327                 return -EINVAL;
7328
7329         if (amdgpu_ring_alloc(kiq_ring, kiq->pmf->unmap_queues_size *
7330                                         adev->gfx.num_gfx_rings))
7331                 return -ENOMEM;
7332
7333         for (i = 0; i < adev->gfx.num_gfx_rings; i++)
7334                 kiq->pmf->kiq_unmap_queues(kiq_ring, &adev->gfx.gfx_ring[i],
7335                                            PREEMPT_QUEUES, 0, 0);
7336
7337         return amdgpu_ring_test_helper(kiq_ring);
7338 }
7339 #endif
7340
7341 static int gfx_v10_0_hw_fini(void *handle)
7342 {
7343         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7344         int r;
7345         uint32_t tmp;
7346
7347         amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0);
7348         amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0);
7349
7350         if (!adev->in_pci_err_recovery) {
7351 #ifndef BRING_UP_DEBUG
7352                 if (amdgpu_async_gfx_ring) {
7353                         r = gfx_v10_0_kiq_disable_kgq(adev);
7354                         if (r)
7355                                 DRM_ERROR("KGQ disable failed\n");
7356                 }
7357 #endif
7358                 if (amdgpu_gfx_disable_kcq(adev))
7359                         DRM_ERROR("KCQ disable failed\n");
7360         }
7361
7362         if (amdgpu_sriov_vf(adev)) {
7363                 gfx_v10_0_cp_gfx_enable(adev, false);
7364                 /* Program KIQ position of RLC_CP_SCHEDULERS during destroy */
7365                 tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS);
7366                 tmp &= 0xffffff00;
7367                 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS, tmp);
7368
7369                 return 0;
7370         }
7371         gfx_v10_0_cp_enable(adev, false);
7372         gfx_v10_0_enable_gui_idle_interrupt(adev, false);
7373
7374         return 0;
7375 }
7376
7377 static int gfx_v10_0_suspend(void *handle)
7378 {
7379         return gfx_v10_0_hw_fini(handle);
7380 }
7381
7382 static int gfx_v10_0_resume(void *handle)
7383 {
7384         return gfx_v10_0_hw_init(handle);
7385 }
7386
7387 static bool gfx_v10_0_is_idle(void *handle)
7388 {
7389         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7390
7391         if (REG_GET_FIELD(RREG32_SOC15(GC, 0, mmGRBM_STATUS),
7392                                 GRBM_STATUS, GUI_ACTIVE))
7393                 return false;
7394         else
7395                 return true;
7396 }
7397
7398 static int gfx_v10_0_wait_for_idle(void *handle)
7399 {
7400         unsigned i;
7401         u32 tmp;
7402         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7403
7404         for (i = 0; i < adev->usec_timeout; i++) {
7405                 /* read MC_STATUS */
7406                 tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS) &
7407                         GRBM_STATUS__GUI_ACTIVE_MASK;
7408
7409                 if (!REG_GET_FIELD(tmp, GRBM_STATUS, GUI_ACTIVE))
7410                         return 0;
7411                 udelay(1);
7412         }
7413         return -ETIMEDOUT;
7414 }
7415
7416 static int gfx_v10_0_soft_reset(void *handle)
7417 {
7418         u32 grbm_soft_reset = 0;
7419         u32 tmp;
7420         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7421
7422         /* GRBM_STATUS */
7423         tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS);
7424         if (tmp & (GRBM_STATUS__PA_BUSY_MASK | GRBM_STATUS__SC_BUSY_MASK |
7425                    GRBM_STATUS__BCI_BUSY_MASK | GRBM_STATUS__SX_BUSY_MASK |
7426                    GRBM_STATUS__TA_BUSY_MASK | GRBM_STATUS__DB_BUSY_MASK |
7427                    GRBM_STATUS__CB_BUSY_MASK | GRBM_STATUS__GDS_BUSY_MASK |
7428                    GRBM_STATUS__SPI_BUSY_MASK | GRBM_STATUS__GE_BUSY_NO_DMA_MASK)) {
7429                 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
7430                                                 GRBM_SOFT_RESET, SOFT_RESET_CP,
7431                                                 1);
7432                 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
7433                                                 GRBM_SOFT_RESET, SOFT_RESET_GFX,
7434                                                 1);
7435         }
7436
7437         if (tmp & (GRBM_STATUS__CP_BUSY_MASK | GRBM_STATUS__CP_COHERENCY_BUSY_MASK)) {
7438                 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
7439                                                 GRBM_SOFT_RESET, SOFT_RESET_CP,
7440                                                 1);
7441         }
7442
7443         /* GRBM_STATUS2 */
7444         tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS2);
7445         switch (adev->asic_type) {
7446         case CHIP_SIENNA_CICHLID:
7447         case CHIP_NAVY_FLOUNDER:
7448         case CHIP_VANGOGH:
7449         case CHIP_DIMGREY_CAVEFISH:
7450                 if (REG_GET_FIELD(tmp, GRBM_STATUS2, RLC_BUSY_Sienna_Cichlid))
7451                         grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
7452                                                         GRBM_SOFT_RESET,
7453                                                         SOFT_RESET_RLC,
7454                                                         1);
7455                 break;
7456         default:
7457                 if (REG_GET_FIELD(tmp, GRBM_STATUS2, RLC_BUSY))
7458                         grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
7459                                                         GRBM_SOFT_RESET,
7460                                                         SOFT_RESET_RLC,
7461                                                         1);
7462                 break;
7463         }
7464
7465         if (grbm_soft_reset) {
7466                 /* stop the rlc */
7467                 gfx_v10_0_rlc_stop(adev);
7468
7469                 /* Disable GFX parsing/prefetching */
7470                 gfx_v10_0_cp_gfx_enable(adev, false);
7471
7472                 /* Disable MEC parsing/prefetching */
7473                 gfx_v10_0_cp_compute_enable(adev, false);
7474
7475                 if (grbm_soft_reset) {
7476                         tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);
7477                         tmp |= grbm_soft_reset;
7478                         dev_info(adev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp);
7479                         WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp);
7480                         tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);
7481
7482                         udelay(50);
7483
7484                         tmp &= ~grbm_soft_reset;
7485                         WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp);
7486                         tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);
7487                 }
7488
7489                 /* Wait a little for things to settle down */
7490                 udelay(50);
7491         }
7492         return 0;
7493 }
7494
7495 static uint64_t gfx_v10_0_get_gpu_clock_counter(struct amdgpu_device *adev)
7496 {
7497         uint64_t clock;
7498
7499         amdgpu_gfx_off_ctrl(adev, false);
7500         mutex_lock(&adev->gfx.gpu_clock_mutex);
7501         switch (adev->asic_type) {
7502         case CHIP_VANGOGH:
7503                 clock = (uint64_t)RREG32_SOC15(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER_Vangogh) |
7504                         ((uint64_t)RREG32_SOC15(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER_Vangogh) << 32ULL);
7505                 break;
7506         default:
7507                 clock = (uint64_t)RREG32_SOC15(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER) |
7508                         ((uint64_t)RREG32_SOC15(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER) << 32ULL);
7509                 break;
7510         }
7511         mutex_unlock(&adev->gfx.gpu_clock_mutex);
7512         amdgpu_gfx_off_ctrl(adev, true);
7513         return clock;
7514 }
7515
7516 static void gfx_v10_0_ring_emit_gds_switch(struct amdgpu_ring *ring,
7517                                            uint32_t vmid,
7518                                            uint32_t gds_base, uint32_t gds_size,
7519                                            uint32_t gws_base, uint32_t gws_size,
7520                                            uint32_t oa_base, uint32_t oa_size)
7521 {
7522         struct amdgpu_device *adev = ring->adev;
7523
7524         /* GDS Base */
7525         gfx_v10_0_write_data_to_reg(ring, 0, false,
7526                                     SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_BASE) + 2 * vmid,
7527                                     gds_base);
7528
7529         /* GDS Size */
7530         gfx_v10_0_write_data_to_reg(ring, 0, false,
7531                                     SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_SIZE) + 2 * vmid,
7532                                     gds_size);
7533
7534         /* GWS */
7535         gfx_v10_0_write_data_to_reg(ring, 0, false,
7536                                     SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID0) + vmid,
7537                                     gws_size << GDS_GWS_VMID0__SIZE__SHIFT | gws_base);
7538
7539         /* OA */
7540         gfx_v10_0_write_data_to_reg(ring, 0, false,
7541                                     SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID0) + vmid,
7542                                     (1 << (oa_size + oa_base)) - (1 << oa_base));
7543 }
7544
7545 static int gfx_v10_0_early_init(void *handle)
7546 {
7547         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7548
7549         switch (adev->asic_type) {
7550         case CHIP_NAVI10:
7551         case CHIP_NAVI14:
7552         case CHIP_NAVI12:
7553                 adev->gfx.num_gfx_rings = GFX10_NUM_GFX_RINGS_NV1X;
7554                 break;
7555         case CHIP_SIENNA_CICHLID:
7556         case CHIP_NAVY_FLOUNDER:
7557         case CHIP_VANGOGH:
7558         case CHIP_DIMGREY_CAVEFISH:
7559         case CHIP_BEIGE_GOBY:
7560                 adev->gfx.num_gfx_rings = GFX10_NUM_GFX_RINGS_Sienna_Cichlid;
7561                 break;
7562         default:
7563                 break;
7564         }
7565
7566         adev->gfx.num_compute_rings = min(amdgpu_gfx_get_num_kcq(adev),
7567                                           AMDGPU_MAX_COMPUTE_RINGS);
7568
7569         gfx_v10_0_set_kiq_pm4_funcs(adev);
7570         gfx_v10_0_set_ring_funcs(adev);
7571         gfx_v10_0_set_irq_funcs(adev);
7572         gfx_v10_0_set_gds_init(adev);
7573         gfx_v10_0_set_rlc_funcs(adev);
7574
7575         return 0;
7576 }
7577
7578 static int gfx_v10_0_late_init(void *handle)
7579 {
7580         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7581         int r;
7582
7583         r = amdgpu_irq_get(adev, &adev->gfx.priv_reg_irq, 0);
7584         if (r)
7585                 return r;
7586
7587         r = amdgpu_irq_get(adev, &adev->gfx.priv_inst_irq, 0);
7588         if (r)
7589                 return r;
7590
7591         return 0;
7592 }
7593
7594 static bool gfx_v10_0_is_rlc_enabled(struct amdgpu_device *adev)
7595 {
7596         uint32_t rlc_cntl;
7597
7598         /* if RLC is not enabled, do nothing */
7599         rlc_cntl = RREG32_SOC15(GC, 0, mmRLC_CNTL);
7600         return (REG_GET_FIELD(rlc_cntl, RLC_CNTL, RLC_ENABLE_F32)) ? true : false;
7601 }
7602
7603 static void gfx_v10_0_set_safe_mode(struct amdgpu_device *adev)
7604 {
7605         uint32_t data;
7606         unsigned i;
7607
7608         data = RLC_SAFE_MODE__CMD_MASK;
7609         data |= (1 << RLC_SAFE_MODE__MESSAGE__SHIFT);
7610
7611         switch (adev->asic_type) {
7612         case CHIP_SIENNA_CICHLID:
7613         case CHIP_NAVY_FLOUNDER:
7614         case CHIP_VANGOGH:
7615         case CHIP_DIMGREY_CAVEFISH:
7616                 WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE_Sienna_Cichlid, data);
7617
7618                 /* wait for RLC_SAFE_MODE */
7619                 for (i = 0; i < adev->usec_timeout; i++) {
7620                         if (!REG_GET_FIELD(RREG32_SOC15(GC, 0, mmRLC_SAFE_MODE_Sienna_Cichlid),
7621                                            RLC_SAFE_MODE, CMD))
7622                                 break;
7623                         udelay(1);
7624                 }
7625                 break;
7626         default:
7627                 WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE, data);
7628
7629                 /* wait for RLC_SAFE_MODE */
7630                 for (i = 0; i < adev->usec_timeout; i++) {
7631                         if (!REG_GET_FIELD(RREG32_SOC15(GC, 0, mmRLC_SAFE_MODE),
7632                                            RLC_SAFE_MODE, CMD))
7633                                 break;
7634                         udelay(1);
7635                 }
7636                 break;
7637         }
7638 }
7639
7640 static void gfx_v10_0_unset_safe_mode(struct amdgpu_device *adev)
7641 {
7642         uint32_t data;
7643
7644         data = RLC_SAFE_MODE__CMD_MASK;
7645         switch (adev->asic_type) {
7646         case CHIP_SIENNA_CICHLID:
7647         case CHIP_NAVY_FLOUNDER:
7648         case CHIP_VANGOGH:
7649         case CHIP_DIMGREY_CAVEFISH:
7650                 WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE_Sienna_Cichlid, data);
7651                 break;
7652         default:
7653                 WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE, data);
7654                 break;
7655         }
7656 }
7657
7658 static void gfx_v10_0_update_medium_grain_clock_gating(struct amdgpu_device *adev,
7659                                                       bool enable)
7660 {
7661         uint32_t data, def;
7662
7663         /* It is disabled by HW by default */
7664         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) {
7665                 /* 0 - Disable some blocks' MGCG */
7666                 WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, 0xe0000000);
7667                 WREG32_SOC15(GC, 0, mmCGTT_WD_CLK_CTRL, 0xff000000);
7668                 WREG32_SOC15(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xff000000);
7669                 WREG32_SOC15(GC, 0, mmCGTT_IA_CLK_CTRL, 0xff000000);
7670
7671                 /* 1 - RLC_CGTT_MGCG_OVERRIDE */
7672                 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
7673                 data &= ~(RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK |
7674                           RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK |
7675                           RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK |
7676                           RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK |
7677                           RLC_CGTT_MGCG_OVERRIDE__ENABLE_CGTS_LEGACY_MASK);
7678
7679                 if (def != data)
7680                         WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
7681
7682                 /* MGLS is a global flag to control all MGLS in GFX */
7683                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGLS) {
7684                         /* 2 - RLC memory Light sleep */
7685                         if (adev->cg_flags & AMD_CG_SUPPORT_GFX_RLC_LS) {
7686                                 def = data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL);
7687                                 data |= RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK;
7688                                 if (def != data)
7689                                         WREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL, data);
7690                         }
7691                         /* 3 - CP memory Light sleep */
7692                         if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CP_LS) {
7693                                 def = data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL);
7694                                 data |= CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK;
7695                                 if (def != data)
7696                                         WREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL, data);
7697                         }
7698                 }
7699         } else {
7700                 /* 1 - MGCG_OVERRIDE */
7701                 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
7702                 data |= (RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK |
7703                          RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK |
7704                          RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK |
7705                          RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK);
7706                 if (def != data)
7707                         WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
7708
7709                 /* 2 - disable MGLS in CP */
7710                 data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL);
7711                 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) {
7712                         data &= ~CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK;
7713                         WREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL, data);
7714                 }
7715
7716                 /* 3 - disable MGLS in RLC */
7717                 data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL);
7718                 if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK) {
7719                         data &= ~RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK;
7720                         WREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL, data);
7721                 }
7722
7723         }
7724 }
7725
7726 static void gfx_v10_0_update_3d_clock_gating(struct amdgpu_device *adev,
7727                                            bool enable)
7728 {
7729         uint32_t data, def;
7730
7731         /* Enable 3D CGCG/CGLS */
7732         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG)) {
7733                 /* write cmd to clear cgcg/cgls ov */
7734                 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
7735                 /* unset CGCG override */
7736                 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_GFX3D_CG_OVERRIDE_MASK;
7737                 /* update CGCG and CGLS override bits */
7738                 if (def != data)
7739                         WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
7740                 /* enable 3Dcgcg FSM(0x0000363f) */
7741                 def = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D);
7742                 data = (0x36 << RLC_CGCG_CGLS_CTRL_3D__CGCG_GFX_IDLE_THRESHOLD__SHIFT) |
7743                         RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK;
7744                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS)
7745                         data |= (0x000F << RLC_CGCG_CGLS_CTRL_3D__CGLS_REP_COMPANSAT_DELAY__SHIFT) |
7746                                 RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK;
7747                 if (def != data)
7748                         WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D, data);
7749
7750                 /* set IDLE_POLL_COUNT(0x00900100) */
7751                 def = RREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL);
7752                 data = (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) |
7753                         (0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT);
7754                 if (def != data)
7755                         WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL, data);
7756         } else {
7757                 /* Disable CGCG/CGLS */
7758                 def = data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D);
7759                 /* disable cgcg, cgls should be disabled */
7760                 data &= ~(RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK |
7761                           RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK);
7762                 /* disable cgcg and cgls in FSM */
7763                 if (def != data)
7764                         WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D, data);
7765         }
7766 }
7767
7768 static void gfx_v10_0_update_coarse_grain_clock_gating(struct amdgpu_device *adev,
7769                                                       bool enable)
7770 {
7771         uint32_t def, data;
7772
7773         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)) {
7774                 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
7775                 /* unset CGCG override */
7776                 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGCG_OVERRIDE_MASK;
7777                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS)
7778                         data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK;
7779                 else
7780                         data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK;
7781                 /* update CGCG and CGLS override bits */
7782                 if (def != data)
7783                         WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
7784
7785                 /* enable cgcg FSM(0x0000363F) */
7786                 def = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL);
7787                 data = (0x36 << RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT) |
7788                         RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK;
7789                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS)
7790                         data |= (0x000F << RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY__SHIFT) |
7791                                 RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK;
7792                 if (def != data)
7793                         WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, data);
7794
7795                 /* set IDLE_POLL_COUNT(0x00900100) */
7796                 def = RREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL);
7797                 data = (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) |
7798                         (0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT);
7799                 if (def != data)
7800                         WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL, data);
7801         } else {
7802                 def = data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL);
7803                 /* reset CGCG/CGLS bits */
7804                 data &= ~(RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK | RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK);
7805                 /* disable cgcg and cgls in FSM */
7806                 if (def != data)
7807                         WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, data);
7808         }
7809 }
7810
7811 static void gfx_v10_0_update_fine_grain_clock_gating(struct amdgpu_device *adev,
7812                                                       bool enable)
7813 {
7814         uint32_t def, data;
7815
7816         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_FGCG)) {
7817                 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
7818                 /* unset FGCG override */
7819                 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK;
7820                 /* update FGCG override bits */
7821                 if (def != data)
7822                         WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
7823
7824                 def = data = RREG32_SOC15(GC, 0, mmRLC_CLK_CNTL);
7825                 /* unset RLC SRAM CLK GATER override */
7826                 data &= ~RLC_CLK_CNTL__RLC_SRAM_CLK_GATER_OVERRIDE_MASK;
7827                 /* update RLC SRAM CLK GATER override bits */
7828                 if (def != data)
7829                         WREG32_SOC15(GC, 0, mmRLC_CLK_CNTL, data);
7830         } else {
7831                 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
7832                 /* reset FGCG bits */
7833                 data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK;
7834                 /* disable FGCG*/
7835                 if (def != data)
7836                         WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
7837
7838                 def = data = RREG32_SOC15(GC, 0, mmRLC_CLK_CNTL);
7839                 /* reset RLC SRAM CLK GATER bits */
7840                 data |= RLC_CLK_CNTL__RLC_SRAM_CLK_GATER_OVERRIDE_MASK;
7841                 /* disable RLC SRAM CLK*/
7842                 if (def != data)
7843                         WREG32_SOC15(GC, 0, mmRLC_CLK_CNTL, data);
7844         }
7845 }
7846
7847 static int gfx_v10_0_update_gfx_clock_gating(struct amdgpu_device *adev,
7848                                             bool enable)
7849 {
7850         amdgpu_gfx_rlc_enter_safe_mode(adev);
7851
7852         if (enable) {
7853                 /* enable FGCG firstly*/
7854                 gfx_v10_0_update_fine_grain_clock_gating(adev, enable);
7855                 /* CGCG/CGLS should be enabled after MGCG/MGLS
7856                  * ===  MGCG + MGLS ===
7857                  */
7858                 gfx_v10_0_update_medium_grain_clock_gating(adev, enable);
7859                 /* ===  CGCG /CGLS for GFX 3D Only === */
7860                 gfx_v10_0_update_3d_clock_gating(adev, enable);
7861                 /* ===  CGCG + CGLS === */
7862                 gfx_v10_0_update_coarse_grain_clock_gating(adev, enable);
7863         } else {
7864                 /* CGCG/CGLS should be disabled before MGCG/MGLS
7865                  * ===  CGCG + CGLS ===
7866                  */
7867                 gfx_v10_0_update_coarse_grain_clock_gating(adev, enable);
7868                 /* ===  CGCG /CGLS for GFX 3D Only === */
7869                 gfx_v10_0_update_3d_clock_gating(adev, enable);
7870                 /* ===  MGCG + MGLS === */
7871                 gfx_v10_0_update_medium_grain_clock_gating(adev, enable);
7872                 /* disable fgcg at last*/
7873                 gfx_v10_0_update_fine_grain_clock_gating(adev, enable);
7874         }
7875
7876         if (adev->cg_flags &
7877             (AMD_CG_SUPPORT_GFX_MGCG |
7878              AMD_CG_SUPPORT_GFX_CGLS |
7879              AMD_CG_SUPPORT_GFX_CGCG |
7880              AMD_CG_SUPPORT_GFX_3D_CGCG |
7881              AMD_CG_SUPPORT_GFX_3D_CGLS))
7882                 gfx_v10_0_enable_gui_idle_interrupt(adev, enable);
7883
7884         amdgpu_gfx_rlc_exit_safe_mode(adev);
7885
7886         return 0;
7887 }
7888
7889 static void gfx_v10_0_update_spm_vmid(struct amdgpu_device *adev, unsigned vmid)
7890 {
7891         u32 reg, data;
7892
7893         reg = SOC15_REG_OFFSET(GC, 0, mmRLC_SPM_MC_CNTL);
7894         if (amdgpu_sriov_is_pp_one_vf(adev))
7895                 data = RREG32_NO_KIQ(reg);
7896         else
7897                 data = RREG32(reg);
7898
7899         data &= ~RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK;
7900         data |= (vmid & RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK) << RLC_SPM_MC_CNTL__RLC_SPM_VMID__SHIFT;
7901
7902         if (amdgpu_sriov_is_pp_one_vf(adev))
7903                 WREG32_SOC15_NO_KIQ(GC, 0, mmRLC_SPM_MC_CNTL, data);
7904         else
7905                 WREG32_SOC15(GC, 0, mmRLC_SPM_MC_CNTL, data);
7906 }
7907
7908 static bool gfx_v10_0_check_rlcg_range(struct amdgpu_device *adev,
7909                                         uint32_t offset,
7910                                         struct soc15_reg_rlcg *entries, int arr_size)
7911 {
7912         int i;
7913         uint32_t reg;
7914
7915         if (!entries)
7916                 return false;
7917
7918         for (i = 0; i < arr_size; i++) {
7919                 const struct soc15_reg_rlcg *entry;
7920
7921                 entry = &entries[i];
7922                 reg = adev->reg_offset[entry->hwip][entry->instance][entry->segment] + entry->reg;
7923                 if (offset == reg)
7924                         return true;
7925         }
7926
7927         return false;
7928 }
7929
7930 static bool gfx_v10_0_is_rlcg_access_range(struct amdgpu_device *adev, u32 offset)
7931 {
7932         return gfx_v10_0_check_rlcg_range(adev, offset, NULL, 0);
7933 }
7934
7935 static void gfx_v10_cntl_power_gating(struct amdgpu_device *adev, bool enable)
7936 {
7937         u32 data = RREG32_SOC15(GC, 0, mmRLC_PG_CNTL);
7938
7939         if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG))
7940                 data |= RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK;
7941         else
7942                 data &= ~RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK;
7943
7944         WREG32_SOC15(GC, 0, mmRLC_PG_CNTL, data);
7945
7946         /*
7947          * CGPG enablement required and the register to program the hysteresis value
7948          * RLC_PG_DELAY_3.CGCG_ACTIVE_BEFORE_CGPG to the desired CGPG hysteresis value
7949          * in refclk count. Note that RLC FW is modified to take 16 bits from
7950          * RLC_PG_DELAY_3[15:0] as the hysteresis instead of just 8 bits.
7951          *
7952          * The recommendation from RLC team is setting RLC_PG_DELAY_3 to 200us(0x4E20)
7953          * as part of CGPG enablement starting point.
7954          */
7955         if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG) && adev->asic_type == CHIP_VANGOGH) {
7956                 data = 0x4E20 & RLC_PG_DELAY_3__CGCG_ACTIVE_BEFORE_CGPG_MASK_Vangogh;
7957                 WREG32_SOC15(GC, 0, mmRLC_PG_DELAY_3, data);
7958         }
7959 }
7960
7961 static void gfx_v10_cntl_pg(struct amdgpu_device *adev, bool enable)
7962 {
7963         amdgpu_gfx_rlc_enter_safe_mode(adev);
7964
7965         gfx_v10_cntl_power_gating(adev, enable);
7966
7967         amdgpu_gfx_rlc_exit_safe_mode(adev);
7968 }
7969
7970 static const struct amdgpu_rlc_funcs gfx_v10_0_rlc_funcs = {
7971         .is_rlc_enabled = gfx_v10_0_is_rlc_enabled,
7972         .set_safe_mode = gfx_v10_0_set_safe_mode,
7973         .unset_safe_mode = gfx_v10_0_unset_safe_mode,
7974         .init = gfx_v10_0_rlc_init,
7975         .get_csb_size = gfx_v10_0_get_csb_size,
7976         .get_csb_buffer = gfx_v10_0_get_csb_buffer,
7977         .resume = gfx_v10_0_rlc_resume,
7978         .stop = gfx_v10_0_rlc_stop,
7979         .reset = gfx_v10_0_rlc_reset,
7980         .start = gfx_v10_0_rlc_start,
7981         .update_spm_vmid = gfx_v10_0_update_spm_vmid,
7982 };
7983
7984 static const struct amdgpu_rlc_funcs gfx_v10_0_rlc_funcs_sriov = {
7985         .is_rlc_enabled = gfx_v10_0_is_rlc_enabled,
7986         .set_safe_mode = gfx_v10_0_set_safe_mode,
7987         .unset_safe_mode = gfx_v10_0_unset_safe_mode,
7988         .init = gfx_v10_0_rlc_init,
7989         .get_csb_size = gfx_v10_0_get_csb_size,
7990         .get_csb_buffer = gfx_v10_0_get_csb_buffer,
7991         .resume = gfx_v10_0_rlc_resume,
7992         .stop = gfx_v10_0_rlc_stop,
7993         .reset = gfx_v10_0_rlc_reset,
7994         .start = gfx_v10_0_rlc_start,
7995         .update_spm_vmid = gfx_v10_0_update_spm_vmid,
7996         .rlcg_wreg = gfx_v10_rlcg_wreg,
7997         .rlcg_rreg = gfx_v10_rlcg_rreg,
7998         .is_rlcg_access_range = gfx_v10_0_is_rlcg_access_range,
7999 };
8000
8001 static int gfx_v10_0_set_powergating_state(void *handle,
8002                                           enum amd_powergating_state state)
8003 {
8004         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
8005         bool enable = (state == AMD_PG_STATE_GATE);
8006
8007         if (amdgpu_sriov_vf(adev))
8008                 return 0;
8009
8010         switch (adev->asic_type) {
8011         case CHIP_NAVI10:
8012         case CHIP_NAVI14:
8013         case CHIP_NAVI12:
8014         case CHIP_SIENNA_CICHLID:
8015         case CHIP_NAVY_FLOUNDER:
8016         case CHIP_DIMGREY_CAVEFISH:
8017                 amdgpu_gfx_off_ctrl(adev, enable);
8018                 break;
8019         case CHIP_VANGOGH:
8020                 gfx_v10_cntl_pg(adev, enable);
8021                 amdgpu_gfx_off_ctrl(adev, enable);
8022                 break;
8023         default:
8024                 break;
8025         }
8026         return 0;
8027 }
8028
8029 static int gfx_v10_0_set_clockgating_state(void *handle,
8030                                           enum amd_clockgating_state state)
8031 {
8032         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
8033
8034         if (amdgpu_sriov_vf(adev))
8035                 return 0;
8036
8037         switch (adev->asic_type) {
8038         case CHIP_NAVI10:
8039         case CHIP_NAVI14:
8040         case CHIP_NAVI12:
8041         case CHIP_SIENNA_CICHLID:
8042         case CHIP_NAVY_FLOUNDER:
8043         case CHIP_VANGOGH:
8044         case CHIP_DIMGREY_CAVEFISH:
8045         case CHIP_BEIGE_GOBY:
8046                 gfx_v10_0_update_gfx_clock_gating(adev,
8047                                                  state == AMD_CG_STATE_GATE);
8048                 break;
8049         default:
8050                 break;
8051         }
8052         return 0;
8053 }
8054
8055 static void gfx_v10_0_get_clockgating_state(void *handle, u32 *flags)
8056 {
8057         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
8058         int data;
8059
8060         /* AMD_CG_SUPPORT_GFX_FGCG */
8061         data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE));
8062         if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK))
8063                 *flags |= AMD_CG_SUPPORT_GFX_FGCG;
8064
8065         /* AMD_CG_SUPPORT_GFX_MGCG */
8066         data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE));
8067         if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK))
8068                 *flags |= AMD_CG_SUPPORT_GFX_MGCG;
8069
8070         /* AMD_CG_SUPPORT_GFX_CGCG */
8071         data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGCG_CGLS_CTRL));
8072         if (data & RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK)
8073                 *flags |= AMD_CG_SUPPORT_GFX_CGCG;
8074
8075         /* AMD_CG_SUPPORT_GFX_CGLS */
8076         if (data & RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK)
8077                 *flags |= AMD_CG_SUPPORT_GFX_CGLS;
8078
8079         /* AMD_CG_SUPPORT_GFX_RLC_LS */
8080         data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_MEM_SLP_CNTL));
8081         if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK)
8082                 *flags |= AMD_CG_SUPPORT_GFX_RLC_LS | AMD_CG_SUPPORT_GFX_MGLS;
8083
8084         /* AMD_CG_SUPPORT_GFX_CP_LS */
8085         data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmCP_MEM_SLP_CNTL));
8086         if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK)
8087                 *flags |= AMD_CG_SUPPORT_GFX_CP_LS | AMD_CG_SUPPORT_GFX_MGLS;
8088
8089         /* AMD_CG_SUPPORT_GFX_3D_CGCG */
8090         data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D));
8091         if (data & RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK)
8092                 *flags |= AMD_CG_SUPPORT_GFX_3D_CGCG;
8093
8094         /* AMD_CG_SUPPORT_GFX_3D_CGLS */
8095         if (data & RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK)
8096                 *flags |= AMD_CG_SUPPORT_GFX_3D_CGLS;
8097 }
8098
8099 static u64 gfx_v10_0_ring_get_rptr_gfx(struct amdgpu_ring *ring)
8100 {
8101         return ring->adev->wb.wb[ring->rptr_offs]; /* gfx10 is 32bit rptr*/
8102 }
8103
8104 static u64 gfx_v10_0_ring_get_wptr_gfx(struct amdgpu_ring *ring)
8105 {
8106         struct amdgpu_device *adev = ring->adev;
8107         u64 wptr;
8108
8109         /* XXX check if swapping is necessary on BE */
8110         if (ring->use_doorbell) {
8111                 wptr = atomic64_read((atomic64_t *)&adev->wb.wb[ring->wptr_offs]);
8112         } else {
8113                 wptr = RREG32_SOC15(GC, 0, mmCP_RB0_WPTR);
8114                 wptr += (u64)RREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI) << 32;
8115         }
8116
8117         return wptr;
8118 }
8119
8120 static void gfx_v10_0_ring_set_wptr_gfx(struct amdgpu_ring *ring)
8121 {
8122         struct amdgpu_device *adev = ring->adev;
8123
8124         if (ring->use_doorbell) {
8125                 /* XXX check if swapping is necessary on BE */
8126                 atomic64_set((atomic64_t *)&adev->wb.wb[ring->wptr_offs], ring->wptr);
8127                 WDOORBELL64(ring->doorbell_index, ring->wptr);
8128         } else {
8129                 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR, lower_32_bits(ring->wptr));
8130                 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI, upper_32_bits(ring->wptr));
8131         }
8132 }
8133
8134 static u64 gfx_v10_0_ring_get_rptr_compute(struct amdgpu_ring *ring)
8135 {
8136         return ring->adev->wb.wb[ring->rptr_offs]; /* gfx10 hardware is 32bit rptr */
8137 }
8138
8139 static u64 gfx_v10_0_ring_get_wptr_compute(struct amdgpu_ring *ring)
8140 {
8141         u64 wptr;
8142
8143         /* XXX check if swapping is necessary on BE */
8144         if (ring->use_doorbell)
8145                 wptr = atomic64_read((atomic64_t *)&ring->adev->wb.wb[ring->wptr_offs]);
8146         else
8147                 BUG();
8148         return wptr;
8149 }
8150
8151 static void gfx_v10_0_ring_set_wptr_compute(struct amdgpu_ring *ring)
8152 {
8153         struct amdgpu_device *adev = ring->adev;
8154
8155         /* XXX check if swapping is necessary on BE */
8156         if (ring->use_doorbell) {
8157                 atomic64_set((atomic64_t *)&adev->wb.wb[ring->wptr_offs], ring->wptr);
8158                 WDOORBELL64(ring->doorbell_index, ring->wptr);
8159         } else {
8160                 BUG(); /* only DOORBELL method supported on gfx10 now */
8161         }
8162 }
8163
8164 static void gfx_v10_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
8165 {
8166         struct amdgpu_device *adev = ring->adev;
8167         u32 ref_and_mask, reg_mem_engine;
8168         const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio.hdp_flush_reg;
8169
8170         if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) {
8171                 switch (ring->me) {
8172                 case 1:
8173                         ref_and_mask = nbio_hf_reg->ref_and_mask_cp2 << ring->pipe;
8174                         break;
8175                 case 2:
8176                         ref_and_mask = nbio_hf_reg->ref_and_mask_cp6 << ring->pipe;
8177                         break;
8178                 default:
8179                         return;
8180                 }
8181                 reg_mem_engine = 0;
8182         } else {
8183                 ref_and_mask = nbio_hf_reg->ref_and_mask_cp0;
8184                 reg_mem_engine = 1; /* pfp */
8185         }
8186
8187         gfx_v10_0_wait_reg_mem(ring, reg_mem_engine, 0, 1,
8188                                adev->nbio.funcs->get_hdp_flush_req_offset(adev),
8189                                adev->nbio.funcs->get_hdp_flush_done_offset(adev),
8190                                ref_and_mask, ref_and_mask, 0x20);
8191 }
8192
8193 static void gfx_v10_0_ring_emit_ib_gfx(struct amdgpu_ring *ring,
8194                                        struct amdgpu_job *job,
8195                                        struct amdgpu_ib *ib,
8196                                        uint32_t flags)
8197 {
8198         unsigned vmid = AMDGPU_JOB_GET_VMID(job);
8199         u32 header, control = 0;
8200
8201         if (ib->flags & AMDGPU_IB_FLAG_CE)
8202                 header = PACKET3(PACKET3_INDIRECT_BUFFER_CNST, 2);
8203         else
8204                 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2);
8205
8206         control |= ib->length_dw | (vmid << 24);
8207
8208         if ((amdgpu_sriov_vf(ring->adev) || amdgpu_mcbp) && (ib->flags & AMDGPU_IB_FLAG_PREEMPT)) {
8209                 control |= INDIRECT_BUFFER_PRE_ENB(1);
8210
8211                 if (flags & AMDGPU_IB_PREEMPTED)
8212                         control |= INDIRECT_BUFFER_PRE_RESUME(1);
8213
8214                 if (!(ib->flags & AMDGPU_IB_FLAG_CE) && vmid)
8215                         gfx_v10_0_ring_emit_de_meta(ring,
8216                                     (!amdgpu_sriov_vf(ring->adev) && flags & AMDGPU_IB_PREEMPTED) ? true : false);
8217         }
8218
8219         amdgpu_ring_write(ring, header);
8220         BUG_ON(ib->gpu_addr & 0x3); /* Dword align */
8221         amdgpu_ring_write(ring,
8222 #ifdef __BIG_ENDIAN
8223                 (2 << 0) |
8224 #endif
8225                 lower_32_bits(ib->gpu_addr));
8226         amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
8227         amdgpu_ring_write(ring, control);
8228 }
8229
8230 static void gfx_v10_0_ring_emit_ib_compute(struct amdgpu_ring *ring,
8231                                            struct amdgpu_job *job,
8232                                            struct amdgpu_ib *ib,
8233                                            uint32_t flags)
8234 {
8235         unsigned vmid = AMDGPU_JOB_GET_VMID(job);
8236         u32 control = INDIRECT_BUFFER_VALID | ib->length_dw | (vmid << 24);
8237
8238         /* Currently, there is a high possibility to get wave ID mismatch
8239          * between ME and GDS, leading to a hw deadlock, because ME generates
8240          * different wave IDs than the GDS expects. This situation happens
8241          * randomly when at least 5 compute pipes use GDS ordered append.
8242          * The wave IDs generated by ME are also wrong after suspend/resume.
8243          * Those are probably bugs somewhere else in the kernel driver.
8244          *
8245          * Writing GDS_COMPUTE_MAX_WAVE_ID resets wave ID counters in ME and
8246          * GDS to 0 for this ring (me/pipe).
8247          */
8248         if (ib->flags & AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID) {
8249                 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
8250                 amdgpu_ring_write(ring, mmGDS_COMPUTE_MAX_WAVE_ID);
8251                 amdgpu_ring_write(ring, ring->adev->gds.gds_compute_max_wave_id);
8252         }
8253
8254         amdgpu_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
8255         BUG_ON(ib->gpu_addr & 0x3); /* Dword align */
8256         amdgpu_ring_write(ring,
8257 #ifdef __BIG_ENDIAN
8258                                 (2 << 0) |
8259 #endif
8260                                 lower_32_bits(ib->gpu_addr));
8261         amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
8262         amdgpu_ring_write(ring, control);
8263 }
8264
8265 static void gfx_v10_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr,
8266                                      u64 seq, unsigned flags)
8267 {
8268         bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
8269         bool int_sel = flags & AMDGPU_FENCE_FLAG_INT;
8270
8271         /* RELEASE_MEM - flush caches, send int */
8272         amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 6));
8273         amdgpu_ring_write(ring, (PACKET3_RELEASE_MEM_GCR_SEQ |
8274                                  PACKET3_RELEASE_MEM_GCR_GL2_WB |
8275                                  PACKET3_RELEASE_MEM_GCR_GLM_INV | /* must be set with GLM_WB */
8276                                  PACKET3_RELEASE_MEM_GCR_GLM_WB |
8277                                  PACKET3_RELEASE_MEM_CACHE_POLICY(3) |
8278                                  PACKET3_RELEASE_MEM_EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) |
8279                                  PACKET3_RELEASE_MEM_EVENT_INDEX(5)));
8280         amdgpu_ring_write(ring, (PACKET3_RELEASE_MEM_DATA_SEL(write64bit ? 2 : 1) |
8281                                  PACKET3_RELEASE_MEM_INT_SEL(int_sel ? 2 : 0)));
8282
8283         /*
8284          * the address should be Qword aligned if 64bit write, Dword
8285          * aligned if only send 32bit data low (discard data high)
8286          */
8287         if (write64bit)
8288                 BUG_ON(addr & 0x7);
8289         else
8290                 BUG_ON(addr & 0x3);
8291         amdgpu_ring_write(ring, lower_32_bits(addr));
8292         amdgpu_ring_write(ring, upper_32_bits(addr));
8293         amdgpu_ring_write(ring, lower_32_bits(seq));
8294         amdgpu_ring_write(ring, upper_32_bits(seq));
8295         amdgpu_ring_write(ring, 0);
8296 }
8297
8298 static void gfx_v10_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
8299 {
8300         int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
8301         uint32_t seq = ring->fence_drv.sync_seq;
8302         uint64_t addr = ring->fence_drv.gpu_addr;
8303
8304         gfx_v10_0_wait_reg_mem(ring, usepfp, 1, 0, lower_32_bits(addr),
8305                                upper_32_bits(addr), seq, 0xffffffff, 4);
8306 }
8307
8308 static void gfx_v10_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
8309                                          unsigned vmid, uint64_t pd_addr)
8310 {
8311         amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
8312
8313         /* compute doesn't have PFP */
8314         if (ring->funcs->type == AMDGPU_RING_TYPE_GFX) {
8315                 /* sync PFP to ME, otherwise we might get invalid PFP reads */
8316                 amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0));
8317                 amdgpu_ring_write(ring, 0x0);
8318         }
8319 }
8320
8321 static void gfx_v10_0_ring_emit_fence_kiq(struct amdgpu_ring *ring, u64 addr,
8322                                           u64 seq, unsigned int flags)
8323 {
8324         struct amdgpu_device *adev = ring->adev;
8325
8326         /* we only allocate 32bit for each seq wb address */
8327         BUG_ON(flags & AMDGPU_FENCE_FLAG_64BIT);
8328
8329         /* write fence seq to the "addr" */
8330         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
8331         amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
8332                                  WRITE_DATA_DST_SEL(5) | WR_CONFIRM));
8333         amdgpu_ring_write(ring, lower_32_bits(addr));
8334         amdgpu_ring_write(ring, upper_32_bits(addr));
8335         amdgpu_ring_write(ring, lower_32_bits(seq));
8336
8337         if (flags & AMDGPU_FENCE_FLAG_INT) {
8338                 /* set register to trigger INT */
8339                 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
8340                 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
8341                                          WRITE_DATA_DST_SEL(0) | WR_CONFIRM));
8342                 amdgpu_ring_write(ring, SOC15_REG_OFFSET(GC, 0, mmCPC_INT_STATUS));
8343                 amdgpu_ring_write(ring, 0);
8344                 amdgpu_ring_write(ring, 0x20000000); /* src_id is 178 */
8345         }
8346 }
8347
8348 static void gfx_v10_0_ring_emit_sb(struct amdgpu_ring *ring)
8349 {
8350         amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
8351         amdgpu_ring_write(ring, 0);
8352 }
8353
8354 static void gfx_v10_0_ring_emit_cntxcntl(struct amdgpu_ring *ring,
8355                                          uint32_t flags)
8356 {
8357         uint32_t dw2 = 0;
8358
8359         if (amdgpu_mcbp || amdgpu_sriov_vf(ring->adev))
8360                 gfx_v10_0_ring_emit_ce_meta(ring,
8361                                     (!amdgpu_sriov_vf(ring->adev) && flags & AMDGPU_IB_PREEMPTED) ? true : false);
8362
8363         dw2 |= 0x80000000; /* set load_enable otherwise this package is just NOPs */
8364         if (flags & AMDGPU_HAVE_CTX_SWITCH) {
8365                 /* set load_global_config & load_global_uconfig */
8366                 dw2 |= 0x8001;
8367                 /* set load_cs_sh_regs */
8368                 dw2 |= 0x01000000;
8369                 /* set load_per_context_state & load_gfx_sh_regs for GFX */
8370                 dw2 |= 0x10002;
8371
8372                 /* set load_ce_ram if preamble presented */
8373                 if (AMDGPU_PREAMBLE_IB_PRESENT & flags)
8374                         dw2 |= 0x10000000;
8375         } else {
8376                 /* still load_ce_ram if this is the first time preamble presented
8377                  * although there is no context switch happens.
8378                  */
8379                 if (AMDGPU_PREAMBLE_IB_PRESENT_FIRST & flags)
8380                         dw2 |= 0x10000000;
8381         }
8382
8383         amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1));
8384         amdgpu_ring_write(ring, dw2);
8385         amdgpu_ring_write(ring, 0);
8386 }
8387
8388 static unsigned gfx_v10_0_ring_emit_init_cond_exec(struct amdgpu_ring *ring)
8389 {
8390         unsigned ret;
8391
8392         amdgpu_ring_write(ring, PACKET3(PACKET3_COND_EXEC, 3));
8393         amdgpu_ring_write(ring, lower_32_bits(ring->cond_exe_gpu_addr));
8394         amdgpu_ring_write(ring, upper_32_bits(ring->cond_exe_gpu_addr));
8395         amdgpu_ring_write(ring, 0); /* discard following DWs if *cond_exec_gpu_addr==0 */
8396         ret = ring->wptr & ring->buf_mask;
8397         amdgpu_ring_write(ring, 0x55aa55aa); /* patch dummy value later */
8398
8399         return ret;
8400 }
8401
8402 static void gfx_v10_0_ring_emit_patch_cond_exec(struct amdgpu_ring *ring, unsigned offset)
8403 {
8404         unsigned cur;
8405         BUG_ON(offset > ring->buf_mask);
8406         BUG_ON(ring->ring[offset] != 0x55aa55aa);
8407
8408         cur = (ring->wptr - 1) & ring->buf_mask;
8409         if (likely(cur > offset))
8410                 ring->ring[offset] = cur - offset;
8411         else
8412                 ring->ring[offset] = (ring->buf_mask + 1) - offset + cur;
8413 }
8414
8415 static int gfx_v10_0_ring_preempt_ib(struct amdgpu_ring *ring)
8416 {
8417         int i, r = 0;
8418         struct amdgpu_device *adev = ring->adev;
8419         struct amdgpu_kiq *kiq = &adev->gfx.kiq;
8420         struct amdgpu_ring *kiq_ring = &kiq->ring;
8421         unsigned long flags;
8422
8423         if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues)
8424                 return -EINVAL;
8425
8426         spin_lock_irqsave(&kiq->ring_lock, flags);
8427
8428         if (amdgpu_ring_alloc(kiq_ring, kiq->pmf->unmap_queues_size)) {
8429                 spin_unlock_irqrestore(&kiq->ring_lock, flags);
8430                 return -ENOMEM;
8431         }
8432
8433         /* assert preemption condition */
8434         amdgpu_ring_set_preempt_cond_exec(ring, false);
8435
8436         /* assert IB preemption, emit the trailing fence */
8437         kiq->pmf->kiq_unmap_queues(kiq_ring, ring, PREEMPT_QUEUES_NO_UNMAP,
8438                                    ring->trail_fence_gpu_addr,
8439                                    ++ring->trail_seq);
8440         amdgpu_ring_commit(kiq_ring);
8441
8442         spin_unlock_irqrestore(&kiq->ring_lock, flags);
8443
8444         /* poll the trailing fence */
8445         for (i = 0; i < adev->usec_timeout; i++) {
8446                 if (ring->trail_seq ==
8447                     le32_to_cpu(*(ring->trail_fence_cpu_addr)))
8448                         break;
8449                 udelay(1);
8450         }
8451
8452         if (i >= adev->usec_timeout) {
8453                 r = -EINVAL;
8454                 DRM_ERROR("ring %d failed to preempt ib\n", ring->idx);
8455         }
8456
8457         /* deassert preemption condition */
8458         amdgpu_ring_set_preempt_cond_exec(ring, true);
8459         return r;
8460 }
8461
8462 static void gfx_v10_0_ring_emit_ce_meta(struct amdgpu_ring *ring, bool resume)
8463 {
8464         struct amdgpu_device *adev = ring->adev;
8465         struct v10_ce_ib_state ce_payload = {0};
8466         uint64_t csa_addr;
8467         int cnt;
8468
8469         cnt = (sizeof(ce_payload) >> 2) + 4 - 2;
8470         csa_addr = amdgpu_csa_vaddr(ring->adev);
8471
8472         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt));
8473         amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(2) |
8474                                  WRITE_DATA_DST_SEL(8) |
8475                                  WR_CONFIRM) |
8476                                  WRITE_DATA_CACHE_POLICY(0));
8477         amdgpu_ring_write(ring, lower_32_bits(csa_addr +
8478                               offsetof(struct v10_gfx_meta_data, ce_payload)));
8479         amdgpu_ring_write(ring, upper_32_bits(csa_addr +
8480                               offsetof(struct v10_gfx_meta_data, ce_payload)));
8481
8482         if (resume)
8483                 amdgpu_ring_write_multiple(ring, adev->virt.csa_cpu_addr +
8484                                            offsetof(struct v10_gfx_meta_data,
8485                                                     ce_payload),
8486                                            sizeof(ce_payload) >> 2);
8487         else
8488                 amdgpu_ring_write_multiple(ring, (void *)&ce_payload,
8489                                            sizeof(ce_payload) >> 2);
8490 }
8491
8492 static void gfx_v10_0_ring_emit_de_meta(struct amdgpu_ring *ring, bool resume)
8493 {
8494         struct amdgpu_device *adev = ring->adev;
8495         struct v10_de_ib_state de_payload = {0};
8496         uint64_t csa_addr, gds_addr;
8497         int cnt;
8498
8499         csa_addr = amdgpu_csa_vaddr(ring->adev);
8500         gds_addr = ALIGN(csa_addr + AMDGPU_CSA_SIZE - adev->gds.gds_size,
8501                          PAGE_SIZE);
8502         de_payload.gds_backup_addrlo = lower_32_bits(gds_addr);
8503         de_payload.gds_backup_addrhi = upper_32_bits(gds_addr);
8504
8505         cnt = (sizeof(de_payload) >> 2) + 4 - 2;
8506         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt));
8507         amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(1) |
8508                                  WRITE_DATA_DST_SEL(8) |
8509                                  WR_CONFIRM) |
8510                                  WRITE_DATA_CACHE_POLICY(0));
8511         amdgpu_ring_write(ring, lower_32_bits(csa_addr +
8512                               offsetof(struct v10_gfx_meta_data, de_payload)));
8513         amdgpu_ring_write(ring, upper_32_bits(csa_addr +
8514                               offsetof(struct v10_gfx_meta_data, de_payload)));
8515
8516         if (resume)
8517                 amdgpu_ring_write_multiple(ring, adev->virt.csa_cpu_addr +
8518                                            offsetof(struct v10_gfx_meta_data,
8519                                                     de_payload),
8520                                            sizeof(de_payload) >> 2);
8521         else
8522                 amdgpu_ring_write_multiple(ring, (void *)&de_payload,
8523                                            sizeof(de_payload) >> 2);
8524 }
8525
8526 static void gfx_v10_0_ring_emit_frame_cntl(struct amdgpu_ring *ring, bool start,
8527                                     bool secure)
8528 {
8529         uint32_t v = secure ? FRAME_TMZ : 0;
8530
8531         amdgpu_ring_write(ring, PACKET3(PACKET3_FRAME_CONTROL, 0));
8532         amdgpu_ring_write(ring, v | FRAME_CMD(start ? 0 : 1));
8533 }
8534
8535 static void gfx_v10_0_ring_emit_rreg(struct amdgpu_ring *ring, uint32_t reg,
8536                                      uint32_t reg_val_offs)
8537 {
8538         struct amdgpu_device *adev = ring->adev;
8539
8540         amdgpu_ring_write(ring, PACKET3(PACKET3_COPY_DATA, 4));
8541         amdgpu_ring_write(ring, 0 |     /* src: register*/
8542                                 (5 << 8) |      /* dst: memory */
8543                                 (1 << 20));     /* write confirm */
8544         amdgpu_ring_write(ring, reg);
8545         amdgpu_ring_write(ring, 0);
8546         amdgpu_ring_write(ring, lower_32_bits(adev->wb.gpu_addr +
8547                                 reg_val_offs * 4));
8548         amdgpu_ring_write(ring, upper_32_bits(adev->wb.gpu_addr +
8549                                 reg_val_offs * 4));
8550 }
8551
8552 static void gfx_v10_0_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg,
8553                                    uint32_t val)
8554 {
8555         uint32_t cmd = 0;
8556
8557         switch (ring->funcs->type) {
8558         case AMDGPU_RING_TYPE_GFX:
8559                 cmd = WRITE_DATA_ENGINE_SEL(1) | WR_CONFIRM;
8560                 break;
8561         case AMDGPU_RING_TYPE_KIQ:
8562                 cmd = (1 << 16); /* no inc addr */
8563                 break;
8564         default:
8565                 cmd = WR_CONFIRM;
8566                 break;
8567         }
8568         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
8569         amdgpu_ring_write(ring, cmd);
8570         amdgpu_ring_write(ring, reg);
8571         amdgpu_ring_write(ring, 0);
8572         amdgpu_ring_write(ring, val);
8573 }
8574
8575 static void gfx_v10_0_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,
8576                                         uint32_t val, uint32_t mask)
8577 {
8578         gfx_v10_0_wait_reg_mem(ring, 0, 0, 0, reg, 0, val, mask, 0x20);
8579 }
8580
8581 static void gfx_v10_0_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring,
8582                                                    uint32_t reg0, uint32_t reg1,
8583                                                    uint32_t ref, uint32_t mask)
8584 {
8585         int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
8586         struct amdgpu_device *adev = ring->adev;
8587         bool fw_version_ok = false;
8588
8589         fw_version_ok = adev->gfx.cp_fw_write_wait;
8590
8591         if (fw_version_ok)
8592                 gfx_v10_0_wait_reg_mem(ring, usepfp, 0, 1, reg0, reg1,
8593                                        ref, mask, 0x20);
8594         else
8595                 amdgpu_ring_emit_reg_write_reg_wait_helper(ring, reg0, reg1,
8596                                                            ref, mask);
8597 }
8598
8599 static void gfx_v10_0_ring_soft_recovery(struct amdgpu_ring *ring,
8600                                          unsigned vmid)
8601 {
8602         struct amdgpu_device *adev = ring->adev;
8603         uint32_t value = 0;
8604
8605         value = REG_SET_FIELD(value, SQ_CMD, CMD, 0x03);
8606         value = REG_SET_FIELD(value, SQ_CMD, MODE, 0x01);
8607         value = REG_SET_FIELD(value, SQ_CMD, CHECK_VMID, 1);
8608         value = REG_SET_FIELD(value, SQ_CMD, VM_ID, vmid);
8609         WREG32_SOC15(GC, 0, mmSQ_CMD, value);
8610 }
8611
8612 static void
8613 gfx_v10_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev,
8614                                       uint32_t me, uint32_t pipe,
8615                                       enum amdgpu_interrupt_state state)
8616 {
8617         uint32_t cp_int_cntl, cp_int_cntl_reg;
8618
8619         if (!me) {
8620                 switch (pipe) {
8621                 case 0:
8622                         cp_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_INT_CNTL_RING0);
8623                         break;
8624                 case 1:
8625                         cp_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_INT_CNTL_RING1);
8626                         break;
8627                 default:
8628                         DRM_DEBUG("invalid pipe %d\n", pipe);
8629                         return;
8630                 }
8631         } else {
8632                 DRM_DEBUG("invalid me %d\n", me);
8633                 return;
8634         }
8635
8636         switch (state) {
8637         case AMDGPU_IRQ_STATE_DISABLE:
8638                 cp_int_cntl = RREG32(cp_int_cntl_reg);
8639                 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
8640                                             TIME_STAMP_INT_ENABLE, 0);
8641                 WREG32(cp_int_cntl_reg, cp_int_cntl);
8642                 break;
8643         case AMDGPU_IRQ_STATE_ENABLE:
8644                 cp_int_cntl = RREG32(cp_int_cntl_reg);
8645                 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
8646                                             TIME_STAMP_INT_ENABLE, 1);
8647                 WREG32(cp_int_cntl_reg, cp_int_cntl);
8648                 break;
8649         default:
8650                 break;
8651         }
8652 }
8653
8654 static void gfx_v10_0_set_compute_eop_interrupt_state(struct amdgpu_device *adev,
8655                                                      int me, int pipe,
8656                                                      enum amdgpu_interrupt_state state)
8657 {
8658         u32 mec_int_cntl, mec_int_cntl_reg;
8659
8660         /*
8661          * amdgpu controls only the first MEC. That's why this function only
8662          * handles the setting of interrupts for this specific MEC. All other
8663          * pipes' interrupts are set by amdkfd.
8664          */
8665
8666         if (me == 1) {
8667                 switch (pipe) {
8668                 case 0:
8669                         mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE0_INT_CNTL);
8670                         break;
8671                 case 1:
8672                         mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE1_INT_CNTL);
8673                         break;
8674                 case 2:
8675                         mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE2_INT_CNTL);
8676                         break;
8677                 case 3:
8678                         mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE3_INT_CNTL);
8679                         break;
8680                 default:
8681                         DRM_DEBUG("invalid pipe %d\n", pipe);
8682                         return;
8683                 }
8684         } else {
8685                 DRM_DEBUG("invalid me %d\n", me);
8686                 return;
8687         }
8688
8689         switch (state) {
8690         case AMDGPU_IRQ_STATE_DISABLE:
8691                 mec_int_cntl = RREG32(mec_int_cntl_reg);
8692                 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,
8693                                              TIME_STAMP_INT_ENABLE, 0);
8694                 WREG32(mec_int_cntl_reg, mec_int_cntl);
8695                 break;
8696         case AMDGPU_IRQ_STATE_ENABLE:
8697                 mec_int_cntl = RREG32(mec_int_cntl_reg);
8698                 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,
8699                                              TIME_STAMP_INT_ENABLE, 1);
8700                 WREG32(mec_int_cntl_reg, mec_int_cntl);
8701                 break;
8702         default:
8703                 break;
8704         }
8705 }
8706
8707 static int gfx_v10_0_set_eop_interrupt_state(struct amdgpu_device *adev,
8708                                             struct amdgpu_irq_src *src,
8709                                             unsigned type,
8710                                             enum amdgpu_interrupt_state state)
8711 {
8712         switch (type) {
8713         case AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP:
8714                 gfx_v10_0_set_gfx_eop_interrupt_state(adev, 0, 0, state);
8715                 break;
8716         case AMDGPU_CP_IRQ_GFX_ME0_PIPE1_EOP:
8717                 gfx_v10_0_set_gfx_eop_interrupt_state(adev, 0, 1, state);
8718                 break;
8719         case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP:
8720                 gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 0, state);
8721                 break;
8722         case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP:
8723                 gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 1, state);
8724                 break;
8725         case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP:
8726                 gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 2, state);
8727                 break;
8728         case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP:
8729                 gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 3, state);
8730                 break;
8731         case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP:
8732                 gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 0, state);
8733                 break;
8734         case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP:
8735                 gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 1, state);
8736                 break;
8737         case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP:
8738                 gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 2, state);
8739                 break;
8740         case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP:
8741                 gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 3, state);
8742                 break;
8743         default:
8744                 break;
8745         }
8746         return 0;
8747 }
8748
8749 static int gfx_v10_0_eop_irq(struct amdgpu_device *adev,
8750                              struct amdgpu_irq_src *source,
8751                              struct amdgpu_iv_entry *entry)
8752 {
8753         int i;
8754         u8 me_id, pipe_id, queue_id;
8755         struct amdgpu_ring *ring;
8756
8757         DRM_DEBUG("IH: CP EOP\n");
8758         me_id = (entry->ring_id & 0x0c) >> 2;
8759         pipe_id = (entry->ring_id & 0x03) >> 0;
8760         queue_id = (entry->ring_id & 0x70) >> 4;
8761
8762         switch (me_id) {
8763         case 0:
8764                 if (pipe_id == 0)
8765                         amdgpu_fence_process(&adev->gfx.gfx_ring[0]);
8766                 else
8767                         amdgpu_fence_process(&adev->gfx.gfx_ring[1]);
8768                 break;
8769         case 1:
8770         case 2:
8771                 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
8772                         ring = &adev->gfx.compute_ring[i];
8773                         /* Per-queue interrupt is supported for MEC starting from VI.
8774                           * The interrupt can only be enabled/disabled per pipe instead of per queue.
8775                           */
8776                         if ((ring->me == me_id) && (ring->pipe == pipe_id) && (ring->queue == queue_id))
8777                                 amdgpu_fence_process(ring);
8778                 }
8779                 break;
8780         }
8781         return 0;
8782 }
8783
8784 static int gfx_v10_0_set_priv_reg_fault_state(struct amdgpu_device *adev,
8785                                               struct amdgpu_irq_src *source,
8786                                               unsigned type,
8787                                               enum amdgpu_interrupt_state state)
8788 {
8789         switch (state) {
8790         case AMDGPU_IRQ_STATE_DISABLE:
8791         case AMDGPU_IRQ_STATE_ENABLE:
8792                 WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0,
8793                                PRIV_REG_INT_ENABLE,
8794                                state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
8795                 break;
8796         default:
8797                 break;
8798         }
8799
8800         return 0;
8801 }
8802
8803 static int gfx_v10_0_set_priv_inst_fault_state(struct amdgpu_device *adev,
8804                                                struct amdgpu_irq_src *source,
8805                                                unsigned type,
8806                                                enum amdgpu_interrupt_state state)
8807 {
8808         switch (state) {
8809         case AMDGPU_IRQ_STATE_DISABLE:
8810         case AMDGPU_IRQ_STATE_ENABLE:
8811                 WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0,
8812                                PRIV_INSTR_INT_ENABLE,
8813                                state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
8814                 break;
8815         default:
8816                 break;
8817         }
8818
8819         return 0;
8820 }
8821
8822 static void gfx_v10_0_handle_priv_fault(struct amdgpu_device *adev,
8823                                         struct amdgpu_iv_entry *entry)
8824 {
8825         u8 me_id, pipe_id, queue_id;
8826         struct amdgpu_ring *ring;
8827         int i;
8828
8829         me_id = (entry->ring_id & 0x0c) >> 2;
8830         pipe_id = (entry->ring_id & 0x03) >> 0;
8831         queue_id = (entry->ring_id & 0x70) >> 4;
8832
8833         switch (me_id) {
8834         case 0:
8835                 for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
8836                         ring = &adev->gfx.gfx_ring[i];
8837                         /* we only enabled 1 gfx queue per pipe for now */
8838                         if (ring->me == me_id && ring->pipe == pipe_id)
8839                                 drm_sched_fault(&ring->sched);
8840                 }
8841                 break;
8842         case 1:
8843         case 2:
8844                 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
8845                         ring = &adev->gfx.compute_ring[i];
8846                         if (ring->me == me_id && ring->pipe == pipe_id &&
8847                             ring->queue == queue_id)
8848                                 drm_sched_fault(&ring->sched);
8849                 }
8850                 break;
8851         default:
8852                 BUG();
8853         }
8854 }
8855
8856 static int gfx_v10_0_priv_reg_irq(struct amdgpu_device *adev,
8857                                   struct amdgpu_irq_src *source,
8858                                   struct amdgpu_iv_entry *entry)
8859 {
8860         DRM_ERROR("Illegal register access in command stream\n");
8861         gfx_v10_0_handle_priv_fault(adev, entry);
8862         return 0;
8863 }
8864
8865 static int gfx_v10_0_priv_inst_irq(struct amdgpu_device *adev,
8866                                    struct amdgpu_irq_src *source,
8867                                    struct amdgpu_iv_entry *entry)
8868 {
8869         DRM_ERROR("Illegal instruction in command stream\n");
8870         gfx_v10_0_handle_priv_fault(adev, entry);
8871         return 0;
8872 }
8873
8874 static int gfx_v10_0_kiq_set_interrupt_state(struct amdgpu_device *adev,
8875                                              struct amdgpu_irq_src *src,
8876                                              unsigned int type,
8877                                              enum amdgpu_interrupt_state state)
8878 {
8879         uint32_t tmp, target;
8880         struct amdgpu_ring *ring = &(adev->gfx.kiq.ring);
8881
8882         if (ring->me == 1)
8883                 target = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE0_INT_CNTL);
8884         else
8885                 target = SOC15_REG_OFFSET(GC, 0, mmCP_ME2_PIPE0_INT_CNTL);
8886         target += ring->pipe;
8887
8888         switch (type) {
8889         case AMDGPU_CP_KIQ_IRQ_DRIVER0:
8890                 if (state == AMDGPU_IRQ_STATE_DISABLE) {
8891                         tmp = RREG32_SOC15(GC, 0, mmCPC_INT_CNTL);
8892                         tmp = REG_SET_FIELD(tmp, CPC_INT_CNTL,
8893                                             GENERIC2_INT_ENABLE, 0);
8894                         WREG32_SOC15(GC, 0, mmCPC_INT_CNTL, tmp);
8895
8896                         tmp = RREG32(target);
8897                         tmp = REG_SET_FIELD(tmp, CP_ME2_PIPE0_INT_CNTL,
8898                                             GENERIC2_INT_ENABLE, 0);
8899                         WREG32(target, tmp);
8900                 } else {
8901                         tmp = RREG32_SOC15(GC, 0, mmCPC_INT_CNTL);
8902                         tmp = REG_SET_FIELD(tmp, CPC_INT_CNTL,
8903                                             GENERIC2_INT_ENABLE, 1);
8904                         WREG32_SOC15(GC, 0, mmCPC_INT_CNTL, tmp);
8905
8906                         tmp = RREG32(target);
8907                         tmp = REG_SET_FIELD(tmp, CP_ME2_PIPE0_INT_CNTL,
8908                                             GENERIC2_INT_ENABLE, 1);
8909                         WREG32(target, tmp);
8910                 }
8911                 break;
8912         default:
8913                 BUG(); /* kiq only support GENERIC2_INT now */
8914                 break;
8915         }
8916         return 0;
8917 }
8918
8919 static int gfx_v10_0_kiq_irq(struct amdgpu_device *adev,
8920                              struct amdgpu_irq_src *source,
8921                              struct amdgpu_iv_entry *entry)
8922 {
8923         u8 me_id, pipe_id, queue_id;
8924         struct amdgpu_ring *ring = &(adev->gfx.kiq.ring);
8925
8926         me_id = (entry->ring_id & 0x0c) >> 2;
8927         pipe_id = (entry->ring_id & 0x03) >> 0;
8928         queue_id = (entry->ring_id & 0x70) >> 4;
8929         DRM_DEBUG("IH: CPC GENERIC2_INT, me:%d, pipe:%d, queue:%d\n",
8930                    me_id, pipe_id, queue_id);
8931
8932         amdgpu_fence_process(ring);
8933         return 0;
8934 }
8935
8936 static void gfx_v10_0_emit_mem_sync(struct amdgpu_ring *ring)
8937 {
8938         const unsigned int gcr_cntl =
8939                         PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_INV(1) |
8940                         PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_WB(1) |
8941                         PACKET3_ACQUIRE_MEM_GCR_CNTL_GLM_INV(1) |
8942                         PACKET3_ACQUIRE_MEM_GCR_CNTL_GLM_WB(1) |
8943                         PACKET3_ACQUIRE_MEM_GCR_CNTL_GL1_INV(1) |
8944                         PACKET3_ACQUIRE_MEM_GCR_CNTL_GLV_INV(1) |
8945                         PACKET3_ACQUIRE_MEM_GCR_CNTL_GLK_INV(1) |
8946                         PACKET3_ACQUIRE_MEM_GCR_CNTL_GLI_INV(1);
8947
8948         /* ACQUIRE_MEM - make one or more surfaces valid for use by the subsequent operations */
8949         amdgpu_ring_write(ring, PACKET3(PACKET3_ACQUIRE_MEM, 6));
8950         amdgpu_ring_write(ring, 0); /* CP_COHER_CNTL */
8951         amdgpu_ring_write(ring, 0xffffffff);  /* CP_COHER_SIZE */
8952         amdgpu_ring_write(ring, 0xffffff);  /* CP_COHER_SIZE_HI */
8953         amdgpu_ring_write(ring, 0); /* CP_COHER_BASE */
8954         amdgpu_ring_write(ring, 0);  /* CP_COHER_BASE_HI */
8955         amdgpu_ring_write(ring, 0x0000000A); /* POLL_INTERVAL */
8956         amdgpu_ring_write(ring, gcr_cntl); /* GCR_CNTL */
8957 }
8958
8959 static const struct amd_ip_funcs gfx_v10_0_ip_funcs = {
8960         .name = "gfx_v10_0",
8961         .early_init = gfx_v10_0_early_init,
8962         .late_init = gfx_v10_0_late_init,
8963         .sw_init = gfx_v10_0_sw_init,
8964         .sw_fini = gfx_v10_0_sw_fini,
8965         .hw_init = gfx_v10_0_hw_init,
8966         .hw_fini = gfx_v10_0_hw_fini,
8967         .suspend = gfx_v10_0_suspend,
8968         .resume = gfx_v10_0_resume,
8969         .is_idle = gfx_v10_0_is_idle,
8970         .wait_for_idle = gfx_v10_0_wait_for_idle,
8971         .soft_reset = gfx_v10_0_soft_reset,
8972         .set_clockgating_state = gfx_v10_0_set_clockgating_state,
8973         .set_powergating_state = gfx_v10_0_set_powergating_state,
8974         .get_clockgating_state = gfx_v10_0_get_clockgating_state,
8975 };
8976
8977 static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_gfx = {
8978         .type = AMDGPU_RING_TYPE_GFX,
8979         .align_mask = 0xff,
8980         .nop = PACKET3(PACKET3_NOP, 0x3FFF),
8981         .support_64bit_ptrs = true,
8982         .vmhub = AMDGPU_GFXHUB_0,
8983         .get_rptr = gfx_v10_0_ring_get_rptr_gfx,
8984         .get_wptr = gfx_v10_0_ring_get_wptr_gfx,
8985         .set_wptr = gfx_v10_0_ring_set_wptr_gfx,
8986         .emit_frame_size = /* totally 242 maximum if 16 IBs */
8987                 5 + /* COND_EXEC */
8988                 7 + /* PIPELINE_SYNC */
8989                 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 +
8990                 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 +
8991                 2 + /* VM_FLUSH */
8992                 8 + /* FENCE for VM_FLUSH */
8993                 20 + /* GDS switch */
8994                 4 + /* double SWITCH_BUFFER,
8995                      * the first COND_EXEC jump to the place
8996                      * just prior to this double SWITCH_BUFFER
8997                      */
8998                 5 + /* COND_EXEC */
8999                 7 + /* HDP_flush */
9000                 4 + /* VGT_flush */
9001                 14 + /* CE_META */
9002                 31 + /* DE_META */
9003                 3 + /* CNTX_CTRL */
9004                 5 + /* HDP_INVL */
9005                 8 + 8 + /* FENCE x2 */
9006                 2 + /* SWITCH_BUFFER */
9007                 8, /* gfx_v10_0_emit_mem_sync */
9008         .emit_ib_size = 4, /* gfx_v10_0_ring_emit_ib_gfx */
9009         .emit_ib = gfx_v10_0_ring_emit_ib_gfx,
9010         .emit_fence = gfx_v10_0_ring_emit_fence,
9011         .emit_pipeline_sync = gfx_v10_0_ring_emit_pipeline_sync,
9012         .emit_vm_flush = gfx_v10_0_ring_emit_vm_flush,
9013         .emit_gds_switch = gfx_v10_0_ring_emit_gds_switch,
9014         .emit_hdp_flush = gfx_v10_0_ring_emit_hdp_flush,
9015         .test_ring = gfx_v10_0_ring_test_ring,
9016         .test_ib = gfx_v10_0_ring_test_ib,
9017         .insert_nop = amdgpu_ring_insert_nop,
9018         .pad_ib = amdgpu_ring_generic_pad_ib,
9019         .emit_switch_buffer = gfx_v10_0_ring_emit_sb,
9020         .emit_cntxcntl = gfx_v10_0_ring_emit_cntxcntl,
9021         .init_cond_exec = gfx_v10_0_ring_emit_init_cond_exec,
9022         .patch_cond_exec = gfx_v10_0_ring_emit_patch_cond_exec,
9023         .preempt_ib = gfx_v10_0_ring_preempt_ib,
9024         .emit_frame_cntl = gfx_v10_0_ring_emit_frame_cntl,
9025         .emit_wreg = gfx_v10_0_ring_emit_wreg,
9026         .emit_reg_wait = gfx_v10_0_ring_emit_reg_wait,
9027         .emit_reg_write_reg_wait = gfx_v10_0_ring_emit_reg_write_reg_wait,
9028         .soft_recovery = gfx_v10_0_ring_soft_recovery,
9029         .emit_mem_sync = gfx_v10_0_emit_mem_sync,
9030 };
9031
9032 static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_compute = {
9033         .type = AMDGPU_RING_TYPE_COMPUTE,
9034         .align_mask = 0xff,
9035         .nop = PACKET3(PACKET3_NOP, 0x3FFF),
9036         .support_64bit_ptrs = true,
9037         .vmhub = AMDGPU_GFXHUB_0,
9038         .get_rptr = gfx_v10_0_ring_get_rptr_compute,
9039         .get_wptr = gfx_v10_0_ring_get_wptr_compute,
9040         .set_wptr = gfx_v10_0_ring_set_wptr_compute,
9041         .emit_frame_size =
9042                 20 + /* gfx_v10_0_ring_emit_gds_switch */
9043                 7 + /* gfx_v10_0_ring_emit_hdp_flush */
9044                 5 + /* hdp invalidate */
9045                 7 + /* gfx_v10_0_ring_emit_pipeline_sync */
9046                 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 +
9047                 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 +
9048                 2 + /* gfx_v10_0_ring_emit_vm_flush */
9049                 8 + 8 + 8 + /* gfx_v10_0_ring_emit_fence x3 for user fence, vm fence */
9050                 8, /* gfx_v10_0_emit_mem_sync */
9051         .emit_ib_size = 7, /* gfx_v10_0_ring_emit_ib_compute */
9052         .emit_ib = gfx_v10_0_ring_emit_ib_compute,
9053         .emit_fence = gfx_v10_0_ring_emit_fence,
9054         .emit_pipeline_sync = gfx_v10_0_ring_emit_pipeline_sync,
9055         .emit_vm_flush = gfx_v10_0_ring_emit_vm_flush,
9056         .emit_gds_switch = gfx_v10_0_ring_emit_gds_switch,
9057         .emit_hdp_flush = gfx_v10_0_ring_emit_hdp_flush,
9058         .test_ring = gfx_v10_0_ring_test_ring,
9059         .test_ib = gfx_v10_0_ring_test_ib,
9060         .insert_nop = amdgpu_ring_insert_nop,
9061         .pad_ib = amdgpu_ring_generic_pad_ib,
9062         .emit_wreg = gfx_v10_0_ring_emit_wreg,
9063         .emit_reg_wait = gfx_v10_0_ring_emit_reg_wait,
9064         .emit_reg_write_reg_wait = gfx_v10_0_ring_emit_reg_write_reg_wait,
9065         .emit_mem_sync = gfx_v10_0_emit_mem_sync,
9066 };
9067
9068 static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_kiq = {
9069         .type = AMDGPU_RING_TYPE_KIQ,
9070         .align_mask = 0xff,
9071         .nop = PACKET3(PACKET3_NOP, 0x3FFF),
9072         .support_64bit_ptrs = true,
9073         .vmhub = AMDGPU_GFXHUB_0,
9074         .get_rptr = gfx_v10_0_ring_get_rptr_compute,
9075         .get_wptr = gfx_v10_0_ring_get_wptr_compute,
9076         .set_wptr = gfx_v10_0_ring_set_wptr_compute,
9077         .emit_frame_size =
9078                 20 + /* gfx_v10_0_ring_emit_gds_switch */
9079                 7 + /* gfx_v10_0_ring_emit_hdp_flush */
9080                 5 + /*hdp invalidate */
9081                 7 + /* gfx_v10_0_ring_emit_pipeline_sync */
9082                 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 +
9083                 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 +
9084                 2 + /* gfx_v10_0_ring_emit_vm_flush */
9085                 8 + 8 + 8, /* gfx_v10_0_ring_emit_fence_kiq x3 for user fence, vm fence */
9086         .emit_ib_size = 7, /* gfx_v10_0_ring_emit_ib_compute */
9087         .emit_ib = gfx_v10_0_ring_emit_ib_compute,
9088         .emit_fence = gfx_v10_0_ring_emit_fence_kiq,
9089         .test_ring = gfx_v10_0_ring_test_ring,
9090         .test_ib = gfx_v10_0_ring_test_ib,
9091         .insert_nop = amdgpu_ring_insert_nop,
9092         .pad_ib = amdgpu_ring_generic_pad_ib,
9093         .emit_rreg = gfx_v10_0_ring_emit_rreg,
9094         .emit_wreg = gfx_v10_0_ring_emit_wreg,
9095         .emit_reg_wait = gfx_v10_0_ring_emit_reg_wait,
9096         .emit_reg_write_reg_wait = gfx_v10_0_ring_emit_reg_write_reg_wait,
9097 };
9098
9099 static void gfx_v10_0_set_ring_funcs(struct amdgpu_device *adev)
9100 {
9101         int i;
9102
9103         adev->gfx.kiq.ring.funcs = &gfx_v10_0_ring_funcs_kiq;
9104
9105         for (i = 0; i < adev->gfx.num_gfx_rings; i++)
9106                 adev->gfx.gfx_ring[i].funcs = &gfx_v10_0_ring_funcs_gfx;
9107
9108         for (i = 0; i < adev->gfx.num_compute_rings; i++)
9109                 adev->gfx.compute_ring[i].funcs = &gfx_v10_0_ring_funcs_compute;
9110 }
9111
9112 static const struct amdgpu_irq_src_funcs gfx_v10_0_eop_irq_funcs = {
9113         .set = gfx_v10_0_set_eop_interrupt_state,
9114         .process = gfx_v10_0_eop_irq,
9115 };
9116
9117 static const struct amdgpu_irq_src_funcs gfx_v10_0_priv_reg_irq_funcs = {
9118         .set = gfx_v10_0_set_priv_reg_fault_state,
9119         .process = gfx_v10_0_priv_reg_irq,
9120 };
9121
9122 static const struct amdgpu_irq_src_funcs gfx_v10_0_priv_inst_irq_funcs = {
9123         .set = gfx_v10_0_set_priv_inst_fault_state,
9124         .process = gfx_v10_0_priv_inst_irq,
9125 };
9126
9127 static const struct amdgpu_irq_src_funcs gfx_v10_0_kiq_irq_funcs = {
9128         .set = gfx_v10_0_kiq_set_interrupt_state,
9129         .process = gfx_v10_0_kiq_irq,
9130 };
9131
9132 static void gfx_v10_0_set_irq_funcs(struct amdgpu_device *adev)
9133 {
9134         adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST;
9135         adev->gfx.eop_irq.funcs = &gfx_v10_0_eop_irq_funcs;
9136
9137         adev->gfx.kiq.irq.num_types = AMDGPU_CP_KIQ_IRQ_LAST;
9138         adev->gfx.kiq.irq.funcs = &gfx_v10_0_kiq_irq_funcs;
9139
9140         adev->gfx.priv_reg_irq.num_types = 1;
9141         adev->gfx.priv_reg_irq.funcs = &gfx_v10_0_priv_reg_irq_funcs;
9142
9143         adev->gfx.priv_inst_irq.num_types = 1;
9144         adev->gfx.priv_inst_irq.funcs = &gfx_v10_0_priv_inst_irq_funcs;
9145 }
9146
9147 static void gfx_v10_0_set_rlc_funcs(struct amdgpu_device *adev)
9148 {
9149         switch (adev->asic_type) {
9150         case CHIP_NAVI10:
9151         case CHIP_NAVI14:
9152         case CHIP_SIENNA_CICHLID:
9153         case CHIP_NAVY_FLOUNDER:
9154         case CHIP_VANGOGH:
9155         case CHIP_DIMGREY_CAVEFISH:
9156         case CHIP_BEIGE_GOBY:
9157                 adev->gfx.rlc.funcs = &gfx_v10_0_rlc_funcs;
9158                 break;
9159         case CHIP_NAVI12:
9160                 adev->gfx.rlc.funcs = &gfx_v10_0_rlc_funcs_sriov;
9161                 break;
9162         default:
9163                 break;
9164         }
9165 }
9166
9167 static void gfx_v10_0_set_gds_init(struct amdgpu_device *adev)
9168 {
9169         unsigned total_cu = adev->gfx.config.max_cu_per_sh *
9170                             adev->gfx.config.max_sh_per_se *
9171                             adev->gfx.config.max_shader_engines;
9172
9173         adev->gds.gds_size = 0x10000;
9174         adev->gds.gds_compute_max_wave_id = total_cu * 32 - 1;
9175         adev->gds.gws_size = 64;
9176         adev->gds.oa_size = 16;
9177 }
9178
9179 static void gfx_v10_0_set_user_wgp_inactive_bitmap_per_sh(struct amdgpu_device *adev,
9180                                                           u32 bitmap)
9181 {
9182         u32 data;
9183
9184         if (!bitmap)
9185                 return;
9186
9187         data = bitmap << GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT;
9188         data &= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK;
9189
9190         WREG32_SOC15(GC, 0, mmGC_USER_SHADER_ARRAY_CONFIG, data);
9191 }
9192
9193 static u32 gfx_v10_0_get_wgp_active_bitmap_per_sh(struct amdgpu_device *adev)
9194 {
9195         u32 data, wgp_bitmask;
9196         data = RREG32_SOC15(GC, 0, mmCC_GC_SHADER_ARRAY_CONFIG);
9197         data |= RREG32_SOC15(GC, 0, mmGC_USER_SHADER_ARRAY_CONFIG);
9198
9199         data &= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK;
9200         data >>= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT;
9201
9202         wgp_bitmask =
9203                 amdgpu_gfx_create_bitmask(adev->gfx.config.max_cu_per_sh >> 1);
9204
9205         return (~data) & wgp_bitmask;
9206 }
9207
9208 static u32 gfx_v10_0_get_cu_active_bitmap_per_sh(struct amdgpu_device *adev)
9209 {
9210         u32 wgp_idx, wgp_active_bitmap;
9211         u32 cu_bitmap_per_wgp, cu_active_bitmap;
9212
9213         wgp_active_bitmap = gfx_v10_0_get_wgp_active_bitmap_per_sh(adev);
9214         cu_active_bitmap = 0;
9215
9216         for (wgp_idx = 0; wgp_idx < 16; wgp_idx++) {
9217                 /* if there is one WGP enabled, it means 2 CUs will be enabled */
9218                 cu_bitmap_per_wgp = 3 << (2 * wgp_idx);
9219                 if (wgp_active_bitmap & (1 << wgp_idx))
9220                         cu_active_bitmap |= cu_bitmap_per_wgp;
9221         }
9222
9223         return cu_active_bitmap;
9224 }
9225
9226 static int gfx_v10_0_get_cu_info(struct amdgpu_device *adev,
9227                                  struct amdgpu_cu_info *cu_info)
9228 {
9229         int i, j, k, counter, active_cu_number = 0;
9230         u32 mask, bitmap, ao_bitmap, ao_cu_mask = 0;
9231         unsigned disable_masks[4 * 2];
9232
9233         if (!adev || !cu_info)
9234                 return -EINVAL;
9235
9236         amdgpu_gfx_parse_disable_cu(disable_masks, 4, 2);
9237
9238         mutex_lock(&adev->grbm_idx_mutex);
9239         for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
9240                 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
9241                         bitmap = i * adev->gfx.config.max_sh_per_se + j;
9242                         if ((adev->asic_type == CHIP_SIENNA_CICHLID) &&
9243                             ((gfx_v10_3_get_disabled_sa(adev) >> bitmap) & 1))
9244                                 continue;
9245                         mask = 1;
9246                         ao_bitmap = 0;
9247                         counter = 0;
9248                         gfx_v10_0_select_se_sh(adev, i, j, 0xffffffff);
9249                         if (i < 4 && j < 2)
9250                                 gfx_v10_0_set_user_wgp_inactive_bitmap_per_sh(
9251                                         adev, disable_masks[i * 2 + j]);
9252                         bitmap = gfx_v10_0_get_cu_active_bitmap_per_sh(adev);
9253                         cu_info->bitmap[i][j] = bitmap;
9254
9255                         for (k = 0; k < adev->gfx.config.max_cu_per_sh; k++) {
9256                                 if (bitmap & mask) {
9257                                         if (counter < adev->gfx.config.max_cu_per_sh)
9258                                                 ao_bitmap |= mask;
9259                                         counter++;
9260                                 }
9261                                 mask <<= 1;
9262                         }
9263                         active_cu_number += counter;
9264                         if (i < 2 && j < 2)
9265                                 ao_cu_mask |= (ao_bitmap << (i * 16 + j * 8));
9266                         cu_info->ao_cu_bitmap[i][j] = ao_bitmap;
9267                 }
9268         }
9269         gfx_v10_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
9270         mutex_unlock(&adev->grbm_idx_mutex);
9271
9272         cu_info->number = active_cu_number;
9273         cu_info->ao_cu_mask = ao_cu_mask;
9274         cu_info->simd_per_cu = NUM_SIMD_PER_CU;
9275
9276         return 0;
9277 }
9278
9279 static u32 gfx_v10_3_get_disabled_sa(struct amdgpu_device *adev)
9280 {
9281         uint32_t efuse_setting, vbios_setting, disabled_sa, max_sa_mask;
9282
9283         efuse_setting = RREG32_SOC15(GC, 0, mmCC_GC_SA_UNIT_DISABLE);
9284         efuse_setting &= CC_GC_SA_UNIT_DISABLE__SA_DISABLE_MASK;
9285         efuse_setting >>= CC_GC_SA_UNIT_DISABLE__SA_DISABLE__SHIFT;
9286
9287         vbios_setting = RREG32_SOC15(GC, 0, mmGC_USER_SA_UNIT_DISABLE);
9288         vbios_setting &= GC_USER_SA_UNIT_DISABLE__SA_DISABLE_MASK;
9289         vbios_setting >>= GC_USER_SA_UNIT_DISABLE__SA_DISABLE__SHIFT;
9290
9291         max_sa_mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_sh_per_se *
9292                                                 adev->gfx.config.max_shader_engines);
9293         disabled_sa = efuse_setting | vbios_setting;
9294         disabled_sa &= max_sa_mask;
9295
9296         return disabled_sa;
9297 }
9298
9299 static void gfx_v10_3_program_pbb_mode(struct amdgpu_device *adev)
9300 {
9301         uint32_t max_sa_per_se, max_sa_per_se_mask, max_shader_engines;
9302         uint32_t disabled_sa_mask, se_index, disabled_sa_per_se;
9303
9304         disabled_sa_mask = gfx_v10_3_get_disabled_sa(adev);
9305
9306         max_sa_per_se = adev->gfx.config.max_sh_per_se;
9307         max_sa_per_se_mask = (1 << max_sa_per_se) - 1;
9308         max_shader_engines = adev->gfx.config.max_shader_engines;
9309
9310         for (se_index = 0; max_shader_engines > se_index; se_index++) {
9311                 disabled_sa_per_se = disabled_sa_mask >> (se_index * max_sa_per_se);
9312                 disabled_sa_per_se &= max_sa_per_se_mask;
9313                 if (disabled_sa_per_se == max_sa_per_se_mask) {
9314                         WREG32_FIELD15(GC, 0, PA_SC_ENHANCE_3, FORCE_PBB_WORKLOAD_MODE_TO_ZERO, 1);
9315                         break;
9316                 }
9317         }
9318 }
9319
9320 static void gfx_v10_3_set_power_brake_sequence(struct amdgpu_device *adev)
9321 {
9322         WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX,
9323                      (0x1 << GRBM_GFX_INDEX__SA_BROADCAST_WRITES__SHIFT) |
9324                      (0x1 << GRBM_GFX_INDEX__INSTANCE_BROADCAST_WRITES__SHIFT) |
9325                      (0x1 << GRBM_GFX_INDEX__SE_BROADCAST_WRITES__SHIFT));
9326
9327         WREG32_SOC15(GC, 0, mmGC_CAC_IND_INDEX, ixPWRBRK_STALL_PATTERN_CTRL);
9328         WREG32_SOC15(GC, 0, mmGC_CAC_IND_DATA,
9329                      (0x1 << PWRBRK_STALL_PATTERN_CTRL__PWRBRK_STEP_INTERVAL__SHIFT) |
9330                      (0x12 << PWRBRK_STALL_PATTERN_CTRL__PWRBRK_BEGIN_STEP__SHIFT) |
9331                      (0x13 << PWRBRK_STALL_PATTERN_CTRL__PWRBRK_END_STEP__SHIFT) |
9332                      (0xf << PWRBRK_STALL_PATTERN_CTRL__PWRBRK_THROTTLE_PATTERN_BIT_NUMS__SHIFT));
9333
9334         WREG32_SOC15(GC, 0, mmGC_THROTTLE_CTRL_Sienna_Cichlid,
9335                      (0x1 << GC_THROTTLE_CTRL__PWRBRK_STALL_EN__SHIFT) |
9336                      (0x1 << GC_THROTTLE_CTRL__PATTERN_MODE__SHIFT) |
9337                      (0x5 << GC_THROTTLE_CTRL__RELEASE_STEP_INTERVAL__SHIFT));
9338
9339         WREG32_SOC15(GC, 0, mmDIDT_IND_INDEX, ixDIDT_SQ_THROTTLE_CTRL);
9340
9341         WREG32_SOC15(GC, 0, mmDIDT_IND_DATA,
9342                      (0x1 << DIDT_SQ_THROTTLE_CTRL__PWRBRK_STALL_EN__SHIFT));
9343 }
9344
9345 const struct amdgpu_ip_block_version gfx_v10_0_ip_block =
9346 {
9347         .type = AMD_IP_BLOCK_TYPE_GFX,
9348         .major = 10,
9349         .minor = 0,
9350         .rev = 0,
9351         .funcs = &gfx_v10_0_ip_funcs,
9352 };