drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

   1 /*
   2  * Copyright 2019 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #include <linux/delay.h>
  25 #include <linux/kernel.h>
  26 #include <linux/firmware.h>
  27 #include <linux/module.h>
  28 #include <linux/pci.h>
  29 #include "amdgpu.h"
  30 #include "amdgpu_gfx.h"
  31 #include "amdgpu_psp.h"
  32 #include "nv.h"
  33 #include "nvd.h"
  34
  35 #include "gc/gc_10_1_0_offset.h"
  36 #include "gc/gc_10_1_0_sh_mask.h"
  37 #include "smuio/smuio_11_0_0_offset.h"
  38 #include "smuio/smuio_11_0_0_sh_mask.h"
  39 #include "navi10_enum.h"
  40 #include "ivsrcid/gfx/irqsrcs_gfx_10_1.h"
  41
  42 #include "soc15.h"
  43 #include "soc15d.h"
  44 #include "soc15_common.h"
  45 #include "clearstate_gfx10.h"
  46 #include "v10_structs.h"
  47 #include "gfx_v10_0.h"
  48 #include "nbio_v2_3.h"
  49
  50 /**
  51  * Navi10 has two graphic rings to share each graphic pipe.
  52  * 1. Primary ring
  53  * 2. Async ring
  54  */
  55 #define GFX10_NUM_GFX_RINGS_NV1X        1
  56 #define GFX10_NUM_GFX_RINGS_Sienna_Cichlid      1
  57 #define GFX10_MEC_HPD_SIZE      2048
  58
  59 #define F32_CE_PROGRAM_RAM_SIZE         65536
  60 #define RLCG_UCODE_LOADING_START_ADDRESS        0x00002000L
  61
  62 #define mmCGTT_GS_NGG_CLK_CTRL  0x5087
  63 #define mmCGTT_GS_NGG_CLK_CTRL_BASE_IDX 1
  64 #define mmCGTT_SPI_RA0_CLK_CTRL 0x507a
  65 #define mmCGTT_SPI_RA0_CLK_CTRL_BASE_IDX 1
  66 #define mmCGTT_SPI_RA1_CLK_CTRL 0x507b
  67 #define mmCGTT_SPI_RA1_CLK_CTRL_BASE_IDX 1
  68
  69 #define GB_ADDR_CONFIG__NUM_PKRS__SHIFT                                                                       0x8
  70 #define GB_ADDR_CONFIG__NUM_PKRS_MASK                                                                         0x00000700L
  71
  72 #define mmCGTS_TCC_DISABLE_gc_10_3                 0x5006
  73 #define mmCGTS_TCC_DISABLE_gc_10_3_BASE_IDX        1
  74 #define mmCGTS_USER_TCC_DISABLE_gc_10_3            0x5007
  75 #define mmCGTS_USER_TCC_DISABLE_gc_10_3_BASE_IDX   1
  76
  77 #define mmCP_MEC_CNTL_Sienna_Cichlid                      0x0f55
  78 #define mmCP_MEC_CNTL_Sienna_Cichlid_BASE_IDX             0
  79 #define mmRLC_SAFE_MODE_Sienna_Cichlid                  0x4ca0
  80 #define mmRLC_SAFE_MODE_Sienna_Cichlid_BASE_IDX         1
  81 #define mmRLC_CP_SCHEDULERS_Sienna_Cichlid              0x4ca1
  82 #define mmRLC_CP_SCHEDULERS_Sienna_Cichlid_BASE_IDX     1
  83 #define mmSPI_CONFIG_CNTL_Sienna_Cichlid                        0x11ec
  84 #define mmSPI_CONFIG_CNTL_Sienna_Cichlid_BASE_IDX               0
  85 #define mmVGT_ESGS_RING_SIZE_Sienna_Cichlid             0x0fc1
  86 #define mmVGT_ESGS_RING_SIZE_Sienna_Cichlid_BASE_IDX    0
  87 #define mmVGT_GSVS_RING_SIZE_Sienna_Cichlid             0x0fc2
  88 #define mmVGT_GSVS_RING_SIZE_Sienna_Cichlid_BASE_IDX    0
  89 #define mmVGT_TF_RING_SIZE_Sienna_Cichlid                       0x0fc3
  90 #define mmVGT_TF_RING_SIZE_Sienna_Cichlid_BASE_IDX      0
  91 #define mmVGT_HS_OFFCHIP_PARAM_Sienna_Cichlid           0x0fc4
  92 #define mmVGT_HS_OFFCHIP_PARAM_Sienna_Cichlid_BASE_IDX  0
  93 #define mmVGT_TF_MEMORY_BASE_Sienna_Cichlid             0x0fc5
  94 #define mmVGT_TF_MEMORY_BASE_Sienna_Cichlid_BASE_IDX    0
  95 #define mmVGT_TF_MEMORY_BASE_HI_Sienna_Cichlid          0x0fc6
  96 #define mmVGT_TF_MEMORY_BASE_HI_Sienna_Cichlid_BASE_IDX 0
  97 #define GRBM_STATUS2__RLC_BUSY_Sienna_Cichlid__SHIFT    0x1a
  98 #define GRBM_STATUS2__RLC_BUSY_Sienna_Cichlid_MASK      0x04000000L
  99 #define CP_RB_DOORBELL_RANGE_LOWER__DOORBELL_RANGE_LOWER_Sienna_Cichlid_MASK    0x00000FFCL
 100 #define CP_RB_DOORBELL_RANGE_LOWER__DOORBELL_RANGE_LOWER_Sienna_Cichlid__SHIFT  0x2
 101 #define CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_Sienna_Cichlid_MASK    0x00000FFCL
 102 #define mmGCR_GENERAL_CNTL_Sienna_Cichlid                       0x1580
 103 #define mmGCR_GENERAL_CNTL_Sienna_Cichlid_BASE_IDX      0
 104
 105 #define mmGOLDEN_TSC_COUNT_UPPER_Vangogh                0x0025
 106 #define mmGOLDEN_TSC_COUNT_UPPER_Vangogh_BASE_IDX       1
 107 #define mmGOLDEN_TSC_COUNT_LOWER_Vangogh                0x0026
 108 #define mmGOLDEN_TSC_COUNT_LOWER_Vangogh_BASE_IDX       1
 109 #define mmSPI_CONFIG_CNTL_1_Vangogh              0x2441
 110 #define mmSPI_CONFIG_CNTL_1_Vangogh_BASE_IDX     1
 111 #define mmVGT_TF_MEMORY_BASE_HI_Vangogh          0x2261
 112 #define mmVGT_TF_MEMORY_BASE_HI_Vangogh_BASE_IDX 1
 113 #define mmVGT_HS_OFFCHIP_PARAM_Vangogh           0x224f
 114 #define mmVGT_HS_OFFCHIP_PARAM_Vangogh_BASE_IDX  1
 115 #define mmVGT_TF_RING_SIZE_Vangogh               0x224e
 116 #define mmVGT_TF_RING_SIZE_Vangogh_BASE_IDX      1
 117 #define mmVGT_GSVS_RING_SIZE_Vangogh             0x2241
 118 #define mmVGT_GSVS_RING_SIZE_Vangogh_BASE_IDX    1
 119 #define mmVGT_TF_MEMORY_BASE_Vangogh             0x2250
 120 #define mmVGT_TF_MEMORY_BASE_Vangogh_BASE_IDX    1
 121 #define mmVGT_ESGS_RING_SIZE_Vangogh             0x2240
 122 #define mmVGT_ESGS_RING_SIZE_Vangogh_BASE_IDX    1
 123 #define mmSPI_CONFIG_CNTL_Vangogh                0x2440
 124 #define mmSPI_CONFIG_CNTL_Vangogh_BASE_IDX       1
 125 #define mmGCR_GENERAL_CNTL_Vangogh               0x1580
 126 #define mmGCR_GENERAL_CNTL_Vangogh_BASE_IDX      0
 127 #define RLC_PG_DELAY_3__CGCG_ACTIVE_BEFORE_CGPG_MASK_Vangogh   0x0000FFFFL
 128
 129 #define mmCP_HYP_PFP_UCODE_ADDR                 0x5814
 130 #define mmCP_HYP_PFP_UCODE_ADDR_BASE_IDX        1
 131 #define mmCP_HYP_PFP_UCODE_DATA                 0x5815
 132 #define mmCP_HYP_PFP_UCODE_DATA_BASE_IDX        1
 133 #define mmCP_HYP_CE_UCODE_ADDR                  0x5818
 134 #define mmCP_HYP_CE_UCODE_ADDR_BASE_IDX         1
 135 #define mmCP_HYP_CE_UCODE_DATA                  0x5819
 136 #define mmCP_HYP_CE_UCODE_DATA_BASE_IDX         1
 137 #define mmCP_HYP_ME_UCODE_ADDR                  0x5816
 138 #define mmCP_HYP_ME_UCODE_ADDR_BASE_IDX         1
 139 #define mmCP_HYP_ME_UCODE_DATA                  0x5817
 140 #define mmCP_HYP_ME_UCODE_DATA_BASE_IDX         1
 141
 142 #define mmCPG_PSP_DEBUG                         0x5c10
 143 #define mmCPG_PSP_DEBUG_BASE_IDX                1
 144 #define mmCPC_PSP_DEBUG                         0x5c11
 145 #define mmCPC_PSP_DEBUG_BASE_IDX                1
 146 #define CPC_PSP_DEBUG__GPA_OVERRIDE_MASK        0x00000008L
 147 #define CPG_PSP_DEBUG__GPA_OVERRIDE_MASK        0x00000008L
 148
 149 //CC_GC_SA_UNIT_DISABLE
 150 #define mmCC_GC_SA_UNIT_DISABLE                 0x0fe9
 151 #define mmCC_GC_SA_UNIT_DISABLE_BASE_IDX        0
 152 #define CC_GC_SA_UNIT_DISABLE__SA_DISABLE__SHIFT        0x8
 153 #define CC_GC_SA_UNIT_DISABLE__SA_DISABLE_MASK          0x0000FF00L
 154 //GC_USER_SA_UNIT_DISABLE
 155 #define mmGC_USER_SA_UNIT_DISABLE               0x0fea
 156 #define mmGC_USER_SA_UNIT_DISABLE_BASE_IDX      0
 157 #define GC_USER_SA_UNIT_DISABLE__SA_DISABLE__SHIFT      0x8
 158 #define GC_USER_SA_UNIT_DISABLE__SA_DISABLE_MASK        0x0000FF00L
 159 //PA_SC_ENHANCE_3
 160 #define mmPA_SC_ENHANCE_3                       0x1085
 161 #define mmPA_SC_ENHANCE_3_BASE_IDX              0
 162 #define PA_SC_ENHANCE_3__FORCE_PBB_WORKLOAD_MODE_TO_ZERO__SHIFT 0x3
 163 #define PA_SC_ENHANCE_3__FORCE_PBB_WORKLOAD_MODE_TO_ZERO_MASK   0x00000008L
 164
 165 #define mmCGTT_SPI_CS_CLK_CTRL                  0x507c
 166 #define mmCGTT_SPI_CS_CLK_CTRL_BASE_IDX         1
 167
 168 #define mmGCUTCL2_CGTT_CLK_CTRL_Sienna_Cichlid          0x16f3
 169 #define mmGCUTCL2_CGTT_CLK_CTRL_Sienna_Cichlid_BASE_IDX 0
 170 #define mmGCVM_L2_CGTT_CLK_CTRL_Sienna_Cichlid          0x15db
 171 #define mmGCVM_L2_CGTT_CLK_CTRL_Sienna_Cichlid_BASE_IDX 0
 172
 173 #define mmGC_THROTTLE_CTRL_Sienna_Cichlid              0x2030
 174 #define mmGC_THROTTLE_CTRL_Sienna_Cichlid_BASE_IDX     0
 175
 176 #define GFX_RLCG_GC_WRITE_OLD   (0x8 << 28)
 177 #define GFX_RLCG_GC_WRITE       (0x0 << 28)
 178 #define GFX_RLCG_GC_READ        (0x1 << 28)
 179 #define GFX_RLCG_MMHUB_WRITE    (0x2 << 28)
 180
 181 MODULE_FIRMWARE("amdgpu/navi10_ce.bin");
 182 MODULE_FIRMWARE("amdgpu/navi10_pfp.bin");
 183 MODULE_FIRMWARE("amdgpu/navi10_me.bin");
 184 MODULE_FIRMWARE("amdgpu/navi10_mec.bin");
 185 MODULE_FIRMWARE("amdgpu/navi10_mec2.bin");
 186 MODULE_FIRMWARE("amdgpu/navi10_rlc.bin");
 187
 188 MODULE_FIRMWARE("amdgpu/navi14_ce_wks.bin");
 189 MODULE_FIRMWARE("amdgpu/navi14_pfp_wks.bin");
 190 MODULE_FIRMWARE("amdgpu/navi14_me_wks.bin");
 191 MODULE_FIRMWARE("amdgpu/navi14_mec_wks.bin");
 192 MODULE_FIRMWARE("amdgpu/navi14_mec2_wks.bin");
 193 MODULE_FIRMWARE("amdgpu/navi14_ce.bin");
 194 MODULE_FIRMWARE("amdgpu/navi14_pfp.bin");
 195 MODULE_FIRMWARE("amdgpu/navi14_me.bin");
 196 MODULE_FIRMWARE("amdgpu/navi14_mec.bin");
 197 MODULE_FIRMWARE("amdgpu/navi14_mec2.bin");
 198 MODULE_FIRMWARE("amdgpu/navi14_rlc.bin");
 199
 200 MODULE_FIRMWARE("amdgpu/navi12_ce.bin");
 201 MODULE_FIRMWARE("amdgpu/navi12_pfp.bin");
 202 MODULE_FIRMWARE("amdgpu/navi12_me.bin");
 203 MODULE_FIRMWARE("amdgpu/navi12_mec.bin");
 204 MODULE_FIRMWARE("amdgpu/navi12_mec2.bin");
 205 MODULE_FIRMWARE("amdgpu/navi12_rlc.bin");
 206
 207 MODULE_FIRMWARE("amdgpu/sienna_cichlid_ce.bin");
 208 MODULE_FIRMWARE("amdgpu/sienna_cichlid_pfp.bin");
 209 MODULE_FIRMWARE("amdgpu/sienna_cichlid_me.bin");
 210 MODULE_FIRMWARE("amdgpu/sienna_cichlid_mec.bin");
 211 MODULE_FIRMWARE("amdgpu/sienna_cichlid_mec2.bin");
 212 MODULE_FIRMWARE("amdgpu/sienna_cichlid_rlc.bin");
 213
 214 MODULE_FIRMWARE("amdgpu/navy_flounder_ce.bin");
 215 MODULE_FIRMWARE("amdgpu/navy_flounder_pfp.bin");
 216 MODULE_FIRMWARE("amdgpu/navy_flounder_me.bin");
 217 MODULE_FIRMWARE("amdgpu/navy_flounder_mec.bin");
 218 MODULE_FIRMWARE("amdgpu/navy_flounder_mec2.bin");
 219 MODULE_FIRMWARE("amdgpu/navy_flounder_rlc.bin");
 220
 221 MODULE_FIRMWARE("amdgpu/vangogh_ce.bin");
 222 MODULE_FIRMWARE("amdgpu/vangogh_pfp.bin");
 223 MODULE_FIRMWARE("amdgpu/vangogh_me.bin");
 224 MODULE_FIRMWARE("amdgpu/vangogh_mec.bin");
 225 MODULE_FIRMWARE("amdgpu/vangogh_mec2.bin");
 226 MODULE_FIRMWARE("amdgpu/vangogh_rlc.bin");
 227
 228 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_ce.bin");
 229 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_pfp.bin");
 230 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_me.bin");
 231 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_mec.bin");
 232 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_mec2.bin");
 233 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_rlc.bin");
 234
 235 MODULE_FIRMWARE("amdgpu/beige_goby_ce.bin");
 236 MODULE_FIRMWARE("amdgpu/beige_goby_pfp.bin");
 237 MODULE_FIRMWARE("amdgpu/beige_goby_me.bin");
 238 MODULE_FIRMWARE("amdgpu/beige_goby_mec.bin");
 239 MODULE_FIRMWARE("amdgpu/beige_goby_mec2.bin");
 240 MODULE_FIRMWARE("amdgpu/beige_goby_rlc.bin");
 241
 242 static const struct soc15_reg_golden golden_settings_gc_10_1[] =
 243 {
 244         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0xffffffff, 0x00400014),
 245         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_CPF_CLK_CTRL, 0xfcff8fff, 0xf8000100),
 246         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xcd000000, 0x0d000100),
 247         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQ_CLK_CTRL, 0x60000ff0, 0x60000100),
 248         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQG_CLK_CTRL, 0x40000000, 0x40000100),
 249         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xffff8fff, 0xffff8100),
 250         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_WD_CLK_CTRL, 0xfeff8fff, 0xfeff8100),
 251         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
 252         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_VC5_ENABLE, 0x00000002, 0x00000000),
 253         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0x000007ff, 0x000005ff),
 254         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG, 0x20000000, 0x20000000),
 255         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xffffffff, 0x00000420),
 256         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0x00000200, 0x00000200),
 257         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0x07900000, 0x04900000),
 258         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DFSM_TILES_IN_FLIGHT, 0x0000ffff, 0x0000003f),
 259         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_LAST_OF_BURST_CONFIG, 0xffffffff, 0x03860204),
 260         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff0ffff, 0x00000500),
 261         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PRIV_CONTROL, 0x000007ff, 0x000001fe),
 262         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
 263         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x10321032),
 264         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x02310231),
 265         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
 266         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
 267         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CGTT_SCLK_CTRL, 0x10000000, 0x10000100),
 268         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL2, 0xffffffff, 0x1402002f),
 269         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xffff9fff, 0x00001188),
 270         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
 271         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x08000009),
 272         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0x00400000, 0x04440000),
 273         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0x00000800, 0x00000820),
 274         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000),
 275         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0xffffffff, 0xffff3101),
 276         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0x001f0000, 0x00070104),
 277         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ALU_CLK_CTRL, 0xffffffff, 0xffffffff),
 278         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x00000100, 0x00000130),
 279         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0xffffffff, 0xffffffff),
 280         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
 281         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CNTL, 0x60000010, 0x479c0010),
 282         SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CGTT_CLK_CTRL, 0xfeff0fff, 0x40000100),
 283         SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0x00c00000, 0x00c00000)
 284 };
 285
 286 static const struct soc15_reg_golden golden_settings_gc_10_0_nv10[] =
 287 {
 288         /* Pending on emulation bring up */
 289 };
 290
 291 static const struct soc15_reg_golden golden_settings_gc_rlc_spm_10_0_nv10[] =
 292 {
 293         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xe0000000, 0x0),
 294         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 295         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
 296         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 297         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
 298         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 299         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
 300         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 301         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
 302         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 303         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
 304         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 305         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
 306         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 307         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
 308         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 309         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 310         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 311         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8),
 312         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 313         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
 314         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 315         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc),
 316         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 317         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
 318         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 319         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0),
 320         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 321         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
 322         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 323         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4),
 324         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 325         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
 326         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 327         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
 328         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 329         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
 330         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 331         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
 332         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 333         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
 334         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 335         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
 336         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 337         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
 338         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 339         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
 340         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 341         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
 342         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 343         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
 344         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 345         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
 346         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 347         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
 348         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 349         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
 350         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 351         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
 352         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 353         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
 354         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 355         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
 356         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 357         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
 358         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 359         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
 360         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 361         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
 362         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 363         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0),
 364         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 365         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
 366         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 367         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4),
 368         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 369         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
 370         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 371         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8),
 372         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 373         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 374         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 375         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc),
 376         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 377         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
 378         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 379         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0),
 380         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 381         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 382         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 383         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4),
 384         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 385         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 386         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 387         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90),
 388         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 389         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
 390         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 391         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94),
 392         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 393         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
 394         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 395         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98),
 396         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 397         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
 398         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 399         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c),
 400         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 401         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
 402         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 403         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0),
 404         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 405         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
 406         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 407         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4),
 408         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 409         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
 410         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 411         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8),
 412         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 413         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
 414         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 415         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac),
 416         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 417         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
 418         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 419         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
 420         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 421         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
 422         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 423         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
 424         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 425         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
 426         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 427         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
 428         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 429         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
 430         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 431         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
 432         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 433         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
 434         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 435         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
 436         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 437         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
 438         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 439         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
 440         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 441         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 442         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 443         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
 444         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 445         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
 446         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 447         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
 448         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 449         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
 450         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 451         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
 452         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 453         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
 454         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 455         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
 456         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 457         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
 458         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 459         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
 460         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 461         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
 462         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 463         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
 464         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 465         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
 466         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 467         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
 468         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 469         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
 470         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 471         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
 472         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 473         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
 474         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 475         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
 476         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 477         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
 478         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 479         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
 480         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 481         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
 482         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 483         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
 484         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 485         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
 486         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 487         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
 488         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 489         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
 490         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 491         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
 492         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 493         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
 494         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 495         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
 496         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 497         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
 498         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 499         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
 500         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 501         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
 502         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 503         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
 504         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 505         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
 506         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 507         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
 508         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 509         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
 510         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 511         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c),
 512         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 513         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
 514         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 515         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
 516         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 517         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 518         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 519         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
 520         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 521         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
 522         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 523         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
 524         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 525         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
 526         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 527         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
 528         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 529         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
 530         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 531         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
 532         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 533         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
 534         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 535         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
 536         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 537         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 538         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 539         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
 540         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 541         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 542         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 543         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
 544         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 545         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
 546         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 547         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
 548         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 549         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
 550         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 551         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
 552         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 553         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 554         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 555         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
 556         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 557         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 558         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 559         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
 560         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 561         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
 562         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 563         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
 564         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 565         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
 566         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 567         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
 568         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 569         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 570         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 571         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
 572         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 573         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 574         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 575         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
 576         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 577         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
 578         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 579         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
 580         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 581         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
 582         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 583         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
 584         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 585         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
 586         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 587         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
 588         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 589         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
 590         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 591         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
 592         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 593         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 594         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 595         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
 596         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 597         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 598         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 599         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
 600         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 601         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 602         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 603         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
 604         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 605         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 606         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 607         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
 608         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 609         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 610         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 611         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
 612         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 613         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 614         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 615         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
 616         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 617         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 618         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 619         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
 620         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 621         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 622         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 623         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
 624         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 625         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
 626         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 627         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
 628         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 629         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
 630         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 631         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
 632         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 633         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
 634         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 635         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
 636         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 637         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
 638         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 639         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
 640         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 641         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
 642         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 643         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
 644         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 645         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
 646         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 647         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
 648         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 649         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
 650         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 651         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
 652         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 653         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
 654         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 655         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
 656         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 657         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
 658         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 659         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
 660         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 661         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
 662         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 663         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
 664         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 665         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17),
 666         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 667         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
 668         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 669         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17),
 670         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 671         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
 672         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 673         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 674         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 675         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
 676         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 677         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 678         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 679         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
 680         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 681         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
 682         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 683         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
 684         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 685         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
 686         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 687         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
 688         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 689         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
 690         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 691         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
 692         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 693         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
 694         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 695         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
 696         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 697         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 698         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 699         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
 700         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 701         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 702         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 703         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
 704         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 705         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 706         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 707         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
 708         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 709         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 710         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 711         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
 712         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 713         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
 714         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 715         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
 716         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 717         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
 718         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 719         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
 720         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 721         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
 722         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 723         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
 724         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 725         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
 726         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 727         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
 728         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 729         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 730         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 731         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
 732         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 733         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 734         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 735         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
 736         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 737         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 738         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 739         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
 740         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 741         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 742         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 743         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
 744         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 745         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 746         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 747         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
 748         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 749         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 750         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 751         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
 752         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 753         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 754         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 755         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
 756         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 757         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 758         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 759         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
 760         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 761         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 762         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 763         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
 764         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 765         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 766         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 767         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90),
 768         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 769         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
 770         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 771         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90),
 772         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 773         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
 774         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 775         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94),
 776         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 777         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
 778         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 779         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94),
 780         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 781         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
 782         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 783         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0),
 784         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 785         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
 786         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 787         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0),
 788         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 789         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
 790         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 791         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4),
 792         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 793         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
 794         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 795         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4),
 796         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 797         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
 798         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 799         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98),
 800         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 801         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
 802         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 803         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98),
 804         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 805         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
 806         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 807         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c),
 808         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 809         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
 810         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 811         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c),
 812         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 813         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
 814         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 815         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8),
 816         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 817         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 818         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 819         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8),
 820         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 821         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 822         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 823         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac),
 824         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 825         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 826         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 827         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac),
 828         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 829         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 830         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 831         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8),
 832         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 833         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
 834         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 835         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8),
 836         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 837         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
 838         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 839         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc),
 840         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 841         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
 842         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 843         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc),
 844         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 845         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
 846         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 847         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0),
 848         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 849         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 850         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 851         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0),
 852         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 853         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 854         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 855         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4),
 856         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 857         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 858         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 859         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4),
 860         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 861         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 862         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 863         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0),
 864         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 865         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
 866         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 867         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0),
 868         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 869         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
 870         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 871         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4),
 872         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 873         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 874         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 875         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4),
 876         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 877         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 878         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 879         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0),
 880         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 881         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
 882         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 883         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0),
 884         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 885         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
 886         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 887         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4),
 888         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 889         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
 890         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 891         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4),
 892         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 893         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
 894         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 895         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8),
 896         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 897         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
 898         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 899         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8),
 900         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 901         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
 902         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 903         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc),
 904         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 905         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
 906         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 907         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc),
 908         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 909         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
 910         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 911         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8),
 912         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 913         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 914         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 915         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8),
 916         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 917         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 918         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 919         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec),
 920         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 921         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 922         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 923         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec),
 924         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 925         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 926         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 927         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0),
 928         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 929         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
 930         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 931         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0),
 932         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 933         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
 934         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 935         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4),
 936         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 937         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
 938         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 939         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4),
 940         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 941         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
 942         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 943         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8),
 944         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 945         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 946         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 947         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8),
 948         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 949         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 950         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 951         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xfc),
 952         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 953         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 954         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 955         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xfc),
 956         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 957         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 958         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 959         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100),
 960         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 961         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 962         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 963         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100),
 964         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 965         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 966         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 967         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104),
 968         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 969         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
 970         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 971         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104),
 972         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 973         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
 974         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 975         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0),
 976         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 977         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
 978         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 979         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0),
 980         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 981         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
 982         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 983         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118),
 984         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 985         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
 986         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 987         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118),
 988         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 989         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
 990         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 991         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c),
 992         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 993         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
 994         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 995         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c),
 996         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 997         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
 998         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 999         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120),
1000         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1001         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
1002         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1003         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120),
1004         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1005         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
1006         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1007         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124),
1008         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1009         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
1010         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1011         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124),
1012         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1013         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
1014         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1015         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc),
1016         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1017         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
1018         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1019         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc),
1020         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1021         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
1022         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1023         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110),
1024         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1025         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1026         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1027         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110),
1028         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1029         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1030         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1031         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114),
1032         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1033         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1034         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1035         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114),
1036         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1037         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1038         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1039         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108),
1040         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1041         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1042         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1043         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108),
1044         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1045         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1046         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1047         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c),
1048         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1049         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1050         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1051         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c),
1052         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1053         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1054         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1055         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8),
1056         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1057         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17),
1058         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1059         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8),
1060         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1061         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17),
1062         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1063         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128),
1064         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1065         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
1066         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1067         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128),
1068         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1069         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
1070         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1071         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c),
1072         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1073         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1074         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1075         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c),
1076         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1077         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1078         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1079         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138),
1080         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1081         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1082         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1083         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138),
1084         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1085         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1086         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1087         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c),
1088         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1089         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1090         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1091         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c),
1092         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1093         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1094         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1095         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130),
1096         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1097         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1098         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1099         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130),
1100         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1101         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1102         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1103         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134),
1104         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1105         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1106         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1107         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134),
1108         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1109         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1110         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1111         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140),
1112         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1113         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1114         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1115         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140),
1116         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1117         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1118         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1119         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144),
1120         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1121         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
1122         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1123         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144),
1124         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1125         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
1126         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1127         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150),
1128         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1129         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1130         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1131         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150),
1132         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1133         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1134         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1135         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154),
1136         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1137         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
1138         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1139         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154),
1140         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1141         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
1142         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1143         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148),
1144         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1145         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1146         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1147         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148),
1148         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1149         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1150         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1151         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c),
1152         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1153         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
1154         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1155         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c),
1156         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1157         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
1158         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1159         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158),
1160         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1161         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
1162         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1163         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158),
1164         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1165         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
1166         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1167         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c),
1168         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1169         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1170         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1171         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c),
1172         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1173         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1174         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1175         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168),
1176         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1177         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1),
1178         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1179         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168),
1180         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1181         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1),
1182         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1183         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c),
1184         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1185         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
1186         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1187         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c),
1188         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1189         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
1190         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1191         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160),
1192         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1193         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
1194         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1195         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160),
1196         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1197         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
1198         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1199         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164),
1200         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1201         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1202         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1203         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164),
1204         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1205         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1206         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1207         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170),
1208         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1209         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
1210         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1211         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170),
1212         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1213         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
1214         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1215         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174),
1216         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1217         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
1218         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1219         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174),
1220         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1221         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
1222         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1223         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180),
1224         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1225         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
1226         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1227         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180),
1228         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1229         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
1230         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1231         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184),
1232         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1233         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1234         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1235         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184),
1236         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1237         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1238         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1239         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178),
1240         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1241         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
1242         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1243         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178),
1244         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1245         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
1246         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1247         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c),
1248         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1249         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
1250         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1251         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c),
1252         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1253         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
1254         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1255         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188),
1256         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1257         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1258         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1259         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188),
1260         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1261         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1262         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1263         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c),
1264         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1265         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
1266         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1267         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c),
1268         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1269         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
1270         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1271         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198),
1272         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1273         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
1274         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1275         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198),
1276         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1277         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
1278         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1279         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c),
1280         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1281         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
1282         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1283         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c),
1284         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1285         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
1286         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1287         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190),
1288         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1289         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1290         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1291         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190),
1292         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1293         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1294         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1295         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194),
1296         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1297         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
1298         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1299         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194),
1300         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1301         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
1302         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1303         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
1304         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1305         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
1306         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1307         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
1308         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1309         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1310         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1311         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
1312         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1313         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
1314         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1315         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
1316         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1317         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
1318         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1319         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
1320         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1321         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1f),
1322         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1323         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
1324         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1325         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1f),
1326         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1327         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
1328         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1329         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
1330         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1331         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_SAMPLE_SKEW, 0x000000FF, 0x19),
1332         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1333         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_MUXSEL_SKEW, 0x000000FF, 0x20),
1334         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1335         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0x5),
1336         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1337         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0xa),
1338         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1339         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x14),
1340         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1341         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x19),
1342         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1343         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_DESER_START_SKEW, 0x000000FF, 0x33),
1344         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xFFFFFFFF, 0xe0000000)
1345 };
1346
1347 static const struct soc15_reg_golden golden_settings_gc_10_1_1[] =
1348 {
1349         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0xffffffff, 0x003c0014),
1350         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_GS_NGG_CLK_CTRL, 0xffff8fff, 0xffff8100),
1351         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_IA_CLK_CTRL, 0xffff0fff, 0xffff0100),
1352         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xcd000000, 0x0d000100),
1353         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQ_CLK_CTRL, 0xf8ff0fff, 0x60000100),
1354         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQG_CLK_CTRL, 0x40000ff0, 0x40000100),
1355         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xffff8fff, 0xffff8100),
1356         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_WD_CLK_CTRL, 0xffff8fff, 0xffff8100),
1357         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
1358         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_VC5_ENABLE, 0x00000002, 0x00000000),
1359         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0x800007ff, 0x000005ff),
1360         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG, 0xffffffff, 0x20000000),
1361         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xffffffff, 0x00000420),
1362         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0x00000200, 0x00000200),
1363         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x04900000),
1364         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DFSM_TILES_IN_FLIGHT, 0x0000ffff, 0x0000003f),
1365         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_LAST_OF_BURST_CONFIG, 0xffffffff, 0x03860204),
1366         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff0ffff, 0x00000500),
1367         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PRIV_CONTROL, 0x000007ff, 0x000001fe),
1368         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
1369         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffe7),
1370         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffe7),
1371         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CGTT_SCLK_CTRL, 0xffff0fff, 0x10000100),
1372         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL2, 0xffffffff, 0x1402002f),
1373         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xffffbfff, 0x00000188),
1374         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
1375         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x08000009),
1376         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0x00400000, 0x04440000),
1377         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0x00000800, 0x00000820),
1378         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000),
1379         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0xffffffff, 0xffff3101),
1380         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0x001f0000, 0x00070105),
1381         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ALU_CLK_CTRL, 0xffffffff, 0xffffffff),
1382         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x00000133, 0x00000130),
1383         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0xffffffff, 0xffffffff),
1384         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
1385         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CNTL, 0x60000010, 0x479c0010),
1386         SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0x00c00000, 0x00c00000),
1387 };
1388
1389 static const struct soc15_reg_golden golden_settings_gc_10_1_2[] =
1390 {
1391         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0x003e001f, 0x003c0014),
1392         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_GS_NGG_CLK_CTRL, 0xffff8fff, 0xffff8100),
1393         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_IA_CLK_CTRL, 0xffff0fff, 0xffff0100),
1394         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xff7f0fff, 0x0d000100),
1395         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQ_CLK_CTRL, 0xffffcfff, 0x60000100),
1396         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQG_CLK_CTRL, 0xffff0fff, 0x40000100),
1397         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xffff8fff, 0xffff8100),
1398         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_WD_CLK_CTRL, 0xffff8fff, 0xffff8100),
1399         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
1400         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_VC5_ENABLE, 0x00000003, 0x00000000),
1401         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0x800007ff, 0x000005ff),
1402         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG, 0xffffffff, 0x20000000),
1403         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xffffffff, 0x00000420),
1404         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000200),
1405         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x04800000),
1406         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DFSM_TILES_IN_FLIGHT, 0x0000ffff, 0x0000003f),
1407         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_LAST_OF_BURST_CONFIG, 0xffffffff, 0x03860204),
1408         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff0ffff, 0x00000500),
1409         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PRIV_CONTROL, 0x00007fff, 0x000001fe),
1410         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
1411         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x10321032),
1412         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x02310231),
1413         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
1414         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
1415         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CGTT_SCLK_CTRL, 0xffff0fff, 0x10000100),
1416         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL2, 0xffffffff, 0x1402002f),
1417         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xffffbfff, 0x00000188),
1418         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_0, 0xffffffff, 0x842a4c02),
1419         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
1420         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x08000009),
1421         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0xffffffff, 0x04440000),
1422         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0x00000820, 0x00000820),
1423         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000),
1424         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0xffffffff, 0xffff3101),
1425         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ALU_CLK_CTRL, 0xffffffff, 0xffffffff),
1426         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x00000133, 0x00000130),
1427         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0xffffffff, 0xffffffff),
1428         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
1429         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CNTL, 0xffdf80ff, 0x479c0010),
1430         SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffffffff, 0x00800000)
1431 };
1432
1433 static bool gfx_v10_is_rlcg_rw(struct amdgpu_device *adev, u32 offset, uint32_t *flag, bool write)
1434 {
1435         /* always programed by rlcg, only for gc */
1436         if (offset == SOC15_REG_OFFSET(GC, 0, mmRLC_CSIB_ADDR_HI) ||
1437             offset == SOC15_REG_OFFSET(GC, 0, mmRLC_CSIB_ADDR_LO) ||
1438             offset == SOC15_REG_OFFSET(GC, 0, mmRLC_CSIB_LENGTH) ||
1439             offset == SOC15_REG_OFFSET(GC, 0, mmGRBM_GFX_CNTL) ||
1440             offset == SOC15_REG_OFFSET(GC, 0, mmGRBM_GFX_INDEX) ||
1441             offset == SOC15_REG_OFFSET(GC, 0, mmCP_ME_CNTL)) {
1442                 if (!amdgpu_sriov_reg_indirect_gc(adev))
1443                         *flag = GFX_RLCG_GC_WRITE_OLD;
1444                 else
1445                         *flag = write ? GFX_RLCG_GC_WRITE : GFX_RLCG_GC_READ;
1446
1447                 return true;
1448         }
1449
1450         /* currently support gc read/write, mmhub write */
1451         if (offset >= SOC15_REG_OFFSET(GC, 0, mmSDMA0_DEC_START) &&
1452             offset <= SOC15_REG_OFFSET(GC, 0, mmRLC_GTS_OFFSET_MSB)) {
1453                 if (amdgpu_sriov_reg_indirect_gc(adev))
1454                         *flag = write ? GFX_RLCG_GC_WRITE : GFX_RLCG_GC_READ;
1455                 else
1456                         return false;
1457         } else {
1458                 if (amdgpu_sriov_reg_indirect_mmhub(adev))
1459                         *flag = GFX_RLCG_MMHUB_WRITE;
1460                 else
1461                         return false;
1462         }
1463
1464         return true;
1465 }
1466
1467 static u32 gfx_v10_rlcg_rw(struct amdgpu_device *adev, u32 offset, u32 v, uint32_t flag)
1468 {
1469         static void *scratch_reg0;
1470         static void *scratch_reg1;
1471         static void *scratch_reg2;
1472         static void *scratch_reg3;
1473         static void *spare_int;
1474         static uint32_t grbm_cntl;
1475         static uint32_t grbm_idx;
1476         uint32_t i = 0;
1477         uint32_t retries = 50000;
1478         u32 ret = 0;
1479
1480         scratch_reg0 = adev->rmmio +
1481                        (adev->reg_offset[GC_HWIP][0][mmSCRATCH_REG0_BASE_IDX] + mmSCRATCH_REG0) * 4;
1482         scratch_reg1 = adev->rmmio +
1483                        (adev->reg_offset[GC_HWIP][0][mmSCRATCH_REG1_BASE_IDX] + mmSCRATCH_REG1) * 4;
1484         scratch_reg2 = adev->rmmio +
1485                        (adev->reg_offset[GC_HWIP][0][mmSCRATCH_REG0_BASE_IDX] + mmSCRATCH_REG2) * 4;
1486         scratch_reg3 = adev->rmmio +
1487                        (adev->reg_offset[GC_HWIP][0][mmSCRATCH_REG1_BASE_IDX] + mmSCRATCH_REG3) * 4;
1488         spare_int = adev->rmmio +
1489                     (adev->reg_offset[GC_HWIP][0][mmRLC_SPARE_INT_BASE_IDX] + mmRLC_SPARE_INT) * 4;
1490
1491         grbm_cntl = adev->reg_offset[GC_HWIP][0][mmGRBM_GFX_CNTL_BASE_IDX] + mmGRBM_GFX_CNTL;
1492         grbm_idx = adev->reg_offset[GC_HWIP][0][mmGRBM_GFX_INDEX_BASE_IDX] + mmGRBM_GFX_INDEX;
1493
1494         if (offset == grbm_cntl || offset == grbm_idx) {
1495                 if (offset  == grbm_cntl)
1496                         writel(v, scratch_reg2);
1497                 else if (offset == grbm_idx)
1498                         writel(v, scratch_reg3);
1499
1500                 writel(v, ((void __iomem *)adev->rmmio) + (offset * 4));
1501         } else {
1502                 writel(v, scratch_reg0);
1503                 writel(offset | flag, scratch_reg1);
1504                 writel(1, spare_int);
1505                 for (i = 0; i < retries; i++) {
1506                         u32 tmp;
1507
1508                         tmp = readl(scratch_reg1);
1509                         if (!(tmp & flag))
1510                                 break;
1511
1512                         udelay(10);
1513                 }
1514
1515                 if (i >= retries)
1516                         pr_err("timeout: rlcg program reg:0x%05x failed !\n", offset);
1517         }
1518
1519         ret = readl(scratch_reg0);
1520
1521         return ret;
1522 }
1523
1524 static void gfx_v10_rlcg_wreg(struct amdgpu_device *adev, u32 offset, u32 value, u32 flag)
1525 {
1526         uint32_t rlcg_flag;
1527
1528         if (amdgpu_sriov_fullaccess(adev) &&
1529             gfx_v10_is_rlcg_rw(adev, offset, &rlcg_flag, 1)) {
1530                 gfx_v10_rlcg_rw(adev, offset, value, rlcg_flag);
1531
1532                 return;
1533         }
1534         if (flag & AMDGPU_REGS_NO_KIQ)
1535                 WREG32_NO_KIQ(offset, value);
1536         else
1537                 WREG32(offset, value);
1538 }
1539
1540 static u32 gfx_v10_rlcg_rreg(struct amdgpu_device *adev, u32 offset, u32 flag)
1541 {
1542         uint32_t rlcg_flag;
1543
1544         if (amdgpu_sriov_fullaccess(adev) &&
1545             gfx_v10_is_rlcg_rw(adev, offset, &rlcg_flag, 0))
1546                 return gfx_v10_rlcg_rw(adev, offset, 0, rlcg_flag);
1547
1548         if (flag & AMDGPU_REGS_NO_KIQ)
1549                 return RREG32_NO_KIQ(offset);
1550         else
1551                 return RREG32(offset);
1552
1553         return 0;
1554 }
1555
1556 static const struct soc15_reg_golden golden_settings_gc_10_1_nv14[] =
1557 {
1558         /* Pending on emulation bring up */
1559 };
1560
1561 static const struct soc15_reg_golden golden_settings_gc_rlc_spm_10_1_nv14[] =
1562 {
1563         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xE0000000L, 0x0),
1564         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1565         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
1566         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1567         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1568         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1569         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
1570         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1571         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
1572         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1573         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
1574         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1575         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
1576         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1577         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
1578         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1579         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1580         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1581         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
1582         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1583         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1584         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1585         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
1586         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1587         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1588         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1589         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
1590         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1591         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1592         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1593         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
1594         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1595         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1596         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1597         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
1598         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1599         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1600         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1601         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
1602         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1603         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1604         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1605         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
1606         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1607         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1608         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1609         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
1610         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1611         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1612         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1613         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
1614         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1615         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20),
1616         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1617         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
1618         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1619         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
1620         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1621         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
1622         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1623         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1624         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1625         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
1626         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1627         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1628         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1629         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
1630         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1631         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1632         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1633         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
1634         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1635         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1636         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1637         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
1638         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1639         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1640         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1641         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
1642         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1643         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
1644         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1645         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
1646         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1647         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1648         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1649         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
1650         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1651         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1652         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1653         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
1654         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1655         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1656         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1657         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
1658         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1659         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1660         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1661         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
1662         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1663         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
1664         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1665         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
1666         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1667         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
1668         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1669         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
1670         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1671         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
1672         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1673         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
1674         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1675         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
1676         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1677         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
1678         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1679         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
1680         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1681         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
1682         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1683         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
1684         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1685         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
1686         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1687         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
1688         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1689         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
1690         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1691         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
1692         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1693         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
1694         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1695         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
1696         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1697         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
1698         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1699         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
1700         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1701         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c),
1702         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1703         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1704         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1705         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
1706         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1707         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1708         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1709         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
1710         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1711         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1712         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1713         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
1714         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1715         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1716         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1717         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
1718         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1719         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1720         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1721         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
1722         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1723         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
1724         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1725         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
1726         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1727         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1728         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1729         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
1730         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1731         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1732         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1733         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
1734         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1735         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
1736         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1737         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
1738         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1739         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
1740         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1741         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
1742         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1743         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
1744         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1745         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
1746         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1747         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e),
1748         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1749         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
1750         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1751         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e),
1752         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1753         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
1754         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1755         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e),
1756         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1757         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
1758         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1759         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e),
1760         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1761         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
1762         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1763         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20),
1764         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1765         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
1766         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1767         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
1768         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1769         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
1770         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1771         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
1772         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1773         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
1774         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1775         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e),
1776         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1777         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
1778         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1779         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e),
1780         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1781         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
1782         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1783         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
1784         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1785         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
1786         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1787         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1788         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1789         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
1790         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1791         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1792         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1793         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
1794         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1795         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1796         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1797         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
1798         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1799         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1800         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1801         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
1802         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1803         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1804         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1805         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
1806         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1807         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1808         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1809         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
1810         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1811         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1812         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1813         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
1814         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1815         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1816         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1817         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
1818         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1819         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1820         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1821         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
1822         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1823         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1824         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1825         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
1826         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1827         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1828         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1829         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
1830         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1831         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1832         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1833         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90),
1834         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1835         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1836         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1837         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94),
1838         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1839         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
1840         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1841         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0),
1842         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1843         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1844         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1845         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4),
1846         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1847         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1848         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1849         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98),
1850         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1851         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1852         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1853         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c),
1854         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1855         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
1856         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1857         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8),
1858         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1859         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
1860         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1861         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac),
1862         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1863         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1864         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1865         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8),
1866         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1867         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1868         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1869         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc),
1870         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1871         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1872         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1873         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0),
1874         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1875         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
1876         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1877         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4),
1878         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1879         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1880         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1881         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0),
1882         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1883         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1884         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1885         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4),
1886         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1887         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1888         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1889         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0),
1890         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1891         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1892         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1893         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4),
1894         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1895         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1896         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1897         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8),
1898         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1899         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1900         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1901         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc),
1902         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1903         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1904         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1905         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8),
1906         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1907         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1908         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1909         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc),
1910         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1911         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1912         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1913         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8),
1914         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1915         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1916         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1917         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec),
1918         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1919         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1920         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1921         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0),
1922         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1923         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1924         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1925         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe4),
1926         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1927         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1928         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1929         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100),
1930         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1931         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1932         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1933         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104),
1934         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1935         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1936         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1937         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108),
1938         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1939         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1940         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1941         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c),
1942         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1943         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1944         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1945         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110),
1946         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1947         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1948         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1949         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114),
1950         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1951         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1952         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1953         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118),
1954         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1955         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1956         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1957         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c),
1958         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1959         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1960         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1961         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8),
1962         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1963         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17),
1964         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1965         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130),
1966         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1967         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1968         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1969         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134),
1970         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1971         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1972         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1973         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138),
1974         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1975         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1976         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1977         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c),
1978         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1979         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1980         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1981         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4),
1982         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1983         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20),
1984         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1985         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128),
1986         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1987         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1988         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1989         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c),
1990         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1991         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1992         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1993         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120),
1994         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1995         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1996         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1997         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124),
1998         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1999         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
2000         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2001         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0),
2002         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2003         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2004         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2005         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140),
2006         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2007         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2008         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2009         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144),
2010         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2011         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
2012         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2013         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150),
2014         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2015         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2016         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2017         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154),
2018         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2019         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2020         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2021         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148),
2022         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2023         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2024         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2025         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c),
2026         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2027         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
2028         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2029         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158),
2030         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2031         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
2032         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2033         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c),
2034         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2035         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2036         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2037         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168),
2038         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2039         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2040         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2041         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c),
2042         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2043         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
2044         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2045         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160),
2046         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2047         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
2048         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2049         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164),
2050         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2051         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2052         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2053         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170),
2054         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2055         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2056         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2057         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174),
2058         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2059         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
2060         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2061         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180),
2062         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2063         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
2064         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2065         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184),
2066         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2067         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
2068         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2069         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178),
2070         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2071         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2072         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2073         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c),
2074         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2075         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
2076         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2077         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188),
2078         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2079         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
2080         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2081         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c),
2082         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2083         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2084         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2085         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198),
2086         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2087         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2088         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2089         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c),
2090         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2091         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2092         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2093         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190),
2094         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2095         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
2096         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2097         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194),
2098         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2099         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2100         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2101         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1a0),
2102         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2103         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2104         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2105         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1a4),
2106         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2107         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
2108         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2109         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1b0),
2110         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2111         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2112         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2113         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1b4),
2114         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2115         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2116         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2117         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1a8),
2118         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2119         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2120         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2121         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1ac),
2122         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2123         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
2124         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2125         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1b8),
2126         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2127         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
2128         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2129         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1bc),
2130         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2131         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2132         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2133         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c8),
2134         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2135         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
2136         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2137         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1cc),
2138         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2139         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
2140         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2141         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c0),
2142         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2143         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
2144         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2145         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c4),
2146         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2147         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2148         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2149         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
2150         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2151         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2152         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2153         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
2154         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2155         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2156         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2157         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
2158         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2159         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20),
2160         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2161         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
2162         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2163         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20),
2164         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2165         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
2166         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2167         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
2168         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2169         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_SAMPLE_SKEW, 0x000000FF, 0x26),
2170         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2171         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_MUXSEL_SKEW, 0x000000FF, 0x28),
2172         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2173         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0xf),
2174         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2175         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0x15),
2176         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2177         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x1f),
2178         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2179         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x25),
2180         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2181         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_DESER_START_SKEW, 0x000000FF, 0x3b),
2182         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xFFFFFFFF, 0xe0000000)
2183 };
2184
2185 static const struct soc15_reg_golden golden_settings_gc_10_1_2_nv12[] =
2186 {
2187         /* Pending on emulation bring up */
2188 };
2189
2190 static const struct soc15_reg_golden golden_settings_gc_rlc_spm_10_1_2_nv12[] =
2191 {
2192         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xe0000000L, 0x0),
2193         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2194         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
2195         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2196         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
2197         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2198         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
2199         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2200         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
2201         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2202         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
2203         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2204         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
2205         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2206         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
2207         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2208         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
2209         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2210         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8),
2211         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2212         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2213         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2214         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc),
2215         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2216         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2217         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2218         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0),
2219         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2220         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2221         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2222         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4),
2223         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2224         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2225         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2226         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
2227         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2228         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2229         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2230         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
2231         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2232         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2233         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2234         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
2235         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2236         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2237         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2238         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
2239         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2240         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2241         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2242         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
2243         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2244         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2245         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2246         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
2247         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2248         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2249         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2250         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
2251         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2252         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2253         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2254         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
2255         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2256         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
2257         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2258         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
2259         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2260         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
2261         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2262         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0),
2263         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2264         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
2265         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2266         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4),
2267         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2268         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
2269         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2270         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8),
2271         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2272         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2273         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2274         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc),
2275         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2276         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2277         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2278         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0),
2279         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2280         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2281         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2282         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4),
2283         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2284         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2285         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2286         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90),
2287         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2288         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
2289         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2290         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94),
2291         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2292         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1),
2293         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2294         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98),
2295         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2296         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
2297         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2298         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c),
2299         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2300         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2301         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2302         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0),
2303         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2304         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1),
2305         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2306         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4),
2307         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2308         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2309         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2310         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8),
2311         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2312         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2313         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2314         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac),
2315         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2316         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2317         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2318         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
2319         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2320         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
2321         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2322         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
2323         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2324         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2325         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2326         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
2327         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2328         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
2329         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2330         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
2331         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2332         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2333         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2334         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
2335         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2336         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2337         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2338         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
2339         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2340         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2341         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2342         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
2343         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2344         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
2345         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2346         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
2347         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2348         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2349         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2350         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
2351         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2352         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2353         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2354         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
2355         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2356         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
2357         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2358         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
2359         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2360         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2361         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2362         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
2363         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2364         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
2365         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2366         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
2367         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2368         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
2369         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2370         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
2371         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2372         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2373         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2374         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
2375         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2376         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2377         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2378         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
2379         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2380         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2381         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2382         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
2383         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2384         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
2385         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2386         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
2387         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2388         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2389         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2390         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
2391         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2392         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2393         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2394         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
2395         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2396         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2397         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2398         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
2399         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2400         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2401         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2402         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
2403         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2404         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2405         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2406         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
2407         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2408         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
2409         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2410         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c),
2411         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2412         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
2413         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2414         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
2415         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2416         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2417         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2418         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
2419         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2420         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
2421         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2422         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
2423         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2424         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
2425         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2426         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
2427         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2428         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2429         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2430         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
2431         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2432         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2433         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2434         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
2435         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2436         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2437         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2438         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
2439         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2440         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2441         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2442         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
2443         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2444         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2445         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2446         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
2447         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2448         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2449         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2450         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
2451         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2452         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
2453         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2454         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
2455         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2456         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
2457         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2458         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
2459         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2460         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2461         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2462         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
2463         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2464         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2465         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2466         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
2467         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2468         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
2469         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2470         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
2471         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2472         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
2473         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2474         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
2475         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2476         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2477         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2478         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
2479         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2480         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2481         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2482         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
2483         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2484         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
2485         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2486         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
2487         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2488         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
2489         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2490         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
2491         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2492         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2493         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2494         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
2495         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2496         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2497         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2498         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
2499         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2500         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2501         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2502         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
2503         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2504         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2505         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2506         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
2507         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2508         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2509         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2510         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
2511         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2512         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2513         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2514         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
2515         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2516         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2517         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2518         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
2519         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2520         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2521         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2522         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
2523         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2524         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2525         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2526         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
2527         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2528         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2529         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2530         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
2531         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2532         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2533         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2534         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
2535         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2536         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2537         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2538         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
2539         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2540         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2541         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2542         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
2543         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2544         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2545         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2546         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
2547         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2548         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2549         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2550         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
2551         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2552         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2553         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2554         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
2555         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2556         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2557         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2558         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
2559         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2560         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2561         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2562         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
2563         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2564         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
2565         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2566         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
2567         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2568         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
2569         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2570         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
2571         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2572         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2573         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2574         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
2575         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2576         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2577         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2578         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
2579         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2580         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
2581         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2582         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
2583         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2584         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
2585         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2586         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
2587         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2588         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
2589         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2590         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
2591         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2592         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
2593         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2594         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
2595         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2596         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2597         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2598         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
2599         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2600         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2601         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2602         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
2603         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2604         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2605         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2606         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
2607         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2608         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2609         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2610         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
2611         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2612         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
2613         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2614         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
2615         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2616         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
2617         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2618         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
2619         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2620         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2621         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2622         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
2623         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2624         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2625         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2626         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
2627         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2628         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2629         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2630         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
2631         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2632         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2633         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2634         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
2635         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2636         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2637         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2638         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
2639         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2640         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2641         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2642         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
2643         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2644         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2645         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2646         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
2647         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2648         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2649         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2650         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
2651         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2652         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2653         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2654         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
2655         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2656         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2657         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2658         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
2659         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2660         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2661         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2662         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
2663         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2664         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2665         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2666         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90),
2667         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2668         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
2669         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2670         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90),
2671         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2672         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
2673         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2674         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94),
2675         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2676         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2677         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2678         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94),
2679         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2680         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2681         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2682         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0),
2683         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2684         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2685         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2686         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0),
2687         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2688         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2689         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2690         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4),
2691         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2692         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2693         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2694         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4),
2695         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2696         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2697         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2698         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98),
2699         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2700         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
2701         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2702         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98),
2703         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2704         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
2705         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2706         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c),
2707         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2708         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2709         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2710         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c),
2711         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2712         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2713         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2714         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8),
2715         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2716         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2717         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2718         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8),
2719         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2720         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2721         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2722         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac),
2723         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2724         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2725         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2726         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac),
2727         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2728         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2729         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2730         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8),
2731         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2732         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2733         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2734         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8),
2735         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2736         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2737         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2738         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc),
2739         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2740         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2741         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2742         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc),
2743         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2744         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2745         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2746         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0),
2747         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2748         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2749         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2750         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0),
2751         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2752         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2753         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2754         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4),
2755         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2756         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2757         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2758         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4),
2759         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2760         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2761         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2762         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0),
2763         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2764         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2765         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2766         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0),
2767         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2768         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2769         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2770         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4),
2771         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2772         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2773         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2774         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4),
2775         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2776         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2777         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2778         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0),
2779         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2780         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2781         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2782         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0),
2783         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2784         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2785         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2786         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4),
2787         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2788         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2789         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2790         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4),
2791         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2792         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2793         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2794         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8),
2795         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2796         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2797         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2798         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8),
2799         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2800         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2801         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2802         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc),
2803         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2804         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2805         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2806         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc),
2807         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2808         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2809         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2810         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8),
2811         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2812         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2813         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2814         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8),
2815         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2816         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2817         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2818         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec),
2819         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2820         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
2821         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2822         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec),
2823         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2824         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
2825         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2826         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0),
2827         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2828         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2829         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2830         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0),
2831         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2832         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2833         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2834         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4),
2835         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2836         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2837         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2838         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4),
2839         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2840         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2841         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2842         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8),
2843         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2844         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2845         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2846         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8),
2847         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2848         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2849         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2850         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xfc),
2851         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2852         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17),
2853         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2854         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xfc),
2855         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2856         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17),
2857         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2858         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100),
2859         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2860         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
2861         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2862         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100),
2863         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2864         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
2865         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2866         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104),
2867         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2868         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2869         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2870         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104),
2871         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2872         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2873         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2874         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0),
2875         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2876         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2877         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2878         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0),
2879         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2880         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2881         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2882         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118),
2883         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2884         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2885         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2886         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118),
2887         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2888         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2889         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2890         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c),
2891         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2892         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2893         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2894         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c),
2895         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2896         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2897         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2898         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120),
2899         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2900         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2901         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2902         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120),
2903         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2904         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2905         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2906         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124),
2907         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2908         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2909         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2910         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124),
2911         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2912         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2913         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2914         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc),
2915         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2916         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2917         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2918         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc),
2919         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2920         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2921         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2922         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110),
2923         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2924         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2925         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2926         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110),
2927         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2928         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2929         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2930         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114),
2931         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2932         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2933         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2934         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114),
2935         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2936         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2937         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2938         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108),
2939         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2940         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2941         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2942         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108),
2943         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2944         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2945         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2946         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c),
2947         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2948         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2949         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2950         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c),
2951         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2952         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2953         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2954         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8),
2955         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2956         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
2957         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2958         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8),
2959         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2960         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
2961         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2962         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128),
2963         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2964         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2965         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2966         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128),
2967         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2968         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2969         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2970         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c),
2971         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2972         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2973         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2974         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c),
2975         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2976         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2977         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2978         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138),
2979         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2980         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2981         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2982         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138),
2983         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2984         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2985         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2986         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c),
2987         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2988         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2989         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2990         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c),
2991         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2992         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2993         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2994         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130),
2995         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2996         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2997         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2998         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130),
2999         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3000         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
3001         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3002         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134),
3003         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3004         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
3005         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3006         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134),
3007         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3008         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
3009         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3010         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140),
3011         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3012         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3013         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3014         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140),
3015         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3016         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3017         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3018         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144),
3019         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3020         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
3021         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3022         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144),
3023         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3024         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
3025         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3026         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150),
3027         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3028         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3029         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3030         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150),
3031         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3032         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3033         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3034         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154),
3035         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3036         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
3037         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3038         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154),
3039         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3040         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
3041         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3042         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148),
3043         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3044         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3045         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3046         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148),
3047         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3048         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3049         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3050         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c),
3051         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3052         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
3053         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3054         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c),
3055         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3056         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
3057         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3058         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158),
3059         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3060         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
3061         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3062         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158),
3063         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3064         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
3065         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3066         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c),
3067         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3068         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
3069         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3070         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c),
3071         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3072         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
3073         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3074         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168),
3075         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3076         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
3077         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3078         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168),
3079         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3080         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
3081         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3082         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c),
3083         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3084         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
3085         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3086         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c),
3087         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3088         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
3089         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3090         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160),
3091         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3092         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
3093         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3094         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160),
3095         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3096         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
3097         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3098         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164),
3099         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3100         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
3101         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3102         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164),
3103         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3104         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
3105         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3106         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170),
3107         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3108         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
3109         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3110         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170),
3111         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3112         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
3113         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3114         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174),
3115         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3116         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3117         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3118         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174),
3119         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3120         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3121         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3122         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180),
3123         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3124         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
3125         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3126         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180),
3127         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3128         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
3129         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3130         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184),
3131         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3132         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3133         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3134         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184),
3135         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3136         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3137         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3138         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178),
3139         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3140         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
3141         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3142         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178),
3143         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3144         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
3145         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3146         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c),
3147         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3148         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3149         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3150         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c),
3151         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3152         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3153         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3154         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188),
3155         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3156         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3157         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3158         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188),
3159         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3160         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3161         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3162         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c),
3163         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3164         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
3165         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3166         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c),
3167         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3168         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
3169         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3170         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198),
3171         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3172         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
3173         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3174         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198),
3175         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3176         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
3177         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3178         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c),
3179         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3180         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
3181         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3182         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c),
3183         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3184         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
3185         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3186         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190),
3187         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3188         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3189         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3190         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190),
3191         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3192         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3193         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3194         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194),
3195         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3196         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
3197         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3198         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194),
3199         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3200         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
3201         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3202         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
3203         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3204         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
3205         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3206         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
3207         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3208         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
3209         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3210         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
3211         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3212         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
3213         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3214         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
3215         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3216         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
3217         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3218         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
3219         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3220         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1f),
3221         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3222         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
3223         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3224         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1f),
3225         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3226         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
3227         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3228         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
3229         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3230         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_SAMPLE_SKEW, 0x000000FF, 0x1f),
3231         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3232         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_MUXSEL_SKEW, 0x000000FF, 0x22),
3233         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3234         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0x1),
3235         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3236         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0x6),
3237         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3238         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x10),
3239         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3240         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x15),
3241         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3242         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_DESER_START_SKEW, 0x000000FF, 0x35),
3243         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xFFFFFFFF, 0xe0000000)
3244 };
3245
3246 static const struct soc15_reg_golden golden_settings_gc_10_3[] =
3247 {
3248         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0x78000000, 0x78000100),
3249         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_PS_CLK_CTRL, 0xff7f0fff, 0x78000100),
3250         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA0_CLK_CTRL, 0xff7f0fff, 0x30000100),
3251         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA1_CLK_CTRL, 0xff7f0fff, 0x7e000100),
3252         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c000),
3253         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000280),
3254         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000),
3255         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_EXCEPTION_CONTROL, 0x7fff0f1f, 0x00b80000),
3256         SOC15_REG_GOLDEN_VALUE(GC, 0 ,mmGCEA_SDP_TAG_RESERVE0, 0xffffffff, 0x10100100),
3257         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCEA_SDP_TAG_RESERVE1, 0xffffffff, 0x17000088),
3258         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Sienna_Cichlid, 0x1ff1ffff, 0x00000500),
3259         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCUTCL2_CGTT_CLK_CTRL_Sienna_Cichlid, 0xff000000, 0xff008080),
3260         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCVM_L2_CGTT_CLK_CTRL_Sienna_Cichlid, 0xff000000, 0xff008080),
3261         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PC_CNTL, 0x003fffff, 0x00280400),
3262         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
3263         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
3264         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008),
3265         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x10f80988),
3266         SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG,  0x00000020, 0x00000020),
3267         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007),
3268         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
3269         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0xffffffbf, 0x00000820),
3270         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0xffffffff, 0x00070104),
3271         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_CONFIG, 0xe07df47f, 0x00180070),
3272         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER0_SELECT, 0xf0f001ff, 0x00000000),
3273         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER1_SELECT, 0xf0f001ff, 0x00000000),
3274         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER10_SELECT, 0xf0f001ff, 0x00000000),
3275         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER11_SELECT, 0xf0f001ff, 0x00000000),
3276         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER12_SELECT, 0xf0f001ff, 0x00000000),
3277         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER13_SELECT, 0xf0f001ff, 0x00000000),
3278         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER14_SELECT, 0xf0f001ff, 0x00000000),
3279         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER15_SELECT, 0xf0f001ff, 0x00000000),
3280         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER2_SELECT, 0xf0f001ff, 0x00000000),
3281         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER3_SELECT, 0xf0f001ff, 0x00000000),
3282         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER4_SELECT, 0xf0f001ff, 0x00000000),
3283         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER5_SELECT, 0xf0f001ff, 0x00000000),
3284         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER6_SELECT, 0xf0f001ff, 0x00000000),
3285         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER7_SELECT, 0xf0f001ff, 0x00000000),
3286         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER8_SELECT, 0xf0f001ff, 0x00000000),
3287         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER9_SELECT, 0xf0f001ff, 0x00000000),
3288         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
3289         SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffbfffff, 0x00a00000)
3290 };
3291
3292 static const struct soc15_reg_golden golden_settings_gc_10_3_sienna_cichlid[] =
3293 {
3294         /* Pending on emulation bring up */
3295 };
3296
3297 static const struct soc15_reg_golden golden_settings_gc_10_3_2[] =
3298 {
3299         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0xff7f0fff, 0x78000100),
3300         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_PS_CLK_CTRL, 0xff7f0fff, 0x78000100),
3301         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA0_CLK_CTRL, 0xff7f0fff, 0x30000100),
3302         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA1_CLK_CTRL, 0xff7f0fff, 0x7e000100),
3303         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c000),
3304         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000280),
3305         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000),
3306         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_EXCEPTION_CONTROL, 0x7fff0f1f, 0x00b80000),
3307         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Sienna_Cichlid, 0x1ff1ffff, 0x00000500),
3308         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCUTCL2_CGTT_CLK_CTRL_Sienna_Cichlid, 0xffffffff, 0xff008080),
3309         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCVM_L2_CGTT_CLK_CTRL_Sienna_Cichlid, 0xffff8fff, 0xff008080),
3310         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PC_CNTL, 0x003fffff, 0x00280400),
3311         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
3312         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
3313         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008),
3314         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x00f80988),
3315         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007),
3316         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
3317         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0xffffffbf, 0x00000820),
3318         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0xffffffff, 0x00070104),
3319         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_START_PHASE, 0x000000ff, 0x00000004),
3320         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_CONFIG, 0xe07df47f, 0x00180070),
3321         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER0_SELECT, 0xf0f001ff, 0x00000000),
3322         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER1_SELECT, 0xf0f001ff, 0x00000000),
3323         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER10_SELECT, 0xf0f001ff, 0x00000000),
3324         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER11_SELECT, 0xf0f001ff, 0x00000000),
3325         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER12_SELECT, 0xf0f001ff, 0x00000000),
3326         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER13_SELECT, 0xf0f001ff, 0x00000000),
3327         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER14_SELECT, 0xf0f001ff, 0x00000000),
3328         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER15_SELECT, 0xf0f001ff, 0x00000000),
3329         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER2_SELECT, 0xf0f001ff, 0x00000000),
3330         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER3_SELECT, 0xf0f001ff, 0x00000000),
3331         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER4_SELECT, 0xf0f001ff, 0x00000000),
3332         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER5_SELECT, 0xf0f001ff, 0x00000000),
3333         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER6_SELECT, 0xf0f001ff, 0x00000000),
3334         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER7_SELECT, 0xf0f001ff, 0x00000000),
3335         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER8_SELECT, 0xf0f001ff, 0x00000000),
3336         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER9_SELECT, 0xf0f001ff, 0x00000000),
3337         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
3338         SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffbfffff, 0x00a00000),
3339         SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_GS_MAX_WAVE_ID, 0x00000fff, 0x000003ff),
3340
3341         /* This is not in GDB yet. Don't remove it. It fixes a GPU hang on Navy Flounder. */
3342         SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG,  0x00000020, 0x00000020),
3343 };
3344
3345 static const struct soc15_reg_golden golden_settings_gc_10_3_vangogh[] =
3346 {
3347         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA0_CLK_CTRL, 0xff7f0fff, 0x30000100),
3348         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA1_CLK_CTRL, 0xff7f0fff, 0x7e000100),
3349         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0x000000ff, 0x000000e4),
3350         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000200),
3351         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000),
3352         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_EXCEPTION_CONTROL, 0x7fff0f1f, 0x00b80000),
3353         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0x0c1807ff, 0x00000142),
3354         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Vangogh, 0x1ff1ffff, 0x00000500),
3355         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0x000000ff, 0x000000e4),
3356         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x32103210),
3357         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x32103210),
3358         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xfffffff3),
3359         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xfffffff3),
3360         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008),
3361         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x00f80988),
3362         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007),
3363         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
3364         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0xffffffbf, 0x00000020),
3365         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1_Vangogh, 0xffffffff, 0x00070103),
3366         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQG_CONFIG, 0x000017ff, 0x00001000),
3367         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
3368         SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffffffff, 0x00400000),
3369         SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_GS_MAX_WAVE_ID, 0x00000fff, 0x000000ff),
3370
3371         /* This is not in GDB yet. Don't remove it. It fixes a GPU hang on VanGogh. */
3372         SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG,  0x00000020, 0x00000020),
3373 };
3374
3375 static const struct soc15_reg_golden golden_settings_gc_10_3_4[] =
3376 {
3377         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0x78000000, 0x78000100),
3378         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA0_CLK_CTRL, 0x30000000, 0x30000100),
3379         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA1_CLK_CTRL, 0x7e000000, 0x7e000100),
3380         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c000),
3381         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0x00000280, 0x00000280),
3382         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0x07800000, 0x00800000),
3383         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Sienna_Cichlid, 0x00001d00, 0x00000500),
3384         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PC_CNTL, 0x003c0000, 0x00280400),
3385         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
3386         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
3387         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0x40000000, 0x580f1008),
3388         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0x00040000, 0x00f80988),
3389         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0x01000000, 0x01200007),
3390         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
3391         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0x00000800, 0x00000820),
3392         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_CONFIG, 0x0000001f, 0x00180070),
3393         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER0_SELECT, 0xf0f001ff, 0x00000000),
3394         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER1_SELECT, 0xf0f001ff, 0x00000000),
3395         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER10_SELECT, 0xf0f001ff, 0x00000000),
3396         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER11_SELECT, 0xf0f001ff, 0x00000000),
3397         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER12_SELECT, 0xf0f001ff, 0x00000000),
3398         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER13_SELECT, 0xf0f001ff, 0x00000000),
3399         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER14_SELECT, 0xf0f001ff, 0x00000000),
3400         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER15_SELECT, 0xf0f001ff, 0x00000000),
3401         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER2_SELECT, 0xf0f001ff, 0x00000000),
3402         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER3_SELECT, 0xf0f001ff, 0x00000000),
3403         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER4_SELECT, 0xf0f001ff, 0x00000000),
3404         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER5_SELECT, 0xf0f001ff, 0x00000000),
3405         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER6_SELECT, 0xf0f001ff, 0x00000000),
3406         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER7_SELECT, 0xf0f001ff, 0x00000000),
3407         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER8_SELECT, 0xf0f001ff, 0x00000000),
3408         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER9_SELECT, 0xf0f001ff, 0x00000000),
3409         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0x01030000, 0x01030000),
3410         SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0x03a00000, 0x00a00000),
3411         SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG,  0x00000020, 0x00000020)
3412 };
3413
3414 static const struct soc15_reg_golden golden_settings_gc_10_3_5[] = {
3415         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0x78000000, 0x78000100),
3416         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c000),
3417         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000280),
3418         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000),
3419         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff1ffff, 0x00000500),
3420         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
3421         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
3422         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008),
3423         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x00f80988),
3424         SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG, 0x000001ff, 0x00000020),
3425         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007),
3426         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_CONFIG, 0xe07df47f, 0x00180070),
3427         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER0_SELECT, 0xf0f001ff, 0x00000000),
3428         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER1_SELECT, 0xf0f001ff, 0x00000000),
3429         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER10_SELECT, 0xf0f001ff, 0x00000000),
3430         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER11_SELECT, 0xf0f001ff, 0x00000000),
3431         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER12_SELECT, 0xf0f001ff, 0x00000000),
3432         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER13_SELECT, 0xf0f001ff, 0x00000000),
3433         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER14_SELECT, 0xf0f001ff, 0x00000000),
3434         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER15_SELECT, 0xf0f001ff, 0x00000000),
3435         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER2_SELECT, 0xf0f001ff, 0x00000000),
3436         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER3_SELECT, 0xf0f001ff, 0x00000000),
3437         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER4_SELECT, 0xf0f001ff, 0x00000000),
3438         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER5_SELECT, 0xf0f001ff, 0x00000000),
3439         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER6_SELECT, 0xf0f001ff, 0x00000000),
3440         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER7_SELECT, 0xf0f001ff, 0x00000000),
3441         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER8_SELECT, 0xf0f001ff, 0x00000000),
3442         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER9_SELECT, 0xf0f001ff, 0x00000000),
3443         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX,0xfff7ffff, 0x01030000),
3444         SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffbfffff, 0x00a00000)
3445 };
3446
3447 #define DEFAULT_SH_MEM_CONFIG \
3448         ((SH_MEM_ADDRESS_MODE_64 << SH_MEM_CONFIG__ADDRESS_MODE__SHIFT) | \
3449          (SH_MEM_ALIGNMENT_MODE_UNALIGNED << SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT) | \
3450          (SH_MEM_RETRY_MODE_ALL << SH_MEM_CONFIG__RETRY_MODE__SHIFT) | \
3451          (3 << SH_MEM_CONFIG__INITIAL_INST_PREFETCH__SHIFT))
3452
3453
3454 static void gfx_v10_0_set_ring_funcs(struct amdgpu_device *adev);
3455 static void gfx_v10_0_set_irq_funcs(struct amdgpu_device *adev);
3456 static void gfx_v10_0_set_gds_init(struct amdgpu_device *adev);
3457 static void gfx_v10_0_set_rlc_funcs(struct amdgpu_device *adev);
3458 static int gfx_v10_0_get_cu_info(struct amdgpu_device *adev,
3459                                  struct amdgpu_cu_info *cu_info);
3460 static uint64_t gfx_v10_0_get_gpu_clock_counter(struct amdgpu_device *adev);
3461 static void gfx_v10_0_select_se_sh(struct amdgpu_device *adev, u32 se_num,
3462                                    u32 sh_num, u32 instance);
3463 static u32 gfx_v10_0_get_wgp_active_bitmap_per_sh(struct amdgpu_device *adev);
3464
3465 static int gfx_v10_0_rlc_backdoor_autoload_buffer_init(struct amdgpu_device *adev);
3466 static void gfx_v10_0_rlc_backdoor_autoload_buffer_fini(struct amdgpu_device *adev);
3467 static int gfx_v10_0_rlc_backdoor_autoload_enable(struct amdgpu_device *adev);
3468 static int gfx_v10_0_wait_for_rlc_autoload_complete(struct amdgpu_device *adev);
3469 static void gfx_v10_0_ring_emit_ce_meta(struct amdgpu_ring *ring, bool resume);
3470 static void gfx_v10_0_ring_emit_de_meta(struct amdgpu_ring *ring, bool resume);
3471 static void gfx_v10_0_ring_emit_frame_cntl(struct amdgpu_ring *ring, bool start, bool secure);
3472 static u32 gfx_v10_3_get_disabled_sa(struct amdgpu_device *adev);
3473 static void gfx_v10_3_program_pbb_mode(struct amdgpu_device *adev);
3474 static void gfx_v10_3_set_power_brake_sequence(struct amdgpu_device *adev);
3475
3476 static void gfx10_kiq_set_resources(struct amdgpu_ring *kiq_ring, uint64_t queue_mask)
3477 {
3478         amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_RESOURCES, 6));
3479         amdgpu_ring_write(kiq_ring, PACKET3_SET_RESOURCES_VMID_MASK(0) |
3480                           PACKET3_SET_RESOURCES_QUEUE_TYPE(0)); /* vmid_mask:0 queue_type:0 (KIQ) */
3481         amdgpu_ring_write(kiq_ring, lower_32_bits(queue_mask)); /* queue mask lo */
3482         amdgpu_ring_write(kiq_ring, upper_32_bits(queue_mask)); /* queue mask hi */
3483         amdgpu_ring_write(kiq_ring, 0); /* gws mask lo */
3484         amdgpu_ring_write(kiq_ring, 0); /* gws mask hi */
3485         amdgpu_ring_write(kiq_ring, 0); /* oac mask */
3486         amdgpu_ring_write(kiq_ring, 0); /* gds heap base:0, gds heap size:0 */
3487 }
3488
3489 static void gfx10_kiq_map_queues(struct amdgpu_ring *kiq_ring,
3490                                  struct amdgpu_ring *ring)
3491 {
3492         struct amdgpu_device *adev = kiq_ring->adev;
3493         uint64_t mqd_addr = amdgpu_bo_gpu_offset(ring->mqd_obj);
3494         uint64_t wptr_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
3495         uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0;
3496
3497         amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5));
3498         /* Q_sel:0, vmid:0, vidmem: 1, engine:0, num_Q:1*/
3499         amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */
3500                           PACKET3_MAP_QUEUES_QUEUE_SEL(0) | /* Queue_Sel */
3501                           PACKET3_MAP_QUEUES_VMID(0) | /* VMID */
3502                           PACKET3_MAP_QUEUES_QUEUE(ring->queue) |
3503                           PACKET3_MAP_QUEUES_PIPE(ring->pipe) |
3504                           PACKET3_MAP_QUEUES_ME((ring->me == 1 ? 0 : 1)) |
3505                           PACKET3_MAP_QUEUES_QUEUE_TYPE(0) | /*queue_type: normal compute queue */
3506                           PACKET3_MAP_QUEUES_ALLOC_FORMAT(0) | /* alloc format: all_on_one_pipe */
3507                           PACKET3_MAP_QUEUES_ENGINE_SEL(eng_sel) |
3508                           PACKET3_MAP_QUEUES_NUM_QUEUES(1)); /* num_queues: must be 1 */
3509         amdgpu_ring_write(kiq_ring, PACKET3_MAP_QUEUES_DOORBELL_OFFSET(ring->doorbell_index));
3510         amdgpu_ring_write(kiq_ring, lower_32_bits(mqd_addr));
3511         amdgpu_ring_write(kiq_ring, upper_32_bits(mqd_addr));
3512         amdgpu_ring_write(kiq_ring, lower_32_bits(wptr_addr));
3513         amdgpu_ring_write(kiq_ring, upper_32_bits(wptr_addr));
3514 }
3515
3516 static void gfx10_kiq_unmap_queues(struct amdgpu_ring *kiq_ring,
3517                                    struct amdgpu_ring *ring,
3518                                    enum amdgpu_unmap_queues_action action,
3519                                    u64 gpu_addr, u64 seq)
3520 {
3521         uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0;
3522
3523         amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_UNMAP_QUEUES, 4));
3524         amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */
3525                           PACKET3_UNMAP_QUEUES_ACTION(action) |
3526                           PACKET3_UNMAP_QUEUES_QUEUE_SEL(0) |
3527                           PACKET3_UNMAP_QUEUES_ENGINE_SEL(eng_sel) |
3528                           PACKET3_UNMAP_QUEUES_NUM_QUEUES(1));
3529         amdgpu_ring_write(kiq_ring,
3530                   PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET0(ring->doorbell_index));
3531
3532         if (action == PREEMPT_QUEUES_NO_UNMAP) {
3533                 amdgpu_ring_write(kiq_ring, lower_32_bits(gpu_addr));
3534                 amdgpu_ring_write(kiq_ring, upper_32_bits(gpu_addr));
3535                 amdgpu_ring_write(kiq_ring, seq);
3536         } else {
3537                 amdgpu_ring_write(kiq_ring, 0);
3538                 amdgpu_ring_write(kiq_ring, 0);
3539                 amdgpu_ring_write(kiq_ring, 0);
3540         }
3541 }
3542
3543 static void gfx10_kiq_query_status(struct amdgpu_ring *kiq_ring,
3544                                    struct amdgpu_ring *ring,
3545                                    u64 addr,
3546                                    u64 seq)
3547 {
3548         uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0;
3549
3550         amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_QUERY_STATUS, 5));
3551         amdgpu_ring_write(kiq_ring,
3552                           PACKET3_QUERY_STATUS_CONTEXT_ID(0) |
3553                           PACKET3_QUERY_STATUS_INTERRUPT_SEL(0) |
3554                           PACKET3_QUERY_STATUS_COMMAND(2));
3555         amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */
3556                           PACKET3_QUERY_STATUS_DOORBELL_OFFSET(ring->doorbell_index) |
3557                           PACKET3_QUERY_STATUS_ENG_SEL(eng_sel));
3558         amdgpu_ring_write(kiq_ring, lower_32_bits(addr));
3559         amdgpu_ring_write(kiq_ring, upper_32_bits(addr));
3560         amdgpu_ring_write(kiq_ring, lower_32_bits(seq));
3561         amdgpu_ring_write(kiq_ring, upper_32_bits(seq));
3562 }
3563
3564 static void gfx10_kiq_invalidate_tlbs(struct amdgpu_ring *kiq_ring,
3565                                 uint16_t pasid, uint32_t flush_type,
3566                                 bool all_hub)
3567 {
3568         amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_INVALIDATE_TLBS, 0));
3569         amdgpu_ring_write(kiq_ring,
3570                         PACKET3_INVALIDATE_TLBS_DST_SEL(1) |
3571                         PACKET3_INVALIDATE_TLBS_ALL_HUB(all_hub) |
3572                         PACKET3_INVALIDATE_TLBS_PASID(pasid) |
3573                         PACKET3_INVALIDATE_TLBS_FLUSH_TYPE(flush_type));
3574 }
3575
3576 static const struct kiq_pm4_funcs gfx_v10_0_kiq_pm4_funcs = {
3577         .kiq_set_resources = gfx10_kiq_set_resources,
3578         .kiq_map_queues = gfx10_kiq_map_queues,
3579         .kiq_unmap_queues = gfx10_kiq_unmap_queues,
3580         .kiq_query_status = gfx10_kiq_query_status,
3581         .kiq_invalidate_tlbs = gfx10_kiq_invalidate_tlbs,
3582         .set_resources_size = 8,
3583         .map_queues_size = 7,
3584         .unmap_queues_size = 6,
3585         .query_status_size = 7,
3586         .invalidate_tlbs_size = 2,
3587 };
3588
3589 static void gfx_v10_0_set_kiq_pm4_funcs(struct amdgpu_device *adev)
3590 {
3591         adev->gfx.kiq.pmf = &gfx_v10_0_kiq_pm4_funcs;
3592 }
3593
3594 static void gfx_v10_0_init_spm_golden_registers(struct amdgpu_device *adev)
3595 {
3596         switch (adev->asic_type) {
3597         case CHIP_NAVI10:
3598                 soc15_program_register_sequence(adev,
3599                                                 golden_settings_gc_rlc_spm_10_0_nv10,
3600                                                 (const u32)ARRAY_SIZE(golden_settings_gc_rlc_spm_10_0_nv10));
3601                 break;
3602         case CHIP_NAVI14:
3603                 soc15_program_register_sequence(adev,
3604                                                 golden_settings_gc_rlc_spm_10_1_nv14,
3605                                                 (const u32)ARRAY_SIZE(golden_settings_gc_rlc_spm_10_1_nv14));
3606                 break;
3607         case CHIP_NAVI12:
3608                 soc15_program_register_sequence(adev,
3609                                                 golden_settings_gc_rlc_spm_10_1_2_nv12,
3610                                                 (const u32)ARRAY_SIZE(golden_settings_gc_rlc_spm_10_1_2_nv12));
3611                 break;
3612         default:
3613                 break;
3614         }
3615 }
3616
3617 static void gfx_v10_0_init_golden_registers(struct amdgpu_device *adev)
3618 {
3619         switch (adev->asic_type) {
3620         case CHIP_NAVI10:
3621                 soc15_program_register_sequence(adev,
3622                                                 golden_settings_gc_10_1,
3623                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_1));
3624                 soc15_program_register_sequence(adev,
3625                                                 golden_settings_gc_10_0_nv10,
3626                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_0_nv10));
3627                 break;
3628         case CHIP_NAVI14:
3629                 soc15_program_register_sequence(adev,
3630                                                 golden_settings_gc_10_1_1,
3631                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_1_1));
3632                 soc15_program_register_sequence(adev,
3633                                                 golden_settings_gc_10_1_nv14,
3634                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_1_nv14));
3635                 break;
3636         case CHIP_NAVI12:
3637                 soc15_program_register_sequence(adev,
3638                                                 golden_settings_gc_10_1_2,
3639                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_1_2));
3640                 soc15_program_register_sequence(adev,
3641                                                 golden_settings_gc_10_1_2_nv12,
3642                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_1_2_nv12));
3643                 break;
3644         case CHIP_SIENNA_CICHLID:
3645                 soc15_program_register_sequence(adev,
3646                                                 golden_settings_gc_10_3,
3647                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_3));
3648                 soc15_program_register_sequence(adev,
3649                                                 golden_settings_gc_10_3_sienna_cichlid,
3650                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_sienna_cichlid));
3651                 break;
3652         case CHIP_NAVY_FLOUNDER:
3653                 soc15_program_register_sequence(adev,
3654                                                 golden_settings_gc_10_3_2,
3655                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_2));
3656                 break;
3657         case CHIP_VANGOGH:
3658                 soc15_program_register_sequence(adev,
3659                                                 golden_settings_gc_10_3_vangogh,
3660                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_vangogh));
3661                 break;
3662         case CHIP_DIMGREY_CAVEFISH:
3663                 soc15_program_register_sequence(adev,
3664                                                 golden_settings_gc_10_3_4,
3665                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_4));
3666                 break;
3667         case CHIP_BEIGE_GOBY:
3668                 soc15_program_register_sequence(adev,
3669                                                 golden_settings_gc_10_3_5,
3670                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_5));
3671                 break;
3672         default:
3673                 break;
3674         }
3675         gfx_v10_0_init_spm_golden_registers(adev);
3676 }
3677
3678 static void gfx_v10_0_scratch_init(struct amdgpu_device *adev)
3679 {
3680         adev->gfx.scratch.num_reg = 8;
3681         adev->gfx.scratch.reg_base = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG0);
3682         adev->gfx.scratch.free_mask = (1u << adev->gfx.scratch.num_reg) - 1;
3683 }
3684
3685 static void gfx_v10_0_write_data_to_reg(struct amdgpu_ring *ring, int eng_sel,
3686                                        bool wc, uint32_t reg, uint32_t val)
3687 {
3688         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
3689         amdgpu_ring_write(ring, WRITE_DATA_ENGINE_SEL(eng_sel) |
3690                           WRITE_DATA_DST_SEL(0) | (wc ? WR_CONFIRM : 0));
3691         amdgpu_ring_write(ring, reg);
3692         amdgpu_ring_write(ring, 0);
3693         amdgpu_ring_write(ring, val);
3694 }
3695
3696 static void gfx_v10_0_wait_reg_mem(struct amdgpu_ring *ring, int eng_sel,
3697                                   int mem_space, int opt, uint32_t addr0,
3698                                   uint32_t addr1, uint32_t ref, uint32_t mask,
3699                                   uint32_t inv)
3700 {
3701         amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
3702         amdgpu_ring_write(ring,
3703                           /* memory (1) or register (0) */
3704                           (WAIT_REG_MEM_MEM_SPACE(mem_space) |
3705                            WAIT_REG_MEM_OPERATION(opt) | /* wait */
3706                            WAIT_REG_MEM_FUNCTION(3) |  /* equal */
3707                            WAIT_REG_MEM_ENGINE(eng_sel)));
3708
3709         if (mem_space)
3710                 BUG_ON(addr0 & 0x3); /* Dword align */
3711         amdgpu_ring_write(ring, addr0);
3712         amdgpu_ring_write(ring, addr1);
3713         amdgpu_ring_write(ring, ref);
3714         amdgpu_ring_write(ring, mask);
3715         amdgpu_ring_write(ring, inv); /* poll interval */
3716 }
3717
3718 static int gfx_v10_0_ring_test_ring(struct amdgpu_ring *ring)
3719 {
3720         struct amdgpu_device *adev = ring->adev;
3721         uint32_t scratch;
3722         uint32_t tmp = 0;
3723         unsigned i;
3724         int r;
3725
3726         r = amdgpu_gfx_scratch_get(adev, &scratch);
3727         if (r) {
3728                 DRM_ERROR("amdgpu: cp failed to get scratch reg (%d).\n", r);
3729                 return r;
3730         }
3731
3732         WREG32(scratch, 0xCAFEDEAD);
3733
3734         r = amdgpu_ring_alloc(ring, 3);
3735         if (r) {
3736                 DRM_ERROR("amdgpu: cp failed to lock ring %d (%d).\n",
3737                           ring->idx, r);
3738                 amdgpu_gfx_scratch_free(adev, scratch);
3739                 return r;
3740         }
3741
3742         amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1));
3743         amdgpu_ring_write(ring, (scratch - PACKET3_SET_UCONFIG_REG_START));
3744         amdgpu_ring_write(ring, 0xDEADBEEF);
3745         amdgpu_ring_commit(ring);
3746
3747         for (i = 0; i < adev->usec_timeout; i++) {
3748                 tmp = RREG32(scratch);
3749                 if (tmp == 0xDEADBEEF)
3750                         break;
3751                 if (amdgpu_emu_mode == 1)
3752                         msleep(1);
3753                 else
3754                         udelay(1);
3755         }
3756
3757         if (i >= adev->usec_timeout)
3758                 r = -ETIMEDOUT;
3759
3760         amdgpu_gfx_scratch_free(adev, scratch);
3761
3762         return r;
3763 }
3764
3765 static int gfx_v10_0_ring_test_ib(struct amdgpu_ring *ring, long timeout)
3766 {
3767         struct amdgpu_device *adev = ring->adev;
3768         struct amdgpu_ib ib;
3769         struct dma_fence *f = NULL;
3770         unsigned index;
3771         uint64_t gpu_addr;
3772         uint32_t tmp;
3773         long r;
3774
3775         r = amdgpu_device_wb_get(adev, &index);
3776         if (r)
3777                 return r;
3778
3779         gpu_addr = adev->wb.gpu_addr + (index * 4);
3780         adev->wb.wb[index] = cpu_to_le32(0xCAFEDEAD);
3781         memset(&ib, 0, sizeof(ib));
3782         r = amdgpu_ib_get(adev, NULL, 16,
3783                                         AMDGPU_IB_POOL_DIRECT, &ib);
3784         if (r)
3785                 goto err1;
3786
3787         ib.ptr[0] = PACKET3(PACKET3_WRITE_DATA, 3);
3788         ib.ptr[1] = WRITE_DATA_DST_SEL(5) | WR_CONFIRM;
3789         ib.ptr[2] = lower_32_bits(gpu_addr);
3790         ib.ptr[3] = upper_32_bits(gpu_addr);
3791         ib.ptr[4] = 0xDEADBEEF;
3792         ib.length_dw = 5;
3793
3794         r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
3795         if (r)
3796                 goto err2;
3797
3798         r = dma_fence_wait_timeout(f, false, timeout);
3799         if (r == 0) {
3800                 r = -ETIMEDOUT;
3801                 goto err2;
3802         } else if (r < 0) {
3803                 goto err2;
3804         }
3805
3806         tmp = adev->wb.wb[index];
3807         if (tmp == 0xDEADBEEF)
3808                 r = 0;
3809         else
3810                 r = -EINVAL;
3811 err2:
3812         amdgpu_ib_free(adev, &ib, NULL);
3813         dma_fence_put(f);
3814 err1:
3815         amdgpu_device_wb_free(adev, index);
3816         return r;
3817 }
3818
3819 static void gfx_v10_0_free_microcode(struct amdgpu_device *adev)
3820 {
3821         release_firmware(adev->gfx.pfp_fw);
3822         adev->gfx.pfp_fw = NULL;
3823         release_firmware(adev->gfx.me_fw);
3824         adev->gfx.me_fw = NULL;
3825         release_firmware(adev->gfx.ce_fw);
3826         adev->gfx.ce_fw = NULL;
3827         release_firmware(adev->gfx.rlc_fw);
3828         adev->gfx.rlc_fw = NULL;
3829         release_firmware(adev->gfx.mec_fw);
3830         adev->gfx.mec_fw = NULL;
3831         release_firmware(adev->gfx.mec2_fw);
3832         adev->gfx.mec2_fw = NULL;
3833
3834         kfree(adev->gfx.rlc.register_list_format);
3835 }
3836
3837 static void gfx_v10_0_check_fw_write_wait(struct amdgpu_device *adev)
3838 {
3839         adev->gfx.cp_fw_write_wait = false;
3840
3841         switch (adev->asic_type) {
3842         case CHIP_NAVI10:
3843         case CHIP_NAVI12:
3844         case CHIP_NAVI14:
3845                 if ((adev->gfx.me_fw_version >= 0x00000046) &&
3846                     (adev->gfx.me_feature_version >= 27) &&
3847                     (adev->gfx.pfp_fw_version >= 0x00000068) &&
3848                     (adev->gfx.pfp_feature_version >= 27) &&
3849                     (adev->gfx.mec_fw_version >= 0x0000005b) &&
3850                     (adev->gfx.mec_feature_version >= 27))
3851                         adev->gfx.cp_fw_write_wait = true;
3852                 break;
3853         case CHIP_SIENNA_CICHLID:
3854         case CHIP_NAVY_FLOUNDER:
3855         case CHIP_VANGOGH:
3856         case CHIP_DIMGREY_CAVEFISH:
3857         case CHIP_BEIGE_GOBY:
3858                 adev->gfx.cp_fw_write_wait = true;
3859                 break;
3860         default:
3861                 break;
3862         }
3863
3864         if (!adev->gfx.cp_fw_write_wait)
3865                 DRM_WARN_ONCE("CP firmware version too old, please update!");
3866 }
3867
3868
3869 static void gfx_v10_0_init_rlc_ext_microcode(struct amdgpu_device *adev)
3870 {
3871         const struct rlc_firmware_header_v2_1 *rlc_hdr;
3872
3873         rlc_hdr = (const struct rlc_firmware_header_v2_1 *)adev->gfx.rlc_fw->data;
3874         adev->gfx.rlc_srlc_fw_version = le32_to_cpu(rlc_hdr->save_restore_list_cntl_ucode_ver);
3875         adev->gfx.rlc_srlc_feature_version = le32_to_cpu(rlc_hdr->save_restore_list_cntl_feature_ver);
3876         adev->gfx.rlc.save_restore_list_cntl_size_bytes = le32_to_cpu(rlc_hdr->save_restore_list_cntl_size_bytes);
3877         adev->gfx.rlc.save_restore_list_cntl = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_list_cntl_offset_bytes);
3878         adev->gfx.rlc_srlg_fw_version = le32_to_cpu(rlc_hdr->save_restore_list_gpm_ucode_ver);
3879         adev->gfx.rlc_srlg_feature_version = le32_to_cpu(rlc_hdr->save_restore_list_gpm_feature_ver);
3880         adev->gfx.rlc.save_restore_list_gpm_size_bytes = le32_to_cpu(rlc_hdr->save_restore_list_gpm_size_bytes);
3881         adev->gfx.rlc.save_restore_list_gpm = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_list_gpm_offset_bytes);
3882         adev->gfx.rlc_srls_fw_version = le32_to_cpu(rlc_hdr->save_restore_list_srm_ucode_ver);
3883         adev->gfx.rlc_srls_feature_version = le32_to_cpu(rlc_hdr->save_restore_list_srm_feature_ver);
3884         adev->gfx.rlc.save_restore_list_srm_size_bytes = le32_to_cpu(rlc_hdr->save_restore_list_srm_size_bytes);
3885         adev->gfx.rlc.save_restore_list_srm = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_list_srm_offset_bytes);
3886         adev->gfx.rlc.reg_list_format_direct_reg_list_length =
3887                         le32_to_cpu(rlc_hdr->reg_list_format_direct_reg_list_length);
3888 }
3889
3890 static void gfx_v10_0_init_rlc_iram_dram_microcode(struct amdgpu_device *adev)
3891 {
3892         const struct rlc_firmware_header_v2_2 *rlc_hdr;
3893
3894         rlc_hdr = (const struct rlc_firmware_header_v2_2 *)adev->gfx.rlc_fw->data;
3895         adev->gfx.rlc.rlc_iram_ucode_size_bytes = le32_to_cpu(rlc_hdr->rlc_iram_ucode_size_bytes);
3896         adev->gfx.rlc.rlc_iram_ucode = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->rlc_iram_ucode_offset_bytes);
3897         adev->gfx.rlc.rlc_dram_ucode_size_bytes = le32_to_cpu(rlc_hdr->rlc_dram_ucode_size_bytes);
3898         adev->gfx.rlc.rlc_dram_ucode = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->rlc_dram_ucode_offset_bytes);
3899 }
3900
3901 static bool gfx_v10_0_navi10_gfxoff_should_enable(struct amdgpu_device *adev)
3902 {
3903         bool ret = false;
3904
3905         switch (adev->pdev->revision) {
3906         case 0xc2:
3907         case 0xc3:
3908                 ret = true;
3909                 break;
3910         default:
3911                 ret = false;
3912                 break;
3913         }
3914
3915         return ret ;
3916 }
3917
3918 static void gfx_v10_0_check_gfxoff_flag(struct amdgpu_device *adev)
3919 {
3920         switch (adev->asic_type) {
3921         case CHIP_NAVI10:
3922                 if (!gfx_v10_0_navi10_gfxoff_should_enable(adev))
3923                         adev->pm.pp_feature &= ~PP_GFXOFF_MASK;
3924                 break;
3925         default:
3926                 break;
3927         }
3928 }
3929
3930 static int gfx_v10_0_init_microcode(struct amdgpu_device *adev)
3931 {
3932         const char *chip_name;
3933         char fw_name[40];
3934         char wks[10];
3935         int err;
3936         struct amdgpu_firmware_info *info = NULL;
3937         const struct common_firmware_header *header = NULL;
3938         const struct gfx_firmware_header_v1_0 *cp_hdr;
3939         const struct rlc_firmware_header_v2_0 *rlc_hdr;
3940         unsigned int *tmp = NULL;
3941         unsigned int i = 0;
3942         uint16_t version_major;
3943         uint16_t version_minor;
3944
3945         DRM_DEBUG("\n");
3946
3947         memset(wks, 0, sizeof(wks));
3948         switch (adev->asic_type) {
3949         case CHIP_NAVI10:
3950                 chip_name = "navi10";
3951                 break;
3952         case CHIP_NAVI14:
3953                 chip_name = "navi14";
3954                 if (!(adev->pdev->device == 0x7340 &&
3955                       adev->pdev->revision != 0x00))
3956                         snprintf(wks, sizeof(wks), "_wks");
3957                 break;
3958         case CHIP_NAVI12:
3959                 chip_name = "navi12";
3960                 break;
3961         case CHIP_SIENNA_CICHLID:
3962                 chip_name = "sienna_cichlid";
3963                 break;
3964         case CHIP_NAVY_FLOUNDER:
3965                 chip_name = "navy_flounder";
3966                 break;
3967         case CHIP_VANGOGH:
3968                 chip_name = "vangogh";
3969                 break;
3970         case CHIP_DIMGREY_CAVEFISH:
3971                 chip_name = "dimgrey_cavefish";
3972                 break;
3973         case CHIP_BEIGE_GOBY:
3974                 chip_name = "beige_goby";
3975                 break;
3976         default:
3977                 BUG();
3978         }
3979
3980         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_pfp%s.bin", chip_name, wks);
3981         err = request_firmware(&adev->gfx.pfp_fw, fw_name, adev->dev);
3982         if (err)
3983                 goto out;
3984         err = amdgpu_ucode_validate(adev->gfx.pfp_fw);
3985         if (err)
3986                 goto out;
3987         cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data;
3988         adev->gfx.pfp_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
3989         adev->gfx.pfp_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
3990
3991         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_me%s.bin", chip_name, wks);
3992         err = request_firmware(&adev->gfx.me_fw, fw_name, adev->dev);
3993         if (err)
3994                 goto out;
3995         err = amdgpu_ucode_validate(adev->gfx.me_fw);
3996         if (err)
3997                 goto out;
3998         cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data;
3999         adev->gfx.me_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
4000         adev->gfx.me_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
4001
4002         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ce%s.bin", chip_name, wks);
4003         err = request_firmware(&adev->gfx.ce_fw, fw_name, adev->dev);
4004         if (err)
4005                 goto out;
4006         err = amdgpu_ucode_validate(adev->gfx.ce_fw);
4007         if (err)
4008                 goto out;
4009         cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data;
4010         adev->gfx.ce_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
4011         adev->gfx.ce_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
4012
4013         if (!amdgpu_sriov_vf(adev)) {
4014                 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_rlc.bin", chip_name);
4015                 err = request_firmware(&adev->gfx.rlc_fw, fw_name, adev->dev);
4016                 if (err)
4017                         goto out;
4018                 err = amdgpu_ucode_validate(adev->gfx.rlc_fw);
4019                 rlc_hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data;
4020                 version_major = le16_to_cpu(rlc_hdr->header.header_version_major);
4021                 version_minor = le16_to_cpu(rlc_hdr->header.header_version_minor);
4022
4023                 adev->gfx.rlc_fw_version = le32_to_cpu(rlc_hdr->header.ucode_version);
4024                 adev->gfx.rlc_feature_version = le32_to_cpu(rlc_hdr->ucode_feature_version);
4025                 adev->gfx.rlc.save_and_restore_offset =
4026                         le32_to_cpu(rlc_hdr->save_and_restore_offset);
4027                 adev->gfx.rlc.clear_state_descriptor_offset =
4028                         le32_to_cpu(rlc_hdr->clear_state_descriptor_offset);
4029                 adev->gfx.rlc.avail_scratch_ram_locations =
4030                         le32_to_cpu(rlc_hdr->avail_scratch_ram_locations);
4031                 adev->gfx.rlc.reg_restore_list_size =
4032                         le32_to_cpu(rlc_hdr->reg_restore_list_size);
4033                 adev->gfx.rlc.reg_list_format_start =
4034                         le32_to_cpu(rlc_hdr->reg_list_format_start);
4035                 adev->gfx.rlc.reg_list_format_separate_start =
4036                         le32_to_cpu(rlc_hdr->reg_list_format_separate_start);
4037                 adev->gfx.rlc.starting_offsets_start =
4038                         le32_to_cpu(rlc_hdr->starting_offsets_start);
4039                 adev->gfx.rlc.reg_list_format_size_bytes =
4040                         le32_to_cpu(rlc_hdr->reg_list_format_size_bytes);
4041                 adev->gfx.rlc.reg_list_size_bytes =
4042                         le32_to_cpu(rlc_hdr->reg_list_size_bytes);
4043                 adev->gfx.rlc.register_list_format =
4044                         kmalloc(adev->gfx.rlc.reg_list_format_size_bytes +
4045                                         adev->gfx.rlc.reg_list_size_bytes, GFP_KERNEL);
4046                 if (!adev->gfx.rlc.register_list_format) {
4047                         err = -ENOMEM;
4048                         goto out;
4049                 }
4050
4051                 tmp = (unsigned int *)((uintptr_t)rlc_hdr +
4052                                                            le32_to_cpu(rlc_hdr->reg_list_format_array_offset_bytes));
4053                 for (i = 0 ; i < (rlc_hdr->reg_list_format_size_bytes >> 2); i++)
4054                         adev->gfx.rlc.register_list_format[i] = le32_to_cpu(tmp[i]);
4055
4056                 adev->gfx.rlc.register_restore = adev->gfx.rlc.register_list_format + i;
4057
4058                 tmp = (unsigned int *)((uintptr_t)rlc_hdr +
4059                                                            le32_to_cpu(rlc_hdr->reg_list_array_offset_bytes));
4060                 for (i = 0 ; i < (rlc_hdr->reg_list_size_bytes >> 2); i++)
4061                         adev->gfx.rlc.register_restore[i] = le32_to_cpu(tmp[i]);
4062
4063                 if (version_major == 2) {
4064                         if (version_minor >= 1)
4065                                 gfx_v10_0_init_rlc_ext_microcode(adev);
4066                         if (version_minor == 2)
4067                                 gfx_v10_0_init_rlc_iram_dram_microcode(adev);
4068                 }
4069         }
4070
4071         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec%s.bin", chip_name, wks);
4072         err = request_firmware(&adev->gfx.mec_fw, fw_name, adev->dev);
4073         if (err)
4074                 goto out;
4075         err = amdgpu_ucode_validate(adev->gfx.mec_fw);
4076         if (err)
4077                 goto out;
4078         cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
4079         adev->gfx.mec_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
4080         adev->gfx.mec_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
4081
4082         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec2%s.bin", chip_name, wks);
4083         err = request_firmware(&adev->gfx.mec2_fw, fw_name, adev->dev);
4084         if (!err) {
4085                 err = amdgpu_ucode_validate(adev->gfx.mec2_fw);
4086                 if (err)
4087                         goto out;
4088                 cp_hdr = (const struct gfx_firmware_header_v1_0 *)
4089                 adev->gfx.mec2_fw->data;
4090                 adev->gfx.mec2_fw_version =
4091                 le32_to_cpu(cp_hdr->header.ucode_version);
4092                 adev->gfx.mec2_feature_version =
4093                 le32_to_cpu(cp_hdr->ucode_feature_version);
4094         } else {
4095                 err = 0;
4096                 adev->gfx.mec2_fw = NULL;
4097         }
4098
4099         if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
4100                 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_PFP];
4101                 info->ucode_id = AMDGPU_UCODE_ID_CP_PFP;
4102                 info->fw = adev->gfx.pfp_fw;
4103                 header = (const struct common_firmware_header *)info->fw->data;
4104                 adev->firmware.fw_size +=
4105                         ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
4106
4107                 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_ME];
4108                 info->ucode_id = AMDGPU_UCODE_ID_CP_ME;
4109                 info->fw = adev->gfx.me_fw;
4110                 header = (const struct common_firmware_header *)info->fw->data;
4111                 adev->firmware.fw_size +=
4112                         ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
4113
4114                 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_CE];
4115                 info->ucode_id = AMDGPU_UCODE_ID_CP_CE;
4116                 info->fw = adev->gfx.ce_fw;
4117                 header = (const struct common_firmware_header *)info->fw->data;
4118                 adev->firmware.fw_size +=
4119                         ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
4120
4121                 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_G];
4122                 info->ucode_id = AMDGPU_UCODE_ID_RLC_G;
4123                 info->fw = adev->gfx.rlc_fw;
4124                 if (info->fw) {
4125                         header = (const struct common_firmware_header *)info->fw->data;
4126                         adev->firmware.fw_size +=
4127                                 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
4128                 }
4129                 if (adev->gfx.rlc.save_restore_list_cntl_size_bytes &&
4130                     adev->gfx.rlc.save_restore_list_gpm_size_bytes &&
4131                     adev->gfx.rlc.save_restore_list_srm_size_bytes) {
4132                         info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL];
4133                         info->ucode_id = AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL;
4134                         info->fw = adev->gfx.rlc_fw;
4135                         adev->firmware.fw_size +=
4136                                 ALIGN(adev->gfx.rlc.save_restore_list_cntl_size_bytes, PAGE_SIZE);
4137
4138                         info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM];
4139                         info->ucode_id = AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM;
4140                         info->fw = adev->gfx.rlc_fw;
4141                         adev->firmware.fw_size +=
4142                                 ALIGN(adev->gfx.rlc.save_restore_list_gpm_size_bytes, PAGE_SIZE);
4143
4144                         info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM];
4145                         info->ucode_id = AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM;
4146                         info->fw = adev->gfx.rlc_fw;
4147                         adev->firmware.fw_size +=
4148                                 ALIGN(adev->gfx.rlc.save_restore_list_srm_size_bytes, PAGE_SIZE);
4149
4150                         if (adev->gfx.rlc.rlc_iram_ucode_size_bytes &&
4151                             adev->gfx.rlc.rlc_dram_ucode_size_bytes) {
4152                                 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_IRAM];
4153                                 info->ucode_id = AMDGPU_UCODE_ID_RLC_IRAM;
4154                                 info->fw = adev->gfx.rlc_fw;
4155                                 adev->firmware.fw_size +=
4156                                         ALIGN(adev->gfx.rlc.rlc_iram_ucode_size_bytes, PAGE_SIZE);
4157
4158                                 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_DRAM];
4159                                 info->ucode_id = AMDGPU_UCODE_ID_RLC_DRAM;
4160                                 info->fw = adev->gfx.rlc_fw;
4161                                 adev->firmware.fw_size +=
4162                                         ALIGN(adev->gfx.rlc.rlc_dram_ucode_size_bytes, PAGE_SIZE);
4163                         }
4164                 }
4165
4166                 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC1];
4167                 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC1;
4168                 info->fw = adev->gfx.mec_fw;
4169                 header = (const struct common_firmware_header *)info->fw->data;
4170                 cp_hdr = (const struct gfx_firmware_header_v1_0 *)info->fw->data;
4171                 adev->firmware.fw_size +=
4172                         ALIGN(le32_to_cpu(header->ucode_size_bytes) -
4173                               le32_to_cpu(cp_hdr->jt_size) * 4, PAGE_SIZE);
4174
4175                 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC1_JT];
4176                 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC1_JT;
4177                 info->fw = adev->gfx.mec_fw;
4178                 adev->firmware.fw_size +=
4179                         ALIGN(le32_to_cpu(cp_hdr->jt_size) * 4, PAGE_SIZE);
4180
4181                 if (adev->gfx.mec2_fw) {
4182                         info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC2];
4183                         info->ucode_id = AMDGPU_UCODE_ID_CP_MEC2;
4184                         info->fw = adev->gfx.mec2_fw;
4185                         header = (const struct common_firmware_header *)info->fw->data;
4186                         cp_hdr = (const struct gfx_firmware_header_v1_0 *)info->fw->data;
4187                         adev->firmware.fw_size +=
4188                                 ALIGN(le32_to_cpu(header->ucode_size_bytes) -
4189                                       le32_to_cpu(cp_hdr->jt_size) * 4,
4190                                       PAGE_SIZE);
4191                         info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC2_JT];
4192                         info->ucode_id = AMDGPU_UCODE_ID_CP_MEC2_JT;
4193                         info->fw = adev->gfx.mec2_fw;
4194                         adev->firmware.fw_size +=
4195                                 ALIGN(le32_to_cpu(cp_hdr->jt_size) * 4,
4196                                       PAGE_SIZE);
4197                 }
4198         }
4199
4200         gfx_v10_0_check_fw_write_wait(adev);
4201 out:
4202         if (err) {
4203                 dev_err(adev->dev,
4204                         "gfx10: Failed to load firmware \"%s\"\n",
4205                         fw_name);
4206                 release_firmware(adev->gfx.pfp_fw);
4207                 adev->gfx.pfp_fw = NULL;
4208                 release_firmware(adev->gfx.me_fw);
4209                 adev->gfx.me_fw = NULL;
4210                 release_firmware(adev->gfx.ce_fw);
4211                 adev->gfx.ce_fw = NULL;
4212                 release_firmware(adev->gfx.rlc_fw);
4213                 adev->gfx.rlc_fw = NULL;
4214                 release_firmware(adev->gfx.mec_fw);
4215                 adev->gfx.mec_fw = NULL;
4216                 release_firmware(adev->gfx.mec2_fw);
4217                 adev->gfx.mec2_fw = NULL;
4218         }
4219
4220         gfx_v10_0_check_gfxoff_flag(adev);
4221
4222         return err;
4223 }
4224
4225 static u32 gfx_v10_0_get_csb_size(struct amdgpu_device *adev)
4226 {
4227         u32 count = 0;
4228         const struct cs_section_def *sect = NULL;
4229         const struct cs_extent_def *ext = NULL;
4230
4231         /* begin clear state */
4232         count += 2;
4233         /* context control state */
4234         count += 3;
4235
4236         for (sect = gfx10_cs_data; sect->section != NULL; ++sect) {
4237                 for (ext = sect->section; ext->extent != NULL; ++ext) {
4238                         if (sect->id == SECT_CONTEXT)
4239                                 count += 2 + ext->reg_count;
4240                         else
4241                                 return 0;
4242                 }
4243         }
4244
4245         /* set PA_SC_TILE_STEERING_OVERRIDE */
4246         count += 3;
4247         /* end clear state */
4248         count += 2;
4249         /* clear state */
4250         count += 2;
4251
4252         return count;
4253 }
4254
4255 static void gfx_v10_0_get_csb_buffer(struct amdgpu_device *adev,
4256                                     volatile u32 *buffer)
4257 {
4258         u32 count = 0, i;
4259         const struct cs_section_def *sect = NULL;
4260         const struct cs_extent_def *ext = NULL;
4261         int ctx_reg_offset;
4262
4263         if (adev->gfx.rlc.cs_data == NULL)
4264                 return;
4265         if (buffer == NULL)
4266                 return;
4267
4268         buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));
4269         buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
4270
4271         buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CONTEXT_CONTROL, 1));
4272         buffer[count++] = cpu_to_le32(0x80000000);
4273         buffer[count++] = cpu_to_le32(0x80000000);
4274
4275         for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) {
4276                 for (ext = sect->section; ext->extent != NULL; ++ext) {
4277                         if (sect->id == SECT_CONTEXT) {
4278                                 buffer[count++] =
4279                                         cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count));
4280                                 buffer[count++] = cpu_to_le32(ext->reg_index -
4281                                                 PACKET3_SET_CONTEXT_REG_START);
4282                                 for (i = 0; i < ext->reg_count; i++)
4283                                         buffer[count++] = cpu_to_le32(ext->extent[i]);
4284                         } else {
4285                                 return;
4286                         }
4287                 }
4288         }
4289
4290         ctx_reg_offset =
4291                 SOC15_REG_OFFSET(GC, 0, mmPA_SC_TILE_STEERING_OVERRIDE) - PACKET3_SET_CONTEXT_REG_START;
4292         buffer[count++] = cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, 1));
4293         buffer[count++] = cpu_to_le32(ctx_reg_offset);
4294         buffer[count++] = cpu_to_le32(adev->gfx.config.pa_sc_tile_steering_override);
4295
4296         buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));
4297         buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_END_CLEAR_STATE);
4298
4299         buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CLEAR_STATE, 0));
4300         buffer[count++] = cpu_to_le32(0);
4301 }
4302
4303 static void gfx_v10_0_rlc_fini(struct amdgpu_device *adev)
4304 {
4305         /* clear state block */
4306         amdgpu_bo_free_kernel(&adev->gfx.rlc.clear_state_obj,
4307                         &adev->gfx.rlc.clear_state_gpu_addr,
4308                         (void **)&adev->gfx.rlc.cs_ptr);
4309
4310         /* jump table block */
4311         amdgpu_bo_free_kernel(&adev->gfx.rlc.cp_table_obj,
4312                         &adev->gfx.rlc.cp_table_gpu_addr,
4313                         (void **)&adev->gfx.rlc.cp_table_ptr);
4314 }
4315
4316 static int gfx_v10_0_rlc_init(struct amdgpu_device *adev)
4317 {
4318         const struct cs_section_def *cs_data;
4319         int r;
4320
4321         adev->gfx.rlc.cs_data = gfx10_cs_data;
4322
4323         cs_data = adev->gfx.rlc.cs_data;
4324
4325         if (cs_data) {
4326                 /* init clear state block */
4327                 r = amdgpu_gfx_rlc_init_csb(adev);
4328                 if (r)
4329                         return r;
4330         }
4331
4332         /* init spm vmid with 0xf */
4333         if (adev->gfx.rlc.funcs->update_spm_vmid)
4334                 adev->gfx.rlc.funcs->update_spm_vmid(adev, 0xf);
4335
4336         return 0;
4337 }
4338
4339 static void gfx_v10_0_mec_fini(struct amdgpu_device *adev)
4340 {
4341         amdgpu_bo_free_kernel(&adev->gfx.mec.hpd_eop_obj, NULL, NULL);
4342         amdgpu_bo_free_kernel(&adev->gfx.mec.mec_fw_obj, NULL, NULL);
4343 }
4344
4345 static int gfx_v10_0_me_init(struct amdgpu_device *adev)
4346 {
4347         int r;
4348
4349         bitmap_zero(adev->gfx.me.queue_bitmap, AMDGPU_MAX_GFX_QUEUES);
4350
4351         amdgpu_gfx_graphics_queue_acquire(adev);
4352
4353         r = gfx_v10_0_init_microcode(adev);
4354         if (r)
4355                 DRM_ERROR("Failed to load gfx firmware!\n");
4356
4357         return r;
4358 }
4359
4360 static int gfx_v10_0_mec_init(struct amdgpu_device *adev)
4361 {
4362         int r;
4363         u32 *hpd;
4364         const __le32 *fw_data = NULL;
4365         unsigned fw_size;
4366         u32 *fw = NULL;
4367         size_t mec_hpd_size;
4368
4369         const struct gfx_firmware_header_v1_0 *mec_hdr = NULL;
4370
4371         bitmap_zero(adev->gfx.mec.queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES);
4372
4373         /* take ownership of the relevant compute queues */
4374         amdgpu_gfx_compute_queue_acquire(adev);
4375         mec_hpd_size = adev->gfx.num_compute_rings * GFX10_MEC_HPD_SIZE;
4376
4377         if (mec_hpd_size) {
4378                 r = amdgpu_bo_create_reserved(adev, mec_hpd_size, PAGE_SIZE,
4379                                               AMDGPU_GEM_DOMAIN_GTT,
4380                                               &adev->gfx.mec.hpd_eop_obj,
4381                                               &adev->gfx.mec.hpd_eop_gpu_addr,
4382                                               (void **)&hpd);
4383                 if (r) {
4384                         dev_warn(adev->dev, "(%d) create HDP EOP bo failed\n", r);
4385                         gfx_v10_0_mec_fini(adev);
4386                         return r;
4387                 }
4388
4389                 memset(hpd, 0, mec_hpd_size);
4390
4391                 amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj);
4392                 amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj);
4393         }
4394
4395         if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
4396                 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
4397
4398                 fw_data = (const __le32 *) (adev->gfx.mec_fw->data +
4399                          le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes));
4400                 fw_size = le32_to_cpu(mec_hdr->header.ucode_size_bytes);
4401
4402                 r = amdgpu_bo_create_reserved(adev, mec_hdr->header.ucode_size_bytes,
4403                                               PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,
4404                                               &adev->gfx.mec.mec_fw_obj,
4405                                               &adev->gfx.mec.mec_fw_gpu_addr,
4406                                               (void **)&fw);
4407                 if (r) {
4408                         dev_err(adev->dev, "(%d) failed to create mec fw bo\n", r);
4409                         gfx_v10_0_mec_fini(adev);
4410                         return r;
4411                 }
4412
4413                 memcpy(fw, fw_data, fw_size);
4414
4415                 amdgpu_bo_kunmap(adev->gfx.mec.mec_fw_obj);
4416                 amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_obj);
4417         }
4418
4419         return 0;
4420 }
4421
4422 static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t wave, uint32_t address)
4423 {
4424         WREG32_SOC15(GC, 0, mmSQ_IND_INDEX,
4425                 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) |
4426                 (address << SQ_IND_INDEX__INDEX__SHIFT));
4427         return RREG32_SOC15(GC, 0, mmSQ_IND_DATA);
4428 }
4429
4430 static void wave_read_regs(struct amdgpu_device *adev, uint32_t wave,
4431                            uint32_t thread, uint32_t regno,
4432                            uint32_t num, uint32_t *out)
4433 {
4434         WREG32_SOC15(GC, 0, mmSQ_IND_INDEX,
4435                 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) |
4436                 (regno << SQ_IND_INDEX__INDEX__SHIFT) |
4437                 (thread << SQ_IND_INDEX__WORKITEM_ID__SHIFT) |
4438                 (SQ_IND_INDEX__AUTO_INCR_MASK));
4439         while (num--)
4440                 *(out++) = RREG32_SOC15(GC, 0, mmSQ_IND_DATA);
4441 }
4442
4443 static void gfx_v10_0_read_wave_data(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t *dst, int *no_fields)
4444 {
4445         /* in gfx10 the SIMD_ID is specified as part of the INSTANCE
4446          * field when performing a select_se_sh so it should be
4447          * zero here */
4448         WARN_ON(simd != 0);
4449
4450         /* type 2 wave data */
4451         dst[(*no_fields)++] = 2;
4452         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_STATUS);
4453         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_PC_LO);
4454         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_PC_HI);
4455         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXEC_LO);
4456         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXEC_HI);
4457         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_HW_ID1);
4458         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_HW_ID2);
4459         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_INST_DW0);
4460         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_GPR_ALLOC);
4461         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_LDS_ALLOC);
4462         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_TRAPSTS);
4463         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_STS);
4464         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_STS2);
4465         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_DBG1);
4466         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_M0);
4467 }
4468
4469 static void gfx_v10_0_read_wave_sgprs(struct amdgpu_device *adev, uint32_t simd,
4470                                      uint32_t wave, uint32_t start,
4471                                      uint32_t size, uint32_t *dst)
4472 {
4473         WARN_ON(simd != 0);
4474
4475         wave_read_regs(
4476                 adev, wave, 0, start + SQIND_WAVE_SGPRS_OFFSET, size,
4477                 dst);
4478 }
4479
4480 static void gfx_v10_0_read_wave_vgprs(struct amdgpu_device *adev, uint32_t simd,
4481                                       uint32_t wave, uint32_t thread,
4482                                       uint32_t start, uint32_t size,
4483                                       uint32_t *dst)
4484 {
4485         wave_read_regs(
4486                 adev, wave, thread,
4487                 start + SQIND_WAVE_VGPRS_OFFSET, size, dst);
4488 }
4489
4490 static void gfx_v10_0_select_me_pipe_q(struct amdgpu_device *adev,
4491                                        u32 me, u32 pipe, u32 q, u32 vm)
4492 {
4493         nv_grbm_select(adev, me, pipe, q, vm);
4494 }
4495
4496 static void gfx_v10_0_update_perfmon_mgcg(struct amdgpu_device *adev,
4497                                           bool enable)
4498 {
4499         uint32_t data, def;
4500
4501         data = def = RREG32_SOC15(GC, 0, mmRLC_PERFMON_CLK_CNTL);
4502
4503         if (enable)
4504                 data |= RLC_PERFMON_CLK_CNTL__PERFMON_CLOCK_STATE_MASK;
4505         else
4506                 data &= ~RLC_PERFMON_CLK_CNTL__PERFMON_CLOCK_STATE_MASK;
4507
4508         if (data != def)
4509                 WREG32_SOC15(GC, 0, mmRLC_PERFMON_CLK_CNTL, data);
4510 }
4511
4512 static const struct amdgpu_gfx_funcs gfx_v10_0_gfx_funcs = {
4513         .get_gpu_clock_counter = &gfx_v10_0_get_gpu_clock_counter,
4514         .select_se_sh = &gfx_v10_0_select_se_sh,
4515         .read_wave_data = &gfx_v10_0_read_wave_data,
4516         .read_wave_sgprs = &gfx_v10_0_read_wave_sgprs,
4517         .read_wave_vgprs = &gfx_v10_0_read_wave_vgprs,
4518         .select_me_pipe_q = &gfx_v10_0_select_me_pipe_q,
4519         .init_spm_golden = &gfx_v10_0_init_spm_golden_registers,
4520         .update_perfmon_mgcg = &gfx_v10_0_update_perfmon_mgcg,
4521 };
4522
4523 static void gfx_v10_0_gpu_early_init(struct amdgpu_device *adev)
4524 {
4525         u32 gb_addr_config;
4526
4527         adev->gfx.funcs = &gfx_v10_0_gfx_funcs;
4528
4529         switch (adev->asic_type) {
4530         case CHIP_NAVI10:
4531         case CHIP_NAVI14:
4532         case CHIP_NAVI12:
4533                 adev->gfx.config.max_hw_contexts = 8;
4534                 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
4535                 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
4536                 adev->gfx.config.sc_hiz_tile_fifo_size = 0;
4537                 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0;
4538                 gb_addr_config = RREG32_SOC15(GC, 0, mmGB_ADDR_CONFIG);
4539                 break;
4540         case CHIP_SIENNA_CICHLID:
4541         case CHIP_NAVY_FLOUNDER:
4542         case CHIP_VANGOGH:
4543         case CHIP_DIMGREY_CAVEFISH:
4544         case CHIP_BEIGE_GOBY:
4545                 adev->gfx.config.max_hw_contexts = 8;
4546                 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
4547                 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
4548                 adev->gfx.config.sc_hiz_tile_fifo_size = 0;
4549                 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0;
4550                 gb_addr_config = RREG32_SOC15(GC, 0, mmGB_ADDR_CONFIG);
4551                 adev->gfx.config.gb_addr_config_fields.num_pkrs =
4552                         1 << REG_GET_FIELD(gb_addr_config, GB_ADDR_CONFIG, NUM_PKRS);
4553                 break;
4554         default:
4555                 BUG();
4556                 break;
4557         }
4558
4559         adev->gfx.config.gb_addr_config = gb_addr_config;
4560
4561         adev->gfx.config.gb_addr_config_fields.num_pipes = 1 <<
4562                         REG_GET_FIELD(adev->gfx.config.gb_addr_config,
4563                                       GB_ADDR_CONFIG, NUM_PIPES);
4564
4565         adev->gfx.config.max_tile_pipes =
4566                 adev->gfx.config.gb_addr_config_fields.num_pipes;
4567
4568         adev->gfx.config.gb_addr_config_fields.max_compress_frags = 1 <<
4569                         REG_GET_FIELD(adev->gfx.config.gb_addr_config,
4570                                       GB_ADDR_CONFIG, MAX_COMPRESSED_FRAGS);
4571         adev->gfx.config.gb_addr_config_fields.num_rb_per_se = 1 <<
4572                         REG_GET_FIELD(adev->gfx.config.gb_addr_config,
4573                                       GB_ADDR_CONFIG, NUM_RB_PER_SE);
4574         adev->gfx.config.gb_addr_config_fields.num_se = 1 <<
4575                         REG_GET_FIELD(adev->gfx.config.gb_addr_config,
4576                                       GB_ADDR_CONFIG, NUM_SHADER_ENGINES);
4577         adev->gfx.config.gb_addr_config_fields.pipe_interleave_size = 1 << (8 +
4578                         REG_GET_FIELD(adev->gfx.config.gb_addr_config,
4579                                       GB_ADDR_CONFIG, PIPE_INTERLEAVE_SIZE));
4580 }
4581
4582 static int gfx_v10_0_gfx_ring_init(struct amdgpu_device *adev, int ring_id,
4583                                    int me, int pipe, int queue)
4584 {
4585         int r;
4586         struct amdgpu_ring *ring;
4587         unsigned int irq_type;
4588
4589         ring = &adev->gfx.gfx_ring[ring_id];
4590
4591         ring->me = me;
4592         ring->pipe = pipe;
4593         ring->queue = queue;
4594
4595         ring->ring_obj = NULL;
4596         ring->use_doorbell = true;
4597
4598         if (!ring_id)
4599                 ring->doorbell_index = adev->doorbell_index.gfx_ring0 << 1;
4600         else
4601                 ring->doorbell_index = adev->doorbell_index.gfx_ring1 << 1;
4602         sprintf(ring->name, "gfx_%d.%d.%d", ring->me, ring->pipe, ring->queue);
4603
4604         irq_type = AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP + ring->pipe;
4605         r = amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, irq_type,
4606                              AMDGPU_RING_PRIO_DEFAULT, NULL);
4607         if (r)
4608                 return r;
4609         return 0;
4610 }
4611
4612 static int gfx_v10_0_compute_ring_init(struct amdgpu_device *adev, int ring_id,
4613                                        int mec, int pipe, int queue)
4614 {
4615         int r;
4616         unsigned irq_type;
4617         struct amdgpu_ring *ring;
4618         unsigned int hw_prio;
4619
4620         ring = &adev->gfx.compute_ring[ring_id];
4621
4622         /* mec0 is me1 */
4623         ring->me = mec + 1;
4624         ring->pipe = pipe;
4625         ring->queue = queue;
4626
4627         ring->ring_obj = NULL;
4628         ring->use_doorbell = true;
4629         ring->doorbell_index = (adev->doorbell_index.mec_ring0 + ring_id) << 1;
4630         ring->eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr
4631                                 + (ring_id * GFX10_MEC_HPD_SIZE);
4632         sprintf(ring->name, "comp_%d.%d.%d", ring->me, ring->pipe, ring->queue);
4633
4634         irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP
4635                 + ((ring->me - 1) * adev->gfx.mec.num_pipe_per_mec)
4636                 + ring->pipe;
4637         hw_prio = amdgpu_gfx_is_high_priority_compute_queue(adev, ring) ?
4638                         AMDGPU_GFX_PIPE_PRIO_HIGH : AMDGPU_GFX_PIPE_PRIO_NORMAL;
4639         /* type-2 packets are deprecated on MEC, use type-3 instead */
4640         r = amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, irq_type,
4641                              hw_prio, NULL);
4642         if (r)
4643                 return r;
4644
4645         return 0;
4646 }
4647
4648 static int gfx_v10_0_sw_init(void *handle)
4649 {
4650         int i, j, k, r, ring_id = 0;
4651         struct amdgpu_kiq *kiq;
4652         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4653
4654         switch (adev->asic_type) {
4655         case CHIP_NAVI10:
4656         case CHIP_NAVI14:
4657         case CHIP_NAVI12:
4658                 adev->gfx.me.num_me = 1;
4659                 adev->gfx.me.num_pipe_per_me = 1;
4660                 adev->gfx.me.num_queue_per_pipe = 1;
4661                 adev->gfx.mec.num_mec = 2;
4662                 adev->gfx.mec.num_pipe_per_mec = 4;
4663                 adev->gfx.mec.num_queue_per_pipe = 8;
4664                 break;
4665         case CHIP_SIENNA_CICHLID:
4666         case CHIP_NAVY_FLOUNDER:
4667         case CHIP_VANGOGH:
4668         case CHIP_DIMGREY_CAVEFISH:
4669         case CHIP_BEIGE_GOBY:
4670                 adev->gfx.me.num_me = 1;
4671                 adev->gfx.me.num_pipe_per_me = 1;
4672                 adev->gfx.me.num_queue_per_pipe = 1;
4673                 adev->gfx.mec.num_mec = 2;
4674                 adev->gfx.mec.num_pipe_per_mec = 4;
4675                 adev->gfx.mec.num_queue_per_pipe = 4;
4676                 break;
4677         default:
4678                 adev->gfx.me.num_me = 1;
4679                 adev->gfx.me.num_pipe_per_me = 1;
4680                 adev->gfx.me.num_queue_per_pipe = 1;
4681                 adev->gfx.mec.num_mec = 1;
4682                 adev->gfx.mec.num_pipe_per_mec = 4;
4683                 adev->gfx.mec.num_queue_per_pipe = 8;
4684                 break;
4685         }
4686
4687         /* KIQ event */
4688         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP,
4689                               GFX_10_1__SRCID__CP_IB2_INTERRUPT_PKT,
4690                               &adev->gfx.kiq.irq);
4691         if (r)
4692                 return r;
4693
4694         /* EOP Event */
4695         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP,
4696                               GFX_10_1__SRCID__CP_EOP_INTERRUPT,
4697                               &adev->gfx.eop_irq);
4698         if (r)
4699                 return r;
4700
4701         /* Privileged reg */
4702         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_10_1__SRCID__CP_PRIV_REG_FAULT,
4703                               &adev->gfx.priv_reg_irq);
4704         if (r)
4705                 return r;
4706
4707         /* Privileged inst */
4708         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_10_1__SRCID__CP_PRIV_INSTR_FAULT,
4709                               &adev->gfx.priv_inst_irq);
4710         if (r)
4711                 return r;
4712
4713         adev->gfx.gfx_current_status = AMDGPU_GFX_NORMAL_MODE;
4714
4715         gfx_v10_0_scratch_init(adev);
4716
4717         r = gfx_v10_0_me_init(adev);
4718         if (r)
4719                 return r;
4720
4721         r = gfx_v10_0_rlc_init(adev);
4722         if (r) {
4723                 DRM_ERROR("Failed to init rlc BOs!\n");
4724                 return r;
4725         }
4726
4727         r = gfx_v10_0_mec_init(adev);
4728         if (r) {
4729                 DRM_ERROR("Failed to init MEC BOs!\n");
4730                 return r;
4731         }
4732
4733         /* set up the gfx ring */
4734         for (i = 0; i < adev->gfx.me.num_me; i++) {
4735                 for (j = 0; j < adev->gfx.me.num_queue_per_pipe; j++) {
4736                         for (k = 0; k < adev->gfx.me.num_pipe_per_me; k++) {
4737                                 if (!amdgpu_gfx_is_me_queue_enabled(adev, i, k, j))
4738                                         continue;
4739
4740                                 r = gfx_v10_0_gfx_ring_init(adev, ring_id,
4741                                                             i, k, j);
4742                                 if (r)
4743                                         return r;
4744                                 ring_id++;
4745                         }
4746                 }
4747         }
4748
4749         ring_id = 0;
4750         /* set up the compute queues - allocate horizontally across pipes */
4751         for (i = 0; i < adev->gfx.mec.num_mec; ++i) {
4752                 for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) {
4753                         for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) {
4754                                 if (!amdgpu_gfx_is_mec_queue_enabled(adev, i, k,
4755                                                                      j))
4756                                         continue;
4757
4758                                 r = gfx_v10_0_compute_ring_init(adev, ring_id,
4759                                                                 i, k, j);
4760                                 if (r)
4761                                         return r;
4762
4763                                 ring_id++;
4764                         }
4765                 }
4766         }
4767
4768         r = amdgpu_gfx_kiq_init(adev, GFX10_MEC_HPD_SIZE);
4769         if (r) {
4770                 DRM_ERROR("Failed to init KIQ BOs!\n");
4771                 return r;
4772         }
4773
4774         kiq = &adev->gfx.kiq;
4775         r = amdgpu_gfx_kiq_init_ring(adev, &kiq->ring, &kiq->irq);
4776         if (r)
4777                 return r;
4778
4779         r = amdgpu_gfx_mqd_sw_init(adev, sizeof(struct v10_compute_mqd));
4780         if (r)
4781                 return r;
4782
4783         /* allocate visible FB for rlc auto-loading fw */
4784         if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) {
4785                 r = gfx_v10_0_rlc_backdoor_autoload_buffer_init(adev);
4786                 if (r)
4787                         return r;
4788         }
4789
4790         adev->gfx.ce_ram_size = F32_CE_PROGRAM_RAM_SIZE;
4791
4792         gfx_v10_0_gpu_early_init(adev);
4793
4794         return 0;
4795 }
4796
4797 static void gfx_v10_0_pfp_fini(struct amdgpu_device *adev)
4798 {
4799         amdgpu_bo_free_kernel(&adev->gfx.pfp.pfp_fw_obj,
4800                               &adev->gfx.pfp.pfp_fw_gpu_addr,
4801                               (void **)&adev->gfx.pfp.pfp_fw_ptr);
4802 }
4803
4804 static void gfx_v10_0_ce_fini(struct amdgpu_device *adev)
4805 {
4806         amdgpu_bo_free_kernel(&adev->gfx.ce.ce_fw_obj,
4807                               &adev->gfx.ce.ce_fw_gpu_addr,
4808                               (void **)&adev->gfx.ce.ce_fw_ptr);
4809 }
4810
4811 static void gfx_v10_0_me_fini(struct amdgpu_device *adev)
4812 {
4813         amdgpu_bo_free_kernel(&adev->gfx.me.me_fw_obj,
4814                               &adev->gfx.me.me_fw_gpu_addr,
4815                               (void **)&adev->gfx.me.me_fw_ptr);
4816 }
4817
4818 static int gfx_v10_0_sw_fini(void *handle)
4819 {
4820         int i;
4821         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4822
4823         for (i = 0; i < adev->gfx.num_gfx_rings; i++)
4824                 amdgpu_ring_fini(&adev->gfx.gfx_ring[i]);
4825         for (i = 0; i < adev->gfx.num_compute_rings; i++)
4826                 amdgpu_ring_fini(&adev->gfx.compute_ring[i]);
4827
4828         amdgpu_gfx_mqd_sw_fini(adev);
4829         amdgpu_gfx_kiq_free_ring(&adev->gfx.kiq.ring);
4830         amdgpu_gfx_kiq_fini(adev);
4831
4832         gfx_v10_0_pfp_fini(adev);
4833         gfx_v10_0_ce_fini(adev);
4834         gfx_v10_0_me_fini(adev);
4835         gfx_v10_0_rlc_fini(adev);
4836         gfx_v10_0_mec_fini(adev);
4837
4838         if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO)
4839                 gfx_v10_0_rlc_backdoor_autoload_buffer_fini(adev);
4840
4841         gfx_v10_0_free_microcode(adev);
4842
4843         return 0;
4844 }
4845
4846 static void gfx_v10_0_select_se_sh(struct amdgpu_device *adev, u32 se_num,
4847                                    u32 sh_num, u32 instance)
4848 {
4849         u32 data;
4850
4851         if (instance == 0xffffffff)
4852                 data = REG_SET_FIELD(0, GRBM_GFX_INDEX,
4853                                      INSTANCE_BROADCAST_WRITES, 1);
4854         else
4855                 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_INDEX,
4856                                      instance);
4857
4858         if (se_num == 0xffffffff)
4859                 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_BROADCAST_WRITES,
4860                                      1);
4861         else
4862                 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num);
4863
4864         if (sh_num == 0xffffffff)
4865                 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SA_BROADCAST_WRITES,
4866                                      1);
4867         else
4868                 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SA_INDEX, sh_num);
4869
4870         WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, data);
4871 }
4872
4873 static u32 gfx_v10_0_get_rb_active_bitmap(struct amdgpu_device *adev)
4874 {
4875         u32 data, mask;
4876
4877         data = RREG32_SOC15(GC, 0, mmCC_RB_BACKEND_DISABLE);
4878         data |= RREG32_SOC15(GC, 0, mmGC_USER_RB_BACKEND_DISABLE);
4879
4880         data &= CC_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK;
4881         data >>= GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT;
4882
4883         mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_backends_per_se /
4884                                          adev->gfx.config.max_sh_per_se);
4885
4886         return (~data) & mask;
4887 }
4888
4889 static void gfx_v10_0_setup_rb(struct amdgpu_device *adev)
4890 {
4891         int i, j;
4892         u32 data;
4893         u32 active_rbs = 0;
4894         u32 bitmap;
4895         u32 rb_bitmap_width_per_sh = adev->gfx.config.max_backends_per_se /
4896                                         adev->gfx.config.max_sh_per_se;
4897
4898         mutex_lock(&adev->grbm_idx_mutex);
4899         for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
4900                 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
4901                         bitmap = i * adev->gfx.config.max_sh_per_se + j;
4902                         if ((adev->asic_type == CHIP_SIENNA_CICHLID) &&
4903                             ((gfx_v10_3_get_disabled_sa(adev) >> bitmap) & 1))
4904                                 continue;
4905                         gfx_v10_0_select_se_sh(adev, i, j, 0xffffffff);
4906                         data = gfx_v10_0_get_rb_active_bitmap(adev);
4907                         active_rbs |= data << ((i * adev->gfx.config.max_sh_per_se + j) *
4908                                                rb_bitmap_width_per_sh);
4909                 }
4910         }
4911         gfx_v10_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
4912         mutex_unlock(&adev->grbm_idx_mutex);
4913
4914         adev->gfx.config.backend_enable_mask = active_rbs;
4915         adev->gfx.config.num_rbs = hweight32(active_rbs);
4916 }
4917
4918 static u32 gfx_v10_0_init_pa_sc_tile_steering_override(struct amdgpu_device *adev)
4919 {
4920         uint32_t num_sc;
4921         uint32_t enabled_rb_per_sh;
4922         uint32_t active_rb_bitmap;
4923         uint32_t num_rb_per_sc;
4924         uint32_t num_packer_per_sc;
4925         uint32_t pa_sc_tile_steering_override;
4926
4927         /* for ASICs that integrates GFX v10.3
4928          * pa_sc_tile_steering_override should be set to 0 */
4929         if (adev->asic_type >= CHIP_SIENNA_CICHLID)
4930                 return 0;
4931
4932         /* init num_sc */
4933         num_sc = adev->gfx.config.max_shader_engines * adev->gfx.config.max_sh_per_se *
4934                         adev->gfx.config.num_sc_per_sh;
4935         /* init num_rb_per_sc */
4936         active_rb_bitmap = gfx_v10_0_get_rb_active_bitmap(adev);
4937         enabled_rb_per_sh = hweight32(active_rb_bitmap);
4938         num_rb_per_sc = enabled_rb_per_sh / adev->gfx.config.num_sc_per_sh;
4939         /* init num_packer_per_sc */
4940         num_packer_per_sc = adev->gfx.config.num_packer_per_sc;
4941
4942         pa_sc_tile_steering_override = 0;
4943         pa_sc_tile_steering_override |=
4944                 (order_base_2(num_sc) << PA_SC_TILE_STEERING_OVERRIDE__NUM_SC__SHIFT) &
4945                 PA_SC_TILE_STEERING_OVERRIDE__NUM_SC_MASK;
4946         pa_sc_tile_steering_override |=
4947                 (order_base_2(num_rb_per_sc) << PA_SC_TILE_STEERING_OVERRIDE__NUM_RB_PER_SC__SHIFT) &
4948                 PA_SC_TILE_STEERING_OVERRIDE__NUM_RB_PER_SC_MASK;
4949         pa_sc_tile_steering_override |=
4950                 (order_base_2(num_packer_per_sc) << PA_SC_TILE_STEERING_OVERRIDE__NUM_PACKER_PER_SC__SHIFT) &
4951                 PA_SC_TILE_STEERING_OVERRIDE__NUM_PACKER_PER_SC_MASK;
4952
4953         return pa_sc_tile_steering_override;
4954 }
4955
4956 #define DEFAULT_SH_MEM_BASES    (0x6000)
4957
4958 static void gfx_v10_0_init_compute_vmid(struct amdgpu_device *adev)
4959 {
4960         int i;
4961         uint32_t sh_mem_bases;
4962
4963         /*
4964          * Configure apertures:
4965          * LDS:         0x60000000'00000000 - 0x60000001'00000000 (4GB)
4966          * Scratch:     0x60000001'00000000 - 0x60000002'00000000 (4GB)
4967          * GPUVM:       0x60010000'00000000 - 0x60020000'00000000 (1TB)
4968          */
4969         sh_mem_bases = DEFAULT_SH_MEM_BASES | (DEFAULT_SH_MEM_BASES << 16);
4970
4971         mutex_lock(&adev->srbm_mutex);
4972         for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) {
4973                 nv_grbm_select(adev, 0, 0, 0, i);
4974                 /* CP and shaders */
4975                 WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, DEFAULT_SH_MEM_CONFIG);
4976                 WREG32_SOC15(GC, 0, mmSH_MEM_BASES, sh_mem_bases);
4977         }
4978         nv_grbm_select(adev, 0, 0, 0, 0);
4979         mutex_unlock(&adev->srbm_mutex);
4980
4981         /* Initialize all compute VMIDs to have no GDS, GWS, or OA
4982            acccess. These should be enabled by FW for target VMIDs. */
4983         for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) {
4984                 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_BASE, 2 * i, 0);
4985                 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_SIZE, 2 * i, 0);
4986                 WREG32_SOC15_OFFSET(GC, 0, mmGDS_GWS_VMID0, i, 0);
4987                 WREG32_SOC15_OFFSET(GC, 0, mmGDS_OA_VMID0, i, 0);
4988         }
4989 }
4990
4991 static void gfx_v10_0_init_gds_vmid(struct amdgpu_device *adev)
4992 {
4993         int vmid;
4994
4995         /*
4996          * Initialize all compute and user-gfx VMIDs to have no GDS, GWS, or OA
4997          * access. Compute VMIDs should be enabled by FW for target VMIDs,
4998          * the driver can enable them for graphics. VMID0 should maintain
4999          * access so that HWS firmware can save/restore entries.
5000          */
5001         for (vmid = 1; vmid < AMDGPU_NUM_VMID; vmid++) {
5002                 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_BASE, 2 * vmid, 0);
5003                 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_SIZE, 2 * vmid, 0);
5004                 WREG32_SOC15_OFFSET(GC, 0, mmGDS_GWS_VMID0, vmid, 0);
5005                 WREG32_SOC15_OFFSET(GC, 0, mmGDS_OA_VMID0, vmid, 0);
5006         }
5007 }
5008
5009
5010 static void gfx_v10_0_tcp_harvest(struct amdgpu_device *adev)
5011 {
5012         int i, j, k;
5013         int max_wgp_per_sh = adev->gfx.config.max_cu_per_sh >> 1;
5014         u32 tmp, wgp_active_bitmap = 0;
5015         u32 gcrd_targets_disable_tcp = 0;
5016         u32 utcl_invreq_disable = 0;
5017         /*
5018          * GCRD_TARGETS_DISABLE field contains
5019          * for Navi10/Navi12: GL1C=[18:15], SQC=[14:10], TCP=[9:0]
5020          * for Navi14: GL1C=[21:18], SQC=[17:12], TCP=[11:0]
5021          */
5022         u32 gcrd_targets_disable_mask = amdgpu_gfx_create_bitmask(
5023                 2 * max_wgp_per_sh + /* TCP */
5024                 max_wgp_per_sh + /* SQC */
5025                 4); /* GL1C */
5026         /*
5027          * UTCL1_UTCL0_INVREQ_DISABLE field contains
5028          * for Navi10Navi12: SQG=[24], RMI=[23:20], SQC=[19:10], TCP=[9:0]
5029          * for Navi14: SQG=[28], RMI=[27:24], SQC=[23:12], TCP=[11:0]
5030          */
5031         u32 utcl_invreq_disable_mask = amdgpu_gfx_create_bitmask(
5032                 2 * max_wgp_per_sh + /* TCP */
5033                 2 * max_wgp_per_sh + /* SQC */
5034                 4 + /* RMI */
5035                 1); /* SQG */
5036
5037         if (adev->asic_type == CHIP_NAVI10 ||
5038             adev->asic_type == CHIP_NAVI14 ||
5039             adev->asic_type == CHIP_NAVI12) {
5040                 mutex_lock(&adev->grbm_idx_mutex);
5041                 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
5042                         for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
5043                                 gfx_v10_0_select_se_sh(adev, i, j, 0xffffffff);
5044                                 wgp_active_bitmap = gfx_v10_0_get_wgp_active_bitmap_per_sh(adev);
5045                                 /*
5046                                  * Set corresponding TCP bits for the inactive WGPs in
5047                                  * GCRD_SA_TARGETS_DISABLE
5048                                  */
5049                                 gcrd_targets_disable_tcp = 0;
5050                                 /* Set TCP & SQC bits in UTCL1_UTCL0_INVREQ_DISABLE */
5051                                 utcl_invreq_disable = 0;
5052
5053                                 for (k = 0; k < max_wgp_per_sh; k++) {
5054                                         if (!(wgp_active_bitmap & (1 << k))) {
5055                                                 gcrd_targets_disable_tcp |= 3 << (2 * k);
5056                                                 utcl_invreq_disable |= (3 << (2 * k)) |
5057                                                         (3 << (2 * (max_wgp_per_sh + k)));
5058                                         }
5059                                 }
5060
5061                                 tmp = RREG32_SOC15(GC, 0, mmUTCL1_UTCL0_INVREQ_DISABLE);
5062                                 /* only override TCP & SQC bits */
5063                                 tmp &= 0xffffffff << (4 * max_wgp_per_sh);
5064                                 tmp |= (utcl_invreq_disable & utcl_invreq_disable_mask);
5065                                 WREG32_SOC15(GC, 0, mmUTCL1_UTCL0_INVREQ_DISABLE, tmp);
5066
5067                                 tmp = RREG32_SOC15(GC, 0, mmGCRD_SA_TARGETS_DISABLE);
5068                                 /* only override TCP bits */
5069                                 tmp &= 0xffffffff << (2 * max_wgp_per_sh);
5070                                 tmp |= (gcrd_targets_disable_tcp & gcrd_targets_disable_mask);
5071                                 WREG32_SOC15(GC, 0, mmGCRD_SA_TARGETS_DISABLE, tmp);
5072                         }
5073                 }
5074
5075                 gfx_v10_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
5076                 mutex_unlock(&adev->grbm_idx_mutex);
5077         }
5078 }
5079
5080 static void gfx_v10_0_get_tcc_info(struct amdgpu_device *adev)
5081 {
5082         /* TCCs are global (not instanced). */
5083         uint32_t tcc_disable;
5084
5085         if (adev->asic_type >= CHIP_SIENNA_CICHLID) {
5086                 tcc_disable = RREG32_SOC15(GC, 0, mmCGTS_TCC_DISABLE_gc_10_3) |
5087                               RREG32_SOC15(GC, 0, mmCGTS_USER_TCC_DISABLE_gc_10_3);
5088         } else {
5089                 tcc_disable = RREG32_SOC15(GC, 0, mmCGTS_TCC_DISABLE) |
5090                               RREG32_SOC15(GC, 0, mmCGTS_USER_TCC_DISABLE);
5091         }
5092
5093         adev->gfx.config.tcc_disabled_mask =
5094                 REG_GET_FIELD(tcc_disable, CGTS_TCC_DISABLE, TCC_DISABLE) |
5095                 (REG_GET_FIELD(tcc_disable, CGTS_TCC_DISABLE, HI_TCC_DISABLE) << 16);
5096 }
5097
5098 static void gfx_v10_0_constants_init(struct amdgpu_device *adev)
5099 {
5100         u32 tmp;
5101         int i;
5102
5103         WREG32_FIELD15(GC, 0, GRBM_CNTL, READ_TIMEOUT, 0xff);
5104
5105         gfx_v10_0_setup_rb(adev);
5106         gfx_v10_0_get_cu_info(adev, &adev->gfx.cu_info);
5107         gfx_v10_0_get_tcc_info(adev);
5108         adev->gfx.config.pa_sc_tile_steering_override =
5109                 gfx_v10_0_init_pa_sc_tile_steering_override(adev);
5110
5111         /* XXX SH_MEM regs */
5112         /* where to put LDS, scratch, GPUVM in FSA64 space */
5113         mutex_lock(&adev->srbm_mutex);
5114         for (i = 0; i < adev->vm_manager.id_mgr[AMDGPU_GFXHUB_0].num_ids; i++) {
5115                 nv_grbm_select(adev, 0, 0, 0, i);
5116                 /* CP and shaders */
5117                 WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, DEFAULT_SH_MEM_CONFIG);
5118                 if (i != 0) {
5119                         tmp = REG_SET_FIELD(0, SH_MEM_BASES, PRIVATE_BASE,
5120                                 (adev->gmc.private_aperture_start >> 48));
5121                         tmp = REG_SET_FIELD(tmp, SH_MEM_BASES, SHARED_BASE,
5122                                 (adev->gmc.shared_aperture_start >> 48));
5123                         WREG32_SOC15(GC, 0, mmSH_MEM_BASES, tmp);
5124                 }
5125         }
5126         nv_grbm_select(adev, 0, 0, 0, 0);
5127
5128         mutex_unlock(&adev->srbm_mutex);
5129
5130         gfx_v10_0_init_compute_vmid(adev);
5131         gfx_v10_0_init_gds_vmid(adev);
5132
5133 }
5134
5135 static void gfx_v10_0_enable_gui_idle_interrupt(struct amdgpu_device *adev,
5136                                                bool enable)
5137 {
5138         u32 tmp;
5139
5140         if (amdgpu_sriov_vf(adev))
5141                 return;
5142
5143         tmp = RREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0);
5144
5145         tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE,
5146                             enable ? 1 : 0);
5147         tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE,
5148                             enable ? 1 : 0);
5149         tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE,
5150                             enable ? 1 : 0);
5151         tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, GFX_IDLE_INT_ENABLE,
5152                             enable ? 1 : 0);
5153
5154         WREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0, tmp);
5155 }
5156
5157 static int gfx_v10_0_init_csb(struct amdgpu_device *adev)
5158 {
5159         adev->gfx.rlc.funcs->get_csb_buffer(adev, adev->gfx.rlc.cs_ptr);
5160
5161         /* csib */
5162         if (adev->asic_type == CHIP_NAVI12) {
5163                 WREG32_SOC15_RLC(GC, 0, mmRLC_CSIB_ADDR_HI,
5164                                 adev->gfx.rlc.clear_state_gpu_addr >> 32);
5165                 WREG32_SOC15_RLC(GC, 0, mmRLC_CSIB_ADDR_LO,
5166                                 adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc);
5167                 WREG32_SOC15_RLC(GC, 0, mmRLC_CSIB_LENGTH, adev->gfx.rlc.clear_state_size);
5168         } else {
5169                 WREG32_SOC15(GC, 0, mmRLC_CSIB_ADDR_HI,
5170                                 adev->gfx.rlc.clear_state_gpu_addr >> 32);
5171                 WREG32_SOC15(GC, 0, mmRLC_CSIB_ADDR_LO,
5172                                 adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc);
5173                 WREG32_SOC15(GC, 0, mmRLC_CSIB_LENGTH, adev->gfx.rlc.clear_state_size);
5174         }
5175         return 0;
5176 }
5177
5178 static void gfx_v10_0_rlc_stop(struct amdgpu_device *adev)
5179 {
5180         u32 tmp = RREG32_SOC15(GC, 0, mmRLC_CNTL);
5181
5182         tmp = REG_SET_FIELD(tmp, RLC_CNTL, RLC_ENABLE_F32, 0);
5183         WREG32_SOC15(GC, 0, mmRLC_CNTL, tmp);
5184 }
5185
5186 static void gfx_v10_0_rlc_reset(struct amdgpu_device *adev)
5187 {
5188         WREG32_FIELD15(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 1);
5189         udelay(50);
5190         WREG32_FIELD15(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 0);
5191         udelay(50);
5192 }
5193
5194 static void gfx_v10_0_rlc_smu_handshake_cntl(struct amdgpu_device *adev,
5195                                              bool enable)
5196 {
5197         uint32_t rlc_pg_cntl;
5198
5199         rlc_pg_cntl = RREG32_SOC15(GC, 0, mmRLC_PG_CNTL);
5200
5201         if (!enable) {
5202                 /* RLC_PG_CNTL[23] = 0 (default)
5203                  * RLC will wait for handshake acks with SMU
5204                  * GFXOFF will be enabled
5205                  * RLC_PG_CNTL[23] = 1
5206                  * RLC will not issue any message to SMU
5207                  * hence no handshake between SMU & RLC
5208                  * GFXOFF will be disabled
5209                  */
5210                 rlc_pg_cntl |= 0x800000;
5211         } else
5212                 rlc_pg_cntl &= ~0x800000;
5213         WREG32_SOC15(GC, 0, mmRLC_PG_CNTL, rlc_pg_cntl);
5214 }
5215
5216 static void gfx_v10_0_rlc_start(struct amdgpu_device *adev)
5217 {
5218         /* TODO: enable rlc & smu handshake until smu
5219          * and gfxoff feature works as expected */
5220         if (!(amdgpu_pp_feature_mask & PP_GFXOFF_MASK))
5221                 gfx_v10_0_rlc_smu_handshake_cntl(adev, false);
5222
5223         WREG32_FIELD15(GC, 0, RLC_CNTL, RLC_ENABLE_F32, 1);
5224         udelay(50);
5225 }
5226
5227 static void gfx_v10_0_rlc_enable_srm(struct amdgpu_device *adev)
5228 {
5229         uint32_t tmp;
5230
5231         /* enable Save Restore Machine */
5232         tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_CNTL));
5233         tmp |= RLC_SRM_CNTL__AUTO_INCR_ADDR_MASK;
5234         tmp |= RLC_SRM_CNTL__SRM_ENABLE_MASK;
5235         WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_CNTL), tmp);
5236 }
5237
5238 static int gfx_v10_0_rlc_load_microcode(struct amdgpu_device *adev)
5239 {
5240         const struct rlc_firmware_header_v2_0 *hdr;
5241         const __le32 *fw_data;
5242         unsigned i, fw_size;
5243
5244         if (!adev->gfx.rlc_fw)
5245                 return -EINVAL;
5246
5247         hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data;
5248         amdgpu_ucode_print_rlc_hdr(&hdr->header);
5249
5250         fw_data = (const __le32 *)(adev->gfx.rlc_fw->data +
5251                            le32_to_cpu(hdr->header.ucode_array_offset_bytes));
5252         fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
5253
5254         WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_ADDR,
5255                      RLCG_UCODE_LOADING_START_ADDRESS);
5256
5257         for (i = 0; i < fw_size; i++)
5258                 WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_DATA,
5259                              le32_to_cpup(fw_data++));
5260
5261         WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_ADDR, adev->gfx.rlc_fw_version);
5262
5263         return 0;
5264 }
5265
5266 static int gfx_v10_0_rlc_resume(struct amdgpu_device *adev)
5267 {
5268         int r;
5269
5270         if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
5271
5272                 r = gfx_v10_0_wait_for_rlc_autoload_complete(adev);
5273                 if (r)
5274                         return r;
5275
5276                 gfx_v10_0_init_csb(adev);
5277
5278                 if (!amdgpu_sriov_vf(adev)) /* enable RLC SRM */
5279                         gfx_v10_0_rlc_enable_srm(adev);
5280         } else {
5281                 if (amdgpu_sriov_vf(adev)) {
5282                         gfx_v10_0_init_csb(adev);
5283                         return 0;
5284                 }
5285
5286                 adev->gfx.rlc.funcs->stop(adev);
5287
5288                 /* disable CG */
5289                 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, 0);
5290
5291                 /* disable PG */
5292                 WREG32_SOC15(GC, 0, mmRLC_PG_CNTL, 0);
5293
5294                 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
5295                         /* legacy rlc firmware loading */
5296                         r = gfx_v10_0_rlc_load_microcode(adev);
5297                         if (r)
5298                                 return r;
5299                 } else if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) {
5300                         /* rlc backdoor autoload firmware */
5301                         r = gfx_v10_0_rlc_backdoor_autoload_enable(adev);
5302                         if (r)
5303                                 return r;
5304                 }
5305
5306                 gfx_v10_0_init_csb(adev);
5307
5308                 adev->gfx.rlc.funcs->start(adev);
5309
5310                 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) {
5311                         r = gfx_v10_0_wait_for_rlc_autoload_complete(adev);
5312                         if (r)
5313                                 return r;
5314                 }
5315         }
5316         return 0;
5317 }
5318
5319 static struct {
5320         FIRMWARE_ID     id;
5321         unsigned int    offset;
5322         unsigned int    size;
5323 } rlc_autoload_info[FIRMWARE_ID_MAX];
5324
5325 static int gfx_v10_0_parse_rlc_toc(struct amdgpu_device *adev)
5326 {
5327         int ret;
5328         RLC_TABLE_OF_CONTENT *rlc_toc;
5329
5330         ret = amdgpu_bo_create_reserved(adev, adev->psp.toc_bin_size, PAGE_SIZE,
5331                                         AMDGPU_GEM_DOMAIN_GTT,
5332                                         &adev->gfx.rlc.rlc_toc_bo,
5333                                         &adev->gfx.rlc.rlc_toc_gpu_addr,
5334                                         (void **)&adev->gfx.rlc.rlc_toc_buf);
5335         if (ret) {
5336                 dev_err(adev->dev, "(%d) failed to create rlc toc bo\n", ret);
5337                 return ret;
5338         }
5339
5340         /* Copy toc from psp sos fw to rlc toc buffer */
5341         memcpy(adev->gfx.rlc.rlc_toc_buf, adev->psp.toc_start_addr, adev->psp.toc_bin_size);
5342
5343         rlc_toc = (RLC_TABLE_OF_CONTENT *)adev->gfx.rlc.rlc_toc_buf;
5344         while (rlc_toc && (rlc_toc->id > FIRMWARE_ID_INVALID) &&
5345                 (rlc_toc->id < FIRMWARE_ID_MAX)) {
5346                 if ((rlc_toc->id >= FIRMWARE_ID_CP_CE) &&
5347                     (rlc_toc->id <= FIRMWARE_ID_CP_MES)) {
5348                         /* Offset needs 4KB alignment */
5349                         rlc_toc->offset = ALIGN(rlc_toc->offset * 4, PAGE_SIZE);
5350                 }
5351
5352                 rlc_autoload_info[rlc_toc->id].id = rlc_toc->id;
5353                 rlc_autoload_info[rlc_toc->id].offset = rlc_toc->offset * 4;
5354                 rlc_autoload_info[rlc_toc->id].size = rlc_toc->size * 4;
5355
5356                 rlc_toc++;
5357         }
5358
5359         return 0;
5360 }
5361
5362 static uint32_t gfx_v10_0_calc_toc_total_size(struct amdgpu_device *adev)
5363 {
5364         uint32_t total_size = 0;
5365         FIRMWARE_ID id;
5366         int ret;
5367
5368         ret = gfx_v10_0_parse_rlc_toc(adev);
5369         if (ret) {
5370                 dev_err(adev->dev, "failed to parse rlc toc\n");
5371                 return 0;
5372         }
5373
5374         for (id = FIRMWARE_ID_RLC_G_UCODE; id < FIRMWARE_ID_MAX; id++)
5375                 total_size += rlc_autoload_info[id].size;
5376
5377         /* In case the offset in rlc toc ucode is aligned */
5378         if (total_size < rlc_autoload_info[FIRMWARE_ID_MAX-1].offset)
5379                 total_size = rlc_autoload_info[FIRMWARE_ID_MAX-1].offset +
5380                                 rlc_autoload_info[FIRMWARE_ID_MAX-1].size;
5381
5382         return total_size;
5383 }
5384
5385 static int gfx_v10_0_rlc_backdoor_autoload_buffer_init(struct amdgpu_device *adev)
5386 {
5387         int r;
5388         uint32_t total_size;
5389
5390         total_size = gfx_v10_0_calc_toc_total_size(adev);
5391
5392         r = amdgpu_bo_create_reserved(adev, total_size, PAGE_SIZE,
5393                                       AMDGPU_GEM_DOMAIN_GTT,
5394                                       &adev->gfx.rlc.rlc_autoload_bo,
5395                                       &adev->gfx.rlc.rlc_autoload_gpu_addr,
5396                                       (void **)&adev->gfx.rlc.rlc_autoload_ptr);
5397         if (r) {
5398                 dev_err(adev->dev, "(%d) failed to create fw autoload bo\n", r);
5399                 return r;
5400         }
5401
5402         return 0;
5403 }
5404
5405 static void gfx_v10_0_rlc_backdoor_autoload_buffer_fini(struct amdgpu_device *adev)
5406 {
5407         amdgpu_bo_free_kernel(&adev->gfx.rlc.rlc_toc_bo,
5408                               &adev->gfx.rlc.rlc_toc_gpu_addr,
5409                               (void **)&adev->gfx.rlc.rlc_toc_buf);
5410         amdgpu_bo_free_kernel(&adev->gfx.rlc.rlc_autoload_bo,
5411                               &adev->gfx.rlc.rlc_autoload_gpu_addr,
5412                               (void **)&adev->gfx.rlc.rlc_autoload_ptr);
5413 }
5414
5415 static void gfx_v10_0_rlc_backdoor_autoload_copy_ucode(struct amdgpu_device *adev,
5416                                                        FIRMWARE_ID id,
5417                                                        const void *fw_data,
5418                                                        uint32_t fw_size)
5419 {
5420         uint32_t toc_offset;
5421         uint32_t toc_fw_size;
5422         char *ptr = adev->gfx.rlc.rlc_autoload_ptr;
5423
5424         if (id <= FIRMWARE_ID_INVALID || id >= FIRMWARE_ID_MAX)
5425                 return;
5426
5427         toc_offset = rlc_autoload_info[id].offset;
5428         toc_fw_size = rlc_autoload_info[id].size;
5429
5430         if (fw_size == 0)
5431                 fw_size = toc_fw_size;
5432
5433         if (fw_size > toc_fw_size)
5434                 fw_size = toc_fw_size;
5435
5436         memcpy(ptr + toc_offset, fw_data, fw_size);
5437
5438         if (fw_size < toc_fw_size)
5439                 memset(ptr + toc_offset + fw_size, 0, toc_fw_size - fw_size);
5440 }
5441
5442 static void gfx_v10_0_rlc_backdoor_autoload_copy_toc_ucode(struct amdgpu_device *adev)
5443 {
5444         void *data;
5445         uint32_t size;
5446
5447         data = adev->gfx.rlc.rlc_toc_buf;
5448         size = rlc_autoload_info[FIRMWARE_ID_RLC_TOC].size;
5449
5450         gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5451                                                    FIRMWARE_ID_RLC_TOC,
5452                                                    data, size);
5453 }
5454
5455 static void gfx_v10_0_rlc_backdoor_autoload_copy_gfx_ucode(struct amdgpu_device *adev)
5456 {
5457         const __le32 *fw_data;
5458         uint32_t fw_size;
5459         const struct gfx_firmware_header_v1_0 *cp_hdr;
5460         const struct rlc_firmware_header_v2_0 *rlc_hdr;
5461
5462         /* pfp ucode */
5463         cp_hdr = (const struct gfx_firmware_header_v1_0 *)
5464                 adev->gfx.pfp_fw->data;
5465         fw_data = (const __le32 *)(adev->gfx.pfp_fw->data +
5466                 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes));
5467         fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes);
5468         gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5469                                                    FIRMWARE_ID_CP_PFP,
5470                                                    fw_data, fw_size);
5471
5472         /* ce ucode */
5473         cp_hdr = (const struct gfx_firmware_header_v1_0 *)
5474                 adev->gfx.ce_fw->data;
5475         fw_data = (const __le32 *)(adev->gfx.ce_fw->data +
5476                 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes));
5477         fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes);
5478         gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5479                                                    FIRMWARE_ID_CP_CE,
5480                                                    fw_data, fw_size);
5481
5482         /* me ucode */
5483         cp_hdr = (const struct gfx_firmware_header_v1_0 *)
5484                 adev->gfx.me_fw->data;
5485         fw_data = (const __le32 *)(adev->gfx.me_fw->data +
5486                 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes));
5487         fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes);
5488         gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5489                                                    FIRMWARE_ID_CP_ME,
5490                                                    fw_data, fw_size);
5491
5492         /* rlc ucode */
5493         rlc_hdr = (const struct rlc_firmware_header_v2_0 *)
5494                 adev->gfx.rlc_fw->data;
5495         fw_data = (const __le32 *)(adev->gfx.rlc_fw->data +
5496                 le32_to_cpu(rlc_hdr->header.ucode_array_offset_bytes));
5497         fw_size = le32_to_cpu(rlc_hdr->header.ucode_size_bytes);
5498         gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5499                                                    FIRMWARE_ID_RLC_G_UCODE,
5500                                                    fw_data, fw_size);
5501
5502         /* mec1 ucode */
5503         cp_hdr = (const struct gfx_firmware_header_v1_0 *)
5504                 adev->gfx.mec_fw->data;
5505         fw_data = (const __le32 *) (adev->gfx.mec_fw->data +
5506                 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes));
5507         fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes) -
5508                 cp_hdr->jt_size * 4;
5509         gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5510                                                    FIRMWARE_ID_CP_MEC,
5511                                                    fw_data, fw_size);
5512         /* mec2 ucode is not necessary if mec2 ucode is same as mec1 */
5513 }
5514
5515 /* Temporarily put sdma part here */
5516 static void gfx_v10_0_rlc_backdoor_autoload_copy_sdma_ucode(struct amdgpu_device *adev)
5517 {
5518         const __le32 *fw_data;
5519         uint32_t fw_size;
5520         const struct sdma_firmware_header_v1_0 *sdma_hdr;
5521         int i;
5522
5523         for (i = 0; i < adev->sdma.num_instances; i++) {
5524                 sdma_hdr = (const struct sdma_firmware_header_v1_0 *)
5525                         adev->sdma.instance[i].fw->data;
5526                 fw_data = (const __le32 *) (adev->sdma.instance[i].fw->data +
5527                         le32_to_cpu(sdma_hdr->header.ucode_array_offset_bytes));
5528                 fw_size = le32_to_cpu(sdma_hdr->header.ucode_size_bytes);
5529
5530                 if (i == 0) {
5531                         gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5532                                 FIRMWARE_ID_SDMA0_UCODE, fw_data, fw_size);
5533                         gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5534                                 FIRMWARE_ID_SDMA0_JT,
5535                                 (uint32_t *)fw_data +
5536                                 sdma_hdr->jt_offset,
5537                                 sdma_hdr->jt_size * 4);
5538                 } else if (i == 1) {
5539                         gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5540                                 FIRMWARE_ID_SDMA1_UCODE, fw_data, fw_size);
5541                         gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5542                                 FIRMWARE_ID_SDMA1_JT,
5543                                 (uint32_t *)fw_data +
5544                                 sdma_hdr->jt_offset,
5545                                 sdma_hdr->jt_size * 4);
5546                 }
5547         }
5548 }
5549
5550 static int gfx_v10_0_rlc_backdoor_autoload_enable(struct amdgpu_device *adev)
5551 {
5552         uint32_t rlc_g_offset, rlc_g_size, tmp;
5553         uint64_t gpu_addr;
5554
5555         gfx_v10_0_rlc_backdoor_autoload_copy_toc_ucode(adev);
5556         gfx_v10_0_rlc_backdoor_autoload_copy_sdma_ucode(adev);
5557         gfx_v10_0_rlc_backdoor_autoload_copy_gfx_ucode(adev);
5558
5559         rlc_g_offset = rlc_autoload_info[FIRMWARE_ID_RLC_G_UCODE].offset;
5560         rlc_g_size = rlc_autoload_info[FIRMWARE_ID_RLC_G_UCODE].size;
5561         gpu_addr = adev->gfx.rlc.rlc_autoload_gpu_addr + rlc_g_offset;
5562
5563         WREG32_SOC15(GC, 0, mmRLC_HYP_BOOTLOAD_ADDR_HI, upper_32_bits(gpu_addr));
5564         WREG32_SOC15(GC, 0, mmRLC_HYP_BOOTLOAD_ADDR_LO, lower_32_bits(gpu_addr));
5565         WREG32_SOC15(GC, 0, mmRLC_HYP_BOOTLOAD_SIZE, rlc_g_size);
5566
5567         tmp = RREG32_SOC15(GC, 0, mmRLC_HYP_RESET_VECTOR);
5568         if (!(tmp & (RLC_HYP_RESET_VECTOR__COLD_BOOT_EXIT_MASK |
5569                    RLC_HYP_RESET_VECTOR__VDDGFX_EXIT_MASK))) {
5570                 DRM_ERROR("Neither COLD_BOOT_EXIT nor VDDGFX_EXIT is set\n");
5571                 return -EINVAL;
5572         }
5573
5574         tmp = RREG32_SOC15(GC, 0, mmRLC_CNTL);
5575         if (tmp & RLC_CNTL__RLC_ENABLE_F32_MASK) {
5576                 DRM_ERROR("RLC ROM should halt itself\n");
5577                 return -EINVAL;
5578         }
5579
5580         return 0;
5581 }
5582
5583 static int gfx_v10_0_rlc_backdoor_autoload_config_me_cache(struct amdgpu_device *adev)
5584 {
5585         uint32_t usec_timeout = 50000;  /* wait for 50ms */
5586         uint32_t tmp;
5587         int i;
5588         uint64_t addr;
5589
5590         /* Trigger an invalidation of the L1 instruction caches */
5591         tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL);
5592         tmp = REG_SET_FIELD(tmp, CP_ME_IC_OP_CNTL, INVALIDATE_CACHE, 1);
5593         WREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL, tmp);
5594
5595         /* Wait for invalidation complete */
5596         for (i = 0; i < usec_timeout; i++) {
5597                 tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL);
5598                 if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL,
5599                         INVALIDATE_CACHE_COMPLETE))
5600                         break;
5601                 udelay(1);
5602         }
5603
5604         if (i >= usec_timeout) {
5605                 dev_err(adev->dev, "failed to invalidate instruction cache\n");
5606                 return -EINVAL;
5607         }
5608
5609         /* Program me ucode address into intruction cache address register */
5610         addr = adev->gfx.rlc.rlc_autoload_gpu_addr +
5611                 rlc_autoload_info[FIRMWARE_ID_CP_ME].offset;
5612         WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_LO,
5613                         lower_32_bits(addr) & 0xFFFFF000);
5614         WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_HI,
5615                         upper_32_bits(addr));
5616
5617         return 0;
5618 }
5619
5620 static int gfx_v10_0_rlc_backdoor_autoload_config_ce_cache(struct amdgpu_device *adev)
5621 {
5622         uint32_t usec_timeout = 50000;  /* wait for 50ms */
5623         uint32_t tmp;
5624         int i;
5625         uint64_t addr;
5626
5627         /* Trigger an invalidation of the L1 instruction caches */
5628         tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL);
5629         tmp = REG_SET_FIELD(tmp, CP_CE_IC_OP_CNTL, INVALIDATE_CACHE, 1);
5630         WREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL, tmp);
5631
5632         /* Wait for invalidation complete */
5633         for (i = 0; i < usec_timeout; i++) {
5634                 tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL);
5635                 if (1 == REG_GET_FIELD(tmp, CP_CE_IC_OP_CNTL,
5636                         INVALIDATE_CACHE_COMPLETE))
5637                         break;
5638                 udelay(1);
5639         }
5640
5641         if (i >= usec_timeout) {
5642                 dev_err(adev->dev, "failed to invalidate instruction cache\n");
5643                 return -EINVAL;
5644         }
5645
5646         /* Program ce ucode address into intruction cache address register */
5647         addr = adev->gfx.rlc.rlc_autoload_gpu_addr +
5648                 rlc_autoload_info[FIRMWARE_ID_CP_CE].offset;
5649         WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_LO,
5650                         lower_32_bits(addr) & 0xFFFFF000);
5651         WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_HI,
5652                         upper_32_bits(addr));
5653
5654         return 0;
5655 }
5656
5657 static int gfx_v10_0_rlc_backdoor_autoload_config_pfp_cache(struct amdgpu_device *adev)
5658 {
5659         uint32_t usec_timeout = 50000;  /* wait for 50ms */
5660         uint32_t tmp;
5661         int i;
5662         uint64_t addr;
5663
5664         /* Trigger an invalidation of the L1 instruction caches */
5665         tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL);
5666         tmp = REG_SET_FIELD(tmp, CP_PFP_IC_OP_CNTL, INVALIDATE_CACHE, 1);
5667         WREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL, tmp);
5668
5669         /* Wait for invalidation complete */
5670         for (i = 0; i < usec_timeout; i++) {
5671                 tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL);
5672                 if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL,
5673                         INVALIDATE_CACHE_COMPLETE))
5674                         break;
5675                 udelay(1);
5676         }
5677
5678         if (i >= usec_timeout) {
5679                 dev_err(adev->dev, "failed to invalidate instruction cache\n");
5680                 return -EINVAL;
5681         }
5682
5683         /* Program pfp ucode address into intruction cache address register */
5684         addr = adev->gfx.rlc.rlc_autoload_gpu_addr +
5685                 rlc_autoload_info[FIRMWARE_ID_CP_PFP].offset;
5686         WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_LO,
5687                         lower_32_bits(addr) & 0xFFFFF000);
5688         WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_HI,
5689                         upper_32_bits(addr));
5690
5691         return 0;
5692 }
5693
5694 static int gfx_v10_0_rlc_backdoor_autoload_config_mec_cache(struct amdgpu_device *adev)
5695 {
5696         uint32_t usec_timeout = 50000;  /* wait for 50ms */
5697         uint32_t tmp;
5698         int i;
5699         uint64_t addr;
5700
5701         /* Trigger an invalidation of the L1 instruction caches */
5702         tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL);
5703         tmp = REG_SET_FIELD(tmp, CP_CPC_IC_OP_CNTL, INVALIDATE_CACHE, 1);
5704         WREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL, tmp);
5705
5706         /* Wait for invalidation complete */
5707         for (i = 0; i < usec_timeout; i++) {
5708                 tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL);
5709                 if (1 == REG_GET_FIELD(tmp, CP_CPC_IC_OP_CNTL,
5710                         INVALIDATE_CACHE_COMPLETE))
5711                         break;
5712                 udelay(1);
5713         }
5714
5715         if (i >= usec_timeout) {
5716                 dev_err(adev->dev, "failed to invalidate instruction cache\n");
5717                 return -EINVAL;
5718         }
5719
5720         /* Program mec1 ucode address into intruction cache address register */
5721         addr = adev->gfx.rlc.rlc_autoload_gpu_addr +
5722                 rlc_autoload_info[FIRMWARE_ID_CP_MEC].offset;
5723         WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_LO,
5724                         lower_32_bits(addr) & 0xFFFFF000);
5725         WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_HI,
5726                         upper_32_bits(addr));
5727
5728         return 0;
5729 }
5730
5731 static int gfx_v10_0_wait_for_rlc_autoload_complete(struct amdgpu_device *adev)
5732 {
5733         uint32_t cp_status;
5734         uint32_t bootload_status;
5735         int i, r;
5736
5737         for (i = 0; i < adev->usec_timeout; i++) {
5738                 cp_status = RREG32_SOC15(GC, 0, mmCP_STAT);
5739                 bootload_status = RREG32_SOC15(GC, 0, mmRLC_RLCS_BOOTLOAD_STATUS);
5740                 if ((cp_status == 0) &&
5741                     (REG_GET_FIELD(bootload_status,
5742                         RLC_RLCS_BOOTLOAD_STATUS, BOOTLOAD_COMPLETE) == 1)) {
5743                         break;
5744                 }
5745                 udelay(1);
5746         }
5747
5748         if (i >= adev->usec_timeout) {
5749                 dev_err(adev->dev, "rlc autoload: gc ucode autoload timeout\n");
5750                 return -ETIMEDOUT;
5751         }
5752
5753         if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) {
5754                 r = gfx_v10_0_rlc_backdoor_autoload_config_me_cache(adev);
5755                 if (r)
5756                         return r;
5757
5758                 r = gfx_v10_0_rlc_backdoor_autoload_config_ce_cache(adev);
5759                 if (r)
5760                         return r;
5761
5762                 r = gfx_v10_0_rlc_backdoor_autoload_config_pfp_cache(adev);
5763                 if (r)
5764                         return r;
5765
5766                 r = gfx_v10_0_rlc_backdoor_autoload_config_mec_cache(adev);
5767                 if (r)
5768                         return r;
5769         }
5770
5771         return 0;
5772 }
5773
5774 static int gfx_v10_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable)
5775 {
5776         int i;
5777         u32 tmp = RREG32_SOC15(GC, 0, mmCP_ME_CNTL);
5778
5779         tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, enable ? 0 : 1);
5780         tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, enable ? 0 : 1);
5781         tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_HALT, enable ? 0 : 1);
5782
5783         if (adev->asic_type == CHIP_NAVI12) {
5784                 WREG32_SOC15_RLC(GC, 0, mmCP_ME_CNTL, tmp);
5785         } else {
5786                 WREG32_SOC15(GC, 0, mmCP_ME_CNTL, tmp);
5787         }
5788
5789         for (i = 0; i < adev->usec_timeout; i++) {
5790                 if (RREG32_SOC15(GC, 0, mmCP_STAT) == 0)
5791                         break;
5792                 udelay(1);
5793         }
5794
5795         if (i >= adev->usec_timeout)
5796                 DRM_ERROR("failed to %s cp gfx\n", enable ? "unhalt" : "halt");
5797
5798         return 0;
5799 }
5800
5801 static int gfx_v10_0_cp_gfx_load_pfp_microcode(struct amdgpu_device *adev)
5802 {
5803         int r;
5804         const struct gfx_firmware_header_v1_0 *pfp_hdr;
5805         const __le32 *fw_data;
5806         unsigned i, fw_size;
5807         uint32_t tmp;
5808         uint32_t usec_timeout = 50000;  /* wait for 50ms */
5809
5810         pfp_hdr = (const struct gfx_firmware_header_v1_0 *)
5811                 adev->gfx.pfp_fw->data;
5812
5813         amdgpu_ucode_print_gfx_hdr(&pfp_hdr->header);
5814
5815         fw_data = (const __le32 *)(adev->gfx.pfp_fw->data +
5816                 le32_to_cpu(pfp_hdr->header.ucode_array_offset_bytes));
5817         fw_size = le32_to_cpu(pfp_hdr->header.ucode_size_bytes);
5818
5819         r = amdgpu_bo_create_reserved(adev, pfp_hdr->header.ucode_size_bytes,
5820                                       PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,
5821                                       &adev->gfx.pfp.pfp_fw_obj,
5822                                       &adev->gfx.pfp.pfp_fw_gpu_addr,
5823                                       (void **)&adev->gfx.pfp.pfp_fw_ptr);
5824         if (r) {
5825                 dev_err(adev->dev, "(%d) failed to create pfp fw bo\n", r);
5826                 gfx_v10_0_pfp_fini(adev);
5827                 return r;
5828         }
5829
5830         memcpy(adev->gfx.pfp.pfp_fw_ptr, fw_data, fw_size);
5831
5832         amdgpu_bo_kunmap(adev->gfx.pfp.pfp_fw_obj);
5833         amdgpu_bo_unreserve(adev->gfx.pfp.pfp_fw_obj);
5834
5835         /* Trigger an invalidation of the L1 instruction caches */
5836         tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL);
5837         tmp = REG_SET_FIELD(tmp, CP_PFP_IC_OP_CNTL, INVALIDATE_CACHE, 1);
5838         WREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL, tmp);
5839
5840         /* Wait for invalidation complete */
5841         for (i = 0; i < usec_timeout; i++) {
5842                 tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL);
5843                 if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL,
5844                         INVALIDATE_CACHE_COMPLETE))
5845                         break;
5846                 udelay(1);
5847         }
5848
5849         if (i >= usec_timeout) {
5850                 dev_err(adev->dev, "failed to invalidate instruction cache\n");
5851                 return -EINVAL;
5852         }
5853
5854         if (amdgpu_emu_mode == 1)
5855                 adev->hdp.funcs->flush_hdp(adev, NULL);
5856
5857         tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_CNTL);
5858         tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, VMID, 0);
5859         tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, CACHE_POLICY, 0);
5860         tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, EXE_DISABLE, 0);
5861         tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, ADDRESS_CLAMP, 1);
5862         WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_CNTL, tmp);
5863         WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_LO,
5864                 adev->gfx.pfp.pfp_fw_gpu_addr & 0xFFFFF000);
5865         WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_HI,
5866                 upper_32_bits(adev->gfx.pfp.pfp_fw_gpu_addr));
5867
5868         WREG32_SOC15(GC, 0, mmCP_HYP_PFP_UCODE_ADDR, 0);
5869
5870         for (i = 0; i < pfp_hdr->jt_size; i++)
5871                 WREG32_SOC15(GC, 0, mmCP_HYP_PFP_UCODE_DATA,
5872                              le32_to_cpup(fw_data + pfp_hdr->jt_offset + i));
5873
5874         WREG32_SOC15(GC, 0, mmCP_HYP_PFP_UCODE_ADDR, adev->gfx.pfp_fw_version);
5875
5876         return 0;
5877 }
5878
5879 static int gfx_v10_0_cp_gfx_load_ce_microcode(struct amdgpu_device *adev)
5880 {
5881         int r;
5882         const struct gfx_firmware_header_v1_0 *ce_hdr;
5883         const __le32 *fw_data;
5884         unsigned i, fw_size;
5885         uint32_t tmp;
5886         uint32_t usec_timeout = 50000;  /* wait for 50ms */
5887
5888         ce_hdr = (const struct gfx_firmware_header_v1_0 *)
5889                 adev->gfx.ce_fw->data;
5890
5891         amdgpu_ucode_print_gfx_hdr(&ce_hdr->header);
5892
5893         fw_data = (const __le32 *)(adev->gfx.ce_fw->data +
5894                 le32_to_cpu(ce_hdr->header.ucode_array_offset_bytes));
5895         fw_size = le32_to_cpu(ce_hdr->header.ucode_size_bytes);
5896
5897         r = amdgpu_bo_create_reserved(adev, ce_hdr->header.ucode_size_bytes,
5898                                       PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,
5899                                       &adev->gfx.ce.ce_fw_obj,
5900                                       &adev->gfx.ce.ce_fw_gpu_addr,
5901                                       (void **)&adev->gfx.ce.ce_fw_ptr);
5902         if (r) {
5903                 dev_err(adev->dev, "(%d) failed to create ce fw bo\n", r);
5904                 gfx_v10_0_ce_fini(adev);
5905                 return r;
5906         }
5907
5908         memcpy(adev->gfx.ce.ce_fw_ptr, fw_data, fw_size);
5909
5910         amdgpu_bo_kunmap(adev->gfx.ce.ce_fw_obj);
5911         amdgpu_bo_unreserve(adev->gfx.ce.ce_fw_obj);
5912
5913         /* Trigger an invalidation of the L1 instruction caches */
5914         tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL);
5915         tmp = REG_SET_FIELD(tmp, CP_CE_IC_OP_CNTL, INVALIDATE_CACHE, 1);
5916         WREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL, tmp);
5917
5918         /* Wait for invalidation complete */
5919         for (i = 0; i < usec_timeout; i++) {
5920                 tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL);
5921                 if (1 == REG_GET_FIELD(tmp, CP_CE_IC_OP_CNTL,
5922                         INVALIDATE_CACHE_COMPLETE))
5923                         break;
5924                 udelay(1);
5925         }
5926
5927         if (i >= usec_timeout) {
5928                 dev_err(adev->dev, "failed to invalidate instruction cache\n");
5929                 return -EINVAL;
5930         }
5931
5932         if (amdgpu_emu_mode == 1)
5933                 adev->hdp.funcs->flush_hdp(adev, NULL);
5934
5935         tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_CNTL);
5936         tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, VMID, 0);
5937         tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, CACHE_POLICY, 0);
5938         tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, EXE_DISABLE, 0);
5939         tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, ADDRESS_CLAMP, 1);
5940         WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_LO,
5941                 adev->gfx.ce.ce_fw_gpu_addr & 0xFFFFF000);
5942         WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_HI,
5943                 upper_32_bits(adev->gfx.ce.ce_fw_gpu_addr));
5944
5945         WREG32_SOC15(GC, 0, mmCP_HYP_CE_UCODE_ADDR, 0);
5946
5947         for (i = 0; i < ce_hdr->jt_size; i++)
5948                 WREG32_SOC15(GC, 0, mmCP_HYP_CE_UCODE_DATA,
5949                              le32_to_cpup(fw_data + ce_hdr->jt_offset + i));
5950
5951         WREG32_SOC15(GC, 0, mmCP_HYP_CE_UCODE_ADDR, adev->gfx.ce_fw_version);
5952
5953         return 0;
5954 }
5955
5956 static int gfx_v10_0_cp_gfx_load_me_microcode(struct amdgpu_device *adev)
5957 {
5958         int r;
5959         const struct gfx_firmware_header_v1_0 *me_hdr;
5960         const __le32 *fw_data;
5961         unsigned i, fw_size;
5962         uint32_t tmp;
5963         uint32_t usec_timeout = 50000;  /* wait for 50ms */
5964
5965         me_hdr = (const struct gfx_firmware_header_v1_0 *)
5966                 adev->gfx.me_fw->data;
5967
5968         amdgpu_ucode_print_gfx_hdr(&me_hdr->header);
5969
5970         fw_data = (const __le32 *)(adev->gfx.me_fw->data +
5971                 le32_to_cpu(me_hdr->header.ucode_array_offset_bytes));
5972         fw_size = le32_to_cpu(me_hdr->header.ucode_size_bytes);
5973
5974         r = amdgpu_bo_create_reserved(adev, me_hdr->header.ucode_size_bytes,
5975                                       PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,
5976                                       &adev->gfx.me.me_fw_obj,
5977                                       &adev->gfx.me.me_fw_gpu_addr,
5978                                       (void **)&adev->gfx.me.me_fw_ptr);
5979         if (r) {
5980                 dev_err(adev->dev, "(%d) failed to create me fw bo\n", r);
5981                 gfx_v10_0_me_fini(adev);
5982                 return r;
5983         }
5984
5985         memcpy(adev->gfx.me.me_fw_ptr, fw_data, fw_size);
5986
5987         amdgpu_bo_kunmap(adev->gfx.me.me_fw_obj);
5988         amdgpu_bo_unreserve(adev->gfx.me.me_fw_obj);
5989
5990         /* Trigger an invalidation of the L1 instruction caches */
5991         tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL);
5992         tmp = REG_SET_FIELD(tmp, CP_ME_IC_OP_CNTL, INVALIDATE_CACHE, 1);
5993         WREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL, tmp);
5994
5995         /* Wait for invalidation complete */
5996         for (i = 0; i < usec_timeout; i++) {
5997                 tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL);
5998                 if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL,
5999                         INVALIDATE_CACHE_COMPLETE))
6000                         break;
6001                 udelay(1);
6002         }
6003
6004         if (i >= usec_timeout) {
6005                 dev_err(adev->dev, "failed to invalidate instruction cache\n");
6006                 return -EINVAL;
6007         }
6008
6009         if (amdgpu_emu_mode == 1)
6010                 adev->hdp.funcs->flush_hdp(adev, NULL);
6011
6012         tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_CNTL);
6013         tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, VMID, 0);
6014         tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, CACHE_POLICY, 0);
6015         tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, EXE_DISABLE, 0);
6016         tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, ADDRESS_CLAMP, 1);
6017         WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_LO,
6018                 adev->gfx.me.me_fw_gpu_addr & 0xFFFFF000);
6019         WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_HI,
6020                 upper_32_bits(adev->gfx.me.me_fw_gpu_addr));
6021
6022         WREG32_SOC15(GC, 0, mmCP_HYP_ME_UCODE_ADDR, 0);
6023
6024         for (i = 0; i < me_hdr->jt_size; i++)
6025                 WREG32_SOC15(GC, 0, mmCP_HYP_ME_UCODE_DATA,
6026                              le32_to_cpup(fw_data + me_hdr->jt_offset + i));
6027
6028         WREG32_SOC15(GC, 0, mmCP_HYP_ME_UCODE_ADDR, adev->gfx.me_fw_version);
6029
6030         return 0;
6031 }
6032
6033 static int gfx_v10_0_cp_gfx_load_microcode(struct amdgpu_device *adev)
6034 {
6035         int r;
6036
6037         if (!adev->gfx.me_fw || !adev->gfx.pfp_fw || !adev->gfx.ce_fw)
6038                 return -EINVAL;
6039
6040         gfx_v10_0_cp_gfx_enable(adev, false);
6041
6042         r = gfx_v10_0_cp_gfx_load_pfp_microcode(adev);
6043         if (r) {
6044                 dev_err(adev->dev, "(%d) failed to load pfp fw\n", r);
6045                 return r;
6046         }
6047
6048         r = gfx_v10_0_cp_gfx_load_ce_microcode(adev);
6049         if (r) {
6050                 dev_err(adev->dev, "(%d) failed to load ce fw\n", r);
6051                 return r;
6052         }
6053
6054         r = gfx_v10_0_cp_gfx_load_me_microcode(adev);
6055         if (r) {
6056                 dev_err(adev->dev, "(%d) failed to load me fw\n", r);
6057                 return r;
6058         }
6059
6060         return 0;
6061 }
6062
6063 static int gfx_v10_0_cp_gfx_start(struct amdgpu_device *adev)
6064 {
6065         struct amdgpu_ring *ring;
6066         const struct cs_section_def *sect = NULL;
6067         const struct cs_extent_def *ext = NULL;
6068         int r, i;
6069         int ctx_reg_offset;
6070
6071         /* init the CP */
6072         WREG32_SOC15(GC, 0, mmCP_MAX_CONTEXT,
6073                      adev->gfx.config.max_hw_contexts - 1);
6074         WREG32_SOC15(GC, 0, mmCP_DEVICE_ID, 1);
6075
6076         gfx_v10_0_cp_gfx_enable(adev, true);
6077
6078         ring = &adev->gfx.gfx_ring[0];
6079         r = amdgpu_ring_alloc(ring, gfx_v10_0_get_csb_size(adev) + 4);
6080         if (r) {
6081                 DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r);
6082                 return r;
6083         }
6084
6085         amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
6086         amdgpu_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
6087
6088         amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1));
6089         amdgpu_ring_write(ring, 0x80000000);
6090         amdgpu_ring_write(ring, 0x80000000);
6091
6092         for (sect = gfx10_cs_data; sect->section != NULL; ++sect) {
6093                 for (ext = sect->section; ext->extent != NULL; ++ext) {
6094                         if (sect->id == SECT_CONTEXT) {
6095                                 amdgpu_ring_write(ring,
6096                                                   PACKET3(PACKET3_SET_CONTEXT_REG,
6097                                                           ext->reg_count));
6098                                 amdgpu_ring_write(ring, ext->reg_index -
6099                                                   PACKET3_SET_CONTEXT_REG_START);
6100                                 for (i = 0; i < ext->reg_count; i++)
6101                                         amdgpu_ring_write(ring, ext->extent[i]);
6102                         }
6103                 }
6104         }
6105
6106         ctx_reg_offset =
6107                 SOC15_REG_OFFSET(GC, 0, mmPA_SC_TILE_STEERING_OVERRIDE) - PACKET3_SET_CONTEXT_REG_START;
6108         amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
6109         amdgpu_ring_write(ring, ctx_reg_offset);
6110         amdgpu_ring_write(ring, adev->gfx.config.pa_sc_tile_steering_override);
6111
6112         amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
6113         amdgpu_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE);
6114
6115         amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));
6116         amdgpu_ring_write(ring, 0);
6117
6118         amdgpu_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2));
6119         amdgpu_ring_write(ring, PACKET3_BASE_INDEX(CE_PARTITION_BASE));
6120         amdgpu_ring_write(ring, 0x8000);
6121         amdgpu_ring_write(ring, 0x8000);
6122
6123         amdgpu_ring_commit(ring);
6124
6125         /* submit cs packet to copy state 0 to next available state */
6126         if (adev->gfx.num_gfx_rings > 1) {
6127                 /* maximum supported gfx ring is 2 */
6128                 ring = &adev->gfx.gfx_ring[1];
6129                 r = amdgpu_ring_alloc(ring, 2);
6130                 if (r) {
6131                         DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r);
6132                         return r;
6133                 }
6134
6135                 amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));
6136                 amdgpu_ring_write(ring, 0);
6137
6138                 amdgpu_ring_commit(ring);
6139         }
6140         return 0;
6141 }
6142
6143 static void gfx_v10_0_cp_gfx_switch_pipe(struct amdgpu_device *adev,
6144                                          CP_PIPE_ID pipe)
6145 {
6146         u32 tmp;
6147
6148         tmp = RREG32_SOC15(GC, 0, mmGRBM_GFX_CNTL);
6149         tmp = REG_SET_FIELD(tmp, GRBM_GFX_CNTL, PIPEID, pipe);
6150
6151         WREG32_SOC15(GC, 0, mmGRBM_GFX_CNTL, tmp);
6152 }
6153
6154 static void gfx_v10_0_cp_gfx_set_doorbell(struct amdgpu_device *adev,
6155                                           struct amdgpu_ring *ring)
6156 {
6157         u32 tmp;
6158
6159         if (!amdgpu_async_gfx_ring) {
6160                 tmp = RREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL);
6161                 if (ring->use_doorbell) {
6162                         tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
6163                                                 DOORBELL_OFFSET, ring->doorbell_index);
6164                         tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
6165                                                 DOORBELL_EN, 1);
6166                 } else {
6167                         tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
6168                                                 DOORBELL_EN, 0);
6169                 }
6170                 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL, tmp);
6171         }
6172         switch (adev->asic_type) {
6173         case CHIP_SIENNA_CICHLID:
6174         case CHIP_NAVY_FLOUNDER:
6175         case CHIP_VANGOGH:
6176         case CHIP_DIMGREY_CAVEFISH:
6177         case CHIP_BEIGE_GOBY:
6178                 tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER,
6179                                     DOORBELL_RANGE_LOWER_Sienna_Cichlid, ring->doorbell_index);
6180                 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_LOWER, tmp);
6181
6182                 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_UPPER,
6183                              CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_Sienna_Cichlid_MASK);
6184                 break;
6185         default:
6186                 tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER,
6187                                     DOORBELL_RANGE_LOWER, ring->doorbell_index);
6188                 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_LOWER, tmp);
6189
6190                 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_UPPER,
6191                              CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_MASK);
6192                 break;
6193         }
6194 }
6195
6196 static int gfx_v10_0_cp_gfx_resume(struct amdgpu_device *adev)
6197 {
6198         struct amdgpu_ring *ring;
6199         u32 tmp;
6200         u32 rb_bufsz;
6201         u64 rb_addr, rptr_addr, wptr_gpu_addr;
6202         u32 i;
6203
6204         /* Set the write pointer delay */
6205         WREG32_SOC15(GC, 0, mmCP_RB_WPTR_DELAY, 0);
6206
6207         /* set the RB to use vmid 0 */
6208         WREG32_SOC15(GC, 0, mmCP_RB_VMID, 0);
6209
6210         /* Init gfx ring 0 for pipe 0 */
6211         mutex_lock(&adev->srbm_mutex);
6212         gfx_v10_0_cp_gfx_switch_pipe(adev, PIPE_ID0);
6213
6214         /* Set ring buffer size */
6215         ring = &adev->gfx.gfx_ring[0];
6216         rb_bufsz = order_base_2(ring->ring_size / 8);
6217         tmp = REG_SET_FIELD(0, CP_RB0_CNTL, RB_BUFSZ, rb_bufsz);
6218         tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, RB_BLKSZ, rb_bufsz - 2);
6219 #ifdef __BIG_ENDIAN
6220         tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, BUF_SWAP, 1);
6221 #endif
6222         WREG32_SOC15(GC, 0, mmCP_RB0_CNTL, tmp);
6223
6224         /* Initialize the ring buffer's write pointers */
6225         ring->wptr = 0;
6226         WREG32_SOC15(GC, 0, mmCP_RB0_WPTR, lower_32_bits(ring->wptr));
6227         WREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI, upper_32_bits(ring->wptr));
6228
6229         /* set the wb address wether it's enabled or not */
6230         rptr_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
6231         WREG32_SOC15(GC, 0, mmCP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr));
6232         WREG32_SOC15(GC, 0, mmCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) &
6233                      CP_RB_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK);
6234
6235         wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
6236         WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_LO,
6237                      lower_32_bits(wptr_gpu_addr));
6238         WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI,
6239                      upper_32_bits(wptr_gpu_addr));
6240
6241         mdelay(1);
6242         WREG32_SOC15(GC, 0, mmCP_RB0_CNTL, tmp);
6243
6244         rb_addr = ring->gpu_addr >> 8;
6245         WREG32_SOC15(GC, 0, mmCP_RB0_BASE, rb_addr);
6246         WREG32_SOC15(GC, 0, mmCP_RB0_BASE_HI, upper_32_bits(rb_addr));
6247
6248         WREG32_SOC15(GC, 0, mmCP_RB_ACTIVE, 1);
6249
6250         gfx_v10_0_cp_gfx_set_doorbell(adev, ring);
6251         mutex_unlock(&adev->srbm_mutex);
6252
6253         /* Init gfx ring 1 for pipe 1 */
6254         if (adev->gfx.num_gfx_rings > 1) {
6255                 mutex_lock(&adev->srbm_mutex);
6256                 gfx_v10_0_cp_gfx_switch_pipe(adev, PIPE_ID1);
6257                 /* maximum supported gfx ring is 2 */
6258                 ring = &adev->gfx.gfx_ring[1];
6259                 rb_bufsz = order_base_2(ring->ring_size / 8);
6260                 tmp = REG_SET_FIELD(0, CP_RB1_CNTL, RB_BUFSZ, rb_bufsz);
6261                 tmp = REG_SET_FIELD(tmp, CP_RB1_CNTL, RB_BLKSZ, rb_bufsz - 2);
6262                 WREG32_SOC15(GC, 0, mmCP_RB1_CNTL, tmp);
6263                 /* Initialize the ring buffer's write pointers */
6264                 ring->wptr = 0;
6265                 WREG32_SOC15(GC, 0, mmCP_RB1_WPTR, lower_32_bits(ring->wptr));
6266                 WREG32_SOC15(GC, 0, mmCP_RB1_WPTR_HI, upper_32_bits(ring->wptr));
6267                 /* Set the wb address wether it's enabled or not */
6268                 rptr_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
6269                 WREG32_SOC15(GC, 0, mmCP_RB1_RPTR_ADDR, lower_32_bits(rptr_addr));
6270                 WREG32_SOC15(GC, 0, mmCP_RB1_RPTR_ADDR_HI, upper_32_bits(rptr_addr) &
6271                              CP_RB1_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK);
6272                 wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
6273                 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_LO,
6274                              lower_32_bits(wptr_gpu_addr));
6275                 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI,
6276                              upper_32_bits(wptr_gpu_addr));
6277
6278                 mdelay(1);
6279                 WREG32_SOC15(GC, 0, mmCP_RB1_CNTL, tmp);
6280
6281                 rb_addr = ring->gpu_addr >> 8;
6282                 WREG32_SOC15(GC, 0, mmCP_RB1_BASE, rb_addr);
6283                 WREG32_SOC15(GC, 0, mmCP_RB1_BASE_HI, upper_32_bits(rb_addr));
6284                 WREG32_SOC15(GC, 0, mmCP_RB1_ACTIVE, 1);
6285
6286                 gfx_v10_0_cp_gfx_set_doorbell(adev, ring);
6287                 mutex_unlock(&adev->srbm_mutex);
6288         }
6289         /* Switch to pipe 0 */
6290         mutex_lock(&adev->srbm_mutex);
6291         gfx_v10_0_cp_gfx_switch_pipe(adev, PIPE_ID0);
6292         mutex_unlock(&adev->srbm_mutex);
6293
6294         /* start the ring */
6295         gfx_v10_0_cp_gfx_start(adev);
6296
6297         for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
6298                 ring = &adev->gfx.gfx_ring[i];
6299                 ring->sched.ready = true;
6300         }
6301
6302         return 0;
6303 }
6304
6305 static void gfx_v10_0_cp_compute_enable(struct amdgpu_device *adev, bool enable)
6306 {
6307         if (enable) {
6308                 switch (adev->asic_type) {
6309                 case CHIP_SIENNA_CICHLID:
6310                 case CHIP_NAVY_FLOUNDER:
6311                 case CHIP_VANGOGH:
6312                 case CHIP_DIMGREY_CAVEFISH:
6313                 case CHIP_BEIGE_GOBY:
6314                         WREG32_SOC15(GC, 0, mmCP_MEC_CNTL_Sienna_Cichlid, 0);
6315                         break;
6316                 default:
6317                         WREG32_SOC15(GC, 0, mmCP_MEC_CNTL, 0);
6318                         break;
6319                 }
6320         } else {
6321                 switch (adev->asic_type) {
6322                 case CHIP_SIENNA_CICHLID:
6323                 case CHIP_NAVY_FLOUNDER:
6324                 case CHIP_VANGOGH:
6325                 case CHIP_DIMGREY_CAVEFISH:
6326                 case CHIP_BEIGE_GOBY:
6327                         WREG32_SOC15(GC, 0, mmCP_MEC_CNTL_Sienna_Cichlid,
6328                                      (CP_MEC_CNTL__MEC_ME1_HALT_MASK |
6329                                       CP_MEC_CNTL__MEC_ME2_HALT_MASK));
6330                         break;
6331                 default:
6332                         WREG32_SOC15(GC, 0, mmCP_MEC_CNTL,
6333                                      (CP_MEC_CNTL__MEC_ME1_HALT_MASK |
6334                                       CP_MEC_CNTL__MEC_ME2_HALT_MASK));
6335                         break;
6336                 }
6337                 adev->gfx.kiq.ring.sched.ready = false;
6338         }
6339         udelay(50);
6340 }
6341
6342 static int gfx_v10_0_cp_compute_load_microcode(struct amdgpu_device *adev)
6343 {
6344         const struct gfx_firmware_header_v1_0 *mec_hdr;
6345         const __le32 *fw_data;
6346         unsigned i;
6347         u32 tmp;
6348         u32 usec_timeout = 50000; /* Wait for 50 ms */
6349
6350         if (!adev->gfx.mec_fw)
6351                 return -EINVAL;
6352
6353         gfx_v10_0_cp_compute_enable(adev, false);
6354
6355         mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
6356         amdgpu_ucode_print_gfx_hdr(&mec_hdr->header);
6357
6358         fw_data = (const __le32 *)
6359                 (adev->gfx.mec_fw->data +
6360                  le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes));
6361
6362         /* Trigger an invalidation of the L1 instruction caches */
6363         tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL);
6364         tmp = REG_SET_FIELD(tmp, CP_CPC_IC_OP_CNTL, INVALIDATE_CACHE, 1);
6365         WREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL, tmp);
6366
6367         /* Wait for invalidation complete */
6368         for (i = 0; i < usec_timeout; i++) {
6369                 tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL);
6370                 if (1 == REG_GET_FIELD(tmp, CP_CPC_IC_OP_CNTL,
6371                                        INVALIDATE_CACHE_COMPLETE))
6372                         break;
6373                 udelay(1);
6374         }
6375
6376         if (i >= usec_timeout) {
6377                 dev_err(adev->dev, "failed to invalidate instruction cache\n");
6378                 return -EINVAL;
6379         }
6380
6381         if (amdgpu_emu_mode == 1)
6382                 adev->hdp.funcs->flush_hdp(adev, NULL);
6383
6384         tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_CNTL);
6385         tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0);
6386         tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, EXE_DISABLE, 0);
6387         tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, ADDRESS_CLAMP, 1);
6388         WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_CNTL, tmp);
6389
6390         WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_LO, adev->gfx.mec.mec_fw_gpu_addr &
6391                      0xFFFFF000);
6392         WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_HI,
6393                      upper_32_bits(adev->gfx.mec.mec_fw_gpu_addr));
6394
6395         /* MEC1 */
6396         WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_ADDR, 0);
6397
6398         for (i = 0; i < mec_hdr->jt_size; i++)
6399                 WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_DATA,
6400                              le32_to_cpup(fw_data + mec_hdr->jt_offset + i));
6401
6402         WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_ADDR, adev->gfx.mec_fw_version);
6403
6404         /*
6405          * TODO: Loading MEC2 firmware is only necessary if MEC2 should run
6406          * different microcode than MEC1.
6407          */
6408
6409         return 0;
6410 }
6411
6412 static void gfx_v10_0_kiq_setting(struct amdgpu_ring *ring)
6413 {
6414         uint32_t tmp;
6415         struct amdgpu_device *adev = ring->adev;
6416
6417         /* tell RLC which is KIQ queue */
6418         switch (adev->asic_type) {
6419         case CHIP_SIENNA_CICHLID:
6420         case CHIP_NAVY_FLOUNDER:
6421         case CHIP_VANGOGH:
6422         case CHIP_DIMGREY_CAVEFISH:
6423         case CHIP_BEIGE_GOBY:
6424                 tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS_Sienna_Cichlid);
6425                 tmp &= 0xffffff00;
6426                 tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue);
6427                 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS_Sienna_Cichlid, tmp);
6428                 tmp |= 0x80;
6429                 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS_Sienna_Cichlid, tmp);
6430                 break;
6431         default:
6432                 tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS);
6433                 tmp &= 0xffffff00;
6434                 tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue);
6435                 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS, tmp);
6436                 tmp |= 0x80;
6437                 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS, tmp);
6438                 break;
6439         }
6440 }
6441
6442 static int gfx_v10_0_gfx_mqd_init(struct amdgpu_ring *ring)
6443 {
6444         struct amdgpu_device *adev = ring->adev;
6445         struct v10_gfx_mqd *mqd = ring->mqd_ptr;
6446         uint64_t hqd_gpu_addr, wb_gpu_addr;
6447         uint32_t tmp;
6448         uint32_t rb_bufsz;
6449
6450         /* set up gfx hqd wptr */
6451         mqd->cp_gfx_hqd_wptr = 0;
6452         mqd->cp_gfx_hqd_wptr_hi = 0;
6453
6454         /* set the pointer to the MQD */
6455         mqd->cp_mqd_base_addr = ring->mqd_gpu_addr & 0xfffffffc;
6456         mqd->cp_mqd_base_addr_hi = upper_32_bits(ring->mqd_gpu_addr);
6457
6458         /* set up mqd control */
6459         tmp = RREG32_SOC15(GC, 0, mmCP_GFX_MQD_CONTROL);
6460         tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, VMID, 0);
6461         tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, PRIV_STATE, 1);
6462         tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, CACHE_POLICY, 0);
6463         mqd->cp_gfx_mqd_control = tmp;
6464
6465         /* set up gfx_hqd_vimd with 0x0 to indicate the ring buffer's vmid */
6466         tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_VMID);
6467         tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_VMID, VMID, 0);
6468         mqd->cp_gfx_hqd_vmid = 0;
6469
6470         /* set up default queue priority level
6471          * 0x0 = low priority, 0x1 = high priority */
6472         tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_QUEUE_PRIORITY);
6473         tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_QUEUE_PRIORITY, PRIORITY_LEVEL, 0);
6474         mqd->cp_gfx_hqd_queue_priority = tmp;
6475
6476         /* set up time quantum */
6477         tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_QUANTUM);
6478         tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_QUANTUM, QUANTUM_EN, 1);
6479         mqd->cp_gfx_hqd_quantum = tmp;
6480
6481         /* set up gfx hqd base. this is similar as CP_RB_BASE */
6482         hqd_gpu_addr = ring->gpu_addr >> 8;
6483         mqd->cp_gfx_hqd_base = hqd_gpu_addr;
6484         mqd->cp_gfx_hqd_base_hi = upper_32_bits(hqd_gpu_addr);
6485
6486         /* set up hqd_rptr_addr/_hi, similar as CP_RB_RPTR */
6487         wb_gpu_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
6488         mqd->cp_gfx_hqd_rptr_addr = wb_gpu_addr & 0xfffffffc;
6489         mqd->cp_gfx_hqd_rptr_addr_hi =
6490                 upper_32_bits(wb_gpu_addr) & 0xffff;
6491
6492         /* set up rb_wptr_poll addr */
6493         wb_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
6494         mqd->cp_rb_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc;
6495         mqd->cp_rb_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff;
6496
6497         /* set up the gfx_hqd_control, similar as CP_RB0_CNTL */
6498         rb_bufsz = order_base_2(ring->ring_size / 4) - 1;
6499         tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_CNTL);
6500         tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_BUFSZ, rb_bufsz);
6501         tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_BLKSZ, rb_bufsz - 2);
6502 #ifdef __BIG_ENDIAN
6503         tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, BUF_SWAP, 1);
6504 #endif
6505         mqd->cp_gfx_hqd_cntl = tmp;
6506
6507         /* set up cp_doorbell_control */
6508         tmp = RREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL);
6509         if (ring->use_doorbell) {
6510                 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
6511                                     DOORBELL_OFFSET, ring->doorbell_index);
6512                 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
6513                                     DOORBELL_EN, 1);
6514         } else
6515                 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
6516                                     DOORBELL_EN, 0);
6517         mqd->cp_rb_doorbell_control = tmp;
6518
6519         /*if there are 2 gfx rings, set the lower doorbell range of the first ring,
6520          *otherwise the range of the second ring will override the first ring */
6521         if (ring->doorbell_index == adev->doorbell_index.gfx_ring0 << 1)
6522                 gfx_v10_0_cp_gfx_set_doorbell(adev, ring);
6523
6524         /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */
6525         ring->wptr = 0;
6526         mqd->cp_gfx_hqd_rptr = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_RPTR);
6527
6528         /* active the queue */
6529         mqd->cp_gfx_hqd_active = 1;
6530
6531         return 0;
6532 }
6533
6534 #ifdef BRING_UP_DEBUG
6535 static int gfx_v10_0_gfx_queue_init_register(struct amdgpu_ring *ring)
6536 {
6537         struct amdgpu_device *adev = ring->adev;
6538         struct v10_gfx_mqd *mqd = ring->mqd_ptr;
6539
6540         /* set mmCP_GFX_HQD_WPTR/_HI to 0 */
6541         WREG32_SOC15(GC, 0, mmCP_GFX_HQD_WPTR, mqd->cp_gfx_hqd_wptr);
6542         WREG32_SOC15(GC, 0, mmCP_GFX_HQD_WPTR_HI, mqd->cp_gfx_hqd_wptr_hi);
6543
6544         /* set GFX_MQD_BASE */
6545         WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR, mqd->cp_mqd_base_addr);
6546         WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR_HI, mqd->cp_mqd_base_addr_hi);
6547
6548         /* set GFX_MQD_CONTROL */
6549         WREG32_SOC15(GC, 0, mmCP_GFX_MQD_CONTROL, mqd->cp_gfx_mqd_control);
6550
6551         /* set GFX_HQD_VMID to 0 */
6552         WREG32_SOC15(GC, 0, mmCP_GFX_HQD_VMID, mqd->cp_gfx_hqd_vmid);
6553
6554         WREG32_SOC15(GC, 0, mmCP_GFX_HQD_QUEUE_PRIORITY,
6555                         mqd->cp_gfx_hqd_queue_priority);
6556         WREG32_SOC15(GC, 0, mmCP_GFX_HQD_QUANTUM, mqd->cp_gfx_hqd_quantum);
6557
6558         /* set GFX_HQD_BASE, similar as CP_RB_BASE */
6559         WREG32_SOC15(GC, 0, mmCP_GFX_HQD_BASE, mqd->cp_gfx_hqd_base);
6560         WREG32_SOC15(GC, 0, mmCP_GFX_HQD_BASE_HI, mqd->cp_gfx_hqd_base_hi);
6561
6562         /* set GFX_HQD_RPTR_ADDR, similar as CP_RB_RPTR */
6563         WREG32_SOC15(GC, 0, mmCP_GFX_HQD_RPTR_ADDR, mqd->cp_gfx_hqd_rptr_addr);
6564         WREG32_SOC15(GC, 0, mmCP_GFX_HQD_RPTR_ADDR_HI, mqd->cp_gfx_hqd_rptr_addr_hi);
6565
6566         /* set GFX_HQD_CNTL, similar as CP_RB_CNTL */
6567         WREG32_SOC15(GC, 0, mmCP_GFX_HQD_CNTL, mqd->cp_gfx_hqd_cntl);
6568
6569         /* set RB_WPTR_POLL_ADDR */
6570         WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_LO, mqd->cp_rb_wptr_poll_addr_lo);
6571         WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI, mqd->cp_rb_wptr_poll_addr_hi);
6572
6573         /* set RB_DOORBELL_CONTROL */
6574         WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL, mqd->cp_rb_doorbell_control);
6575
6576         /* active the queue */
6577         WREG32_SOC15(GC, 0, mmCP_GFX_HQD_ACTIVE, mqd->cp_gfx_hqd_active);
6578
6579         return 0;
6580 }
6581 #endif
6582
6583 static int gfx_v10_0_gfx_init_queue(struct amdgpu_ring *ring)
6584 {
6585         struct amdgpu_device *adev = ring->adev;
6586         struct v10_gfx_mqd *mqd = ring->mqd_ptr;
6587         int mqd_idx = ring - &adev->gfx.gfx_ring[0];
6588
6589         if (!amdgpu_in_reset(adev) && !adev->in_suspend) {
6590                 memset((void *)mqd, 0, sizeof(*mqd));
6591                 mutex_lock(&adev->srbm_mutex);
6592                 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
6593                 gfx_v10_0_gfx_mqd_init(ring);
6594 #ifdef BRING_UP_DEBUG
6595                 gfx_v10_0_gfx_queue_init_register(ring);
6596 #endif
6597                 nv_grbm_select(adev, 0, 0, 0, 0);
6598                 mutex_unlock(&adev->srbm_mutex);
6599                 if (adev->gfx.me.mqd_backup[mqd_idx])
6600                         memcpy(adev->gfx.me.mqd_backup[mqd_idx], mqd, sizeof(*mqd));
6601         } else if (amdgpu_in_reset(adev)) {
6602                 /* reset mqd with the backup copy */
6603                 if (adev->gfx.me.mqd_backup[mqd_idx])
6604                         memcpy(mqd, adev->gfx.me.mqd_backup[mqd_idx], sizeof(*mqd));
6605                 /* reset the ring */
6606                 ring->wptr = 0;
6607                 adev->wb.wb[ring->wptr_offs] = 0;
6608                 amdgpu_ring_clear_ring(ring);
6609 #ifdef BRING_UP_DEBUG
6610                 mutex_lock(&adev->srbm_mutex);
6611                 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
6612                 gfx_v10_0_gfx_queue_init_register(ring);
6613                 nv_grbm_select(adev, 0, 0, 0, 0);
6614                 mutex_unlock(&adev->srbm_mutex);
6615 #endif
6616         } else {
6617                 amdgpu_ring_clear_ring(ring);
6618         }
6619
6620         return 0;
6621 }
6622
6623 #ifndef BRING_UP_DEBUG
6624 static int gfx_v10_0_kiq_enable_kgq(struct amdgpu_device *adev)
6625 {
6626         struct amdgpu_kiq *kiq = &adev->gfx.kiq;
6627         struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring;
6628         int r, i;
6629
6630         if (!kiq->pmf || !kiq->pmf->kiq_map_queues)
6631                 return -EINVAL;
6632
6633         r = amdgpu_ring_alloc(kiq_ring, kiq->pmf->map_queues_size *
6634                                         adev->gfx.num_gfx_rings);
6635         if (r) {
6636                 DRM_ERROR("Failed to lock KIQ (%d).\n", r);
6637                 return r;
6638         }
6639
6640         for (i = 0; i < adev->gfx.num_gfx_rings; i++)
6641                 kiq->pmf->kiq_map_queues(kiq_ring, &adev->gfx.gfx_ring[i]);
6642
6643         return amdgpu_ring_test_helper(kiq_ring);
6644 }
6645 #endif
6646
6647 static int gfx_v10_0_cp_async_gfx_ring_resume(struct amdgpu_device *adev)
6648 {
6649         int r, i;
6650         struct amdgpu_ring *ring;
6651
6652         for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
6653                 ring = &adev->gfx.gfx_ring[i];
6654
6655                 r = amdgpu_bo_reserve(ring->mqd_obj, false);
6656                 if (unlikely(r != 0))
6657                         goto done;
6658
6659                 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr);
6660                 if (!r) {
6661                         r = gfx_v10_0_gfx_init_queue(ring);
6662                         amdgpu_bo_kunmap(ring->mqd_obj);
6663                         ring->mqd_ptr = NULL;
6664                 }
6665                 amdgpu_bo_unreserve(ring->mqd_obj);
6666                 if (r)
6667                         goto done;
6668         }
6669 #ifndef BRING_UP_DEBUG
6670         r = gfx_v10_0_kiq_enable_kgq(adev);
6671         if (r)
6672                 goto done;
6673 #endif
6674         r = gfx_v10_0_cp_gfx_start(adev);
6675         if (r)
6676                 goto done;
6677
6678         for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
6679                 ring = &adev->gfx.gfx_ring[i];
6680                 ring->sched.ready = true;
6681         }
6682 done:
6683         return r;
6684 }
6685
6686 static void gfx_v10_0_compute_mqd_set_priority(struct amdgpu_ring *ring, struct v10_compute_mqd *mqd)
6687 {
6688         struct amdgpu_device *adev = ring->adev;
6689
6690         if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) {
6691                 if (amdgpu_gfx_is_high_priority_compute_queue(adev, ring)) {
6692                         mqd->cp_hqd_pipe_priority = AMDGPU_GFX_PIPE_PRIO_HIGH;
6693                         mqd->cp_hqd_queue_priority =
6694                                 AMDGPU_GFX_QUEUE_PRIORITY_MAXIMUM;
6695                 }
6696         }
6697 }
6698
6699 static int gfx_v10_0_compute_mqd_init(struct amdgpu_ring *ring)
6700 {
6701         struct amdgpu_device *adev = ring->adev;
6702         struct v10_compute_mqd *mqd = ring->mqd_ptr;
6703         uint64_t hqd_gpu_addr, wb_gpu_addr, eop_base_addr;
6704         uint32_t tmp;
6705
6706         mqd->header = 0xC0310800;
6707         mqd->compute_pipelinestat_enable = 0x00000001;
6708         mqd->compute_static_thread_mgmt_se0 = 0xffffffff;
6709         mqd->compute_static_thread_mgmt_se1 = 0xffffffff;
6710         mqd->compute_static_thread_mgmt_se2 = 0xffffffff;
6711         mqd->compute_static_thread_mgmt_se3 = 0xffffffff;
6712         mqd->compute_misc_reserved = 0x00000003;
6713
6714         eop_base_addr = ring->eop_gpu_addr >> 8;
6715         mqd->cp_hqd_eop_base_addr_lo = eop_base_addr;
6716         mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr);
6717
6718         /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */
6719         tmp = RREG32_SOC15(GC, 0, mmCP_HQD_EOP_CONTROL);
6720         tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE,
6721                         (order_base_2(GFX10_MEC_HPD_SIZE / 4) - 1));
6722
6723         mqd->cp_hqd_eop_control = tmp;
6724
6725         /* enable doorbell? */
6726         tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL);
6727
6728         if (ring->use_doorbell) {
6729                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
6730                                     DOORBELL_OFFSET, ring->doorbell_index);
6731                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
6732                                     DOORBELL_EN, 1);
6733                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
6734                                     DOORBELL_SOURCE, 0);
6735                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
6736                                     DOORBELL_HIT, 0);
6737         } else {
6738                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
6739                                     DOORBELL_EN, 0);
6740         }
6741
6742         mqd->cp_hqd_pq_doorbell_control = tmp;
6743
6744         /* disable the queue if it's active */
6745         ring->wptr = 0;
6746         mqd->cp_hqd_dequeue_request = 0;
6747         mqd->cp_hqd_pq_rptr = 0;
6748         mqd->cp_hqd_pq_wptr_lo = 0;
6749         mqd->cp_hqd_pq_wptr_hi = 0;
6750
6751         /* set the pointer to the MQD */
6752         mqd->cp_mqd_base_addr_lo = ring->mqd_gpu_addr & 0xfffffffc;
6753         mqd->cp_mqd_base_addr_hi = upper_32_bits(ring->mqd_gpu_addr);
6754
6755         /* set MQD vmid to 0 */
6756         tmp = RREG32_SOC15(GC, 0, mmCP_MQD_CONTROL);
6757         tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0);
6758         mqd->cp_mqd_control = tmp;
6759
6760         /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */
6761         hqd_gpu_addr = ring->gpu_addr >> 8;
6762         mqd->cp_hqd_pq_base_lo = hqd_gpu_addr;
6763         mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr);
6764
6765         /* set up the HQD, this is similar to CP_RB0_CNTL */
6766         tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_CONTROL);
6767         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE,
6768                             (order_base_2(ring->ring_size / 4) - 1));
6769         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE,
6770                             ((order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1) << 8));
6771 #ifdef __BIG_ENDIAN
6772         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ENDIAN_SWAP, 1);
6773 #endif
6774         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 0);
6775         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, TUNNEL_DISPATCH, 0);
6776         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1);
6777         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1);
6778         mqd->cp_hqd_pq_control = tmp;
6779
6780         /* set the wb address whether it's enabled or not */
6781         wb_gpu_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
6782         mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc;
6783         mqd->cp_hqd_pq_rptr_report_addr_hi =
6784                 upper_32_bits(wb_gpu_addr) & 0xffff;
6785
6786         /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */
6787         wb_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
6788         mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc;
6789         mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff;
6790
6791         tmp = 0;
6792         /* enable the doorbell if requested */
6793         if (ring->use_doorbell) {
6794                 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL);
6795                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
6796                                 DOORBELL_OFFSET, ring->doorbell_index);
6797
6798                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
6799                                     DOORBELL_EN, 1);
6800                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
6801                                     DOORBELL_SOURCE, 0);
6802                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
6803                                     DOORBELL_HIT, 0);
6804         }
6805
6806         mqd->cp_hqd_pq_doorbell_control = tmp;
6807
6808         /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */
6809         ring->wptr = 0;
6810         mqd->cp_hqd_pq_rptr = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR);
6811
6812         /* set the vmid for the queue */
6813         mqd->cp_hqd_vmid = 0;
6814
6815         tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PERSISTENT_STATE);
6816         tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, PRELOAD_SIZE, 0x53);
6817         mqd->cp_hqd_persistent_state = tmp;
6818
6819         /* set MIN_IB_AVAIL_SIZE */
6820         tmp = RREG32_SOC15(GC, 0, mmCP_HQD_IB_CONTROL);
6821         tmp = REG_SET_FIELD(tmp, CP_HQD_IB_CONTROL, MIN_IB_AVAIL_SIZE, 3);
6822         mqd->cp_hqd_ib_control = tmp;
6823
6824         /* set static priority for a compute queue/ring */
6825         gfx_v10_0_compute_mqd_set_priority(ring, mqd);
6826
6827         /* map_queues packet doesn't need activate the queue,
6828          * so only kiq need set this field.
6829          */
6830         if (ring->funcs->type == AMDGPU_RING_TYPE_KIQ)
6831                 mqd->cp_hqd_active = 1;
6832
6833         return 0;
6834 }
6835
6836 static int gfx_v10_0_kiq_init_register(struct amdgpu_ring *ring)
6837 {
6838         struct amdgpu_device *adev = ring->adev;
6839         struct v10_compute_mqd *mqd = ring->mqd_ptr;
6840         int j;
6841
6842         /* inactivate the queue */
6843         if (amdgpu_sriov_vf(adev))
6844                 WREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE, 0);
6845
6846         /* disable wptr polling */
6847         WREG32_FIELD15(GC, 0, CP_PQ_WPTR_POLL_CNTL, EN, 0);
6848
6849         /* write the EOP addr */
6850         WREG32_SOC15(GC, 0, mmCP_HQD_EOP_BASE_ADDR,
6851                mqd->cp_hqd_eop_base_addr_lo);
6852         WREG32_SOC15(GC, 0, mmCP_HQD_EOP_BASE_ADDR_HI,
6853                mqd->cp_hqd_eop_base_addr_hi);
6854
6855         /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */
6856         WREG32_SOC15(GC, 0, mmCP_HQD_EOP_CONTROL,
6857                mqd->cp_hqd_eop_control);
6858
6859         /* enable doorbell? */
6860         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL,
6861                mqd->cp_hqd_pq_doorbell_control);
6862
6863         /* disable the queue if it's active */
6864         if (RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1) {
6865                 WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST, 1);
6866                 for (j = 0; j < adev->usec_timeout; j++) {
6867                         if (!(RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1))
6868                                 break;
6869                         udelay(1);
6870                 }
6871                 WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST,
6872                        mqd->cp_hqd_dequeue_request);
6873                 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR,
6874                        mqd->cp_hqd_pq_rptr);
6875                 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_LO,
6876                        mqd->cp_hqd_pq_wptr_lo);
6877                 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_HI,
6878                        mqd->cp_hqd_pq_wptr_hi);
6879         }
6880
6881         /* set the pointer to the MQD */
6882         WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR,
6883                mqd->cp_mqd_base_addr_lo);
6884         WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR_HI,
6885                mqd->cp_mqd_base_addr_hi);
6886
6887         /* set MQD vmid to 0 */
6888         WREG32_SOC15(GC, 0, mmCP_MQD_CONTROL,
6889                mqd->cp_mqd_control);
6890
6891         /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */
6892         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_BASE,
6893                mqd->cp_hqd_pq_base_lo);
6894         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_BASE_HI,
6895                mqd->cp_hqd_pq_base_hi);
6896
6897         /* set up the HQD, this is similar to CP_RB0_CNTL */
6898         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_CONTROL,
6899                mqd->cp_hqd_pq_control);
6900
6901         /* set the wb address whether it's enabled or not */
6902         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR_REPORT_ADDR,
6903                 mqd->cp_hqd_pq_rptr_report_addr_lo);
6904         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI,
6905                 mqd->cp_hqd_pq_rptr_report_addr_hi);
6906
6907         /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */
6908         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR,
6909                mqd->cp_hqd_pq_wptr_poll_addr_lo);
6910         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR_HI,
6911                mqd->cp_hqd_pq_wptr_poll_addr_hi);
6912
6913         /* enable the doorbell if requested */
6914         if (ring->use_doorbell) {
6915                 WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_LOWER,
6916                         (adev->doorbell_index.kiq * 2) << 2);
6917                 WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_UPPER,
6918                         (adev->doorbell_index.userqueue_end * 2) << 2);
6919         }
6920
6921         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL,
6922                mqd->cp_hqd_pq_doorbell_control);
6923
6924         /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */
6925         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_LO,
6926                mqd->cp_hqd_pq_wptr_lo);
6927         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_HI,
6928                mqd->cp_hqd_pq_wptr_hi);
6929
6930         /* set the vmid for the queue */
6931         WREG32_SOC15(GC, 0, mmCP_HQD_VMID, mqd->cp_hqd_vmid);
6932
6933         WREG32_SOC15(GC, 0, mmCP_HQD_PERSISTENT_STATE,
6934                mqd->cp_hqd_persistent_state);
6935
6936         /* activate the queue */
6937         WREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE,
6938                mqd->cp_hqd_active);
6939
6940         if (ring->use_doorbell)
6941                 WREG32_FIELD15(GC, 0, CP_PQ_STATUS, DOORBELL_ENABLE, 1);
6942
6943         return 0;
6944 }
6945
6946 static int gfx_v10_0_kiq_init_queue(struct amdgpu_ring *ring)
6947 {
6948         struct amdgpu_device *adev = ring->adev;
6949         struct v10_compute_mqd *mqd = ring->mqd_ptr;
6950         int mqd_idx = AMDGPU_MAX_COMPUTE_RINGS;
6951
6952         gfx_v10_0_kiq_setting(ring);
6953
6954         if (amdgpu_in_reset(adev)) { /* for GPU_RESET case */
6955                 /* reset MQD to a clean status */
6956                 if (adev->gfx.mec.mqd_backup[mqd_idx])
6957                         memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(*mqd));
6958
6959                 /* reset ring buffer */
6960                 ring->wptr = 0;
6961                 amdgpu_ring_clear_ring(ring);
6962
6963                 mutex_lock(&adev->srbm_mutex);
6964                 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
6965                 gfx_v10_0_kiq_init_register(ring);
6966                 nv_grbm_select(adev, 0, 0, 0, 0);
6967                 mutex_unlock(&adev->srbm_mutex);
6968         } else {
6969                 memset((void *)mqd, 0, sizeof(*mqd));
6970                 mutex_lock(&adev->srbm_mutex);
6971                 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
6972                 gfx_v10_0_compute_mqd_init(ring);
6973                 gfx_v10_0_kiq_init_register(ring);
6974                 nv_grbm_select(adev, 0, 0, 0, 0);
6975                 mutex_unlock(&adev->srbm_mutex);
6976
6977                 if (adev->gfx.mec.mqd_backup[mqd_idx])
6978                         memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(*mqd));
6979         }
6980
6981         return 0;
6982 }
6983
6984 static int gfx_v10_0_kcq_init_queue(struct amdgpu_ring *ring)
6985 {
6986         struct amdgpu_device *adev = ring->adev;
6987         struct v10_compute_mqd *mqd = ring->mqd_ptr;
6988         int mqd_idx = ring - &adev->gfx.compute_ring[0];
6989
6990         if (!amdgpu_in_reset(adev) && !adev->in_suspend) {
6991                 memset((void *)mqd, 0, sizeof(*mqd));
6992                 mutex_lock(&adev->srbm_mutex);
6993                 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
6994                 gfx_v10_0_compute_mqd_init(ring);
6995                 nv_grbm_select(adev, 0, 0, 0, 0);
6996                 mutex_unlock(&adev->srbm_mutex);
6997
6998                 if (adev->gfx.mec.mqd_backup[mqd_idx])
6999                         memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(*mqd));
7000         } else if (amdgpu_in_reset(adev)) { /* for GPU_RESET case */
7001                 /* reset MQD to a clean status */
7002                 if (adev->gfx.mec.mqd_backup[mqd_idx])
7003                         memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(*mqd));
7004
7005                 /* reset ring buffer */
7006                 ring->wptr = 0;
7007                 atomic64_set((atomic64_t *)&adev->wb.wb[ring->wptr_offs], 0);
7008                 amdgpu_ring_clear_ring(ring);
7009         } else {
7010                 amdgpu_ring_clear_ring(ring);
7011         }
7012
7013         return 0;
7014 }
7015
7016 static int gfx_v10_0_kiq_resume(struct amdgpu_device *adev)
7017 {
7018         struct amdgpu_ring *ring;
7019         int r;
7020
7021         ring = &adev->gfx.kiq.ring;
7022
7023         r = amdgpu_bo_reserve(ring->mqd_obj, false);
7024         if (unlikely(r != 0))
7025                 return r;
7026
7027         r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr);
7028         if (unlikely(r != 0))
7029                 return r;
7030
7031         gfx_v10_0_kiq_init_queue(ring);
7032         amdgpu_bo_kunmap(ring->mqd_obj);
7033         ring->mqd_ptr = NULL;
7034         amdgpu_bo_unreserve(ring->mqd_obj);
7035         ring->sched.ready = true;
7036         return 0;
7037 }
7038
7039 static int gfx_v10_0_kcq_resume(struct amdgpu_device *adev)
7040 {
7041         struct amdgpu_ring *ring = NULL;
7042         int r = 0, i;
7043
7044         gfx_v10_0_cp_compute_enable(adev, true);
7045
7046         for (i = 0; i < adev->gfx.num_compute_rings; i++) {
7047                 ring = &adev->gfx.compute_ring[i];
7048
7049                 r = amdgpu_bo_reserve(ring->mqd_obj, false);
7050                 if (unlikely(r != 0))
7051                         goto done;
7052                 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr);
7053                 if (!r) {
7054                         r = gfx_v10_0_kcq_init_queue(ring);
7055                         amdgpu_bo_kunmap(ring->mqd_obj);
7056                         ring->mqd_ptr = NULL;
7057                 }
7058                 amdgpu_bo_unreserve(ring->mqd_obj);
7059                 if (r)
7060                         goto done;
7061         }
7062
7063         r = amdgpu_gfx_enable_kcq(adev);
7064 done:
7065         return r;
7066 }
7067
7068 static int gfx_v10_0_cp_resume(struct amdgpu_device *adev)
7069 {
7070         int r, i;
7071         struct amdgpu_ring *ring;
7072
7073         if (!(adev->flags & AMD_IS_APU))
7074                 gfx_v10_0_enable_gui_idle_interrupt(adev, false);
7075
7076         if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
7077                 /* legacy firmware loading */
7078                 r = gfx_v10_0_cp_gfx_load_microcode(adev);
7079                 if (r)
7080                         return r;
7081
7082                 r = gfx_v10_0_cp_compute_load_microcode(adev);
7083                 if (r)
7084                         return r;
7085         }
7086
7087         r = gfx_v10_0_kiq_resume(adev);
7088         if (r)
7089                 return r;
7090
7091         r = gfx_v10_0_kcq_resume(adev);
7092         if (r)
7093                 return r;
7094
7095         if (!amdgpu_async_gfx_ring) {
7096                 r = gfx_v10_0_cp_gfx_resume(adev);
7097                 if (r)
7098                         return r;
7099         } else {
7100                 r = gfx_v10_0_cp_async_gfx_ring_resume(adev);
7101                 if (r)
7102                         return r;
7103         }
7104
7105         for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
7106                 ring = &adev->gfx.gfx_ring[i];
7107                 r = amdgpu_ring_test_helper(ring);
7108                 if (r)
7109                         return r;
7110         }
7111
7112         for (i = 0; i < adev->gfx.num_compute_rings; i++) {
7113                 ring = &adev->gfx.compute_ring[i];
7114                 r = amdgpu_ring_test_helper(ring);
7115                 if (r)
7116                         return r;
7117         }
7118
7119         return 0;
7120 }
7121
7122 static void gfx_v10_0_cp_enable(struct amdgpu_device *adev, bool enable)
7123 {
7124         gfx_v10_0_cp_gfx_enable(adev, enable);
7125         gfx_v10_0_cp_compute_enable(adev, enable);
7126 }
7127
7128 static bool gfx_v10_0_check_grbm_cam_remapping(struct amdgpu_device *adev)
7129 {
7130         uint32_t data, pattern = 0xDEADBEEF;
7131
7132         /* check if mmVGT_ESGS_RING_SIZE_UMD
7133          * has been remapped to mmVGT_ESGS_RING_SIZE */
7134         switch (adev->asic_type) {
7135         case CHIP_SIENNA_CICHLID:
7136         case CHIP_NAVY_FLOUNDER:
7137         case CHIP_DIMGREY_CAVEFISH:
7138         case CHIP_BEIGE_GOBY:
7139                 data = RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid);
7140                 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid, 0);
7141                 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_UMD, pattern);
7142
7143                 if (RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid) == pattern) {
7144                         WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_UMD , data);
7145                         return true;
7146                 } else {
7147                         WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid, data);
7148                         return false;
7149                 }
7150                 break;
7151         case CHIP_VANGOGH:
7152                 return true;
7153         default:
7154                 data = RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE);
7155                 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE, 0);
7156                 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_UMD, pattern);
7157
7158                 if (RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE) == pattern) {
7159                         WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_UMD, data);
7160                         return true;
7161                 } else {
7162                         WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE, data);
7163                         return false;
7164                 }
7165                 break;
7166         }
7167 }
7168
7169 static void gfx_v10_0_setup_grbm_cam_remapping(struct amdgpu_device *adev)
7170 {
7171         uint32_t data;
7172
7173         if (amdgpu_sriov_vf(adev))
7174                 return;
7175
7176         /* initialize cam_index to 0
7177          * index will auto-inc after each data writting */
7178         WREG32_SOC15(GC, 0, mmGRBM_CAM_INDEX, 0);
7179
7180         switch (adev->asic_type) {
7181         case CHIP_SIENNA_CICHLID:
7182         case CHIP_NAVY_FLOUNDER:
7183         case CHIP_VANGOGH:
7184         case CHIP_DIMGREY_CAVEFISH:
7185         case CHIP_BEIGE_GOBY:
7186                 /* mmVGT_TF_RING_SIZE_UMD -> mmVGT_TF_RING_SIZE */
7187                 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE_UMD) <<
7188                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7189                        (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE_Sienna_Cichlid) <<
7190                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7191                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7192                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7193
7194                 /* mmVGT_TF_MEMORY_BASE_UMD -> mmVGT_TF_MEMORY_BASE */
7195                 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_UMD) <<
7196                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7197                        (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_Sienna_Cichlid) <<
7198                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7199                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7200                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7201
7202                 /* mmVGT_TF_MEMORY_BASE_HI_UMD -> mmVGT_TF_MEMORY_BASE_HI */
7203                 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI_UMD) <<
7204                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7205                        (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI_Sienna_Cichlid) <<
7206                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7207                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7208                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7209
7210                 /* mmVGT_HS_OFFCHIP_PARAM_UMD -> mmVGT_HS_OFFCHIP_PARAM */
7211                 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM_UMD) <<
7212                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7213                        (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM_Sienna_Cichlid) <<
7214                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7215                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7216                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7217
7218                 /* mmVGT_ESGS_RING_SIZE_UMD -> mmVGT_ESGS_RING_SIZE */
7219                 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE_UMD) <<
7220                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7221                        (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid) <<
7222                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7223                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7224                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7225
7226                 /* mmVGT_GSVS_RING_SIZE_UMD -> mmVGT_GSVS_RING_SIZE */
7227                 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE_UMD) <<
7228                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7229                        (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE_Sienna_Cichlid) <<
7230                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7231                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7232                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7233
7234                 /* mmSPI_CONFIG_CNTL_REMAP -> mmSPI_CONFIG_CNTL */
7235                 data = (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL_REMAP) <<
7236                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7237                        (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL_Sienna_Cichlid) <<
7238                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7239                 break;
7240         default:
7241                 /* mmVGT_TF_RING_SIZE_UMD -> mmVGT_TF_RING_SIZE */
7242                 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE_UMD) <<
7243                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7244                        (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE) <<
7245                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7246                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7247                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7248
7249                 /* mmVGT_TF_MEMORY_BASE_UMD -> mmVGT_TF_MEMORY_BASE */
7250                 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_UMD) <<
7251                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7252                        (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE) <<
7253                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7254                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7255                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7256
7257                 /* mmVGT_TF_MEMORY_BASE_HI_UMD -> mmVGT_TF_MEMORY_BASE_HI */
7258                 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI_UMD) <<
7259                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7260                        (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI) <<
7261                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7262                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7263                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7264
7265                 /* mmVGT_HS_OFFCHIP_PARAM_UMD -> mmVGT_HS_OFFCHIP_PARAM */
7266                 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM_UMD) <<
7267                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7268                        (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM) <<
7269                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7270                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7271                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7272
7273                 /* mmVGT_ESGS_RING_SIZE_UMD -> mmVGT_ESGS_RING_SIZE */
7274                 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE_UMD) <<
7275                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7276                        (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE) <<
7277                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7278                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7279                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7280
7281                 /* mmVGT_GSVS_RING_SIZE_UMD -> mmVGT_GSVS_RING_SIZE */
7282                 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE_UMD) <<
7283                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7284                        (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE) <<
7285                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7286                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7287                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7288
7289                 /* mmSPI_CONFIG_CNTL_REMAP -> mmSPI_CONFIG_CNTL */
7290                 data = (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL_REMAP) <<
7291                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7292                        (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL) <<
7293                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7294                 break;
7295         }
7296
7297         WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7298         WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7299 }
7300
7301 static void gfx_v10_0_disable_gpa_mode(struct amdgpu_device *adev)
7302 {
7303         uint32_t data;
7304         data = RREG32_SOC15(GC, 0, mmCPC_PSP_DEBUG);
7305         data |= CPC_PSP_DEBUG__GPA_OVERRIDE_MASK;
7306         WREG32_SOC15(GC, 0, mmCPC_PSP_DEBUG, data);
7307
7308         data = RREG32_SOC15(GC, 0, mmCPG_PSP_DEBUG);
7309         data |= CPG_PSP_DEBUG__GPA_OVERRIDE_MASK;
7310         WREG32_SOC15(GC, 0, mmCPG_PSP_DEBUG, data);
7311 }
7312
7313 static int gfx_v10_0_hw_init(void *handle)
7314 {
7315         int r;
7316         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7317
7318         if (!amdgpu_emu_mode)
7319                 gfx_v10_0_init_golden_registers(adev);
7320
7321         if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
7322                 /**
7323                  * For gfx 10, rlc firmware loading relies on smu firmware is
7324                  * loaded firstly, so in direct type, it has to load smc ucode
7325                  * here before rlc.
7326                  */
7327                 if (!(adev->flags & AMD_IS_APU)) {
7328                         r = amdgpu_pm_load_smu_firmware(adev, NULL);
7329                         if (r)
7330                                 return r;
7331                 }
7332                 gfx_v10_0_disable_gpa_mode(adev);
7333         }
7334
7335         /* if GRBM CAM not remapped, set up the remapping */
7336         if (!gfx_v10_0_check_grbm_cam_remapping(adev))
7337                 gfx_v10_0_setup_grbm_cam_remapping(adev);
7338
7339         gfx_v10_0_constants_init(adev);
7340
7341         r = gfx_v10_0_rlc_resume(adev);
7342         if (r)
7343                 return r;
7344
7345         /*
7346          * init golden registers and rlc resume may override some registers,
7347          * reconfig them here
7348          */
7349         gfx_v10_0_tcp_harvest(adev);
7350
7351         r = gfx_v10_0_cp_resume(adev);
7352         if (r)
7353                 return r;
7354
7355         if (adev->asic_type == CHIP_SIENNA_CICHLID)
7356                 gfx_v10_3_program_pbb_mode(adev);
7357
7358         if (adev->asic_type >= CHIP_SIENNA_CICHLID)
7359                 gfx_v10_3_set_power_brake_sequence(adev);
7360
7361         return r;
7362 }
7363
7364 #ifndef BRING_UP_DEBUG
7365 static int gfx_v10_0_kiq_disable_kgq(struct amdgpu_device *adev)
7366 {
7367         struct amdgpu_kiq *kiq = &adev->gfx.kiq;
7368         struct amdgpu_ring *kiq_ring = &kiq->ring;
7369         int i;
7370
7371         if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues)
7372                 return -EINVAL;
7373
7374         if (amdgpu_ring_alloc(kiq_ring, kiq->pmf->unmap_queues_size *
7375                                         adev->gfx.num_gfx_rings))
7376                 return -ENOMEM;
7377
7378         for (i = 0; i < adev->gfx.num_gfx_rings; i++)
7379                 kiq->pmf->kiq_unmap_queues(kiq_ring, &adev->gfx.gfx_ring[i],
7380                                            PREEMPT_QUEUES, 0, 0);
7381
7382         return amdgpu_ring_test_helper(kiq_ring);
7383 }
7384 #endif
7385
7386 static int gfx_v10_0_hw_fini(void *handle)
7387 {
7388         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7389         int r;
7390         uint32_t tmp;
7391
7392         amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0);
7393         amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0);
7394
7395         if (!adev->in_pci_err_recovery) {
7396 #ifndef BRING_UP_DEBUG
7397                 if (amdgpu_async_gfx_ring) {
7398                         r = gfx_v10_0_kiq_disable_kgq(adev);
7399                         if (r)
7400                                 DRM_ERROR("KGQ disable failed\n");
7401                 }
7402 #endif
7403                 if (amdgpu_gfx_disable_kcq(adev))
7404                         DRM_ERROR("KCQ disable failed\n");
7405         }
7406
7407         if (amdgpu_sriov_vf(adev)) {
7408                 gfx_v10_0_cp_gfx_enable(adev, false);
7409                 /* Program KIQ position of RLC_CP_SCHEDULERS during destroy */
7410                 tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS);
7411                 tmp &= 0xffffff00;
7412                 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS, tmp);
7413
7414                 return 0;
7415         }
7416         gfx_v10_0_cp_enable(adev, false);
7417         gfx_v10_0_enable_gui_idle_interrupt(adev, false);
7418
7419         return 0;
7420 }
7421
7422 static int gfx_v10_0_suspend(void *handle)
7423 {
7424         return gfx_v10_0_hw_fini(handle);
7425 }
7426
7427 static int gfx_v10_0_resume(void *handle)
7428 {
7429         return gfx_v10_0_hw_init(handle);
7430 }
7431
7432 static bool gfx_v10_0_is_idle(void *handle)
7433 {
7434         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7435
7436         if (REG_GET_FIELD(RREG32_SOC15(GC, 0, mmGRBM_STATUS),
7437                                 GRBM_STATUS, GUI_ACTIVE))
7438                 return false;
7439         else
7440                 return true;
7441 }
7442
7443 static int gfx_v10_0_wait_for_idle(void *handle)
7444 {
7445         unsigned i;
7446         u32 tmp;
7447         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7448
7449         for (i = 0; i < adev->usec_timeout; i++) {
7450                 /* read MC_STATUS */
7451                 tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS) &
7452                         GRBM_STATUS__GUI_ACTIVE_MASK;
7453
7454                 if (!REG_GET_FIELD(tmp, GRBM_STATUS, GUI_ACTIVE))
7455                         return 0;
7456                 udelay(1);
7457         }
7458         return -ETIMEDOUT;
7459 }
7460
7461 static int gfx_v10_0_soft_reset(void *handle)
7462 {
7463         u32 grbm_soft_reset = 0;
7464         u32 tmp;
7465         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7466
7467         /* GRBM_STATUS */
7468         tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS);
7469         if (tmp & (GRBM_STATUS__PA_BUSY_MASK | GRBM_STATUS__SC_BUSY_MASK |
7470                    GRBM_STATUS__BCI_BUSY_MASK | GRBM_STATUS__SX_BUSY_MASK |
7471                    GRBM_STATUS__TA_BUSY_MASK | GRBM_STATUS__DB_BUSY_MASK |
7472                    GRBM_STATUS__CB_BUSY_MASK | GRBM_STATUS__GDS_BUSY_MASK |
7473                    GRBM_STATUS__SPI_BUSY_MASK | GRBM_STATUS__GE_BUSY_NO_DMA_MASK)) {
7474                 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
7475                                                 GRBM_SOFT_RESET, SOFT_RESET_CP,
7476                                                 1);
7477                 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
7478                                                 GRBM_SOFT_RESET, SOFT_RESET_GFX,
7479                                                 1);
7480         }
7481
7482         if (tmp & (GRBM_STATUS__CP_BUSY_MASK | GRBM_STATUS__CP_COHERENCY_BUSY_MASK)) {
7483                 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
7484                                                 GRBM_SOFT_RESET, SOFT_RESET_CP,
7485                                                 1);
7486         }
7487
7488         /* GRBM_STATUS2 */
7489         tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS2);
7490         switch (adev->asic_type) {
7491         case CHIP_SIENNA_CICHLID:
7492         case CHIP_NAVY_FLOUNDER:
7493         case CHIP_VANGOGH:
7494         case CHIP_DIMGREY_CAVEFISH:
7495         case CHIP_BEIGE_GOBY:
7496                 if (REG_GET_FIELD(tmp, GRBM_STATUS2, RLC_BUSY_Sienna_Cichlid))
7497                         grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
7498                                                         GRBM_SOFT_RESET,
7499                                                         SOFT_RESET_RLC,
7500                                                         1);
7501                 break;
7502         default:
7503                 if (REG_GET_FIELD(tmp, GRBM_STATUS2, RLC_BUSY))
7504                         grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
7505                                                         GRBM_SOFT_RESET,
7506                                                         SOFT_RESET_RLC,
7507                                                         1);
7508                 break;
7509         }
7510
7511         if (grbm_soft_reset) {
7512                 /* stop the rlc */
7513                 gfx_v10_0_rlc_stop(adev);
7514
7515                 /* Disable GFX parsing/prefetching */
7516                 gfx_v10_0_cp_gfx_enable(adev, false);
7517
7518                 /* Disable MEC parsing/prefetching */
7519                 gfx_v10_0_cp_compute_enable(adev, false);
7520
7521                 if (grbm_soft_reset) {
7522                         tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);
7523                         tmp |= grbm_soft_reset;
7524                         dev_info(adev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp);
7525                         WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp);
7526                         tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);
7527
7528                         udelay(50);
7529
7530                         tmp &= ~grbm_soft_reset;
7531                         WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp);
7532                         tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);
7533                 }
7534
7535                 /* Wait a little for things to settle down */
7536                 udelay(50);
7537         }
7538         return 0;
7539 }
7540
7541 static uint64_t gfx_v10_0_get_gpu_clock_counter(struct amdgpu_device *adev)
7542 {
7543         uint64_t clock;
7544
7545         amdgpu_gfx_off_ctrl(adev, false);
7546         mutex_lock(&adev->gfx.gpu_clock_mutex);
7547         switch (adev->asic_type) {
7548         case CHIP_VANGOGH:
7549                 clock = (uint64_t)RREG32_SOC15(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER_Vangogh) |
7550                         ((uint64_t)RREG32_SOC15(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER_Vangogh) << 32ULL);
7551                 break;
7552         default:
7553                 clock = (uint64_t)RREG32_SOC15(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER) |
7554                         ((uint64_t)RREG32_SOC15(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER) << 32ULL);
7555                 break;
7556         }
7557         mutex_unlock(&adev->gfx.gpu_clock_mutex);
7558         amdgpu_gfx_off_ctrl(adev, true);
7559         return clock;
7560 }
7561
7562 static void gfx_v10_0_ring_emit_gds_switch(struct amdgpu_ring *ring,
7563                                            uint32_t vmid,
7564                                            uint32_t gds_base, uint32_t gds_size,
7565                                            uint32_t gws_base, uint32_t gws_size,
7566                                            uint32_t oa_base, uint32_t oa_size)
7567 {
7568         struct amdgpu_device *adev = ring->adev;
7569
7570         /* GDS Base */
7571         gfx_v10_0_write_data_to_reg(ring, 0, false,
7572                                     SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_BASE) + 2 * vmid,
7573                                     gds_base);
7574
7575         /* GDS Size */
7576         gfx_v10_0_write_data_to_reg(ring, 0, false,
7577                                     SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_SIZE) + 2 * vmid,
7578                                     gds_size);
7579
7580         /* GWS */
7581         gfx_v10_0_write_data_to_reg(ring, 0, false,
7582                                     SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID0) + vmid,
7583                                     gws_size << GDS_GWS_VMID0__SIZE__SHIFT | gws_base);
7584
7585         /* OA */
7586         gfx_v10_0_write_data_to_reg(ring, 0, false,
7587                                     SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID0) + vmid,
7588                                     (1 << (oa_size + oa_base)) - (1 << oa_base));
7589 }
7590
7591 static int gfx_v10_0_early_init(void *handle)
7592 {
7593         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7594
7595         switch (adev->asic_type) {
7596         case CHIP_NAVI10:
7597         case CHIP_NAVI14:
7598         case CHIP_NAVI12:
7599                 adev->gfx.num_gfx_rings = GFX10_NUM_GFX_RINGS_NV1X;
7600                 break;
7601         case CHIP_SIENNA_CICHLID:
7602         case CHIP_NAVY_FLOUNDER:
7603         case CHIP_VANGOGH:
7604         case CHIP_DIMGREY_CAVEFISH:
7605         case CHIP_BEIGE_GOBY:
7606                 adev->gfx.num_gfx_rings = GFX10_NUM_GFX_RINGS_Sienna_Cichlid;
7607                 break;
7608         default:
7609                 break;
7610         }
7611
7612         adev->gfx.num_compute_rings = min(amdgpu_gfx_get_num_kcq(adev),
7613                                           AMDGPU_MAX_COMPUTE_RINGS);
7614
7615         gfx_v10_0_set_kiq_pm4_funcs(adev);
7616         gfx_v10_0_set_ring_funcs(adev);
7617         gfx_v10_0_set_irq_funcs(adev);
7618         gfx_v10_0_set_gds_init(adev);
7619         gfx_v10_0_set_rlc_funcs(adev);
7620
7621         return 0;
7622 }
7623
7624 static int gfx_v10_0_late_init(void *handle)
7625 {
7626         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7627         int r;
7628
7629         r = amdgpu_irq_get(adev, &adev->gfx.priv_reg_irq, 0);
7630         if (r)
7631                 return r;
7632
7633         r = amdgpu_irq_get(adev, &adev->gfx.priv_inst_irq, 0);
7634         if (r)
7635                 return r;
7636
7637         return 0;
7638 }
7639
7640 static bool gfx_v10_0_is_rlc_enabled(struct amdgpu_device *adev)
7641 {
7642         uint32_t rlc_cntl;
7643
7644         /* if RLC is not enabled, do nothing */
7645         rlc_cntl = RREG32_SOC15(GC, 0, mmRLC_CNTL);
7646         return (REG_GET_FIELD(rlc_cntl, RLC_CNTL, RLC_ENABLE_F32)) ? true : false;
7647 }
7648
7649 static void gfx_v10_0_set_safe_mode(struct amdgpu_device *adev)
7650 {
7651         uint32_t data;
7652         unsigned i;
7653
7654         data = RLC_SAFE_MODE__CMD_MASK;
7655         data |= (1 << RLC_SAFE_MODE__MESSAGE__SHIFT);
7656
7657         switch (adev->asic_type) {
7658         case CHIP_SIENNA_CICHLID:
7659         case CHIP_NAVY_FLOUNDER:
7660         case CHIP_VANGOGH:
7661         case CHIP_DIMGREY_CAVEFISH:
7662         case CHIP_BEIGE_GOBY:
7663                 WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE_Sienna_Cichlid, data);
7664
7665                 /* wait for RLC_SAFE_MODE */
7666                 for (i = 0; i < adev->usec_timeout; i++) {
7667                         if (!REG_GET_FIELD(RREG32_SOC15(GC, 0, mmRLC_SAFE_MODE_Sienna_Cichlid),
7668                                            RLC_SAFE_MODE, CMD))
7669                                 break;
7670                         udelay(1);
7671                 }
7672                 break;
7673         default:
7674                 WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE, data);
7675
7676                 /* wait for RLC_SAFE_MODE */
7677                 for (i = 0; i < adev->usec_timeout; i++) {
7678                         if (!REG_GET_FIELD(RREG32_SOC15(GC, 0, mmRLC_SAFE_MODE),
7679                                            RLC_SAFE_MODE, CMD))
7680                                 break;
7681                         udelay(1);
7682                 }
7683                 break;
7684         }
7685 }
7686
7687 static void gfx_v10_0_unset_safe_mode(struct amdgpu_device *adev)
7688 {
7689         uint32_t data;
7690
7691         data = RLC_SAFE_MODE__CMD_MASK;
7692         switch (adev->asic_type) {
7693         case CHIP_SIENNA_CICHLID:
7694         case CHIP_NAVY_FLOUNDER:
7695         case CHIP_VANGOGH:
7696         case CHIP_DIMGREY_CAVEFISH:
7697         case CHIP_BEIGE_GOBY:
7698                 WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE_Sienna_Cichlid, data);
7699                 break;
7700         default:
7701                 WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE, data);
7702                 break;
7703         }
7704 }
7705
7706 static void gfx_v10_0_update_medium_grain_clock_gating(struct amdgpu_device *adev,
7707                                                       bool enable)
7708 {
7709         uint32_t data, def;
7710
7711         /* It is disabled by HW by default */
7712         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) {
7713                 /* 0 - Disable some blocks' MGCG */
7714                 WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, 0xe0000000);
7715                 WREG32_SOC15(GC, 0, mmCGTT_WD_CLK_CTRL, 0xff000000);
7716                 WREG32_SOC15(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xff000000);
7717                 WREG32_SOC15(GC, 0, mmCGTT_IA_CLK_CTRL, 0xff000000);
7718
7719                 /* 1 - RLC_CGTT_MGCG_OVERRIDE */
7720                 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
7721                 data &= ~(RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK |
7722                           RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK |
7723                           RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK |
7724                           RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK |
7725                           RLC_CGTT_MGCG_OVERRIDE__ENABLE_CGTS_LEGACY_MASK);
7726
7727                 if (def != data)
7728                         WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
7729
7730                 /* MGLS is a global flag to control all MGLS in GFX */
7731                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGLS) {
7732                         /* 2 - RLC memory Light sleep */
7733                         if (adev->cg_flags & AMD_CG_SUPPORT_GFX_RLC_LS) {
7734                                 def = data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL);
7735                                 data |= RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK;
7736                                 if (def != data)
7737                                         WREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL, data);
7738                         }
7739                         /* 3 - CP memory Light sleep */
7740                         if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CP_LS) {
7741                                 def = data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL);
7742                                 data |= CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK;
7743                                 if (def != data)
7744                                         WREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL, data);
7745                         }
7746                 }
7747         } else {
7748                 /* 1 - MGCG_OVERRIDE */
7749                 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
7750                 data |= (RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK |
7751                          RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK |
7752                          RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK |
7753                          RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK);
7754                 if (def != data)
7755                         WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
7756
7757                 /* 2 - disable MGLS in CP */
7758                 data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL);
7759                 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) {
7760                         data &= ~CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK;
7761                         WREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL, data);
7762                 }
7763
7764                 /* 3 - disable MGLS in RLC */
7765                 data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL);
7766                 if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK) {
7767                         data &= ~RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK;
7768                         WREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL, data);
7769                 }
7770
7771         }
7772 }
7773
7774 static void gfx_v10_0_update_3d_clock_gating(struct amdgpu_device *adev,
7775                                            bool enable)
7776 {
7777         uint32_t data, def;
7778
7779         /* Enable 3D CGCG/CGLS */
7780         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG)) {
7781                 /* write cmd to clear cgcg/cgls ov */
7782                 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
7783                 /* unset CGCG override */
7784                 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_GFX3D_CG_OVERRIDE_MASK;
7785                 /* update CGCG and CGLS override bits */
7786                 if (def != data)
7787                         WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
7788                 /* enable 3Dcgcg FSM(0x0000363f) */
7789                 def = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D);
7790                 data = (0x36 << RLC_CGCG_CGLS_CTRL_3D__CGCG_GFX_IDLE_THRESHOLD__SHIFT) |
7791                         RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK;
7792                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS)
7793                         data |= (0x000F << RLC_CGCG_CGLS_CTRL_3D__CGLS_REP_COMPANSAT_DELAY__SHIFT) |
7794                                 RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK;
7795                 if (def != data)
7796                         WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D, data);
7797
7798                 /* set IDLE_POLL_COUNT(0x00900100) */
7799                 def = RREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL);
7800                 data = (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) |
7801                         (0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT);
7802                 if (def != data)
7803                         WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL, data);
7804         } else {
7805                 /* Disable CGCG/CGLS */
7806                 def = data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D);
7807                 /* disable cgcg, cgls should be disabled */
7808                 data &= ~(RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK |
7809                           RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK);
7810                 /* disable cgcg and cgls in FSM */
7811                 if (def != data)
7812                         WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D, data);
7813         }
7814 }
7815
7816 static void gfx_v10_0_update_coarse_grain_clock_gating(struct amdgpu_device *adev,
7817                                                       bool enable)
7818 {
7819         uint32_t def, data;
7820
7821         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)) {
7822                 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
7823                 /* unset CGCG override */
7824                 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGCG_OVERRIDE_MASK;
7825                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS)
7826                         data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK;
7827                 else
7828                         data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK;
7829                 /* update CGCG and CGLS override bits */
7830                 if (def != data)
7831                         WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
7832
7833                 /* enable cgcg FSM(0x0000363F) */
7834                 def = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL);
7835                 data = (0x36 << RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT) |
7836                         RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK;
7837                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS)
7838                         data |= (0x000F << RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY__SHIFT) |
7839                                 RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK;
7840                 if (def != data)
7841                         WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, data);
7842
7843                 /* set IDLE_POLL_COUNT(0x00900100) */
7844                 def = RREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL);
7845                 data = (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) |
7846                         (0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT);
7847                 if (def != data)
7848                         WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL, data);
7849         } else {
7850                 def = data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL);
7851                 /* reset CGCG/CGLS bits */
7852                 data &= ~(RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK | RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK);
7853                 /* disable cgcg and cgls in FSM */
7854                 if (def != data)
7855                         WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, data);
7856         }
7857 }
7858
7859 static void gfx_v10_0_update_fine_grain_clock_gating(struct amdgpu_device *adev,
7860                                                       bool enable)
7861 {
7862         uint32_t def, data;
7863
7864         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_FGCG)) {
7865                 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
7866                 /* unset FGCG override */
7867                 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK;
7868                 /* update FGCG override bits */
7869                 if (def != data)
7870                         WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
7871
7872                 def = data = RREG32_SOC15(GC, 0, mmRLC_CLK_CNTL);
7873                 /* unset RLC SRAM CLK GATER override */
7874                 data &= ~RLC_CLK_CNTL__RLC_SRAM_CLK_GATER_OVERRIDE_MASK;
7875                 /* update RLC SRAM CLK GATER override bits */
7876                 if (def != data)
7877                         WREG32_SOC15(GC, 0, mmRLC_CLK_CNTL, data);
7878         } else {
7879                 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
7880                 /* reset FGCG bits */
7881                 data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK;
7882                 /* disable FGCG*/
7883                 if (def != data)
7884                         WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
7885
7886                 def = data = RREG32_SOC15(GC, 0, mmRLC_CLK_CNTL);
7887                 /* reset RLC SRAM CLK GATER bits */
7888                 data |= RLC_CLK_CNTL__RLC_SRAM_CLK_GATER_OVERRIDE_MASK;
7889                 /* disable RLC SRAM CLK*/
7890                 if (def != data)
7891                         WREG32_SOC15(GC, 0, mmRLC_CLK_CNTL, data);
7892         }
7893 }
7894
7895 static int gfx_v10_0_update_gfx_clock_gating(struct amdgpu_device *adev,
7896                                             bool enable)
7897 {
7898         amdgpu_gfx_rlc_enter_safe_mode(adev);
7899
7900         if (enable) {
7901                 /* enable FGCG firstly*/
7902                 gfx_v10_0_update_fine_grain_clock_gating(adev, enable);
7903                 /* CGCG/CGLS should be enabled after MGCG/MGLS
7904                  * ===  MGCG + MGLS ===
7905                  */
7906                 gfx_v10_0_update_medium_grain_clock_gating(adev, enable);
7907                 /* ===  CGCG /CGLS for GFX 3D Only === */
7908                 gfx_v10_0_update_3d_clock_gating(adev, enable);
7909                 /* ===  CGCG + CGLS === */
7910                 gfx_v10_0_update_coarse_grain_clock_gating(adev, enable);
7911         } else {
7912                 /* CGCG/CGLS should be disabled before MGCG/MGLS
7913                  * ===  CGCG + CGLS ===
7914                  */
7915                 gfx_v10_0_update_coarse_grain_clock_gating(adev, enable);
7916                 /* ===  CGCG /CGLS for GFX 3D Only === */
7917                 gfx_v10_0_update_3d_clock_gating(adev, enable);
7918                 /* ===  MGCG + MGLS === */
7919                 gfx_v10_0_update_medium_grain_clock_gating(adev, enable);
7920                 /* disable fgcg at last*/
7921                 gfx_v10_0_update_fine_grain_clock_gating(adev, enable);
7922         }
7923
7924         if (adev->cg_flags &
7925             (AMD_CG_SUPPORT_GFX_MGCG |
7926              AMD_CG_SUPPORT_GFX_CGLS |
7927              AMD_CG_SUPPORT_GFX_CGCG |
7928              AMD_CG_SUPPORT_GFX_3D_CGCG |
7929              AMD_CG_SUPPORT_GFX_3D_CGLS))
7930                 gfx_v10_0_enable_gui_idle_interrupt(adev, enable);
7931
7932         amdgpu_gfx_rlc_exit_safe_mode(adev);
7933
7934         return 0;
7935 }
7936
7937 static void gfx_v10_0_update_spm_vmid(struct amdgpu_device *adev, unsigned vmid)
7938 {
7939         u32 reg, data;
7940
7941         reg = SOC15_REG_OFFSET(GC, 0, mmRLC_SPM_MC_CNTL);
7942         if (amdgpu_sriov_is_pp_one_vf(adev))
7943                 data = RREG32_NO_KIQ(reg);
7944         else
7945                 data = RREG32(reg);
7946
7947         data &= ~RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK;
7948         data |= (vmid & RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK) << RLC_SPM_MC_CNTL__RLC_SPM_VMID__SHIFT;
7949
7950         if (amdgpu_sriov_is_pp_one_vf(adev))
7951                 WREG32_SOC15_NO_KIQ(GC, 0, mmRLC_SPM_MC_CNTL, data);
7952         else
7953                 WREG32_SOC15(GC, 0, mmRLC_SPM_MC_CNTL, data);
7954 }
7955
7956 static bool gfx_v10_0_check_rlcg_range(struct amdgpu_device *adev,
7957                                         uint32_t offset,
7958                                         struct soc15_reg_rlcg *entries, int arr_size)
7959 {
7960         int i;
7961         uint32_t reg;
7962
7963         if (!entries)
7964                 return false;
7965
7966         for (i = 0; i < arr_size; i++) {
7967                 const struct soc15_reg_rlcg *entry;
7968
7969                 entry = &entries[i];
7970                 reg = adev->reg_offset[entry->hwip][entry->instance][entry->segment] + entry->reg;
7971                 if (offset == reg)
7972                         return true;
7973         }
7974
7975         return false;
7976 }
7977
7978 static bool gfx_v10_0_is_rlcg_access_range(struct amdgpu_device *adev, u32 offset)
7979 {
7980         return gfx_v10_0_check_rlcg_range(adev, offset, NULL, 0);
7981 }
7982
7983 static void gfx_v10_cntl_power_gating(struct amdgpu_device *adev, bool enable)
7984 {
7985         u32 data = RREG32_SOC15(GC, 0, mmRLC_PG_CNTL);
7986
7987         if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG))
7988                 data |= RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK;
7989         else
7990                 data &= ~RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK;
7991
7992         WREG32_SOC15(GC, 0, mmRLC_PG_CNTL, data);
7993
7994         /*
7995          * CGPG enablement required and the register to program the hysteresis value
7996          * RLC_PG_DELAY_3.CGCG_ACTIVE_BEFORE_CGPG to the desired CGPG hysteresis value
7997          * in refclk count. Note that RLC FW is modified to take 16 bits from
7998          * RLC_PG_DELAY_3[15:0] as the hysteresis instead of just 8 bits.
7999          *
8000          * The recommendation from RLC team is setting RLC_PG_DELAY_3 to 200us(0x4E20)
8001          * as part of CGPG enablement starting point.
8002          */
8003         if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG) && adev->asic_type == CHIP_VANGOGH) {
8004                 data = 0x4E20 & RLC_PG_DELAY_3__CGCG_ACTIVE_BEFORE_CGPG_MASK_Vangogh;
8005                 WREG32_SOC15(GC, 0, mmRLC_PG_DELAY_3, data);
8006         }
8007 }
8008
8009 static void gfx_v10_cntl_pg(struct amdgpu_device *adev, bool enable)
8010 {
8011         amdgpu_gfx_rlc_enter_safe_mode(adev);
8012
8013         gfx_v10_cntl_power_gating(adev, enable);
8014
8015         amdgpu_gfx_rlc_exit_safe_mode(adev);
8016 }
8017
8018 static const struct amdgpu_rlc_funcs gfx_v10_0_rlc_funcs = {
8019         .is_rlc_enabled = gfx_v10_0_is_rlc_enabled,
8020         .set_safe_mode = gfx_v10_0_set_safe_mode,
8021         .unset_safe_mode = gfx_v10_0_unset_safe_mode,
8022         .init = gfx_v10_0_rlc_init,
8023         .get_csb_size = gfx_v10_0_get_csb_size,
8024         .get_csb_buffer = gfx_v10_0_get_csb_buffer,
8025         .resume = gfx_v10_0_rlc_resume,
8026         .stop = gfx_v10_0_rlc_stop,
8027         .reset = gfx_v10_0_rlc_reset,
8028         .start = gfx_v10_0_rlc_start,
8029         .update_spm_vmid = gfx_v10_0_update_spm_vmid,
8030 };
8031
8032 static const struct amdgpu_rlc_funcs gfx_v10_0_rlc_funcs_sriov = {
8033         .is_rlc_enabled = gfx_v10_0_is_rlc_enabled,
8034         .set_safe_mode = gfx_v10_0_set_safe_mode,
8035         .unset_safe_mode = gfx_v10_0_unset_safe_mode,
8036         .init = gfx_v10_0_rlc_init,
8037         .get_csb_size = gfx_v10_0_get_csb_size,
8038         .get_csb_buffer = gfx_v10_0_get_csb_buffer,
8039         .resume = gfx_v10_0_rlc_resume,
8040         .stop = gfx_v10_0_rlc_stop,
8041         .reset = gfx_v10_0_rlc_reset,
8042         .start = gfx_v10_0_rlc_start,
8043         .update_spm_vmid = gfx_v10_0_update_spm_vmid,
8044         .rlcg_wreg = gfx_v10_rlcg_wreg,
8045         .rlcg_rreg = gfx_v10_rlcg_rreg,
8046         .is_rlcg_access_range = gfx_v10_0_is_rlcg_access_range,
8047 };
8048
8049 static int gfx_v10_0_set_powergating_state(void *handle,
8050                                           enum amd_powergating_state state)
8051 {
8052         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
8053         bool enable = (state == AMD_PG_STATE_GATE);
8054
8055         if (amdgpu_sriov_vf(adev))
8056                 return 0;
8057
8058         switch (adev->asic_type) {
8059         case CHIP_NAVI10:
8060         case CHIP_NAVI14:
8061         case CHIP_NAVI12:
8062         case CHIP_SIENNA_CICHLID:
8063         case CHIP_NAVY_FLOUNDER:
8064         case CHIP_DIMGREY_CAVEFISH:
8065                 amdgpu_gfx_off_ctrl(adev, enable);
8066                 break;
8067         case CHIP_VANGOGH:
8068                 gfx_v10_cntl_pg(adev, enable);
8069                 amdgpu_gfx_off_ctrl(adev, enable);
8070                 break;
8071         default:
8072                 break;
8073         }
8074         return 0;
8075 }
8076
8077 static int gfx_v10_0_set_clockgating_state(void *handle,
8078                                           enum amd_clockgating_state state)
8079 {
8080         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
8081
8082         if (amdgpu_sriov_vf(adev))
8083                 return 0;
8084
8085         switch (adev->asic_type) {
8086         case CHIP_NAVI10:
8087         case CHIP_NAVI14:
8088         case CHIP_NAVI12:
8089         case CHIP_SIENNA_CICHLID:
8090         case CHIP_NAVY_FLOUNDER:
8091         case CHIP_VANGOGH:
8092         case CHIP_DIMGREY_CAVEFISH:
8093         case CHIP_BEIGE_GOBY:
8094                 gfx_v10_0_update_gfx_clock_gating(adev,
8095                                                  state == AMD_CG_STATE_GATE);
8096                 break;
8097         default:
8098                 break;
8099         }
8100         return 0;
8101 }
8102
8103 static void gfx_v10_0_get_clockgating_state(void *handle, u32 *flags)
8104 {
8105         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
8106         int data;
8107
8108         /* AMD_CG_SUPPORT_GFX_FGCG */
8109         data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE));
8110         if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK))
8111                 *flags |= AMD_CG_SUPPORT_GFX_FGCG;
8112
8113         /* AMD_CG_SUPPORT_GFX_MGCG */
8114         data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE));
8115         if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK))
8116                 *flags |= AMD_CG_SUPPORT_GFX_MGCG;
8117
8118         /* AMD_CG_SUPPORT_GFX_CGCG */
8119         data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGCG_CGLS_CTRL));
8120         if (data & RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK)
8121                 *flags |= AMD_CG_SUPPORT_GFX_CGCG;
8122
8123         /* AMD_CG_SUPPORT_GFX_CGLS */
8124         if (data & RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK)
8125                 *flags |= AMD_CG_SUPPORT_GFX_CGLS;
8126
8127         /* AMD_CG_SUPPORT_GFX_RLC_LS */
8128         data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_MEM_SLP_CNTL));
8129         if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK)
8130                 *flags |= AMD_CG_SUPPORT_GFX_RLC_LS | AMD_CG_SUPPORT_GFX_MGLS;
8131
8132         /* AMD_CG_SUPPORT_GFX_CP_LS */
8133         data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmCP_MEM_SLP_CNTL));
8134         if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK)
8135                 *flags |= AMD_CG_SUPPORT_GFX_CP_LS | AMD_CG_SUPPORT_GFX_MGLS;
8136
8137         /* AMD_CG_SUPPORT_GFX_3D_CGCG */
8138         data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D));
8139         if (data & RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK)
8140                 *flags |= AMD_CG_SUPPORT_GFX_3D_CGCG;
8141
8142         /* AMD_CG_SUPPORT_GFX_3D_CGLS */
8143         if (data & RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK)
8144                 *flags |= AMD_CG_SUPPORT_GFX_3D_CGLS;
8145 }
8146
8147 static u64 gfx_v10_0_ring_get_rptr_gfx(struct amdgpu_ring *ring)
8148 {
8149         return ring->adev->wb.wb[ring->rptr_offs]; /* gfx10 is 32bit rptr*/
8150 }
8151
8152 static u64 gfx_v10_0_ring_get_wptr_gfx(struct amdgpu_ring *ring)
8153 {
8154         struct amdgpu_device *adev = ring->adev;
8155         u64 wptr;
8156
8157         /* XXX check if swapping is necessary on BE */
8158         if (ring->use_doorbell) {
8159                 wptr = atomic64_read((atomic64_t *)&adev->wb.wb[ring->wptr_offs]);
8160         } else {
8161                 wptr = RREG32_SOC15(GC, 0, mmCP_RB0_WPTR);
8162                 wptr += (u64)RREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI) << 32;
8163         }
8164
8165         return wptr;
8166 }
8167
8168 static void gfx_v10_0_ring_set_wptr_gfx(struct amdgpu_ring *ring)
8169 {
8170         struct amdgpu_device *adev = ring->adev;
8171
8172         if (ring->use_doorbell) {
8173                 /* XXX check if swapping is necessary on BE */
8174                 atomic64_set((atomic64_t *)&adev->wb.wb[ring->wptr_offs], ring->wptr);
8175                 WDOORBELL64(ring->doorbell_index, ring->wptr);
8176         } else {
8177                 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR, lower_32_bits(ring->wptr));
8178                 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI, upper_32_bits(ring->wptr));
8179         }
8180 }
8181
8182 static u64 gfx_v10_0_ring_get_rptr_compute(struct amdgpu_ring *ring)
8183 {
8184         return ring->adev->wb.wb[ring->rptr_offs]; /* gfx10 hardware is 32bit rptr */
8185 }
8186
8187 static u64 gfx_v10_0_ring_get_wptr_compute(struct amdgpu_ring *ring)
8188 {
8189         u64 wptr;
8190
8191         /* XXX check if swapping is necessary on BE */
8192         if (ring->use_doorbell)
8193                 wptr = atomic64_read((atomic64_t *)&ring->adev->wb.wb[ring->wptr_offs]);
8194         else
8195                 BUG();
8196         return wptr;
8197 }
8198
8199 static void gfx_v10_0_ring_set_wptr_compute(struct amdgpu_ring *ring)
8200 {
8201         struct amdgpu_device *adev = ring->adev;
8202
8203         /* XXX check if swapping is necessary on BE */
8204         if (ring->use_doorbell) {
8205                 atomic64_set((atomic64_t *)&adev->wb.wb[ring->wptr_offs], ring->wptr);
8206                 WDOORBELL64(ring->doorbell_index, ring->wptr);
8207         } else {
8208                 BUG(); /* only DOORBELL method supported on gfx10 now */
8209         }
8210 }
8211
8212 static void gfx_v10_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
8213 {
8214         struct amdgpu_device *adev = ring->adev;
8215         u32 ref_and_mask, reg_mem_engine;
8216         const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio.hdp_flush_reg;
8217
8218         if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) {
8219                 switch (ring->me) {
8220                 case 1:
8221                         ref_and_mask = nbio_hf_reg->ref_and_mask_cp2 << ring->pipe;
8222                         break;
8223                 case 2:
8224                         ref_and_mask = nbio_hf_reg->ref_and_mask_cp6 << ring->pipe;
8225                         break;
8226                 default:
8227                         return;
8228                 }
8229                 reg_mem_engine = 0;
8230         } else {
8231                 ref_and_mask = nbio_hf_reg->ref_and_mask_cp0;
8232                 reg_mem_engine = 1; /* pfp */
8233         }
8234
8235         gfx_v10_0_wait_reg_mem(ring, reg_mem_engine, 0, 1,
8236                                adev->nbio.funcs->get_hdp_flush_req_offset(adev),
8237                                adev->nbio.funcs->get_hdp_flush_done_offset(adev),
8238                                ref_and_mask, ref_and_mask, 0x20);
8239 }
8240
8241 static void gfx_v10_0_ring_emit_ib_gfx(struct amdgpu_ring *ring,
8242                                        struct amdgpu_job *job,
8243                                        struct amdgpu_ib *ib,
8244                                        uint32_t flags)
8245 {
8246         unsigned vmid = AMDGPU_JOB_GET_VMID(job);
8247         u32 header, control = 0;
8248
8249         if (ib->flags & AMDGPU_IB_FLAG_CE)
8250                 header = PACKET3(PACKET3_INDIRECT_BUFFER_CNST, 2);
8251         else
8252                 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2);
8253
8254         control |= ib->length_dw | (vmid << 24);
8255
8256         if ((amdgpu_sriov_vf(ring->adev) || amdgpu_mcbp) && (ib->flags & AMDGPU_IB_FLAG_PREEMPT)) {
8257                 control |= INDIRECT_BUFFER_PRE_ENB(1);
8258
8259                 if (flags & AMDGPU_IB_PREEMPTED)
8260                         control |= INDIRECT_BUFFER_PRE_RESUME(1);
8261
8262                 if (!(ib->flags & AMDGPU_IB_FLAG_CE) && vmid)
8263                         gfx_v10_0_ring_emit_de_meta(ring,
8264                                     (!amdgpu_sriov_vf(ring->adev) && flags & AMDGPU_IB_PREEMPTED) ? true : false);
8265         }
8266
8267         amdgpu_ring_write(ring, header);
8268         BUG_ON(ib->gpu_addr & 0x3); /* Dword align */
8269         amdgpu_ring_write(ring,
8270 #ifdef __BIG_ENDIAN
8271                 (2 << 0) |
8272 #endif
8273                 lower_32_bits(ib->gpu_addr));
8274         amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
8275         amdgpu_ring_write(ring, control);
8276 }
8277
8278 static void gfx_v10_0_ring_emit_ib_compute(struct amdgpu_ring *ring,
8279                                            struct amdgpu_job *job,
8280                                            struct amdgpu_ib *ib,
8281                                            uint32_t flags)
8282 {
8283         unsigned vmid = AMDGPU_JOB_GET_VMID(job);
8284         u32 control = INDIRECT_BUFFER_VALID | ib->length_dw | (vmid << 24);
8285
8286         /* Currently, there is a high possibility to get wave ID mismatch
8287          * between ME and GDS, leading to a hw deadlock, because ME generates
8288          * different wave IDs than the GDS expects. This situation happens
8289          * randomly when at least 5 compute pipes use GDS ordered append.
8290          * The wave IDs generated by ME are also wrong after suspend/resume.
8291          * Those are probably bugs somewhere else in the kernel driver.
8292          *
8293          * Writing GDS_COMPUTE_MAX_WAVE_ID resets wave ID counters in ME and
8294          * GDS to 0 for this ring (me/pipe).
8295          */
8296         if (ib->flags & AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID) {
8297                 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
8298                 amdgpu_ring_write(ring, mmGDS_COMPUTE_MAX_WAVE_ID);
8299                 amdgpu_ring_write(ring, ring->adev->gds.gds_compute_max_wave_id);
8300         }
8301
8302         amdgpu_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
8303         BUG_ON(ib->gpu_addr & 0x3); /* Dword align */
8304         amdgpu_ring_write(ring,
8305 #ifdef __BIG_ENDIAN
8306                                 (2 << 0) |
8307 #endif
8308                                 lower_32_bits(ib->gpu_addr));
8309         amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
8310         amdgpu_ring_write(ring, control);
8311 }
8312
8313 static void gfx_v10_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr,
8314                                      u64 seq, unsigned flags)
8315 {
8316         bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
8317         bool int_sel = flags & AMDGPU_FENCE_FLAG_INT;
8318
8319         /* RELEASE_MEM - flush caches, send int */
8320         amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 6));
8321         amdgpu_ring_write(ring, (PACKET3_RELEASE_MEM_GCR_SEQ |
8322                                  PACKET3_RELEASE_MEM_GCR_GL2_WB |
8323                                  PACKET3_RELEASE_MEM_GCR_GLM_INV | /* must be set with GLM_WB */
8324                                  PACKET3_RELEASE_MEM_GCR_GLM_WB |
8325                                  PACKET3_RELEASE_MEM_CACHE_POLICY(3) |
8326                                  PACKET3_RELEASE_MEM_EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) |
8327                                  PACKET3_RELEASE_MEM_EVENT_INDEX(5)));
8328         amdgpu_ring_write(ring, (PACKET3_RELEASE_MEM_DATA_SEL(write64bit ? 2 : 1) |
8329                                  PACKET3_RELEASE_MEM_INT_SEL(int_sel ? 2 : 0)));
8330
8331         /*
8332          * the address should be Qword aligned if 64bit write, Dword
8333          * aligned if only send 32bit data low (discard data high)
8334          */
8335         if (write64bit)
8336                 BUG_ON(addr & 0x7);
8337         else
8338                 BUG_ON(addr & 0x3);
8339         amdgpu_ring_write(ring, lower_32_bits(addr));
8340         amdgpu_ring_write(ring, upper_32_bits(addr));
8341         amdgpu_ring_write(ring, lower_32_bits(seq));
8342         amdgpu_ring_write(ring, upper_32_bits(seq));
8343         amdgpu_ring_write(ring, 0);
8344 }
8345
8346 static void gfx_v10_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
8347 {
8348         int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
8349         uint32_t seq = ring->fence_drv.sync_seq;
8350         uint64_t addr = ring->fence_drv.gpu_addr;
8351
8352         gfx_v10_0_wait_reg_mem(ring, usepfp, 1, 0, lower_32_bits(addr),
8353                                upper_32_bits(addr), seq, 0xffffffff, 4);
8354 }
8355
8356 static void gfx_v10_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
8357                                          unsigned vmid, uint64_t pd_addr)
8358 {
8359         amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
8360
8361         /* compute doesn't have PFP */
8362         if (ring->funcs->type == AMDGPU_RING_TYPE_GFX) {
8363                 /* sync PFP to ME, otherwise we might get invalid PFP reads */
8364                 amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0));
8365                 amdgpu_ring_write(ring, 0x0);
8366         }
8367 }
8368
8369 static void gfx_v10_0_ring_emit_fence_kiq(struct amdgpu_ring *ring, u64 addr,
8370                                           u64 seq, unsigned int flags)
8371 {
8372         struct amdgpu_device *adev = ring->adev;
8373
8374         /* we only allocate 32bit for each seq wb address */
8375         BUG_ON(flags & AMDGPU_FENCE_FLAG_64BIT);
8376
8377         /* write fence seq to the "addr" */
8378         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
8379         amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
8380                                  WRITE_DATA_DST_SEL(5) | WR_CONFIRM));
8381         amdgpu_ring_write(ring, lower_32_bits(addr));
8382         amdgpu_ring_write(ring, upper_32_bits(addr));
8383         amdgpu_ring_write(ring, lower_32_bits(seq));
8384
8385         if (flags & AMDGPU_FENCE_FLAG_INT) {
8386                 /* set register to trigger INT */
8387                 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
8388                 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
8389                                          WRITE_DATA_DST_SEL(0) | WR_CONFIRM));
8390                 amdgpu_ring_write(ring, SOC15_REG_OFFSET(GC, 0, mmCPC_INT_STATUS));
8391                 amdgpu_ring_write(ring, 0);
8392                 amdgpu_ring_write(ring, 0x20000000); /* src_id is 178 */
8393         }
8394 }
8395
8396 static void gfx_v10_0_ring_emit_sb(struct amdgpu_ring *ring)
8397 {
8398         amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
8399         amdgpu_ring_write(ring, 0);
8400 }
8401
8402 static void gfx_v10_0_ring_emit_cntxcntl(struct amdgpu_ring *ring,
8403                                          uint32_t flags)
8404 {
8405         uint32_t dw2 = 0;
8406
8407         if (amdgpu_mcbp || amdgpu_sriov_vf(ring->adev))
8408                 gfx_v10_0_ring_emit_ce_meta(ring,
8409                                     (!amdgpu_sriov_vf(ring->adev) && flags & AMDGPU_IB_PREEMPTED) ? true : false);
8410
8411         dw2 |= 0x80000000; /* set load_enable otherwise this package is just NOPs */
8412         if (flags & AMDGPU_HAVE_CTX_SWITCH) {
8413                 /* set load_global_config & load_global_uconfig */
8414                 dw2 |= 0x8001;
8415                 /* set load_cs_sh_regs */
8416                 dw2 |= 0x01000000;
8417                 /* set load_per_context_state & load_gfx_sh_regs for GFX */
8418                 dw2 |= 0x10002;
8419
8420                 /* set load_ce_ram if preamble presented */
8421                 if (AMDGPU_PREAMBLE_IB_PRESENT & flags)
8422                         dw2 |= 0x10000000;
8423         } else {
8424                 /* still load_ce_ram if this is the first time preamble presented
8425                  * although there is no context switch happens.
8426                  */
8427                 if (AMDGPU_PREAMBLE_IB_PRESENT_FIRST & flags)
8428                         dw2 |= 0x10000000;
8429         }
8430
8431         amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1));
8432         amdgpu_ring_write(ring, dw2);
8433         amdgpu_ring_write(ring, 0);
8434 }
8435
8436 static unsigned gfx_v10_0_ring_emit_init_cond_exec(struct amdgpu_ring *ring)
8437 {
8438         unsigned ret;
8439
8440         amdgpu_ring_write(ring, PACKET3(PACKET3_COND_EXEC, 3));
8441         amdgpu_ring_write(ring, lower_32_bits(ring->cond_exe_gpu_addr));
8442         amdgpu_ring_write(ring, upper_32_bits(ring->cond_exe_gpu_addr));
8443         amdgpu_ring_write(ring, 0); /* discard following DWs if *cond_exec_gpu_addr==0 */
8444         ret = ring->wptr & ring->buf_mask;
8445         amdgpu_ring_write(ring, 0x55aa55aa); /* patch dummy value later */
8446
8447         return ret;
8448 }
8449
8450 static void gfx_v10_0_ring_emit_patch_cond_exec(struct amdgpu_ring *ring, unsigned offset)
8451 {
8452         unsigned cur;
8453         BUG_ON(offset > ring->buf_mask);
8454         BUG_ON(ring->ring[offset] != 0x55aa55aa);
8455
8456         cur = (ring->wptr - 1) & ring->buf_mask;
8457         if (likely(cur > offset))
8458                 ring->ring[offset] = cur - offset;
8459         else
8460                 ring->ring[offset] = (ring->buf_mask + 1) - offset + cur;
8461 }
8462
8463 static int gfx_v10_0_ring_preempt_ib(struct amdgpu_ring *ring)
8464 {
8465         int i, r = 0;
8466         struct amdgpu_device *adev = ring->adev;
8467         struct amdgpu_kiq *kiq = &adev->gfx.kiq;
8468         struct amdgpu_ring *kiq_ring = &kiq->ring;
8469         unsigned long flags;
8470
8471         if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues)
8472                 return -EINVAL;
8473
8474         spin_lock_irqsave(&kiq->ring_lock, flags);
8475
8476         if (amdgpu_ring_alloc(kiq_ring, kiq->pmf->unmap_queues_size)) {
8477                 spin_unlock_irqrestore(&kiq->ring_lock, flags);
8478                 return -ENOMEM;
8479         }
8480
8481         /* assert preemption condition */
8482         amdgpu_ring_set_preempt_cond_exec(ring, false);
8483
8484         /* assert IB preemption, emit the trailing fence */
8485         kiq->pmf->kiq_unmap_queues(kiq_ring, ring, PREEMPT_QUEUES_NO_UNMAP,
8486                                    ring->trail_fence_gpu_addr,
8487                                    ++ring->trail_seq);
8488         amdgpu_ring_commit(kiq_ring);
8489
8490         spin_unlock_irqrestore(&kiq->ring_lock, flags);
8491
8492         /* poll the trailing fence */
8493         for (i = 0; i < adev->usec_timeout; i++) {
8494                 if (ring->trail_seq ==
8495                     le32_to_cpu(*(ring->trail_fence_cpu_addr)))
8496                         break;
8497                 udelay(1);
8498         }
8499
8500         if (i >= adev->usec_timeout) {
8501                 r = -EINVAL;
8502                 DRM_ERROR("ring %d failed to preempt ib\n", ring->idx);
8503         }
8504
8505         /* deassert preemption condition */
8506         amdgpu_ring_set_preempt_cond_exec(ring, true);
8507         return r;
8508 }
8509
8510 static void gfx_v10_0_ring_emit_ce_meta(struct amdgpu_ring *ring, bool resume)
8511 {
8512         struct amdgpu_device *adev = ring->adev;
8513         struct v10_ce_ib_state ce_payload = {0};
8514         uint64_t csa_addr;
8515         int cnt;
8516
8517         cnt = (sizeof(ce_payload) >> 2) + 4 - 2;
8518         csa_addr = amdgpu_csa_vaddr(ring->adev);
8519
8520         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt));
8521         amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(2) |
8522                                  WRITE_DATA_DST_SEL(8) |
8523                                  WR_CONFIRM) |
8524                                  WRITE_DATA_CACHE_POLICY(0));
8525         amdgpu_ring_write(ring, lower_32_bits(csa_addr +
8526                               offsetof(struct v10_gfx_meta_data, ce_payload)));
8527         amdgpu_ring_write(ring, upper_32_bits(csa_addr +
8528                               offsetof(struct v10_gfx_meta_data, ce_payload)));
8529
8530         if (resume)
8531                 amdgpu_ring_write_multiple(ring, adev->virt.csa_cpu_addr +
8532                                            offsetof(struct v10_gfx_meta_data,
8533                                                     ce_payload),
8534                                            sizeof(ce_payload) >> 2);
8535         else
8536                 amdgpu_ring_write_multiple(ring, (void *)&ce_payload,
8537                                            sizeof(ce_payload) >> 2);
8538 }
8539
8540 static void gfx_v10_0_ring_emit_de_meta(struct amdgpu_ring *ring, bool resume)
8541 {
8542         struct amdgpu_device *adev = ring->adev;
8543         struct v10_de_ib_state de_payload = {0};
8544         uint64_t csa_addr, gds_addr;
8545         int cnt;
8546
8547         csa_addr = amdgpu_csa_vaddr(ring->adev);
8548         gds_addr = ALIGN(csa_addr + AMDGPU_CSA_SIZE - adev->gds.gds_size,
8549                          PAGE_SIZE);
8550         de_payload.gds_backup_addrlo = lower_32_bits(gds_addr);
8551         de_payload.gds_backup_addrhi = upper_32_bits(gds_addr);
8552
8553         cnt = (sizeof(de_payload) >> 2) + 4 - 2;
8554         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt));
8555         amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(1) |
8556                                  WRITE_DATA_DST_SEL(8) |
8557                                  WR_CONFIRM) |
8558                                  WRITE_DATA_CACHE_POLICY(0));
8559         amdgpu_ring_write(ring, lower_32_bits(csa_addr +
8560                               offsetof(struct v10_gfx_meta_data, de_payload)));
8561         amdgpu_ring_write(ring, upper_32_bits(csa_addr +
8562                               offsetof(struct v10_gfx_meta_data, de_payload)));
8563
8564         if (resume)
8565                 amdgpu_ring_write_multiple(ring, adev->virt.csa_cpu_addr +
8566                                            offsetof(struct v10_gfx_meta_data,
8567                                                     de_payload),
8568                                            sizeof(de_payload) >> 2);
8569         else
8570                 amdgpu_ring_write_multiple(ring, (void *)&de_payload,
8571                                            sizeof(de_payload) >> 2);
8572 }
8573
8574 static void gfx_v10_0_ring_emit_frame_cntl(struct amdgpu_ring *ring, bool start,
8575                                     bool secure)
8576 {
8577         uint32_t v = secure ? FRAME_TMZ : 0;
8578
8579         amdgpu_ring_write(ring, PACKET3(PACKET3_FRAME_CONTROL, 0));
8580         amdgpu_ring_write(ring, v | FRAME_CMD(start ? 0 : 1));
8581 }
8582
8583 static void gfx_v10_0_ring_emit_rreg(struct amdgpu_ring *ring, uint32_t reg,
8584                                      uint32_t reg_val_offs)
8585 {
8586         struct amdgpu_device *adev = ring->adev;
8587
8588         amdgpu_ring_write(ring, PACKET3(PACKET3_COPY_DATA, 4));
8589         amdgpu_ring_write(ring, 0 |     /* src: register*/
8590                                 (5 << 8) |      /* dst: memory */
8591                                 (1 << 20));     /* write confirm */
8592         amdgpu_ring_write(ring, reg);
8593         amdgpu_ring_write(ring, 0);
8594         amdgpu_ring_write(ring, lower_32_bits(adev->wb.gpu_addr +
8595                                 reg_val_offs * 4));
8596         amdgpu_ring_write(ring, upper_32_bits(adev->wb.gpu_addr +
8597                                 reg_val_offs * 4));
8598 }
8599
8600 static void gfx_v10_0_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg,
8601                                    uint32_t val)
8602 {
8603         uint32_t cmd = 0;
8604
8605         switch (ring->funcs->type) {
8606         case AMDGPU_RING_TYPE_GFX:
8607                 cmd = WRITE_DATA_ENGINE_SEL(1) | WR_CONFIRM;
8608                 break;
8609         case AMDGPU_RING_TYPE_KIQ:
8610                 cmd = (1 << 16); /* no inc addr */
8611                 break;
8612         default:
8613                 cmd = WR_CONFIRM;
8614                 break;
8615         }
8616         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
8617         amdgpu_ring_write(ring, cmd);
8618         amdgpu_ring_write(ring, reg);
8619         amdgpu_ring_write(ring, 0);
8620         amdgpu_ring_write(ring, val);
8621 }
8622
8623 static void gfx_v10_0_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,
8624                                         uint32_t val, uint32_t mask)
8625 {
8626         gfx_v10_0_wait_reg_mem(ring, 0, 0, 0, reg, 0, val, mask, 0x20);
8627 }
8628
8629 static void gfx_v10_0_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring,
8630                                                    uint32_t reg0, uint32_t reg1,
8631                                                    uint32_t ref, uint32_t mask)
8632 {
8633         int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
8634         struct amdgpu_device *adev = ring->adev;
8635         bool fw_version_ok = false;
8636
8637         fw_version_ok = adev->gfx.cp_fw_write_wait;
8638
8639         if (fw_version_ok)
8640                 gfx_v10_0_wait_reg_mem(ring, usepfp, 0, 1, reg0, reg1,
8641                                        ref, mask, 0x20);
8642         else
8643                 amdgpu_ring_emit_reg_write_reg_wait_helper(ring, reg0, reg1,
8644                                                            ref, mask);
8645 }
8646
8647 static void gfx_v10_0_ring_soft_recovery(struct amdgpu_ring *ring,
8648                                          unsigned vmid)
8649 {
8650         struct amdgpu_device *adev = ring->adev;
8651         uint32_t value = 0;
8652
8653         value = REG_SET_FIELD(value, SQ_CMD, CMD, 0x03);
8654         value = REG_SET_FIELD(value, SQ_CMD, MODE, 0x01);
8655         value = REG_SET_FIELD(value, SQ_CMD, CHECK_VMID, 1);
8656         value = REG_SET_FIELD(value, SQ_CMD, VM_ID, vmid);
8657         WREG32_SOC15(GC, 0, mmSQ_CMD, value);
8658 }
8659
8660 static void
8661 gfx_v10_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev,
8662                                       uint32_t me, uint32_t pipe,
8663                                       enum amdgpu_interrupt_state state)
8664 {
8665         uint32_t cp_int_cntl, cp_int_cntl_reg;
8666
8667         if (!me) {
8668                 switch (pipe) {
8669                 case 0:
8670                         cp_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_INT_CNTL_RING0);
8671                         break;
8672                 case 1:
8673                         cp_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_INT_CNTL_RING1);
8674                         break;
8675                 default:
8676                         DRM_DEBUG("invalid pipe %d\n", pipe);
8677                         return;
8678                 }
8679         } else {
8680                 DRM_DEBUG("invalid me %d\n", me);
8681                 return;
8682         }
8683
8684         switch (state) {
8685         case AMDGPU_IRQ_STATE_DISABLE:
8686                 cp_int_cntl = RREG32(cp_int_cntl_reg);
8687                 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
8688                                             TIME_STAMP_INT_ENABLE, 0);
8689                 WREG32(cp_int_cntl_reg, cp_int_cntl);
8690                 break;
8691         case AMDGPU_IRQ_STATE_ENABLE:
8692                 cp_int_cntl = RREG32(cp_int_cntl_reg);
8693                 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
8694                                             TIME_STAMP_INT_ENABLE, 1);
8695                 WREG32(cp_int_cntl_reg, cp_int_cntl);
8696                 break;
8697         default:
8698                 break;
8699         }
8700 }
8701
8702 static void gfx_v10_0_set_compute_eop_interrupt_state(struct amdgpu_device *adev,
8703                                                      int me, int pipe,
8704                                                      enum amdgpu_interrupt_state state)
8705 {
8706         u32 mec_int_cntl, mec_int_cntl_reg;
8707
8708         /*
8709          * amdgpu controls only the first MEC. That's why this function only
8710          * handles the setting of interrupts for this specific MEC. All other
8711          * pipes' interrupts are set by amdkfd.
8712          */
8713
8714         if (me == 1) {
8715                 switch (pipe) {
8716                 case 0:
8717                         mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE0_INT_CNTL);
8718                         break;
8719                 case 1:
8720                         mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE1_INT_CNTL);
8721                         break;
8722                 case 2:
8723                         mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE2_INT_CNTL);
8724                         break;
8725                 case 3:
8726                         mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE3_INT_CNTL);
8727                         break;
8728                 default:
8729                         DRM_DEBUG("invalid pipe %d\n", pipe);
8730                         return;
8731                 }
8732         } else {
8733                 DRM_DEBUG("invalid me %d\n", me);
8734                 return;
8735         }
8736
8737         switch (state) {
8738         case AMDGPU_IRQ_STATE_DISABLE:
8739                 mec_int_cntl = RREG32(mec_int_cntl_reg);
8740                 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,
8741                                              TIME_STAMP_INT_ENABLE, 0);
8742                 WREG32(mec_int_cntl_reg, mec_int_cntl);
8743                 break;
8744         case AMDGPU_IRQ_STATE_ENABLE:
8745                 mec_int_cntl = RREG32(mec_int_cntl_reg);
8746                 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,
8747                                              TIME_STAMP_INT_ENABLE, 1);
8748                 WREG32(mec_int_cntl_reg, mec_int_cntl);
8749                 break;
8750         default:
8751                 break;
8752         }
8753 }
8754
8755 static int gfx_v10_0_set_eop_interrupt_state(struct amdgpu_device *adev,
8756                                             struct amdgpu_irq_src *src,
8757                                             unsigned type,
8758                                             enum amdgpu_interrupt_state state)
8759 {
8760         switch (type) {
8761         case AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP:
8762                 gfx_v10_0_set_gfx_eop_interrupt_state(adev, 0, 0, state);
8763                 break;
8764         case AMDGPU_CP_IRQ_GFX_ME0_PIPE1_EOP:
8765                 gfx_v10_0_set_gfx_eop_interrupt_state(adev, 0, 1, state);
8766                 break;
8767         case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP:
8768                 gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 0, state);
8769                 break;
8770         case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP:
8771                 gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 1, state);
8772                 break;
8773         case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP:
8774                 gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 2, state);
8775                 break;
8776         case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP:
8777                 gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 3, state);
8778                 break;
8779         case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP:
8780                 gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 0, state);
8781                 break;
8782         case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP:
8783                 gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 1, state);
8784                 break;
8785         case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP:
8786                 gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 2, state);
8787                 break;
8788         case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP:
8789                 gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 3, state);
8790                 break;
8791         default:
8792                 break;
8793         }
8794         return 0;
8795 }
8796
8797 static int gfx_v10_0_eop_irq(struct amdgpu_device *adev,
8798                              struct amdgpu_irq_src *source,
8799                              struct amdgpu_iv_entry *entry)
8800 {
8801         int i;
8802         u8 me_id, pipe_id, queue_id;
8803         struct amdgpu_ring *ring;
8804
8805         DRM_DEBUG("IH: CP EOP\n");
8806         me_id = (entry->ring_id & 0x0c) >> 2;
8807         pipe_id = (entry->ring_id & 0x03) >> 0;
8808         queue_id = (entry->ring_id & 0x70) >> 4;
8809
8810         switch (me_id) {
8811         case 0:
8812                 if (pipe_id == 0)
8813                         amdgpu_fence_process(&adev->gfx.gfx_ring[0]);
8814                 else
8815                         amdgpu_fence_process(&adev->gfx.gfx_ring[1]);
8816                 break;
8817         case 1:
8818         case 2:
8819                 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
8820                         ring = &adev->gfx.compute_ring[i];
8821                         /* Per-queue interrupt is supported for MEC starting from VI.
8822                           * The interrupt can only be enabled/disabled per pipe instead of per queue.
8823                           */
8824                         if ((ring->me == me_id) && (ring->pipe == pipe_id) && (ring->queue == queue_id))
8825                                 amdgpu_fence_process(ring);
8826                 }
8827                 break;
8828         }
8829         return 0;
8830 }
8831
8832 static int gfx_v10_0_set_priv_reg_fault_state(struct amdgpu_device *adev,
8833                                               struct amdgpu_irq_src *source,
8834                                               unsigned type,
8835                                               enum amdgpu_interrupt_state state)
8836 {
8837         switch (state) {
8838         case AMDGPU_IRQ_STATE_DISABLE:
8839         case AMDGPU_IRQ_STATE_ENABLE:
8840                 WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0,
8841                                PRIV_REG_INT_ENABLE,
8842                                state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
8843                 break;
8844         default:
8845                 break;
8846         }
8847
8848         return 0;
8849 }
8850
8851 static int gfx_v10_0_set_priv_inst_fault_state(struct amdgpu_device *adev,
8852                                                struct amdgpu_irq_src *source,
8853                                                unsigned type,
8854                                                enum amdgpu_interrupt_state state)
8855 {
8856         switch (state) {
8857         case AMDGPU_IRQ_STATE_DISABLE:
8858         case AMDGPU_IRQ_STATE_ENABLE:
8859                 WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0,
8860                                PRIV_INSTR_INT_ENABLE,
8861                                state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
8862                 break;
8863         default:
8864                 break;
8865         }
8866
8867         return 0;
8868 }
8869
8870 static void gfx_v10_0_handle_priv_fault(struct amdgpu_device *adev,
8871                                         struct amdgpu_iv_entry *entry)
8872 {
8873         u8 me_id, pipe_id, queue_id;
8874         struct amdgpu_ring *ring;
8875         int i;
8876
8877         me_id = (entry->ring_id & 0x0c) >> 2;
8878         pipe_id = (entry->ring_id & 0x03) >> 0;
8879         queue_id = (entry->ring_id & 0x70) >> 4;
8880
8881         switch (me_id) {
8882         case 0:
8883                 for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
8884                         ring = &adev->gfx.gfx_ring[i];
8885                         /* we only enabled 1 gfx queue per pipe for now */
8886                         if (ring->me == me_id && ring->pipe == pipe_id)
8887                                 drm_sched_fault(&ring->sched);
8888                 }
8889                 break;
8890         case 1:
8891         case 2:
8892                 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
8893                         ring = &adev->gfx.compute_ring[i];
8894                         if (ring->me == me_id && ring->pipe == pipe_id &&
8895                             ring->queue == queue_id)
8896                                 drm_sched_fault(&ring->sched);
8897                 }
8898                 break;
8899         default:
8900                 BUG();
8901         }
8902 }
8903
8904 static int gfx_v10_0_priv_reg_irq(struct amdgpu_device *adev,
8905                                   struct amdgpu_irq_src *source,
8906                                   struct amdgpu_iv_entry *entry)
8907 {
8908         DRM_ERROR("Illegal register access in command stream\n");
8909         gfx_v10_0_handle_priv_fault(adev, entry);
8910         return 0;
8911 }
8912
8913 static int gfx_v10_0_priv_inst_irq(struct amdgpu_device *adev,
8914                                    struct amdgpu_irq_src *source,
8915                                    struct amdgpu_iv_entry *entry)
8916 {
8917         DRM_ERROR("Illegal instruction in command stream\n");
8918         gfx_v10_0_handle_priv_fault(adev, entry);
8919         return 0;
8920 }
8921
8922 static int gfx_v10_0_kiq_set_interrupt_state(struct amdgpu_device *adev,
8923                                              struct amdgpu_irq_src *src,
8924                                              unsigned int type,
8925                                              enum amdgpu_interrupt_state state)
8926 {
8927         uint32_t tmp, target;
8928         struct amdgpu_ring *ring = &(adev->gfx.kiq.ring);
8929
8930         if (ring->me == 1)
8931                 target = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE0_INT_CNTL);
8932         else
8933                 target = SOC15_REG_OFFSET(GC, 0, mmCP_ME2_PIPE0_INT_CNTL);
8934         target += ring->pipe;
8935
8936         switch (type) {
8937         case AMDGPU_CP_KIQ_IRQ_DRIVER0:
8938                 if (state == AMDGPU_IRQ_STATE_DISABLE) {
8939                         tmp = RREG32_SOC15(GC, 0, mmCPC_INT_CNTL);
8940                         tmp = REG_SET_FIELD(tmp, CPC_INT_CNTL,
8941                                             GENERIC2_INT_ENABLE, 0);
8942                         WREG32_SOC15(GC, 0, mmCPC_INT_CNTL, tmp);
8943
8944                         tmp = RREG32(target);
8945                         tmp = REG_SET_FIELD(tmp, CP_ME2_PIPE0_INT_CNTL,
8946                                             GENERIC2_INT_ENABLE, 0);
8947                         WREG32(target, tmp);
8948                 } else {
8949                         tmp = RREG32_SOC15(GC, 0, mmCPC_INT_CNTL);
8950                         tmp = REG_SET_FIELD(tmp, CPC_INT_CNTL,
8951                                             GENERIC2_INT_ENABLE, 1);
8952                         WREG32_SOC15(GC, 0, mmCPC_INT_CNTL, tmp);
8953
8954                         tmp = RREG32(target);
8955                         tmp = REG_SET_FIELD(tmp, CP_ME2_PIPE0_INT_CNTL,
8956                                             GENERIC2_INT_ENABLE, 1);
8957                         WREG32(target, tmp);
8958                 }
8959                 break;
8960         default:
8961                 BUG(); /* kiq only support GENERIC2_INT now */
8962                 break;
8963         }
8964         return 0;
8965 }
8966
8967 static int gfx_v10_0_kiq_irq(struct amdgpu_device *adev,
8968                              struct amdgpu_irq_src *source,
8969                              struct amdgpu_iv_entry *entry)
8970 {
8971         u8 me_id, pipe_id, queue_id;
8972         struct amdgpu_ring *ring = &(adev->gfx.kiq.ring);
8973
8974         me_id = (entry->ring_id & 0x0c) >> 2;
8975         pipe_id = (entry->ring_id & 0x03) >> 0;
8976         queue_id = (entry->ring_id & 0x70) >> 4;
8977         DRM_DEBUG("IH: CPC GENERIC2_INT, me:%d, pipe:%d, queue:%d\n",
8978                    me_id, pipe_id, queue_id);
8979
8980         amdgpu_fence_process(ring);
8981         return 0;
8982 }
8983
8984 static void gfx_v10_0_emit_mem_sync(struct amdgpu_ring *ring)
8985 {
8986         const unsigned int gcr_cntl =
8987                         PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_INV(1) |
8988                         PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_WB(1) |
8989                         PACKET3_ACQUIRE_MEM_GCR_CNTL_GLM_INV(1) |
8990                         PACKET3_ACQUIRE_MEM_GCR_CNTL_GLM_WB(1) |
8991                         PACKET3_ACQUIRE_MEM_GCR_CNTL_GL1_INV(1) |
8992                         PACKET3_ACQUIRE_MEM_GCR_CNTL_GLV_INV(1) |
8993                         PACKET3_ACQUIRE_MEM_GCR_CNTL_GLK_INV(1) |
8994                         PACKET3_ACQUIRE_MEM_GCR_CNTL_GLI_INV(1);
8995
8996         /* ACQUIRE_MEM - make one or more surfaces valid for use by the subsequent operations */
8997         amdgpu_ring_write(ring, PACKET3(PACKET3_ACQUIRE_MEM, 6));
8998         amdgpu_ring_write(ring, 0); /* CP_COHER_CNTL */
8999         amdgpu_ring_write(ring, 0xffffffff);  /* CP_COHER_SIZE */
9000         amdgpu_ring_write(ring, 0xffffff);  /* CP_COHER_SIZE_HI */
9001         amdgpu_ring_write(ring, 0); /* CP_COHER_BASE */
9002         amdgpu_ring_write(ring, 0);  /* CP_COHER_BASE_HI */
9003         amdgpu_ring_write(ring, 0x0000000A); /* POLL_INTERVAL */
9004         amdgpu_ring_write(ring, gcr_cntl); /* GCR_CNTL */
9005 }
9006
9007 static const struct amd_ip_funcs gfx_v10_0_ip_funcs = {
9008         .name = "gfx_v10_0",
9009         .early_init = gfx_v10_0_early_init,
9010         .late_init = gfx_v10_0_late_init,
9011         .sw_init = gfx_v10_0_sw_init,
9012         .sw_fini = gfx_v10_0_sw_fini,
9013         .hw_init = gfx_v10_0_hw_init,
9014         .hw_fini = gfx_v10_0_hw_fini,
9015         .suspend = gfx_v10_0_suspend,
9016         .resume = gfx_v10_0_resume,
9017         .is_idle = gfx_v10_0_is_idle,
9018         .wait_for_idle = gfx_v10_0_wait_for_idle,
9019         .soft_reset = gfx_v10_0_soft_reset,
9020         .set_clockgating_state = gfx_v10_0_set_clockgating_state,
9021         .set_powergating_state = gfx_v10_0_set_powergating_state,
9022         .get_clockgating_state = gfx_v10_0_get_clockgating_state,
9023 };
9024
9025 static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_gfx = {
9026         .type = AMDGPU_RING_TYPE_GFX,
9027         .align_mask = 0xff,
9028         .nop = PACKET3(PACKET3_NOP, 0x3FFF),
9029         .support_64bit_ptrs = true,
9030         .vmhub = AMDGPU_GFXHUB_0,
9031         .get_rptr = gfx_v10_0_ring_get_rptr_gfx,
9032         .get_wptr = gfx_v10_0_ring_get_wptr_gfx,
9033         .set_wptr = gfx_v10_0_ring_set_wptr_gfx,
9034         .emit_frame_size = /* totally 242 maximum if 16 IBs */
9035                 5 + /* COND_EXEC */
9036                 7 + /* PIPELINE_SYNC */
9037                 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 +
9038                 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 +
9039                 2 + /* VM_FLUSH */
9040                 8 + /* FENCE for VM_FLUSH */
9041                 20 + /* GDS switch */
9042                 4 + /* double SWITCH_BUFFER,
9043                      * the first COND_EXEC jump to the place
9044                      * just prior to this double SWITCH_BUFFER
9045                      */
9046                 5 + /* COND_EXEC */
9047                 7 + /* HDP_flush */
9048                 4 + /* VGT_flush */
9049                 14 + /* CE_META */
9050                 31 + /* DE_META */
9051                 3 + /* CNTX_CTRL */
9052                 5 + /* HDP_INVL */
9053                 8 + 8 + /* FENCE x2 */
9054                 2 + /* SWITCH_BUFFER */
9055                 8, /* gfx_v10_0_emit_mem_sync */
9056         .emit_ib_size = 4, /* gfx_v10_0_ring_emit_ib_gfx */
9057         .emit_ib = gfx_v10_0_ring_emit_ib_gfx,
9058         .emit_fence = gfx_v10_0_ring_emit_fence,
9059         .emit_pipeline_sync = gfx_v10_0_ring_emit_pipeline_sync,
9060         .emit_vm_flush = gfx_v10_0_ring_emit_vm_flush,
9061         .emit_gds_switch = gfx_v10_0_ring_emit_gds_switch,
9062         .emit_hdp_flush = gfx_v10_0_ring_emit_hdp_flush,
9063         .test_ring = gfx_v10_0_ring_test_ring,
9064         .test_ib = gfx_v10_0_ring_test_ib,
9065         .insert_nop = amdgpu_ring_insert_nop,
9066         .pad_ib = amdgpu_ring_generic_pad_ib,
9067         .emit_switch_buffer = gfx_v10_0_ring_emit_sb,
9068         .emit_cntxcntl = gfx_v10_0_ring_emit_cntxcntl,
9069         .init_cond_exec = gfx_v10_0_ring_emit_init_cond_exec,
9070         .patch_cond_exec = gfx_v10_0_ring_emit_patch_cond_exec,
9071         .preempt_ib = gfx_v10_0_ring_preempt_ib,
9072         .emit_frame_cntl = gfx_v10_0_ring_emit_frame_cntl,
9073         .emit_wreg = gfx_v10_0_ring_emit_wreg,
9074         .emit_reg_wait = gfx_v10_0_ring_emit_reg_wait,
9075         .emit_reg_write_reg_wait = gfx_v10_0_ring_emit_reg_write_reg_wait,
9076         .soft_recovery = gfx_v10_0_ring_soft_recovery,
9077         .emit_mem_sync = gfx_v10_0_emit_mem_sync,
9078 };
9079
9080 static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_compute = {
9081         .type = AMDGPU_RING_TYPE_COMPUTE,
9082         .align_mask = 0xff,
9083         .nop = PACKET3(PACKET3_NOP, 0x3FFF),
9084         .support_64bit_ptrs = true,
9085         .vmhub = AMDGPU_GFXHUB_0,
9086         .get_rptr = gfx_v10_0_ring_get_rptr_compute,
9087         .get_wptr = gfx_v10_0_ring_get_wptr_compute,
9088         .set_wptr = gfx_v10_0_ring_set_wptr_compute,
9089         .emit_frame_size =
9090                 20 + /* gfx_v10_0_ring_emit_gds_switch */
9091                 7 + /* gfx_v10_0_ring_emit_hdp_flush */
9092                 5 + /* hdp invalidate */
9093                 7 + /* gfx_v10_0_ring_emit_pipeline_sync */
9094                 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 +
9095                 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 +
9096                 2 + /* gfx_v10_0_ring_emit_vm_flush */
9097                 8 + 8 + 8 + /* gfx_v10_0_ring_emit_fence x3 for user fence, vm fence */
9098                 8, /* gfx_v10_0_emit_mem_sync */
9099         .emit_ib_size = 7, /* gfx_v10_0_ring_emit_ib_compute */
9100         .emit_ib = gfx_v10_0_ring_emit_ib_compute,
9101         .emit_fence = gfx_v10_0_ring_emit_fence,
9102         .emit_pipeline_sync = gfx_v10_0_ring_emit_pipeline_sync,
9103         .emit_vm_flush = gfx_v10_0_ring_emit_vm_flush,
9104         .emit_gds_switch = gfx_v10_0_ring_emit_gds_switch,
9105         .emit_hdp_flush = gfx_v10_0_ring_emit_hdp_flush,
9106         .test_ring = gfx_v10_0_ring_test_ring,
9107         .test_ib = gfx_v10_0_ring_test_ib,
9108         .insert_nop = amdgpu_ring_insert_nop,
9109         .pad_ib = amdgpu_ring_generic_pad_ib,
9110         .emit_wreg = gfx_v10_0_ring_emit_wreg,
9111         .emit_reg_wait = gfx_v10_0_ring_emit_reg_wait,
9112         .emit_reg_write_reg_wait = gfx_v10_0_ring_emit_reg_write_reg_wait,
9113         .emit_mem_sync = gfx_v10_0_emit_mem_sync,
9114 };
9115
9116 static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_kiq = {
9117         .type = AMDGPU_RING_TYPE_KIQ,
9118         .align_mask = 0xff,
9119         .nop = PACKET3(PACKET3_NOP, 0x3FFF),
9120         .support_64bit_ptrs = true,
9121         .vmhub = AMDGPU_GFXHUB_0,
9122         .get_rptr = gfx_v10_0_ring_get_rptr_compute,
9123         .get_wptr = gfx_v10_0_ring_get_wptr_compute,
9124         .set_wptr = gfx_v10_0_ring_set_wptr_compute,
9125         .emit_frame_size =
9126                 20 + /* gfx_v10_0_ring_emit_gds_switch */
9127                 7 + /* gfx_v10_0_ring_emit_hdp_flush */
9128                 5 + /*hdp invalidate */
9129                 7 + /* gfx_v10_0_ring_emit_pipeline_sync */
9130                 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 +
9131                 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 +
9132                 2 + /* gfx_v10_0_ring_emit_vm_flush */
9133                 8 + 8 + 8, /* gfx_v10_0_ring_emit_fence_kiq x3 for user fence, vm fence */
9134         .emit_ib_size = 7, /* gfx_v10_0_ring_emit_ib_compute */
9135         .emit_ib = gfx_v10_0_ring_emit_ib_compute,
9136         .emit_fence = gfx_v10_0_ring_emit_fence_kiq,
9137         .test_ring = gfx_v10_0_ring_test_ring,
9138         .test_ib = gfx_v10_0_ring_test_ib,
9139         .insert_nop = amdgpu_ring_insert_nop,
9140         .pad_ib = amdgpu_ring_generic_pad_ib,
9141         .emit_rreg = gfx_v10_0_ring_emit_rreg,
9142         .emit_wreg = gfx_v10_0_ring_emit_wreg,
9143         .emit_reg_wait = gfx_v10_0_ring_emit_reg_wait,
9144         .emit_reg_write_reg_wait = gfx_v10_0_ring_emit_reg_write_reg_wait,
9145 };
9146
9147 static void gfx_v10_0_set_ring_funcs(struct amdgpu_device *adev)
9148 {
9149         int i;
9150
9151         adev->gfx.kiq.ring.funcs = &gfx_v10_0_ring_funcs_kiq;
9152
9153         for (i = 0; i < adev->gfx.num_gfx_rings; i++)
9154                 adev->gfx.gfx_ring[i].funcs = &gfx_v10_0_ring_funcs_gfx;
9155
9156         for (i = 0; i < adev->gfx.num_compute_rings; i++)
9157                 adev->gfx.compute_ring[i].funcs = &gfx_v10_0_ring_funcs_compute;
9158 }
9159
9160 static const struct amdgpu_irq_src_funcs gfx_v10_0_eop_irq_funcs = {
9161         .set = gfx_v10_0_set_eop_interrupt_state,
9162         .process = gfx_v10_0_eop_irq,
9163 };
9164
9165 static const struct amdgpu_irq_src_funcs gfx_v10_0_priv_reg_irq_funcs = {
9166         .set = gfx_v10_0_set_priv_reg_fault_state,
9167         .process = gfx_v10_0_priv_reg_irq,
9168 };
9169
9170 static const struct amdgpu_irq_src_funcs gfx_v10_0_priv_inst_irq_funcs = {
9171         .set = gfx_v10_0_set_priv_inst_fault_state,
9172         .process = gfx_v10_0_priv_inst_irq,
9173 };
9174
9175 static const struct amdgpu_irq_src_funcs gfx_v10_0_kiq_irq_funcs = {
9176         .set = gfx_v10_0_kiq_set_interrupt_state,
9177         .process = gfx_v10_0_kiq_irq,
9178 };
9179
9180 static void gfx_v10_0_set_irq_funcs(struct amdgpu_device *adev)
9181 {
9182         adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST;
9183         adev->gfx.eop_irq.funcs = &gfx_v10_0_eop_irq_funcs;
9184
9185         adev->gfx.kiq.irq.num_types = AMDGPU_CP_KIQ_IRQ_LAST;
9186         adev->gfx.kiq.irq.funcs = &gfx_v10_0_kiq_irq_funcs;
9187
9188         adev->gfx.priv_reg_irq.num_types = 1;
9189         adev->gfx.priv_reg_irq.funcs = &gfx_v10_0_priv_reg_irq_funcs;
9190
9191         adev->gfx.priv_inst_irq.num_types = 1;
9192         adev->gfx.priv_inst_irq.funcs = &gfx_v10_0_priv_inst_irq_funcs;
9193 }
9194
9195 static void gfx_v10_0_set_rlc_funcs(struct amdgpu_device *adev)
9196 {
9197         switch (adev->asic_type) {
9198         case CHIP_NAVI10:
9199         case CHIP_NAVI14:
9200         case CHIP_SIENNA_CICHLID:
9201         case CHIP_NAVY_FLOUNDER:
9202         case CHIP_VANGOGH:
9203         case CHIP_DIMGREY_CAVEFISH:
9204         case CHIP_BEIGE_GOBY:
9205                 adev->gfx.rlc.funcs = &gfx_v10_0_rlc_funcs;
9206                 break;
9207         case CHIP_NAVI12:
9208                 adev->gfx.rlc.funcs = &gfx_v10_0_rlc_funcs_sriov;
9209                 break;
9210         default:
9211                 break;
9212         }
9213 }
9214
9215 static void gfx_v10_0_set_gds_init(struct amdgpu_device *adev)
9216 {
9217         unsigned total_cu = adev->gfx.config.max_cu_per_sh *
9218                             adev->gfx.config.max_sh_per_se *
9219                             adev->gfx.config.max_shader_engines;
9220
9221         adev->gds.gds_size = 0x10000;
9222         adev->gds.gds_compute_max_wave_id = total_cu * 32 - 1;
9223         adev->gds.gws_size = 64;
9224         adev->gds.oa_size = 16;
9225 }
9226
9227 static void gfx_v10_0_set_user_wgp_inactive_bitmap_per_sh(struct amdgpu_device *adev,
9228                                                           u32 bitmap)
9229 {
9230         u32 data;
9231
9232         if (!bitmap)
9233                 return;
9234
9235         data = bitmap << GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT;
9236         data &= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK;
9237
9238         WREG32_SOC15(GC, 0, mmGC_USER_SHADER_ARRAY_CONFIG, data);
9239 }
9240
9241 static u32 gfx_v10_0_get_wgp_active_bitmap_per_sh(struct amdgpu_device *adev)
9242 {
9243         u32 data, wgp_bitmask;
9244         data = RREG32_SOC15(GC, 0, mmCC_GC_SHADER_ARRAY_CONFIG);
9245         data |= RREG32_SOC15(GC, 0, mmGC_USER_SHADER_ARRAY_CONFIG);
9246
9247         data &= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK;
9248         data >>= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT;
9249
9250         wgp_bitmask =
9251                 amdgpu_gfx_create_bitmask(adev->gfx.config.max_cu_per_sh >> 1);
9252
9253         return (~data) & wgp_bitmask;
9254 }
9255
9256 static u32 gfx_v10_0_get_cu_active_bitmap_per_sh(struct amdgpu_device *adev)
9257 {
9258         u32 wgp_idx, wgp_active_bitmap;
9259         u32 cu_bitmap_per_wgp, cu_active_bitmap;
9260
9261         wgp_active_bitmap = gfx_v10_0_get_wgp_active_bitmap_per_sh(adev);
9262         cu_active_bitmap = 0;
9263
9264         for (wgp_idx = 0; wgp_idx < 16; wgp_idx++) {
9265                 /* if there is one WGP enabled, it means 2 CUs will be enabled */
9266                 cu_bitmap_per_wgp = 3 << (2 * wgp_idx);
9267                 if (wgp_active_bitmap & (1 << wgp_idx))
9268                         cu_active_bitmap |= cu_bitmap_per_wgp;
9269         }
9270
9271         return cu_active_bitmap;
9272 }
9273
9274 static int gfx_v10_0_get_cu_info(struct amdgpu_device *adev,
9275                                  struct amdgpu_cu_info *cu_info)
9276 {
9277         int i, j, k, counter, active_cu_number = 0;
9278         u32 mask, bitmap, ao_bitmap, ao_cu_mask = 0;
9279         unsigned disable_masks[4 * 2];
9280
9281         if (!adev || !cu_info)
9282                 return -EINVAL;
9283
9284         amdgpu_gfx_parse_disable_cu(disable_masks, 4, 2);
9285
9286         mutex_lock(&adev->grbm_idx_mutex);
9287         for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
9288                 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
9289                         bitmap = i * adev->gfx.config.max_sh_per_se + j;
9290                         if ((adev->asic_type == CHIP_SIENNA_CICHLID) &&
9291                             ((gfx_v10_3_get_disabled_sa(adev) >> bitmap) & 1))
9292                                 continue;
9293                         mask = 1;
9294                         ao_bitmap = 0;
9295                         counter = 0;
9296                         gfx_v10_0_select_se_sh(adev, i, j, 0xffffffff);
9297                         if (i < 4 && j < 2)
9298                                 gfx_v10_0_set_user_wgp_inactive_bitmap_per_sh(
9299                                         adev, disable_masks[i * 2 + j]);
9300                         bitmap = gfx_v10_0_get_cu_active_bitmap_per_sh(adev);
9301                         cu_info->bitmap[i][j] = bitmap;
9302
9303                         for (k = 0; k < adev->gfx.config.max_cu_per_sh; k++) {
9304                                 if (bitmap & mask) {
9305                                         if (counter < adev->gfx.config.max_cu_per_sh)
9306                                                 ao_bitmap |= mask;
9307                                         counter++;
9308                                 }
9309                                 mask <<= 1;
9310                         }
9311                         active_cu_number += counter;
9312                         if (i < 2 && j < 2)
9313                                 ao_cu_mask |= (ao_bitmap << (i * 16 + j * 8));
9314                         cu_info->ao_cu_bitmap[i][j] = ao_bitmap;
9315                 }
9316         }
9317         gfx_v10_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
9318         mutex_unlock(&adev->grbm_idx_mutex);
9319
9320         cu_info->number = active_cu_number;
9321         cu_info->ao_cu_mask = ao_cu_mask;
9322         cu_info->simd_per_cu = NUM_SIMD_PER_CU;
9323
9324         return 0;
9325 }
9326
9327 static u32 gfx_v10_3_get_disabled_sa(struct amdgpu_device *adev)
9328 {
9329         uint32_t efuse_setting, vbios_setting, disabled_sa, max_sa_mask;
9330
9331         efuse_setting = RREG32_SOC15(GC, 0, mmCC_GC_SA_UNIT_DISABLE);
9332         efuse_setting &= CC_GC_SA_UNIT_DISABLE__SA_DISABLE_MASK;
9333         efuse_setting >>= CC_GC_SA_UNIT_DISABLE__SA_DISABLE__SHIFT;
9334
9335         vbios_setting = RREG32_SOC15(GC, 0, mmGC_USER_SA_UNIT_DISABLE);
9336         vbios_setting &= GC_USER_SA_UNIT_DISABLE__SA_DISABLE_MASK;
9337         vbios_setting >>= GC_USER_SA_UNIT_DISABLE__SA_DISABLE__SHIFT;
9338
9339         max_sa_mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_sh_per_se *
9340                                                 adev->gfx.config.max_shader_engines);
9341         disabled_sa = efuse_setting | vbios_setting;
9342         disabled_sa &= max_sa_mask;
9343
9344         return disabled_sa;
9345 }
9346
9347 static void gfx_v10_3_program_pbb_mode(struct amdgpu_device *adev)
9348 {
9349         uint32_t max_sa_per_se, max_sa_per_se_mask, max_shader_engines;
9350         uint32_t disabled_sa_mask, se_index, disabled_sa_per_se;
9351
9352         disabled_sa_mask = gfx_v10_3_get_disabled_sa(adev);
9353
9354         max_sa_per_se = adev->gfx.config.max_sh_per_se;
9355         max_sa_per_se_mask = (1 << max_sa_per_se) - 1;
9356         max_shader_engines = adev->gfx.config.max_shader_engines;
9357
9358         for (se_index = 0; max_shader_engines > se_index; se_index++) {
9359                 disabled_sa_per_se = disabled_sa_mask >> (se_index * max_sa_per_se);
9360                 disabled_sa_per_se &= max_sa_per_se_mask;
9361                 if (disabled_sa_per_se == max_sa_per_se_mask) {
9362                         WREG32_FIELD15(GC, 0, PA_SC_ENHANCE_3, FORCE_PBB_WORKLOAD_MODE_TO_ZERO, 1);
9363                         break;
9364                 }
9365         }
9366 }
9367
9368 static void gfx_v10_3_set_power_brake_sequence(struct amdgpu_device *adev)
9369 {
9370         WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX,
9371                      (0x1 << GRBM_GFX_INDEX__SA_BROADCAST_WRITES__SHIFT) |
9372                      (0x1 << GRBM_GFX_INDEX__INSTANCE_BROADCAST_WRITES__SHIFT) |
9373                      (0x1 << GRBM_GFX_INDEX__SE_BROADCAST_WRITES__SHIFT));
9374
9375         WREG32_SOC15(GC, 0, mmGC_CAC_IND_INDEX, ixPWRBRK_STALL_PATTERN_CTRL);
9376         WREG32_SOC15(GC, 0, mmGC_CAC_IND_DATA,
9377                      (0x1 << PWRBRK_STALL_PATTERN_CTRL__PWRBRK_STEP_INTERVAL__SHIFT) |
9378                      (0x12 << PWRBRK_STALL_PATTERN_CTRL__PWRBRK_BEGIN_STEP__SHIFT) |
9379                      (0x13 << PWRBRK_STALL_PATTERN_CTRL__PWRBRK_END_STEP__SHIFT) |
9380                      (0xf << PWRBRK_STALL_PATTERN_CTRL__PWRBRK_THROTTLE_PATTERN_BIT_NUMS__SHIFT));
9381
9382         WREG32_SOC15(GC, 0, mmGC_THROTTLE_CTRL_Sienna_Cichlid,
9383                      (0x1 << GC_THROTTLE_CTRL__PWRBRK_STALL_EN__SHIFT) |
9384                      (0x1 << GC_THROTTLE_CTRL__PATTERN_MODE__SHIFT) |
9385                      (0x5 << GC_THROTTLE_CTRL__RELEASE_STEP_INTERVAL__SHIFT));
9386
9387         WREG32_SOC15(GC, 0, mmDIDT_IND_INDEX, ixDIDT_SQ_THROTTLE_CTRL);
9388
9389         WREG32_SOC15(GC, 0, mmDIDT_IND_DATA,
9390                      (0x1 << DIDT_SQ_THROTTLE_CTRL__PWRBRK_STALL_EN__SHIFT));
9391 }
9392
9393 const struct amdgpu_ip_block_version gfx_v10_0_ip_block =
9394 {
9395         .type = AMD_IP_BLOCK_TYPE_GFX,
9396         .major = 10,
9397         .minor = 0,
9398         .rev = 0,
9399         .funcs = &gfx_v10_0_ip_funcs,
9400 };