drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

   1 /*
   2  * Copyright 2019 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #include <linux/delay.h>
  25 #include <linux/kernel.h>
  26 #include <linux/firmware.h>
  27 #include <linux/module.h>
  28 #include <linux/pci.h>
  29 #include "amdgpu.h"
  30 #include "amdgpu_gfx.h"
  31 #include "amdgpu_psp.h"
  32 #include "nv.h"
  33 #include "nvd.h"
  34
  35 #include "gc/gc_10_1_0_offset.h"
  36 #include "gc/gc_10_1_0_sh_mask.h"
  37 #include "smuio/smuio_11_0_0_offset.h"
  38 #include "smuio/smuio_11_0_0_sh_mask.h"
  39 #include "navi10_enum.h"
  40 #include "ivsrcid/gfx/irqsrcs_gfx_10_1.h"
  41
  42 #include "soc15.h"
  43 #include "soc15d.h"
  44 #include "soc15_common.h"
  45 #include "clearstate_gfx10.h"
  46 #include "v10_structs.h"
  47 #include "gfx_v10_0.h"
  48 #include "nbio_v2_3.h"
  49
  50 /*
  51  * Navi10 has two graphic rings to share each graphic pipe.
  52  * 1. Primary ring
  53  * 2. Async ring
  54  */
  55 #define GFX10_NUM_GFX_RINGS_NV1X        1
  56 #define GFX10_NUM_GFX_RINGS_Sienna_Cichlid      1
  57 #define GFX10_MEC_HPD_SIZE      2048
  58
  59 #define F32_CE_PROGRAM_RAM_SIZE         65536
  60 #define RLCG_UCODE_LOADING_START_ADDRESS        0x00002000L
  61
  62 #define mmCGTT_GS_NGG_CLK_CTRL  0x5087
  63 #define mmCGTT_GS_NGG_CLK_CTRL_BASE_IDX 1
  64 #define mmCGTT_SPI_RA0_CLK_CTRL 0x507a
  65 #define mmCGTT_SPI_RA0_CLK_CTRL_BASE_IDX 1
  66 #define mmCGTT_SPI_RA1_CLK_CTRL 0x507b
  67 #define mmCGTT_SPI_RA1_CLK_CTRL_BASE_IDX 1
  68
  69 #define GB_ADDR_CONFIG__NUM_PKRS__SHIFT                                                                       0x8
  70 #define GB_ADDR_CONFIG__NUM_PKRS_MASK                                                                         0x00000700L
  71
  72 #define mmCGTS_TCC_DISABLE_gc_10_3                 0x5006
  73 #define mmCGTS_TCC_DISABLE_gc_10_3_BASE_IDX        1
  74 #define mmCGTS_USER_TCC_DISABLE_gc_10_3            0x5007
  75 #define mmCGTS_USER_TCC_DISABLE_gc_10_3_BASE_IDX   1
  76
  77 #define mmCP_MEC_CNTL_Sienna_Cichlid                      0x0f55
  78 #define mmCP_MEC_CNTL_Sienna_Cichlid_BASE_IDX             0
  79 #define mmRLC_SAFE_MODE_Sienna_Cichlid                  0x4ca0
  80 #define mmRLC_SAFE_MODE_Sienna_Cichlid_BASE_IDX         1
  81 #define mmRLC_CP_SCHEDULERS_Sienna_Cichlid              0x4ca1
  82 #define mmRLC_CP_SCHEDULERS_Sienna_Cichlid_BASE_IDX     1
  83 #define mmSPI_CONFIG_CNTL_Sienna_Cichlid                        0x11ec
  84 #define mmSPI_CONFIG_CNTL_Sienna_Cichlid_BASE_IDX               0
  85 #define mmVGT_ESGS_RING_SIZE_Sienna_Cichlid             0x0fc1
  86 #define mmVGT_ESGS_RING_SIZE_Sienna_Cichlid_BASE_IDX    0
  87 #define mmVGT_GSVS_RING_SIZE_Sienna_Cichlid             0x0fc2
  88 #define mmVGT_GSVS_RING_SIZE_Sienna_Cichlid_BASE_IDX    0
  89 #define mmVGT_TF_RING_SIZE_Sienna_Cichlid                       0x0fc3
  90 #define mmVGT_TF_RING_SIZE_Sienna_Cichlid_BASE_IDX      0
  91 #define mmVGT_HS_OFFCHIP_PARAM_Sienna_Cichlid           0x0fc4
  92 #define mmVGT_HS_OFFCHIP_PARAM_Sienna_Cichlid_BASE_IDX  0
  93 #define mmVGT_TF_MEMORY_BASE_Sienna_Cichlid             0x0fc5
  94 #define mmVGT_TF_MEMORY_BASE_Sienna_Cichlid_BASE_IDX    0
  95 #define mmVGT_TF_MEMORY_BASE_HI_Sienna_Cichlid          0x0fc6
  96 #define mmVGT_TF_MEMORY_BASE_HI_Sienna_Cichlid_BASE_IDX 0
  97 #define GRBM_STATUS2__RLC_BUSY_Sienna_Cichlid__SHIFT    0x1a
  98 #define GRBM_STATUS2__RLC_BUSY_Sienna_Cichlid_MASK      0x04000000L
  99 #define CP_RB_DOORBELL_RANGE_LOWER__DOORBELL_RANGE_LOWER_Sienna_Cichlid_MASK    0x00000FFCL
 100 #define CP_RB_DOORBELL_RANGE_LOWER__DOORBELL_RANGE_LOWER_Sienna_Cichlid__SHIFT  0x2
 101 #define CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_Sienna_Cichlid_MASK    0x00000FFCL
 102 #define mmGCR_GENERAL_CNTL_Sienna_Cichlid                       0x1580
 103 #define mmGCR_GENERAL_CNTL_Sienna_Cichlid_BASE_IDX      0
 104
 105 #define mmGOLDEN_TSC_COUNT_UPPER_Vangogh                0x0025
 106 #define mmGOLDEN_TSC_COUNT_UPPER_Vangogh_BASE_IDX       1
 107 #define mmGOLDEN_TSC_COUNT_LOWER_Vangogh                0x0026
 108 #define mmGOLDEN_TSC_COUNT_LOWER_Vangogh_BASE_IDX       1
 109 #define mmSPI_CONFIG_CNTL_1_Vangogh              0x2441
 110 #define mmSPI_CONFIG_CNTL_1_Vangogh_BASE_IDX     1
 111 #define mmVGT_TF_MEMORY_BASE_HI_Vangogh          0x2261
 112 #define mmVGT_TF_MEMORY_BASE_HI_Vangogh_BASE_IDX 1
 113 #define mmVGT_HS_OFFCHIP_PARAM_Vangogh           0x224f
 114 #define mmVGT_HS_OFFCHIP_PARAM_Vangogh_BASE_IDX  1
 115 #define mmVGT_TF_RING_SIZE_Vangogh               0x224e
 116 #define mmVGT_TF_RING_SIZE_Vangogh_BASE_IDX      1
 117 #define mmVGT_GSVS_RING_SIZE_Vangogh             0x2241
 118 #define mmVGT_GSVS_RING_SIZE_Vangogh_BASE_IDX    1
 119 #define mmVGT_TF_MEMORY_BASE_Vangogh             0x2250
 120 #define mmVGT_TF_MEMORY_BASE_Vangogh_BASE_IDX    1
 121 #define mmVGT_ESGS_RING_SIZE_Vangogh             0x2240
 122 #define mmVGT_ESGS_RING_SIZE_Vangogh_BASE_IDX    1
 123 #define mmSPI_CONFIG_CNTL_Vangogh                0x2440
 124 #define mmSPI_CONFIG_CNTL_Vangogh_BASE_IDX       1
 125 #define mmGCR_GENERAL_CNTL_Vangogh               0x1580
 126 #define mmGCR_GENERAL_CNTL_Vangogh_BASE_IDX      0
 127 #define RLC_PG_DELAY_3__CGCG_ACTIVE_BEFORE_CGPG_MASK_Vangogh   0x0000FFFFL
 128
 129 #define mmCP_HYP_PFP_UCODE_ADDR                 0x5814
 130 #define mmCP_HYP_PFP_UCODE_ADDR_BASE_IDX        1
 131 #define mmCP_HYP_PFP_UCODE_DATA                 0x5815
 132 #define mmCP_HYP_PFP_UCODE_DATA_BASE_IDX        1
 133 #define mmCP_HYP_CE_UCODE_ADDR                  0x5818
 134 #define mmCP_HYP_CE_UCODE_ADDR_BASE_IDX         1
 135 #define mmCP_HYP_CE_UCODE_DATA                  0x5819
 136 #define mmCP_HYP_CE_UCODE_DATA_BASE_IDX         1
 137 #define mmCP_HYP_ME_UCODE_ADDR                  0x5816
 138 #define mmCP_HYP_ME_UCODE_ADDR_BASE_IDX         1
 139 #define mmCP_HYP_ME_UCODE_DATA                  0x5817
 140 #define mmCP_HYP_ME_UCODE_DATA_BASE_IDX         1
 141
 142 #define mmCPG_PSP_DEBUG                         0x5c10
 143 #define mmCPG_PSP_DEBUG_BASE_IDX                1
 144 #define mmCPC_PSP_DEBUG                         0x5c11
 145 #define mmCPC_PSP_DEBUG_BASE_IDX                1
 146 #define CPC_PSP_DEBUG__GPA_OVERRIDE_MASK        0x00000008L
 147 #define CPG_PSP_DEBUG__GPA_OVERRIDE_MASK        0x00000008L
 148
 149 //CC_GC_SA_UNIT_DISABLE
 150 #define mmCC_GC_SA_UNIT_DISABLE                 0x0fe9
 151 #define mmCC_GC_SA_UNIT_DISABLE_BASE_IDX        0
 152 #define CC_GC_SA_UNIT_DISABLE__SA_DISABLE__SHIFT        0x8
 153 #define CC_GC_SA_UNIT_DISABLE__SA_DISABLE_MASK          0x0000FF00L
 154 //GC_USER_SA_UNIT_DISABLE
 155 #define mmGC_USER_SA_UNIT_DISABLE               0x0fea
 156 #define mmGC_USER_SA_UNIT_DISABLE_BASE_IDX      0
 157 #define GC_USER_SA_UNIT_DISABLE__SA_DISABLE__SHIFT      0x8
 158 #define GC_USER_SA_UNIT_DISABLE__SA_DISABLE_MASK        0x0000FF00L
 159 //PA_SC_ENHANCE_3
 160 #define mmPA_SC_ENHANCE_3                       0x1085
 161 #define mmPA_SC_ENHANCE_3_BASE_IDX              0
 162 #define PA_SC_ENHANCE_3__FORCE_PBB_WORKLOAD_MODE_TO_ZERO__SHIFT 0x3
 163 #define PA_SC_ENHANCE_3__FORCE_PBB_WORKLOAD_MODE_TO_ZERO_MASK   0x00000008L
 164
 165 #define mmCGTT_SPI_CS_CLK_CTRL                  0x507c
 166 #define mmCGTT_SPI_CS_CLK_CTRL_BASE_IDX         1
 167
 168 #define mmGCUTCL2_CGTT_CLK_CTRL_Sienna_Cichlid          0x16f3
 169 #define mmGCUTCL2_CGTT_CLK_CTRL_Sienna_Cichlid_BASE_IDX 0
 170 #define mmGCVM_L2_CGTT_CLK_CTRL_Sienna_Cichlid          0x15db
 171 #define mmGCVM_L2_CGTT_CLK_CTRL_Sienna_Cichlid_BASE_IDX 0
 172
 173 #define mmGC_THROTTLE_CTRL_Sienna_Cichlid              0x2030
 174 #define mmGC_THROTTLE_CTRL_Sienna_Cichlid_BASE_IDX     0
 175
 176 #define mmRLC_SPARE_INT_0_Sienna_Cichlid               0x4ca5
 177 #define mmRLC_SPARE_INT_0_Sienna_Cichlid_BASE_IDX      1
 178
 179 MODULE_FIRMWARE("amdgpu/navi10_ce.bin");
 180 MODULE_FIRMWARE("amdgpu/navi10_pfp.bin");
 181 MODULE_FIRMWARE("amdgpu/navi10_me.bin");
 182 MODULE_FIRMWARE("amdgpu/navi10_mec.bin");
 183 MODULE_FIRMWARE("amdgpu/navi10_mec2.bin");
 184 MODULE_FIRMWARE("amdgpu/navi10_rlc.bin");
 185
 186 MODULE_FIRMWARE("amdgpu/navi14_ce_wks.bin");
 187 MODULE_FIRMWARE("amdgpu/navi14_pfp_wks.bin");
 188 MODULE_FIRMWARE("amdgpu/navi14_me_wks.bin");
 189 MODULE_FIRMWARE("amdgpu/navi14_mec_wks.bin");
 190 MODULE_FIRMWARE("amdgpu/navi14_mec2_wks.bin");
 191 MODULE_FIRMWARE("amdgpu/navi14_ce.bin");
 192 MODULE_FIRMWARE("amdgpu/navi14_pfp.bin");
 193 MODULE_FIRMWARE("amdgpu/navi14_me.bin");
 194 MODULE_FIRMWARE("amdgpu/navi14_mec.bin");
 195 MODULE_FIRMWARE("amdgpu/navi14_mec2.bin");
 196 MODULE_FIRMWARE("amdgpu/navi14_rlc.bin");
 197
 198 MODULE_FIRMWARE("amdgpu/navi12_ce.bin");
 199 MODULE_FIRMWARE("amdgpu/navi12_pfp.bin");
 200 MODULE_FIRMWARE("amdgpu/navi12_me.bin");
 201 MODULE_FIRMWARE("amdgpu/navi12_mec.bin");
 202 MODULE_FIRMWARE("amdgpu/navi12_mec2.bin");
 203 MODULE_FIRMWARE("amdgpu/navi12_rlc.bin");
 204
 205 MODULE_FIRMWARE("amdgpu/sienna_cichlid_ce.bin");
 206 MODULE_FIRMWARE("amdgpu/sienna_cichlid_pfp.bin");
 207 MODULE_FIRMWARE("amdgpu/sienna_cichlid_me.bin");
 208 MODULE_FIRMWARE("amdgpu/sienna_cichlid_mec.bin");
 209 MODULE_FIRMWARE("amdgpu/sienna_cichlid_mec2.bin");
 210 MODULE_FIRMWARE("amdgpu/sienna_cichlid_rlc.bin");
 211
 212 MODULE_FIRMWARE("amdgpu/navy_flounder_ce.bin");
 213 MODULE_FIRMWARE("amdgpu/navy_flounder_pfp.bin");
 214 MODULE_FIRMWARE("amdgpu/navy_flounder_me.bin");
 215 MODULE_FIRMWARE("amdgpu/navy_flounder_mec.bin");
 216 MODULE_FIRMWARE("amdgpu/navy_flounder_mec2.bin");
 217 MODULE_FIRMWARE("amdgpu/navy_flounder_rlc.bin");
 218
 219 MODULE_FIRMWARE("amdgpu/vangogh_ce.bin");
 220 MODULE_FIRMWARE("amdgpu/vangogh_pfp.bin");
 221 MODULE_FIRMWARE("amdgpu/vangogh_me.bin");
 222 MODULE_FIRMWARE("amdgpu/vangogh_mec.bin");
 223 MODULE_FIRMWARE("amdgpu/vangogh_mec2.bin");
 224 MODULE_FIRMWARE("amdgpu/vangogh_rlc.bin");
 225
 226 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_ce.bin");
 227 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_pfp.bin");
 228 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_me.bin");
 229 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_mec.bin");
 230 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_mec2.bin");
 231 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_rlc.bin");
 232
 233 MODULE_FIRMWARE("amdgpu/beige_goby_ce.bin");
 234 MODULE_FIRMWARE("amdgpu/beige_goby_pfp.bin");
 235 MODULE_FIRMWARE("amdgpu/beige_goby_me.bin");
 236 MODULE_FIRMWARE("amdgpu/beige_goby_mec.bin");
 237 MODULE_FIRMWARE("amdgpu/beige_goby_mec2.bin");
 238 MODULE_FIRMWARE("amdgpu/beige_goby_rlc.bin");
 239
 240 MODULE_FIRMWARE("amdgpu/yellow_carp_ce.bin");
 241 MODULE_FIRMWARE("amdgpu/yellow_carp_pfp.bin");
 242 MODULE_FIRMWARE("amdgpu/yellow_carp_me.bin");
 243 MODULE_FIRMWARE("amdgpu/yellow_carp_mec.bin");
 244 MODULE_FIRMWARE("amdgpu/yellow_carp_mec2.bin");
 245 MODULE_FIRMWARE("amdgpu/yellow_carp_rlc.bin");
 246
 247 MODULE_FIRMWARE("amdgpu/cyan_skillfish_ce.bin");
 248 MODULE_FIRMWARE("amdgpu/cyan_skillfish_pfp.bin");
 249 MODULE_FIRMWARE("amdgpu/cyan_skillfish_me.bin");
 250 MODULE_FIRMWARE("amdgpu/cyan_skillfish_mec.bin");
 251 MODULE_FIRMWARE("amdgpu/cyan_skillfish_mec2.bin");
 252 MODULE_FIRMWARE("amdgpu/cyan_skillfish_rlc.bin");
 253
 254 MODULE_FIRMWARE("amdgpu/cyan_skillfish2_ce.bin");
 255 MODULE_FIRMWARE("amdgpu/cyan_skillfish2_pfp.bin");
 256 MODULE_FIRMWARE("amdgpu/cyan_skillfish2_me.bin");
 257 MODULE_FIRMWARE("amdgpu/cyan_skillfish2_mec.bin");
 258 MODULE_FIRMWARE("amdgpu/cyan_skillfish2_mec2.bin");
 259 MODULE_FIRMWARE("amdgpu/cyan_skillfish2_rlc.bin");
 260
 261 MODULE_FIRMWARE("amdgpu/gc_10_3_7_ce.bin");
 262 MODULE_FIRMWARE("amdgpu/gc_10_3_7_pfp.bin");
 263 MODULE_FIRMWARE("amdgpu/gc_10_3_7_me.bin");
 264 MODULE_FIRMWARE("amdgpu/gc_10_3_7_mec.bin");
 265 MODULE_FIRMWARE("amdgpu/gc_10_3_7_mec2.bin");
 266 MODULE_FIRMWARE("amdgpu/gc_10_3_7_rlc.bin");
 267
 268 static const struct soc15_reg_golden golden_settings_gc_10_1[] =
 269 {
 270         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0xffffffff, 0x00400014),
 271         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_CPF_CLK_CTRL, 0xfcff8fff, 0xf8000100),
 272         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xcd000000, 0x0d000100),
 273         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQ_CLK_CTRL, 0x60000ff0, 0x60000100),
 274         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQG_CLK_CTRL, 0x40000000, 0x40000100),
 275         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xffff8fff, 0xffff8100),
 276         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_WD_CLK_CTRL, 0xfeff8fff, 0xfeff8100),
 277         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
 278         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_VC5_ENABLE, 0x00000002, 0x00000000),
 279         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0x000007ff, 0x000005ff),
 280         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG, 0x20000000, 0x20000000),
 281         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xffffffff, 0x00000420),
 282         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0x00000200, 0x00000200),
 283         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0x07900000, 0x04900000),
 284         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DFSM_TILES_IN_FLIGHT, 0x0000ffff, 0x0000003f),
 285         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_LAST_OF_BURST_CONFIG, 0xffffffff, 0x03860204),
 286         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff0ffff, 0x00000500),
 287         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PRIV_CONTROL, 0x000007ff, 0x000001fe),
 288         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
 289         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x10321032),
 290         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x02310231),
 291         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
 292         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
 293         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CGTT_SCLK_CTRL, 0x10000000, 0x10000100),
 294         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL2, 0xffffffff, 0x1402002f),
 295         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xffff9fff, 0x00001188),
 296         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
 297         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x08000009),
 298         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0x00400000, 0x04440000),
 299         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0x00000800, 0x00000820),
 300         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000),
 301         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0xffffffff, 0xffff3101),
 302         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0x001f0000, 0x00070104),
 303         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ALU_CLK_CTRL, 0xffffffff, 0xffffffff),
 304         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x00000100, 0x00000130),
 305         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0xffffffff, 0xffffffff),
 306         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
 307         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CNTL, 0x60000010, 0x479c0010),
 308         SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CGTT_CLK_CTRL, 0xfeff0fff, 0x40000100),
 309         SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0x00c00000, 0x00c00000)
 310 };
 311
 312 static const struct soc15_reg_golden golden_settings_gc_10_0_nv10[] =
 313 {
 314         /* Pending on emulation bring up */
 315 };
 316
 317 static const struct soc15_reg_golden golden_settings_gc_rlc_spm_10_0_nv10[] =
 318 {
 319         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xe0000000, 0x0),
 320         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 321         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
 322         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 323         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
 324         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 325         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
 326         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 327         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
 328         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 329         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
 330         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 331         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
 332         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 333         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
 334         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 335         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 336         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 337         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8),
 338         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 339         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
 340         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 341         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc),
 342         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 343         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
 344         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 345         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0),
 346         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 347         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
 348         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 349         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4),
 350         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 351         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
 352         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 353         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
 354         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 355         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
 356         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 357         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
 358         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 359         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
 360         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 361         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
 362         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 363         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
 364         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 365         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
 366         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 367         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
 368         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 369         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
 370         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 371         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
 372         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 373         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
 374         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 375         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
 376         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 377         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
 378         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 379         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
 380         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 381         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
 382         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 383         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
 384         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 385         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
 386         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 387         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
 388         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 389         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0),
 390         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 391         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
 392         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 393         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4),
 394         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 395         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
 396         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 397         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8),
 398         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 399         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 400         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 401         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc),
 402         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 403         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
 404         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 405         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0),
 406         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 407         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 408         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 409         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4),
 410         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 411         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 412         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 413         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90),
 414         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 415         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
 416         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 417         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94),
 418         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 419         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
 420         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 421         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98),
 422         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 423         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
 424         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 425         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c),
 426         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 427         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
 428         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 429         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0),
 430         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 431         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
 432         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 433         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4),
 434         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 435         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
 436         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 437         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8),
 438         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 439         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
 440         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 441         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac),
 442         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 443         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
 444         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 445         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
 446         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 447         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
 448         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 449         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
 450         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 451         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
 452         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 453         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
 454         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 455         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
 456         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 457         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
 458         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 459         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
 460         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 461         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
 462         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 463         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
 464         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 465         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
 466         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 467         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 468         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 469         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
 470         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 471         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
 472         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 473         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
 474         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 475         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
 476         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 477         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
 478         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 479         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
 480         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 481         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
 482         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 483         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
 484         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 485         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
 486         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 487         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
 488         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 489         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
 490         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 491         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
 492         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 493         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
 494         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 495         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
 496         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 497         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
 498         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 499         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
 500         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 501         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
 502         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 503         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
 504         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 505         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
 506         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 507         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
 508         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 509         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
 510         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 511         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
 512         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 513         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
 514         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 515         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
 516         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 517         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
 518         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 519         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
 520         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 521         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
 522         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 523         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
 524         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 525         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
 526         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 527         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
 528         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 529         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
 530         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 531         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
 532         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 533         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
 534         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 535         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
 536         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 537         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c),
 538         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 539         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
 540         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 541         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
 542         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 543         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 544         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 545         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
 546         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 547         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
 548         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 549         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
 550         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 551         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
 552         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 553         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
 554         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 555         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
 556         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 557         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
 558         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 559         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
 560         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 561         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
 562         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 563         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 564         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 565         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
 566         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 567         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 568         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 569         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
 570         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 571         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
 572         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 573         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
 574         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 575         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
 576         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 577         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
 578         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 579         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 580         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 581         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
 582         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 583         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 584         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 585         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
 586         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 587         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
 588         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 589         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
 590         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 591         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
 592         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 593         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
 594         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 595         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 596         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 597         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
 598         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 599         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 600         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 601         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
 602         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 603         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
 604         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 605         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
 606         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 607         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
 608         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 609         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
 610         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 611         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
 612         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 613         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
 614         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 615         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
 616         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 617         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
 618         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 619         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 620         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 621         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
 622         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 623         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 624         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 625         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
 626         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 627         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 628         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 629         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
 630         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 631         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 632         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 633         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
 634         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 635         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 636         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 637         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
 638         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 639         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 640         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 641         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
 642         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 643         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 644         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 645         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
 646         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 647         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 648         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 649         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
 650         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 651         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
 652         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 653         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
 654         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 655         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
 656         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 657         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
 658         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 659         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
 660         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 661         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
 662         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 663         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
 664         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 665         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
 666         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 667         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
 668         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 669         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
 670         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 671         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
 672         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 673         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
 674         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 675         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
 676         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 677         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
 678         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 679         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
 680         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 681         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
 682         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 683         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
 684         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 685         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
 686         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 687         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
 688         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 689         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
 690         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 691         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17),
 692         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 693         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
 694         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 695         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17),
 696         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 697         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
 698         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 699         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 700         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 701         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
 702         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 703         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 704         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 705         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
 706         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 707         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
 708         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 709         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
 710         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 711         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
 712         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 713         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
 714         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 715         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
 716         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 717         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
 718         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 719         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
 720         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 721         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
 722         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 723         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 724         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 725         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
 726         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 727         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 728         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 729         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
 730         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 731         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 732         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 733         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
 734         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 735         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 736         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 737         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
 738         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 739         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
 740         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 741         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
 742         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 743         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
 744         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 745         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
 746         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 747         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
 748         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 749         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
 750         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 751         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
 752         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 753         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
 754         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 755         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 756         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 757         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
 758         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 759         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 760         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 761         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
 762         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 763         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 764         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 765         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
 766         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 767         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 768         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 769         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
 770         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 771         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 772         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 773         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
 774         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 775         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 776         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 777         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
 778         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 779         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 780         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 781         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
 782         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 783         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 784         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 785         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
 786         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 787         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 788         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 789         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
 790         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 791         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 792         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 793         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90),
 794         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 795         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
 796         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 797         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90),
 798         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 799         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
 800         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 801         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94),
 802         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 803         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
 804         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 805         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94),
 806         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 807         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
 808         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 809         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0),
 810         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 811         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
 812         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 813         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0),
 814         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 815         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
 816         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 817         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4),
 818         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 819         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
 820         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 821         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4),
 822         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 823         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
 824         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 825         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98),
 826         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 827         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
 828         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 829         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98),
 830         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 831         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
 832         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 833         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c),
 834         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 835         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
 836         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 837         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c),
 838         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 839         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
 840         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 841         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8),
 842         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 843         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 844         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 845         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8),
 846         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 847         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 848         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 849         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac),
 850         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 851         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 852         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 853         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac),
 854         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 855         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 856         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 857         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8),
 858         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 859         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
 860         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 861         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8),
 862         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 863         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
 864         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 865         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc),
 866         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 867         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
 868         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 869         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc),
 870         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 871         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
 872         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 873         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0),
 874         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 875         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 876         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 877         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0),
 878         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 879         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 880         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 881         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4),
 882         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 883         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 884         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 885         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4),
 886         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 887         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 888         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 889         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0),
 890         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 891         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
 892         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 893         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0),
 894         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 895         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
 896         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 897         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4),
 898         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 899         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 900         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 901         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4),
 902         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 903         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 904         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 905         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0),
 906         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 907         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
 908         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 909         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0),
 910         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 911         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
 912         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 913         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4),
 914         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 915         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
 916         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 917         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4),
 918         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 919         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
 920         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 921         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8),
 922         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 923         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
 924         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 925         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8),
 926         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 927         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
 928         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 929         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc),
 930         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 931         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
 932         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 933         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc),
 934         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 935         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
 936         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 937         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8),
 938         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 939         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 940         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 941         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8),
 942         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 943         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 944         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 945         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec),
 946         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 947         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 948         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 949         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec),
 950         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 951         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 952         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 953         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0),
 954         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 955         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
 956         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 957         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0),
 958         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 959         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
 960         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 961         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4),
 962         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 963         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
 964         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 965         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4),
 966         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 967         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
 968         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 969         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8),
 970         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 971         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 972         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 973         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8),
 974         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 975         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 976         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 977         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xfc),
 978         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 979         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 980         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 981         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xfc),
 982         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 983         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 984         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 985         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100),
 986         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 987         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 988         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 989         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100),
 990         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 991         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 992         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 993         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104),
 994         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 995         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
 996         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 997         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104),
 998         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 999         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1000         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1001         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0),
1002         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1003         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
1004         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1005         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0),
1006         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1007         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
1008         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1009         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118),
1010         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1011         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
1012         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1013         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118),
1014         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1015         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
1016         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1017         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c),
1018         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1019         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
1020         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1021         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c),
1022         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1023         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
1024         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1025         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120),
1026         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1027         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
1028         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1029         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120),
1030         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1031         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
1032         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1033         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124),
1034         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1035         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
1036         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1037         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124),
1038         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1039         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
1040         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1041         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc),
1042         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1043         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
1044         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1045         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc),
1046         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1047         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
1048         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1049         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110),
1050         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1051         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1052         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1053         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110),
1054         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1055         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1056         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1057         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114),
1058         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1059         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1060         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1061         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114),
1062         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1063         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1064         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1065         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108),
1066         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1067         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1068         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1069         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108),
1070         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1071         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1072         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1073         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c),
1074         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1075         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1076         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1077         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c),
1078         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1079         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1080         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1081         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8),
1082         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1083         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17),
1084         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1085         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8),
1086         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1087         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17),
1088         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1089         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128),
1090         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1091         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
1092         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1093         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128),
1094         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1095         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
1096         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1097         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c),
1098         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1099         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1100         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1101         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c),
1102         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1103         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1104         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1105         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138),
1106         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1107         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1108         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1109         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138),
1110         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1111         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1112         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1113         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c),
1114         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1115         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1116         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1117         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c),
1118         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1119         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1120         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1121         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130),
1122         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1123         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1124         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1125         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130),
1126         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1127         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1128         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1129         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134),
1130         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1131         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1132         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1133         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134),
1134         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1135         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1136         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1137         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140),
1138         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1139         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1140         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1141         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140),
1142         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1143         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1144         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1145         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144),
1146         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1147         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
1148         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1149         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144),
1150         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1151         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
1152         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1153         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150),
1154         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1155         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1156         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1157         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150),
1158         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1159         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1160         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1161         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154),
1162         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1163         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
1164         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1165         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154),
1166         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1167         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
1168         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1169         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148),
1170         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1171         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1172         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1173         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148),
1174         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1175         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1176         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1177         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c),
1178         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1179         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
1180         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1181         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c),
1182         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1183         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
1184         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1185         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158),
1186         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1187         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
1188         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1189         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158),
1190         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1191         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
1192         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1193         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c),
1194         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1195         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1196         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1197         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c),
1198         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1199         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1200         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1201         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168),
1202         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1203         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1),
1204         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1205         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168),
1206         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1207         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1),
1208         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1209         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c),
1210         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1211         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
1212         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1213         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c),
1214         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1215         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
1216         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1217         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160),
1218         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1219         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
1220         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1221         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160),
1222         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1223         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
1224         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1225         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164),
1226         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1227         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1228         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1229         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164),
1230         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1231         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1232         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1233         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170),
1234         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1235         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
1236         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1237         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170),
1238         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1239         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
1240         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1241         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174),
1242         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1243         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
1244         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1245         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174),
1246         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1247         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
1248         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1249         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180),
1250         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1251         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
1252         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1253         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180),
1254         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1255         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
1256         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1257         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184),
1258         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1259         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1260         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1261         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184),
1262         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1263         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1264         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1265         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178),
1266         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1267         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
1268         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1269         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178),
1270         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1271         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
1272         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1273         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c),
1274         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1275         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
1276         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1277         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c),
1278         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1279         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
1280         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1281         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188),
1282         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1283         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1284         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1285         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188),
1286         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1287         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1288         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1289         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c),
1290         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1291         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
1292         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1293         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c),
1294         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1295         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
1296         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1297         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198),
1298         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1299         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
1300         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1301         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198),
1302         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1303         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
1304         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1305         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c),
1306         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1307         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
1308         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1309         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c),
1310         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1311         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
1312         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1313         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190),
1314         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1315         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1316         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1317         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190),
1318         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1319         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1320         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1321         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194),
1322         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1323         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
1324         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1325         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194),
1326         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1327         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
1328         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1329         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
1330         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1331         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
1332         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1333         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
1334         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1335         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1336         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1337         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
1338         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1339         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
1340         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1341         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
1342         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1343         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
1344         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1345         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
1346         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1347         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1f),
1348         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1349         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
1350         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1351         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1f),
1352         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1353         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
1354         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1355         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
1356         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1357         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_SAMPLE_SKEW, 0x000000FF, 0x19),
1358         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1359         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_MUXSEL_SKEW, 0x000000FF, 0x20),
1360         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1361         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0x5),
1362         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1363         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0xa),
1364         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1365         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x14),
1366         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1367         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x19),
1368         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1369         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_DESER_START_SKEW, 0x000000FF, 0x33),
1370         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xFFFFFFFF, 0xe0000000)
1371 };
1372
1373 static const struct soc15_reg_golden golden_settings_gc_10_1_1[] =
1374 {
1375         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0xffffffff, 0x003c0014),
1376         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_GS_NGG_CLK_CTRL, 0xffff8fff, 0xffff8100),
1377         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_IA_CLK_CTRL, 0xffff0fff, 0xffff0100),
1378         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xcd000000, 0x0d000100),
1379         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQ_CLK_CTRL, 0xf8ff0fff, 0x60000100),
1380         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQG_CLK_CTRL, 0x40000ff0, 0x40000100),
1381         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xffff8fff, 0xffff8100),
1382         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_WD_CLK_CTRL, 0xffff8fff, 0xffff8100),
1383         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
1384         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_VC5_ENABLE, 0x00000002, 0x00000000),
1385         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0x800007ff, 0x000005ff),
1386         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG, 0xffffffff, 0x20000000),
1387         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xffffffff, 0x00000420),
1388         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0x00000200, 0x00000200),
1389         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x04900000),
1390         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DFSM_TILES_IN_FLIGHT, 0x0000ffff, 0x0000003f),
1391         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_LAST_OF_BURST_CONFIG, 0xffffffff, 0x03860204),
1392         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff0ffff, 0x00000500),
1393         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PRIV_CONTROL, 0x000007ff, 0x000001fe),
1394         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
1395         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffe7),
1396         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffe7),
1397         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CGTT_SCLK_CTRL, 0xffff0fff, 0x10000100),
1398         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL2, 0xffffffff, 0x1402002f),
1399         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xffffbfff, 0x00000188),
1400         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
1401         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x08000009),
1402         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0x00400000, 0x04440000),
1403         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0x00000800, 0x00000820),
1404         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000),
1405         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0xffffffff, 0xffff3101),
1406         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0x001f0000, 0x00070105),
1407         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ALU_CLK_CTRL, 0xffffffff, 0xffffffff),
1408         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x00000133, 0x00000130),
1409         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0xffffffff, 0xffffffff),
1410         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
1411         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CNTL, 0x60000010, 0x479c0010),
1412         SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0x00c00000, 0x00c00000),
1413 };
1414
1415 static const struct soc15_reg_golden golden_settings_gc_10_1_2[] =
1416 {
1417         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0x003e001f, 0x003c0014),
1418         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_GS_NGG_CLK_CTRL, 0xffff8fff, 0xffff8100),
1419         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_IA_CLK_CTRL, 0xffff0fff, 0xffff0100),
1420         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xff7f0fff, 0x0d000100),
1421         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQ_CLK_CTRL, 0xffffcfff, 0x60000100),
1422         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQG_CLK_CTRL, 0xffff0fff, 0x40000100),
1423         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xffff8fff, 0xffff8100),
1424         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_WD_CLK_CTRL, 0xffff8fff, 0xffff8100),
1425         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
1426         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_VC5_ENABLE, 0x00000003, 0x00000000),
1427         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0x800007ff, 0x000005ff),
1428         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG, 0xffffffff, 0x20000000),
1429         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xffffffff, 0x00000420),
1430         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000200),
1431         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x04900000),
1432         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DFSM_TILES_IN_FLIGHT, 0x0000ffff, 0x0000003f),
1433         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_LAST_OF_BURST_CONFIG, 0xffffffff, 0x03860204),
1434         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0x0c1800ff, 0x00000044),
1435         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff0ffff, 0x00000500),
1436         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PRIV_CONTROL, 0x00007fff, 0x000001fe),
1437         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
1438         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x10321032),
1439         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x02310231),
1440         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
1441         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
1442         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CGTT_SCLK_CTRL, 0xffff0fff, 0x10000100),
1443         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL2, 0xffffffff, 0x1402002f),
1444         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xffffbfff, 0x00000188),
1445         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_0, 0xffffffff, 0x842a4c02),
1446         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
1447         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x08000009),
1448         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0xffffffff, 0x04440000),
1449         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0x00000820, 0x00000820),
1450         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000),
1451         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0xffffffff, 0xffff3101),
1452         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0x001f0000, 0x00070104),
1453         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ALU_CLK_CTRL, 0xffffffff, 0xffffffff),
1454         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x00000133, 0x00000130),
1455         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0xffffffff, 0xffffffff),
1456         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
1457         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CNTL, 0xffdf80ff, 0x479c0010),
1458         SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffffffff, 0x00c00000)
1459 };
1460
1461 static const struct soc15_reg_golden golden_settings_gc_10_1_nv14[] =
1462 {
1463         /* Pending on emulation bring up */
1464 };
1465
1466 static const struct soc15_reg_golden golden_settings_gc_rlc_spm_10_1_nv14[] =
1467 {
1468         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xE0000000L, 0x0),
1469         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1470         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
1471         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1472         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1473         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1474         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
1475         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1476         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
1477         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1478         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
1479         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1480         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
1481         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1482         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
1483         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1484         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1485         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1486         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
1487         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1488         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1489         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1490         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
1491         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1492         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1493         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1494         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
1495         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1496         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1497         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1498         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
1499         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1500         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1501         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1502         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
1503         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1504         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1505         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1506         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
1507         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1508         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1509         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1510         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
1511         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1512         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1513         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1514         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
1515         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1516         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1517         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1518         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
1519         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1520         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20),
1521         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1522         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
1523         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1524         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
1525         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1526         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
1527         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1528         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1529         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1530         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
1531         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1532         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1533         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1534         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
1535         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1536         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1537         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1538         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
1539         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1540         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1541         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1542         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
1543         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1544         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1545         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1546         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
1547         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1548         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
1549         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1550         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
1551         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1552         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1553         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1554         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
1555         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1556         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1557         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1558         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
1559         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1560         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1561         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1562         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
1563         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1564         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1565         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1566         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
1567         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1568         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
1569         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1570         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
1571         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1572         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
1573         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1574         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
1575         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1576         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
1577         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1578         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
1579         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1580         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
1581         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1582         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
1583         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1584         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
1585         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1586         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
1587         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1588         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
1589         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1590         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
1591         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1592         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
1593         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1594         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
1595         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1596         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
1597         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1598         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
1599         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1600         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
1601         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1602         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
1603         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1604         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
1605         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1606         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c),
1607         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1608         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1609         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1610         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
1611         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1612         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1613         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1614         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
1615         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1616         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1617         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1618         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
1619         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1620         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1621         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1622         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
1623         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1624         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1625         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1626         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
1627         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1628         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
1629         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1630         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
1631         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1632         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1633         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1634         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
1635         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1636         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1637         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1638         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
1639         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1640         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
1641         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1642         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
1643         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1644         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
1645         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1646         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
1647         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1648         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
1649         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1650         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
1651         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1652         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e),
1653         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1654         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
1655         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1656         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e),
1657         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1658         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
1659         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1660         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e),
1661         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1662         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
1663         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1664         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e),
1665         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1666         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
1667         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1668         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20),
1669         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1670         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
1671         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1672         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
1673         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1674         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
1675         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1676         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
1677         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1678         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
1679         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1680         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e),
1681         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1682         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
1683         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1684         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e),
1685         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1686         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
1687         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1688         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
1689         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1690         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
1691         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1692         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1693         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1694         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
1695         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1696         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1697         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1698         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
1699         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1700         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1701         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1702         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
1703         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1704         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1705         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1706         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
1707         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1708         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1709         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1710         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
1711         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1712         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1713         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1714         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
1715         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1716         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1717         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1718         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
1719         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1720         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1721         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1722         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
1723         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1724         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1725         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1726         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
1727         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1728         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1729         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1730         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
1731         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1732         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1733         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1734         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
1735         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1736         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1737         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1738         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90),
1739         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1740         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1741         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1742         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94),
1743         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1744         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
1745         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1746         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0),
1747         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1748         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1749         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1750         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4),
1751         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1752         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1753         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1754         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98),
1755         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1756         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1757         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1758         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c),
1759         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1760         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
1761         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1762         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8),
1763         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1764         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
1765         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1766         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac),
1767         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1768         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1769         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1770         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8),
1771         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1772         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1773         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1774         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc),
1775         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1776         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1777         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1778         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0),
1779         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1780         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
1781         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1782         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4),
1783         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1784         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1785         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1786         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0),
1787         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1788         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1789         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1790         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4),
1791         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1792         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1793         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1794         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0),
1795         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1796         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1797         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1798         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4),
1799         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1800         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1801         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1802         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8),
1803         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1804         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1805         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1806         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc),
1807         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1808         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1809         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1810         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8),
1811         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1812         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1813         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1814         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc),
1815         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1816         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1817         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1818         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8),
1819         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1820         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1821         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1822         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec),
1823         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1824         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1825         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1826         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0),
1827         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1828         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1829         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1830         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe4),
1831         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1832         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1833         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1834         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100),
1835         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1836         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1837         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1838         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104),
1839         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1840         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1841         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1842         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108),
1843         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1844         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1845         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1846         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c),
1847         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1848         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1849         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1850         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110),
1851         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1852         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1853         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1854         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114),
1855         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1856         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1857         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1858         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118),
1859         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1860         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1861         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1862         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c),
1863         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1864         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1865         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1866         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8),
1867         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1868         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17),
1869         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1870         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130),
1871         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1872         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1873         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1874         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134),
1875         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1876         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1877         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1878         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138),
1879         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1880         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1881         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1882         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c),
1883         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1884         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1885         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1886         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4),
1887         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1888         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20),
1889         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1890         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128),
1891         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1892         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1893         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1894         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c),
1895         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1896         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1897         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1898         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120),
1899         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1900         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1901         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1902         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124),
1903         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1904         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1905         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1906         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0),
1907         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1908         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
1909         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1910         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140),
1911         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1912         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1913         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1914         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144),
1915         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1916         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1917         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1918         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150),
1919         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1920         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1921         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1922         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154),
1923         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1924         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1925         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1926         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148),
1927         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1928         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1929         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1930         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c),
1931         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1932         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1933         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1934         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158),
1935         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1936         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1937         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1938         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c),
1939         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1940         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
1941         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1942         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168),
1943         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1944         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1945         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1946         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c),
1947         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1948         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1949         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1950         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160),
1951         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1952         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1953         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1954         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164),
1955         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1956         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
1957         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1958         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170),
1959         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1960         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
1961         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1962         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174),
1963         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1964         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
1965         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1966         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180),
1967         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1968         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1969         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1970         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184),
1971         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1972         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
1973         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1974         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178),
1975         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1976         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
1977         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1978         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c),
1979         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1980         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
1981         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1982         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188),
1983         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1984         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1985         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1986         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c),
1987         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1988         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1989         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1990         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198),
1991         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1992         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1993         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1994         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c),
1995         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1996         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1997         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1998         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190),
1999         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2000         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
2001         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2002         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194),
2003         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2004         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2005         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2006         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1a0),
2007         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2008         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2009         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2010         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1a4),
2011         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2012         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
2013         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2014         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1b0),
2015         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2016         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2017         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2018         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1b4),
2019         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2020         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2021         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2022         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1a8),
2023         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2024         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2025         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2026         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1ac),
2027         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2028         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
2029         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2030         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1b8),
2031         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2032         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
2033         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2034         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1bc),
2035         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2036         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2037         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2038         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c8),
2039         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2040         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
2041         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2042         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1cc),
2043         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2044         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
2045         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2046         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c0),
2047         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2048         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
2049         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2050         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c4),
2051         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2052         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2053         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2054         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
2055         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2056         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2057         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2058         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
2059         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2060         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2061         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2062         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
2063         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2064         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20),
2065         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2066         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
2067         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2068         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20),
2069         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2070         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
2071         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2072         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
2073         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2074         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_SAMPLE_SKEW, 0x000000FF, 0x26),
2075         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2076         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_MUXSEL_SKEW, 0x000000FF, 0x28),
2077         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2078         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0xf),
2079         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2080         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0x15),
2081         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2082         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x1f),
2083         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2084         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x25),
2085         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2086         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_DESER_START_SKEW, 0x000000FF, 0x3b),
2087         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xFFFFFFFF, 0xe0000000)
2088 };
2089
2090 static const struct soc15_reg_golden golden_settings_gc_10_1_2_nv12[] =
2091 {
2092         /* Pending on emulation bring up */
2093 };
2094
2095 static const struct soc15_reg_golden golden_settings_gc_rlc_spm_10_1_2_nv12[] =
2096 {
2097         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xe0000000L, 0x0),
2098         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2099         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
2100         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2101         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
2102         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2103         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
2104         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2105         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
2106         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2107         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
2108         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2109         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
2110         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2111         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
2112         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2113         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
2114         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2115         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8),
2116         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2117         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2118         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2119         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc),
2120         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2121         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2122         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2123         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0),
2124         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2125         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2126         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2127         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4),
2128         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2129         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2130         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2131         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
2132         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2133         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2134         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2135         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
2136         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2137         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2138         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2139         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
2140         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2141         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2142         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2143         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
2144         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2145         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2146         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2147         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
2148         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2149         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2150         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2151         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
2152         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2153         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2154         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2155         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
2156         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2157         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2158         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2159         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
2160         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2161         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
2162         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2163         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
2164         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2165         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
2166         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2167         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0),
2168         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2169         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
2170         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2171         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4),
2172         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2173         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
2174         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2175         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8),
2176         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2177         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2178         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2179         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc),
2180         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2181         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2182         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2183         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0),
2184         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2185         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2186         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2187         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4),
2188         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2189         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2190         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2191         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90),
2192         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2193         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
2194         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2195         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94),
2196         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2197         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1),
2198         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2199         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98),
2200         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2201         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
2202         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2203         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c),
2204         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2205         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2206         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2207         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0),
2208         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2209         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1),
2210         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2211         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4),
2212         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2213         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2214         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2215         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8),
2216         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2217         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2218         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2219         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac),
2220         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2221         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2222         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2223         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
2224         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2225         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
2226         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2227         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
2228         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2229         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2230         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2231         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
2232         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2233         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
2234         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2235         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
2236         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2237         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2238         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2239         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
2240         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2241         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2242         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2243         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
2244         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2245         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2246         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2247         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
2248         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2249         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
2250         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2251         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
2252         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2253         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2254         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2255         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
2256         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2257         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2258         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2259         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
2260         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2261         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
2262         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2263         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
2264         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2265         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2266         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2267         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
2268         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2269         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
2270         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2271         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
2272         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2273         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
2274         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2275         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
2276         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2277         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2278         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2279         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
2280         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2281         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2282         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2283         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
2284         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2285         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2286         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2287         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
2288         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2289         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
2290         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2291         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
2292         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2293         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2294         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2295         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
2296         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2297         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2298         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2299         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
2300         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2301         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2302         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2303         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
2304         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2305         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2306         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2307         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
2308         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2309         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2310         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2311         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
2312         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2313         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
2314         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2315         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c),
2316         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2317         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
2318         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2319         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
2320         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2321         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2322         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2323         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
2324         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2325         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
2326         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2327         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
2328         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2329         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
2330         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2331         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
2332         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2333         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2334         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2335         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
2336         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2337         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2338         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2339         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
2340         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2341         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2342         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2343         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
2344         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2345         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2346         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2347         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
2348         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2349         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2350         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2351         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
2352         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2353         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2354         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2355         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
2356         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2357         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
2358         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2359         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
2360         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2361         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
2362         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2363         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
2364         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2365         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2366         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2367         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
2368         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2369         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2370         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2371         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
2372         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2373         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
2374         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2375         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
2376         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2377         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
2378         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2379         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
2380         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2381         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2382         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2383         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
2384         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2385         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2386         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2387         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
2388         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2389         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
2390         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2391         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
2392         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2393         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
2394         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2395         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
2396         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2397         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2398         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2399         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
2400         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2401         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2402         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2403         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
2404         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2405         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2406         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2407         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
2408         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2409         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2410         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2411         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
2412         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2413         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2414         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2415         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
2416         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2417         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2418         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2419         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
2420         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2421         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2422         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2423         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
2424         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2425         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2426         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2427         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
2428         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2429         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2430         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2431         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
2432         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2433         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2434         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2435         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
2436         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2437         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2438         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2439         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
2440         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2441         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2442         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2443         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
2444         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2445         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2446         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2447         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
2448         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2449         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2450         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2451         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
2452         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2453         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2454         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2455         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
2456         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2457         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2458         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2459         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
2460         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2461         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2462         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2463         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
2464         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2465         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2466         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2467         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
2468         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2469         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
2470         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2471         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
2472         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2473         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
2474         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2475         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
2476         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2477         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2478         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2479         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
2480         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2481         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2482         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2483         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
2484         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2485         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
2486         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2487         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
2488         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2489         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
2490         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2491         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
2492         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2493         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
2494         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2495         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
2496         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2497         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
2498         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2499         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
2500         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2501         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2502         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2503         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
2504         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2505         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2506         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2507         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
2508         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2509         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2510         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2511         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
2512         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2513         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2514         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2515         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
2516         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2517         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
2518         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2519         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
2520         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2521         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
2522         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2523         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
2524         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2525         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2526         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2527         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
2528         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2529         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2530         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2531         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
2532         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2533         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2534         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2535         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
2536         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2537         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2538         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2539         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
2540         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2541         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2542         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2543         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
2544         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2545         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2546         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2547         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
2548         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2549         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2550         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2551         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
2552         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2553         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2554         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2555         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
2556         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2557         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2558         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2559         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
2560         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2561         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2562         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2563         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
2564         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2565         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2566         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2567         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
2568         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2569         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2570         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2571         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90),
2572         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2573         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
2574         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2575         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90),
2576         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2577         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
2578         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2579         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94),
2580         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2581         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2582         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2583         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94),
2584         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2585         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2586         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2587         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0),
2588         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2589         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2590         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2591         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0),
2592         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2593         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2594         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2595         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4),
2596         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2597         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2598         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2599         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4),
2600         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2601         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2602         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2603         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98),
2604         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2605         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
2606         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2607         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98),
2608         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2609         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
2610         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2611         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c),
2612         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2613         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2614         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2615         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c),
2616         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2617         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2618         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2619         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8),
2620         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2621         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2622         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2623         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8),
2624         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2625         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2626         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2627         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac),
2628         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2629         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2630         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2631         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac),
2632         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2633         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2634         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2635         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8),
2636         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2637         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2638         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2639         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8),
2640         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2641         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2642         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2643         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc),
2644         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2645         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2646         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2647         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc),
2648         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2649         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2650         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2651         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0),
2652         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2653         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2654         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2655         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0),
2656         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2657         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2658         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2659         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4),
2660         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2661         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2662         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2663         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4),
2664         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2665         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2666         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2667         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0),
2668         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2669         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2670         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2671         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0),
2672         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2673         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2674         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2675         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4),
2676         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2677         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2678         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2679         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4),
2680         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2681         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2682         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2683         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0),
2684         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2685         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2686         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2687         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0),
2688         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2689         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2690         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2691         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4),
2692         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2693         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2694         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2695         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4),
2696         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2697         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2698         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2699         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8),
2700         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2701         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2702         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2703         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8),
2704         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2705         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2706         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2707         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc),
2708         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2709         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2710         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2711         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc),
2712         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2713         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2714         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2715         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8),
2716         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2717         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2718         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2719         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8),
2720         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2721         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2722         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2723         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec),
2724         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2725         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
2726         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2727         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec),
2728         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2729         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
2730         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2731         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0),
2732         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2733         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2734         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2735         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0),
2736         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2737         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2738         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2739         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4),
2740         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2741         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2742         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2743         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4),
2744         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2745         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2746         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2747         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8),
2748         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2749         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2750         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2751         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8),
2752         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2753         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2754         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2755         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xfc),
2756         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2757         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17),
2758         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2759         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xfc),
2760         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2761         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17),
2762         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2763         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100),
2764         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2765         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
2766         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2767         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100),
2768         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2769         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
2770         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2771         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104),
2772         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2773         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2774         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2775         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104),
2776         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2777         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2778         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2779         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0),
2780         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2781         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2782         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2783         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0),
2784         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2785         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2786         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2787         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118),
2788         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2789         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2790         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2791         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118),
2792         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2793         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2794         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2795         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c),
2796         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2797         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2798         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2799         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c),
2800         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2801         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2802         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2803         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120),
2804         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2805         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2806         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2807         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120),
2808         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2809         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2810         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2811         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124),
2812         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2813         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2814         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2815         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124),
2816         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2817         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2818         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2819         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc),
2820         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2821         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2822         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2823         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc),
2824         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2825         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2826         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2827         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110),
2828         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2829         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2830         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2831         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110),
2832         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2833         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2834         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2835         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114),
2836         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2837         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2838         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2839         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114),
2840         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2841         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2842         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2843         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108),
2844         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2845         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2846         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2847         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108),
2848         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2849         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2850         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2851         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c),
2852         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2853         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2854         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2855         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c),
2856         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2857         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2858         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2859         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8),
2860         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2861         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
2862         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2863         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8),
2864         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2865         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
2866         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2867         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128),
2868         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2869         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2870         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2871         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128),
2872         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2873         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2874         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2875         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c),
2876         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2877         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2878         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2879         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c),
2880         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2881         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2882         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2883         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138),
2884         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2885         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2886         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2887         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138),
2888         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2889         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2890         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2891         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c),
2892         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2893         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2894         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2895         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c),
2896         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2897         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2898         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2899         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130),
2900         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2901         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2902         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2903         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130),
2904         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2905         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2906         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2907         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134),
2908         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2909         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
2910         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2911         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134),
2912         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2913         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
2914         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2915         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140),
2916         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2917         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2918         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2919         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140),
2920         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2921         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2922         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2923         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144),
2924         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2925         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2926         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2927         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144),
2928         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2929         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2930         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2931         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150),
2932         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2933         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2934         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2935         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150),
2936         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2937         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2938         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2939         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154),
2940         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2941         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2942         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2943         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154),
2944         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2945         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2946         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2947         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148),
2948         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2949         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2950         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2951         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148),
2952         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2953         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2954         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2955         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c),
2956         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2957         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2958         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2959         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c),
2960         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2961         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2962         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2963         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158),
2964         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2965         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
2966         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2967         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158),
2968         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2969         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
2970         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2971         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c),
2972         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2973         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
2974         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2975         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c),
2976         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2977         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
2978         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2979         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168),
2980         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2981         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
2982         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2983         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168),
2984         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2985         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
2986         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2987         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c),
2988         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2989         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
2990         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2991         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c),
2992         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2993         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
2994         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2995         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160),
2996         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2997         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
2998         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2999         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160),
3000         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3001         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
3002         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3003         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164),
3004         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3005         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
3006         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3007         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164),
3008         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3009         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
3010         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3011         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170),
3012         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3013         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
3014         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3015         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170),
3016         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3017         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
3018         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3019         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174),
3020         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3021         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3022         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3023         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174),
3024         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3025         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3026         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3027         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180),
3028         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3029         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
3030         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3031         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180),
3032         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3033         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
3034         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3035         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184),
3036         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3037         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3038         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3039         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184),
3040         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3041         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3042         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3043         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178),
3044         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3045         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
3046         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3047         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178),
3048         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3049         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
3050         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3051         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c),
3052         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3053         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3054         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3055         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c),
3056         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3057         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3058         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3059         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188),
3060         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3061         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3062         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3063         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188),
3064         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3065         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3066         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3067         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c),
3068         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3069         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
3070         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3071         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c),
3072         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3073         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
3074         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3075         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198),
3076         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3077         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
3078         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3079         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198),
3080         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3081         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
3082         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3083         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c),
3084         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3085         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
3086         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3087         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c),
3088         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3089         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
3090         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3091         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190),
3092         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3093         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3094         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3095         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190),
3096         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3097         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3098         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3099         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194),
3100         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3101         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
3102         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3103         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194),
3104         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3105         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
3106         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3107         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
3108         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3109         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
3110         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3111         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
3112         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3113         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
3114         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3115         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
3116         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3117         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
3118         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3119         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
3120         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3121         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
3122         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3123         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
3124         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3125         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1f),
3126         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3127         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
3128         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3129         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1f),
3130         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3131         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
3132         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3133         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
3134         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3135         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_SAMPLE_SKEW, 0x000000FF, 0x1f),
3136         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3137         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_MUXSEL_SKEW, 0x000000FF, 0x22),
3138         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3139         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0x1),
3140         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3141         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0x6),
3142         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3143         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x10),
3144         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3145         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x15),
3146         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3147         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_DESER_START_SKEW, 0x000000FF, 0x35),
3148         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xFFFFFFFF, 0xe0000000)
3149 };
3150
3151 static const struct soc15_reg_golden golden_settings_gc_10_3[] =
3152 {
3153         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0x78000000, 0x78000100),
3154         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_PS_CLK_CTRL, 0xff7f0fff, 0x78000100),
3155         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA0_CLK_CTRL, 0xff7f0fff, 0x30000100),
3156         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA1_CLK_CTRL, 0xff7f0fff, 0x7e000100),
3157         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c000),
3158         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000280),
3159         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000),
3160         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_EXCEPTION_CONTROL, 0x7fff0f1f, 0x00b80000),
3161         SOC15_REG_GOLDEN_VALUE(GC, 0 ,mmGCEA_SDP_TAG_RESERVE0, 0xffffffff, 0x10100100),
3162         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCEA_SDP_TAG_RESERVE1, 0xffffffff, 0x17000088),
3163         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Sienna_Cichlid, 0x1ff1ffff, 0x00000500),
3164         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCUTCL2_CGTT_CLK_CTRL_Sienna_Cichlid, 0xff000000, 0xff008080),
3165         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCVM_L2_CGTT_CLK_CTRL_Sienna_Cichlid, 0xff000000, 0xff008080),
3166         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PC_CNTL, 0x003fffff, 0x00280400),
3167         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
3168         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
3169         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008),
3170         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x10f80988),
3171         SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG,  0x00000020, 0x00000020),
3172         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007),
3173         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
3174         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0xffffffbf, 0x00000820),
3175         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0xffffffff, 0x00070104),
3176         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_CONFIG, 0xe07df47f, 0x00180070),
3177         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER0_SELECT, 0xf0f001ff, 0x00000000),
3178         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER1_SELECT, 0xf0f001ff, 0x00000000),
3179         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER10_SELECT, 0xf0f001ff, 0x00000000),
3180         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER11_SELECT, 0xf0f001ff, 0x00000000),
3181         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER12_SELECT, 0xf0f001ff, 0x00000000),
3182         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER13_SELECT, 0xf0f001ff, 0x00000000),
3183         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER14_SELECT, 0xf0f001ff, 0x00000000),
3184         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER15_SELECT, 0xf0f001ff, 0x00000000),
3185         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER2_SELECT, 0xf0f001ff, 0x00000000),
3186         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER3_SELECT, 0xf0f001ff, 0x00000000),
3187         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER4_SELECT, 0xf0f001ff, 0x00000000),
3188         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER5_SELECT, 0xf0f001ff, 0x00000000),
3189         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER6_SELECT, 0xf0f001ff, 0x00000000),
3190         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER7_SELECT, 0xf0f001ff, 0x00000000),
3191         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER8_SELECT, 0xf0f001ff, 0x00000000),
3192         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER9_SELECT, 0xf0f001ff, 0x00000000),
3193         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSX_DEBUG_1, 0x00010000, 0x00010020),
3194         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
3195         SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffbfffff, 0x00a00000)
3196 };
3197
3198 static const struct soc15_reg_golden golden_settings_gc_10_3_sienna_cichlid[] =
3199 {
3200         /* Pending on emulation bring up */
3201 };
3202
3203 static const struct soc15_reg_golden golden_settings_gc_10_3_2[] =
3204 {
3205         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0xff7f0fff, 0x78000100),
3206         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_PS_CLK_CTRL, 0xff7f0fff, 0x78000100),
3207         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA0_CLK_CTRL, 0xff7f0fff, 0x30000100),
3208         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA1_CLK_CTRL, 0xff7f0fff, 0x7e000100),
3209         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c000),
3210         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000280),
3211         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000),
3212         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_EXCEPTION_CONTROL, 0x7fff0f1f, 0x00b80000),
3213         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Sienna_Cichlid, 0x1ff1ffff, 0x00000500),
3214         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCUTCL2_CGTT_CLK_CTRL_Sienna_Cichlid, 0xffffffff, 0xff008080),
3215         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCVM_L2_CGTT_CLK_CTRL_Sienna_Cichlid, 0xffff8fff, 0xff008080),
3216         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PC_CNTL, 0x003fffff, 0x00280400),
3217         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
3218         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
3219         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008),
3220         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x00f80988),
3221         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007),
3222         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
3223         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0xffffffbf, 0x00000820),
3224         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0xffffffff, 0x00070104),
3225         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_START_PHASE, 0x000000ff, 0x00000004),
3226         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_CONFIG, 0xe07df47f, 0x00180070),
3227         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER0_SELECT, 0xf0f001ff, 0x00000000),
3228         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER1_SELECT, 0xf0f001ff, 0x00000000),
3229         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER10_SELECT, 0xf0f001ff, 0x00000000),
3230         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER11_SELECT, 0xf0f001ff, 0x00000000),
3231         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER12_SELECT, 0xf0f001ff, 0x00000000),
3232         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER13_SELECT, 0xf0f001ff, 0x00000000),
3233         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER14_SELECT, 0xf0f001ff, 0x00000000),
3234         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER15_SELECT, 0xf0f001ff, 0x00000000),
3235         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER2_SELECT, 0xf0f001ff, 0x00000000),
3236         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER3_SELECT, 0xf0f001ff, 0x00000000),
3237         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER4_SELECT, 0xf0f001ff, 0x00000000),
3238         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER5_SELECT, 0xf0f001ff, 0x00000000),
3239         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER6_SELECT, 0xf0f001ff, 0x00000000),
3240         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER7_SELECT, 0xf0f001ff, 0x00000000),
3241         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER8_SELECT, 0xf0f001ff, 0x00000000),
3242         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER9_SELECT, 0xf0f001ff, 0x00000000),
3243         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
3244         SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffbfffff, 0x00a00000),
3245         SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_GS_MAX_WAVE_ID, 0x00000fff, 0x000003ff),
3246
3247         /* This is not in GDB yet. Don't remove it. It fixes a GPU hang on Navy Flounder. */
3248         SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG,  0x00000020, 0x00000020),
3249 };
3250
3251 static const struct soc15_reg_golden golden_settings_gc_10_3_vangogh[] =
3252 {
3253         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA0_CLK_CTRL, 0xff7f0fff, 0x30000100),
3254         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA1_CLK_CTRL, 0xff7f0fff, 0x7e000100),
3255         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0x000000ff, 0x000000e4),
3256         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000200),
3257         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000),
3258         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_EXCEPTION_CONTROL, 0x7fff0f1f, 0x00b80000),
3259         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0x0c1807ff, 0x00000142),
3260         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Vangogh, 0x1ff1ffff, 0x00000500),
3261         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0x000000ff, 0x000000e4),
3262         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x32103210),
3263         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x32103210),
3264         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xfffffff3),
3265         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xfffffff3),
3266         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008),
3267         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x00f80988),
3268         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007),
3269         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
3270         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0xffffffbf, 0x00000020),
3271         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1_Vangogh, 0xffffffff, 0x00070103),
3272         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQG_CONFIG, 0x000017ff, 0x00001000),
3273         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSX_DEBUG_1, 0x00010000, 0x00010020),
3274         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
3275         SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffffffff, 0x00400000),
3276         SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_GS_MAX_WAVE_ID, 0x00000fff, 0x000000ff),
3277
3278         /* This is not in GDB yet. Don't remove it. It fixes a GPU hang on VanGogh. */
3279         SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG,  0x00000020, 0x00000020),
3280 };
3281
3282 static const struct soc15_reg_golden golden_settings_gc_10_3_3[] =
3283 {
3284         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0xff7f0fff, 0x78000100),
3285         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0x000000ff, 0x000000e4),
3286         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c200),
3287         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000280),
3288         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000),
3289         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0x0c1807ff, 0x00000242),
3290         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff1ffff, 0x00000500),
3291         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0x000000ff, 0x000000e4),
3292         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x32103210),
3293         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x32103210),
3294         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xfffffff3),
3295         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xfffffff3),
3296         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008),
3297         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x00f80988),
3298         SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG, 0x000001ff, 0x00000020),
3299         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007),
3300         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
3301         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0xffffffbf, 0x00000820),
3302         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
3303         SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffffffff, 0x00100000)
3304 };
3305
3306 static const struct soc15_reg_golden golden_settings_gc_10_3_4[] =
3307 {
3308         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0x78000000, 0x78000100),
3309         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA0_CLK_CTRL, 0x30000000, 0x30000100),
3310         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA1_CLK_CTRL, 0x7e000000, 0x7e000100),
3311         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c000),
3312         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0x00000280, 0x00000280),
3313         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0x07800000, 0x00800000),
3314         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Sienna_Cichlid, 0x00001d00, 0x00000500),
3315         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PC_CNTL, 0x003c0000, 0x00280400),
3316         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
3317         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
3318         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0x40000000, 0x580f1008),
3319         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0x00040000, 0x00f80988),
3320         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0x01000000, 0x01200007),
3321         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
3322         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0x00000800, 0x00000820),
3323         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_CONFIG, 0x0000001f, 0x00180070),
3324         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER0_SELECT, 0xf0f001ff, 0x00000000),
3325         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER1_SELECT, 0xf0f001ff, 0x00000000),
3326         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER10_SELECT, 0xf0f001ff, 0x00000000),
3327         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER11_SELECT, 0xf0f001ff, 0x00000000),
3328         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER12_SELECT, 0xf0f001ff, 0x00000000),
3329         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER13_SELECT, 0xf0f001ff, 0x00000000),
3330         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER14_SELECT, 0xf0f001ff, 0x00000000),
3331         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER15_SELECT, 0xf0f001ff, 0x00000000),
3332         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER2_SELECT, 0xf0f001ff, 0x00000000),
3333         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER3_SELECT, 0xf0f001ff, 0x00000000),
3334         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER4_SELECT, 0xf0f001ff, 0x00000000),
3335         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER5_SELECT, 0xf0f001ff, 0x00000000),
3336         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER6_SELECT, 0xf0f001ff, 0x00000000),
3337         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER7_SELECT, 0xf0f001ff, 0x00000000),
3338         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER8_SELECT, 0xf0f001ff, 0x00000000),
3339         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER9_SELECT, 0xf0f001ff, 0x00000000),
3340         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSX_DEBUG_1, 0x00010000, 0x00010020),
3341         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0x01030000, 0x01030000),
3342         SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0x03a00000, 0x00a00000),
3343         SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG,  0x00000020, 0x00000020)
3344 };
3345
3346 static const struct soc15_reg_golden golden_settings_gc_10_3_5[] = {
3347         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0x78000000, 0x78000100),
3348         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA0_CLK_CTRL, 0xb0000ff0, 0x30000100),
3349         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA1_CLK_CTRL, 0xff000000, 0x7e000100),
3350         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c000),
3351         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000280),
3352         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000),
3353         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Sienna_Cichlid, 0x1ff1ffff, 0x00000500),
3354         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
3355         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
3356         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008),
3357         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x00f80988),
3358         SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG, 0x000001ff, 0x00000020),
3359         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007),
3360         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_CONFIG, 0xe07df47f, 0x00180070),
3361         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER0_SELECT, 0xf0f001ff, 0x00000000),
3362         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER1_SELECT, 0xf0f001ff, 0x00000000),
3363         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER10_SELECT, 0xf0f001ff, 0x00000000),
3364         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER11_SELECT, 0xf0f001ff, 0x00000000),
3365         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER12_SELECT, 0xf0f001ff, 0x00000000),
3366         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER13_SELECT, 0xf0f001ff, 0x00000000),
3367         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER14_SELECT, 0xf0f001ff, 0x00000000),
3368         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER15_SELECT, 0xf0f001ff, 0x00000000),
3369         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER2_SELECT, 0xf0f001ff, 0x00000000),
3370         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER3_SELECT, 0xf0f001ff, 0x00000000),
3371         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER4_SELECT, 0xf0f001ff, 0x00000000),
3372         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER5_SELECT, 0xf0f001ff, 0x00000000),
3373         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER6_SELECT, 0xf0f001ff, 0x00000000),
3374         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER7_SELECT, 0xf0f001ff, 0x00000000),
3375         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER8_SELECT, 0xf0f001ff, 0x00000000),
3376         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER9_SELECT, 0xf0f001ff, 0x00000000),
3377         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX,0xfff7ffff, 0x01030000),
3378         SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffbfffff, 0x00a00000)
3379 };
3380
3381 static const struct soc15_reg_golden golden_settings_gc_10_0_cyan_skillfish[] = {
3382         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000),
3383         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_FAST_CLKS, 0x3fffffff, 0x0000493e),
3384         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_CPF_CLK_CTRL, 0xfcff8fff, 0xf8000100),
3385         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xff7f0fff, 0x3c000100),
3386         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_3, 0xa0000000, 0xa0000000),
3387         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0x00008000, 0x003c8014),
3388         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_DRAM_BURST_CTRL, 0x00000010, 0x00000017),
3389         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0xffffffff, 0xd8d8d8d8),
3390         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_VC5_ENABLE, 0x00000003, 0x00000003),
3391         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0x800007ff, 0x000005ff),
3392         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG, 0xffffffff, 0x20000000),
3393         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000200),
3394         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x04800000),
3395         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_LAST_OF_BURST_CONFIG, 0xffffffff, 0x03860210),
3396         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0x0c1800ff, 0x00000044),
3397         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x00009d00, 0x00008500),
3398         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCMC_VM_CACHEABLE_DRAM_ADDRESS_END, 0xffffffff, 0x000fffff),
3399         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_DRAM_BURST_CTRL, 0x00000010, 0x00000017),
3400         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0xfcfcfcfc, 0xd8d8d8d8),
3401         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77707770, 0x21302130),
3402         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77707770, 0x21302130),
3403         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
3404         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
3405         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CGTT_SCLK_CTRL, 0x10000000, 0x10000100),
3406         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL2, 0xfc02002f, 0x9402002f),
3407         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0x00002188, 0x00000188),
3408         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x08000009, 0x08000009),
3409         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_0, 0xcc3fcc03, 0x842a4c02),
3410         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000000f, 0x00000000),
3411         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0xffff3109, 0xffff3101),
3412         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x00000100, 0x00000130),
3413         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0xffffffff, 0xffffffff),
3414         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0x00030008, 0x01030000),
3415         SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0x00800000, 0x00800000)
3416 };
3417
3418 static const struct soc15_reg_golden golden_settings_gc_10_3_7[] = {
3419         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0xff7f0fff, 0x78000100),
3420         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0x000000ff, 0x000000e4),
3421         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c200),
3422         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000280),
3423         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000),
3424         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0x0c1807ff, 0x00000041),
3425         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff1ffff, 0x00000500),
3426         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0x000000ff, 0x000000e4),
3427         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x32103210),
3428         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x32103210),
3429         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffff),
3430         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffff),
3431         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008),
3432         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x00f80988),
3433         SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG, 0x000001ff, 0x00000020),
3434         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf000003f, 0x01200007),
3435         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
3436         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0xffffffbf, 0x00000820),
3437         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQG_CONFIG, 0x000017ff, 0x00001000),
3438         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSX_DEBUG_1, 0xffffff7f, 0x00010020),
3439         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
3440         SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffffffff, 0x00100000)
3441 };
3442
3443 #define DEFAULT_SH_MEM_CONFIG \
3444         ((SH_MEM_ADDRESS_MODE_64 << SH_MEM_CONFIG__ADDRESS_MODE__SHIFT) | \
3445          (SH_MEM_ALIGNMENT_MODE_UNALIGNED << SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT) | \
3446          (SH_MEM_RETRY_MODE_ALL << SH_MEM_CONFIG__RETRY_MODE__SHIFT) | \
3447          (3 << SH_MEM_CONFIG__INITIAL_INST_PREFETCH__SHIFT))
3448
3449 /* TODO: pending on golden setting value of gb address config */
3450 #define CYAN_SKILLFISH_GB_ADDR_CONFIG_GOLDEN 0x00100044
3451
3452 static void gfx_v10_0_set_ring_funcs(struct amdgpu_device *adev);
3453 static void gfx_v10_0_set_irq_funcs(struct amdgpu_device *adev);
3454 static void gfx_v10_0_set_gds_init(struct amdgpu_device *adev);
3455 static void gfx_v10_0_set_rlc_funcs(struct amdgpu_device *adev);
3456 static int gfx_v10_0_get_cu_info(struct amdgpu_device *adev,
3457                                  struct amdgpu_cu_info *cu_info);
3458 static uint64_t gfx_v10_0_get_gpu_clock_counter(struct amdgpu_device *adev);
3459 static void gfx_v10_0_select_se_sh(struct amdgpu_device *adev, u32 se_num,
3460                                    u32 sh_num, u32 instance);
3461 static u32 gfx_v10_0_get_wgp_active_bitmap_per_sh(struct amdgpu_device *adev);
3462
3463 static int gfx_v10_0_rlc_backdoor_autoload_buffer_init(struct amdgpu_device *adev);
3464 static void gfx_v10_0_rlc_backdoor_autoload_buffer_fini(struct amdgpu_device *adev);
3465 static int gfx_v10_0_rlc_backdoor_autoload_enable(struct amdgpu_device *adev);
3466 static int gfx_v10_0_wait_for_rlc_autoload_complete(struct amdgpu_device *adev);
3467 static void gfx_v10_0_ring_emit_ce_meta(struct amdgpu_ring *ring, bool resume);
3468 static void gfx_v10_0_ring_emit_de_meta(struct amdgpu_ring *ring, bool resume);
3469 static void gfx_v10_0_ring_emit_frame_cntl(struct amdgpu_ring *ring, bool start, bool secure);
3470 static u32 gfx_v10_3_get_disabled_sa(struct amdgpu_device *adev);
3471 static void gfx_v10_3_program_pbb_mode(struct amdgpu_device *adev);
3472 static void gfx_v10_3_set_power_brake_sequence(struct amdgpu_device *adev);
3473
3474 static void gfx10_kiq_set_resources(struct amdgpu_ring *kiq_ring, uint64_t queue_mask)
3475 {
3476         amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_RESOURCES, 6));
3477         amdgpu_ring_write(kiq_ring, PACKET3_SET_RESOURCES_VMID_MASK(0) |
3478                           PACKET3_SET_RESOURCES_QUEUE_TYPE(0)); /* vmid_mask:0 queue_type:0 (KIQ) */
3479         amdgpu_ring_write(kiq_ring, lower_32_bits(queue_mask)); /* queue mask lo */
3480         amdgpu_ring_write(kiq_ring, upper_32_bits(queue_mask)); /* queue mask hi */
3481         amdgpu_ring_write(kiq_ring, 0); /* gws mask lo */
3482         amdgpu_ring_write(kiq_ring, 0); /* gws mask hi */
3483         amdgpu_ring_write(kiq_ring, 0); /* oac mask */
3484         amdgpu_ring_write(kiq_ring, 0); /* gds heap base:0, gds heap size:0 */
3485 }
3486
3487 static void gfx10_kiq_map_queues(struct amdgpu_ring *kiq_ring,
3488                                  struct amdgpu_ring *ring)
3489 {
3490         struct amdgpu_device *adev = kiq_ring->adev;
3491         uint64_t mqd_addr = amdgpu_bo_gpu_offset(ring->mqd_obj);
3492         uint64_t wptr_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
3493         uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0;
3494
3495         amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5));
3496         /* Q_sel:0, vmid:0, vidmem: 1, engine:0, num_Q:1*/
3497         amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */
3498                           PACKET3_MAP_QUEUES_QUEUE_SEL(0) | /* Queue_Sel */
3499                           PACKET3_MAP_QUEUES_VMID(0) | /* VMID */
3500                           PACKET3_MAP_QUEUES_QUEUE(ring->queue) |
3501                           PACKET3_MAP_QUEUES_PIPE(ring->pipe) |
3502                           PACKET3_MAP_QUEUES_ME((ring->me == 1 ? 0 : 1)) |
3503                           PACKET3_MAP_QUEUES_QUEUE_TYPE(0) | /*queue_type: normal compute queue */
3504                           PACKET3_MAP_QUEUES_ALLOC_FORMAT(0) | /* alloc format: all_on_one_pipe */
3505                           PACKET3_MAP_QUEUES_ENGINE_SEL(eng_sel) |
3506                           PACKET3_MAP_QUEUES_NUM_QUEUES(1)); /* num_queues: must be 1 */
3507         amdgpu_ring_write(kiq_ring, PACKET3_MAP_QUEUES_DOORBELL_OFFSET(ring->doorbell_index));
3508         amdgpu_ring_write(kiq_ring, lower_32_bits(mqd_addr));
3509         amdgpu_ring_write(kiq_ring, upper_32_bits(mqd_addr));
3510         amdgpu_ring_write(kiq_ring, lower_32_bits(wptr_addr));
3511         amdgpu_ring_write(kiq_ring, upper_32_bits(wptr_addr));
3512 }
3513
3514 static void gfx10_kiq_unmap_queues(struct amdgpu_ring *kiq_ring,
3515                                    struct amdgpu_ring *ring,
3516                                    enum amdgpu_unmap_queues_action action,
3517                                    u64 gpu_addr, u64 seq)
3518 {
3519         uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0;
3520
3521         amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_UNMAP_QUEUES, 4));
3522         amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */
3523                           PACKET3_UNMAP_QUEUES_ACTION(action) |
3524                           PACKET3_UNMAP_QUEUES_QUEUE_SEL(0) |
3525                           PACKET3_UNMAP_QUEUES_ENGINE_SEL(eng_sel) |
3526                           PACKET3_UNMAP_QUEUES_NUM_QUEUES(1));
3527         amdgpu_ring_write(kiq_ring,
3528                   PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET0(ring->doorbell_index));
3529
3530         if (action == PREEMPT_QUEUES_NO_UNMAP) {
3531                 amdgpu_ring_write(kiq_ring, lower_32_bits(gpu_addr));
3532                 amdgpu_ring_write(kiq_ring, upper_32_bits(gpu_addr));
3533                 amdgpu_ring_write(kiq_ring, seq);
3534         } else {
3535                 amdgpu_ring_write(kiq_ring, 0);
3536                 amdgpu_ring_write(kiq_ring, 0);
3537                 amdgpu_ring_write(kiq_ring, 0);
3538         }
3539 }
3540
3541 static void gfx10_kiq_query_status(struct amdgpu_ring *kiq_ring,
3542                                    struct amdgpu_ring *ring,
3543                                    u64 addr,
3544                                    u64 seq)
3545 {
3546         uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0;
3547
3548         amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_QUERY_STATUS, 5));
3549         amdgpu_ring_write(kiq_ring,
3550                           PACKET3_QUERY_STATUS_CONTEXT_ID(0) |
3551                           PACKET3_QUERY_STATUS_INTERRUPT_SEL(0) |
3552                           PACKET3_QUERY_STATUS_COMMAND(2));
3553         amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */
3554                           PACKET3_QUERY_STATUS_DOORBELL_OFFSET(ring->doorbell_index) |
3555                           PACKET3_QUERY_STATUS_ENG_SEL(eng_sel));
3556         amdgpu_ring_write(kiq_ring, lower_32_bits(addr));
3557         amdgpu_ring_write(kiq_ring, upper_32_bits(addr));
3558         amdgpu_ring_write(kiq_ring, lower_32_bits(seq));
3559         amdgpu_ring_write(kiq_ring, upper_32_bits(seq));
3560 }
3561
3562 static void gfx10_kiq_invalidate_tlbs(struct amdgpu_ring *kiq_ring,
3563                                 uint16_t pasid, uint32_t flush_type,
3564                                 bool all_hub)
3565 {
3566         amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_INVALIDATE_TLBS, 0));
3567         amdgpu_ring_write(kiq_ring,
3568                         PACKET3_INVALIDATE_TLBS_DST_SEL(1) |
3569                         PACKET3_INVALIDATE_TLBS_ALL_HUB(all_hub) |
3570                         PACKET3_INVALIDATE_TLBS_PASID(pasid) |
3571                         PACKET3_INVALIDATE_TLBS_FLUSH_TYPE(flush_type));
3572 }
3573
3574 static const struct kiq_pm4_funcs gfx_v10_0_kiq_pm4_funcs = {
3575         .kiq_set_resources = gfx10_kiq_set_resources,
3576         .kiq_map_queues = gfx10_kiq_map_queues,
3577         .kiq_unmap_queues = gfx10_kiq_unmap_queues,
3578         .kiq_query_status = gfx10_kiq_query_status,
3579         .kiq_invalidate_tlbs = gfx10_kiq_invalidate_tlbs,
3580         .set_resources_size = 8,
3581         .map_queues_size = 7,
3582         .unmap_queues_size = 6,
3583         .query_status_size = 7,
3584         .invalidate_tlbs_size = 2,
3585 };
3586
3587 static void gfx_v10_0_set_kiq_pm4_funcs(struct amdgpu_device *adev)
3588 {
3589         adev->gfx.kiq.pmf = &gfx_v10_0_kiq_pm4_funcs;
3590 }
3591
3592 static void gfx_v10_0_init_spm_golden_registers(struct amdgpu_device *adev)
3593 {
3594         switch (adev->ip_versions[GC_HWIP][0]) {
3595         case IP_VERSION(10, 1, 10):
3596                 soc15_program_register_sequence(adev,
3597                                                 golden_settings_gc_rlc_spm_10_0_nv10,
3598                                                 (const u32)ARRAY_SIZE(golden_settings_gc_rlc_spm_10_0_nv10));
3599                 break;
3600         case IP_VERSION(10, 1, 1):
3601                 soc15_program_register_sequence(adev,
3602                                                 golden_settings_gc_rlc_spm_10_1_nv14,
3603                                                 (const u32)ARRAY_SIZE(golden_settings_gc_rlc_spm_10_1_nv14));
3604                 break;
3605         case IP_VERSION(10, 1, 2):
3606                 soc15_program_register_sequence(adev,
3607                                                 golden_settings_gc_rlc_spm_10_1_2_nv12,
3608                                                 (const u32)ARRAY_SIZE(golden_settings_gc_rlc_spm_10_1_2_nv12));
3609                 break;
3610         default:
3611                 break;
3612         }
3613 }
3614
3615 static void gfx_v10_0_init_golden_registers(struct amdgpu_device *adev)
3616 {
3617         switch (adev->ip_versions[GC_HWIP][0]) {
3618         case IP_VERSION(10, 1, 10):
3619                 soc15_program_register_sequence(adev,
3620                                                 golden_settings_gc_10_1,
3621                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_1));
3622                 soc15_program_register_sequence(adev,
3623                                                 golden_settings_gc_10_0_nv10,
3624                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_0_nv10));
3625                 break;
3626         case IP_VERSION(10, 1, 1):
3627                 soc15_program_register_sequence(adev,
3628                                                 golden_settings_gc_10_1_1,
3629                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_1_1));
3630                 soc15_program_register_sequence(adev,
3631                                                 golden_settings_gc_10_1_nv14,
3632                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_1_nv14));
3633                 break;
3634         case IP_VERSION(10, 1, 2):
3635                 soc15_program_register_sequence(adev,
3636                                                 golden_settings_gc_10_1_2,
3637                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_1_2));
3638                 soc15_program_register_sequence(adev,
3639                                                 golden_settings_gc_10_1_2_nv12,
3640                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_1_2_nv12));
3641                 break;
3642         case IP_VERSION(10, 3, 0):
3643                 soc15_program_register_sequence(adev,
3644                                                 golden_settings_gc_10_3,
3645                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_3));
3646                 soc15_program_register_sequence(adev,
3647                                                 golden_settings_gc_10_3_sienna_cichlid,
3648                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_sienna_cichlid));
3649                 break;
3650         case IP_VERSION(10, 3, 2):
3651                 soc15_program_register_sequence(adev,
3652                                                 golden_settings_gc_10_3_2,
3653                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_2));
3654                 break;
3655         case IP_VERSION(10, 3, 1):
3656                 soc15_program_register_sequence(adev,
3657                                                 golden_settings_gc_10_3_vangogh,
3658                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_vangogh));
3659                 break;
3660         case IP_VERSION(10, 3, 3):
3661                 soc15_program_register_sequence(adev,
3662                                                 golden_settings_gc_10_3_3,
3663                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_3));
3664                 break;
3665         case IP_VERSION(10, 3, 4):
3666                 soc15_program_register_sequence(adev,
3667                                                 golden_settings_gc_10_3_4,
3668                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_4));
3669                 break;
3670         case IP_VERSION(10, 3, 5):
3671                 soc15_program_register_sequence(adev,
3672                                                 golden_settings_gc_10_3_5,
3673                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_5));
3674                 break;
3675         case IP_VERSION(10, 1, 3):
3676         case IP_VERSION(10, 1, 4):
3677                 soc15_program_register_sequence(adev,
3678                                                 golden_settings_gc_10_0_cyan_skillfish,
3679                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_0_cyan_skillfish));
3680                 break;
3681         case IP_VERSION(10, 3, 7):
3682                 soc15_program_register_sequence(adev,
3683                                                 golden_settings_gc_10_3_7,
3684                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_7));
3685                 break;
3686         default:
3687                 break;
3688         }
3689         gfx_v10_0_init_spm_golden_registers(adev);
3690 }
3691
3692 static void gfx_v10_0_scratch_init(struct amdgpu_device *adev)
3693 {
3694         adev->gfx.scratch.num_reg = 8;
3695         adev->gfx.scratch.reg_base = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG0);
3696         adev->gfx.scratch.free_mask = (1u << adev->gfx.scratch.num_reg) - 1;
3697 }
3698
3699 static void gfx_v10_0_write_data_to_reg(struct amdgpu_ring *ring, int eng_sel,
3700                                        bool wc, uint32_t reg, uint32_t val)
3701 {
3702         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
3703         amdgpu_ring_write(ring, WRITE_DATA_ENGINE_SEL(eng_sel) |
3704                           WRITE_DATA_DST_SEL(0) | (wc ? WR_CONFIRM : 0));
3705         amdgpu_ring_write(ring, reg);
3706         amdgpu_ring_write(ring, 0);
3707         amdgpu_ring_write(ring, val);
3708 }
3709
3710 static void gfx_v10_0_wait_reg_mem(struct amdgpu_ring *ring, int eng_sel,
3711                                   int mem_space, int opt, uint32_t addr0,
3712                                   uint32_t addr1, uint32_t ref, uint32_t mask,
3713                                   uint32_t inv)
3714 {
3715         amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
3716         amdgpu_ring_write(ring,
3717                           /* memory (1) or register (0) */
3718                           (WAIT_REG_MEM_MEM_SPACE(mem_space) |
3719                            WAIT_REG_MEM_OPERATION(opt) | /* wait */
3720                            WAIT_REG_MEM_FUNCTION(3) |  /* equal */
3721                            WAIT_REG_MEM_ENGINE(eng_sel)));
3722
3723         if (mem_space)
3724                 BUG_ON(addr0 & 0x3); /* Dword align */
3725         amdgpu_ring_write(ring, addr0);
3726         amdgpu_ring_write(ring, addr1);
3727         amdgpu_ring_write(ring, ref);
3728         amdgpu_ring_write(ring, mask);
3729         amdgpu_ring_write(ring, inv); /* poll interval */
3730 }
3731
3732 static int gfx_v10_0_ring_test_ring(struct amdgpu_ring *ring)
3733 {
3734         struct amdgpu_device *adev = ring->adev;
3735         uint32_t scratch;
3736         uint32_t tmp = 0;
3737         unsigned i;
3738         int r;
3739
3740         r = amdgpu_gfx_scratch_get(adev, &scratch);
3741         if (r) {
3742                 DRM_ERROR("amdgpu: cp failed to get scratch reg (%d).\n", r);
3743                 return r;
3744         }
3745
3746         WREG32(scratch, 0xCAFEDEAD);
3747
3748         r = amdgpu_ring_alloc(ring, 3);
3749         if (r) {
3750                 DRM_ERROR("amdgpu: cp failed to lock ring %d (%d).\n",
3751                           ring->idx, r);
3752                 amdgpu_gfx_scratch_free(adev, scratch);
3753                 return r;
3754         }
3755
3756         amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1));
3757         amdgpu_ring_write(ring, (scratch - PACKET3_SET_UCONFIG_REG_START));
3758         amdgpu_ring_write(ring, 0xDEADBEEF);
3759         amdgpu_ring_commit(ring);
3760
3761         for (i = 0; i < adev->usec_timeout; i++) {
3762                 tmp = RREG32(scratch);
3763                 if (tmp == 0xDEADBEEF)
3764                         break;
3765                 if (amdgpu_emu_mode == 1)
3766                         msleep(1);
3767                 else
3768                         udelay(1);
3769         }
3770
3771         if (i >= adev->usec_timeout)
3772                 r = -ETIMEDOUT;
3773
3774         amdgpu_gfx_scratch_free(adev, scratch);
3775
3776         return r;
3777 }
3778
3779 static int gfx_v10_0_ring_test_ib(struct amdgpu_ring *ring, long timeout)
3780 {
3781         struct amdgpu_device *adev = ring->adev;
3782         struct amdgpu_ib ib;
3783         struct dma_fence *f = NULL;
3784         unsigned index;
3785         uint64_t gpu_addr;
3786         uint32_t tmp;
3787         long r;
3788
3789         r = amdgpu_device_wb_get(adev, &index);
3790         if (r)
3791                 return r;
3792
3793         gpu_addr = adev->wb.gpu_addr + (index * 4);
3794         adev->wb.wb[index] = cpu_to_le32(0xCAFEDEAD);
3795         memset(&ib, 0, sizeof(ib));
3796         r = amdgpu_ib_get(adev, NULL, 16,
3797                                         AMDGPU_IB_POOL_DIRECT, &ib);
3798         if (r)
3799                 goto err1;
3800
3801         ib.ptr[0] = PACKET3(PACKET3_WRITE_DATA, 3);
3802         ib.ptr[1] = WRITE_DATA_DST_SEL(5) | WR_CONFIRM;
3803         ib.ptr[2] = lower_32_bits(gpu_addr);
3804         ib.ptr[3] = upper_32_bits(gpu_addr);
3805         ib.ptr[4] = 0xDEADBEEF;
3806         ib.length_dw = 5;
3807
3808         r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
3809         if (r)
3810                 goto err2;
3811
3812         r = dma_fence_wait_timeout(f, false, timeout);
3813         if (r == 0) {
3814                 r = -ETIMEDOUT;
3815                 goto err2;
3816         } else if (r < 0) {
3817                 goto err2;
3818         }
3819
3820         tmp = adev->wb.wb[index];
3821         if (tmp == 0xDEADBEEF)
3822                 r = 0;
3823         else
3824                 r = -EINVAL;
3825 err2:
3826         amdgpu_ib_free(adev, &ib, NULL);
3827         dma_fence_put(f);
3828 err1:
3829         amdgpu_device_wb_free(adev, index);
3830         return r;
3831 }
3832
3833 static void gfx_v10_0_free_microcode(struct amdgpu_device *adev)
3834 {
3835         release_firmware(adev->gfx.pfp_fw);
3836         adev->gfx.pfp_fw = NULL;
3837         release_firmware(adev->gfx.me_fw);
3838         adev->gfx.me_fw = NULL;
3839         release_firmware(adev->gfx.ce_fw);
3840         adev->gfx.ce_fw = NULL;
3841         release_firmware(adev->gfx.rlc_fw);
3842         adev->gfx.rlc_fw = NULL;
3843         release_firmware(adev->gfx.mec_fw);
3844         adev->gfx.mec_fw = NULL;
3845         release_firmware(adev->gfx.mec2_fw);
3846         adev->gfx.mec2_fw = NULL;
3847
3848         kfree(adev->gfx.rlc.register_list_format);
3849 }
3850
3851 static void gfx_v10_0_check_fw_write_wait(struct amdgpu_device *adev)
3852 {
3853         adev->gfx.cp_fw_write_wait = false;
3854
3855         switch (adev->ip_versions[GC_HWIP][0]) {
3856         case IP_VERSION(10, 1, 10):
3857         case IP_VERSION(10, 1, 2):
3858         case IP_VERSION(10, 1, 1):
3859         case IP_VERSION(10, 1, 3):
3860         case IP_VERSION(10, 1, 4):
3861                 if ((adev->gfx.me_fw_version >= 0x00000046) &&
3862                     (adev->gfx.me_feature_version >= 27) &&
3863                     (adev->gfx.pfp_fw_version >= 0x00000068) &&
3864                     (adev->gfx.pfp_feature_version >= 27) &&
3865                     (adev->gfx.mec_fw_version >= 0x0000005b) &&
3866                     (adev->gfx.mec_feature_version >= 27))
3867                         adev->gfx.cp_fw_write_wait = true;
3868                 break;
3869         case IP_VERSION(10, 3, 0):
3870         case IP_VERSION(10, 3, 2):
3871         case IP_VERSION(10, 3, 1):
3872         case IP_VERSION(10, 3, 4):
3873         case IP_VERSION(10, 3, 5):
3874         case IP_VERSION(10, 3, 3):
3875         case IP_VERSION(10, 3, 7):
3876                 adev->gfx.cp_fw_write_wait = true;
3877                 break;
3878         default:
3879                 break;
3880         }
3881
3882         if (!adev->gfx.cp_fw_write_wait)
3883                 DRM_WARN_ONCE("CP firmware version too old, please update!");
3884 }
3885
3886
3887 static void gfx_v10_0_init_rlc_ext_microcode(struct amdgpu_device *adev)
3888 {
3889         const struct rlc_firmware_header_v2_1 *rlc_hdr;
3890
3891         rlc_hdr = (const struct rlc_firmware_header_v2_1 *)adev->gfx.rlc_fw->data;
3892         adev->gfx.rlc_srlc_fw_version = le32_to_cpu(rlc_hdr->save_restore_list_cntl_ucode_ver);
3893         adev->gfx.rlc_srlc_feature_version = le32_to_cpu(rlc_hdr->save_restore_list_cntl_feature_ver);
3894         adev->gfx.rlc.save_restore_list_cntl_size_bytes = le32_to_cpu(rlc_hdr->save_restore_list_cntl_size_bytes);
3895         adev->gfx.rlc.save_restore_list_cntl = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_list_cntl_offset_bytes);
3896         adev->gfx.rlc_srlg_fw_version = le32_to_cpu(rlc_hdr->save_restore_list_gpm_ucode_ver);
3897         adev->gfx.rlc_srlg_feature_version = le32_to_cpu(rlc_hdr->save_restore_list_gpm_feature_ver);
3898         adev->gfx.rlc.save_restore_list_gpm_size_bytes = le32_to_cpu(rlc_hdr->save_restore_list_gpm_size_bytes);
3899         adev->gfx.rlc.save_restore_list_gpm = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_list_gpm_offset_bytes);
3900         adev->gfx.rlc_srls_fw_version = le32_to_cpu(rlc_hdr->save_restore_list_srm_ucode_ver);
3901         adev->gfx.rlc_srls_feature_version = le32_to_cpu(rlc_hdr->save_restore_list_srm_feature_ver);
3902         adev->gfx.rlc.save_restore_list_srm_size_bytes = le32_to_cpu(rlc_hdr->save_restore_list_srm_size_bytes);
3903         adev->gfx.rlc.save_restore_list_srm = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_list_srm_offset_bytes);
3904         adev->gfx.rlc.reg_list_format_direct_reg_list_length =
3905                         le32_to_cpu(rlc_hdr->reg_list_format_direct_reg_list_length);
3906 }
3907
3908 static void gfx_v10_0_init_rlc_iram_dram_microcode(struct amdgpu_device *adev)
3909 {
3910         const struct rlc_firmware_header_v2_2 *rlc_hdr;
3911
3912         rlc_hdr = (const struct rlc_firmware_header_v2_2 *)adev->gfx.rlc_fw->data;
3913         adev->gfx.rlc.rlc_iram_ucode_size_bytes = le32_to_cpu(rlc_hdr->rlc_iram_ucode_size_bytes);
3914         adev->gfx.rlc.rlc_iram_ucode = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->rlc_iram_ucode_offset_bytes);
3915         adev->gfx.rlc.rlc_dram_ucode_size_bytes = le32_to_cpu(rlc_hdr->rlc_dram_ucode_size_bytes);
3916         adev->gfx.rlc.rlc_dram_ucode = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->rlc_dram_ucode_offset_bytes);
3917 }
3918
3919 static bool gfx_v10_0_navi10_gfxoff_should_enable(struct amdgpu_device *adev)
3920 {
3921         bool ret = false;
3922
3923         switch (adev->pdev->revision) {
3924         case 0xc2:
3925         case 0xc3:
3926                 ret = true;
3927                 break;
3928         default:
3929                 ret = false;
3930                 break;
3931         }
3932
3933         return ret ;
3934 }
3935
3936 static void gfx_v10_0_check_gfxoff_flag(struct amdgpu_device *adev)
3937 {
3938         switch (adev->ip_versions[GC_HWIP][0]) {
3939         case IP_VERSION(10, 1, 10):
3940                 if (!gfx_v10_0_navi10_gfxoff_should_enable(adev))
3941                         adev->pm.pp_feature &= ~PP_GFXOFF_MASK;
3942                 break;
3943         default:
3944                 break;
3945         }
3946 }
3947
3948 static int gfx_v10_0_init_microcode(struct amdgpu_device *adev)
3949 {
3950         const char *chip_name;
3951         char fw_name[40];
3952         char *wks = "";
3953         int err;
3954         struct amdgpu_firmware_info *info = NULL;
3955         const struct common_firmware_header *header = NULL;
3956         const struct gfx_firmware_header_v1_0 *cp_hdr;
3957         const struct rlc_firmware_header_v2_0 *rlc_hdr;
3958         unsigned int *tmp = NULL;
3959         unsigned int i = 0;
3960         uint16_t version_major;
3961         uint16_t version_minor;
3962
3963         DRM_DEBUG("\n");
3964
3965         switch (adev->ip_versions[GC_HWIP][0]) {
3966         case IP_VERSION(10, 1, 10):
3967                 chip_name = "navi10";
3968                 break;
3969         case IP_VERSION(10, 1, 1):
3970                 chip_name = "navi14";
3971                 if (!(adev->pdev->device == 0x7340 &&
3972                       adev->pdev->revision != 0x00))
3973                         wks = "_wks";
3974                 break;
3975         case IP_VERSION(10, 1, 2):
3976                 chip_name = "navi12";
3977                 break;
3978         case IP_VERSION(10, 3, 0):
3979                 chip_name = "sienna_cichlid";
3980                 break;
3981         case IP_VERSION(10, 3, 2):
3982                 chip_name = "navy_flounder";
3983                 break;
3984         case IP_VERSION(10, 3, 1):
3985                 chip_name = "vangogh";
3986                 break;
3987         case IP_VERSION(10, 3, 4):
3988                 chip_name = "dimgrey_cavefish";
3989                 break;
3990         case IP_VERSION(10, 3, 5):
3991                 chip_name = "beige_goby";
3992                 break;
3993         case IP_VERSION(10, 3, 3):
3994                 chip_name = "yellow_carp";
3995                 break;
3996         case IP_VERSION(10, 1, 3):
3997         case IP_VERSION(10, 1, 4):
3998                 if (adev->apu_flags & AMD_APU_IS_CYAN_SKILLFISH2)
3999                         chip_name = "cyan_skillfish2";
4000                 else
4001                         chip_name = "cyan_skillfish";
4002                 break;
4003         case IP_VERSION(10, 3, 7):
4004                 chip_name = "gc_10_3_7";
4005                 break;
4006         default:
4007                 BUG();
4008         }
4009
4010         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_pfp%s.bin", chip_name, wks);
4011         err = request_firmware(&adev->gfx.pfp_fw, fw_name, adev->dev);
4012         if (err)
4013                 goto out;
4014         err = amdgpu_ucode_validate(adev->gfx.pfp_fw);
4015         if (err)
4016                 goto out;
4017         cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data;
4018         adev->gfx.pfp_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
4019         adev->gfx.pfp_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
4020
4021         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_me%s.bin", chip_name, wks);
4022         err = request_firmware(&adev->gfx.me_fw, fw_name, adev->dev);
4023         if (err)
4024                 goto out;
4025         err = amdgpu_ucode_validate(adev->gfx.me_fw);
4026         if (err)
4027                 goto out;
4028         cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data;
4029         adev->gfx.me_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
4030         adev->gfx.me_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
4031
4032         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ce%s.bin", chip_name, wks);
4033         err = request_firmware(&adev->gfx.ce_fw, fw_name, adev->dev);
4034         if (err)
4035                 goto out;
4036         err = amdgpu_ucode_validate(adev->gfx.ce_fw);
4037         if (err)
4038                 goto out;
4039         cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data;
4040         adev->gfx.ce_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
4041         adev->gfx.ce_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
4042
4043         if (!amdgpu_sriov_vf(adev)) {
4044                 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_rlc.bin", chip_name);
4045                 err = request_firmware(&adev->gfx.rlc_fw, fw_name, adev->dev);
4046                 if (err)
4047                         goto out;
4048                 err = amdgpu_ucode_validate(adev->gfx.rlc_fw);
4049                 rlc_hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data;
4050                 version_major = le16_to_cpu(rlc_hdr->header.header_version_major);
4051                 version_minor = le16_to_cpu(rlc_hdr->header.header_version_minor);
4052
4053                 adev->gfx.rlc_fw_version = le32_to_cpu(rlc_hdr->header.ucode_version);
4054                 adev->gfx.rlc_feature_version = le32_to_cpu(rlc_hdr->ucode_feature_version);
4055                 adev->gfx.rlc.save_and_restore_offset =
4056                         le32_to_cpu(rlc_hdr->save_and_restore_offset);
4057                 adev->gfx.rlc.clear_state_descriptor_offset =
4058                         le32_to_cpu(rlc_hdr->clear_state_descriptor_offset);
4059                 adev->gfx.rlc.avail_scratch_ram_locations =
4060                         le32_to_cpu(rlc_hdr->avail_scratch_ram_locations);
4061                 adev->gfx.rlc.reg_restore_list_size =
4062                         le32_to_cpu(rlc_hdr->reg_restore_list_size);
4063                 adev->gfx.rlc.reg_list_format_start =
4064                         le32_to_cpu(rlc_hdr->reg_list_format_start);
4065                 adev->gfx.rlc.reg_list_format_separate_start =
4066                         le32_to_cpu(rlc_hdr->reg_list_format_separate_start);
4067                 adev->gfx.rlc.starting_offsets_start =
4068                         le32_to_cpu(rlc_hdr->starting_offsets_start);
4069                 adev->gfx.rlc.reg_list_format_size_bytes =
4070                         le32_to_cpu(rlc_hdr->reg_list_format_size_bytes);
4071                 adev->gfx.rlc.reg_list_size_bytes =
4072                         le32_to_cpu(rlc_hdr->reg_list_size_bytes);
4073                 adev->gfx.rlc.register_list_format =
4074                         kmalloc(adev->gfx.rlc.reg_list_format_size_bytes +
4075                                         adev->gfx.rlc.reg_list_size_bytes, GFP_KERNEL);
4076                 if (!adev->gfx.rlc.register_list_format) {
4077                         err = -ENOMEM;
4078                         goto out;
4079                 }
4080
4081                 tmp = (unsigned int *)((uintptr_t)rlc_hdr +
4082                                                            le32_to_cpu(rlc_hdr->reg_list_format_array_offset_bytes));
4083                 for (i = 0 ; i < (rlc_hdr->reg_list_format_size_bytes >> 2); i++)
4084                         adev->gfx.rlc.register_list_format[i] = le32_to_cpu(tmp[i]);
4085
4086                 adev->gfx.rlc.register_restore = adev->gfx.rlc.register_list_format + i;
4087
4088                 tmp = (unsigned int *)((uintptr_t)rlc_hdr +
4089                                                            le32_to_cpu(rlc_hdr->reg_list_array_offset_bytes));
4090                 for (i = 0 ; i < (rlc_hdr->reg_list_size_bytes >> 2); i++)
4091                         adev->gfx.rlc.register_restore[i] = le32_to_cpu(tmp[i]);
4092
4093                 if (version_major == 2) {
4094                         if (version_minor >= 1)
4095                                 gfx_v10_0_init_rlc_ext_microcode(adev);
4096                         if (version_minor == 2)
4097                                 gfx_v10_0_init_rlc_iram_dram_microcode(adev);
4098                 }
4099         }
4100
4101         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec%s.bin", chip_name, wks);
4102         err = request_firmware(&adev->gfx.mec_fw, fw_name, adev->dev);
4103         if (err)
4104                 goto out;
4105         err = amdgpu_ucode_validate(adev->gfx.mec_fw);
4106         if (err)
4107                 goto out;
4108         cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
4109         adev->gfx.mec_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
4110         adev->gfx.mec_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
4111
4112         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec2%s.bin", chip_name, wks);
4113         err = request_firmware(&adev->gfx.mec2_fw, fw_name, adev->dev);
4114         if (!err) {
4115                 err = amdgpu_ucode_validate(adev->gfx.mec2_fw);
4116                 if (err)
4117                         goto out;
4118                 cp_hdr = (const struct gfx_firmware_header_v1_0 *)
4119                 adev->gfx.mec2_fw->data;
4120                 adev->gfx.mec2_fw_version =
4121                 le32_to_cpu(cp_hdr->header.ucode_version);
4122                 adev->gfx.mec2_feature_version =
4123                 le32_to_cpu(cp_hdr->ucode_feature_version);
4124         } else {
4125                 err = 0;
4126                 adev->gfx.mec2_fw = NULL;
4127         }
4128
4129         if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
4130                 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_PFP];
4131                 info->ucode_id = AMDGPU_UCODE_ID_CP_PFP;
4132                 info->fw = adev->gfx.pfp_fw;
4133                 header = (const struct common_firmware_header *)info->fw->data;
4134                 adev->firmware.fw_size +=
4135                         ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
4136
4137                 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_ME];
4138                 info->ucode_id = AMDGPU_UCODE_ID_CP_ME;
4139                 info->fw = adev->gfx.me_fw;
4140                 header = (const struct common_firmware_header *)info->fw->data;
4141                 adev->firmware.fw_size +=
4142                         ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
4143
4144                 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_CE];
4145                 info->ucode_id = AMDGPU_UCODE_ID_CP_CE;
4146                 info->fw = adev->gfx.ce_fw;
4147                 header = (const struct common_firmware_header *)info->fw->data;
4148                 adev->firmware.fw_size +=
4149                         ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
4150
4151                 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_G];
4152                 info->ucode_id = AMDGPU_UCODE_ID_RLC_G;
4153                 info->fw = adev->gfx.rlc_fw;
4154                 if (info->fw) {
4155                         header = (const struct common_firmware_header *)info->fw->data;
4156                         adev->firmware.fw_size +=
4157                                 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
4158                 }
4159                 if (adev->gfx.rlc.save_restore_list_cntl_size_bytes &&
4160                     adev->gfx.rlc.save_restore_list_gpm_size_bytes &&
4161                     adev->gfx.rlc.save_restore_list_srm_size_bytes) {
4162                         info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL];
4163                         info->ucode_id = AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL;
4164                         info->fw = adev->gfx.rlc_fw;
4165                         adev->firmware.fw_size +=
4166                                 ALIGN(adev->gfx.rlc.save_restore_list_cntl_size_bytes, PAGE_SIZE);
4167
4168                         info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM];
4169                         info->ucode_id = AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM;
4170                         info->fw = adev->gfx.rlc_fw;
4171                         adev->firmware.fw_size +=
4172                                 ALIGN(adev->gfx.rlc.save_restore_list_gpm_size_bytes, PAGE_SIZE);
4173
4174                         info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM];
4175                         info->ucode_id = AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM;
4176                         info->fw = adev->gfx.rlc_fw;
4177                         adev->firmware.fw_size +=
4178                                 ALIGN(adev->gfx.rlc.save_restore_list_srm_size_bytes, PAGE_SIZE);
4179
4180                         if (adev->gfx.rlc.rlc_iram_ucode_size_bytes &&
4181                             adev->gfx.rlc.rlc_dram_ucode_size_bytes) {
4182                                 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_IRAM];
4183                                 info->ucode_id = AMDGPU_UCODE_ID_RLC_IRAM;
4184                                 info->fw = adev->gfx.rlc_fw;
4185                                 adev->firmware.fw_size +=
4186                                         ALIGN(adev->gfx.rlc.rlc_iram_ucode_size_bytes, PAGE_SIZE);
4187
4188                                 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_DRAM];
4189                                 info->ucode_id = AMDGPU_UCODE_ID_RLC_DRAM;
4190                                 info->fw = adev->gfx.rlc_fw;
4191                                 adev->firmware.fw_size +=
4192                                         ALIGN(adev->gfx.rlc.rlc_dram_ucode_size_bytes, PAGE_SIZE);
4193                         }
4194                 }
4195
4196                 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC1];
4197                 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC1;
4198                 info->fw = adev->gfx.mec_fw;
4199                 header = (const struct common_firmware_header *)info->fw->data;
4200                 cp_hdr = (const struct gfx_firmware_header_v1_0 *)info->fw->data;
4201                 adev->firmware.fw_size +=
4202                         ALIGN(le32_to_cpu(header->ucode_size_bytes) -
4203                               le32_to_cpu(cp_hdr->jt_size) * 4, PAGE_SIZE);
4204
4205                 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC1_JT];
4206                 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC1_JT;
4207                 info->fw = adev->gfx.mec_fw;
4208                 adev->firmware.fw_size +=
4209                         ALIGN(le32_to_cpu(cp_hdr->jt_size) * 4, PAGE_SIZE);
4210
4211                 if (adev->gfx.mec2_fw) {
4212                         info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC2];
4213                         info->ucode_id = AMDGPU_UCODE_ID_CP_MEC2;
4214                         info->fw = adev->gfx.mec2_fw;
4215                         header = (const struct common_firmware_header *)info->fw->data;
4216                         cp_hdr = (const struct gfx_firmware_header_v1_0 *)info->fw->data;
4217                         adev->firmware.fw_size +=
4218                                 ALIGN(le32_to_cpu(header->ucode_size_bytes) -
4219                                       le32_to_cpu(cp_hdr->jt_size) * 4,
4220                                       PAGE_SIZE);
4221                         info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC2_JT];
4222                         info->ucode_id = AMDGPU_UCODE_ID_CP_MEC2_JT;
4223                         info->fw = adev->gfx.mec2_fw;
4224                         adev->firmware.fw_size +=
4225                                 ALIGN(le32_to_cpu(cp_hdr->jt_size) * 4,
4226                                       PAGE_SIZE);
4227                 }
4228         }
4229
4230         gfx_v10_0_check_fw_write_wait(adev);
4231 out:
4232         if (err) {
4233                 dev_err(adev->dev,
4234                         "gfx10: Failed to load firmware \"%s\"\n",
4235                         fw_name);
4236                 release_firmware(adev->gfx.pfp_fw);
4237                 adev->gfx.pfp_fw = NULL;
4238                 release_firmware(adev->gfx.me_fw);
4239                 adev->gfx.me_fw = NULL;
4240                 release_firmware(adev->gfx.ce_fw);
4241                 adev->gfx.ce_fw = NULL;
4242                 release_firmware(adev->gfx.rlc_fw);
4243                 adev->gfx.rlc_fw = NULL;
4244                 release_firmware(adev->gfx.mec_fw);
4245                 adev->gfx.mec_fw = NULL;
4246                 release_firmware(adev->gfx.mec2_fw);
4247                 adev->gfx.mec2_fw = NULL;
4248         }
4249
4250         gfx_v10_0_check_gfxoff_flag(adev);
4251
4252         return err;
4253 }
4254
4255 static u32 gfx_v10_0_get_csb_size(struct amdgpu_device *adev)
4256 {
4257         u32 count = 0;
4258         const struct cs_section_def *sect = NULL;
4259         const struct cs_extent_def *ext = NULL;
4260
4261         /* begin clear state */
4262         count += 2;
4263         /* context control state */
4264         count += 3;
4265
4266         for (sect = gfx10_cs_data; sect->section != NULL; ++sect) {
4267                 for (ext = sect->section; ext->extent != NULL; ++ext) {
4268                         if (sect->id == SECT_CONTEXT)
4269                                 count += 2 + ext->reg_count;
4270                         else
4271                                 return 0;
4272                 }
4273         }
4274
4275         /* set PA_SC_TILE_STEERING_OVERRIDE */
4276         count += 3;
4277         /* end clear state */
4278         count += 2;
4279         /* clear state */
4280         count += 2;
4281
4282         return count;
4283 }
4284
4285 static void gfx_v10_0_get_csb_buffer(struct amdgpu_device *adev,
4286                                     volatile u32 *buffer)
4287 {
4288         u32 count = 0, i;
4289         const struct cs_section_def *sect = NULL;
4290         const struct cs_extent_def *ext = NULL;
4291         int ctx_reg_offset;
4292
4293         if (adev->gfx.rlc.cs_data == NULL)
4294                 return;
4295         if (buffer == NULL)
4296                 return;
4297
4298         buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));
4299         buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
4300
4301         buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CONTEXT_CONTROL, 1));
4302         buffer[count++] = cpu_to_le32(0x80000000);
4303         buffer[count++] = cpu_to_le32(0x80000000);
4304
4305         for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) {
4306                 for (ext = sect->section; ext->extent != NULL; ++ext) {
4307                         if (sect->id == SECT_CONTEXT) {
4308                                 buffer[count++] =
4309                                         cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count));
4310                                 buffer[count++] = cpu_to_le32(ext->reg_index -
4311                                                 PACKET3_SET_CONTEXT_REG_START);
4312                                 for (i = 0; i < ext->reg_count; i++)
4313                                         buffer[count++] = cpu_to_le32(ext->extent[i]);
4314                         } else {
4315                                 return;
4316                         }
4317                 }
4318         }
4319
4320         ctx_reg_offset =
4321                 SOC15_REG_OFFSET(GC, 0, mmPA_SC_TILE_STEERING_OVERRIDE) - PACKET3_SET_CONTEXT_REG_START;
4322         buffer[count++] = cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, 1));
4323         buffer[count++] = cpu_to_le32(ctx_reg_offset);
4324         buffer[count++] = cpu_to_le32(adev->gfx.config.pa_sc_tile_steering_override);
4325
4326         buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));
4327         buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_END_CLEAR_STATE);
4328
4329         buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CLEAR_STATE, 0));
4330         buffer[count++] = cpu_to_le32(0);
4331 }
4332
4333 static void gfx_v10_0_rlc_fini(struct amdgpu_device *adev)
4334 {
4335         /* clear state block */
4336         amdgpu_bo_free_kernel(&adev->gfx.rlc.clear_state_obj,
4337                         &adev->gfx.rlc.clear_state_gpu_addr,
4338                         (void **)&adev->gfx.rlc.cs_ptr);
4339
4340         /* jump table block */
4341         amdgpu_bo_free_kernel(&adev->gfx.rlc.cp_table_obj,
4342                         &adev->gfx.rlc.cp_table_gpu_addr,
4343                         (void **)&adev->gfx.rlc.cp_table_ptr);
4344 }
4345
4346 static void gfx_v10_0_init_rlcg_reg_access_ctrl(struct amdgpu_device *adev)
4347 {
4348         struct amdgpu_rlcg_reg_access_ctrl *reg_access_ctrl;
4349
4350         reg_access_ctrl = &adev->gfx.rlc.reg_access_ctrl;
4351         reg_access_ctrl->scratch_reg0 = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG0);
4352         reg_access_ctrl->scratch_reg1 = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG1);
4353         reg_access_ctrl->scratch_reg2 = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG2);
4354         reg_access_ctrl->scratch_reg3 = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG3);
4355         reg_access_ctrl->grbm_cntl = SOC15_REG_OFFSET(GC, 0, mmGRBM_GFX_CNTL);
4356         reg_access_ctrl->grbm_idx = SOC15_REG_OFFSET(GC, 0, mmGRBM_GFX_INDEX);
4357         switch (adev->ip_versions[GC_HWIP][0]) {
4358                 case IP_VERSION(10, 3, 0):
4359                         reg_access_ctrl->spare_int =
4360                                 SOC15_REG_OFFSET(GC, 0, mmRLC_SPARE_INT_0_Sienna_Cichlid);
4361                         break;
4362                 default:
4363                         reg_access_ctrl->spare_int =
4364                                 SOC15_REG_OFFSET(GC, 0, mmRLC_SPARE_INT);
4365                         break;
4366         }
4367         adev->gfx.rlc.rlcg_reg_access_supported = true;
4368 }
4369
4370 static int gfx_v10_0_rlc_init(struct amdgpu_device *adev)
4371 {
4372         const struct cs_section_def *cs_data;
4373         int r;
4374
4375         adev->gfx.rlc.cs_data = gfx10_cs_data;
4376
4377         cs_data = adev->gfx.rlc.cs_data;
4378
4379         if (cs_data) {
4380                 /* init clear state block */
4381                 r = amdgpu_gfx_rlc_init_csb(adev);
4382                 if (r)
4383                         return r;
4384         }
4385
4386         /* init spm vmid with 0xf */
4387         if (adev->gfx.rlc.funcs->update_spm_vmid)
4388                 adev->gfx.rlc.funcs->update_spm_vmid(adev, 0xf);
4389
4390
4391         return 0;
4392 }
4393
4394 static void gfx_v10_0_mec_fini(struct amdgpu_device *adev)
4395 {
4396         amdgpu_bo_free_kernel(&adev->gfx.mec.hpd_eop_obj, NULL, NULL);
4397         amdgpu_bo_free_kernel(&adev->gfx.mec.mec_fw_obj, NULL, NULL);
4398 }
4399
4400 static int gfx_v10_0_me_init(struct amdgpu_device *adev)
4401 {
4402         int r;
4403
4404         bitmap_zero(adev->gfx.me.queue_bitmap, AMDGPU_MAX_GFX_QUEUES);
4405
4406         amdgpu_gfx_graphics_queue_acquire(adev);
4407
4408         r = gfx_v10_0_init_microcode(adev);
4409         if (r)
4410                 DRM_ERROR("Failed to load gfx firmware!\n");
4411
4412         return r;
4413 }
4414
4415 static int gfx_v10_0_mec_init(struct amdgpu_device *adev)
4416 {
4417         int r;
4418         u32 *hpd;
4419         const __le32 *fw_data = NULL;
4420         unsigned fw_size;
4421         u32 *fw = NULL;
4422         size_t mec_hpd_size;
4423
4424         const struct gfx_firmware_header_v1_0 *mec_hdr = NULL;
4425
4426         bitmap_zero(adev->gfx.mec.queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES);
4427
4428         /* take ownership of the relevant compute queues */
4429         amdgpu_gfx_compute_queue_acquire(adev);
4430         mec_hpd_size = adev->gfx.num_compute_rings * GFX10_MEC_HPD_SIZE;
4431
4432         if (mec_hpd_size) {
4433                 r = amdgpu_bo_create_reserved(adev, mec_hpd_size, PAGE_SIZE,
4434                                               AMDGPU_GEM_DOMAIN_GTT,
4435                                               &adev->gfx.mec.hpd_eop_obj,
4436                                               &adev->gfx.mec.hpd_eop_gpu_addr,
4437                                               (void **)&hpd);
4438                 if (r) {
4439                         dev_warn(adev->dev, "(%d) create HDP EOP bo failed\n", r);
4440                         gfx_v10_0_mec_fini(adev);
4441                         return r;
4442                 }
4443
4444                 memset(hpd, 0, mec_hpd_size);
4445
4446                 amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj);
4447                 amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj);
4448         }
4449
4450         if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
4451                 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
4452
4453                 fw_data = (const __le32 *) (adev->gfx.mec_fw->data +
4454                          le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes));
4455                 fw_size = le32_to_cpu(mec_hdr->header.ucode_size_bytes);
4456
4457                 r = amdgpu_bo_create_reserved(adev, mec_hdr->header.ucode_size_bytes,
4458                                               PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,
4459                                               &adev->gfx.mec.mec_fw_obj,
4460                                               &adev->gfx.mec.mec_fw_gpu_addr,
4461                                               (void **)&fw);
4462                 if (r) {
4463                         dev_err(adev->dev, "(%d) failed to create mec fw bo\n", r);
4464                         gfx_v10_0_mec_fini(adev);
4465                         return r;
4466                 }
4467
4468                 memcpy(fw, fw_data, fw_size);
4469
4470                 amdgpu_bo_kunmap(adev->gfx.mec.mec_fw_obj);
4471                 amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_obj);
4472         }
4473
4474         return 0;
4475 }
4476
4477 static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t wave, uint32_t address)
4478 {
4479         WREG32_SOC15(GC, 0, mmSQ_IND_INDEX,
4480                 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) |
4481                 (address << SQ_IND_INDEX__INDEX__SHIFT));
4482         return RREG32_SOC15(GC, 0, mmSQ_IND_DATA);
4483 }
4484
4485 static void wave_read_regs(struct amdgpu_device *adev, uint32_t wave,
4486                            uint32_t thread, uint32_t regno,
4487                            uint32_t num, uint32_t *out)
4488 {
4489         WREG32_SOC15(GC, 0, mmSQ_IND_INDEX,
4490                 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) |
4491                 (regno << SQ_IND_INDEX__INDEX__SHIFT) |
4492                 (thread << SQ_IND_INDEX__WORKITEM_ID__SHIFT) |
4493                 (SQ_IND_INDEX__AUTO_INCR_MASK));
4494         while (num--)
4495                 *(out++) = RREG32_SOC15(GC, 0, mmSQ_IND_DATA);
4496 }
4497
4498 static void gfx_v10_0_read_wave_data(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t *dst, int *no_fields)
4499 {
4500         /* in gfx10 the SIMD_ID is specified as part of the INSTANCE
4501          * field when performing a select_se_sh so it should be
4502          * zero here */
4503         WARN_ON(simd != 0);
4504
4505         /* type 2 wave data */
4506         dst[(*no_fields)++] = 2;
4507         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_STATUS);
4508         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_PC_LO);
4509         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_PC_HI);
4510         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXEC_LO);
4511         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXEC_HI);
4512         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_HW_ID1);
4513         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_HW_ID2);
4514         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_INST_DW0);
4515         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_GPR_ALLOC);
4516         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_LDS_ALLOC);
4517         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_TRAPSTS);
4518         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_STS);
4519         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_STS2);
4520         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_DBG1);
4521         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_M0);
4522         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_MODE);
4523 }
4524
4525 static void gfx_v10_0_read_wave_sgprs(struct amdgpu_device *adev, uint32_t simd,
4526                                      uint32_t wave, uint32_t start,
4527                                      uint32_t size, uint32_t *dst)
4528 {
4529         WARN_ON(simd != 0);
4530
4531         wave_read_regs(
4532                 adev, wave, 0, start + SQIND_WAVE_SGPRS_OFFSET, size,
4533                 dst);
4534 }
4535
4536 static void gfx_v10_0_read_wave_vgprs(struct amdgpu_device *adev, uint32_t simd,
4537                                       uint32_t wave, uint32_t thread,
4538                                       uint32_t start, uint32_t size,
4539                                       uint32_t *dst)
4540 {
4541         wave_read_regs(
4542                 adev, wave, thread,
4543                 start + SQIND_WAVE_VGPRS_OFFSET, size, dst);
4544 }
4545
4546 static void gfx_v10_0_select_me_pipe_q(struct amdgpu_device *adev,
4547                                        u32 me, u32 pipe, u32 q, u32 vm)
4548 {
4549         nv_grbm_select(adev, me, pipe, q, vm);
4550 }
4551
4552 static void gfx_v10_0_update_perfmon_mgcg(struct amdgpu_device *adev,
4553                                           bool enable)
4554 {
4555         uint32_t data, def;
4556
4557         data = def = RREG32_SOC15(GC, 0, mmRLC_PERFMON_CLK_CNTL);
4558
4559         if (enable)
4560                 data |= RLC_PERFMON_CLK_CNTL__PERFMON_CLOCK_STATE_MASK;
4561         else
4562                 data &= ~RLC_PERFMON_CLK_CNTL__PERFMON_CLOCK_STATE_MASK;
4563
4564         if (data != def)
4565                 WREG32_SOC15(GC, 0, mmRLC_PERFMON_CLK_CNTL, data);
4566 }
4567
4568 static const struct amdgpu_gfx_funcs gfx_v10_0_gfx_funcs = {
4569         .get_gpu_clock_counter = &gfx_v10_0_get_gpu_clock_counter,
4570         .select_se_sh = &gfx_v10_0_select_se_sh,
4571         .read_wave_data = &gfx_v10_0_read_wave_data,
4572         .read_wave_sgprs = &gfx_v10_0_read_wave_sgprs,
4573         .read_wave_vgprs = &gfx_v10_0_read_wave_vgprs,
4574         .select_me_pipe_q = &gfx_v10_0_select_me_pipe_q,
4575         .init_spm_golden = &gfx_v10_0_init_spm_golden_registers,
4576         .update_perfmon_mgcg = &gfx_v10_0_update_perfmon_mgcg,
4577 };
4578
4579 static void gfx_v10_0_gpu_early_init(struct amdgpu_device *adev)
4580 {
4581         u32 gb_addr_config;
4582
4583         adev->gfx.funcs = &gfx_v10_0_gfx_funcs;
4584
4585         switch (adev->ip_versions[GC_HWIP][0]) {
4586         case IP_VERSION(10, 1, 10):
4587         case IP_VERSION(10, 1, 1):
4588         case IP_VERSION(10, 1, 2):
4589                 adev->gfx.config.max_hw_contexts = 8;
4590                 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
4591                 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
4592                 adev->gfx.config.sc_hiz_tile_fifo_size = 0;
4593                 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0;
4594                 gb_addr_config = RREG32_SOC15(GC, 0, mmGB_ADDR_CONFIG);
4595                 break;
4596         case IP_VERSION(10, 3, 0):
4597         case IP_VERSION(10, 3, 2):
4598         case IP_VERSION(10, 3, 1):
4599         case IP_VERSION(10, 3, 4):
4600         case IP_VERSION(10, 3, 5):
4601         case IP_VERSION(10, 3, 3):
4602         case IP_VERSION(10, 3, 7):
4603                 adev->gfx.config.max_hw_contexts = 8;
4604                 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
4605                 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
4606                 adev->gfx.config.sc_hiz_tile_fifo_size = 0;
4607                 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0;
4608                 gb_addr_config = RREG32_SOC15(GC, 0, mmGB_ADDR_CONFIG);
4609                 adev->gfx.config.gb_addr_config_fields.num_pkrs =
4610                         1 << REG_GET_FIELD(gb_addr_config, GB_ADDR_CONFIG, NUM_PKRS);
4611                 break;
4612         case IP_VERSION(10, 1, 3):
4613         case IP_VERSION(10, 1, 4):
4614                 adev->gfx.config.max_hw_contexts = 8;
4615                 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
4616                 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
4617                 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
4618                 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0;
4619                 gb_addr_config = CYAN_SKILLFISH_GB_ADDR_CONFIG_GOLDEN;
4620                 break;
4621         default:
4622                 BUG();
4623                 break;
4624         }
4625
4626         adev->gfx.config.gb_addr_config = gb_addr_config;
4627
4628         adev->gfx.config.gb_addr_config_fields.num_pipes = 1 <<
4629                         REG_GET_FIELD(adev->gfx.config.gb_addr_config,
4630                                       GB_ADDR_CONFIG, NUM_PIPES);
4631
4632         adev->gfx.config.max_tile_pipes =
4633                 adev->gfx.config.gb_addr_config_fields.num_pipes;
4634
4635         adev->gfx.config.gb_addr_config_fields.max_compress_frags = 1 <<
4636                         REG_GET_FIELD(adev->gfx.config.gb_addr_config,
4637                                       GB_ADDR_CONFIG, MAX_COMPRESSED_FRAGS);
4638         adev->gfx.config.gb_addr_config_fields.num_rb_per_se = 1 <<
4639                         REG_GET_FIELD(adev->gfx.config.gb_addr_config,
4640                                       GB_ADDR_CONFIG, NUM_RB_PER_SE);
4641         adev->gfx.config.gb_addr_config_fields.num_se = 1 <<
4642                         REG_GET_FIELD(adev->gfx.config.gb_addr_config,
4643                                       GB_ADDR_CONFIG, NUM_SHADER_ENGINES);
4644         adev->gfx.config.gb_addr_config_fields.pipe_interleave_size = 1 << (8 +
4645                         REG_GET_FIELD(adev->gfx.config.gb_addr_config,
4646                                       GB_ADDR_CONFIG, PIPE_INTERLEAVE_SIZE));
4647 }
4648
4649 static int gfx_v10_0_gfx_ring_init(struct amdgpu_device *adev, int ring_id,
4650                                    int me, int pipe, int queue)
4651 {
4652         int r;
4653         struct amdgpu_ring *ring;
4654         unsigned int irq_type;
4655
4656         ring = &adev->gfx.gfx_ring[ring_id];
4657
4658         ring->me = me;
4659         ring->pipe = pipe;
4660         ring->queue = queue;
4661
4662         ring->ring_obj = NULL;
4663         ring->use_doorbell = true;
4664
4665         if (!ring_id)
4666                 ring->doorbell_index = adev->doorbell_index.gfx_ring0 << 1;
4667         else
4668                 ring->doorbell_index = adev->doorbell_index.gfx_ring1 << 1;
4669         sprintf(ring->name, "gfx_%d.%d.%d", ring->me, ring->pipe, ring->queue);
4670
4671         irq_type = AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP + ring->pipe;
4672         r = amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, irq_type,
4673                              AMDGPU_RING_PRIO_DEFAULT, NULL);
4674         if (r)
4675                 return r;
4676         return 0;
4677 }
4678
4679 static int gfx_v10_0_compute_ring_init(struct amdgpu_device *adev, int ring_id,
4680                                        int mec, int pipe, int queue)
4681 {
4682         int r;
4683         unsigned irq_type;
4684         struct amdgpu_ring *ring;
4685         unsigned int hw_prio;
4686
4687         ring = &adev->gfx.compute_ring[ring_id];
4688
4689         /* mec0 is me1 */
4690         ring->me = mec + 1;
4691         ring->pipe = pipe;
4692         ring->queue = queue;
4693
4694         ring->ring_obj = NULL;
4695         ring->use_doorbell = true;
4696         ring->doorbell_index = (adev->doorbell_index.mec_ring0 + ring_id) << 1;
4697         ring->eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr
4698                                 + (ring_id * GFX10_MEC_HPD_SIZE);
4699         sprintf(ring->name, "comp_%d.%d.%d", ring->me, ring->pipe, ring->queue);
4700
4701         irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP
4702                 + ((ring->me - 1) * adev->gfx.mec.num_pipe_per_mec)
4703                 + ring->pipe;
4704         hw_prio = amdgpu_gfx_is_high_priority_compute_queue(adev, ring) ?
4705                         AMDGPU_GFX_PIPE_PRIO_HIGH : AMDGPU_GFX_PIPE_PRIO_NORMAL;
4706         /* type-2 packets are deprecated on MEC, use type-3 instead */
4707         r = amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, irq_type,
4708                              hw_prio, NULL);
4709         if (r)
4710                 return r;
4711
4712         return 0;
4713 }
4714
4715 static int gfx_v10_0_sw_init(void *handle)
4716 {
4717         int i, j, k, r, ring_id = 0;
4718         struct amdgpu_kiq *kiq;
4719         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4720
4721         switch (adev->ip_versions[GC_HWIP][0]) {
4722         case IP_VERSION(10, 1, 10):
4723         case IP_VERSION(10, 1, 1):
4724         case IP_VERSION(10, 1, 2):
4725         case IP_VERSION(10, 1, 3):
4726         case IP_VERSION(10, 1, 4):
4727                 adev->gfx.me.num_me = 1;
4728                 adev->gfx.me.num_pipe_per_me = 1;
4729                 adev->gfx.me.num_queue_per_pipe = 1;
4730                 adev->gfx.mec.num_mec = 2;
4731                 adev->gfx.mec.num_pipe_per_mec = 4;
4732                 adev->gfx.mec.num_queue_per_pipe = 8;
4733                 break;
4734         case IP_VERSION(10, 3, 0):
4735         case IP_VERSION(10, 3, 2):
4736         case IP_VERSION(10, 3, 1):
4737         case IP_VERSION(10, 3, 4):
4738         case IP_VERSION(10, 3, 5):
4739         case IP_VERSION(10, 3, 3):
4740         case IP_VERSION(10, 3, 7):
4741                 adev->gfx.me.num_me = 1;
4742                 adev->gfx.me.num_pipe_per_me = 1;
4743                 adev->gfx.me.num_queue_per_pipe = 1;
4744                 adev->gfx.mec.num_mec = 2;
4745                 adev->gfx.mec.num_pipe_per_mec = 4;
4746                 adev->gfx.mec.num_queue_per_pipe = 4;
4747                 break;
4748         default:
4749                 adev->gfx.me.num_me = 1;
4750                 adev->gfx.me.num_pipe_per_me = 1;
4751                 adev->gfx.me.num_queue_per_pipe = 1;
4752                 adev->gfx.mec.num_mec = 1;
4753                 adev->gfx.mec.num_pipe_per_mec = 4;
4754                 adev->gfx.mec.num_queue_per_pipe = 8;
4755                 break;
4756         }
4757
4758         /* KIQ event */
4759         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP,
4760                               GFX_10_1__SRCID__CP_IB2_INTERRUPT_PKT,
4761                               &adev->gfx.kiq.irq);
4762         if (r)
4763                 return r;
4764
4765         /* EOP Event */
4766         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP,
4767                               GFX_10_1__SRCID__CP_EOP_INTERRUPT,
4768                               &adev->gfx.eop_irq);
4769         if (r)
4770                 return r;
4771
4772         /* Privileged reg */
4773         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_10_1__SRCID__CP_PRIV_REG_FAULT,
4774                               &adev->gfx.priv_reg_irq);
4775         if (r)
4776                 return r;
4777
4778         /* Privileged inst */
4779         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_10_1__SRCID__CP_PRIV_INSTR_FAULT,
4780                               &adev->gfx.priv_inst_irq);
4781         if (r)
4782                 return r;
4783
4784         adev->gfx.gfx_current_status = AMDGPU_GFX_NORMAL_MODE;
4785
4786         gfx_v10_0_scratch_init(adev);
4787
4788         r = gfx_v10_0_me_init(adev);
4789         if (r)
4790                 return r;
4791
4792         if (adev->gfx.rlc.funcs) {
4793                 if (adev->gfx.rlc.funcs->init) {
4794                         r = adev->gfx.rlc.funcs->init(adev);
4795                         if (r) {
4796                                 dev_err(adev->dev, "Failed to init rlc BOs!\n");
4797                                 return r;
4798                         }
4799                 }
4800         }
4801
4802         r = gfx_v10_0_mec_init(adev);
4803         if (r) {
4804                 DRM_ERROR("Failed to init MEC BOs!\n");
4805                 return r;
4806         }
4807
4808         /* set up the gfx ring */
4809         for (i = 0; i < adev->gfx.me.num_me; i++) {
4810                 for (j = 0; j < adev->gfx.me.num_queue_per_pipe; j++) {
4811                         for (k = 0; k < adev->gfx.me.num_pipe_per_me; k++) {
4812                                 if (!amdgpu_gfx_is_me_queue_enabled(adev, i, k, j))
4813                                         continue;
4814
4815                                 r = gfx_v10_0_gfx_ring_init(adev, ring_id,
4816                                                             i, k, j);
4817                                 if (r)
4818                                         return r;
4819                                 ring_id++;
4820                         }
4821                 }
4822         }
4823
4824         ring_id = 0;
4825         /* set up the compute queues - allocate horizontally across pipes */
4826         for (i = 0; i < adev->gfx.mec.num_mec; ++i) {
4827                 for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) {
4828                         for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) {
4829                                 if (!amdgpu_gfx_is_mec_queue_enabled(adev, i, k,
4830                                                                      j))
4831                                         continue;
4832
4833                                 r = gfx_v10_0_compute_ring_init(adev, ring_id,
4834                                                                 i, k, j);
4835                                 if (r)
4836                                         return r;
4837
4838                                 ring_id++;
4839                         }
4840                 }
4841         }
4842
4843         r = amdgpu_gfx_kiq_init(adev, GFX10_MEC_HPD_SIZE);
4844         if (r) {
4845                 DRM_ERROR("Failed to init KIQ BOs!\n");
4846                 return r;
4847         }
4848
4849         kiq = &adev->gfx.kiq;
4850         r = amdgpu_gfx_kiq_init_ring(adev, &kiq->ring, &kiq->irq);
4851         if (r)
4852                 return r;
4853
4854         r = amdgpu_gfx_mqd_sw_init(adev, sizeof(struct v10_compute_mqd));
4855         if (r)
4856                 return r;
4857
4858         /* allocate visible FB for rlc auto-loading fw */
4859         if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) {
4860                 r = gfx_v10_0_rlc_backdoor_autoload_buffer_init(adev);
4861                 if (r)
4862                         return r;
4863         }
4864
4865         adev->gfx.ce_ram_size = F32_CE_PROGRAM_RAM_SIZE;
4866
4867         gfx_v10_0_gpu_early_init(adev);
4868
4869         return 0;
4870 }
4871
4872 static void gfx_v10_0_pfp_fini(struct amdgpu_device *adev)
4873 {
4874         amdgpu_bo_free_kernel(&adev->gfx.pfp.pfp_fw_obj,
4875                               &adev->gfx.pfp.pfp_fw_gpu_addr,
4876                               (void **)&adev->gfx.pfp.pfp_fw_ptr);
4877 }
4878
4879 static void gfx_v10_0_ce_fini(struct amdgpu_device *adev)
4880 {
4881         amdgpu_bo_free_kernel(&adev->gfx.ce.ce_fw_obj,
4882                               &adev->gfx.ce.ce_fw_gpu_addr,
4883                               (void **)&adev->gfx.ce.ce_fw_ptr);
4884 }
4885
4886 static void gfx_v10_0_me_fini(struct amdgpu_device *adev)
4887 {
4888         amdgpu_bo_free_kernel(&adev->gfx.me.me_fw_obj,
4889                               &adev->gfx.me.me_fw_gpu_addr,
4890                               (void **)&adev->gfx.me.me_fw_ptr);
4891 }
4892
4893 static int gfx_v10_0_sw_fini(void *handle)
4894 {
4895         int i;
4896         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4897
4898         for (i = 0; i < adev->gfx.num_gfx_rings; i++)
4899                 amdgpu_ring_fini(&adev->gfx.gfx_ring[i]);
4900         for (i = 0; i < adev->gfx.num_compute_rings; i++)
4901                 amdgpu_ring_fini(&adev->gfx.compute_ring[i]);
4902
4903         amdgpu_gfx_mqd_sw_fini(adev);
4904         amdgpu_gfx_kiq_free_ring(&adev->gfx.kiq.ring);
4905         amdgpu_gfx_kiq_fini(adev);
4906
4907         gfx_v10_0_pfp_fini(adev);
4908         gfx_v10_0_ce_fini(adev);
4909         gfx_v10_0_me_fini(adev);
4910         gfx_v10_0_rlc_fini(adev);
4911         gfx_v10_0_mec_fini(adev);
4912
4913         if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO)
4914                 gfx_v10_0_rlc_backdoor_autoload_buffer_fini(adev);
4915
4916         gfx_v10_0_free_microcode(adev);
4917
4918         return 0;
4919 }
4920
4921 static void gfx_v10_0_select_se_sh(struct amdgpu_device *adev, u32 se_num,
4922                                    u32 sh_num, u32 instance)
4923 {
4924         u32 data;
4925
4926         if (instance == 0xffffffff)
4927                 data = REG_SET_FIELD(0, GRBM_GFX_INDEX,
4928                                      INSTANCE_BROADCAST_WRITES, 1);
4929         else
4930                 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_INDEX,
4931                                      instance);
4932
4933         if (se_num == 0xffffffff)
4934                 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_BROADCAST_WRITES,
4935                                      1);
4936         else
4937                 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num);
4938
4939         if (sh_num == 0xffffffff)
4940                 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SA_BROADCAST_WRITES,
4941                                      1);
4942         else
4943                 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SA_INDEX, sh_num);
4944
4945         WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, data);
4946 }
4947
4948 static u32 gfx_v10_0_get_rb_active_bitmap(struct amdgpu_device *adev)
4949 {
4950         u32 data, mask;
4951
4952         data = RREG32_SOC15(GC, 0, mmCC_RB_BACKEND_DISABLE);
4953         data |= RREG32_SOC15(GC, 0, mmGC_USER_RB_BACKEND_DISABLE);
4954
4955         data &= CC_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK;
4956         data >>= GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT;
4957
4958         mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_backends_per_se /
4959                                          adev->gfx.config.max_sh_per_se);
4960
4961         return (~data) & mask;
4962 }
4963
4964 static void gfx_v10_0_setup_rb(struct amdgpu_device *adev)
4965 {
4966         int i, j;
4967         u32 data;
4968         u32 active_rbs = 0;
4969         u32 bitmap;
4970         u32 rb_bitmap_width_per_sh = adev->gfx.config.max_backends_per_se /
4971                                         adev->gfx.config.max_sh_per_se;
4972
4973         mutex_lock(&adev->grbm_idx_mutex);
4974         for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
4975                 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
4976                         bitmap = i * adev->gfx.config.max_sh_per_se + j;
4977                         if (((adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 3, 0)) ||
4978                                 (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 3, 3))) &&
4979                             ((gfx_v10_3_get_disabled_sa(adev) >> bitmap) & 1))
4980                                 continue;
4981                         gfx_v10_0_select_se_sh(adev, i, j, 0xffffffff);
4982                         data = gfx_v10_0_get_rb_active_bitmap(adev);
4983                         active_rbs |= data << ((i * adev->gfx.config.max_sh_per_se + j) *
4984                                                rb_bitmap_width_per_sh);
4985                 }
4986         }
4987         gfx_v10_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
4988         mutex_unlock(&adev->grbm_idx_mutex);
4989
4990         adev->gfx.config.backend_enable_mask = active_rbs;
4991         adev->gfx.config.num_rbs = hweight32(active_rbs);
4992 }
4993
4994 static u32 gfx_v10_0_init_pa_sc_tile_steering_override(struct amdgpu_device *adev)
4995 {
4996         uint32_t num_sc;
4997         uint32_t enabled_rb_per_sh;
4998         uint32_t active_rb_bitmap;
4999         uint32_t num_rb_per_sc;
5000         uint32_t num_packer_per_sc;
5001         uint32_t pa_sc_tile_steering_override;
5002
5003         /* for ASICs that integrates GFX v10.3
5004          * pa_sc_tile_steering_override should be set to 0 */
5005         if (adev->ip_versions[GC_HWIP][0] >= IP_VERSION(10, 3, 0))
5006                 return 0;
5007
5008         /* init num_sc */
5009         num_sc = adev->gfx.config.max_shader_engines * adev->gfx.config.max_sh_per_se *
5010                         adev->gfx.config.num_sc_per_sh;
5011         /* init num_rb_per_sc */
5012         active_rb_bitmap = gfx_v10_0_get_rb_active_bitmap(adev);
5013         enabled_rb_per_sh = hweight32(active_rb_bitmap);
5014         num_rb_per_sc = enabled_rb_per_sh / adev->gfx.config.num_sc_per_sh;
5015         /* init num_packer_per_sc */
5016         num_packer_per_sc = adev->gfx.config.num_packer_per_sc;
5017
5018         pa_sc_tile_steering_override = 0;
5019         pa_sc_tile_steering_override |=
5020                 (order_base_2(num_sc) << PA_SC_TILE_STEERING_OVERRIDE__NUM_SC__SHIFT) &
5021                 PA_SC_TILE_STEERING_OVERRIDE__NUM_SC_MASK;
5022         pa_sc_tile_steering_override |=
5023                 (order_base_2(num_rb_per_sc) << PA_SC_TILE_STEERING_OVERRIDE__NUM_RB_PER_SC__SHIFT) &
5024                 PA_SC_TILE_STEERING_OVERRIDE__NUM_RB_PER_SC_MASK;
5025         pa_sc_tile_steering_override |=
5026                 (order_base_2(num_packer_per_sc) << PA_SC_TILE_STEERING_OVERRIDE__NUM_PACKER_PER_SC__SHIFT) &
5027                 PA_SC_TILE_STEERING_OVERRIDE__NUM_PACKER_PER_SC_MASK;
5028
5029         return pa_sc_tile_steering_override;
5030 }
5031
5032 #define DEFAULT_SH_MEM_BASES    (0x6000)
5033
5034 static void gfx_v10_0_init_compute_vmid(struct amdgpu_device *adev)
5035 {
5036         int i;
5037         uint32_t sh_mem_bases;
5038
5039         /*
5040          * Configure apertures:
5041          * LDS:         0x60000000'00000000 - 0x60000001'00000000 (4GB)
5042          * Scratch:     0x60000001'00000000 - 0x60000002'00000000 (4GB)
5043          * GPUVM:       0x60010000'00000000 - 0x60020000'00000000 (1TB)
5044          */
5045         sh_mem_bases = DEFAULT_SH_MEM_BASES | (DEFAULT_SH_MEM_BASES << 16);
5046
5047         mutex_lock(&adev->srbm_mutex);
5048         for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) {
5049                 nv_grbm_select(adev, 0, 0, 0, i);
5050                 /* CP and shaders */
5051                 WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, DEFAULT_SH_MEM_CONFIG);
5052                 WREG32_SOC15(GC, 0, mmSH_MEM_BASES, sh_mem_bases);
5053         }
5054         nv_grbm_select(adev, 0, 0, 0, 0);
5055         mutex_unlock(&adev->srbm_mutex);
5056
5057         /* Initialize all compute VMIDs to have no GDS, GWS, or OA
5058            acccess. These should be enabled by FW for target VMIDs. */
5059         for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) {
5060                 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_BASE, 2 * i, 0);
5061                 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_SIZE, 2 * i, 0);
5062                 WREG32_SOC15_OFFSET(GC, 0, mmGDS_GWS_VMID0, i, 0);
5063                 WREG32_SOC15_OFFSET(GC, 0, mmGDS_OA_VMID0, i, 0);
5064         }
5065 }
5066
5067 static void gfx_v10_0_init_gds_vmid(struct amdgpu_device *adev)
5068 {
5069         int vmid;
5070
5071         /*
5072          * Initialize all compute and user-gfx VMIDs to have no GDS, GWS, or OA
5073          * access. Compute VMIDs should be enabled by FW for target VMIDs,
5074          * the driver can enable them for graphics. VMID0 should maintain
5075          * access so that HWS firmware can save/restore entries.
5076          */
5077         for (vmid = 1; vmid < AMDGPU_NUM_VMID; vmid++) {
5078                 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_BASE, 2 * vmid, 0);
5079                 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_SIZE, 2 * vmid, 0);
5080                 WREG32_SOC15_OFFSET(GC, 0, mmGDS_GWS_VMID0, vmid, 0);
5081                 WREG32_SOC15_OFFSET(GC, 0, mmGDS_OA_VMID0, vmid, 0);
5082         }
5083 }
5084
5085
5086 static void gfx_v10_0_tcp_harvest(struct amdgpu_device *adev)
5087 {
5088         int i, j, k;
5089         int max_wgp_per_sh = adev->gfx.config.max_cu_per_sh >> 1;
5090         u32 tmp, wgp_active_bitmap = 0;
5091         u32 gcrd_targets_disable_tcp = 0;
5092         u32 utcl_invreq_disable = 0;
5093         /*
5094          * GCRD_TARGETS_DISABLE field contains
5095          * for Navi10/Navi12: GL1C=[18:15], SQC=[14:10], TCP=[9:0]
5096          * for Navi14: GL1C=[21:18], SQC=[17:12], TCP=[11:0]
5097          */
5098         u32 gcrd_targets_disable_mask = amdgpu_gfx_create_bitmask(
5099                 2 * max_wgp_per_sh + /* TCP */
5100                 max_wgp_per_sh + /* SQC */
5101                 4); /* GL1C */
5102         /*
5103          * UTCL1_UTCL0_INVREQ_DISABLE field contains
5104          * for Navi10Navi12: SQG=[24], RMI=[23:20], SQC=[19:10], TCP=[9:0]
5105          * for Navi14: SQG=[28], RMI=[27:24], SQC=[23:12], TCP=[11:0]
5106          */
5107         u32 utcl_invreq_disable_mask = amdgpu_gfx_create_bitmask(
5108                 2 * max_wgp_per_sh + /* TCP */
5109                 2 * max_wgp_per_sh + /* SQC */
5110                 4 + /* RMI */
5111                 1); /* SQG */
5112
5113         mutex_lock(&adev->grbm_idx_mutex);
5114         for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
5115                 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
5116                         gfx_v10_0_select_se_sh(adev, i, j, 0xffffffff);
5117                         wgp_active_bitmap = gfx_v10_0_get_wgp_active_bitmap_per_sh(adev);
5118                         /*
5119                          * Set corresponding TCP bits for the inactive WGPs in
5120                          * GCRD_SA_TARGETS_DISABLE
5121                          */
5122                         gcrd_targets_disable_tcp = 0;
5123                         /* Set TCP & SQC bits in UTCL1_UTCL0_INVREQ_DISABLE */
5124                         utcl_invreq_disable = 0;
5125
5126                         for (k = 0; k < max_wgp_per_sh; k++) {
5127                                 if (!(wgp_active_bitmap & (1 << k))) {
5128                                         gcrd_targets_disable_tcp |= 3 << (2 * k);
5129                                         gcrd_targets_disable_tcp |= 1 << (k + (max_wgp_per_sh * 2));
5130                                         utcl_invreq_disable |= (3 << (2 * k)) |
5131                                                 (3 << (2 * (max_wgp_per_sh + k)));
5132                                 }
5133                         }
5134
5135                         tmp = RREG32_SOC15(GC, 0, mmUTCL1_UTCL0_INVREQ_DISABLE);
5136                         /* only override TCP & SQC bits */
5137                         tmp &= (0xffffffffU << (4 * max_wgp_per_sh));
5138                         tmp |= (utcl_invreq_disable & utcl_invreq_disable_mask);
5139                         WREG32_SOC15(GC, 0, mmUTCL1_UTCL0_INVREQ_DISABLE, tmp);
5140
5141                         tmp = RREG32_SOC15(GC, 0, mmGCRD_SA_TARGETS_DISABLE);
5142                         /* only override TCP & SQC bits */
5143                         tmp &= (0xffffffffU << (3 * max_wgp_per_sh));
5144                         tmp |= (gcrd_targets_disable_tcp & gcrd_targets_disable_mask);
5145                         WREG32_SOC15(GC, 0, mmGCRD_SA_TARGETS_DISABLE, tmp);
5146                 }
5147         }
5148
5149         gfx_v10_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
5150         mutex_unlock(&adev->grbm_idx_mutex);
5151 }
5152
5153 static void gfx_v10_0_get_tcc_info(struct amdgpu_device *adev)
5154 {
5155         /* TCCs are global (not instanced). */
5156         uint32_t tcc_disable;
5157
5158         if (adev->ip_versions[GC_HWIP][0] >= IP_VERSION(10, 3, 0)) {
5159                 tcc_disable = RREG32_SOC15(GC, 0, mmCGTS_TCC_DISABLE_gc_10_3) |
5160                               RREG32_SOC15(GC, 0, mmCGTS_USER_TCC_DISABLE_gc_10_3);
5161         } else {
5162                 tcc_disable = RREG32_SOC15(GC, 0, mmCGTS_TCC_DISABLE) |
5163                               RREG32_SOC15(GC, 0, mmCGTS_USER_TCC_DISABLE);
5164         }
5165
5166         adev->gfx.config.tcc_disabled_mask =
5167                 REG_GET_FIELD(tcc_disable, CGTS_TCC_DISABLE, TCC_DISABLE) |
5168                 (REG_GET_FIELD(tcc_disable, CGTS_TCC_DISABLE, HI_TCC_DISABLE) << 16);
5169 }
5170
5171 static void gfx_v10_0_constants_init(struct amdgpu_device *adev)
5172 {
5173         u32 tmp;
5174         int i;
5175
5176         WREG32_FIELD15(GC, 0, GRBM_CNTL, READ_TIMEOUT, 0xff);
5177
5178         gfx_v10_0_setup_rb(adev);
5179         gfx_v10_0_get_cu_info(adev, &adev->gfx.cu_info);
5180         gfx_v10_0_get_tcc_info(adev);
5181         adev->gfx.config.pa_sc_tile_steering_override =
5182                 gfx_v10_0_init_pa_sc_tile_steering_override(adev);
5183
5184         /* XXX SH_MEM regs */
5185         /* where to put LDS, scratch, GPUVM in FSA64 space */
5186         mutex_lock(&adev->srbm_mutex);
5187         for (i = 0; i < adev->vm_manager.id_mgr[AMDGPU_GFXHUB_0].num_ids; i++) {
5188                 nv_grbm_select(adev, 0, 0, 0, i);
5189                 /* CP and shaders */
5190                 WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, DEFAULT_SH_MEM_CONFIG);
5191                 if (i != 0) {
5192                         tmp = REG_SET_FIELD(0, SH_MEM_BASES, PRIVATE_BASE,
5193                                 (adev->gmc.private_aperture_start >> 48));
5194                         tmp = REG_SET_FIELD(tmp, SH_MEM_BASES, SHARED_BASE,
5195                                 (adev->gmc.shared_aperture_start >> 48));
5196                         WREG32_SOC15(GC, 0, mmSH_MEM_BASES, tmp);
5197                 }
5198         }
5199         nv_grbm_select(adev, 0, 0, 0, 0);
5200
5201         mutex_unlock(&adev->srbm_mutex);
5202
5203         gfx_v10_0_init_compute_vmid(adev);
5204         gfx_v10_0_init_gds_vmid(adev);
5205
5206 }
5207
5208 static void gfx_v10_0_enable_gui_idle_interrupt(struct amdgpu_device *adev,
5209                                                bool enable)
5210 {
5211         u32 tmp;
5212
5213         if (amdgpu_sriov_vf(adev))
5214                 return;
5215
5216         tmp = RREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0);
5217
5218         tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE,
5219                             enable ? 1 : 0);
5220         tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE,
5221                             enable ? 1 : 0);
5222         tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE,
5223                             enable ? 1 : 0);
5224         tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, GFX_IDLE_INT_ENABLE,
5225                             enable ? 1 : 0);
5226
5227         WREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0, tmp);
5228 }
5229
5230 static int gfx_v10_0_init_csb(struct amdgpu_device *adev)
5231 {
5232         adev->gfx.rlc.funcs->get_csb_buffer(adev, adev->gfx.rlc.cs_ptr);
5233
5234         /* csib */
5235         if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 1, 2)) {
5236                 WREG32_SOC15_RLC(GC, 0, mmRLC_CSIB_ADDR_HI,
5237                                 adev->gfx.rlc.clear_state_gpu_addr >> 32);
5238                 WREG32_SOC15_RLC(GC, 0, mmRLC_CSIB_ADDR_LO,
5239                                 adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc);
5240                 WREG32_SOC15_RLC(GC, 0, mmRLC_CSIB_LENGTH, adev->gfx.rlc.clear_state_size);
5241         } else {
5242                 WREG32_SOC15(GC, 0, mmRLC_CSIB_ADDR_HI,
5243                                 adev->gfx.rlc.clear_state_gpu_addr >> 32);
5244                 WREG32_SOC15(GC, 0, mmRLC_CSIB_ADDR_LO,
5245                                 adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc);
5246                 WREG32_SOC15(GC, 0, mmRLC_CSIB_LENGTH, adev->gfx.rlc.clear_state_size);
5247         }
5248         return 0;
5249 }
5250
5251 static void gfx_v10_0_rlc_stop(struct amdgpu_device *adev)
5252 {
5253         u32 tmp = RREG32_SOC15(GC, 0, mmRLC_CNTL);
5254
5255         tmp = REG_SET_FIELD(tmp, RLC_CNTL, RLC_ENABLE_F32, 0);
5256         WREG32_SOC15(GC, 0, mmRLC_CNTL, tmp);
5257 }
5258
5259 static void gfx_v10_0_rlc_reset(struct amdgpu_device *adev)
5260 {
5261         WREG32_FIELD15(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 1);
5262         udelay(50);
5263         WREG32_FIELD15(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 0);
5264         udelay(50);
5265 }
5266
5267 static void gfx_v10_0_rlc_smu_handshake_cntl(struct amdgpu_device *adev,
5268                                              bool enable)
5269 {
5270         uint32_t rlc_pg_cntl;
5271
5272         rlc_pg_cntl = RREG32_SOC15(GC, 0, mmRLC_PG_CNTL);
5273
5274         if (!enable) {
5275                 /* RLC_PG_CNTL[23] = 0 (default)
5276                  * RLC will wait for handshake acks with SMU
5277                  * GFXOFF will be enabled
5278                  * RLC_PG_CNTL[23] = 1
5279                  * RLC will not issue any message to SMU
5280                  * hence no handshake between SMU & RLC
5281                  * GFXOFF will be disabled
5282                  */
5283                 rlc_pg_cntl |= 0x800000;
5284         } else
5285                 rlc_pg_cntl &= ~0x800000;
5286         WREG32_SOC15(GC, 0, mmRLC_PG_CNTL, rlc_pg_cntl);
5287 }
5288
5289 static void gfx_v10_0_rlc_start(struct amdgpu_device *adev)
5290 {
5291         /* TODO: enable rlc & smu handshake until smu
5292          * and gfxoff feature works as expected */
5293         if (!(amdgpu_pp_feature_mask & PP_GFXOFF_MASK))
5294                 gfx_v10_0_rlc_smu_handshake_cntl(adev, false);
5295
5296         WREG32_FIELD15(GC, 0, RLC_CNTL, RLC_ENABLE_F32, 1);
5297         udelay(50);
5298 }
5299
5300 static void gfx_v10_0_rlc_enable_srm(struct amdgpu_device *adev)
5301 {
5302         uint32_t tmp;
5303
5304         /* enable Save Restore Machine */
5305         tmp = RREG32_SOC15(GC, 0, mmRLC_SRM_CNTL);
5306         tmp |= RLC_SRM_CNTL__AUTO_INCR_ADDR_MASK;
5307         tmp |= RLC_SRM_CNTL__SRM_ENABLE_MASK;
5308         WREG32_SOC15(GC, 0, mmRLC_SRM_CNTL, tmp);
5309 }
5310
5311 static int gfx_v10_0_rlc_load_microcode(struct amdgpu_device *adev)
5312 {
5313         const struct rlc_firmware_header_v2_0 *hdr;
5314         const __le32 *fw_data;
5315         unsigned i, fw_size;
5316
5317         if (!adev->gfx.rlc_fw)
5318                 return -EINVAL;
5319
5320         hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data;
5321         amdgpu_ucode_print_rlc_hdr(&hdr->header);
5322
5323         fw_data = (const __le32 *)(adev->gfx.rlc_fw->data +
5324                            le32_to_cpu(hdr->header.ucode_array_offset_bytes));
5325         fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
5326
5327         WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_ADDR,
5328                      RLCG_UCODE_LOADING_START_ADDRESS);
5329
5330         for (i = 0; i < fw_size; i++)
5331                 WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_DATA,
5332                              le32_to_cpup(fw_data++));
5333
5334         WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_ADDR, adev->gfx.rlc_fw_version);
5335
5336         return 0;
5337 }
5338
5339 static int gfx_v10_0_rlc_resume(struct amdgpu_device *adev)
5340 {
5341         int r;
5342
5343         if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP &&
5344                 adev->psp.autoload_supported) {
5345
5346                 r = gfx_v10_0_wait_for_rlc_autoload_complete(adev);
5347                 if (r)
5348                         return r;
5349
5350                 gfx_v10_0_init_csb(adev);
5351
5352                 if (!amdgpu_sriov_vf(adev)) /* enable RLC SRM */
5353                         gfx_v10_0_rlc_enable_srm(adev);
5354         } else {
5355                 if (amdgpu_sriov_vf(adev)) {
5356                         gfx_v10_0_init_csb(adev);
5357                         return 0;
5358                 }
5359
5360                 adev->gfx.rlc.funcs->stop(adev);
5361
5362                 /* disable CG */
5363                 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, 0);
5364
5365                 /* disable PG */
5366                 WREG32_SOC15(GC, 0, mmRLC_PG_CNTL, 0);
5367
5368                 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
5369                         /* legacy rlc firmware loading */
5370                         r = gfx_v10_0_rlc_load_microcode(adev);
5371                         if (r)
5372                                 return r;
5373                 } else if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) {
5374                         /* rlc backdoor autoload firmware */
5375                         r = gfx_v10_0_rlc_backdoor_autoload_enable(adev);
5376                         if (r)
5377                                 return r;
5378                 }
5379
5380                 gfx_v10_0_init_csb(adev);
5381
5382                 adev->gfx.rlc.funcs->start(adev);
5383
5384                 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) {
5385                         r = gfx_v10_0_wait_for_rlc_autoload_complete(adev);
5386                         if (r)
5387                                 return r;
5388                 }
5389         }
5390         return 0;
5391 }
5392
5393 static struct {
5394         FIRMWARE_ID     id;
5395         unsigned int    offset;
5396         unsigned int    size;
5397 } rlc_autoload_info[FIRMWARE_ID_MAX];
5398
5399 static int gfx_v10_0_parse_rlc_toc(struct amdgpu_device *adev)
5400 {
5401         int ret;
5402         RLC_TABLE_OF_CONTENT *rlc_toc;
5403
5404         ret = amdgpu_bo_create_reserved(adev, adev->psp.toc.size_bytes, PAGE_SIZE,
5405                                         AMDGPU_GEM_DOMAIN_GTT,
5406                                         &adev->gfx.rlc.rlc_toc_bo,
5407                                         &adev->gfx.rlc.rlc_toc_gpu_addr,
5408                                         (void **)&adev->gfx.rlc.rlc_toc_buf);
5409         if (ret) {
5410                 dev_err(adev->dev, "(%d) failed to create rlc toc bo\n", ret);
5411                 return ret;
5412         }
5413
5414         /* Copy toc from psp sos fw to rlc toc buffer */
5415         memcpy(adev->gfx.rlc.rlc_toc_buf, adev->psp.toc.start_addr, adev->psp.toc.size_bytes);
5416
5417         rlc_toc = (RLC_TABLE_OF_CONTENT *)adev->gfx.rlc.rlc_toc_buf;
5418         while (rlc_toc && (rlc_toc->id > FIRMWARE_ID_INVALID) &&
5419                 (rlc_toc->id < FIRMWARE_ID_MAX)) {
5420                 if ((rlc_toc->id >= FIRMWARE_ID_CP_CE) &&
5421                     (rlc_toc->id <= FIRMWARE_ID_CP_MES)) {
5422                         /* Offset needs 4KB alignment */
5423                         rlc_toc->offset = ALIGN(rlc_toc->offset * 4, PAGE_SIZE);
5424                 }
5425
5426                 rlc_autoload_info[rlc_toc->id].id = rlc_toc->id;
5427                 rlc_autoload_info[rlc_toc->id].offset = rlc_toc->offset * 4;
5428                 rlc_autoload_info[rlc_toc->id].size = rlc_toc->size * 4;
5429
5430                 rlc_toc++;
5431         }
5432
5433         return 0;
5434 }
5435
5436 static uint32_t gfx_v10_0_calc_toc_total_size(struct amdgpu_device *adev)
5437 {
5438         uint32_t total_size = 0;
5439         FIRMWARE_ID id;
5440         int ret;
5441
5442         ret = gfx_v10_0_parse_rlc_toc(adev);
5443         if (ret) {
5444                 dev_err(adev->dev, "failed to parse rlc toc\n");
5445                 return 0;
5446         }
5447
5448         for (id = FIRMWARE_ID_RLC_G_UCODE; id < FIRMWARE_ID_MAX; id++)
5449                 total_size += rlc_autoload_info[id].size;
5450
5451         /* In case the offset in rlc toc ucode is aligned */
5452         if (total_size < rlc_autoload_info[FIRMWARE_ID_MAX-1].offset)
5453                 total_size = rlc_autoload_info[FIRMWARE_ID_MAX-1].offset +
5454                                 rlc_autoload_info[FIRMWARE_ID_MAX-1].size;
5455
5456         return total_size;
5457 }
5458
5459 static int gfx_v10_0_rlc_backdoor_autoload_buffer_init(struct amdgpu_device *adev)
5460 {
5461         int r;
5462         uint32_t total_size;
5463
5464         total_size = gfx_v10_0_calc_toc_total_size(adev);
5465
5466         r = amdgpu_bo_create_reserved(adev, total_size, PAGE_SIZE,
5467                                       AMDGPU_GEM_DOMAIN_GTT,
5468                                       &adev->gfx.rlc.rlc_autoload_bo,
5469                                       &adev->gfx.rlc.rlc_autoload_gpu_addr,
5470                                       (void **)&adev->gfx.rlc.rlc_autoload_ptr);
5471         if (r) {
5472                 dev_err(adev->dev, "(%d) failed to create fw autoload bo\n", r);
5473                 return r;
5474         }
5475
5476         return 0;
5477 }
5478
5479 static void gfx_v10_0_rlc_backdoor_autoload_buffer_fini(struct amdgpu_device *adev)
5480 {
5481         amdgpu_bo_free_kernel(&adev->gfx.rlc.rlc_toc_bo,
5482                               &adev->gfx.rlc.rlc_toc_gpu_addr,
5483                               (void **)&adev->gfx.rlc.rlc_toc_buf);
5484         amdgpu_bo_free_kernel(&adev->gfx.rlc.rlc_autoload_bo,
5485                               &adev->gfx.rlc.rlc_autoload_gpu_addr,
5486                               (void **)&adev->gfx.rlc.rlc_autoload_ptr);
5487 }
5488
5489 static void gfx_v10_0_rlc_backdoor_autoload_copy_ucode(struct amdgpu_device *adev,
5490                                                        FIRMWARE_ID id,
5491                                                        const void *fw_data,
5492                                                        uint32_t fw_size)
5493 {
5494         uint32_t toc_offset;
5495         uint32_t toc_fw_size;
5496         char *ptr = adev->gfx.rlc.rlc_autoload_ptr;
5497
5498         if (id <= FIRMWARE_ID_INVALID || id >= FIRMWARE_ID_MAX)
5499                 return;
5500
5501         toc_offset = rlc_autoload_info[id].offset;
5502         toc_fw_size = rlc_autoload_info[id].size;
5503
5504         if (fw_size == 0)
5505                 fw_size = toc_fw_size;
5506
5507         if (fw_size > toc_fw_size)
5508                 fw_size = toc_fw_size;
5509
5510         memcpy(ptr + toc_offset, fw_data, fw_size);
5511
5512         if (fw_size < toc_fw_size)
5513                 memset(ptr + toc_offset + fw_size, 0, toc_fw_size - fw_size);
5514 }
5515
5516 static void gfx_v10_0_rlc_backdoor_autoload_copy_toc_ucode(struct amdgpu_device *adev)
5517 {
5518         void *data;
5519         uint32_t size;
5520
5521         data = adev->gfx.rlc.rlc_toc_buf;
5522         size = rlc_autoload_info[FIRMWARE_ID_RLC_TOC].size;
5523
5524         gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5525                                                    FIRMWARE_ID_RLC_TOC,
5526                                                    data, size);
5527 }
5528
5529 static void gfx_v10_0_rlc_backdoor_autoload_copy_gfx_ucode(struct amdgpu_device *adev)
5530 {
5531         const __le32 *fw_data;
5532         uint32_t fw_size;
5533         const struct gfx_firmware_header_v1_0 *cp_hdr;
5534         const struct rlc_firmware_header_v2_0 *rlc_hdr;
5535
5536         /* pfp ucode */
5537         cp_hdr = (const struct gfx_firmware_header_v1_0 *)
5538                 adev->gfx.pfp_fw->data;
5539         fw_data = (const __le32 *)(adev->gfx.pfp_fw->data +
5540                 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes));
5541         fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes);
5542         gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5543                                                    FIRMWARE_ID_CP_PFP,
5544                                                    fw_data, fw_size);
5545
5546         /* ce ucode */
5547         cp_hdr = (const struct gfx_firmware_header_v1_0 *)
5548                 adev->gfx.ce_fw->data;
5549         fw_data = (const __le32 *)(adev->gfx.ce_fw->data +
5550                 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes));
5551         fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes);
5552         gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5553                                                    FIRMWARE_ID_CP_CE,
5554                                                    fw_data, fw_size);
5555
5556         /* me ucode */
5557         cp_hdr = (const struct gfx_firmware_header_v1_0 *)
5558                 adev->gfx.me_fw->data;
5559         fw_data = (const __le32 *)(adev->gfx.me_fw->data +
5560                 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes));
5561         fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes);
5562         gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5563                                                    FIRMWARE_ID_CP_ME,
5564                                                    fw_data, fw_size);
5565
5566         /* rlc ucode */
5567         rlc_hdr = (const struct rlc_firmware_header_v2_0 *)
5568                 adev->gfx.rlc_fw->data;
5569         fw_data = (const __le32 *)(adev->gfx.rlc_fw->data +
5570                 le32_to_cpu(rlc_hdr->header.ucode_array_offset_bytes));
5571         fw_size = le32_to_cpu(rlc_hdr->header.ucode_size_bytes);
5572         gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5573                                                    FIRMWARE_ID_RLC_G_UCODE,
5574                                                    fw_data, fw_size);
5575
5576         /* mec1 ucode */
5577         cp_hdr = (const struct gfx_firmware_header_v1_0 *)
5578                 adev->gfx.mec_fw->data;
5579         fw_data = (const __le32 *) (adev->gfx.mec_fw->data +
5580                 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes));
5581         fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes) -
5582                 cp_hdr->jt_size * 4;
5583         gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5584                                                    FIRMWARE_ID_CP_MEC,
5585                                                    fw_data, fw_size);
5586         /* mec2 ucode is not necessary if mec2 ucode is same as mec1 */
5587 }
5588
5589 /* Temporarily put sdma part here */
5590 static void gfx_v10_0_rlc_backdoor_autoload_copy_sdma_ucode(struct amdgpu_device *adev)
5591 {
5592         const __le32 *fw_data;
5593         uint32_t fw_size;
5594         const struct sdma_firmware_header_v1_0 *sdma_hdr;
5595         int i;
5596
5597         for (i = 0; i < adev->sdma.num_instances; i++) {
5598                 sdma_hdr = (const struct sdma_firmware_header_v1_0 *)
5599                         adev->sdma.instance[i].fw->data;
5600                 fw_data = (const __le32 *) (adev->sdma.instance[i].fw->data +
5601                         le32_to_cpu(sdma_hdr->header.ucode_array_offset_bytes));
5602                 fw_size = le32_to_cpu(sdma_hdr->header.ucode_size_bytes);
5603
5604                 if (i == 0) {
5605                         gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5606                                 FIRMWARE_ID_SDMA0_UCODE, fw_data, fw_size);
5607                         gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5608                                 FIRMWARE_ID_SDMA0_JT,
5609                                 (uint32_t *)fw_data +
5610                                 sdma_hdr->jt_offset,
5611                                 sdma_hdr->jt_size * 4);
5612                 } else if (i == 1) {
5613                         gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5614                                 FIRMWARE_ID_SDMA1_UCODE, fw_data, fw_size);
5615                         gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5616                                 FIRMWARE_ID_SDMA1_JT,
5617                                 (uint32_t *)fw_data +
5618                                 sdma_hdr->jt_offset,
5619                                 sdma_hdr->jt_size * 4);
5620                 }
5621         }
5622 }
5623
5624 static int gfx_v10_0_rlc_backdoor_autoload_enable(struct amdgpu_device *adev)
5625 {
5626         uint32_t rlc_g_offset, rlc_g_size, tmp;
5627         uint64_t gpu_addr;
5628
5629         gfx_v10_0_rlc_backdoor_autoload_copy_toc_ucode(adev);
5630         gfx_v10_0_rlc_backdoor_autoload_copy_sdma_ucode(adev);
5631         gfx_v10_0_rlc_backdoor_autoload_copy_gfx_ucode(adev);
5632
5633         rlc_g_offset = rlc_autoload_info[FIRMWARE_ID_RLC_G_UCODE].offset;
5634         rlc_g_size = rlc_autoload_info[FIRMWARE_ID_RLC_G_UCODE].size;
5635         gpu_addr = adev->gfx.rlc.rlc_autoload_gpu_addr + rlc_g_offset;
5636
5637         WREG32_SOC15(GC, 0, mmRLC_HYP_BOOTLOAD_ADDR_HI, upper_32_bits(gpu_addr));
5638         WREG32_SOC15(GC, 0, mmRLC_HYP_BOOTLOAD_ADDR_LO, lower_32_bits(gpu_addr));
5639         WREG32_SOC15(GC, 0, mmRLC_HYP_BOOTLOAD_SIZE, rlc_g_size);
5640
5641         tmp = RREG32_SOC15(GC, 0, mmRLC_HYP_RESET_VECTOR);
5642         if (!(tmp & (RLC_HYP_RESET_VECTOR__COLD_BOOT_EXIT_MASK |
5643                    RLC_HYP_RESET_VECTOR__VDDGFX_EXIT_MASK))) {
5644                 DRM_ERROR("Neither COLD_BOOT_EXIT nor VDDGFX_EXIT is set\n");
5645                 return -EINVAL;
5646         }
5647
5648         tmp = RREG32_SOC15(GC, 0, mmRLC_CNTL);
5649         if (tmp & RLC_CNTL__RLC_ENABLE_F32_MASK) {
5650                 DRM_ERROR("RLC ROM should halt itself\n");
5651                 return -EINVAL;
5652         }
5653
5654         return 0;
5655 }
5656
5657 static int gfx_v10_0_rlc_backdoor_autoload_config_me_cache(struct amdgpu_device *adev)
5658 {
5659         uint32_t usec_timeout = 50000;  /* wait for 50ms */
5660         uint32_t tmp;
5661         int i;
5662         uint64_t addr;
5663
5664         /* Trigger an invalidation of the L1 instruction caches */
5665         tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL);
5666         tmp = REG_SET_FIELD(tmp, CP_ME_IC_OP_CNTL, INVALIDATE_CACHE, 1);
5667         WREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL, tmp);
5668
5669         /* Wait for invalidation complete */
5670         for (i = 0; i < usec_timeout; i++) {
5671                 tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL);
5672                 if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL,
5673                         INVALIDATE_CACHE_COMPLETE))
5674                         break;
5675                 udelay(1);
5676         }
5677
5678         if (i >= usec_timeout) {
5679                 dev_err(adev->dev, "failed to invalidate instruction cache\n");
5680                 return -EINVAL;
5681         }
5682
5683         /* Program me ucode address into intruction cache address register */
5684         addr = adev->gfx.rlc.rlc_autoload_gpu_addr +
5685                 rlc_autoload_info[FIRMWARE_ID_CP_ME].offset;
5686         WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_LO,
5687                         lower_32_bits(addr) & 0xFFFFF000);
5688         WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_HI,
5689                         upper_32_bits(addr));
5690
5691         return 0;
5692 }
5693
5694 static int gfx_v10_0_rlc_backdoor_autoload_config_ce_cache(struct amdgpu_device *adev)
5695 {
5696         uint32_t usec_timeout = 50000;  /* wait for 50ms */
5697         uint32_t tmp;
5698         int i;
5699         uint64_t addr;
5700
5701         /* Trigger an invalidation of the L1 instruction caches */
5702         tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL);
5703         tmp = REG_SET_FIELD(tmp, CP_CE_IC_OP_CNTL, INVALIDATE_CACHE, 1);
5704         WREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL, tmp);
5705
5706         /* Wait for invalidation complete */
5707         for (i = 0; i < usec_timeout; i++) {
5708                 tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL);
5709                 if (1 == REG_GET_FIELD(tmp, CP_CE_IC_OP_CNTL,
5710                         INVALIDATE_CACHE_COMPLETE))
5711                         break;
5712                 udelay(1);
5713         }
5714
5715         if (i >= usec_timeout) {
5716                 dev_err(adev->dev, "failed to invalidate instruction cache\n");
5717                 return -EINVAL;
5718         }
5719
5720         /* Program ce ucode address into intruction cache address register */
5721         addr = adev->gfx.rlc.rlc_autoload_gpu_addr +
5722                 rlc_autoload_info[FIRMWARE_ID_CP_CE].offset;
5723         WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_LO,
5724                         lower_32_bits(addr) & 0xFFFFF000);
5725         WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_HI,
5726                         upper_32_bits(addr));
5727
5728         return 0;
5729 }
5730
5731 static int gfx_v10_0_rlc_backdoor_autoload_config_pfp_cache(struct amdgpu_device *adev)
5732 {
5733         uint32_t usec_timeout = 50000;  /* wait for 50ms */
5734         uint32_t tmp;
5735         int i;
5736         uint64_t addr;
5737
5738         /* Trigger an invalidation of the L1 instruction caches */
5739         tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL);
5740         tmp = REG_SET_FIELD(tmp, CP_PFP_IC_OP_CNTL, INVALIDATE_CACHE, 1);
5741         WREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL, tmp);
5742
5743         /* Wait for invalidation complete */
5744         for (i = 0; i < usec_timeout; i++) {
5745                 tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL);
5746                 if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL,
5747                         INVALIDATE_CACHE_COMPLETE))
5748                         break;
5749                 udelay(1);
5750         }
5751
5752         if (i >= usec_timeout) {
5753                 dev_err(adev->dev, "failed to invalidate instruction cache\n");
5754                 return -EINVAL;
5755         }
5756
5757         /* Program pfp ucode address into intruction cache address register */
5758         addr = adev->gfx.rlc.rlc_autoload_gpu_addr +
5759                 rlc_autoload_info[FIRMWARE_ID_CP_PFP].offset;
5760         WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_LO,
5761                         lower_32_bits(addr) & 0xFFFFF000);
5762         WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_HI,
5763                         upper_32_bits(addr));
5764
5765         return 0;
5766 }
5767
5768 static int gfx_v10_0_rlc_backdoor_autoload_config_mec_cache(struct amdgpu_device *adev)
5769 {
5770         uint32_t usec_timeout = 50000;  /* wait for 50ms */
5771         uint32_t tmp;
5772         int i;
5773         uint64_t addr;
5774
5775         /* Trigger an invalidation of the L1 instruction caches */
5776         tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL);
5777         tmp = REG_SET_FIELD(tmp, CP_CPC_IC_OP_CNTL, INVALIDATE_CACHE, 1);
5778         WREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL, tmp);
5779
5780         /* Wait for invalidation complete */
5781         for (i = 0; i < usec_timeout; i++) {
5782                 tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL);
5783                 if (1 == REG_GET_FIELD(tmp, CP_CPC_IC_OP_CNTL,
5784                         INVALIDATE_CACHE_COMPLETE))
5785                         break;
5786                 udelay(1);
5787         }
5788
5789         if (i >= usec_timeout) {
5790                 dev_err(adev->dev, "failed to invalidate instruction cache\n");
5791                 return -EINVAL;
5792         }
5793
5794         /* Program mec1 ucode address into intruction cache address register */
5795         addr = adev->gfx.rlc.rlc_autoload_gpu_addr +
5796                 rlc_autoload_info[FIRMWARE_ID_CP_MEC].offset;
5797         WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_LO,
5798                         lower_32_bits(addr) & 0xFFFFF000);
5799         WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_HI,
5800                         upper_32_bits(addr));
5801
5802         return 0;
5803 }
5804
5805 static int gfx_v10_0_wait_for_rlc_autoload_complete(struct amdgpu_device *adev)
5806 {
5807         uint32_t cp_status;
5808         uint32_t bootload_status;
5809         int i, r;
5810
5811         for (i = 0; i < adev->usec_timeout; i++) {
5812                 cp_status = RREG32_SOC15(GC, 0, mmCP_STAT);
5813                 bootload_status = RREG32_SOC15(GC, 0, mmRLC_RLCS_BOOTLOAD_STATUS);
5814                 if ((cp_status == 0) &&
5815                     (REG_GET_FIELD(bootload_status,
5816                         RLC_RLCS_BOOTLOAD_STATUS, BOOTLOAD_COMPLETE) == 1)) {
5817                         break;
5818                 }
5819                 udelay(1);
5820         }
5821
5822         if (i >= adev->usec_timeout) {
5823                 dev_err(adev->dev, "rlc autoload: gc ucode autoload timeout\n");
5824                 return -ETIMEDOUT;
5825         }
5826
5827         if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) {
5828                 r = gfx_v10_0_rlc_backdoor_autoload_config_me_cache(adev);
5829                 if (r)
5830                         return r;
5831
5832                 r = gfx_v10_0_rlc_backdoor_autoload_config_ce_cache(adev);
5833                 if (r)
5834                         return r;
5835
5836                 r = gfx_v10_0_rlc_backdoor_autoload_config_pfp_cache(adev);
5837                 if (r)
5838                         return r;
5839
5840                 r = gfx_v10_0_rlc_backdoor_autoload_config_mec_cache(adev);
5841                 if (r)
5842                         return r;
5843         }
5844
5845         return 0;
5846 }
5847
5848 static int gfx_v10_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable)
5849 {
5850         int i;
5851         u32 tmp = RREG32_SOC15(GC, 0, mmCP_ME_CNTL);
5852
5853         tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, enable ? 0 : 1);
5854         tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, enable ? 0 : 1);
5855         tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_HALT, enable ? 0 : 1);
5856
5857         if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 1, 2)) {
5858                 WREG32_SOC15_RLC(GC, 0, mmCP_ME_CNTL, tmp);
5859         } else {
5860                 WREG32_SOC15(GC, 0, mmCP_ME_CNTL, tmp);
5861         }
5862
5863         for (i = 0; i < adev->usec_timeout; i++) {
5864                 if (RREG32_SOC15(GC, 0, mmCP_STAT) == 0)
5865                         break;
5866                 udelay(1);
5867         }
5868
5869         if (i >= adev->usec_timeout)
5870                 DRM_ERROR("failed to %s cp gfx\n", enable ? "unhalt" : "halt");
5871
5872         return 0;
5873 }
5874
5875 static int gfx_v10_0_cp_gfx_load_pfp_microcode(struct amdgpu_device *adev)
5876 {
5877         int r;
5878         const struct gfx_firmware_header_v1_0 *pfp_hdr;
5879         const __le32 *fw_data;
5880         unsigned i, fw_size;
5881         uint32_t tmp;
5882         uint32_t usec_timeout = 50000;  /* wait for 50ms */
5883
5884         pfp_hdr = (const struct gfx_firmware_header_v1_0 *)
5885                 adev->gfx.pfp_fw->data;
5886
5887         amdgpu_ucode_print_gfx_hdr(&pfp_hdr->header);
5888
5889         fw_data = (const __le32 *)(adev->gfx.pfp_fw->data +
5890                 le32_to_cpu(pfp_hdr->header.ucode_array_offset_bytes));
5891         fw_size = le32_to_cpu(pfp_hdr->header.ucode_size_bytes);
5892
5893         r = amdgpu_bo_create_reserved(adev, pfp_hdr->header.ucode_size_bytes,
5894                                       PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,
5895                                       &adev->gfx.pfp.pfp_fw_obj,
5896                                       &adev->gfx.pfp.pfp_fw_gpu_addr,
5897                                       (void **)&adev->gfx.pfp.pfp_fw_ptr);
5898         if (r) {
5899                 dev_err(adev->dev, "(%d) failed to create pfp fw bo\n", r);
5900                 gfx_v10_0_pfp_fini(adev);
5901                 return r;
5902         }
5903
5904         memcpy(adev->gfx.pfp.pfp_fw_ptr, fw_data, fw_size);
5905
5906         amdgpu_bo_kunmap(adev->gfx.pfp.pfp_fw_obj);
5907         amdgpu_bo_unreserve(adev->gfx.pfp.pfp_fw_obj);
5908
5909         /* Trigger an invalidation of the L1 instruction caches */
5910         tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL);
5911         tmp = REG_SET_FIELD(tmp, CP_PFP_IC_OP_CNTL, INVALIDATE_CACHE, 1);
5912         WREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL, tmp);
5913
5914         /* Wait for invalidation complete */
5915         for (i = 0; i < usec_timeout; i++) {
5916                 tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL);
5917                 if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL,
5918                         INVALIDATE_CACHE_COMPLETE))
5919                         break;
5920                 udelay(1);
5921         }
5922
5923         if (i >= usec_timeout) {
5924                 dev_err(adev->dev, "failed to invalidate instruction cache\n");
5925                 return -EINVAL;
5926         }
5927
5928         if (amdgpu_emu_mode == 1)
5929                 adev->hdp.funcs->flush_hdp(adev, NULL);
5930
5931         tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_CNTL);
5932         tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, VMID, 0);
5933         tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, CACHE_POLICY, 0);
5934         tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, EXE_DISABLE, 0);
5935         tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, ADDRESS_CLAMP, 1);
5936         WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_CNTL, tmp);
5937         WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_LO,
5938                 adev->gfx.pfp.pfp_fw_gpu_addr & 0xFFFFF000);
5939         WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_HI,
5940                 upper_32_bits(adev->gfx.pfp.pfp_fw_gpu_addr));
5941
5942         WREG32_SOC15(GC, 0, mmCP_HYP_PFP_UCODE_ADDR, 0);
5943
5944         for (i = 0; i < pfp_hdr->jt_size; i++)
5945                 WREG32_SOC15(GC, 0, mmCP_HYP_PFP_UCODE_DATA,
5946                              le32_to_cpup(fw_data + pfp_hdr->jt_offset + i));
5947
5948         WREG32_SOC15(GC, 0, mmCP_HYP_PFP_UCODE_ADDR, adev->gfx.pfp_fw_version);
5949
5950         return 0;
5951 }
5952
5953 static int gfx_v10_0_cp_gfx_load_ce_microcode(struct amdgpu_device *adev)
5954 {
5955         int r;
5956         const struct gfx_firmware_header_v1_0 *ce_hdr;
5957         const __le32 *fw_data;
5958         unsigned i, fw_size;
5959         uint32_t tmp;
5960         uint32_t usec_timeout = 50000;  /* wait for 50ms */
5961
5962         ce_hdr = (const struct gfx_firmware_header_v1_0 *)
5963                 adev->gfx.ce_fw->data;
5964
5965         amdgpu_ucode_print_gfx_hdr(&ce_hdr->header);
5966
5967         fw_data = (const __le32 *)(adev->gfx.ce_fw->data +
5968                 le32_to_cpu(ce_hdr->header.ucode_array_offset_bytes));
5969         fw_size = le32_to_cpu(ce_hdr->header.ucode_size_bytes);
5970
5971         r = amdgpu_bo_create_reserved(adev, ce_hdr->header.ucode_size_bytes,
5972                                       PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,
5973                                       &adev->gfx.ce.ce_fw_obj,
5974                                       &adev->gfx.ce.ce_fw_gpu_addr,
5975                                       (void **)&adev->gfx.ce.ce_fw_ptr);
5976         if (r) {
5977                 dev_err(adev->dev, "(%d) failed to create ce fw bo\n", r);
5978                 gfx_v10_0_ce_fini(adev);
5979                 return r;
5980         }
5981
5982         memcpy(adev->gfx.ce.ce_fw_ptr, fw_data, fw_size);
5983
5984         amdgpu_bo_kunmap(adev->gfx.ce.ce_fw_obj);
5985         amdgpu_bo_unreserve(adev->gfx.ce.ce_fw_obj);
5986
5987         /* Trigger an invalidation of the L1 instruction caches */
5988         tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL);
5989         tmp = REG_SET_FIELD(tmp, CP_CE_IC_OP_CNTL, INVALIDATE_CACHE, 1);
5990         WREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL, tmp);
5991
5992         /* Wait for invalidation complete */
5993         for (i = 0; i < usec_timeout; i++) {
5994                 tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL);
5995                 if (1 == REG_GET_FIELD(tmp, CP_CE_IC_OP_CNTL,
5996                         INVALIDATE_CACHE_COMPLETE))
5997                         break;
5998                 udelay(1);
5999         }
6000
6001         if (i >= usec_timeout) {
6002                 dev_err(adev->dev, "failed to invalidate instruction cache\n");
6003                 return -EINVAL;
6004         }
6005
6006         if (amdgpu_emu_mode == 1)
6007                 adev->hdp.funcs->flush_hdp(adev, NULL);
6008
6009         tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_CNTL);
6010         tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, VMID, 0);
6011         tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, CACHE_POLICY, 0);
6012         tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, EXE_DISABLE, 0);
6013         tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, ADDRESS_CLAMP, 1);
6014         WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_LO,
6015                 adev->gfx.ce.ce_fw_gpu_addr & 0xFFFFF000);
6016         WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_HI,
6017                 upper_32_bits(adev->gfx.ce.ce_fw_gpu_addr));
6018
6019         WREG32_SOC15(GC, 0, mmCP_HYP_CE_UCODE_ADDR, 0);
6020
6021         for (i = 0; i < ce_hdr->jt_size; i++)
6022                 WREG32_SOC15(GC, 0, mmCP_HYP_CE_UCODE_DATA,
6023                              le32_to_cpup(fw_data + ce_hdr->jt_offset + i));
6024
6025         WREG32_SOC15(GC, 0, mmCP_HYP_CE_UCODE_ADDR, adev->gfx.ce_fw_version);
6026
6027         return 0;
6028 }
6029
6030 static int gfx_v10_0_cp_gfx_load_me_microcode(struct amdgpu_device *adev)
6031 {
6032         int r;
6033         const struct gfx_firmware_header_v1_0 *me_hdr;
6034         const __le32 *fw_data;
6035         unsigned i, fw_size;
6036         uint32_t tmp;
6037         uint32_t usec_timeout = 50000;  /* wait for 50ms */
6038
6039         me_hdr = (const struct gfx_firmware_header_v1_0 *)
6040                 adev->gfx.me_fw->data;
6041
6042         amdgpu_ucode_print_gfx_hdr(&me_hdr->header);
6043
6044         fw_data = (const __le32 *)(adev->gfx.me_fw->data +
6045                 le32_to_cpu(me_hdr->header.ucode_array_offset_bytes));
6046         fw_size = le32_to_cpu(me_hdr->header.ucode_size_bytes);
6047
6048         r = amdgpu_bo_create_reserved(adev, me_hdr->header.ucode_size_bytes,
6049                                       PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,
6050                                       &adev->gfx.me.me_fw_obj,
6051                                       &adev->gfx.me.me_fw_gpu_addr,
6052                                       (void **)&adev->gfx.me.me_fw_ptr);
6053         if (r) {
6054                 dev_err(adev->dev, "(%d) failed to create me fw bo\n", r);
6055                 gfx_v10_0_me_fini(adev);
6056                 return r;
6057         }
6058
6059         memcpy(adev->gfx.me.me_fw_ptr, fw_data, fw_size);
6060
6061         amdgpu_bo_kunmap(adev->gfx.me.me_fw_obj);
6062         amdgpu_bo_unreserve(adev->gfx.me.me_fw_obj);
6063
6064         /* Trigger an invalidation of the L1 instruction caches */
6065         tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL);
6066         tmp = REG_SET_FIELD(tmp, CP_ME_IC_OP_CNTL, INVALIDATE_CACHE, 1);
6067         WREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL, tmp);
6068
6069         /* Wait for invalidation complete */
6070         for (i = 0; i < usec_timeout; i++) {
6071                 tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL);
6072                 if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL,
6073                         INVALIDATE_CACHE_COMPLETE))
6074                         break;
6075                 udelay(1);
6076         }
6077
6078         if (i >= usec_timeout) {
6079                 dev_err(adev->dev, "failed to invalidate instruction cache\n");
6080                 return -EINVAL;
6081         }
6082
6083         if (amdgpu_emu_mode == 1)
6084                 adev->hdp.funcs->flush_hdp(adev, NULL);
6085
6086         tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_CNTL);
6087         tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, VMID, 0);
6088         tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, CACHE_POLICY, 0);
6089         tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, EXE_DISABLE, 0);
6090         tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, ADDRESS_CLAMP, 1);
6091         WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_LO,
6092                 adev->gfx.me.me_fw_gpu_addr & 0xFFFFF000);
6093         WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_HI,
6094                 upper_32_bits(adev->gfx.me.me_fw_gpu_addr));
6095
6096         WREG32_SOC15(GC, 0, mmCP_HYP_ME_UCODE_ADDR, 0);
6097
6098         for (i = 0; i < me_hdr->jt_size; i++)
6099                 WREG32_SOC15(GC, 0, mmCP_HYP_ME_UCODE_DATA,
6100                              le32_to_cpup(fw_data + me_hdr->jt_offset + i));
6101
6102         WREG32_SOC15(GC, 0, mmCP_HYP_ME_UCODE_ADDR, adev->gfx.me_fw_version);
6103
6104         return 0;
6105 }
6106
6107 static int gfx_v10_0_cp_gfx_load_microcode(struct amdgpu_device *adev)
6108 {
6109         int r;
6110
6111         if (!adev->gfx.me_fw || !adev->gfx.pfp_fw || !adev->gfx.ce_fw)
6112                 return -EINVAL;
6113
6114         gfx_v10_0_cp_gfx_enable(adev, false);
6115
6116         r = gfx_v10_0_cp_gfx_load_pfp_microcode(adev);
6117         if (r) {
6118                 dev_err(adev->dev, "(%d) failed to load pfp fw\n", r);
6119                 return r;
6120         }
6121
6122         r = gfx_v10_0_cp_gfx_load_ce_microcode(adev);
6123         if (r) {
6124                 dev_err(adev->dev, "(%d) failed to load ce fw\n", r);
6125                 return r;
6126         }
6127
6128         r = gfx_v10_0_cp_gfx_load_me_microcode(adev);
6129         if (r) {
6130                 dev_err(adev->dev, "(%d) failed to load me fw\n", r);
6131                 return r;
6132         }
6133
6134         return 0;
6135 }
6136
6137 static int gfx_v10_0_cp_gfx_start(struct amdgpu_device *adev)
6138 {
6139         struct amdgpu_ring *ring;
6140         const struct cs_section_def *sect = NULL;
6141         const struct cs_extent_def *ext = NULL;
6142         int r, i;
6143         int ctx_reg_offset;
6144
6145         /* init the CP */
6146         WREG32_SOC15(GC, 0, mmCP_MAX_CONTEXT,
6147                      adev->gfx.config.max_hw_contexts - 1);
6148         WREG32_SOC15(GC, 0, mmCP_DEVICE_ID, 1);
6149
6150         gfx_v10_0_cp_gfx_enable(adev, true);
6151
6152         ring = &adev->gfx.gfx_ring[0];
6153         r = amdgpu_ring_alloc(ring, gfx_v10_0_get_csb_size(adev) + 4);
6154         if (r) {
6155                 DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r);
6156                 return r;
6157         }
6158
6159         amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
6160         amdgpu_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
6161
6162         amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1));
6163         amdgpu_ring_write(ring, 0x80000000);
6164         amdgpu_ring_write(ring, 0x80000000);
6165
6166         for (sect = gfx10_cs_data; sect->section != NULL; ++sect) {
6167                 for (ext = sect->section; ext->extent != NULL; ++ext) {
6168                         if (sect->id == SECT_CONTEXT) {
6169                                 amdgpu_ring_write(ring,
6170                                                   PACKET3(PACKET3_SET_CONTEXT_REG,
6171                                                           ext->reg_count));
6172                                 amdgpu_ring_write(ring, ext->reg_index -
6173                                                   PACKET3_SET_CONTEXT_REG_START);
6174                                 for (i = 0; i < ext->reg_count; i++)
6175                                         amdgpu_ring_write(ring, ext->extent[i]);
6176                         }
6177                 }
6178         }
6179
6180         ctx_reg_offset =
6181                 SOC15_REG_OFFSET(GC, 0, mmPA_SC_TILE_STEERING_OVERRIDE) - PACKET3_SET_CONTEXT_REG_START;
6182         amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
6183         amdgpu_ring_write(ring, ctx_reg_offset);
6184         amdgpu_ring_write(ring, adev->gfx.config.pa_sc_tile_steering_override);
6185
6186         amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
6187         amdgpu_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE);
6188
6189         amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));
6190         amdgpu_ring_write(ring, 0);
6191
6192         amdgpu_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2));
6193         amdgpu_ring_write(ring, PACKET3_BASE_INDEX(CE_PARTITION_BASE));
6194         amdgpu_ring_write(ring, 0x8000);
6195         amdgpu_ring_write(ring, 0x8000);
6196
6197         amdgpu_ring_commit(ring);
6198
6199         /* submit cs packet to copy state 0 to next available state */
6200         if (adev->gfx.num_gfx_rings > 1) {
6201                 /* maximum supported gfx ring is 2 */
6202                 ring = &adev->gfx.gfx_ring[1];
6203                 r = amdgpu_ring_alloc(ring, 2);
6204                 if (r) {
6205                         DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r);
6206                         return r;
6207                 }
6208
6209                 amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));
6210                 amdgpu_ring_write(ring, 0);
6211
6212                 amdgpu_ring_commit(ring);
6213         }
6214         return 0;
6215 }
6216
6217 static void gfx_v10_0_cp_gfx_switch_pipe(struct amdgpu_device *adev,
6218                                          CP_PIPE_ID pipe)
6219 {
6220         u32 tmp;
6221
6222         tmp = RREG32_SOC15(GC, 0, mmGRBM_GFX_CNTL);
6223         tmp = REG_SET_FIELD(tmp, GRBM_GFX_CNTL, PIPEID, pipe);
6224
6225         WREG32_SOC15(GC, 0, mmGRBM_GFX_CNTL, tmp);
6226 }
6227
6228 static void gfx_v10_0_cp_gfx_set_doorbell(struct amdgpu_device *adev,
6229                                           struct amdgpu_ring *ring)
6230 {
6231         u32 tmp;
6232
6233         if (!amdgpu_async_gfx_ring) {
6234                 tmp = RREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL);
6235                 if (ring->use_doorbell) {
6236                         tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
6237                                                 DOORBELL_OFFSET, ring->doorbell_index);
6238                         tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
6239                                                 DOORBELL_EN, 1);
6240                 } else {
6241                         tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
6242                                                 DOORBELL_EN, 0);
6243                 }
6244                 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL, tmp);
6245         }
6246         switch (adev->ip_versions[GC_HWIP][0]) {
6247         case IP_VERSION(10, 3, 0):
6248         case IP_VERSION(10, 3, 2):
6249         case IP_VERSION(10, 3, 1):
6250         case IP_VERSION(10, 3, 4):
6251         case IP_VERSION(10, 3, 5):
6252         case IP_VERSION(10, 3, 3):
6253         case IP_VERSION(10, 3, 7):
6254                 tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER,
6255                                     DOORBELL_RANGE_LOWER_Sienna_Cichlid, ring->doorbell_index);
6256                 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_LOWER, tmp);
6257
6258                 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_UPPER,
6259                              CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_Sienna_Cichlid_MASK);
6260                 break;
6261         default:
6262                 tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER,
6263                                     DOORBELL_RANGE_LOWER, ring->doorbell_index);
6264                 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_LOWER, tmp);
6265
6266                 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_UPPER,
6267                              CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_MASK);
6268                 break;
6269         }
6270 }
6271
6272 static int gfx_v10_0_cp_gfx_resume(struct amdgpu_device *adev)
6273 {
6274         struct amdgpu_ring *ring;
6275         u32 tmp;
6276         u32 rb_bufsz;
6277         u64 rb_addr, rptr_addr, wptr_gpu_addr;
6278         u32 i;
6279
6280         /* Set the write pointer delay */
6281         WREG32_SOC15(GC, 0, mmCP_RB_WPTR_DELAY, 0);
6282
6283         /* set the RB to use vmid 0 */
6284         WREG32_SOC15(GC, 0, mmCP_RB_VMID, 0);
6285
6286         /* Init gfx ring 0 for pipe 0 */
6287         mutex_lock(&adev->srbm_mutex);
6288         gfx_v10_0_cp_gfx_switch_pipe(adev, PIPE_ID0);
6289
6290         /* Set ring buffer size */
6291         ring = &adev->gfx.gfx_ring[0];
6292         rb_bufsz = order_base_2(ring->ring_size / 8);
6293         tmp = REG_SET_FIELD(0, CP_RB0_CNTL, RB_BUFSZ, rb_bufsz);
6294         tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, RB_BLKSZ, rb_bufsz - 2);
6295 #ifdef __BIG_ENDIAN
6296         tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, BUF_SWAP, 1);
6297 #endif
6298         WREG32_SOC15(GC, 0, mmCP_RB0_CNTL, tmp);
6299
6300         /* Initialize the ring buffer's write pointers */
6301         ring->wptr = 0;
6302         WREG32_SOC15(GC, 0, mmCP_RB0_WPTR, lower_32_bits(ring->wptr));
6303         WREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI, upper_32_bits(ring->wptr));
6304
6305         /* set the wb address wether it's enabled or not */
6306         rptr_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
6307         WREG32_SOC15(GC, 0, mmCP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr));
6308         WREG32_SOC15(GC, 0, mmCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) &
6309                      CP_RB_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK);
6310
6311         wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
6312         WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_LO,
6313                      lower_32_bits(wptr_gpu_addr));
6314         WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI,
6315                      upper_32_bits(wptr_gpu_addr));
6316
6317         mdelay(1);
6318         WREG32_SOC15(GC, 0, mmCP_RB0_CNTL, tmp);
6319
6320         rb_addr = ring->gpu_addr >> 8;
6321         WREG32_SOC15(GC, 0, mmCP_RB0_BASE, rb_addr);
6322         WREG32_SOC15(GC, 0, mmCP_RB0_BASE_HI, upper_32_bits(rb_addr));
6323
6324         WREG32_SOC15(GC, 0, mmCP_RB_ACTIVE, 1);
6325
6326         gfx_v10_0_cp_gfx_set_doorbell(adev, ring);
6327         mutex_unlock(&adev->srbm_mutex);
6328
6329         /* Init gfx ring 1 for pipe 1 */
6330         if (adev->gfx.num_gfx_rings > 1) {
6331                 mutex_lock(&adev->srbm_mutex);
6332                 gfx_v10_0_cp_gfx_switch_pipe(adev, PIPE_ID1);
6333                 /* maximum supported gfx ring is 2 */
6334                 ring = &adev->gfx.gfx_ring[1];
6335                 rb_bufsz = order_base_2(ring->ring_size / 8);
6336                 tmp = REG_SET_FIELD(0, CP_RB1_CNTL, RB_BUFSZ, rb_bufsz);
6337                 tmp = REG_SET_FIELD(tmp, CP_RB1_CNTL, RB_BLKSZ, rb_bufsz - 2);
6338                 WREG32_SOC15(GC, 0, mmCP_RB1_CNTL, tmp);
6339                 /* Initialize the ring buffer's write pointers */
6340                 ring->wptr = 0;
6341                 WREG32_SOC15(GC, 0, mmCP_RB1_WPTR, lower_32_bits(ring->wptr));
6342                 WREG32_SOC15(GC, 0, mmCP_RB1_WPTR_HI, upper_32_bits(ring->wptr));
6343                 /* Set the wb address wether it's enabled or not */
6344                 rptr_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
6345                 WREG32_SOC15(GC, 0, mmCP_RB1_RPTR_ADDR, lower_32_bits(rptr_addr));
6346                 WREG32_SOC15(GC, 0, mmCP_RB1_RPTR_ADDR_HI, upper_32_bits(rptr_addr) &
6347                              CP_RB1_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK);
6348                 wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
6349                 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_LO,
6350                              lower_32_bits(wptr_gpu_addr));
6351                 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI,
6352                              upper_32_bits(wptr_gpu_addr));
6353
6354                 mdelay(1);
6355                 WREG32_SOC15(GC, 0, mmCP_RB1_CNTL, tmp);
6356
6357                 rb_addr = ring->gpu_addr >> 8;
6358                 WREG32_SOC15(GC, 0, mmCP_RB1_BASE, rb_addr);
6359                 WREG32_SOC15(GC, 0, mmCP_RB1_BASE_HI, upper_32_bits(rb_addr));
6360                 WREG32_SOC15(GC, 0, mmCP_RB1_ACTIVE, 1);
6361
6362                 gfx_v10_0_cp_gfx_set_doorbell(adev, ring);
6363                 mutex_unlock(&adev->srbm_mutex);
6364         }
6365         /* Switch to pipe 0 */
6366         mutex_lock(&adev->srbm_mutex);
6367         gfx_v10_0_cp_gfx_switch_pipe(adev, PIPE_ID0);
6368         mutex_unlock(&adev->srbm_mutex);
6369
6370         /* start the ring */
6371         gfx_v10_0_cp_gfx_start(adev);
6372
6373         for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
6374                 ring = &adev->gfx.gfx_ring[i];
6375                 ring->sched.ready = true;
6376         }
6377
6378         return 0;
6379 }
6380
6381 static void gfx_v10_0_cp_compute_enable(struct amdgpu_device *adev, bool enable)
6382 {
6383         if (enable) {
6384                 switch (adev->ip_versions[GC_HWIP][0]) {
6385                 case IP_VERSION(10, 3, 0):
6386                 case IP_VERSION(10, 3, 2):
6387                 case IP_VERSION(10, 3, 1):
6388                 case IP_VERSION(10, 3, 4):
6389                 case IP_VERSION(10, 3, 5):
6390                 case IP_VERSION(10, 3, 3):
6391                 case IP_VERSION(10, 3, 7):
6392                         WREG32_SOC15(GC, 0, mmCP_MEC_CNTL_Sienna_Cichlid, 0);
6393                         break;
6394                 default:
6395                         WREG32_SOC15(GC, 0, mmCP_MEC_CNTL, 0);
6396                         break;
6397                 }
6398         } else {
6399                 switch (adev->ip_versions[GC_HWIP][0]) {
6400                 case IP_VERSION(10, 3, 0):
6401                 case IP_VERSION(10, 3, 2):
6402                 case IP_VERSION(10, 3, 1):
6403                 case IP_VERSION(10, 3, 4):
6404                 case IP_VERSION(10, 3, 5):
6405                 case IP_VERSION(10, 3, 3):
6406                 case IP_VERSION(10, 3, 7):
6407                         WREG32_SOC15(GC, 0, mmCP_MEC_CNTL_Sienna_Cichlid,
6408                                      (CP_MEC_CNTL__MEC_ME1_HALT_MASK |
6409                                       CP_MEC_CNTL__MEC_ME2_HALT_MASK));
6410                         break;
6411                 default:
6412                         WREG32_SOC15(GC, 0, mmCP_MEC_CNTL,
6413                                      (CP_MEC_CNTL__MEC_ME1_HALT_MASK |
6414                                       CP_MEC_CNTL__MEC_ME2_HALT_MASK));
6415                         break;
6416                 }
6417                 adev->gfx.kiq.ring.sched.ready = false;
6418         }
6419         udelay(50);
6420 }
6421
6422 static int gfx_v10_0_cp_compute_load_microcode(struct amdgpu_device *adev)
6423 {
6424         const struct gfx_firmware_header_v1_0 *mec_hdr;
6425         const __le32 *fw_data;
6426         unsigned i;
6427         u32 tmp;
6428         u32 usec_timeout = 50000; /* Wait for 50 ms */
6429
6430         if (!adev->gfx.mec_fw)
6431                 return -EINVAL;
6432
6433         gfx_v10_0_cp_compute_enable(adev, false);
6434
6435         mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
6436         amdgpu_ucode_print_gfx_hdr(&mec_hdr->header);
6437
6438         fw_data = (const __le32 *)
6439                 (adev->gfx.mec_fw->data +
6440                  le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes));
6441
6442         /* Trigger an invalidation of the L1 instruction caches */
6443         tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL);
6444         tmp = REG_SET_FIELD(tmp, CP_CPC_IC_OP_CNTL, INVALIDATE_CACHE, 1);
6445         WREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL, tmp);
6446
6447         /* Wait for invalidation complete */
6448         for (i = 0; i < usec_timeout; i++) {
6449                 tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL);
6450                 if (1 == REG_GET_FIELD(tmp, CP_CPC_IC_OP_CNTL,
6451                                        INVALIDATE_CACHE_COMPLETE))
6452                         break;
6453                 udelay(1);
6454         }
6455
6456         if (i >= usec_timeout) {
6457                 dev_err(adev->dev, "failed to invalidate instruction cache\n");
6458                 return -EINVAL;
6459         }
6460
6461         if (amdgpu_emu_mode == 1)
6462                 adev->hdp.funcs->flush_hdp(adev, NULL);
6463
6464         tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_CNTL);
6465         tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0);
6466         tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, EXE_DISABLE, 0);
6467         tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, ADDRESS_CLAMP, 1);
6468         WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_CNTL, tmp);
6469
6470         WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_LO, adev->gfx.mec.mec_fw_gpu_addr &
6471                      0xFFFFF000);
6472         WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_HI,
6473                      upper_32_bits(adev->gfx.mec.mec_fw_gpu_addr));
6474
6475         /* MEC1 */
6476         WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_ADDR, 0);
6477
6478         for (i = 0; i < mec_hdr->jt_size; i++)
6479                 WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_DATA,
6480                              le32_to_cpup(fw_data + mec_hdr->jt_offset + i));
6481
6482         WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_ADDR, adev->gfx.mec_fw_version);
6483
6484         /*
6485          * TODO: Loading MEC2 firmware is only necessary if MEC2 should run
6486          * different microcode than MEC1.
6487          */
6488
6489         return 0;
6490 }
6491
6492 static void gfx_v10_0_kiq_setting(struct amdgpu_ring *ring)
6493 {
6494         uint32_t tmp;
6495         struct amdgpu_device *adev = ring->adev;
6496
6497         /* tell RLC which is KIQ queue */
6498         switch (adev->ip_versions[GC_HWIP][0]) {
6499         case IP_VERSION(10, 3, 0):
6500         case IP_VERSION(10, 3, 2):
6501         case IP_VERSION(10, 3, 1):
6502         case IP_VERSION(10, 3, 4):
6503         case IP_VERSION(10, 3, 5):
6504         case IP_VERSION(10, 3, 3):
6505                 tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS_Sienna_Cichlid);
6506                 tmp &= 0xffffff00;
6507                 tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue);
6508                 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS_Sienna_Cichlid, tmp);
6509                 tmp |= 0x80;
6510                 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS_Sienna_Cichlid, tmp);
6511                 break;
6512         default:
6513                 tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS);
6514                 tmp &= 0xffffff00;
6515                 tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue);
6516                 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS, tmp);
6517                 tmp |= 0x80;
6518                 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS, tmp);
6519                 break;
6520         }
6521 }
6522
6523 static int gfx_v10_0_gfx_mqd_init(struct amdgpu_ring *ring)
6524 {
6525         struct amdgpu_device *adev = ring->adev;
6526         struct v10_gfx_mqd *mqd = ring->mqd_ptr;
6527         uint64_t hqd_gpu_addr, wb_gpu_addr;
6528         uint32_t tmp;
6529         uint32_t rb_bufsz;
6530
6531         /* set up gfx hqd wptr */
6532         mqd->cp_gfx_hqd_wptr = 0;
6533         mqd->cp_gfx_hqd_wptr_hi = 0;
6534
6535         /* set the pointer to the MQD */
6536         mqd->cp_mqd_base_addr = ring->mqd_gpu_addr & 0xfffffffc;
6537         mqd->cp_mqd_base_addr_hi = upper_32_bits(ring->mqd_gpu_addr);
6538
6539         /* set up mqd control */
6540         tmp = RREG32_SOC15(GC, 0, mmCP_GFX_MQD_CONTROL);
6541         tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, VMID, 0);
6542         tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, PRIV_STATE, 1);
6543         tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, CACHE_POLICY, 0);
6544         mqd->cp_gfx_mqd_control = tmp;
6545
6546         /* set up gfx_hqd_vimd with 0x0 to indicate the ring buffer's vmid */
6547         tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_VMID);
6548         tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_VMID, VMID, 0);
6549         mqd->cp_gfx_hqd_vmid = 0;
6550
6551         /* set up default queue priority level
6552          * 0x0 = low priority, 0x1 = high priority */
6553         tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_QUEUE_PRIORITY);
6554         tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_QUEUE_PRIORITY, PRIORITY_LEVEL, 0);
6555         mqd->cp_gfx_hqd_queue_priority = tmp;
6556
6557         /* set up time quantum */
6558         tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_QUANTUM);
6559         tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_QUANTUM, QUANTUM_EN, 1);
6560         mqd->cp_gfx_hqd_quantum = tmp;
6561
6562         /* set up gfx hqd base. this is similar as CP_RB_BASE */
6563         hqd_gpu_addr = ring->gpu_addr >> 8;
6564         mqd->cp_gfx_hqd_base = hqd_gpu_addr;
6565         mqd->cp_gfx_hqd_base_hi = upper_32_bits(hqd_gpu_addr);
6566
6567         /* set up hqd_rptr_addr/_hi, similar as CP_RB_RPTR */
6568         wb_gpu_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
6569         mqd->cp_gfx_hqd_rptr_addr = wb_gpu_addr & 0xfffffffc;
6570         mqd->cp_gfx_hqd_rptr_addr_hi =
6571                 upper_32_bits(wb_gpu_addr) & 0xffff;
6572
6573         /* set up rb_wptr_poll addr */
6574         wb_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
6575         mqd->cp_rb_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc;
6576         mqd->cp_rb_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff;
6577
6578         /* set up the gfx_hqd_control, similar as CP_RB0_CNTL */
6579         rb_bufsz = order_base_2(ring->ring_size / 4) - 1;
6580         tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_CNTL);
6581         tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_BUFSZ, rb_bufsz);
6582         tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_BLKSZ, rb_bufsz - 2);
6583 #ifdef __BIG_ENDIAN
6584         tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, BUF_SWAP, 1);
6585 #endif
6586         mqd->cp_gfx_hqd_cntl = tmp;
6587
6588         /* set up cp_doorbell_control */
6589         tmp = RREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL);
6590         if (ring->use_doorbell) {
6591                 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
6592                                     DOORBELL_OFFSET, ring->doorbell_index);
6593                 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
6594                                     DOORBELL_EN, 1);
6595         } else
6596                 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
6597                                     DOORBELL_EN, 0);
6598         mqd->cp_rb_doorbell_control = tmp;
6599
6600         /*if there are 2 gfx rings, set the lower doorbell range of the first ring,
6601          *otherwise the range of the second ring will override the first ring */
6602         if (ring->doorbell_index == adev->doorbell_index.gfx_ring0 << 1)
6603                 gfx_v10_0_cp_gfx_set_doorbell(adev, ring);
6604
6605         /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */
6606         ring->wptr = 0;
6607         mqd->cp_gfx_hqd_rptr = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_RPTR);
6608
6609         /* active the queue */
6610         mqd->cp_gfx_hqd_active = 1;
6611
6612         return 0;
6613 }
6614
6615 #ifdef BRING_UP_DEBUG
6616 static int gfx_v10_0_gfx_queue_init_register(struct amdgpu_ring *ring)
6617 {
6618         struct amdgpu_device *adev = ring->adev;
6619         struct v10_gfx_mqd *mqd = ring->mqd_ptr;
6620
6621         /* set mmCP_GFX_HQD_WPTR/_HI to 0 */
6622         WREG32_SOC15(GC, 0, mmCP_GFX_HQD_WPTR, mqd->cp_gfx_hqd_wptr);
6623         WREG32_SOC15(GC, 0, mmCP_GFX_HQD_WPTR_HI, mqd->cp_gfx_hqd_wptr_hi);
6624
6625         /* set GFX_MQD_BASE */
6626         WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR, mqd->cp_mqd_base_addr);
6627         WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR_HI, mqd->cp_mqd_base_addr_hi);
6628
6629         /* set GFX_MQD_CONTROL */
6630         WREG32_SOC15(GC, 0, mmCP_GFX_MQD_CONTROL, mqd->cp_gfx_mqd_control);
6631
6632         /* set GFX_HQD_VMID to 0 */
6633         WREG32_SOC15(GC, 0, mmCP_GFX_HQD_VMID, mqd->cp_gfx_hqd_vmid);
6634
6635         WREG32_SOC15(GC, 0, mmCP_GFX_HQD_QUEUE_PRIORITY,
6636                         mqd->cp_gfx_hqd_queue_priority);
6637         WREG32_SOC15(GC, 0, mmCP_GFX_HQD_QUANTUM, mqd->cp_gfx_hqd_quantum);
6638
6639         /* set GFX_HQD_BASE, similar as CP_RB_BASE */
6640         WREG32_SOC15(GC, 0, mmCP_GFX_HQD_BASE, mqd->cp_gfx_hqd_base);
6641         WREG32_SOC15(GC, 0, mmCP_GFX_HQD_BASE_HI, mqd->cp_gfx_hqd_base_hi);
6642
6643         /* set GFX_HQD_RPTR_ADDR, similar as CP_RB_RPTR */
6644         WREG32_SOC15(GC, 0, mmCP_GFX_HQD_RPTR_ADDR, mqd->cp_gfx_hqd_rptr_addr);
6645         WREG32_SOC15(GC, 0, mmCP_GFX_HQD_RPTR_ADDR_HI, mqd->cp_gfx_hqd_rptr_addr_hi);
6646
6647         /* set GFX_HQD_CNTL, similar as CP_RB_CNTL */
6648         WREG32_SOC15(GC, 0, mmCP_GFX_HQD_CNTL, mqd->cp_gfx_hqd_cntl);
6649
6650         /* set RB_WPTR_POLL_ADDR */
6651         WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_LO, mqd->cp_rb_wptr_poll_addr_lo);
6652         WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI, mqd->cp_rb_wptr_poll_addr_hi);
6653
6654         /* set RB_DOORBELL_CONTROL */
6655         WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL, mqd->cp_rb_doorbell_control);
6656
6657         /* active the queue */
6658         WREG32_SOC15(GC, 0, mmCP_GFX_HQD_ACTIVE, mqd->cp_gfx_hqd_active);
6659
6660         return 0;
6661 }
6662 #endif
6663
6664 static int gfx_v10_0_gfx_init_queue(struct amdgpu_ring *ring)
6665 {
6666         struct amdgpu_device *adev = ring->adev;
6667         struct v10_gfx_mqd *mqd = ring->mqd_ptr;
6668         int mqd_idx = ring - &adev->gfx.gfx_ring[0];
6669
6670         if (!amdgpu_in_reset(adev) && !adev->in_suspend) {
6671                 memset((void *)mqd, 0, sizeof(*mqd));
6672                 mutex_lock(&adev->srbm_mutex);
6673                 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
6674                 gfx_v10_0_gfx_mqd_init(ring);
6675 #ifdef BRING_UP_DEBUG
6676                 gfx_v10_0_gfx_queue_init_register(ring);
6677 #endif
6678                 nv_grbm_select(adev, 0, 0, 0, 0);
6679                 mutex_unlock(&adev->srbm_mutex);
6680                 if (adev->gfx.me.mqd_backup[mqd_idx])
6681                         memcpy(adev->gfx.me.mqd_backup[mqd_idx], mqd, sizeof(*mqd));
6682         } else if (amdgpu_in_reset(adev)) {
6683                 /* reset mqd with the backup copy */
6684                 if (adev->gfx.me.mqd_backup[mqd_idx])
6685                         memcpy(mqd, adev->gfx.me.mqd_backup[mqd_idx], sizeof(*mqd));
6686                 /* reset the ring */
6687                 ring->wptr = 0;
6688                 adev->wb.wb[ring->wptr_offs] = 0;
6689                 amdgpu_ring_clear_ring(ring);
6690 #ifdef BRING_UP_DEBUG
6691                 mutex_lock(&adev->srbm_mutex);
6692                 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
6693                 gfx_v10_0_gfx_queue_init_register(ring);
6694                 nv_grbm_select(adev, 0, 0, 0, 0);
6695                 mutex_unlock(&adev->srbm_mutex);
6696 #endif
6697         } else {
6698                 amdgpu_ring_clear_ring(ring);
6699         }
6700
6701         return 0;
6702 }
6703
6704 #ifndef BRING_UP_DEBUG
6705 static int gfx_v10_0_kiq_enable_kgq(struct amdgpu_device *adev)
6706 {
6707         struct amdgpu_kiq *kiq = &adev->gfx.kiq;
6708         struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring;
6709         int r, i;
6710
6711         if (!kiq->pmf || !kiq->pmf->kiq_map_queues)
6712                 return -EINVAL;
6713
6714         r = amdgpu_ring_alloc(kiq_ring, kiq->pmf->map_queues_size *
6715                                         adev->gfx.num_gfx_rings);
6716         if (r) {
6717                 DRM_ERROR("Failed to lock KIQ (%d).\n", r);
6718                 return r;
6719         }
6720
6721         for (i = 0; i < adev->gfx.num_gfx_rings; i++)
6722                 kiq->pmf->kiq_map_queues(kiq_ring, &adev->gfx.gfx_ring[i]);
6723
6724         return amdgpu_ring_test_helper(kiq_ring);
6725 }
6726 #endif
6727
6728 static int gfx_v10_0_cp_async_gfx_ring_resume(struct amdgpu_device *adev)
6729 {
6730         int r, i;
6731         struct amdgpu_ring *ring;
6732
6733         for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
6734                 ring = &adev->gfx.gfx_ring[i];
6735
6736                 r = amdgpu_bo_reserve(ring->mqd_obj, false);
6737                 if (unlikely(r != 0))
6738                         goto done;
6739
6740                 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr);
6741                 if (!r) {
6742                         r = gfx_v10_0_gfx_init_queue(ring);
6743                         amdgpu_bo_kunmap(ring->mqd_obj);
6744                         ring->mqd_ptr = NULL;
6745                 }
6746                 amdgpu_bo_unreserve(ring->mqd_obj);
6747                 if (r)
6748                         goto done;
6749         }
6750 #ifndef BRING_UP_DEBUG
6751         r = gfx_v10_0_kiq_enable_kgq(adev);
6752         if (r)
6753                 goto done;
6754 #endif
6755         r = gfx_v10_0_cp_gfx_start(adev);
6756         if (r)
6757                 goto done;
6758
6759         for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
6760                 ring = &adev->gfx.gfx_ring[i];
6761                 ring->sched.ready = true;
6762         }
6763 done:
6764         return r;
6765 }
6766
6767 static void gfx_v10_0_compute_mqd_set_priority(struct amdgpu_ring *ring, struct v10_compute_mqd *mqd)
6768 {
6769         struct amdgpu_device *adev = ring->adev;
6770
6771         if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) {
6772                 if (amdgpu_gfx_is_high_priority_compute_queue(adev, ring)) {
6773                         mqd->cp_hqd_pipe_priority = AMDGPU_GFX_PIPE_PRIO_HIGH;
6774                         mqd->cp_hqd_queue_priority =
6775                                 AMDGPU_GFX_QUEUE_PRIORITY_MAXIMUM;
6776                 }
6777         }
6778 }
6779
6780 static int gfx_v10_0_compute_mqd_init(struct amdgpu_ring *ring)
6781 {
6782         struct amdgpu_device *adev = ring->adev;
6783         struct v10_compute_mqd *mqd = ring->mqd_ptr;
6784         uint64_t hqd_gpu_addr, wb_gpu_addr, eop_base_addr;
6785         uint32_t tmp;
6786
6787         mqd->header = 0xC0310800;
6788         mqd->compute_pipelinestat_enable = 0x00000001;
6789         mqd->compute_static_thread_mgmt_se0 = 0xffffffff;
6790         mqd->compute_static_thread_mgmt_se1 = 0xffffffff;
6791         mqd->compute_static_thread_mgmt_se2 = 0xffffffff;
6792         mqd->compute_static_thread_mgmt_se3 = 0xffffffff;
6793         mqd->compute_misc_reserved = 0x00000003;
6794
6795         eop_base_addr = ring->eop_gpu_addr >> 8;
6796         mqd->cp_hqd_eop_base_addr_lo = eop_base_addr;
6797         mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr);
6798
6799         /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */
6800         tmp = RREG32_SOC15(GC, 0, mmCP_HQD_EOP_CONTROL);
6801         tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE,
6802                         (order_base_2(GFX10_MEC_HPD_SIZE / 4) - 1));
6803
6804         mqd->cp_hqd_eop_control = tmp;
6805
6806         /* enable doorbell? */
6807         tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL);
6808
6809         if (ring->use_doorbell) {
6810                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
6811                                     DOORBELL_OFFSET, ring->doorbell_index);
6812                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
6813                                     DOORBELL_EN, 1);
6814                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
6815                                     DOORBELL_SOURCE, 0);
6816                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
6817                                     DOORBELL_HIT, 0);
6818         } else {
6819                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
6820                                     DOORBELL_EN, 0);
6821         }
6822
6823         mqd->cp_hqd_pq_doorbell_control = tmp;
6824
6825         /* disable the queue if it's active */
6826         ring->wptr = 0;
6827         mqd->cp_hqd_dequeue_request = 0;
6828         mqd->cp_hqd_pq_rptr = 0;
6829         mqd->cp_hqd_pq_wptr_lo = 0;
6830         mqd->cp_hqd_pq_wptr_hi = 0;
6831
6832         /* set the pointer to the MQD */
6833         mqd->cp_mqd_base_addr_lo = ring->mqd_gpu_addr & 0xfffffffc;
6834         mqd->cp_mqd_base_addr_hi = upper_32_bits(ring->mqd_gpu_addr);
6835
6836         /* set MQD vmid to 0 */
6837         tmp = RREG32_SOC15(GC, 0, mmCP_MQD_CONTROL);
6838         tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0);
6839         mqd->cp_mqd_control = tmp;
6840
6841         /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */
6842         hqd_gpu_addr = ring->gpu_addr >> 8;
6843         mqd->cp_hqd_pq_base_lo = hqd_gpu_addr;
6844         mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr);
6845
6846         /* set up the HQD, this is similar to CP_RB0_CNTL */
6847         tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_CONTROL);
6848         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE,
6849                             (order_base_2(ring->ring_size / 4) - 1));
6850         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE,
6851                             ((order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1) << 8));
6852 #ifdef __BIG_ENDIAN
6853         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ENDIAN_SWAP, 1);
6854 #endif
6855         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 0);
6856         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, TUNNEL_DISPATCH, 0);
6857         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1);
6858         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1);
6859         mqd->cp_hqd_pq_control = tmp;
6860
6861         /* set the wb address whether it's enabled or not */
6862         wb_gpu_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
6863         mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc;
6864         mqd->cp_hqd_pq_rptr_report_addr_hi =
6865                 upper_32_bits(wb_gpu_addr) & 0xffff;
6866
6867         /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */
6868         wb_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
6869         mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc;
6870         mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff;
6871
6872         tmp = 0;
6873         /* enable the doorbell if requested */
6874         if (ring->use_doorbell) {
6875                 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL);
6876                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
6877                                 DOORBELL_OFFSET, ring->doorbell_index);
6878
6879                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
6880                                     DOORBELL_EN, 1);
6881                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
6882                                     DOORBELL_SOURCE, 0);
6883                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
6884                                     DOORBELL_HIT, 0);
6885         }
6886
6887         mqd->cp_hqd_pq_doorbell_control = tmp;
6888
6889         /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */
6890         ring->wptr = 0;
6891         mqd->cp_hqd_pq_rptr = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR);
6892
6893         /* set the vmid for the queue */
6894         mqd->cp_hqd_vmid = 0;
6895
6896         tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PERSISTENT_STATE);
6897         tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, PRELOAD_SIZE, 0x53);
6898         mqd->cp_hqd_persistent_state = tmp;
6899
6900         /* set MIN_IB_AVAIL_SIZE */
6901         tmp = RREG32_SOC15(GC, 0, mmCP_HQD_IB_CONTROL);
6902         tmp = REG_SET_FIELD(tmp, CP_HQD_IB_CONTROL, MIN_IB_AVAIL_SIZE, 3);
6903         mqd->cp_hqd_ib_control = tmp;
6904
6905         /* set static priority for a compute queue/ring */
6906         gfx_v10_0_compute_mqd_set_priority(ring, mqd);
6907
6908         /* map_queues packet doesn't need activate the queue,
6909          * so only kiq need set this field.
6910          */
6911         if (ring->funcs->type == AMDGPU_RING_TYPE_KIQ)
6912                 mqd->cp_hqd_active = 1;
6913
6914         return 0;
6915 }
6916
6917 static int gfx_v10_0_kiq_init_register(struct amdgpu_ring *ring)
6918 {
6919         struct amdgpu_device *adev = ring->adev;
6920         struct v10_compute_mqd *mqd = ring->mqd_ptr;
6921         int j;
6922
6923         /* inactivate the queue */
6924         if (amdgpu_sriov_vf(adev))
6925                 WREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE, 0);
6926
6927         /* disable wptr polling */
6928         WREG32_FIELD15(GC, 0, CP_PQ_WPTR_POLL_CNTL, EN, 0);
6929
6930         /* write the EOP addr */
6931         WREG32_SOC15(GC, 0, mmCP_HQD_EOP_BASE_ADDR,
6932                mqd->cp_hqd_eop_base_addr_lo);
6933         WREG32_SOC15(GC, 0, mmCP_HQD_EOP_BASE_ADDR_HI,
6934                mqd->cp_hqd_eop_base_addr_hi);
6935
6936         /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */
6937         WREG32_SOC15(GC, 0, mmCP_HQD_EOP_CONTROL,
6938                mqd->cp_hqd_eop_control);
6939
6940         /* enable doorbell? */
6941         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL,
6942                mqd->cp_hqd_pq_doorbell_control);
6943
6944         /* disable the queue if it's active */
6945         if (RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1) {
6946                 WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST, 1);
6947                 for (j = 0; j < adev->usec_timeout; j++) {
6948                         if (!(RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1))
6949                                 break;
6950                         udelay(1);
6951                 }
6952                 WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST,
6953                        mqd->cp_hqd_dequeue_request);
6954                 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR,
6955                        mqd->cp_hqd_pq_rptr);
6956                 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_LO,
6957                        mqd->cp_hqd_pq_wptr_lo);
6958                 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_HI,
6959                        mqd->cp_hqd_pq_wptr_hi);
6960         }
6961
6962         /* set the pointer to the MQD */
6963         WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR,
6964                mqd->cp_mqd_base_addr_lo);
6965         WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR_HI,
6966                mqd->cp_mqd_base_addr_hi);
6967
6968         /* set MQD vmid to 0 */
6969         WREG32_SOC15(GC, 0, mmCP_MQD_CONTROL,
6970                mqd->cp_mqd_control);
6971
6972         /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */
6973         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_BASE,
6974                mqd->cp_hqd_pq_base_lo);
6975         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_BASE_HI,
6976                mqd->cp_hqd_pq_base_hi);
6977
6978         /* set up the HQD, this is similar to CP_RB0_CNTL */
6979         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_CONTROL,
6980                mqd->cp_hqd_pq_control);
6981
6982         /* set the wb address whether it's enabled or not */
6983         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR_REPORT_ADDR,
6984                 mqd->cp_hqd_pq_rptr_report_addr_lo);
6985         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI,
6986                 mqd->cp_hqd_pq_rptr_report_addr_hi);
6987
6988         /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */
6989         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR,
6990                mqd->cp_hqd_pq_wptr_poll_addr_lo);
6991         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR_HI,
6992                mqd->cp_hqd_pq_wptr_poll_addr_hi);
6993
6994         /* enable the doorbell if requested */
6995         if (ring->use_doorbell) {
6996                 WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_LOWER,
6997                         (adev->doorbell_index.kiq * 2) << 2);
6998                 WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_UPPER,
6999                         (adev->doorbell_index.userqueue_end * 2) << 2);
7000         }
7001
7002         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL,
7003                mqd->cp_hqd_pq_doorbell_control);
7004
7005         /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */
7006         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_LO,
7007                mqd->cp_hqd_pq_wptr_lo);
7008         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_HI,
7009                mqd->cp_hqd_pq_wptr_hi);
7010
7011         /* set the vmid for the queue */
7012         WREG32_SOC15(GC, 0, mmCP_HQD_VMID, mqd->cp_hqd_vmid);
7013
7014         WREG32_SOC15(GC, 0, mmCP_HQD_PERSISTENT_STATE,
7015                mqd->cp_hqd_persistent_state);
7016
7017         /* activate the queue */
7018         WREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE,
7019                mqd->cp_hqd_active);
7020
7021         if (ring->use_doorbell)
7022                 WREG32_FIELD15(GC, 0, CP_PQ_STATUS, DOORBELL_ENABLE, 1);
7023
7024         return 0;
7025 }
7026
7027 static int gfx_v10_0_kiq_init_queue(struct amdgpu_ring *ring)
7028 {
7029         struct amdgpu_device *adev = ring->adev;
7030         struct v10_compute_mqd *mqd = ring->mqd_ptr;
7031         int mqd_idx = AMDGPU_MAX_COMPUTE_RINGS;
7032
7033         gfx_v10_0_kiq_setting(ring);
7034
7035         if (amdgpu_in_reset(adev)) { /* for GPU_RESET case */
7036                 /* reset MQD to a clean status */
7037                 if (adev->gfx.mec.mqd_backup[mqd_idx])
7038                         memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(*mqd));
7039
7040                 /* reset ring buffer */
7041                 ring->wptr = 0;
7042                 amdgpu_ring_clear_ring(ring);
7043
7044                 mutex_lock(&adev->srbm_mutex);
7045                 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
7046                 gfx_v10_0_kiq_init_register(ring);
7047                 nv_grbm_select(adev, 0, 0, 0, 0);
7048                 mutex_unlock(&adev->srbm_mutex);
7049         } else {
7050                 memset((void *)mqd, 0, sizeof(*mqd));
7051                 mutex_lock(&adev->srbm_mutex);
7052                 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
7053                 gfx_v10_0_compute_mqd_init(ring);
7054                 gfx_v10_0_kiq_init_register(ring);
7055                 nv_grbm_select(adev, 0, 0, 0, 0);
7056                 mutex_unlock(&adev->srbm_mutex);
7057
7058                 if (adev->gfx.mec.mqd_backup[mqd_idx])
7059                         memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(*mqd));
7060         }
7061
7062         return 0;
7063 }
7064
7065 static int gfx_v10_0_kcq_init_queue(struct amdgpu_ring *ring)
7066 {
7067         struct amdgpu_device *adev = ring->adev;
7068         struct v10_compute_mqd *mqd = ring->mqd_ptr;
7069         int mqd_idx = ring - &adev->gfx.compute_ring[0];
7070
7071         if (!amdgpu_in_reset(adev) && !adev->in_suspend) {
7072                 memset((void *)mqd, 0, sizeof(*mqd));
7073                 mutex_lock(&adev->srbm_mutex);
7074                 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
7075                 gfx_v10_0_compute_mqd_init(ring);
7076                 nv_grbm_select(adev, 0, 0, 0, 0);
7077                 mutex_unlock(&adev->srbm_mutex);
7078
7079                 if (adev->gfx.mec.mqd_backup[mqd_idx])
7080                         memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(*mqd));
7081         } else if (amdgpu_in_reset(adev)) { /* for GPU_RESET case */
7082                 /* reset MQD to a clean status */
7083                 if (adev->gfx.mec.mqd_backup[mqd_idx])
7084                         memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(*mqd));
7085
7086                 /* reset ring buffer */
7087                 ring->wptr = 0;
7088                 atomic64_set((atomic64_t *)&adev->wb.wb[ring->wptr_offs], 0);
7089                 amdgpu_ring_clear_ring(ring);
7090         } else {
7091                 amdgpu_ring_clear_ring(ring);
7092         }
7093
7094         return 0;
7095 }
7096
7097 static int gfx_v10_0_kiq_resume(struct amdgpu_device *adev)
7098 {
7099         struct amdgpu_ring *ring;
7100         int r;
7101
7102         ring = &adev->gfx.kiq.ring;
7103
7104         r = amdgpu_bo_reserve(ring->mqd_obj, false);
7105         if (unlikely(r != 0))
7106                 return r;
7107
7108         r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr);
7109         if (unlikely(r != 0))
7110                 return r;
7111
7112         gfx_v10_0_kiq_init_queue(ring);
7113         amdgpu_bo_kunmap(ring->mqd_obj);
7114         ring->mqd_ptr = NULL;
7115         amdgpu_bo_unreserve(ring->mqd_obj);
7116         ring->sched.ready = true;
7117         return 0;
7118 }
7119
7120 static int gfx_v10_0_kcq_resume(struct amdgpu_device *adev)
7121 {
7122         struct amdgpu_ring *ring = NULL;
7123         int r = 0, i;
7124
7125         gfx_v10_0_cp_compute_enable(adev, true);
7126
7127         for (i = 0; i < adev->gfx.num_compute_rings; i++) {
7128                 ring = &adev->gfx.compute_ring[i];
7129
7130                 r = amdgpu_bo_reserve(ring->mqd_obj, false);
7131                 if (unlikely(r != 0))
7132                         goto done;
7133                 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr);
7134                 if (!r) {
7135                         r = gfx_v10_0_kcq_init_queue(ring);
7136                         amdgpu_bo_kunmap(ring->mqd_obj);
7137                         ring->mqd_ptr = NULL;
7138                 }
7139                 amdgpu_bo_unreserve(ring->mqd_obj);
7140                 if (r)
7141                         goto done;
7142         }
7143
7144         r = amdgpu_gfx_enable_kcq(adev);
7145 done:
7146         return r;
7147 }
7148
7149 static int gfx_v10_0_cp_resume(struct amdgpu_device *adev)
7150 {
7151         int r, i;
7152         struct amdgpu_ring *ring;
7153
7154         if (!(adev->flags & AMD_IS_APU))
7155                 gfx_v10_0_enable_gui_idle_interrupt(adev, false);
7156
7157         if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
7158                 /* legacy firmware loading */
7159                 r = gfx_v10_0_cp_gfx_load_microcode(adev);
7160                 if (r)
7161                         return r;
7162
7163                 r = gfx_v10_0_cp_compute_load_microcode(adev);
7164                 if (r)
7165                         return r;
7166         }
7167
7168         r = gfx_v10_0_kiq_resume(adev);
7169         if (r)
7170                 return r;
7171
7172         r = gfx_v10_0_kcq_resume(adev);
7173         if (r)
7174                 return r;
7175
7176         if (!amdgpu_async_gfx_ring) {
7177                 r = gfx_v10_0_cp_gfx_resume(adev);
7178                 if (r)
7179                         return r;
7180         } else {
7181                 r = gfx_v10_0_cp_async_gfx_ring_resume(adev);
7182                 if (r)
7183                         return r;
7184         }
7185
7186         for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
7187                 ring = &adev->gfx.gfx_ring[i];
7188                 r = amdgpu_ring_test_helper(ring);
7189                 if (r)
7190                         return r;
7191         }
7192
7193         for (i = 0; i < adev->gfx.num_compute_rings; i++) {
7194                 ring = &adev->gfx.compute_ring[i];
7195                 r = amdgpu_ring_test_helper(ring);
7196                 if (r)
7197                         return r;
7198         }
7199
7200         return 0;
7201 }
7202
7203 static void gfx_v10_0_cp_enable(struct amdgpu_device *adev, bool enable)
7204 {
7205         gfx_v10_0_cp_gfx_enable(adev, enable);
7206         gfx_v10_0_cp_compute_enable(adev, enable);
7207 }
7208
7209 static bool gfx_v10_0_check_grbm_cam_remapping(struct amdgpu_device *adev)
7210 {
7211         uint32_t data, pattern = 0xDEADBEEF;
7212
7213         /* check if mmVGT_ESGS_RING_SIZE_UMD
7214          * has been remapped to mmVGT_ESGS_RING_SIZE */
7215         switch (adev->ip_versions[GC_HWIP][0]) {
7216         case IP_VERSION(10, 3, 0):
7217         case IP_VERSION(10, 3, 2):
7218         case IP_VERSION(10, 3, 4):
7219         case IP_VERSION(10, 3, 5):
7220                 data = RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid);
7221                 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid, 0);
7222                 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_UMD, pattern);
7223
7224                 if (RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid) == pattern) {
7225                         WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_UMD , data);
7226                         return true;
7227                 } else {
7228                         WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid, data);
7229                         return false;
7230                 }
7231                 break;
7232         case IP_VERSION(10, 3, 1):
7233         case IP_VERSION(10, 3, 3):
7234         case IP_VERSION(10, 3, 7):
7235                 return true;
7236         default:
7237                 data = RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE);
7238                 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE, 0);
7239                 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_UMD, pattern);
7240
7241                 if (RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE) == pattern) {
7242                         WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_UMD, data);
7243                         return true;
7244                 } else {
7245                         WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE, data);
7246                         return false;
7247                 }
7248                 break;
7249         }
7250 }
7251
7252 static void gfx_v10_0_setup_grbm_cam_remapping(struct amdgpu_device *adev)
7253 {
7254         uint32_t data;
7255
7256         if (amdgpu_sriov_vf(adev))
7257                 return;
7258
7259         /* initialize cam_index to 0
7260          * index will auto-inc after each data writting */
7261         WREG32_SOC15(GC, 0, mmGRBM_CAM_INDEX, 0);
7262
7263         switch (adev->ip_versions[GC_HWIP][0]) {
7264         case IP_VERSION(10, 3, 0):
7265         case IP_VERSION(10, 3, 2):
7266         case IP_VERSION(10, 3, 1):
7267         case IP_VERSION(10, 3, 4):
7268         case IP_VERSION(10, 3, 5):
7269         case IP_VERSION(10, 3, 3):
7270         case IP_VERSION(10, 3, 7):
7271                 /* mmVGT_TF_RING_SIZE_UMD -> mmVGT_TF_RING_SIZE */
7272                 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE_UMD) <<
7273                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7274                        (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE_Sienna_Cichlid) <<
7275                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7276                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7277                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7278
7279                 /* mmVGT_TF_MEMORY_BASE_UMD -> mmVGT_TF_MEMORY_BASE */
7280                 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_UMD) <<
7281                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7282                        (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_Sienna_Cichlid) <<
7283                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7284                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7285                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7286
7287                 /* mmVGT_TF_MEMORY_BASE_HI_UMD -> mmVGT_TF_MEMORY_BASE_HI */
7288                 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI_UMD) <<
7289                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7290                        (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI_Sienna_Cichlid) <<
7291                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7292                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7293                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7294
7295                 /* mmVGT_HS_OFFCHIP_PARAM_UMD -> mmVGT_HS_OFFCHIP_PARAM */
7296                 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM_UMD) <<
7297                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7298                        (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM_Sienna_Cichlid) <<
7299                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7300                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7301                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7302
7303                 /* mmVGT_ESGS_RING_SIZE_UMD -> mmVGT_ESGS_RING_SIZE */
7304                 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE_UMD) <<
7305                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7306                        (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid) <<
7307                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7308                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7309                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7310
7311                 /* mmVGT_GSVS_RING_SIZE_UMD -> mmVGT_GSVS_RING_SIZE */
7312                 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE_UMD) <<
7313                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7314                        (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE_Sienna_Cichlid) <<
7315                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7316                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7317                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7318
7319                 /* mmSPI_CONFIG_CNTL_REMAP -> mmSPI_CONFIG_CNTL */
7320                 data = (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL_REMAP) <<
7321                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7322                        (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL_Sienna_Cichlid) <<
7323                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7324                 break;
7325         default:
7326                 /* mmVGT_TF_RING_SIZE_UMD -> mmVGT_TF_RING_SIZE */
7327                 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE_UMD) <<
7328                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7329                        (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE) <<
7330                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7331                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7332                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7333
7334                 /* mmVGT_TF_MEMORY_BASE_UMD -> mmVGT_TF_MEMORY_BASE */
7335                 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_UMD) <<
7336                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7337                        (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE) <<
7338                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7339                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7340                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7341
7342                 /* mmVGT_TF_MEMORY_BASE_HI_UMD -> mmVGT_TF_MEMORY_BASE_HI */
7343                 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI_UMD) <<
7344                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7345                        (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI) <<
7346                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7347                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7348                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7349
7350                 /* mmVGT_HS_OFFCHIP_PARAM_UMD -> mmVGT_HS_OFFCHIP_PARAM */
7351                 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM_UMD) <<
7352                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7353                        (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM) <<
7354                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7355                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7356                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7357
7358                 /* mmVGT_ESGS_RING_SIZE_UMD -> mmVGT_ESGS_RING_SIZE */
7359                 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE_UMD) <<
7360                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7361                        (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE) <<
7362                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7363                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7364                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7365
7366                 /* mmVGT_GSVS_RING_SIZE_UMD -> mmVGT_GSVS_RING_SIZE */
7367                 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE_UMD) <<
7368                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7369                        (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE) <<
7370                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7371                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7372                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7373
7374                 /* mmSPI_CONFIG_CNTL_REMAP -> mmSPI_CONFIG_CNTL */
7375                 data = (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL_REMAP) <<
7376                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7377                        (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL) <<
7378                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7379                 break;
7380         }
7381
7382         WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7383         WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7384 }
7385
7386 static void gfx_v10_0_disable_gpa_mode(struct amdgpu_device *adev)
7387 {
7388         uint32_t data;
7389         data = RREG32_SOC15(GC, 0, mmCPC_PSP_DEBUG);
7390         data |= CPC_PSP_DEBUG__GPA_OVERRIDE_MASK;
7391         WREG32_SOC15(GC, 0, mmCPC_PSP_DEBUG, data);
7392
7393         data = RREG32_SOC15(GC, 0, mmCPG_PSP_DEBUG);
7394         data |= CPG_PSP_DEBUG__GPA_OVERRIDE_MASK;
7395         WREG32_SOC15(GC, 0, mmCPG_PSP_DEBUG, data);
7396 }
7397
7398 static int gfx_v10_0_hw_init(void *handle)
7399 {
7400         int r;
7401         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7402
7403         if (!amdgpu_emu_mode)
7404                 gfx_v10_0_init_golden_registers(adev);
7405
7406         if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
7407                 /**
7408                  * For gfx 10, rlc firmware loading relies on smu firmware is
7409                  * loaded firstly, so in direct type, it has to load smc ucode
7410                  * here before rlc.
7411                  */
7412                 if (!(adev->flags & AMD_IS_APU)) {
7413                         r = amdgpu_pm_load_smu_firmware(adev, NULL);
7414                         if (r)
7415                                 return r;
7416                 }
7417                 gfx_v10_0_disable_gpa_mode(adev);
7418         }
7419
7420         /* if GRBM CAM not remapped, set up the remapping */
7421         if (!gfx_v10_0_check_grbm_cam_remapping(adev))
7422                 gfx_v10_0_setup_grbm_cam_remapping(adev);
7423
7424         gfx_v10_0_constants_init(adev);
7425
7426         r = gfx_v10_0_rlc_resume(adev);
7427         if (r)
7428                 return r;
7429
7430         /*
7431          * init golden registers and rlc resume may override some registers,
7432          * reconfig them here
7433          */
7434         if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 1, 10) ||
7435             adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 1, 1) ||
7436             adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 1, 2))
7437                 gfx_v10_0_tcp_harvest(adev);
7438
7439         r = gfx_v10_0_cp_resume(adev);
7440         if (r)
7441                 return r;
7442
7443         if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 3, 0))
7444                 gfx_v10_3_program_pbb_mode(adev);
7445
7446         if (adev->ip_versions[GC_HWIP][0] >= IP_VERSION(10, 3, 0))
7447                 gfx_v10_3_set_power_brake_sequence(adev);
7448
7449         return r;
7450 }
7451
7452 #ifndef BRING_UP_DEBUG
7453 static int gfx_v10_0_kiq_disable_kgq(struct amdgpu_device *adev)
7454 {
7455         struct amdgpu_kiq *kiq = &adev->gfx.kiq;
7456         struct amdgpu_ring *kiq_ring = &kiq->ring;
7457         int i;
7458
7459         if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues)
7460                 return -EINVAL;
7461
7462         if (amdgpu_ring_alloc(kiq_ring, kiq->pmf->unmap_queues_size *
7463                                         adev->gfx.num_gfx_rings))
7464                 return -ENOMEM;
7465
7466         for (i = 0; i < adev->gfx.num_gfx_rings; i++)
7467                 kiq->pmf->kiq_unmap_queues(kiq_ring, &adev->gfx.gfx_ring[i],
7468                                            PREEMPT_QUEUES, 0, 0);
7469
7470         return amdgpu_ring_test_helper(kiq_ring);
7471 }
7472 #endif
7473
7474 static int gfx_v10_0_hw_fini(void *handle)
7475 {
7476         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7477         int r;
7478         uint32_t tmp;
7479
7480         amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0);
7481         amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0);
7482
7483         if (!adev->no_hw_access) {
7484 #ifndef BRING_UP_DEBUG
7485                 if (amdgpu_async_gfx_ring) {
7486                         r = gfx_v10_0_kiq_disable_kgq(adev);
7487                         if (r)
7488                                 DRM_ERROR("KGQ disable failed\n");
7489                 }
7490 #endif
7491                 if (amdgpu_gfx_disable_kcq(adev))
7492                         DRM_ERROR("KCQ disable failed\n");
7493         }
7494
7495         if (amdgpu_sriov_vf(adev)) {
7496                 gfx_v10_0_cp_gfx_enable(adev, false);
7497                 /* Program KIQ position of RLC_CP_SCHEDULERS during destroy */
7498                 if (adev->ip_versions[GC_HWIP][0] >= IP_VERSION(10, 3, 0)) {
7499                         tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS_Sienna_Cichlid);
7500                         tmp &= 0xffffff00;
7501                         WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS_Sienna_Cichlid, tmp);
7502                 } else {
7503                         tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS);
7504                         tmp &= 0xffffff00;
7505                         WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS, tmp);
7506                 }
7507
7508                 return 0;
7509         }
7510         gfx_v10_0_cp_enable(adev, false);
7511         gfx_v10_0_enable_gui_idle_interrupt(adev, false);
7512
7513         return 0;
7514 }
7515
7516 static int gfx_v10_0_suspend(void *handle)
7517 {
7518         return gfx_v10_0_hw_fini(handle);
7519 }
7520
7521 static int gfx_v10_0_resume(void *handle)
7522 {
7523         return gfx_v10_0_hw_init(handle);
7524 }
7525
7526 static bool gfx_v10_0_is_idle(void *handle)
7527 {
7528         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7529
7530         if (REG_GET_FIELD(RREG32_SOC15(GC, 0, mmGRBM_STATUS),
7531                                 GRBM_STATUS, GUI_ACTIVE))
7532                 return false;
7533         else
7534                 return true;
7535 }
7536
7537 static int gfx_v10_0_wait_for_idle(void *handle)
7538 {
7539         unsigned i;
7540         u32 tmp;
7541         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7542
7543         for (i = 0; i < adev->usec_timeout; i++) {
7544                 /* read MC_STATUS */
7545                 tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS) &
7546                         GRBM_STATUS__GUI_ACTIVE_MASK;
7547
7548                 if (!REG_GET_FIELD(tmp, GRBM_STATUS, GUI_ACTIVE))
7549                         return 0;
7550                 udelay(1);
7551         }
7552         return -ETIMEDOUT;
7553 }
7554
7555 static int gfx_v10_0_soft_reset(void *handle)
7556 {
7557         u32 grbm_soft_reset = 0;
7558         u32 tmp;
7559         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7560
7561         /* GRBM_STATUS */
7562         tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS);
7563         if (tmp & (GRBM_STATUS__PA_BUSY_MASK | GRBM_STATUS__SC_BUSY_MASK |
7564                    GRBM_STATUS__BCI_BUSY_MASK | GRBM_STATUS__SX_BUSY_MASK |
7565                    GRBM_STATUS__TA_BUSY_MASK | GRBM_STATUS__DB_BUSY_MASK |
7566                    GRBM_STATUS__CB_BUSY_MASK | GRBM_STATUS__GDS_BUSY_MASK |
7567                    GRBM_STATUS__SPI_BUSY_MASK | GRBM_STATUS__GE_BUSY_NO_DMA_MASK)) {
7568                 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
7569                                                 GRBM_SOFT_RESET, SOFT_RESET_CP,
7570                                                 1);
7571                 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
7572                                                 GRBM_SOFT_RESET, SOFT_RESET_GFX,
7573                                                 1);
7574         }
7575
7576         if (tmp & (GRBM_STATUS__CP_BUSY_MASK | GRBM_STATUS__CP_COHERENCY_BUSY_MASK)) {
7577                 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
7578                                                 GRBM_SOFT_RESET, SOFT_RESET_CP,
7579                                                 1);
7580         }
7581
7582         /* GRBM_STATUS2 */
7583         tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS2);
7584         switch (adev->ip_versions[GC_HWIP][0]) {
7585         case IP_VERSION(10, 3, 0):
7586         case IP_VERSION(10, 3, 2):
7587         case IP_VERSION(10, 3, 1):
7588         case IP_VERSION(10, 3, 4):
7589         case IP_VERSION(10, 3, 5):
7590         case IP_VERSION(10, 3, 3):
7591                 if (REG_GET_FIELD(tmp, GRBM_STATUS2, RLC_BUSY_Sienna_Cichlid))
7592                         grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
7593                                                         GRBM_SOFT_RESET,
7594                                                         SOFT_RESET_RLC,
7595                                                         1);
7596                 break;
7597         default:
7598                 if (REG_GET_FIELD(tmp, GRBM_STATUS2, RLC_BUSY))
7599                         grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
7600                                                         GRBM_SOFT_RESET,
7601                                                         SOFT_RESET_RLC,
7602                                                         1);
7603                 break;
7604         }
7605
7606         if (grbm_soft_reset) {
7607                 /* stop the rlc */
7608                 gfx_v10_0_rlc_stop(adev);
7609
7610                 /* Disable GFX parsing/prefetching */
7611                 gfx_v10_0_cp_gfx_enable(adev, false);
7612
7613                 /* Disable MEC parsing/prefetching */
7614                 gfx_v10_0_cp_compute_enable(adev, false);
7615
7616                 if (grbm_soft_reset) {
7617                         tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);
7618                         tmp |= grbm_soft_reset;
7619                         dev_info(adev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp);
7620                         WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp);
7621                         tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);
7622
7623                         udelay(50);
7624
7625                         tmp &= ~grbm_soft_reset;
7626                         WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp);
7627                         tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);
7628                 }
7629
7630                 /* Wait a little for things to settle down */
7631                 udelay(50);
7632         }
7633         return 0;
7634 }
7635
7636 static uint64_t gfx_v10_0_get_gpu_clock_counter(struct amdgpu_device *adev)
7637 {
7638         uint64_t clock, clock_lo, clock_hi, hi_check;
7639
7640         switch (adev->ip_versions[GC_HWIP][0]) {
7641         case IP_VERSION(10, 3, 1):
7642         case IP_VERSION(10, 3, 3):
7643                 preempt_disable();
7644                 clock_hi = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER_Vangogh);
7645                 clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER_Vangogh);
7646                 hi_check = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER_Vangogh);
7647                 /* The SMUIO TSC clock frequency is 100MHz, which sets 32-bit carry over
7648                  * roughly every 42 seconds.
7649                  */
7650                 if (hi_check != clock_hi) {
7651                         clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER_Vangogh);
7652                         clock_hi = hi_check;
7653                 }
7654                 preempt_enable();
7655                 clock = clock_lo | (clock_hi << 32ULL);
7656                 break;
7657         default:
7658                 preempt_disable();
7659                 clock_hi = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER);
7660                 clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER);
7661                 hi_check = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER);
7662                 /* The SMUIO TSC clock frequency is 100MHz, which sets 32-bit carry over
7663                  * roughly every 42 seconds.
7664                  */
7665                 if (hi_check != clock_hi) {
7666                         clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER);
7667                         clock_hi = hi_check;
7668                 }
7669                 preempt_enable();
7670                 clock = clock_lo | (clock_hi << 32ULL);
7671                 break;
7672         }
7673         return clock;
7674 }
7675
7676 static void gfx_v10_0_ring_emit_gds_switch(struct amdgpu_ring *ring,
7677                                            uint32_t vmid,
7678                                            uint32_t gds_base, uint32_t gds_size,
7679                                            uint32_t gws_base, uint32_t gws_size,
7680                                            uint32_t oa_base, uint32_t oa_size)
7681 {
7682         struct amdgpu_device *adev = ring->adev;
7683
7684         /* GDS Base */
7685         gfx_v10_0_write_data_to_reg(ring, 0, false,
7686                                     SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_BASE) + 2 * vmid,
7687                                     gds_base);
7688
7689         /* GDS Size */
7690         gfx_v10_0_write_data_to_reg(ring, 0, false,
7691                                     SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_SIZE) + 2 * vmid,
7692                                     gds_size);
7693
7694         /* GWS */
7695         gfx_v10_0_write_data_to_reg(ring, 0, false,
7696                                     SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID0) + vmid,
7697                                     gws_size << GDS_GWS_VMID0__SIZE__SHIFT | gws_base);
7698
7699         /* OA */
7700         gfx_v10_0_write_data_to_reg(ring, 0, false,
7701                                     SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID0) + vmid,
7702                                     (1 << (oa_size + oa_base)) - (1 << oa_base));
7703 }
7704
7705 static int gfx_v10_0_early_init(void *handle)
7706 {
7707         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7708
7709         switch (adev->ip_versions[GC_HWIP][0]) {
7710         case IP_VERSION(10, 1, 10):
7711         case IP_VERSION(10, 1, 1):
7712         case IP_VERSION(10, 1, 2):
7713         case IP_VERSION(10, 1, 3):
7714         case IP_VERSION(10, 1, 4):
7715                 adev->gfx.num_gfx_rings = GFX10_NUM_GFX_RINGS_NV1X;
7716                 break;
7717         case IP_VERSION(10, 3, 0):
7718         case IP_VERSION(10, 3, 2):
7719         case IP_VERSION(10, 3, 1):
7720         case IP_VERSION(10, 3, 4):
7721         case IP_VERSION(10, 3, 5):
7722         case IP_VERSION(10, 3, 3):
7723         case IP_VERSION(10, 3, 7):
7724                 adev->gfx.num_gfx_rings = GFX10_NUM_GFX_RINGS_Sienna_Cichlid;
7725                 break;
7726         default:
7727                 break;
7728         }
7729
7730         adev->gfx.num_compute_rings = min(amdgpu_gfx_get_num_kcq(adev),
7731                                           AMDGPU_MAX_COMPUTE_RINGS);
7732
7733         gfx_v10_0_set_kiq_pm4_funcs(adev);
7734         gfx_v10_0_set_ring_funcs(adev);
7735         gfx_v10_0_set_irq_funcs(adev);
7736         gfx_v10_0_set_gds_init(adev);
7737         gfx_v10_0_set_rlc_funcs(adev);
7738
7739         /* init rlcg reg access ctrl */
7740         gfx_v10_0_init_rlcg_reg_access_ctrl(adev);
7741
7742         return 0;
7743 }
7744
7745 static int gfx_v10_0_late_init(void *handle)
7746 {
7747         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7748         int r;
7749
7750         r = amdgpu_irq_get(adev, &adev->gfx.priv_reg_irq, 0);
7751         if (r)
7752                 return r;
7753
7754         r = amdgpu_irq_get(adev, &adev->gfx.priv_inst_irq, 0);
7755         if (r)
7756                 return r;
7757
7758         return 0;
7759 }
7760
7761 static bool gfx_v10_0_is_rlc_enabled(struct amdgpu_device *adev)
7762 {
7763         uint32_t rlc_cntl;
7764
7765         /* if RLC is not enabled, do nothing */
7766         rlc_cntl = RREG32_SOC15(GC, 0, mmRLC_CNTL);
7767         return (REG_GET_FIELD(rlc_cntl, RLC_CNTL, RLC_ENABLE_F32)) ? true : false;
7768 }
7769
7770 static void gfx_v10_0_set_safe_mode(struct amdgpu_device *adev)
7771 {
7772         uint32_t data;
7773         unsigned i;
7774
7775         data = RLC_SAFE_MODE__CMD_MASK;
7776         data |= (1 << RLC_SAFE_MODE__MESSAGE__SHIFT);
7777
7778         switch (adev->ip_versions[GC_HWIP][0]) {
7779         case IP_VERSION(10, 3, 0):
7780         case IP_VERSION(10, 3, 2):
7781         case IP_VERSION(10, 3, 1):
7782         case IP_VERSION(10, 3, 4):
7783         case IP_VERSION(10, 3, 5):
7784         case IP_VERSION(10, 3, 3):
7785                 WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE_Sienna_Cichlid, data);
7786
7787                 /* wait for RLC_SAFE_MODE */
7788                 for (i = 0; i < adev->usec_timeout; i++) {
7789                         if (!REG_GET_FIELD(RREG32_SOC15(GC, 0, mmRLC_SAFE_MODE_Sienna_Cichlid),
7790                                            RLC_SAFE_MODE, CMD))
7791                                 break;
7792                         udelay(1);
7793                 }
7794                 break;
7795         default:
7796                 WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE, data);
7797
7798                 /* wait for RLC_SAFE_MODE */
7799                 for (i = 0; i < adev->usec_timeout; i++) {
7800                         if (!REG_GET_FIELD(RREG32_SOC15(GC, 0, mmRLC_SAFE_MODE),
7801                                            RLC_SAFE_MODE, CMD))
7802                                 break;
7803                         udelay(1);
7804                 }
7805                 break;
7806         }
7807 }
7808
7809 static void gfx_v10_0_unset_safe_mode(struct amdgpu_device *adev)
7810 {
7811         uint32_t data;
7812
7813         data = RLC_SAFE_MODE__CMD_MASK;
7814         switch (adev->ip_versions[GC_HWIP][0]) {
7815         case IP_VERSION(10, 3, 0):
7816         case IP_VERSION(10, 3, 2):
7817         case IP_VERSION(10, 3, 1):
7818         case IP_VERSION(10, 3, 4):
7819         case IP_VERSION(10, 3, 5):
7820         case IP_VERSION(10, 3, 3):
7821                 WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE_Sienna_Cichlid, data);
7822                 break;
7823         default:
7824                 WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE, data);
7825                 break;
7826         }
7827 }
7828
7829 static void gfx_v10_0_update_medium_grain_clock_gating(struct amdgpu_device *adev,
7830                                                       bool enable)
7831 {
7832         uint32_t data, def;
7833
7834         if (!(adev->cg_flags & (AMD_CG_SUPPORT_GFX_MGCG | AMD_CG_SUPPORT_GFX_MGLS)))
7835                 return;
7836
7837         /* It is disabled by HW by default */
7838         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) {
7839                 /* 0 - Disable some blocks' MGCG */
7840                 WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, 0xe0000000);
7841                 WREG32_SOC15(GC, 0, mmCGTT_WD_CLK_CTRL, 0xff000000);
7842                 WREG32_SOC15(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xff000000);
7843                 WREG32_SOC15(GC, 0, mmCGTT_IA_CLK_CTRL, 0xff000000);
7844
7845                 /* 1 - RLC_CGTT_MGCG_OVERRIDE */
7846                 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
7847                 data &= ~(RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK |
7848                           RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK |
7849                           RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK |
7850                           RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK |
7851                           RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK |
7852                           RLC_CGTT_MGCG_OVERRIDE__ENABLE_CGTS_LEGACY_MASK);
7853
7854                 if (def != data)
7855                         WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
7856
7857                 /* MGLS is a global flag to control all MGLS in GFX */
7858                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGLS) {
7859                         /* 2 - RLC memory Light sleep */
7860                         if (adev->cg_flags & AMD_CG_SUPPORT_GFX_RLC_LS) {
7861                                 def = data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL);
7862                                 data |= RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK;
7863                                 if (def != data)
7864                                         WREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL, data);
7865                         }
7866                         /* 3 - CP memory Light sleep */
7867                         if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CP_LS) {
7868                                 def = data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL);
7869                                 data |= CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK;
7870                                 if (def != data)
7871                                         WREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL, data);
7872                         }
7873                 }
7874         } else if (!enable || !(adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) {
7875                 /* 1 - MGCG_OVERRIDE */
7876                 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
7877                 data |= (RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK |
7878                          RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK |
7879                          RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK |
7880                          RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK |
7881                          RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK |
7882                          RLC_CGTT_MGCG_OVERRIDE__ENABLE_CGTS_LEGACY_MASK);
7883                 if (def != data)
7884                         WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
7885
7886                 /* 2 - disable MGLS in CP */
7887                 data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL);
7888                 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) {
7889                         data &= ~CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK;
7890                         WREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL, data);
7891                 }
7892
7893                 /* 3 - disable MGLS in RLC */
7894                 data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL);
7895                 if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK) {
7896                         data &= ~RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK;
7897                         WREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL, data);
7898                 }
7899
7900         }
7901 }
7902
7903 static void gfx_v10_0_update_3d_clock_gating(struct amdgpu_device *adev,
7904                                            bool enable)
7905 {
7906         uint32_t data, def;
7907
7908         if (!(adev->cg_flags & (AMD_CG_SUPPORT_GFX_3D_CGCG | AMD_CG_SUPPORT_GFX_3D_CGLS)))
7909                 return;
7910
7911         /* Enable 3D CGCG/CGLS */
7912         if (enable) {
7913                 /* write cmd to clear cgcg/cgls ov */
7914                 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
7915
7916                 /* unset CGCG override */
7917                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG)
7918                         data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_GFX3D_CG_OVERRIDE_MASK;
7919
7920                 /* update CGCG and CGLS override bits */
7921                 if (def != data)
7922                         WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
7923
7924                 /* enable 3Dcgcg FSM(0x0000363f) */
7925                 def = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D);
7926                 data = 0;
7927
7928                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG)
7929                         data = (0x36 << RLC_CGCG_CGLS_CTRL_3D__CGCG_GFX_IDLE_THRESHOLD__SHIFT) |
7930                                 RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK;
7931
7932                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS)
7933                         data |= (0x000F << RLC_CGCG_CGLS_CTRL_3D__CGLS_REP_COMPANSAT_DELAY__SHIFT) |
7934                                 RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK;
7935
7936                 if (def != data)
7937                         WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D, data);
7938
7939                 /* set IDLE_POLL_COUNT(0x00900100) */
7940                 def = RREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL);
7941                 data = (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) |
7942                         (0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT);
7943                 if (def != data)
7944                         WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL, data);
7945         } else {
7946                 /* Disable CGCG/CGLS */
7947                 def = data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D);
7948
7949                 /* disable cgcg, cgls should be disabled */
7950                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG)
7951                         data &= ~RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK;
7952
7953                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS)
7954                         data &= ~RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK;
7955
7956                 /* disable cgcg and cgls in FSM */
7957                 if (def != data)
7958                         WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D, data);
7959         }
7960 }
7961
7962 static void gfx_v10_0_update_coarse_grain_clock_gating(struct amdgpu_device *adev,
7963                                                       bool enable)
7964 {
7965         uint32_t def, data;
7966
7967         if (!(adev->cg_flags & (AMD_CG_SUPPORT_GFX_CGCG | AMD_CG_SUPPORT_GFX_CGLS)))
7968                 return;
7969
7970         if (enable) {
7971                 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
7972
7973                 /* unset CGCG override */
7974                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)
7975                         data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGCG_OVERRIDE_MASK;
7976
7977                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS)
7978                         data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK;
7979
7980                 /* update CGCG and CGLS override bits */
7981                 if (def != data)
7982                         WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
7983
7984                 /* enable cgcg FSM(0x0000363F) */
7985                 def = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL);
7986                 data = 0;
7987
7988                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)
7989                         data = (0x36 << RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT) |
7990                                 RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK;
7991
7992                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS)
7993                         data |= (0x000F << RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY__SHIFT) |
7994                                 RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK;
7995
7996                 if (def != data)
7997                         WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, data);
7998
7999                 /* set IDLE_POLL_COUNT(0x00900100) */
8000                 def = RREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL);
8001                 data = (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) |
8002                         (0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT);
8003                 if (def != data)
8004                         WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL, data);
8005         } else {
8006                 def = data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL);
8007
8008                 /* reset CGCG/CGLS bits */
8009                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)
8010                         data &= ~RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK;
8011
8012                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS)
8013                         data &= ~RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK;
8014
8015                 /* disable cgcg and cgls in FSM */
8016                 if (def != data)
8017                         WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, data);
8018         }
8019 }
8020
8021 static void gfx_v10_0_update_fine_grain_clock_gating(struct amdgpu_device *adev,
8022                                                       bool enable)
8023 {
8024         uint32_t def, data;
8025
8026         if (!(adev->cg_flags & AMD_CG_SUPPORT_GFX_FGCG))
8027                 return;
8028
8029         if (enable) {
8030                 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
8031                 /* unset FGCG override */
8032                 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK;
8033                 /* update FGCG override bits */
8034                 if (def != data)
8035                         WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
8036
8037                 def = data = RREG32_SOC15(GC, 0, mmRLC_CLK_CNTL);
8038                 /* unset RLC SRAM CLK GATER override */
8039                 data &= ~RLC_CLK_CNTL__RLC_SRAM_CLK_GATER_OVERRIDE_MASK;
8040                 /* update RLC SRAM CLK GATER override bits */
8041                 if (def != data)
8042                         WREG32_SOC15(GC, 0, mmRLC_CLK_CNTL, data);
8043         } else {
8044                 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
8045                 /* reset FGCG bits */
8046                 data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK;
8047                 /* disable FGCG*/
8048                 if (def != data)
8049                         WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
8050
8051                 def = data = RREG32_SOC15(GC, 0, mmRLC_CLK_CNTL);
8052                 /* reset RLC SRAM CLK GATER bits */
8053                 data |= RLC_CLK_CNTL__RLC_SRAM_CLK_GATER_OVERRIDE_MASK;
8054                 /* disable RLC SRAM CLK*/
8055                 if (def != data)
8056                         WREG32_SOC15(GC, 0, mmRLC_CLK_CNTL, data);
8057         }
8058 }
8059
8060 static void gfx_v10_0_apply_medium_grain_clock_gating_workaround(struct amdgpu_device *adev)
8061 {
8062         uint32_t reg_data = 0;
8063         uint32_t reg_idx = 0;
8064         uint32_t i;
8065
8066         const uint32_t tcp_ctrl_regs[] = {
8067                 mmCGTS_SA0_WGP00_CU0_TCP_CTRL_REG,
8068                 mmCGTS_SA0_WGP00_CU1_TCP_CTRL_REG,
8069                 mmCGTS_SA0_WGP01_CU0_TCP_CTRL_REG,
8070                 mmCGTS_SA0_WGP01_CU1_TCP_CTRL_REG,
8071                 mmCGTS_SA0_WGP02_CU0_TCP_CTRL_REG,
8072                 mmCGTS_SA0_WGP02_CU1_TCP_CTRL_REG,
8073                 mmCGTS_SA0_WGP10_CU0_TCP_CTRL_REG,
8074                 mmCGTS_SA0_WGP10_CU1_TCP_CTRL_REG,
8075                 mmCGTS_SA0_WGP11_CU0_TCP_CTRL_REG,
8076                 mmCGTS_SA0_WGP11_CU1_TCP_CTRL_REG,
8077                 mmCGTS_SA0_WGP12_CU0_TCP_CTRL_REG,
8078                 mmCGTS_SA0_WGP12_CU1_TCP_CTRL_REG,
8079                 mmCGTS_SA1_WGP00_CU0_TCP_CTRL_REG,
8080                 mmCGTS_SA1_WGP00_CU1_TCP_CTRL_REG,
8081                 mmCGTS_SA1_WGP01_CU0_TCP_CTRL_REG,
8082                 mmCGTS_SA1_WGP01_CU1_TCP_CTRL_REG,
8083                 mmCGTS_SA1_WGP02_CU0_TCP_CTRL_REG,
8084                 mmCGTS_SA1_WGP02_CU1_TCP_CTRL_REG,
8085                 mmCGTS_SA1_WGP10_CU0_TCP_CTRL_REG,
8086                 mmCGTS_SA1_WGP10_CU1_TCP_CTRL_REG,
8087                 mmCGTS_SA1_WGP11_CU0_TCP_CTRL_REG,
8088                 mmCGTS_SA1_WGP11_CU1_TCP_CTRL_REG,
8089                 mmCGTS_SA1_WGP12_CU0_TCP_CTRL_REG,
8090                 mmCGTS_SA1_WGP12_CU1_TCP_CTRL_REG
8091         };
8092
8093         const uint32_t tcp_ctrl_regs_nv12[] = {
8094                 mmCGTS_SA0_WGP00_CU0_TCP_CTRL_REG,
8095                 mmCGTS_SA0_WGP00_CU1_TCP_CTRL_REG,
8096                 mmCGTS_SA0_WGP01_CU0_TCP_CTRL_REG,
8097                 mmCGTS_SA0_WGP01_CU1_TCP_CTRL_REG,
8098                 mmCGTS_SA0_WGP02_CU0_TCP_CTRL_REG,
8099                 mmCGTS_SA0_WGP02_CU1_TCP_CTRL_REG,
8100                 mmCGTS_SA0_WGP10_CU0_TCP_CTRL_REG,
8101                 mmCGTS_SA0_WGP10_CU1_TCP_CTRL_REG,
8102                 mmCGTS_SA0_WGP11_CU0_TCP_CTRL_REG,
8103                 mmCGTS_SA0_WGP11_CU1_TCP_CTRL_REG,
8104                 mmCGTS_SA1_WGP00_CU0_TCP_CTRL_REG,
8105                 mmCGTS_SA1_WGP00_CU1_TCP_CTRL_REG,
8106                 mmCGTS_SA1_WGP01_CU0_TCP_CTRL_REG,
8107                 mmCGTS_SA1_WGP01_CU1_TCP_CTRL_REG,
8108                 mmCGTS_SA1_WGP02_CU0_TCP_CTRL_REG,
8109                 mmCGTS_SA1_WGP02_CU1_TCP_CTRL_REG,
8110                 mmCGTS_SA1_WGP10_CU0_TCP_CTRL_REG,
8111                 mmCGTS_SA1_WGP10_CU1_TCP_CTRL_REG,
8112                 mmCGTS_SA1_WGP11_CU0_TCP_CTRL_REG,
8113                 mmCGTS_SA1_WGP11_CU1_TCP_CTRL_REG,
8114         };
8115
8116         const uint32_t sm_ctlr_regs[] = {
8117                 mmCGTS_SA0_QUAD0_SM_CTRL_REG,
8118                 mmCGTS_SA0_QUAD1_SM_CTRL_REG,
8119                 mmCGTS_SA1_QUAD0_SM_CTRL_REG,
8120                 mmCGTS_SA1_QUAD1_SM_CTRL_REG
8121         };
8122
8123         if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 1, 2)) {
8124                 for (i = 0; i < ARRAY_SIZE(tcp_ctrl_regs_nv12); i++) {
8125                         reg_idx = adev->reg_offset[GC_HWIP][0][mmCGTS_SA0_WGP00_CU0_TCP_CTRL_REG_BASE_IDX] +
8126                                   tcp_ctrl_regs_nv12[i];
8127                         reg_data = RREG32(reg_idx);
8128                         reg_data |= CGTS_SA0_WGP00_CU0_TCP_CTRL_REG__TCPI_LS_OVERRIDE_MASK;
8129                         WREG32(reg_idx, reg_data);
8130                 }
8131         } else {
8132                 for (i = 0; i < ARRAY_SIZE(tcp_ctrl_regs); i++) {
8133                         reg_idx = adev->reg_offset[GC_HWIP][0][mmCGTS_SA0_WGP00_CU0_TCP_CTRL_REG_BASE_IDX] +
8134                                   tcp_ctrl_regs[i];
8135                         reg_data = RREG32(reg_idx);
8136                         reg_data |= CGTS_SA0_WGP00_CU0_TCP_CTRL_REG__TCPI_LS_OVERRIDE_MASK;
8137                         WREG32(reg_idx, reg_data);
8138                 }
8139         }
8140
8141         for (i = 0; i < ARRAY_SIZE(sm_ctlr_regs); i++) {
8142                 reg_idx = adev->reg_offset[GC_HWIP][0][mmCGTS_SA0_QUAD0_SM_CTRL_REG_BASE_IDX] +
8143                           sm_ctlr_regs[i];
8144                 reg_data = RREG32(reg_idx);
8145                 reg_data &= ~CGTS_SA0_QUAD0_SM_CTRL_REG__SM_MODE_MASK;
8146                 reg_data |= 2 << CGTS_SA0_QUAD0_SM_CTRL_REG__SM_MODE__SHIFT;
8147                 WREG32(reg_idx, reg_data);
8148         }
8149 }
8150
8151 static int gfx_v10_0_update_gfx_clock_gating(struct amdgpu_device *adev,
8152                                             bool enable)
8153 {
8154         amdgpu_gfx_rlc_enter_safe_mode(adev);
8155
8156         if (enable) {
8157                 /* enable FGCG firstly*/
8158                 gfx_v10_0_update_fine_grain_clock_gating(adev, enable);
8159                 /* CGCG/CGLS should be enabled after MGCG/MGLS
8160                  * ===  MGCG + MGLS ===
8161                  */
8162                 gfx_v10_0_update_medium_grain_clock_gating(adev, enable);
8163                 /* ===  CGCG /CGLS for GFX 3D Only === */
8164                 gfx_v10_0_update_3d_clock_gating(adev, enable);
8165                 /* ===  CGCG + CGLS === */
8166                 gfx_v10_0_update_coarse_grain_clock_gating(adev, enable);
8167
8168                 if ((adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 1, 10)) ||
8169                     (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 1, 1)) ||
8170                     (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 1, 2)))
8171                         gfx_v10_0_apply_medium_grain_clock_gating_workaround(adev);
8172         } else {
8173                 /* CGCG/CGLS should be disabled before MGCG/MGLS
8174                  * ===  CGCG + CGLS ===
8175                  */
8176                 gfx_v10_0_update_coarse_grain_clock_gating(adev, enable);
8177                 /* ===  CGCG /CGLS for GFX 3D Only === */
8178                 gfx_v10_0_update_3d_clock_gating(adev, enable);
8179                 /* ===  MGCG + MGLS === */
8180                 gfx_v10_0_update_medium_grain_clock_gating(adev, enable);
8181                 /* disable fgcg at last*/
8182                 gfx_v10_0_update_fine_grain_clock_gating(adev, enable);
8183         }
8184
8185         if (adev->cg_flags &
8186             (AMD_CG_SUPPORT_GFX_MGCG |
8187              AMD_CG_SUPPORT_GFX_CGLS |
8188              AMD_CG_SUPPORT_GFX_CGCG |
8189              AMD_CG_SUPPORT_GFX_3D_CGCG |
8190              AMD_CG_SUPPORT_GFX_3D_CGLS))
8191                 gfx_v10_0_enable_gui_idle_interrupt(adev, enable);
8192
8193         amdgpu_gfx_rlc_exit_safe_mode(adev);
8194
8195         return 0;
8196 }
8197
8198 static void gfx_v10_0_update_spm_vmid(struct amdgpu_device *adev, unsigned vmid)
8199 {
8200         u32 reg, data;
8201
8202         amdgpu_gfx_off_ctrl(adev, false);
8203
8204         /* not for *_SOC15 */
8205         reg = SOC15_REG_OFFSET(GC, 0, mmRLC_SPM_MC_CNTL);
8206         if (amdgpu_sriov_is_pp_one_vf(adev))
8207                 data = RREG32_NO_KIQ(reg);
8208         else
8209                 data = RREG32_SOC15(GC, 0, mmRLC_SPM_MC_CNTL);
8210
8211         data &= ~RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK;
8212         data |= (vmid & RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK) << RLC_SPM_MC_CNTL__RLC_SPM_VMID__SHIFT;
8213
8214         if (amdgpu_sriov_is_pp_one_vf(adev))
8215                 WREG32_SOC15_NO_KIQ(GC, 0, mmRLC_SPM_MC_CNTL, data);
8216         else
8217                 WREG32_SOC15(GC, 0, mmRLC_SPM_MC_CNTL, data);
8218
8219         amdgpu_gfx_off_ctrl(adev, true);
8220 }
8221
8222 static bool gfx_v10_0_check_rlcg_range(struct amdgpu_device *adev,
8223                                         uint32_t offset,
8224                                         struct soc15_reg_rlcg *entries, int arr_size)
8225 {
8226         int i;
8227         uint32_t reg;
8228
8229         if (!entries)
8230                 return false;
8231
8232         for (i = 0; i < arr_size; i++) {
8233                 const struct soc15_reg_rlcg *entry;
8234
8235                 entry = &entries[i];
8236                 reg = adev->reg_offset[entry->hwip][entry->instance][entry->segment] + entry->reg;
8237                 if (offset == reg)
8238                         return true;
8239         }
8240
8241         return false;
8242 }
8243
8244 static bool gfx_v10_0_is_rlcg_access_range(struct amdgpu_device *adev, u32 offset)
8245 {
8246         return gfx_v10_0_check_rlcg_range(adev, offset, NULL, 0);
8247 }
8248
8249 static void gfx_v10_cntl_power_gating(struct amdgpu_device *adev, bool enable)
8250 {
8251         u32 data = RREG32_SOC15(GC, 0, mmRLC_PG_CNTL);
8252
8253         if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG))
8254                 data |= RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK;
8255         else
8256                 data &= ~RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK;
8257
8258         WREG32_SOC15(GC, 0, mmRLC_PG_CNTL, data);
8259
8260         /*
8261          * CGPG enablement required and the register to program the hysteresis value
8262          * RLC_PG_DELAY_3.CGCG_ACTIVE_BEFORE_CGPG to the desired CGPG hysteresis value
8263          * in refclk count. Note that RLC FW is modified to take 16 bits from
8264          * RLC_PG_DELAY_3[15:0] as the hysteresis instead of just 8 bits.
8265          *
8266          * The recommendation from RLC team is setting RLC_PG_DELAY_3 to 200us as part)
8267          * of CGPG enablement starting point.
8268          * Power/performance team will optimize it and might give a new value later.
8269          */
8270         if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG)) {
8271                 switch (adev->ip_versions[GC_HWIP][0]) {
8272                 case IP_VERSION(10, 3, 1):
8273                 case IP_VERSION(10, 3, 3):
8274                         data = 0x4E20 & RLC_PG_DELAY_3__CGCG_ACTIVE_BEFORE_CGPG_MASK_Vangogh;
8275                         WREG32_SOC15(GC, 0, mmRLC_PG_DELAY_3, data);
8276                         break;
8277                 default:
8278                         break;
8279                 }
8280         }
8281 }
8282
8283 static void gfx_v10_cntl_pg(struct amdgpu_device *adev, bool enable)
8284 {
8285         amdgpu_gfx_rlc_enter_safe_mode(adev);
8286
8287         gfx_v10_cntl_power_gating(adev, enable);
8288
8289         amdgpu_gfx_rlc_exit_safe_mode(adev);
8290 }
8291
8292 static const struct amdgpu_rlc_funcs gfx_v10_0_rlc_funcs = {
8293         .is_rlc_enabled = gfx_v10_0_is_rlc_enabled,
8294         .set_safe_mode = gfx_v10_0_set_safe_mode,
8295         .unset_safe_mode = gfx_v10_0_unset_safe_mode,
8296         .init = gfx_v10_0_rlc_init,
8297         .get_csb_size = gfx_v10_0_get_csb_size,
8298         .get_csb_buffer = gfx_v10_0_get_csb_buffer,
8299         .resume = gfx_v10_0_rlc_resume,
8300         .stop = gfx_v10_0_rlc_stop,
8301         .reset = gfx_v10_0_rlc_reset,
8302         .start = gfx_v10_0_rlc_start,
8303         .update_spm_vmid = gfx_v10_0_update_spm_vmid,
8304 };
8305
8306 static const struct amdgpu_rlc_funcs gfx_v10_0_rlc_funcs_sriov = {
8307         .is_rlc_enabled = gfx_v10_0_is_rlc_enabled,
8308         .set_safe_mode = gfx_v10_0_set_safe_mode,
8309         .unset_safe_mode = gfx_v10_0_unset_safe_mode,
8310         .init = gfx_v10_0_rlc_init,
8311         .get_csb_size = gfx_v10_0_get_csb_size,
8312         .get_csb_buffer = gfx_v10_0_get_csb_buffer,
8313         .resume = gfx_v10_0_rlc_resume,
8314         .stop = gfx_v10_0_rlc_stop,
8315         .reset = gfx_v10_0_rlc_reset,
8316         .start = gfx_v10_0_rlc_start,
8317         .update_spm_vmid = gfx_v10_0_update_spm_vmid,
8318         .is_rlcg_access_range = gfx_v10_0_is_rlcg_access_range,
8319 };
8320
8321 static int gfx_v10_0_set_powergating_state(void *handle,
8322                                           enum amd_powergating_state state)
8323 {
8324         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
8325         bool enable = (state == AMD_PG_STATE_GATE);
8326
8327         if (amdgpu_sriov_vf(adev))
8328                 return 0;
8329
8330         switch (adev->ip_versions[GC_HWIP][0]) {
8331         case IP_VERSION(10, 1, 10):
8332         case IP_VERSION(10, 1, 1):
8333         case IP_VERSION(10, 1, 2):
8334         case IP_VERSION(10, 3, 0):
8335         case IP_VERSION(10, 3, 2):
8336         case IP_VERSION(10, 3, 4):
8337         case IP_VERSION(10, 3, 5):
8338                 amdgpu_gfx_off_ctrl(adev, enable);
8339                 break;
8340         case IP_VERSION(10, 3, 1):
8341         case IP_VERSION(10, 3, 3):
8342                 gfx_v10_cntl_pg(adev, enable);
8343                 amdgpu_gfx_off_ctrl(adev, enable);
8344                 break;
8345         default:
8346                 break;
8347         }
8348         return 0;
8349 }
8350
8351 static int gfx_v10_0_set_clockgating_state(void *handle,
8352                                           enum amd_clockgating_state state)
8353 {
8354         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
8355
8356         if (amdgpu_sriov_vf(adev))
8357                 return 0;
8358
8359         switch (adev->ip_versions[GC_HWIP][0]) {
8360         case IP_VERSION(10, 1, 10):
8361         case IP_VERSION(10, 1, 1):
8362         case IP_VERSION(10, 1, 2):
8363         case IP_VERSION(10, 3, 0):
8364         case IP_VERSION(10, 3, 2):
8365         case IP_VERSION(10, 3, 1):
8366         case IP_VERSION(10, 3, 4):
8367         case IP_VERSION(10, 3, 5):
8368         case IP_VERSION(10, 3, 3):
8369                 gfx_v10_0_update_gfx_clock_gating(adev,
8370                                                  state == AMD_CG_STATE_GATE);
8371                 break;
8372         default:
8373                 break;
8374         }
8375         return 0;
8376 }
8377
8378 static void gfx_v10_0_get_clockgating_state(void *handle, u32 *flags)
8379 {
8380         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
8381         int data;
8382
8383         /* AMD_CG_SUPPORT_GFX_FGCG */
8384         data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE));
8385         if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK))
8386                 *flags |= AMD_CG_SUPPORT_GFX_FGCG;
8387
8388         /* AMD_CG_SUPPORT_GFX_MGCG */
8389         data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE));
8390         if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK))
8391                 *flags |= AMD_CG_SUPPORT_GFX_MGCG;
8392
8393         /* AMD_CG_SUPPORT_GFX_CGCG */
8394         data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGCG_CGLS_CTRL));
8395         if (data & RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK)
8396                 *flags |= AMD_CG_SUPPORT_GFX_CGCG;
8397
8398         /* AMD_CG_SUPPORT_GFX_CGLS */
8399         if (data & RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK)
8400                 *flags |= AMD_CG_SUPPORT_GFX_CGLS;
8401
8402         /* AMD_CG_SUPPORT_GFX_RLC_LS */
8403         data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_MEM_SLP_CNTL));
8404         if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK)
8405                 *flags |= AMD_CG_SUPPORT_GFX_RLC_LS | AMD_CG_SUPPORT_GFX_MGLS;
8406
8407         /* AMD_CG_SUPPORT_GFX_CP_LS */
8408         data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmCP_MEM_SLP_CNTL));
8409         if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK)
8410                 *flags |= AMD_CG_SUPPORT_GFX_CP_LS | AMD_CG_SUPPORT_GFX_MGLS;
8411
8412         /* AMD_CG_SUPPORT_GFX_3D_CGCG */
8413         data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D));
8414         if (data & RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK)
8415                 *flags |= AMD_CG_SUPPORT_GFX_3D_CGCG;
8416
8417         /* AMD_CG_SUPPORT_GFX_3D_CGLS */
8418         if (data & RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK)
8419                 *flags |= AMD_CG_SUPPORT_GFX_3D_CGLS;
8420 }
8421
8422 static u64 gfx_v10_0_ring_get_rptr_gfx(struct amdgpu_ring *ring)
8423 {
8424         return ring->adev->wb.wb[ring->rptr_offs]; /* gfx10 is 32bit rptr*/
8425 }
8426
8427 static u64 gfx_v10_0_ring_get_wptr_gfx(struct amdgpu_ring *ring)
8428 {
8429         struct amdgpu_device *adev = ring->adev;
8430         u64 wptr;
8431
8432         /* XXX check if swapping is necessary on BE */
8433         if (ring->use_doorbell) {
8434                 wptr = atomic64_read((atomic64_t *)&adev->wb.wb[ring->wptr_offs]);
8435         } else {
8436                 wptr = RREG32_SOC15(GC, 0, mmCP_RB0_WPTR);
8437                 wptr += (u64)RREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI) << 32;
8438         }
8439
8440         return wptr;
8441 }
8442
8443 static void gfx_v10_0_ring_set_wptr_gfx(struct amdgpu_ring *ring)
8444 {
8445         struct amdgpu_device *adev = ring->adev;
8446
8447         if (ring->use_doorbell) {
8448                 /* XXX check if swapping is necessary on BE */
8449                 atomic64_set((atomic64_t *)&adev->wb.wb[ring->wptr_offs], ring->wptr);
8450                 WDOORBELL64(ring->doorbell_index, ring->wptr);
8451         } else {
8452                 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR, lower_32_bits(ring->wptr));
8453                 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI, upper_32_bits(ring->wptr));
8454         }
8455 }
8456
8457 static u64 gfx_v10_0_ring_get_rptr_compute(struct amdgpu_ring *ring)
8458 {
8459         return ring->adev->wb.wb[ring->rptr_offs]; /* gfx10 hardware is 32bit rptr */
8460 }
8461
8462 static u64 gfx_v10_0_ring_get_wptr_compute(struct amdgpu_ring *ring)
8463 {
8464         u64 wptr;
8465
8466         /* XXX check if swapping is necessary on BE */
8467         if (ring->use_doorbell)
8468                 wptr = atomic64_read((atomic64_t *)&ring->adev->wb.wb[ring->wptr_offs]);
8469         else
8470                 BUG();
8471         return wptr;
8472 }
8473
8474 static void gfx_v10_0_ring_set_wptr_compute(struct amdgpu_ring *ring)
8475 {
8476         struct amdgpu_device *adev = ring->adev;
8477
8478         /* XXX check if swapping is necessary on BE */
8479         if (ring->use_doorbell) {
8480                 atomic64_set((atomic64_t *)&adev->wb.wb[ring->wptr_offs], ring->wptr);
8481                 WDOORBELL64(ring->doorbell_index, ring->wptr);
8482         } else {
8483                 BUG(); /* only DOORBELL method supported on gfx10 now */
8484         }
8485 }
8486
8487 static void gfx_v10_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
8488 {
8489         struct amdgpu_device *adev = ring->adev;
8490         u32 ref_and_mask, reg_mem_engine;
8491         const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio.hdp_flush_reg;
8492
8493         if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) {
8494                 switch (ring->me) {
8495                 case 1:
8496                         ref_and_mask = nbio_hf_reg->ref_and_mask_cp2 << ring->pipe;
8497                         break;
8498                 case 2:
8499                         ref_and_mask = nbio_hf_reg->ref_and_mask_cp6 << ring->pipe;
8500                         break;
8501                 default:
8502                         return;
8503                 }
8504                 reg_mem_engine = 0;
8505         } else {
8506                 ref_and_mask = nbio_hf_reg->ref_and_mask_cp0;
8507                 reg_mem_engine = 1; /* pfp */
8508         }
8509
8510         gfx_v10_0_wait_reg_mem(ring, reg_mem_engine, 0, 1,
8511                                adev->nbio.funcs->get_hdp_flush_req_offset(adev),
8512                                adev->nbio.funcs->get_hdp_flush_done_offset(adev),
8513                                ref_and_mask, ref_and_mask, 0x20);
8514 }
8515
8516 static void gfx_v10_0_ring_emit_ib_gfx(struct amdgpu_ring *ring,
8517                                        struct amdgpu_job *job,
8518                                        struct amdgpu_ib *ib,
8519                                        uint32_t flags)
8520 {
8521         unsigned vmid = AMDGPU_JOB_GET_VMID(job);
8522         u32 header, control = 0;
8523
8524         if (ib->flags & AMDGPU_IB_FLAG_CE)
8525                 header = PACKET3(PACKET3_INDIRECT_BUFFER_CNST, 2);
8526         else
8527                 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2);
8528
8529         control |= ib->length_dw | (vmid << 24);
8530
8531         if ((amdgpu_sriov_vf(ring->adev) || amdgpu_mcbp) && (ib->flags & AMDGPU_IB_FLAG_PREEMPT)) {
8532                 control |= INDIRECT_BUFFER_PRE_ENB(1);
8533
8534                 if (flags & AMDGPU_IB_PREEMPTED)
8535                         control |= INDIRECT_BUFFER_PRE_RESUME(1);
8536
8537                 if (!(ib->flags & AMDGPU_IB_FLAG_CE) && vmid)
8538                         gfx_v10_0_ring_emit_de_meta(ring,
8539                                     (!amdgpu_sriov_vf(ring->adev) && flags & AMDGPU_IB_PREEMPTED) ? true : false);
8540         }
8541
8542         amdgpu_ring_write(ring, header);
8543         BUG_ON(ib->gpu_addr & 0x3); /* Dword align */
8544         amdgpu_ring_write(ring,
8545 #ifdef __BIG_ENDIAN
8546                 (2 << 0) |
8547 #endif
8548                 lower_32_bits(ib->gpu_addr));
8549         amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
8550         amdgpu_ring_write(ring, control);
8551 }
8552
8553 static void gfx_v10_0_ring_emit_ib_compute(struct amdgpu_ring *ring,
8554                                            struct amdgpu_job *job,
8555                                            struct amdgpu_ib *ib,
8556                                            uint32_t flags)
8557 {
8558         unsigned vmid = AMDGPU_JOB_GET_VMID(job);
8559         u32 control = INDIRECT_BUFFER_VALID | ib->length_dw | (vmid << 24);
8560
8561         /* Currently, there is a high possibility to get wave ID mismatch
8562          * between ME and GDS, leading to a hw deadlock, because ME generates
8563          * different wave IDs than the GDS expects. This situation happens
8564          * randomly when at least 5 compute pipes use GDS ordered append.
8565          * The wave IDs generated by ME are also wrong after suspend/resume.
8566          * Those are probably bugs somewhere else in the kernel driver.
8567          *
8568          * Writing GDS_COMPUTE_MAX_WAVE_ID resets wave ID counters in ME and
8569          * GDS to 0 for this ring (me/pipe).
8570          */
8571         if (ib->flags & AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID) {
8572                 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
8573                 amdgpu_ring_write(ring, mmGDS_COMPUTE_MAX_WAVE_ID);
8574                 amdgpu_ring_write(ring, ring->adev->gds.gds_compute_max_wave_id);
8575         }
8576
8577         amdgpu_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
8578         BUG_ON(ib->gpu_addr & 0x3); /* Dword align */
8579         amdgpu_ring_write(ring,
8580 #ifdef __BIG_ENDIAN
8581                                 (2 << 0) |
8582 #endif
8583                                 lower_32_bits(ib->gpu_addr));
8584         amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
8585         amdgpu_ring_write(ring, control);
8586 }
8587
8588 static void gfx_v10_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr,
8589                                      u64 seq, unsigned flags)
8590 {
8591         bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
8592         bool int_sel = flags & AMDGPU_FENCE_FLAG_INT;
8593
8594         /* RELEASE_MEM - flush caches, send int */
8595         amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 6));
8596         amdgpu_ring_write(ring, (PACKET3_RELEASE_MEM_GCR_SEQ |
8597                                  PACKET3_RELEASE_MEM_GCR_GL2_WB |
8598                                  PACKET3_RELEASE_MEM_GCR_GLM_INV | /* must be set with GLM_WB */
8599                                  PACKET3_RELEASE_MEM_GCR_GLM_WB |
8600                                  PACKET3_RELEASE_MEM_CACHE_POLICY(3) |
8601                                  PACKET3_RELEASE_MEM_EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) |
8602                                  PACKET3_RELEASE_MEM_EVENT_INDEX(5)));
8603         amdgpu_ring_write(ring, (PACKET3_RELEASE_MEM_DATA_SEL(write64bit ? 2 : 1) |
8604                                  PACKET3_RELEASE_MEM_INT_SEL(int_sel ? 2 : 0)));
8605
8606         /*
8607          * the address should be Qword aligned if 64bit write, Dword
8608          * aligned if only send 32bit data low (discard data high)
8609          */
8610         if (write64bit)
8611                 BUG_ON(addr & 0x7);
8612         else
8613                 BUG_ON(addr & 0x3);
8614         amdgpu_ring_write(ring, lower_32_bits(addr));
8615         amdgpu_ring_write(ring, upper_32_bits(addr));
8616         amdgpu_ring_write(ring, lower_32_bits(seq));
8617         amdgpu_ring_write(ring, upper_32_bits(seq));
8618         amdgpu_ring_write(ring, 0);
8619 }
8620
8621 static void gfx_v10_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
8622 {
8623         int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
8624         uint32_t seq = ring->fence_drv.sync_seq;
8625         uint64_t addr = ring->fence_drv.gpu_addr;
8626
8627         gfx_v10_0_wait_reg_mem(ring, usepfp, 1, 0, lower_32_bits(addr),
8628                                upper_32_bits(addr), seq, 0xffffffff, 4);
8629 }
8630
8631 static void gfx_v10_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
8632                                          unsigned vmid, uint64_t pd_addr)
8633 {
8634         amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
8635
8636         /* compute doesn't have PFP */
8637         if (ring->funcs->type == AMDGPU_RING_TYPE_GFX) {
8638                 /* sync PFP to ME, otherwise we might get invalid PFP reads */
8639                 amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0));
8640                 amdgpu_ring_write(ring, 0x0);
8641         }
8642 }
8643
8644 static void gfx_v10_0_ring_emit_fence_kiq(struct amdgpu_ring *ring, u64 addr,
8645                                           u64 seq, unsigned int flags)
8646 {
8647         struct amdgpu_device *adev = ring->adev;
8648
8649         /* we only allocate 32bit for each seq wb address */
8650         BUG_ON(flags & AMDGPU_FENCE_FLAG_64BIT);
8651
8652         /* write fence seq to the "addr" */
8653         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
8654         amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
8655                                  WRITE_DATA_DST_SEL(5) | WR_CONFIRM));
8656         amdgpu_ring_write(ring, lower_32_bits(addr));
8657         amdgpu_ring_write(ring, upper_32_bits(addr));
8658         amdgpu_ring_write(ring, lower_32_bits(seq));
8659
8660         if (flags & AMDGPU_FENCE_FLAG_INT) {
8661                 /* set register to trigger INT */
8662                 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
8663                 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
8664                                          WRITE_DATA_DST_SEL(0) | WR_CONFIRM));
8665                 amdgpu_ring_write(ring, SOC15_REG_OFFSET(GC, 0, mmCPC_INT_STATUS));
8666                 amdgpu_ring_write(ring, 0);
8667                 amdgpu_ring_write(ring, 0x20000000); /* src_id is 178 */
8668         }
8669 }
8670
8671 static void gfx_v10_0_ring_emit_sb(struct amdgpu_ring *ring)
8672 {
8673         amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
8674         amdgpu_ring_write(ring, 0);
8675 }
8676
8677 static void gfx_v10_0_ring_emit_cntxcntl(struct amdgpu_ring *ring,
8678                                          uint32_t flags)
8679 {
8680         uint32_t dw2 = 0;
8681
8682         if (amdgpu_mcbp || amdgpu_sriov_vf(ring->adev))
8683                 gfx_v10_0_ring_emit_ce_meta(ring,
8684                                     (!amdgpu_sriov_vf(ring->adev) && flags & AMDGPU_IB_PREEMPTED) ? true : false);
8685
8686         dw2 |= 0x80000000; /* set load_enable otherwise this package is just NOPs */
8687         if (flags & AMDGPU_HAVE_CTX_SWITCH) {
8688                 /* set load_global_config & load_global_uconfig */
8689                 dw2 |= 0x8001;
8690                 /* set load_cs_sh_regs */
8691                 dw2 |= 0x01000000;
8692                 /* set load_per_context_state & load_gfx_sh_regs for GFX */
8693                 dw2 |= 0x10002;
8694
8695                 /* set load_ce_ram if preamble presented */
8696                 if (AMDGPU_PREAMBLE_IB_PRESENT & flags)
8697                         dw2 |= 0x10000000;
8698         } else {
8699                 /* still load_ce_ram if this is the first time preamble presented
8700                  * although there is no context switch happens.
8701                  */
8702                 if (AMDGPU_PREAMBLE_IB_PRESENT_FIRST & flags)
8703                         dw2 |= 0x10000000;
8704         }
8705
8706         amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1));
8707         amdgpu_ring_write(ring, dw2);
8708         amdgpu_ring_write(ring, 0);
8709 }
8710
8711 static unsigned gfx_v10_0_ring_emit_init_cond_exec(struct amdgpu_ring *ring)
8712 {
8713         unsigned ret;
8714
8715         amdgpu_ring_write(ring, PACKET3(PACKET3_COND_EXEC, 3));
8716         amdgpu_ring_write(ring, lower_32_bits(ring->cond_exe_gpu_addr));
8717         amdgpu_ring_write(ring, upper_32_bits(ring->cond_exe_gpu_addr));
8718         amdgpu_ring_write(ring, 0); /* discard following DWs if *cond_exec_gpu_addr==0 */
8719         ret = ring->wptr & ring->buf_mask;
8720         amdgpu_ring_write(ring, 0x55aa55aa); /* patch dummy value later */
8721
8722         return ret;
8723 }
8724
8725 static void gfx_v10_0_ring_emit_patch_cond_exec(struct amdgpu_ring *ring, unsigned offset)
8726 {
8727         unsigned cur;
8728         BUG_ON(offset > ring->buf_mask);
8729         BUG_ON(ring->ring[offset] != 0x55aa55aa);
8730
8731         cur = (ring->wptr - 1) & ring->buf_mask;
8732         if (likely(cur > offset))
8733                 ring->ring[offset] = cur - offset;
8734         else
8735                 ring->ring[offset] = (ring->buf_mask + 1) - offset + cur;
8736 }
8737
8738 static int gfx_v10_0_ring_preempt_ib(struct amdgpu_ring *ring)
8739 {
8740         int i, r = 0;
8741         struct amdgpu_device *adev = ring->adev;
8742         struct amdgpu_kiq *kiq = &adev->gfx.kiq;
8743         struct amdgpu_ring *kiq_ring = &kiq->ring;
8744         unsigned long flags;
8745
8746         if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues)
8747                 return -EINVAL;
8748
8749         spin_lock_irqsave(&kiq->ring_lock, flags);
8750
8751         if (amdgpu_ring_alloc(kiq_ring, kiq->pmf->unmap_queues_size)) {
8752                 spin_unlock_irqrestore(&kiq->ring_lock, flags);
8753                 return -ENOMEM;
8754         }
8755
8756         /* assert preemption condition */
8757         amdgpu_ring_set_preempt_cond_exec(ring, false);
8758
8759         /* assert IB preemption, emit the trailing fence */
8760         kiq->pmf->kiq_unmap_queues(kiq_ring, ring, PREEMPT_QUEUES_NO_UNMAP,
8761                                    ring->trail_fence_gpu_addr,
8762                                    ++ring->trail_seq);
8763         amdgpu_ring_commit(kiq_ring);
8764
8765         spin_unlock_irqrestore(&kiq->ring_lock, flags);
8766
8767         /* poll the trailing fence */
8768         for (i = 0; i < adev->usec_timeout; i++) {
8769                 if (ring->trail_seq ==
8770                     le32_to_cpu(*(ring->trail_fence_cpu_addr)))
8771                         break;
8772                 udelay(1);
8773         }
8774
8775         if (i >= adev->usec_timeout) {
8776                 r = -EINVAL;
8777                 DRM_ERROR("ring %d failed to preempt ib\n", ring->idx);
8778         }
8779
8780         /* deassert preemption condition */
8781         amdgpu_ring_set_preempt_cond_exec(ring, true);
8782         return r;
8783 }
8784
8785 static void gfx_v10_0_ring_emit_ce_meta(struct amdgpu_ring *ring, bool resume)
8786 {
8787         struct amdgpu_device *adev = ring->adev;
8788         struct v10_ce_ib_state ce_payload = {0};
8789         uint64_t csa_addr;
8790         int cnt;
8791
8792         cnt = (sizeof(ce_payload) >> 2) + 4 - 2;
8793         csa_addr = amdgpu_csa_vaddr(ring->adev);
8794
8795         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt));
8796         amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(2) |
8797                                  WRITE_DATA_DST_SEL(8) |
8798                                  WR_CONFIRM) |
8799                                  WRITE_DATA_CACHE_POLICY(0));
8800         amdgpu_ring_write(ring, lower_32_bits(csa_addr +
8801                               offsetof(struct v10_gfx_meta_data, ce_payload)));
8802         amdgpu_ring_write(ring, upper_32_bits(csa_addr +
8803                               offsetof(struct v10_gfx_meta_data, ce_payload)));
8804
8805         if (resume)
8806                 amdgpu_ring_write_multiple(ring, adev->virt.csa_cpu_addr +
8807                                            offsetof(struct v10_gfx_meta_data,
8808                                                     ce_payload),
8809                                            sizeof(ce_payload) >> 2);
8810         else
8811                 amdgpu_ring_write_multiple(ring, (void *)&ce_payload,
8812                                            sizeof(ce_payload) >> 2);
8813 }
8814
8815 static void gfx_v10_0_ring_emit_de_meta(struct amdgpu_ring *ring, bool resume)
8816 {
8817         struct amdgpu_device *adev = ring->adev;
8818         struct v10_de_ib_state de_payload = {0};
8819         uint64_t csa_addr, gds_addr;
8820         int cnt;
8821
8822         csa_addr = amdgpu_csa_vaddr(ring->adev);
8823         gds_addr = ALIGN(csa_addr + AMDGPU_CSA_SIZE - adev->gds.gds_size,
8824                          PAGE_SIZE);
8825         de_payload.gds_backup_addrlo = lower_32_bits(gds_addr);
8826         de_payload.gds_backup_addrhi = upper_32_bits(gds_addr);
8827
8828         cnt = (sizeof(de_payload) >> 2) + 4 - 2;
8829         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt));
8830         amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(1) |
8831                                  WRITE_DATA_DST_SEL(8) |
8832                                  WR_CONFIRM) |
8833                                  WRITE_DATA_CACHE_POLICY(0));
8834         amdgpu_ring_write(ring, lower_32_bits(csa_addr +
8835                               offsetof(struct v10_gfx_meta_data, de_payload)));
8836         amdgpu_ring_write(ring, upper_32_bits(csa_addr +
8837                               offsetof(struct v10_gfx_meta_data, de_payload)));
8838
8839         if (resume)
8840                 amdgpu_ring_write_multiple(ring, adev->virt.csa_cpu_addr +
8841                                            offsetof(struct v10_gfx_meta_data,
8842                                                     de_payload),
8843                                            sizeof(de_payload) >> 2);
8844         else
8845                 amdgpu_ring_write_multiple(ring, (void *)&de_payload,
8846                                            sizeof(de_payload) >> 2);
8847 }
8848
8849 static void gfx_v10_0_ring_emit_frame_cntl(struct amdgpu_ring *ring, bool start,
8850                                     bool secure)
8851 {
8852         uint32_t v = secure ? FRAME_TMZ : 0;
8853
8854         amdgpu_ring_write(ring, PACKET3(PACKET3_FRAME_CONTROL, 0));
8855         amdgpu_ring_write(ring, v | FRAME_CMD(start ? 0 : 1));
8856 }
8857
8858 static void gfx_v10_0_ring_emit_rreg(struct amdgpu_ring *ring, uint32_t reg,
8859                                      uint32_t reg_val_offs)
8860 {
8861         struct amdgpu_device *adev = ring->adev;
8862
8863         amdgpu_ring_write(ring, PACKET3(PACKET3_COPY_DATA, 4));
8864         amdgpu_ring_write(ring, 0 |     /* src: register*/
8865                                 (5 << 8) |      /* dst: memory */
8866                                 (1 << 20));     /* write confirm */
8867         amdgpu_ring_write(ring, reg);
8868         amdgpu_ring_write(ring, 0);
8869         amdgpu_ring_write(ring, lower_32_bits(adev->wb.gpu_addr +
8870                                 reg_val_offs * 4));
8871         amdgpu_ring_write(ring, upper_32_bits(adev->wb.gpu_addr +
8872                                 reg_val_offs * 4));
8873 }
8874
8875 static void gfx_v10_0_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg,
8876                                    uint32_t val)
8877 {
8878         uint32_t cmd = 0;
8879
8880         switch (ring->funcs->type) {
8881         case AMDGPU_RING_TYPE_GFX:
8882                 cmd = WRITE_DATA_ENGINE_SEL(1) | WR_CONFIRM;
8883                 break;
8884         case AMDGPU_RING_TYPE_KIQ:
8885                 cmd = (1 << 16); /* no inc addr */
8886                 break;
8887         default:
8888                 cmd = WR_CONFIRM;
8889                 break;
8890         }
8891         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
8892         amdgpu_ring_write(ring, cmd);
8893         amdgpu_ring_write(ring, reg);
8894         amdgpu_ring_write(ring, 0);
8895         amdgpu_ring_write(ring, val);
8896 }
8897
8898 static void gfx_v10_0_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,
8899                                         uint32_t val, uint32_t mask)
8900 {
8901         gfx_v10_0_wait_reg_mem(ring, 0, 0, 0, reg, 0, val, mask, 0x20);
8902 }
8903
8904 static void gfx_v10_0_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring,
8905                                                    uint32_t reg0, uint32_t reg1,
8906                                                    uint32_t ref, uint32_t mask)
8907 {
8908         int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
8909         struct amdgpu_device *adev = ring->adev;
8910         bool fw_version_ok = false;
8911
8912         fw_version_ok = adev->gfx.cp_fw_write_wait;
8913
8914         if (fw_version_ok)
8915                 gfx_v10_0_wait_reg_mem(ring, usepfp, 0, 1, reg0, reg1,
8916                                        ref, mask, 0x20);
8917         else
8918                 amdgpu_ring_emit_reg_write_reg_wait_helper(ring, reg0, reg1,
8919                                                            ref, mask);
8920 }
8921
8922 static void gfx_v10_0_ring_soft_recovery(struct amdgpu_ring *ring,
8923                                          unsigned vmid)
8924 {
8925         struct amdgpu_device *adev = ring->adev;
8926         uint32_t value = 0;
8927
8928         value = REG_SET_FIELD(value, SQ_CMD, CMD, 0x03);
8929         value = REG_SET_FIELD(value, SQ_CMD, MODE, 0x01);
8930         value = REG_SET_FIELD(value, SQ_CMD, CHECK_VMID, 1);
8931         value = REG_SET_FIELD(value, SQ_CMD, VM_ID, vmid);
8932         WREG32_SOC15(GC, 0, mmSQ_CMD, value);
8933 }
8934
8935 static void
8936 gfx_v10_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev,
8937                                       uint32_t me, uint32_t pipe,
8938                                       enum amdgpu_interrupt_state state)
8939 {
8940         uint32_t cp_int_cntl, cp_int_cntl_reg;
8941
8942         if (!me) {
8943                 switch (pipe) {
8944                 case 0:
8945                         cp_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_INT_CNTL_RING0);
8946                         break;
8947                 case 1:
8948                         cp_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_INT_CNTL_RING1);
8949                         break;
8950                 default:
8951                         DRM_DEBUG("invalid pipe %d\n", pipe);
8952                         return;
8953                 }
8954         } else {
8955                 DRM_DEBUG("invalid me %d\n", me);
8956                 return;
8957         }
8958
8959         switch (state) {
8960         case AMDGPU_IRQ_STATE_DISABLE:
8961                 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg);
8962                 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
8963                                             TIME_STAMP_INT_ENABLE, 0);
8964                 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl);
8965                 break;
8966         case AMDGPU_IRQ_STATE_ENABLE:
8967                 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg);
8968                 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
8969                                             TIME_STAMP_INT_ENABLE, 1);
8970                 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl);
8971                 break;
8972         default:
8973                 break;
8974         }
8975 }
8976
8977 static void gfx_v10_0_set_compute_eop_interrupt_state(struct amdgpu_device *adev,
8978                                                      int me, int pipe,
8979                                                      enum amdgpu_interrupt_state state)
8980 {
8981         u32 mec_int_cntl, mec_int_cntl_reg;
8982
8983         /*
8984          * amdgpu controls only the first MEC. That's why this function only
8985          * handles the setting of interrupts for this specific MEC. All other
8986          * pipes' interrupts are set by amdkfd.
8987          */
8988
8989         if (me == 1) {
8990                 switch (pipe) {
8991                 case 0:
8992                         mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE0_INT_CNTL);
8993                         break;
8994                 case 1:
8995                         mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE1_INT_CNTL);
8996                         break;
8997                 case 2:
8998                         mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE2_INT_CNTL);
8999                         break;
9000                 case 3:
9001                         mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE3_INT_CNTL);
9002                         break;
9003                 default:
9004                         DRM_DEBUG("invalid pipe %d\n", pipe);
9005                         return;
9006                 }
9007         } else {
9008                 DRM_DEBUG("invalid me %d\n", me);
9009                 return;
9010         }
9011
9012         switch (state) {
9013         case AMDGPU_IRQ_STATE_DISABLE:
9014                 mec_int_cntl = RREG32_SOC15_IP(GC, mec_int_cntl_reg);
9015                 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,
9016                                              TIME_STAMP_INT_ENABLE, 0);
9017                 WREG32_SOC15_IP(GC, mec_int_cntl_reg, mec_int_cntl);
9018                 break;
9019         case AMDGPU_IRQ_STATE_ENABLE:
9020                 mec_int_cntl = RREG32_SOC15_IP(GC, mec_int_cntl_reg);
9021                 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,
9022                                              TIME_STAMP_INT_ENABLE, 1);
9023                 WREG32_SOC15_IP(GC, mec_int_cntl_reg, mec_int_cntl);
9024                 break;
9025         default:
9026                 break;
9027         }
9028 }
9029
9030 static int gfx_v10_0_set_eop_interrupt_state(struct amdgpu_device *adev,
9031                                             struct amdgpu_irq_src *src,
9032                                             unsigned type,
9033                                             enum amdgpu_interrupt_state state)
9034 {
9035         switch (type) {
9036         case AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP:
9037                 gfx_v10_0_set_gfx_eop_interrupt_state(adev, 0, 0, state);
9038                 break;
9039         case AMDGPU_CP_IRQ_GFX_ME0_PIPE1_EOP:
9040                 gfx_v10_0_set_gfx_eop_interrupt_state(adev, 0, 1, state);
9041                 break;
9042         case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP:
9043                 gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 0, state);
9044                 break;
9045         case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP:
9046                 gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 1, state);
9047                 break;
9048         case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP:
9049                 gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 2, state);
9050                 break;
9051         case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP:
9052                 gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 3, state);
9053                 break;
9054         case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP:
9055                 gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 0, state);
9056                 break;
9057         case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP:
9058                 gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 1, state);
9059                 break;
9060         case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP:
9061                 gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 2, state);
9062                 break;
9063         case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP:
9064                 gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 3, state);
9065                 break;
9066         default:
9067                 break;
9068         }
9069         return 0;
9070 }
9071
9072 static int gfx_v10_0_eop_irq(struct amdgpu_device *adev,
9073                              struct amdgpu_irq_src *source,
9074                              struct amdgpu_iv_entry *entry)
9075 {
9076         int i;
9077         u8 me_id, pipe_id, queue_id;
9078         struct amdgpu_ring *ring;
9079
9080         DRM_DEBUG("IH: CP EOP\n");
9081         me_id = (entry->ring_id & 0x0c) >> 2;
9082         pipe_id = (entry->ring_id & 0x03) >> 0;
9083         queue_id = (entry->ring_id & 0x70) >> 4;
9084
9085         switch (me_id) {
9086         case 0:
9087                 if (pipe_id == 0)
9088                         amdgpu_fence_process(&adev->gfx.gfx_ring[0]);
9089                 else
9090                         amdgpu_fence_process(&adev->gfx.gfx_ring[1]);
9091                 break;
9092         case 1:
9093         case 2:
9094                 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
9095                         ring = &adev->gfx.compute_ring[i];
9096                         /* Per-queue interrupt is supported for MEC starting from VI.
9097                           * The interrupt can only be enabled/disabled per pipe instead of per queue.
9098                           */
9099                         if ((ring->me == me_id) && (ring->pipe == pipe_id) && (ring->queue == queue_id))
9100                                 amdgpu_fence_process(ring);
9101                 }
9102                 break;
9103         }
9104         return 0;
9105 }
9106
9107 static int gfx_v10_0_set_priv_reg_fault_state(struct amdgpu_device *adev,
9108                                               struct amdgpu_irq_src *source,
9109                                               unsigned type,
9110                                               enum amdgpu_interrupt_state state)
9111 {
9112         switch (state) {
9113         case AMDGPU_IRQ_STATE_DISABLE:
9114         case AMDGPU_IRQ_STATE_ENABLE:
9115                 WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0,
9116                                PRIV_REG_INT_ENABLE,
9117                                state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
9118                 break;
9119         default:
9120                 break;
9121         }
9122
9123         return 0;
9124 }
9125
9126 static int gfx_v10_0_set_priv_inst_fault_state(struct amdgpu_device *adev,
9127                                                struct amdgpu_irq_src *source,
9128                                                unsigned type,
9129                                                enum amdgpu_interrupt_state state)
9130 {
9131         switch (state) {
9132         case AMDGPU_IRQ_STATE_DISABLE:
9133         case AMDGPU_IRQ_STATE_ENABLE:
9134                 WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0,
9135                                PRIV_INSTR_INT_ENABLE,
9136                                state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
9137                 break;
9138         default:
9139                 break;
9140         }
9141
9142         return 0;
9143 }
9144
9145 static void gfx_v10_0_handle_priv_fault(struct amdgpu_device *adev,
9146                                         struct amdgpu_iv_entry *entry)
9147 {
9148         u8 me_id, pipe_id, queue_id;
9149         struct amdgpu_ring *ring;
9150         int i;
9151
9152         me_id = (entry->ring_id & 0x0c) >> 2;
9153         pipe_id = (entry->ring_id & 0x03) >> 0;
9154         queue_id = (entry->ring_id & 0x70) >> 4;
9155
9156         switch (me_id) {
9157         case 0:
9158                 for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
9159                         ring = &adev->gfx.gfx_ring[i];
9160                         /* we only enabled 1 gfx queue per pipe for now */
9161                         if (ring->me == me_id && ring->pipe == pipe_id)
9162                                 drm_sched_fault(&ring->sched);
9163                 }
9164                 break;
9165         case 1:
9166         case 2:
9167                 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
9168                         ring = &adev->gfx.compute_ring[i];
9169                         if (ring->me == me_id && ring->pipe == pipe_id &&
9170                             ring->queue == queue_id)
9171                                 drm_sched_fault(&ring->sched);
9172                 }
9173                 break;
9174         default:
9175                 BUG();
9176         }
9177 }
9178
9179 static int gfx_v10_0_priv_reg_irq(struct amdgpu_device *adev,
9180                                   struct amdgpu_irq_src *source,
9181                                   struct amdgpu_iv_entry *entry)
9182 {
9183         DRM_ERROR("Illegal register access in command stream\n");
9184         gfx_v10_0_handle_priv_fault(adev, entry);
9185         return 0;
9186 }
9187
9188 static int gfx_v10_0_priv_inst_irq(struct amdgpu_device *adev,
9189                                    struct amdgpu_irq_src *source,
9190                                    struct amdgpu_iv_entry *entry)
9191 {
9192         DRM_ERROR("Illegal instruction in command stream\n");
9193         gfx_v10_0_handle_priv_fault(adev, entry);
9194         return 0;
9195 }
9196
9197 static int gfx_v10_0_kiq_set_interrupt_state(struct amdgpu_device *adev,
9198                                              struct amdgpu_irq_src *src,
9199                                              unsigned int type,
9200                                              enum amdgpu_interrupt_state state)
9201 {
9202         uint32_t tmp, target;
9203         struct amdgpu_ring *ring = &(adev->gfx.kiq.ring);
9204
9205         if (ring->me == 1)
9206                 target = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE0_INT_CNTL);
9207         else
9208                 target = SOC15_REG_OFFSET(GC, 0, mmCP_ME2_PIPE0_INT_CNTL);
9209         target += ring->pipe;
9210
9211         switch (type) {
9212         case AMDGPU_CP_KIQ_IRQ_DRIVER0:
9213                 if (state == AMDGPU_IRQ_STATE_DISABLE) {
9214                         tmp = RREG32_SOC15(GC, 0, mmCPC_INT_CNTL);
9215                         tmp = REG_SET_FIELD(tmp, CPC_INT_CNTL,
9216                                             GENERIC2_INT_ENABLE, 0);
9217                         WREG32_SOC15(GC, 0, mmCPC_INT_CNTL, tmp);
9218
9219                         tmp = RREG32_SOC15_IP(GC, target);
9220                         tmp = REG_SET_FIELD(tmp, CP_ME2_PIPE0_INT_CNTL,
9221                                             GENERIC2_INT_ENABLE, 0);
9222                         WREG32_SOC15_IP(GC, target, tmp);
9223                 } else {
9224                         tmp = RREG32_SOC15(GC, 0, mmCPC_INT_CNTL);
9225                         tmp = REG_SET_FIELD(tmp, CPC_INT_CNTL,
9226                                             GENERIC2_INT_ENABLE, 1);
9227                         WREG32_SOC15(GC, 0, mmCPC_INT_CNTL, tmp);
9228
9229                         tmp = RREG32_SOC15_IP(GC, target);
9230                         tmp = REG_SET_FIELD(tmp, CP_ME2_PIPE0_INT_CNTL,
9231                                             GENERIC2_INT_ENABLE, 1);
9232                         WREG32_SOC15_IP(GC, target, tmp);
9233                 }
9234                 break;
9235         default:
9236                 BUG(); /* kiq only support GENERIC2_INT now */
9237                 break;
9238         }
9239         return 0;
9240 }
9241
9242 static int gfx_v10_0_kiq_irq(struct amdgpu_device *adev,
9243                              struct amdgpu_irq_src *source,
9244                              struct amdgpu_iv_entry *entry)
9245 {
9246         u8 me_id, pipe_id, queue_id;
9247         struct amdgpu_ring *ring = &(adev->gfx.kiq.ring);
9248
9249         me_id = (entry->ring_id & 0x0c) >> 2;
9250         pipe_id = (entry->ring_id & 0x03) >> 0;
9251         queue_id = (entry->ring_id & 0x70) >> 4;
9252         DRM_DEBUG("IH: CPC GENERIC2_INT, me:%d, pipe:%d, queue:%d\n",
9253                    me_id, pipe_id, queue_id);
9254
9255         amdgpu_fence_process(ring);
9256         return 0;
9257 }
9258
9259 static void gfx_v10_0_emit_mem_sync(struct amdgpu_ring *ring)
9260 {
9261         const unsigned int gcr_cntl =
9262                         PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_INV(1) |
9263                         PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_WB(1) |
9264                         PACKET3_ACQUIRE_MEM_GCR_CNTL_GLM_INV(1) |
9265                         PACKET3_ACQUIRE_MEM_GCR_CNTL_GLM_WB(1) |
9266                         PACKET3_ACQUIRE_MEM_GCR_CNTL_GL1_INV(1) |
9267                         PACKET3_ACQUIRE_MEM_GCR_CNTL_GLV_INV(1) |
9268                         PACKET3_ACQUIRE_MEM_GCR_CNTL_GLK_INV(1) |
9269                         PACKET3_ACQUIRE_MEM_GCR_CNTL_GLI_INV(1);
9270
9271         /* ACQUIRE_MEM - make one or more surfaces valid for use by the subsequent operations */
9272         amdgpu_ring_write(ring, PACKET3(PACKET3_ACQUIRE_MEM, 6));
9273         amdgpu_ring_write(ring, 0); /* CP_COHER_CNTL */
9274         amdgpu_ring_write(ring, 0xffffffff);  /* CP_COHER_SIZE */
9275         amdgpu_ring_write(ring, 0xffffff);  /* CP_COHER_SIZE_HI */
9276         amdgpu_ring_write(ring, 0); /* CP_COHER_BASE */
9277         amdgpu_ring_write(ring, 0);  /* CP_COHER_BASE_HI */
9278         amdgpu_ring_write(ring, 0x0000000A); /* POLL_INTERVAL */
9279         amdgpu_ring_write(ring, gcr_cntl); /* GCR_CNTL */
9280 }
9281
9282 static const struct amd_ip_funcs gfx_v10_0_ip_funcs = {
9283         .name = "gfx_v10_0",
9284         .early_init = gfx_v10_0_early_init,
9285         .late_init = gfx_v10_0_late_init,
9286         .sw_init = gfx_v10_0_sw_init,
9287         .sw_fini = gfx_v10_0_sw_fini,
9288         .hw_init = gfx_v10_0_hw_init,
9289         .hw_fini = gfx_v10_0_hw_fini,
9290         .suspend = gfx_v10_0_suspend,
9291         .resume = gfx_v10_0_resume,
9292         .is_idle = gfx_v10_0_is_idle,
9293         .wait_for_idle = gfx_v10_0_wait_for_idle,
9294         .soft_reset = gfx_v10_0_soft_reset,
9295         .set_clockgating_state = gfx_v10_0_set_clockgating_state,
9296         .set_powergating_state = gfx_v10_0_set_powergating_state,
9297         .get_clockgating_state = gfx_v10_0_get_clockgating_state,
9298 };
9299
9300 static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_gfx = {
9301         .type = AMDGPU_RING_TYPE_GFX,
9302         .align_mask = 0xff,
9303         .nop = PACKET3(PACKET3_NOP, 0x3FFF),
9304         .support_64bit_ptrs = true,
9305         .vmhub = AMDGPU_GFXHUB_0,
9306         .get_rptr = gfx_v10_0_ring_get_rptr_gfx,
9307         .get_wptr = gfx_v10_0_ring_get_wptr_gfx,
9308         .set_wptr = gfx_v10_0_ring_set_wptr_gfx,
9309         .emit_frame_size = /* totally 242 maximum if 16 IBs */
9310                 5 + /* COND_EXEC */
9311                 7 + /* PIPELINE_SYNC */
9312                 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 +
9313                 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 +
9314                 2 + /* VM_FLUSH */
9315                 8 + /* FENCE for VM_FLUSH */
9316                 20 + /* GDS switch */
9317                 4 + /* double SWITCH_BUFFER,
9318                      * the first COND_EXEC jump to the place
9319                      * just prior to this double SWITCH_BUFFER
9320                      */
9321                 5 + /* COND_EXEC */
9322                 7 + /* HDP_flush */
9323                 4 + /* VGT_flush */
9324                 14 + /* CE_META */
9325                 31 + /* DE_META */
9326                 3 + /* CNTX_CTRL */
9327                 5 + /* HDP_INVL */
9328                 8 + 8 + /* FENCE x2 */
9329                 2 + /* SWITCH_BUFFER */
9330                 8, /* gfx_v10_0_emit_mem_sync */
9331         .emit_ib_size = 4, /* gfx_v10_0_ring_emit_ib_gfx */
9332         .emit_ib = gfx_v10_0_ring_emit_ib_gfx,
9333         .emit_fence = gfx_v10_0_ring_emit_fence,
9334         .emit_pipeline_sync = gfx_v10_0_ring_emit_pipeline_sync,
9335         .emit_vm_flush = gfx_v10_0_ring_emit_vm_flush,
9336         .emit_gds_switch = gfx_v10_0_ring_emit_gds_switch,
9337         .emit_hdp_flush = gfx_v10_0_ring_emit_hdp_flush,
9338         .test_ring = gfx_v10_0_ring_test_ring,
9339         .test_ib = gfx_v10_0_ring_test_ib,
9340         .insert_nop = amdgpu_ring_insert_nop,
9341         .pad_ib = amdgpu_ring_generic_pad_ib,
9342         .emit_switch_buffer = gfx_v10_0_ring_emit_sb,
9343         .emit_cntxcntl = gfx_v10_0_ring_emit_cntxcntl,
9344         .init_cond_exec = gfx_v10_0_ring_emit_init_cond_exec,
9345         .patch_cond_exec = gfx_v10_0_ring_emit_patch_cond_exec,
9346         .preempt_ib = gfx_v10_0_ring_preempt_ib,
9347         .emit_frame_cntl = gfx_v10_0_ring_emit_frame_cntl,
9348         .emit_wreg = gfx_v10_0_ring_emit_wreg,
9349         .emit_reg_wait = gfx_v10_0_ring_emit_reg_wait,
9350         .emit_reg_write_reg_wait = gfx_v10_0_ring_emit_reg_write_reg_wait,
9351         .soft_recovery = gfx_v10_0_ring_soft_recovery,
9352         .emit_mem_sync = gfx_v10_0_emit_mem_sync,
9353 };
9354
9355 static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_compute = {
9356         .type = AMDGPU_RING_TYPE_COMPUTE,
9357         .align_mask = 0xff,
9358         .nop = PACKET3(PACKET3_NOP, 0x3FFF),
9359         .support_64bit_ptrs = true,
9360         .vmhub = AMDGPU_GFXHUB_0,
9361         .get_rptr = gfx_v10_0_ring_get_rptr_compute,
9362         .get_wptr = gfx_v10_0_ring_get_wptr_compute,
9363         .set_wptr = gfx_v10_0_ring_set_wptr_compute,
9364         .emit_frame_size =
9365                 20 + /* gfx_v10_0_ring_emit_gds_switch */
9366                 7 + /* gfx_v10_0_ring_emit_hdp_flush */
9367                 5 + /* hdp invalidate */
9368                 7 + /* gfx_v10_0_ring_emit_pipeline_sync */
9369                 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 +
9370                 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 +
9371                 2 + /* gfx_v10_0_ring_emit_vm_flush */
9372                 8 + 8 + 8 + /* gfx_v10_0_ring_emit_fence x3 for user fence, vm fence */
9373                 8, /* gfx_v10_0_emit_mem_sync */
9374         .emit_ib_size = 7, /* gfx_v10_0_ring_emit_ib_compute */
9375         .emit_ib = gfx_v10_0_ring_emit_ib_compute,
9376         .emit_fence = gfx_v10_0_ring_emit_fence,
9377         .emit_pipeline_sync = gfx_v10_0_ring_emit_pipeline_sync,
9378         .emit_vm_flush = gfx_v10_0_ring_emit_vm_flush,
9379         .emit_gds_switch = gfx_v10_0_ring_emit_gds_switch,
9380         .emit_hdp_flush = gfx_v10_0_ring_emit_hdp_flush,
9381         .test_ring = gfx_v10_0_ring_test_ring,
9382         .test_ib = gfx_v10_0_ring_test_ib,
9383         .insert_nop = amdgpu_ring_insert_nop,
9384         .pad_ib = amdgpu_ring_generic_pad_ib,
9385         .emit_wreg = gfx_v10_0_ring_emit_wreg,
9386         .emit_reg_wait = gfx_v10_0_ring_emit_reg_wait,
9387         .emit_reg_write_reg_wait = gfx_v10_0_ring_emit_reg_write_reg_wait,
9388         .emit_mem_sync = gfx_v10_0_emit_mem_sync,
9389 };
9390
9391 static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_kiq = {
9392         .type = AMDGPU_RING_TYPE_KIQ,
9393         .align_mask = 0xff,
9394         .nop = PACKET3(PACKET3_NOP, 0x3FFF),
9395         .support_64bit_ptrs = true,
9396         .vmhub = AMDGPU_GFXHUB_0,
9397         .get_rptr = gfx_v10_0_ring_get_rptr_compute,
9398         .get_wptr = gfx_v10_0_ring_get_wptr_compute,
9399         .set_wptr = gfx_v10_0_ring_set_wptr_compute,
9400         .emit_frame_size =
9401                 20 + /* gfx_v10_0_ring_emit_gds_switch */
9402                 7 + /* gfx_v10_0_ring_emit_hdp_flush */
9403                 5 + /*hdp invalidate */
9404                 7 + /* gfx_v10_0_ring_emit_pipeline_sync */
9405                 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 +
9406                 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 +
9407                 2 + /* gfx_v10_0_ring_emit_vm_flush */
9408                 8 + 8 + 8, /* gfx_v10_0_ring_emit_fence_kiq x3 for user fence, vm fence */
9409         .emit_ib_size = 7, /* gfx_v10_0_ring_emit_ib_compute */
9410         .emit_ib = gfx_v10_0_ring_emit_ib_compute,
9411         .emit_fence = gfx_v10_0_ring_emit_fence_kiq,
9412         .test_ring = gfx_v10_0_ring_test_ring,
9413         .test_ib = gfx_v10_0_ring_test_ib,
9414         .insert_nop = amdgpu_ring_insert_nop,
9415         .pad_ib = amdgpu_ring_generic_pad_ib,
9416         .emit_rreg = gfx_v10_0_ring_emit_rreg,
9417         .emit_wreg = gfx_v10_0_ring_emit_wreg,
9418         .emit_reg_wait = gfx_v10_0_ring_emit_reg_wait,
9419         .emit_reg_write_reg_wait = gfx_v10_0_ring_emit_reg_write_reg_wait,
9420 };
9421
9422 static void gfx_v10_0_set_ring_funcs(struct amdgpu_device *adev)
9423 {
9424         int i;
9425
9426         adev->gfx.kiq.ring.funcs = &gfx_v10_0_ring_funcs_kiq;
9427
9428         for (i = 0; i < adev->gfx.num_gfx_rings; i++)
9429                 adev->gfx.gfx_ring[i].funcs = &gfx_v10_0_ring_funcs_gfx;
9430
9431         for (i = 0; i < adev->gfx.num_compute_rings; i++)
9432                 adev->gfx.compute_ring[i].funcs = &gfx_v10_0_ring_funcs_compute;
9433 }
9434
9435 static const struct amdgpu_irq_src_funcs gfx_v10_0_eop_irq_funcs = {
9436         .set = gfx_v10_0_set_eop_interrupt_state,
9437         .process = gfx_v10_0_eop_irq,
9438 };
9439
9440 static const struct amdgpu_irq_src_funcs gfx_v10_0_priv_reg_irq_funcs = {
9441         .set = gfx_v10_0_set_priv_reg_fault_state,
9442         .process = gfx_v10_0_priv_reg_irq,
9443 };
9444
9445 static const struct amdgpu_irq_src_funcs gfx_v10_0_priv_inst_irq_funcs = {
9446         .set = gfx_v10_0_set_priv_inst_fault_state,
9447         .process = gfx_v10_0_priv_inst_irq,
9448 };
9449
9450 static const struct amdgpu_irq_src_funcs gfx_v10_0_kiq_irq_funcs = {
9451         .set = gfx_v10_0_kiq_set_interrupt_state,
9452         .process = gfx_v10_0_kiq_irq,
9453 };
9454
9455 static void gfx_v10_0_set_irq_funcs(struct amdgpu_device *adev)
9456 {
9457         adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST;
9458         adev->gfx.eop_irq.funcs = &gfx_v10_0_eop_irq_funcs;
9459
9460         adev->gfx.kiq.irq.num_types = AMDGPU_CP_KIQ_IRQ_LAST;
9461         adev->gfx.kiq.irq.funcs = &gfx_v10_0_kiq_irq_funcs;
9462
9463         adev->gfx.priv_reg_irq.num_types = 1;
9464         adev->gfx.priv_reg_irq.funcs = &gfx_v10_0_priv_reg_irq_funcs;
9465
9466         adev->gfx.priv_inst_irq.num_types = 1;
9467         adev->gfx.priv_inst_irq.funcs = &gfx_v10_0_priv_inst_irq_funcs;
9468 }
9469
9470 static void gfx_v10_0_set_rlc_funcs(struct amdgpu_device *adev)
9471 {
9472         switch (adev->ip_versions[GC_HWIP][0]) {
9473         case IP_VERSION(10, 1, 10):
9474         case IP_VERSION(10, 1, 1):
9475         case IP_VERSION(10, 1, 3):
9476         case IP_VERSION(10, 1, 4):
9477         case IP_VERSION(10, 3, 2):
9478         case IP_VERSION(10, 3, 1):
9479         case IP_VERSION(10, 3, 4):
9480         case IP_VERSION(10, 3, 5):
9481         case IP_VERSION(10, 3, 3):
9482         case IP_VERSION(10, 3, 7):
9483                 adev->gfx.rlc.funcs = &gfx_v10_0_rlc_funcs;
9484                 break;
9485         case IP_VERSION(10, 1, 2):
9486         case IP_VERSION(10, 3, 0):
9487                 adev->gfx.rlc.funcs = &gfx_v10_0_rlc_funcs_sriov;
9488                 break;
9489         default:
9490                 break;
9491         }
9492 }
9493
9494 static void gfx_v10_0_set_gds_init(struct amdgpu_device *adev)
9495 {
9496         unsigned total_cu = adev->gfx.config.max_cu_per_sh *
9497                             adev->gfx.config.max_sh_per_se *
9498                             adev->gfx.config.max_shader_engines;
9499
9500         adev->gds.gds_size = 0x10000;
9501         adev->gds.gds_compute_max_wave_id = total_cu * 32 - 1;
9502         adev->gds.gws_size = 64;
9503         adev->gds.oa_size = 16;
9504 }
9505
9506 static void gfx_v10_0_set_user_wgp_inactive_bitmap_per_sh(struct amdgpu_device *adev,
9507                                                           u32 bitmap)
9508 {
9509         u32 data;
9510
9511         if (!bitmap)
9512                 return;
9513
9514         data = bitmap << GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT;
9515         data &= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK;
9516
9517         WREG32_SOC15(GC, 0, mmGC_USER_SHADER_ARRAY_CONFIG, data);
9518 }
9519
9520 static u32 gfx_v10_0_get_wgp_active_bitmap_per_sh(struct amdgpu_device *adev)
9521 {
9522         u32 disabled_mask =
9523                 ~amdgpu_gfx_create_bitmask(adev->gfx.config.max_cu_per_sh >> 1);
9524         u32 efuse_setting = 0;
9525         u32 vbios_setting = 0;
9526
9527         efuse_setting = RREG32_SOC15(GC, 0, mmCC_GC_SHADER_ARRAY_CONFIG);
9528         efuse_setting &= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK;
9529         efuse_setting >>= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT;
9530
9531         vbios_setting = RREG32_SOC15(GC, 0, mmGC_USER_SHADER_ARRAY_CONFIG);
9532         vbios_setting &= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK;
9533         vbios_setting >>= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT;
9534
9535         disabled_mask |= efuse_setting | vbios_setting;
9536
9537         return (~disabled_mask);
9538 }
9539
9540 static u32 gfx_v10_0_get_cu_active_bitmap_per_sh(struct amdgpu_device *adev)
9541 {
9542         u32 wgp_idx, wgp_active_bitmap;
9543         u32 cu_bitmap_per_wgp, cu_active_bitmap;
9544
9545         wgp_active_bitmap = gfx_v10_0_get_wgp_active_bitmap_per_sh(adev);
9546         cu_active_bitmap = 0;
9547
9548         for (wgp_idx = 0; wgp_idx < 16; wgp_idx++) {
9549                 /* if there is one WGP enabled, it means 2 CUs will be enabled */
9550                 cu_bitmap_per_wgp = 3 << (2 * wgp_idx);
9551                 if (wgp_active_bitmap & (1 << wgp_idx))
9552                         cu_active_bitmap |= cu_bitmap_per_wgp;
9553         }
9554
9555         return cu_active_bitmap;
9556 }
9557
9558 static int gfx_v10_0_get_cu_info(struct amdgpu_device *adev,
9559                                  struct amdgpu_cu_info *cu_info)
9560 {
9561         int i, j, k, counter, active_cu_number = 0;
9562         u32 mask, bitmap, ao_bitmap, ao_cu_mask = 0;
9563         unsigned disable_masks[4 * 2];
9564
9565         if (!adev || !cu_info)
9566                 return -EINVAL;
9567
9568         amdgpu_gfx_parse_disable_cu(disable_masks, 4, 2);
9569
9570         mutex_lock(&adev->grbm_idx_mutex);
9571         for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
9572                 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
9573                         bitmap = i * adev->gfx.config.max_sh_per_se + j;
9574                         if (((adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 3, 0)) ||
9575                                 (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 3, 3)) ||
9576                                 (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 3, 7))) &&
9577                             ((gfx_v10_3_get_disabled_sa(adev) >> bitmap) & 1))
9578                                 continue;
9579                         mask = 1;
9580                         ao_bitmap = 0;
9581                         counter = 0;
9582                         gfx_v10_0_select_se_sh(adev, i, j, 0xffffffff);
9583                         if (i < 4 && j < 2)
9584                                 gfx_v10_0_set_user_wgp_inactive_bitmap_per_sh(
9585                                         adev, disable_masks[i * 2 + j]);
9586                         bitmap = gfx_v10_0_get_cu_active_bitmap_per_sh(adev);
9587                         cu_info->bitmap[i][j] = bitmap;
9588
9589                         for (k = 0; k < adev->gfx.config.max_cu_per_sh; k++) {
9590                                 if (bitmap & mask) {
9591                                         if (counter < adev->gfx.config.max_cu_per_sh)
9592                                                 ao_bitmap |= mask;
9593                                         counter++;
9594                                 }
9595                                 mask <<= 1;
9596                         }
9597                         active_cu_number += counter;
9598                         if (i < 2 && j < 2)
9599                                 ao_cu_mask |= (ao_bitmap << (i * 16 + j * 8));
9600                         cu_info->ao_cu_bitmap[i][j] = ao_bitmap;
9601                 }
9602         }
9603         gfx_v10_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
9604         mutex_unlock(&adev->grbm_idx_mutex);
9605
9606         cu_info->number = active_cu_number;
9607         cu_info->ao_cu_mask = ao_cu_mask;
9608         cu_info->simd_per_cu = NUM_SIMD_PER_CU;
9609
9610         return 0;
9611 }
9612
9613 static u32 gfx_v10_3_get_disabled_sa(struct amdgpu_device *adev)
9614 {
9615         uint32_t efuse_setting, vbios_setting, disabled_sa, max_sa_mask;
9616
9617         efuse_setting = RREG32_SOC15(GC, 0, mmCC_GC_SA_UNIT_DISABLE);
9618         efuse_setting &= CC_GC_SA_UNIT_DISABLE__SA_DISABLE_MASK;
9619         efuse_setting >>= CC_GC_SA_UNIT_DISABLE__SA_DISABLE__SHIFT;
9620
9621         vbios_setting = RREG32_SOC15(GC, 0, mmGC_USER_SA_UNIT_DISABLE);
9622         vbios_setting &= GC_USER_SA_UNIT_DISABLE__SA_DISABLE_MASK;
9623         vbios_setting >>= GC_USER_SA_UNIT_DISABLE__SA_DISABLE__SHIFT;
9624
9625         max_sa_mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_sh_per_se *
9626                                                 adev->gfx.config.max_shader_engines);
9627         disabled_sa = efuse_setting | vbios_setting;
9628         disabled_sa &= max_sa_mask;
9629
9630         return disabled_sa;
9631 }
9632
9633 static void gfx_v10_3_program_pbb_mode(struct amdgpu_device *adev)
9634 {
9635         uint32_t max_sa_per_se, max_sa_per_se_mask, max_shader_engines;
9636         uint32_t disabled_sa_mask, se_index, disabled_sa_per_se;
9637
9638         disabled_sa_mask = gfx_v10_3_get_disabled_sa(adev);
9639
9640         max_sa_per_se = adev->gfx.config.max_sh_per_se;
9641         max_sa_per_se_mask = (1 << max_sa_per_se) - 1;
9642         max_shader_engines = adev->gfx.config.max_shader_engines;
9643
9644         for (se_index = 0; max_shader_engines > se_index; se_index++) {
9645                 disabled_sa_per_se = disabled_sa_mask >> (se_index * max_sa_per_se);
9646                 disabled_sa_per_se &= max_sa_per_se_mask;
9647                 if (disabled_sa_per_se == max_sa_per_se_mask) {
9648                         WREG32_FIELD15(GC, 0, PA_SC_ENHANCE_3, FORCE_PBB_WORKLOAD_MODE_TO_ZERO, 1);
9649                         break;
9650                 }
9651         }
9652 }
9653
9654 static void gfx_v10_3_set_power_brake_sequence(struct amdgpu_device *adev)
9655 {
9656         WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX,
9657                      (0x1 << GRBM_GFX_INDEX__SA_BROADCAST_WRITES__SHIFT) |
9658                      (0x1 << GRBM_GFX_INDEX__INSTANCE_BROADCAST_WRITES__SHIFT) |
9659                      (0x1 << GRBM_GFX_INDEX__SE_BROADCAST_WRITES__SHIFT));
9660
9661         WREG32_SOC15(GC, 0, mmGC_CAC_IND_INDEX, ixPWRBRK_STALL_PATTERN_CTRL);
9662         WREG32_SOC15(GC, 0, mmGC_CAC_IND_DATA,
9663                      (0x1 << PWRBRK_STALL_PATTERN_CTRL__PWRBRK_STEP_INTERVAL__SHIFT) |
9664                      (0x12 << PWRBRK_STALL_PATTERN_CTRL__PWRBRK_BEGIN_STEP__SHIFT) |
9665                      (0x13 << PWRBRK_STALL_PATTERN_CTRL__PWRBRK_END_STEP__SHIFT) |
9666                      (0xf << PWRBRK_STALL_PATTERN_CTRL__PWRBRK_THROTTLE_PATTERN_BIT_NUMS__SHIFT));
9667
9668         WREG32_SOC15(GC, 0, mmGC_THROTTLE_CTRL_Sienna_Cichlid,
9669                      (0x1 << GC_THROTTLE_CTRL__PWRBRK_STALL_EN__SHIFT) |
9670                      (0x1 << GC_THROTTLE_CTRL__PATTERN_MODE__SHIFT) |
9671                      (0x5 << GC_THROTTLE_CTRL__RELEASE_STEP_INTERVAL__SHIFT));
9672
9673         WREG32_SOC15(GC, 0, mmDIDT_IND_INDEX, ixDIDT_SQ_THROTTLE_CTRL);
9674
9675         WREG32_SOC15(GC, 0, mmDIDT_IND_DATA,
9676                      (0x1 << DIDT_SQ_THROTTLE_CTRL__PWRBRK_STALL_EN__SHIFT));
9677 }
9678
9679 const struct amdgpu_ip_block_version gfx_v10_0_ip_block =
9680 {
9681         .type = AMD_IP_BLOCK_TYPE_GFX,
9682         .major = 10,
9683         .minor = 0,
9684         .rev = 0,
9685         .funcs = &gfx_v10_0_ip_funcs,
9686 };