drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

   1 /*
   2  * Copyright 2019 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #include <linux/delay.h>
  25 #include <linux/kernel.h>
  26 #include <linux/firmware.h>
  27 #include <linux/module.h>
  28 #include <linux/pci.h>
  29 #include "amdgpu.h"
  30 #include "amdgpu_gfx.h"
  31 #include "amdgpu_psp.h"
  32 #include "amdgpu_smu.h"
  33 #include "nv.h"
  34 #include "nvd.h"
  35
  36 #include "gc/gc_10_1_0_offset.h"
  37 #include "gc/gc_10_1_0_sh_mask.h"
  38 #include "smuio/smuio_11_0_0_offset.h"
  39 #include "smuio/smuio_11_0_0_sh_mask.h"
  40 #include "navi10_enum.h"
  41 #include "hdp/hdp_5_0_0_offset.h"
  42 #include "ivsrcid/gfx/irqsrcs_gfx_10_1.h"
  43
  44 #include "soc15.h"
  45 #include "soc15d.h"
  46 #include "soc15_common.h"
  47 #include "clearstate_gfx10.h"
  48 #include "v10_structs.h"
  49 #include "gfx_v10_0.h"
  50 #include "nbio_v2_3.h"
  51
  52 /**
  53  * Navi10 has two graphic rings to share each graphic pipe.
  54  * 1. Primary ring
  55  * 2. Async ring
  56  */
  57 #define GFX10_NUM_GFX_RINGS_NV1X        1
  58 #define GFX10_NUM_GFX_RINGS_Sienna_Cichlid      1
  59 #define GFX10_MEC_HPD_SIZE      2048
  60
  61 #define F32_CE_PROGRAM_RAM_SIZE         65536
  62 #define RLCG_UCODE_LOADING_START_ADDRESS        0x00002000L
  63
  64 #define mmCGTT_GS_NGG_CLK_CTRL  0x5087
  65 #define mmCGTT_GS_NGG_CLK_CTRL_BASE_IDX 1
  66 #define mmCGTT_SPI_RA0_CLK_CTRL 0x507a
  67 #define mmCGTT_SPI_RA0_CLK_CTRL_BASE_IDX 1
  68 #define mmCGTT_SPI_RA1_CLK_CTRL 0x507b
  69 #define mmCGTT_SPI_RA1_CLK_CTRL_BASE_IDX 1
  70
  71 #define GB_ADDR_CONFIG__NUM_PKRS__SHIFT                                                                       0x8
  72 #define GB_ADDR_CONFIG__NUM_PKRS_MASK                                                                         0x00000700L
  73
  74 #define mmCP_MEC_CNTL_Sienna_Cichlid                      0x0f55
  75 #define mmCP_MEC_CNTL_Sienna_Cichlid_BASE_IDX             0
  76 #define mmRLC_SAFE_MODE_Sienna_Cichlid                  0x4ca0
  77 #define mmRLC_SAFE_MODE_Sienna_Cichlid_BASE_IDX         1
  78 #define mmRLC_CP_SCHEDULERS_Sienna_Cichlid              0x4ca1
  79 #define mmRLC_CP_SCHEDULERS_Sienna_Cichlid_BASE_IDX     1
  80 #define mmSPI_CONFIG_CNTL_Sienna_Cichlid                        0x11ec
  81 #define mmSPI_CONFIG_CNTL_Sienna_Cichlid_BASE_IDX               0
  82 #define mmVGT_ESGS_RING_SIZE_Sienna_Cichlid             0x0fc1
  83 #define mmVGT_ESGS_RING_SIZE_Sienna_Cichlid_BASE_IDX    0
  84 #define mmVGT_GSVS_RING_SIZE_Sienna_Cichlid             0x0fc2
  85 #define mmVGT_GSVS_RING_SIZE_Sienna_Cichlid_BASE_IDX    0
  86 #define mmVGT_TF_RING_SIZE_Sienna_Cichlid                       0x0fc3
  87 #define mmVGT_TF_RING_SIZE_Sienna_Cichlid_BASE_IDX      0
  88 #define mmVGT_HS_OFFCHIP_PARAM_Sienna_Cichlid           0x0fc4
  89 #define mmVGT_HS_OFFCHIP_PARAM_Sienna_Cichlid_BASE_IDX  0
  90 #define mmVGT_TF_MEMORY_BASE_Sienna_Cichlid             0x0fc5
  91 #define mmVGT_TF_MEMORY_BASE_Sienna_Cichlid_BASE_IDX    0
  92 #define mmVGT_TF_MEMORY_BASE_HI_Sienna_Cichlid          0x0fc6
  93 #define mmVGT_TF_MEMORY_BASE_HI_Sienna_Cichlid_BASE_IDX 0
  94 #define GRBM_STATUS2__RLC_BUSY_Sienna_Cichlid__SHIFT    0x1a
  95 #define GRBM_STATUS2__RLC_BUSY_Sienna_Cichlid_MASK      0x04000000L
  96 #define CP_RB_DOORBELL_RANGE_LOWER__DOORBELL_RANGE_LOWER_Sienna_Cichlid_MASK    0x00000FFCL
  97 #define CP_RB_DOORBELL_RANGE_LOWER__DOORBELL_RANGE_LOWER_Sienna_Cichlid__SHIFT  0x2
  98 #define CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_Sienna_Cichlid_MASK    0x00000FFCL
  99 #define mmGCR_GENERAL_CNTL_Sienna_Cichlid                       0x1580
 100 #define mmGCR_GENERAL_CNTL_Sienna_Cichlid_BASE_IDX      0
 101
 102 #define mmSPI_CONFIG_CNTL_1_Vangogh              0x2441
 103 #define mmSPI_CONFIG_CNTL_1_Vangogh_BASE_IDX     1
 104 #define mmVGT_TF_MEMORY_BASE_HI_Vangogh          0x2261
 105 #define mmVGT_TF_MEMORY_BASE_HI_Vangogh_BASE_IDX 1
 106 #define mmVGT_HS_OFFCHIP_PARAM_Vangogh           0x224f
 107 #define mmVGT_HS_OFFCHIP_PARAM_Vangogh_BASE_IDX  1
 108 #define mmVGT_TF_RING_SIZE_Vangogh               0x224e
 109 #define mmVGT_TF_RING_SIZE_Vangogh_BASE_IDX      1
 110 #define mmVGT_GSVS_RING_SIZE_Vangogh             0x2241
 111 #define mmVGT_GSVS_RING_SIZE_Vangogh_BASE_IDX    1
 112 #define mmVGT_TF_MEMORY_BASE_Vangogh             0x2250
 113 #define mmVGT_TF_MEMORY_BASE_Vangogh_BASE_IDX    1
 114 #define mmVGT_ESGS_RING_SIZE_Vangogh             0x2240
 115 #define mmVGT_ESGS_RING_SIZE_Vangogh_BASE_IDX    1
 116 #define mmSPI_CONFIG_CNTL_Vangogh                0x2440
 117 #define mmSPI_CONFIG_CNTL_Vangogh_BASE_IDX       1
 118
 119 #define mmCP_HYP_PFP_UCODE_ADDR                 0x5814
 120 #define mmCP_HYP_PFP_UCODE_ADDR_BASE_IDX        1
 121 #define mmCP_HYP_PFP_UCODE_DATA                 0x5815
 122 #define mmCP_HYP_PFP_UCODE_DATA_BASE_IDX        1
 123 #define mmCP_HYP_CE_UCODE_ADDR                  0x5818
 124 #define mmCP_HYP_CE_UCODE_ADDR_BASE_IDX         1
 125 #define mmCP_HYP_CE_UCODE_DATA                  0x5819
 126 #define mmCP_HYP_CE_UCODE_DATA_BASE_IDX         1
 127 #define mmCP_HYP_ME_UCODE_ADDR                  0x5816
 128 #define mmCP_HYP_ME_UCODE_ADDR_BASE_IDX         1
 129 #define mmCP_HYP_ME_UCODE_DATA                  0x5817
 130 #define mmCP_HYP_ME_UCODE_DATA_BASE_IDX         1
 131
 132 #define mmCPG_PSP_DEBUG                         0x5c10
 133 #define mmCPG_PSP_DEBUG_BASE_IDX                1
 134 #define mmCPC_PSP_DEBUG                         0x5c11
 135 #define mmCPC_PSP_DEBUG_BASE_IDX                1
 136 #define CPC_PSP_DEBUG__GPA_OVERRIDE_MASK        0x00000008L
 137 #define CPG_PSP_DEBUG__GPA_OVERRIDE_MASK        0x00000008L
 138
 139 //CC_GC_SA_UNIT_DISABLE
 140 #define mmCC_GC_SA_UNIT_DISABLE                 0x0fe9
 141 #define mmCC_GC_SA_UNIT_DISABLE_BASE_IDX        0
 142 #define CC_GC_SA_UNIT_DISABLE__SA_DISABLE__SHIFT        0x8
 143 #define CC_GC_SA_UNIT_DISABLE__SA_DISABLE_MASK          0x0000FF00L
 144 //GC_USER_SA_UNIT_DISABLE
 145 #define mmGC_USER_SA_UNIT_DISABLE               0x0fea
 146 #define mmGC_USER_SA_UNIT_DISABLE_BASE_IDX      0
 147 #define GC_USER_SA_UNIT_DISABLE__SA_DISABLE__SHIFT      0x8
 148 #define GC_USER_SA_UNIT_DISABLE__SA_DISABLE_MASK        0x0000FF00L
 149 //PA_SC_ENHANCE_3
 150 #define mmPA_SC_ENHANCE_3                       0x1085
 151 #define mmPA_SC_ENHANCE_3_BASE_IDX              0
 152 #define PA_SC_ENHANCE_3__FORCE_PBB_WORKLOAD_MODE_TO_ZERO__SHIFT 0x3
 153 #define PA_SC_ENHANCE_3__FORCE_PBB_WORKLOAD_MODE_TO_ZERO_MASK   0x00000008L
 154
 155 #define mmCGTT_SPI_CS_CLK_CTRL                  0x507c
 156 #define mmCGTT_SPI_CS_CLK_CTRL_BASE_IDX         1
 157
 158 MODULE_FIRMWARE("amdgpu/navi10_ce.bin");
 159 MODULE_FIRMWARE("amdgpu/navi10_pfp.bin");
 160 MODULE_FIRMWARE("amdgpu/navi10_me.bin");
 161 MODULE_FIRMWARE("amdgpu/navi10_mec.bin");
 162 MODULE_FIRMWARE("amdgpu/navi10_mec2.bin");
 163 MODULE_FIRMWARE("amdgpu/navi10_rlc.bin");
 164
 165 MODULE_FIRMWARE("amdgpu/navi14_ce_wks.bin");
 166 MODULE_FIRMWARE("amdgpu/navi14_pfp_wks.bin");
 167 MODULE_FIRMWARE("amdgpu/navi14_me_wks.bin");
 168 MODULE_FIRMWARE("amdgpu/navi14_mec_wks.bin");
 169 MODULE_FIRMWARE("amdgpu/navi14_mec2_wks.bin");
 170 MODULE_FIRMWARE("amdgpu/navi14_ce.bin");
 171 MODULE_FIRMWARE("amdgpu/navi14_pfp.bin");
 172 MODULE_FIRMWARE("amdgpu/navi14_me.bin");
 173 MODULE_FIRMWARE("amdgpu/navi14_mec.bin");
 174 MODULE_FIRMWARE("amdgpu/navi14_mec2.bin");
 175 MODULE_FIRMWARE("amdgpu/navi14_rlc.bin");
 176
 177 MODULE_FIRMWARE("amdgpu/navi12_ce.bin");
 178 MODULE_FIRMWARE("amdgpu/navi12_pfp.bin");
 179 MODULE_FIRMWARE("amdgpu/navi12_me.bin");
 180 MODULE_FIRMWARE("amdgpu/navi12_mec.bin");
 181 MODULE_FIRMWARE("amdgpu/navi12_mec2.bin");
 182 MODULE_FIRMWARE("amdgpu/navi12_rlc.bin");
 183
 184 MODULE_FIRMWARE("amdgpu/sienna_cichlid_ce.bin");
 185 MODULE_FIRMWARE("amdgpu/sienna_cichlid_pfp.bin");
 186 MODULE_FIRMWARE("amdgpu/sienna_cichlid_me.bin");
 187 MODULE_FIRMWARE("amdgpu/sienna_cichlid_mec.bin");
 188 MODULE_FIRMWARE("amdgpu/sienna_cichlid_mec2.bin");
 189 MODULE_FIRMWARE("amdgpu/sienna_cichlid_rlc.bin");
 190
 191 MODULE_FIRMWARE("amdgpu/navy_flounder_ce.bin");
 192 MODULE_FIRMWARE("amdgpu/navy_flounder_pfp.bin");
 193 MODULE_FIRMWARE("amdgpu/navy_flounder_me.bin");
 194 MODULE_FIRMWARE("amdgpu/navy_flounder_mec.bin");
 195 MODULE_FIRMWARE("amdgpu/navy_flounder_mec2.bin");
 196 MODULE_FIRMWARE("amdgpu/navy_flounder_rlc.bin");
 197
 198 MODULE_FIRMWARE("amdgpu/vangogh_ce.bin");
 199 MODULE_FIRMWARE("amdgpu/vangogh_pfp.bin");
 200 MODULE_FIRMWARE("amdgpu/vangogh_me.bin");
 201 MODULE_FIRMWARE("amdgpu/vangogh_mec.bin");
 202 MODULE_FIRMWARE("amdgpu/vangogh_mec2.bin");
 203 MODULE_FIRMWARE("amdgpu/vangogh_rlc.bin");
 204
 205 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_ce.bin");
 206 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_pfp.bin");
 207 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_me.bin");
 208 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_mec.bin");
 209 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_mec2.bin");
 210 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_rlc.bin");
 211
 212 static const struct soc15_reg_golden golden_settings_gc_10_1[] =
 213 {
 214         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0xffffffff, 0x00400014),
 215         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_CPF_CLK_CTRL, 0xfcff8fff, 0xf8000100),
 216         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xcd000000, 0x0d000100),
 217         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQ_CLK_CTRL, 0x60000ff0, 0x60000100),
 218         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQG_CLK_CTRL, 0x40000000, 0x40000100),
 219         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xffff8fff, 0xffff8100),
 220         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_WD_CLK_CTRL, 0xfeff8fff, 0xfeff8100),
 221         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
 222         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_VC5_ENABLE, 0x00000002, 0x00000000),
 223         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0x000007ff, 0x000005ff),
 224         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG, 0x20000000, 0x20000000),
 225         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xffffffff, 0x00000420),
 226         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0x00000200, 0x00000200),
 227         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0x07900000, 0x04900000),
 228         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DFSM_TILES_IN_FLIGHT, 0x0000ffff, 0x0000003f),
 229         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_LAST_OF_BURST_CONFIG, 0xffffffff, 0x03860204),
 230         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff0ffff, 0x00000500),
 231         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PRIV_CONTROL, 0x000007ff, 0x000001fe),
 232         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
 233         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x10321032),
 234         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x02310231),
 235         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
 236         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
 237         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CGTT_SCLK_CTRL, 0x10000000, 0x10000100),
 238         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL2, 0xffffffff, 0x1402002f),
 239         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xffff9fff, 0x00001188),
 240         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
 241         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x08000009),
 242         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0x00400000, 0x04440000),
 243         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0x00000800, 0x00000820),
 244         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000),
 245         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0xffffffff, 0xffff3101),
 246         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0x001f0000, 0x00070104),
 247         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ALU_CLK_CTRL, 0xffffffff, 0xffffffff),
 248         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x00000100, 0x00000130),
 249         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0xffffffff, 0xffffffff),
 250         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
 251         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CNTL, 0x60000010, 0x479c0010),
 252         SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CGTT_CLK_CTRL, 0xfeff0fff, 0x40000100),
 253         SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0x00c00000, 0x00c00000)
 254 };
 255
 256 static const struct soc15_reg_golden golden_settings_gc_10_0_nv10[] =
 257 {
 258         /* Pending on emulation bring up */
 259 };
 260
 261 static const struct soc15_reg_golden golden_settings_gc_rlc_spm_10_0_nv10[] =
 262 {
 263         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xe0000000, 0x0),
 264         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 265         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
 266         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 267         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
 268         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 269         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
 270         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 271         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
 272         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 273         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
 274         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 275         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
 276         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 277         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
 278         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 279         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 280         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 281         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8),
 282         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 283         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
 284         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 285         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc),
 286         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 287         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
 288         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 289         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0),
 290         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 291         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
 292         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 293         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4),
 294         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 295         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
 296         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 297         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
 298         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 299         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
 300         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 301         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
 302         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 303         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
 304         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 305         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
 306         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 307         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
 308         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 309         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
 310         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 311         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
 312         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 313         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
 314         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 315         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
 316         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 317         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
 318         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 319         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
 320         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 321         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
 322         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 323         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
 324         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 325         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
 326         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 327         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
 328         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 329         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
 330         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 331         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
 332         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 333         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0),
 334         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 335         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
 336         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 337         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4),
 338         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 339         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
 340         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 341         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8),
 342         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 343         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 344         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 345         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc),
 346         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 347         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
 348         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 349         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0),
 350         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 351         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 352         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 353         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4),
 354         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 355         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 356         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 357         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90),
 358         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 359         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
 360         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 361         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94),
 362         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 363         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
 364         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 365         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98),
 366         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 367         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
 368         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 369         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c),
 370         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 371         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
 372         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 373         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0),
 374         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 375         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
 376         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 377         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4),
 378         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 379         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
 380         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 381         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8),
 382         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 383         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
 384         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 385         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac),
 386         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 387         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
 388         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 389         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
 390         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 391         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
 392         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 393         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
 394         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 395         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
 396         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 397         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
 398         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 399         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
 400         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 401         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
 402         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 403         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
 404         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 405         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
 406         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 407         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
 408         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 409         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
 410         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 411         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 412         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 413         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
 414         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 415         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
 416         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 417         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
 418         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 419         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
 420         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 421         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
 422         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 423         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
 424         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 425         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
 426         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 427         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
 428         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 429         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
 430         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 431         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
 432         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 433         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
 434         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 435         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
 436         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 437         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
 438         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 439         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
 440         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 441         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
 442         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 443         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
 444         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 445         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
 446         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 447         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
 448         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 449         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
 450         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 451         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
 452         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 453         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
 454         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 455         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
 456         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 457         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
 458         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 459         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
 460         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 461         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
 462         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 463         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
 464         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 465         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
 466         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 467         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
 468         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 469         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
 470         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 471         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
 472         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 473         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
 474         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 475         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
 476         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 477         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
 478         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 479         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
 480         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 481         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c),
 482         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 483         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
 484         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 485         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
 486         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 487         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 488         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 489         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
 490         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 491         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
 492         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 493         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
 494         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 495         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
 496         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 497         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
 498         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 499         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
 500         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 501         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
 502         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 503         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
 504         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 505         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
 506         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 507         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 508         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 509         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
 510         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 511         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 512         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 513         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
 514         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 515         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
 516         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 517         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
 518         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 519         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
 520         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 521         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
 522         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 523         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 524         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 525         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
 526         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 527         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 528         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 529         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
 530         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 531         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
 532         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 533         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
 534         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 535         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
 536         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 537         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
 538         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 539         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 540         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 541         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
 542         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 543         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 544         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 545         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
 546         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 547         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
 548         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 549         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
 550         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 551         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
 552         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 553         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
 554         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 555         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
 556         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 557         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
 558         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 559         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
 560         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 561         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
 562         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 563         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 564         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 565         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
 566         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 567         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 568         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 569         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
 570         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 571         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 572         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 573         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
 574         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 575         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 576         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 577         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
 578         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 579         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 580         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 581         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
 582         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 583         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 584         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 585         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
 586         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 587         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 588         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 589         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
 590         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 591         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 592         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 593         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
 594         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 595         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
 596         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 597         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
 598         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 599         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
 600         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 601         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
 602         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 603         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
 604         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 605         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
 606         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 607         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
 608         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 609         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
 610         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 611         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
 612         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 613         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
 614         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 615         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
 616         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 617         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
 618         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 619         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
 620         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 621         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
 622         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 623         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
 624         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 625         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
 626         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 627         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
 628         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 629         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
 630         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 631         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
 632         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 633         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
 634         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 635         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17),
 636         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 637         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
 638         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 639         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17),
 640         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 641         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
 642         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 643         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 644         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 645         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
 646         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 647         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 648         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 649         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
 650         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 651         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
 652         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 653         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
 654         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 655         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
 656         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 657         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
 658         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 659         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
 660         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 661         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
 662         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 663         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
 664         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 665         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
 666         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 667         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 668         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 669         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
 670         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 671         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 672         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 673         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
 674         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 675         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 676         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 677         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
 678         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 679         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 680         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 681         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
 682         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 683         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
 684         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 685         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
 686         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 687         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
 688         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 689         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
 690         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 691         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
 692         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 693         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
 694         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 695         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
 696         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 697         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
 698         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 699         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 700         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 701         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
 702         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 703         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 704         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 705         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
 706         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 707         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 708         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 709         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
 710         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 711         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 712         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 713         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
 714         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 715         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 716         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 717         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
 718         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 719         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 720         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 721         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
 722         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 723         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 724         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 725         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
 726         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 727         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 728         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 729         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
 730         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 731         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 732         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 733         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
 734         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 735         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 736         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 737         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90),
 738         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 739         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
 740         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 741         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90),
 742         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 743         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
 744         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 745         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94),
 746         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 747         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
 748         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 749         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94),
 750         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 751         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
 752         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 753         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0),
 754         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 755         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
 756         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 757         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0),
 758         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 759         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
 760         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 761         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4),
 762         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 763         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
 764         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 765         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4),
 766         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 767         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
 768         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 769         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98),
 770         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 771         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
 772         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 773         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98),
 774         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 775         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
 776         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 777         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c),
 778         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 779         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
 780         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 781         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c),
 782         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 783         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
 784         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 785         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8),
 786         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 787         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 788         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 789         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8),
 790         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 791         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 792         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 793         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac),
 794         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 795         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 796         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 797         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac),
 798         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 799         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 800         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 801         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8),
 802         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 803         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
 804         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 805         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8),
 806         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 807         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
 808         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 809         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc),
 810         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 811         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
 812         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 813         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc),
 814         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 815         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
 816         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 817         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0),
 818         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 819         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 820         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 821         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0),
 822         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 823         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 824         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 825         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4),
 826         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 827         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 828         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 829         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4),
 830         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 831         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 832         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 833         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0),
 834         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 835         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
 836         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 837         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0),
 838         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 839         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
 840         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 841         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4),
 842         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 843         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 844         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 845         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4),
 846         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 847         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 848         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 849         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0),
 850         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 851         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
 852         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 853         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0),
 854         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 855         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
 856         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 857         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4),
 858         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 859         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
 860         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 861         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4),
 862         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 863         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
 864         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 865         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8),
 866         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 867         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
 868         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 869         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8),
 870         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 871         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
 872         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 873         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc),
 874         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 875         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
 876         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 877         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc),
 878         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 879         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
 880         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 881         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8),
 882         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 883         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 884         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 885         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8),
 886         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 887         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 888         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 889         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec),
 890         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 891         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 892         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 893         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec),
 894         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 895         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 896         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 897         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0),
 898         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 899         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
 900         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 901         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0),
 902         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 903         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
 904         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 905         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4),
 906         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 907         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
 908         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 909         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4),
 910         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 911         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
 912         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 913         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8),
 914         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 915         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 916         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 917         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8),
 918         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 919         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 920         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 921         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xfc),
 922         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 923         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 924         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 925         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xfc),
 926         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 927         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 928         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 929         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100),
 930         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 931         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 932         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 933         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100),
 934         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 935         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 936         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 937         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104),
 938         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 939         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
 940         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 941         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104),
 942         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 943         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
 944         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 945         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0),
 946         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 947         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
 948         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 949         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0),
 950         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 951         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
 952         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 953         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118),
 954         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 955         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
 956         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 957         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118),
 958         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 959         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
 960         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 961         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c),
 962         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 963         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
 964         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 965         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c),
 966         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 967         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
 968         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 969         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120),
 970         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 971         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
 972         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 973         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120),
 974         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 975         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
 976         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 977         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124),
 978         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 979         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
 980         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 981         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124),
 982         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 983         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
 984         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 985         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc),
 986         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 987         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
 988         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 989         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc),
 990         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 991         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
 992         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 993         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110),
 994         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 995         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
 996         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 997         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110),
 998         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 999         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1000         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1001         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114),
1002         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1003         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1004         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1005         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114),
1006         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1007         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1008         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1009         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108),
1010         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1011         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1012         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1013         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108),
1014         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1015         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1016         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1017         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c),
1018         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1019         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1020         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1021         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c),
1022         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1023         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1024         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1025         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8),
1026         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1027         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17),
1028         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1029         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8),
1030         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1031         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17),
1032         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1033         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128),
1034         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1035         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
1036         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1037         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128),
1038         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1039         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
1040         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1041         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c),
1042         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1043         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1044         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1045         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c),
1046         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1047         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1048         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1049         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138),
1050         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1051         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1052         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1053         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138),
1054         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1055         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1056         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1057         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c),
1058         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1059         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1060         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1061         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c),
1062         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1063         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1064         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1065         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130),
1066         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1067         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1068         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1069         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130),
1070         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1071         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1072         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1073         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134),
1074         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1075         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1076         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1077         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134),
1078         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1079         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1080         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1081         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140),
1082         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1083         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1084         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1085         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140),
1086         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1087         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1088         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1089         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144),
1090         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1091         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
1092         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1093         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144),
1094         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1095         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
1096         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1097         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150),
1098         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1099         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1100         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1101         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150),
1102         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1103         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1104         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1105         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154),
1106         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1107         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
1108         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1109         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154),
1110         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1111         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
1112         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1113         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148),
1114         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1115         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1116         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1117         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148),
1118         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1119         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1120         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1121         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c),
1122         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1123         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
1124         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1125         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c),
1126         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1127         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
1128         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1129         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158),
1130         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1131         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
1132         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1133         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158),
1134         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1135         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
1136         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1137         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c),
1138         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1139         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1140         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1141         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c),
1142         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1143         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1144         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1145         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168),
1146         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1147         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1),
1148         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1149         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168),
1150         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1151         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1),
1152         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1153         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c),
1154         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1155         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
1156         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1157         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c),
1158         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1159         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
1160         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1161         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160),
1162         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1163         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
1164         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1165         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160),
1166         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1167         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
1168         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1169         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164),
1170         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1171         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1172         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1173         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164),
1174         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1175         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1176         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1177         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170),
1178         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1179         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
1180         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1181         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170),
1182         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1183         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
1184         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1185         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174),
1186         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1187         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
1188         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1189         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174),
1190         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1191         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
1192         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1193         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180),
1194         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1195         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
1196         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1197         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180),
1198         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1199         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
1200         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1201         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184),
1202         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1203         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1204         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1205         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184),
1206         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1207         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1208         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1209         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178),
1210         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1211         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
1212         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1213         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178),
1214         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1215         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
1216         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1217         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c),
1218         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1219         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
1220         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1221         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c),
1222         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1223         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
1224         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1225         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188),
1226         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1227         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1228         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1229         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188),
1230         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1231         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1232         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1233         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c),
1234         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1235         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
1236         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1237         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c),
1238         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1239         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
1240         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1241         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198),
1242         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1243         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
1244         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1245         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198),
1246         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1247         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
1248         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1249         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c),
1250         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1251         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
1252         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1253         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c),
1254         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1255         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
1256         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1257         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190),
1258         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1259         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1260         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1261         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190),
1262         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1263         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1264         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1265         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194),
1266         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1267         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
1268         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1269         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194),
1270         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1271         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
1272         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1273         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
1274         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1275         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
1276         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1277         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
1278         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1279         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1280         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1281         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
1282         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1283         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
1284         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1285         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
1286         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1287         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
1288         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1289         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
1290         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1291         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1f),
1292         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1293         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
1294         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1295         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1f),
1296         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1297         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
1298         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1299         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
1300         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1301         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_SAMPLE_SKEW, 0x000000FF, 0x19),
1302         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1303         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_MUXSEL_SKEW, 0x000000FF, 0x20),
1304         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1305         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0x5),
1306         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1307         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0xa),
1308         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1309         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x14),
1310         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1311         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x19),
1312         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1313         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_DESER_START_SKEW, 0x000000FF, 0x33),
1314         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xFFFFFFFF, 0xe0000000)
1315 };
1316
1317 static const struct soc15_reg_golden golden_settings_gc_10_1_1[] =
1318 {
1319         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0xffffffff, 0x003c0014),
1320         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_GS_NGG_CLK_CTRL, 0xffff8fff, 0xffff8100),
1321         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_IA_CLK_CTRL, 0xffff0fff, 0xffff0100),
1322         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xcd000000, 0x0d000100),
1323         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQ_CLK_CTRL, 0xf8ff0fff, 0x60000100),
1324         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQG_CLK_CTRL, 0x40000ff0, 0x40000100),
1325         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xffff8fff, 0xffff8100),
1326         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_WD_CLK_CTRL, 0xffff8fff, 0xffff8100),
1327         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
1328         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_VC5_ENABLE, 0x00000002, 0x00000000),
1329         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0x800007ff, 0x000005ff),
1330         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG, 0xffffffff, 0x20000000),
1331         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xffffffff, 0x00000420),
1332         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0x00000200, 0x00000200),
1333         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x04900000),
1334         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DFSM_TILES_IN_FLIGHT, 0x0000ffff, 0x0000003f),
1335         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_LAST_OF_BURST_CONFIG, 0xffffffff, 0x03860204),
1336         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff0ffff, 0x00000500),
1337         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PRIV_CONTROL, 0x000007ff, 0x000001fe),
1338         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
1339         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffe7),
1340         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffe7),
1341         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CGTT_SCLK_CTRL, 0xffff0fff, 0x10000100),
1342         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL2, 0xffffffff, 0x1402002f),
1343         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xffffbfff, 0x00000188),
1344         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
1345         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x08000009),
1346         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0x00400000, 0x04440000),
1347         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0x00000800, 0x00000820),
1348         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000),
1349         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0xffffffff, 0xffff3101),
1350         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0x001f0000, 0x00070105),
1351         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ALU_CLK_CTRL, 0xffffffff, 0xffffffff),
1352         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x00000133, 0x00000130),
1353         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0xffffffff, 0xffffffff),
1354         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
1355         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CNTL, 0x60000010, 0x479c0010),
1356         SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0x00c00000, 0x00c00000),
1357 };
1358
1359 static const struct soc15_reg_golden golden_settings_gc_10_1_2[] =
1360 {
1361         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0x003e001f, 0x003c0014),
1362         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_GS_NGG_CLK_CTRL, 0xffff8fff, 0xffff8100),
1363         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_IA_CLK_CTRL, 0xffff0fff, 0xffff0100),
1364         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xff7f0fff, 0x0d000100),
1365         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQ_CLK_CTRL, 0xffffcfff, 0x60000100),
1366         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQG_CLK_CTRL, 0xffff0fff, 0x40000100),
1367         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xffff8fff, 0xffff8100),
1368         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_WD_CLK_CTRL, 0xffff8fff, 0xffff8100),
1369         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
1370         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_VC5_ENABLE, 0x00000003, 0x00000000),
1371         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0x800007ff, 0x000005ff),
1372         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG, 0xffffffff, 0x20000000),
1373         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xffffffff, 0x00000420),
1374         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000200),
1375         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x04800000),
1376         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DFSM_TILES_IN_FLIGHT, 0x0000ffff, 0x0000003f),
1377         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_LAST_OF_BURST_CONFIG, 0xffffffff, 0x03860204),
1378         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff0ffff, 0x00000500),
1379         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PRIV_CONTROL, 0x00007fff, 0x000001fe),
1380         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
1381         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x10321032),
1382         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x02310231),
1383         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
1384         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
1385         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CGTT_SCLK_CTRL, 0xffff0fff, 0x10000100),
1386         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL2, 0xffffffff, 0x1402002f),
1387         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xffffbfff, 0x00000188),
1388         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_0, 0xffffffff, 0x842a4c02),
1389         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
1390         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x08000009),
1391         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0xffffffff, 0x04440000),
1392         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0x00000820, 0x00000820),
1393         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000),
1394         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0xffffffff, 0xffff3101),
1395         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ALU_CLK_CTRL, 0xffffffff, 0xffffffff),
1396         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x00000133, 0x00000130),
1397         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0xffffffff, 0xffffffff),
1398         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
1399         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CNTL, 0xffdf80ff, 0x479c0010),
1400         SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffffffff, 0x00800000)
1401 };
1402
1403 static void gfx_v10_rlcg_wreg(struct amdgpu_device *adev, u32 offset, u32 v)
1404 {
1405         static void *scratch_reg0;
1406         static void *scratch_reg1;
1407         static void *scratch_reg2;
1408         static void *scratch_reg3;
1409         static void *spare_int;
1410         static uint32_t grbm_cntl;
1411         static uint32_t grbm_idx;
1412         uint32_t i = 0;
1413         uint32_t retries = 50000;
1414
1415         scratch_reg0 = adev->rmmio + (adev->reg_offset[GC_HWIP][0][mmSCRATCH_REG0_BASE_IDX] + mmSCRATCH_REG0)*4;
1416         scratch_reg1 = adev->rmmio + (adev->reg_offset[GC_HWIP][0][mmSCRATCH_REG1_BASE_IDX] + mmSCRATCH_REG1)*4;
1417         scratch_reg2 = adev->rmmio + (adev->reg_offset[GC_HWIP][0][mmSCRATCH_REG1_BASE_IDX] + mmSCRATCH_REG2)*4;
1418         scratch_reg3 = adev->rmmio + (adev->reg_offset[GC_HWIP][0][mmSCRATCH_REG1_BASE_IDX] + mmSCRATCH_REG3)*4;
1419         spare_int = adev->rmmio + (adev->reg_offset[GC_HWIP][0][mmRLC_SPARE_INT_BASE_IDX] + mmRLC_SPARE_INT)*4;
1420
1421         grbm_cntl = adev->reg_offset[GC_HWIP][0][mmGRBM_GFX_CNTL_BASE_IDX] + mmGRBM_GFX_CNTL;
1422         grbm_idx = adev->reg_offset[GC_HWIP][0][mmGRBM_GFX_INDEX_BASE_IDX] + mmGRBM_GFX_INDEX;
1423
1424         if (amdgpu_sriov_runtime(adev)) {
1425                 pr_err("shouldn't call rlcg write register during runtime\n");
1426                 return;
1427         }
1428
1429         writel(v, scratch_reg0);
1430         writel(offset | 0x80000000, scratch_reg1);
1431         writel(1, spare_int);
1432         for (i = 0; i < retries; i++) {
1433                 u32 tmp;
1434
1435                 tmp = readl(scratch_reg1);
1436                 if (!(tmp & 0x80000000))
1437                         break;
1438
1439                 udelay(10);
1440         }
1441
1442         if (i >= retries)
1443                 pr_err("timeout: rlcg program reg:0x%05x failed !\n", offset);
1444 }
1445
1446 static const struct soc15_reg_golden golden_settings_gc_10_1_nv14[] =
1447 {
1448         /* Pending on emulation bring up */
1449 };
1450
1451 static const struct soc15_reg_golden golden_settings_gc_rlc_spm_10_1_nv14[] =
1452 {
1453         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xE0000000L, 0x0),
1454         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1455         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
1456         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1457         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1458         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1459         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
1460         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1461         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
1462         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1463         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
1464         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1465         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
1466         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1467         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
1468         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1469         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1470         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1471         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
1472         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1473         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1474         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1475         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
1476         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1477         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1478         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1479         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
1480         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1481         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1482         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1483         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
1484         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1485         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1486         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1487         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
1488         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1489         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1490         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1491         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
1492         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1493         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1494         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1495         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
1496         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1497         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1498         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1499         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
1500         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1501         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1502         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1503         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
1504         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1505         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20),
1506         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1507         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
1508         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1509         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
1510         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1511         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
1512         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1513         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1514         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1515         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
1516         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1517         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1518         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1519         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
1520         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1521         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1522         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1523         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
1524         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1525         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1526         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1527         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
1528         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1529         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1530         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1531         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
1532         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1533         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
1534         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1535         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
1536         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1537         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1538         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1539         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
1540         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1541         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1542         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1543         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
1544         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1545         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1546         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1547         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
1548         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1549         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1550         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1551         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
1552         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1553         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
1554         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1555         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
1556         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1557         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
1558         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1559         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
1560         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1561         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
1562         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1563         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
1564         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1565         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
1566         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1567         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
1568         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1569         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
1570         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1571         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
1572         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1573         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
1574         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1575         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
1576         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1577         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
1578         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1579         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
1580         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1581         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
1582         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1583         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
1584         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1585         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
1586         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1587         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
1588         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1589         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
1590         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1591         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c),
1592         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1593         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1594         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1595         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
1596         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1597         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1598         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1599         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
1600         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1601         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1602         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1603         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
1604         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1605         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1606         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1607         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
1608         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1609         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1610         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1611         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
1612         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1613         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
1614         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1615         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
1616         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1617         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1618         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1619         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
1620         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1621         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1622         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1623         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
1624         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1625         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
1626         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1627         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
1628         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1629         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
1630         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1631         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
1632         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1633         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
1634         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1635         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
1636         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1637         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e),
1638         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1639         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
1640         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1641         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e),
1642         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1643         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
1644         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1645         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e),
1646         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1647         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
1648         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1649         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e),
1650         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1651         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
1652         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1653         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20),
1654         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1655         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
1656         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1657         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
1658         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1659         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
1660         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1661         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
1662         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1663         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
1664         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1665         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e),
1666         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1667         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
1668         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1669         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e),
1670         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1671         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
1672         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1673         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
1674         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1675         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
1676         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1677         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1678         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1679         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
1680         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1681         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1682         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1683         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
1684         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1685         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1686         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1687         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
1688         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1689         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1690         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1691         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
1692         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1693         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1694         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1695         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
1696         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1697         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1698         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1699         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
1700         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1701         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1702         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1703         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
1704         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1705         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1706         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1707         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
1708         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1709         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1710         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1711         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
1712         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1713         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1714         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1715         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
1716         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1717         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1718         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1719         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
1720         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1721         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1722         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1723         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90),
1724         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1725         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1726         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1727         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94),
1728         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1729         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
1730         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1731         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0),
1732         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1733         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1734         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1735         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4),
1736         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1737         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1738         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1739         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98),
1740         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1741         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1742         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1743         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c),
1744         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1745         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
1746         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1747         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8),
1748         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1749         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
1750         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1751         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac),
1752         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1753         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1754         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1755         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8),
1756         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1757         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1758         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1759         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc),
1760         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1761         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1762         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1763         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0),
1764         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1765         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
1766         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1767         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4),
1768         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1769         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1770         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1771         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0),
1772         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1773         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1774         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1775         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4),
1776         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1777         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1778         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1779         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0),
1780         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1781         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1782         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1783         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4),
1784         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1785         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1786         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1787         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8),
1788         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1789         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1790         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1791         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc),
1792         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1793         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1794         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1795         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8),
1796         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1797         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1798         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1799         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc),
1800         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1801         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1802         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1803         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8),
1804         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1805         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1806         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1807         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec),
1808         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1809         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1810         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1811         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0),
1812         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1813         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1814         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1815         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe4),
1816         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1817         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1818         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1819         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100),
1820         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1821         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1822         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1823         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104),
1824         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1825         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1826         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1827         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108),
1828         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1829         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1830         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1831         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c),
1832         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1833         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1834         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1835         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110),
1836         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1837         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1838         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1839         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114),
1840         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1841         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1842         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1843         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118),
1844         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1845         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1846         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1847         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c),
1848         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1849         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1850         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1851         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8),
1852         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1853         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17),
1854         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1855         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130),
1856         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1857         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1858         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1859         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134),
1860         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1861         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1862         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1863         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138),
1864         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1865         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1866         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1867         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c),
1868         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1869         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1870         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1871         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4),
1872         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1873         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20),
1874         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1875         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128),
1876         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1877         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1878         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1879         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c),
1880         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1881         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1882         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1883         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120),
1884         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1885         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1886         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1887         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124),
1888         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1889         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1890         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1891         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0),
1892         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1893         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
1894         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1895         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140),
1896         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1897         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1898         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1899         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144),
1900         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1901         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1902         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1903         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150),
1904         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1905         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1906         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1907         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154),
1908         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1909         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1910         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1911         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148),
1912         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1913         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1914         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1915         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c),
1916         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1917         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1918         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1919         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158),
1920         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1921         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1922         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1923         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c),
1924         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1925         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
1926         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1927         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168),
1928         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1929         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1930         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1931         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c),
1932         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1933         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1934         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1935         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160),
1936         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1937         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1938         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1939         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164),
1940         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1941         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
1942         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1943         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170),
1944         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1945         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
1946         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1947         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174),
1948         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1949         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
1950         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1951         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180),
1952         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1953         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1954         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1955         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184),
1956         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1957         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
1958         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1959         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178),
1960         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1961         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
1962         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1963         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c),
1964         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1965         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
1966         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1967         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188),
1968         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1969         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1970         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1971         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c),
1972         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1973         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1974         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1975         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198),
1976         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1977         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1978         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1979         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c),
1980         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1981         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1982         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1983         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190),
1984         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1985         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1986         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1987         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194),
1988         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1989         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1990         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1991         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1a0),
1992         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1993         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1994         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1995         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1a4),
1996         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1997         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1998         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1999         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1b0),
2000         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2001         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2002         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2003         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1b4),
2004         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2005         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2006         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2007         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1a8),
2008         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2009         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2010         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2011         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1ac),
2012         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2013         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
2014         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2015         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1b8),
2016         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2017         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
2018         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2019         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1bc),
2020         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2021         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2022         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2023         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c8),
2024         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2025         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
2026         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2027         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1cc),
2028         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2029         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
2030         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2031         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c0),
2032         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2033         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
2034         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2035         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c4),
2036         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2037         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2038         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2039         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
2040         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2041         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2042         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2043         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
2044         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2045         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2046         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2047         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
2048         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2049         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20),
2050         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2051         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
2052         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2053         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20),
2054         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2055         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
2056         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2057         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
2058         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2059         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_SAMPLE_SKEW, 0x000000FF, 0x26),
2060         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2061         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_MUXSEL_SKEW, 0x000000FF, 0x28),
2062         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2063         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0xf),
2064         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2065         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0x15),
2066         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2067         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x1f),
2068         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2069         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x25),
2070         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2071         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_DESER_START_SKEW, 0x000000FF, 0x3b),
2072         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xFFFFFFFF, 0xe0000000)
2073 };
2074
2075 static const struct soc15_reg_golden golden_settings_gc_10_1_2_nv12[] =
2076 {
2077         /* Pending on emulation bring up */
2078 };
2079
2080 static const struct soc15_reg_golden golden_settings_gc_rlc_spm_10_1_2_nv12[] =
2081 {
2082         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xe0000000L, 0x0),
2083         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2084         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
2085         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2086         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
2087         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2088         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
2089         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2090         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
2091         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2092         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
2093         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2094         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
2095         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2096         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
2097         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2098         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
2099         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2100         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8),
2101         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2102         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2103         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2104         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc),
2105         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2106         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2107         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2108         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0),
2109         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2110         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2111         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2112         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4),
2113         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2114         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2115         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2116         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
2117         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2118         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2119         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2120         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
2121         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2122         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2123         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2124         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
2125         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2126         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2127         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2128         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
2129         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2130         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2131         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2132         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
2133         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2134         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2135         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2136         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
2137         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2138         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2139         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2140         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
2141         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2142         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2143         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2144         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
2145         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2146         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
2147         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2148         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
2149         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2150         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
2151         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2152         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0),
2153         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2154         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
2155         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2156         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4),
2157         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2158         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
2159         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2160         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8),
2161         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2162         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2163         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2164         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc),
2165         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2166         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2167         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2168         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0),
2169         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2170         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2171         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2172         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4),
2173         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2174         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2175         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2176         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90),
2177         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2178         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
2179         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2180         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94),
2181         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2182         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1),
2183         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2184         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98),
2185         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2186         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
2187         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2188         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c),
2189         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2190         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2191         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2192         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0),
2193         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2194         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1),
2195         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2196         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4),
2197         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2198         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2199         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2200         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8),
2201         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2202         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2203         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2204         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac),
2205         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2206         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2207         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2208         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
2209         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2210         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
2211         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2212         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
2213         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2214         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2215         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2216         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
2217         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2218         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
2219         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2220         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
2221         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2222         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2223         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2224         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
2225         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2226         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2227         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2228         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
2229         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2230         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2231         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2232         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
2233         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2234         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
2235         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2236         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
2237         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2238         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2239         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2240         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
2241         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2242         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2243         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2244         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
2245         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2246         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
2247         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2248         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
2249         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2250         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2251         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2252         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
2253         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2254         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
2255         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2256         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
2257         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2258         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
2259         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2260         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
2261         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2262         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2263         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2264         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
2265         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2266         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2267         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2268         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
2269         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2270         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2271         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2272         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
2273         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2274         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
2275         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2276         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
2277         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2278         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2279         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2280         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
2281         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2282         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2283         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2284         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
2285         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2286         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2287         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2288         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
2289         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2290         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2291         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2292         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
2293         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2294         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2295         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2296         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
2297         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2298         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
2299         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2300         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c),
2301         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2302         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
2303         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2304         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
2305         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2306         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2307         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2308         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
2309         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2310         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
2311         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2312         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
2313         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2314         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
2315         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2316         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
2317         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2318         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2319         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2320         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
2321         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2322         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2323         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2324         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
2325         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2326         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2327         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2328         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
2329         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2330         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2331         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2332         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
2333         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2334         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2335         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2336         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
2337         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2338         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2339         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2340         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
2341         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2342         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
2343         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2344         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
2345         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2346         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
2347         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2348         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
2349         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2350         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2351         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2352         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
2353         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2354         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2355         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2356         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
2357         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2358         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
2359         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2360         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
2361         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2362         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
2363         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2364         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
2365         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2366         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2367         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2368         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
2369         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2370         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2371         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2372         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
2373         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2374         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
2375         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2376         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
2377         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2378         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
2379         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2380         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
2381         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2382         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2383         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2384         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
2385         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2386         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2387         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2388         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
2389         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2390         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2391         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2392         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
2393         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2394         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2395         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2396         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
2397         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2398         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2399         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2400         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
2401         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2402         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2403         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2404         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
2405         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2406         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2407         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2408         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
2409         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2410         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2411         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2412         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
2413         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2414         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2415         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2416         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
2417         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2418         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2419         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2420         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
2421         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2422         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2423         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2424         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
2425         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2426         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2427         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2428         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
2429         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2430         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2431         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2432         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
2433         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2434         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2435         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2436         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
2437         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2438         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2439         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2440         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
2441         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2442         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2443         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2444         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
2445         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2446         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2447         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2448         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
2449         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2450         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2451         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2452         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
2453         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2454         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
2455         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2456         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
2457         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2458         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
2459         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2460         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
2461         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2462         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2463         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2464         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
2465         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2466         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2467         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2468         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
2469         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2470         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
2471         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2472         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
2473         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2474         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
2475         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2476         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
2477         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2478         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
2479         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2480         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
2481         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2482         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
2483         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2484         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
2485         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2486         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2487         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2488         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
2489         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2490         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2491         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2492         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
2493         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2494         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2495         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2496         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
2497         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2498         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2499         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2500         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
2501         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2502         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
2503         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2504         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
2505         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2506         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
2507         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2508         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
2509         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2510         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2511         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2512         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
2513         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2514         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2515         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2516         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
2517         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2518         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2519         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2520         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
2521         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2522         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2523         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2524         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
2525         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2526         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2527         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2528         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
2529         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2530         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2531         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2532         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
2533         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2534         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2535         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2536         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
2537         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2538         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2539         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2540         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
2541         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2542         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2543         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2544         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
2545         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2546         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2547         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2548         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
2549         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2550         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2551         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2552         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
2553         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2554         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2555         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2556         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90),
2557         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2558         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
2559         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2560         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90),
2561         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2562         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
2563         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2564         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94),
2565         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2566         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2567         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2568         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94),
2569         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2570         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2571         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2572         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0),
2573         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2574         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2575         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2576         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0),
2577         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2578         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2579         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2580         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4),
2581         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2582         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2583         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2584         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4),
2585         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2586         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2587         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2588         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98),
2589         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2590         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
2591         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2592         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98),
2593         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2594         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
2595         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2596         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c),
2597         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2598         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2599         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2600         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c),
2601         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2602         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2603         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2604         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8),
2605         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2606         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2607         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2608         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8),
2609         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2610         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2611         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2612         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac),
2613         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2614         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2615         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2616         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac),
2617         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2618         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2619         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2620         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8),
2621         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2622         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2623         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2624         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8),
2625         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2626         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2627         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2628         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc),
2629         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2630         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2631         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2632         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc),
2633         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2634         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2635         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2636         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0),
2637         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2638         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2639         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2640         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0),
2641         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2642         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2643         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2644         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4),
2645         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2646         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2647         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2648         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4),
2649         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2650         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2651         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2652         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0),
2653         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2654         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2655         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2656         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0),
2657         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2658         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2659         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2660         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4),
2661         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2662         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2663         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2664         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4),
2665         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2666         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2667         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2668         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0),
2669         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2670         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2671         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2672         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0),
2673         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2674         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2675         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2676         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4),
2677         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2678         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2679         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2680         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4),
2681         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2682         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2683         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2684         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8),
2685         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2686         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2687         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2688         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8),
2689         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2690         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2691         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2692         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc),
2693         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2694         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2695         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2696         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc),
2697         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2698         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2699         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2700         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8),
2701         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2702         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2703         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2704         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8),
2705         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2706         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2707         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2708         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec),
2709         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2710         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
2711         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2712         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec),
2713         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2714         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
2715         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2716         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0),
2717         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2718         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2719         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2720         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0),
2721         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2722         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2723         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2724         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4),
2725         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2726         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2727         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2728         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4),
2729         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2730         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2731         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2732         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8),
2733         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2734         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2735         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2736         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8),
2737         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2738         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2739         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2740         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xfc),
2741         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2742         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17),
2743         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2744         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xfc),
2745         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2746         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17),
2747         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2748         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100),
2749         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2750         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
2751         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2752         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100),
2753         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2754         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
2755         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2756         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104),
2757         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2758         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2759         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2760         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104),
2761         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2762         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2763         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2764         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0),
2765         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2766         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2767         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2768         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0),
2769         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2770         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2771         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2772         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118),
2773         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2774         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2775         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2776         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118),
2777         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2778         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2779         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2780         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c),
2781         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2782         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2783         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2784         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c),
2785         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2786         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2787         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2788         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120),
2789         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2790         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2791         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2792         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120),
2793         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2794         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2795         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2796         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124),
2797         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2798         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2799         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2800         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124),
2801         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2802         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2803         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2804         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc),
2805         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2806         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2807         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2808         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc),
2809         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2810         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2811         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2812         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110),
2813         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2814         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2815         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2816         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110),
2817         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2818         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2819         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2820         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114),
2821         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2822         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2823         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2824         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114),
2825         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2826         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2827         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2828         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108),
2829         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2830         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2831         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2832         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108),
2833         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2834         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2835         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2836         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c),
2837         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2838         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2839         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2840         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c),
2841         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2842         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2843         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2844         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8),
2845         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2846         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
2847         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2848         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8),
2849         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2850         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
2851         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2852         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128),
2853         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2854         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2855         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2856         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128),
2857         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2858         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2859         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2860         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c),
2861         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2862         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2863         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2864         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c),
2865         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2866         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2867         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2868         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138),
2869         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2870         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2871         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2872         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138),
2873         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2874         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2875         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2876         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c),
2877         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2878         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2879         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2880         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c),
2881         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2882         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2883         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2884         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130),
2885         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2886         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2887         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2888         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130),
2889         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2890         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2891         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2892         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134),
2893         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2894         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
2895         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2896         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134),
2897         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2898         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
2899         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2900         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140),
2901         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2902         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2903         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2904         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140),
2905         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2906         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2907         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2908         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144),
2909         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2910         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2911         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2912         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144),
2913         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2914         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2915         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2916         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150),
2917         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2918         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2919         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2920         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150),
2921         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2922         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2923         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2924         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154),
2925         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2926         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2927         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2928         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154),
2929         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2930         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2931         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2932         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148),
2933         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2934         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2935         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2936         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148),
2937         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2938         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2939         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2940         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c),
2941         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2942         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2943         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2944         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c),
2945         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2946         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2947         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2948         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158),
2949         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2950         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
2951         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2952         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158),
2953         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2954         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
2955         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2956         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c),
2957         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2958         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
2959         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2960         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c),
2961         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2962         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
2963         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2964         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168),
2965         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2966         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
2967         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2968         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168),
2969         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2970         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
2971         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2972         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c),
2973         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2974         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
2975         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2976         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c),
2977         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2978         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
2979         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2980         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160),
2981         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2982         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
2983         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2984         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160),
2985         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2986         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
2987         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2988         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164),
2989         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2990         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
2991         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2992         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164),
2993         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2994         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
2995         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2996         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170),
2997         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2998         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2999         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3000         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170),
3001         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3002         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
3003         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3004         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174),
3005         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3006         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3007         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3008         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174),
3009         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3010         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3011         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3012         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180),
3013         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3014         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
3015         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3016         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180),
3017         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3018         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
3019         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3020         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184),
3021         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3022         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3023         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3024         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184),
3025         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3026         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3027         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3028         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178),
3029         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3030         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
3031         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3032         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178),
3033         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3034         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
3035         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3036         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c),
3037         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3038         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3039         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3040         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c),
3041         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3042         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3043         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3044         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188),
3045         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3046         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3047         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3048         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188),
3049         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3050         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3051         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3052         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c),
3053         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3054         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
3055         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3056         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c),
3057         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3058         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
3059         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3060         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198),
3061         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3062         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
3063         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3064         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198),
3065         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3066         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
3067         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3068         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c),
3069         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3070         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
3071         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3072         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c),
3073         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3074         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
3075         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3076         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190),
3077         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3078         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3079         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3080         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190),
3081         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3082         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3083         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3084         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194),
3085         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3086         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
3087         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3088         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194),
3089         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3090         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
3091         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3092         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
3093         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3094         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
3095         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3096         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
3097         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3098         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
3099         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3100         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
3101         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3102         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
3103         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3104         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
3105         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3106         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
3107         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3108         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
3109         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3110         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1f),
3111         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3112         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
3113         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3114         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1f),
3115         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3116         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
3117         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3118         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
3119         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3120         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_SAMPLE_SKEW, 0x000000FF, 0x1f),
3121         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3122         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_MUXSEL_SKEW, 0x000000FF, 0x22),
3123         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3124         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0x1),
3125         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3126         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0x6),
3127         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3128         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x10),
3129         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3130         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x15),
3131         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3132         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_DESER_START_SKEW, 0x000000FF, 0x35),
3133         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xFFFFFFFF, 0xe0000000)
3134 };
3135
3136 static const struct soc15_reg_golden golden_settings_gc_10_3[] =
3137 {
3138         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0x78000000, 0x78000100),
3139         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_PS_CLK_CTRL, 0xff7f0fff, 0x78000100),
3140         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA0_CLK_CTRL, 0xff7f0fff, 0x30000100),
3141         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA1_CLK_CTRL, 0xff7f0fff, 0x7e000100),
3142         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c000),
3143         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000280),
3144         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000),
3145         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_EXCEPTION_CONTROL, 0x7fff0f1f, 0x00b80000),
3146         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Sienna_Cichlid, 0x1ff1ffff, 0x00000500),
3147         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PC_CNTL, 0x003fffff, 0x00280400),
3148         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
3149         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
3150         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008),
3151         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x10f80988),
3152         SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG,  0x00000020, 0x00000020),
3153         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007),
3154         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
3155         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0xffffffbf, 0x00000820),
3156         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0xffffffff, 0x00070104),
3157         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_CONFIG, 0xe07df47f, 0x00180070),
3158         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER0_SELECT, 0xf0f001ff, 0x00000000),
3159         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER1_SELECT, 0xf0f001ff, 0x00000000),
3160         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER10_SELECT, 0xf0f001ff, 0x00000000),
3161         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER11_SELECT, 0xf0f001ff, 0x00000000),
3162         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER12_SELECT, 0xf0f001ff, 0x00000000),
3163         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER13_SELECT, 0xf0f001ff, 0x00000000),
3164         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER14_SELECT, 0xf0f001ff, 0x00000000),
3165         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER15_SELECT, 0xf0f001ff, 0x00000000),
3166         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER2_SELECT, 0xf0f001ff, 0x00000000),
3167         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER3_SELECT, 0xf0f001ff, 0x00000000),
3168         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER4_SELECT, 0xf0f001ff, 0x00000000),
3169         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER5_SELECT, 0xf0f001ff, 0x00000000),
3170         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER6_SELECT, 0xf0f001ff, 0x00000000),
3171         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER7_SELECT, 0xf0f001ff, 0x00000000),
3172         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER8_SELECT, 0xf0f001ff, 0x00000000),
3173         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER9_SELECT, 0xf0f001ff, 0x00000000),
3174         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
3175         SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffbfffff, 0x00a00000)
3176 };
3177
3178 static const struct soc15_reg_golden golden_settings_gc_10_3_sienna_cichlid[] =
3179 {
3180         /* Pending on emulation bring up */
3181 };
3182
3183 static const struct soc15_reg_golden golden_settings_gc_10_3_2[] =
3184 {
3185         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_PS_CLK_CTRL, 0xff7f0fff, 0x78000100),
3186         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA0_CLK_CTRL, 0xff7f0fff, 0x30000100),
3187         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA1_CLK_CTRL, 0xff7f0fff, 0x7e000100),
3188         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c000),
3189         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000280),
3190         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000),
3191         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_EXCEPTION_CONTROL, 0x7fff0f1f, 0x00b80000),
3192         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Sienna_Cichlid, 0x1ff1ffff, 0x00000500),
3193         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PC_CNTL, 0x003fffff, 0x00280400),
3194         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
3195         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
3196         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008),
3197         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x00f80988),
3198         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007),
3199         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
3200         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0xffffffbf, 0x00000820),
3201         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0xffffffff, 0x00070104),
3202         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_START_PHASE, 0x000000ff, 0x00000004),
3203         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_CONFIG, 0xe07df47f, 0x00180070),
3204         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER0_SELECT, 0xf0f001ff, 0x00000000),
3205         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER1_SELECT, 0xf0f001ff, 0x00000000),
3206         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER10_SELECT, 0xf0f001ff, 0x00000000),
3207         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER11_SELECT, 0xf0f001ff, 0x00000000),
3208         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER12_SELECT, 0xf0f001ff, 0x00000000),
3209         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER13_SELECT, 0xf0f001ff, 0x00000000),
3210         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER14_SELECT, 0xf0f001ff, 0x00000000),
3211         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER15_SELECT, 0xf0f001ff, 0x00000000),
3212         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER2_SELECT, 0xf0f001ff, 0x00000000),
3213         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER3_SELECT, 0xf0f001ff, 0x00000000),
3214         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER4_SELECT, 0xf0f001ff, 0x00000000),
3215         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER5_SELECT, 0xf0f001ff, 0x00000000),
3216         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER6_SELECT, 0xf0f001ff, 0x00000000),
3217         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER7_SELECT, 0xf0f001ff, 0x00000000),
3218         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER8_SELECT, 0xf0f001ff, 0x00000000),
3219         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER9_SELECT, 0xf0f001ff, 0x00000000),
3220         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
3221         SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffbfffff, 0x00a00000),
3222         SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_GS_MAX_WAVE_ID, 0x00000fff, 0x000003ff),
3223
3224         /* This is not in GDB yet. Don't remove it. It fixes a GPU hang on Navy Flounder. */
3225         SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG,  0x00000020, 0x00000020),
3226 };
3227
3228 static const struct soc15_reg_golden golden_settings_gc_10_3_vangogh[] =
3229 {
3230         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA0_CLK_CTRL, 0xff7f0fff, 0x30000100),
3231         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA1_CLK_CTRL, 0xff7f0fff, 0x7e000100),
3232         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0x000000ff, 0x000000e4),
3233         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000200),
3234         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000),
3235         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_EXCEPTION_CONTROL, 0x7fff0f1f, 0x00b80000),
3236         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0x0c1807ff, 0x00000142),
3237         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff1ffff, 0x00000500),
3238         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0x000000ff, 0x000000e4),
3239         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x32103210),
3240         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x32103210),
3241         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xfffffff3),
3242         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xfffffff3),
3243         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008),
3244         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x00f80988),
3245         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007),
3246         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
3247         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0xffffffbf, 0x00000020),
3248         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1_Vangogh, 0xffffffff, 0x00070103),
3249         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQG_CONFIG, 0x000017ff, 0x00001000),
3250         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
3251         SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffffffff, 0x00400000),
3252         SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_GS_MAX_WAVE_ID, 0x00000fff, 0x000000ff),
3253 };
3254
3255 static const struct soc15_reg_golden golden_settings_gc_10_3_4[] =
3256 {
3257         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA0_CLK_CTRL, 0x30000000, 0x30000100),
3258         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA1_CLK_CTRL, 0x7e000000, 0x7e000100),
3259         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c000),
3260         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0x00000280, 0x00000280),
3261         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0x07800000, 0x00800000),
3262         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x00001d00, 0x00000500),
3263         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PC_CNTL, 0x003c0000, 0x00280400),
3264         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
3265         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
3266         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0x40000000, 0x580f1008),
3267         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0x00040000, 0x00f80988),
3268         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0x01000000, 0x01200007),
3269         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
3270         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0x00000800, 0x00000820),
3271         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_CONFIG, 0x0000001f, 0x00180070),
3272         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER0_SELECT, 0xf0f001ff, 0x00000000),
3273         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER1_SELECT, 0xf0f001ff, 0x00000000),
3274         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER10_SELECT, 0xf0f001ff, 0x00000000),
3275         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER11_SELECT, 0xf0f001ff, 0x00000000),
3276         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER12_SELECT, 0xf0f001ff, 0x00000000),
3277         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER13_SELECT, 0xf0f001ff, 0x00000000),
3278         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER14_SELECT, 0xf0f001ff, 0x00000000),
3279         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER15_SELECT, 0xf0f001ff, 0x00000000),
3280         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER2_SELECT, 0xf0f001ff, 0x00000000),
3281         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER3_SELECT, 0xf0f001ff, 0x00000000),
3282         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER4_SELECT, 0xf0f001ff, 0x00000000),
3283         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER5_SELECT, 0xf0f001ff, 0x00000000),
3284         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER6_SELECT, 0xf0f001ff, 0x00000000),
3285         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER7_SELECT, 0xf0f001ff, 0x00000000),
3286         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER8_SELECT, 0xf0f001ff, 0x00000000),
3287         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER9_SELECT, 0xf0f001ff, 0x00000000),
3288         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0x01030000, 0x01030000),
3289         SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0x03a00000, 0x00a00000)
3290 };
3291
3292 #define DEFAULT_SH_MEM_CONFIG \
3293         ((SH_MEM_ADDRESS_MODE_64 << SH_MEM_CONFIG__ADDRESS_MODE__SHIFT) | \
3294          (SH_MEM_ALIGNMENT_MODE_UNALIGNED << SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT) | \
3295          (SH_MEM_RETRY_MODE_ALL << SH_MEM_CONFIG__RETRY_MODE__SHIFT) | \
3296          (3 << SH_MEM_CONFIG__INITIAL_INST_PREFETCH__SHIFT))
3297
3298
3299 static void gfx_v10_0_set_ring_funcs(struct amdgpu_device *adev);
3300 static void gfx_v10_0_set_irq_funcs(struct amdgpu_device *adev);
3301 static void gfx_v10_0_set_gds_init(struct amdgpu_device *adev);
3302 static void gfx_v10_0_set_rlc_funcs(struct amdgpu_device *adev);
3303 static int gfx_v10_0_get_cu_info(struct amdgpu_device *adev,
3304                                  struct amdgpu_cu_info *cu_info);
3305 static uint64_t gfx_v10_0_get_gpu_clock_counter(struct amdgpu_device *adev);
3306 static void gfx_v10_0_select_se_sh(struct amdgpu_device *adev, u32 se_num,
3307                                    u32 sh_num, u32 instance);
3308 static u32 gfx_v10_0_get_wgp_active_bitmap_per_sh(struct amdgpu_device *adev);
3309
3310 static int gfx_v10_0_rlc_backdoor_autoload_buffer_init(struct amdgpu_device *adev);
3311 static void gfx_v10_0_rlc_backdoor_autoload_buffer_fini(struct amdgpu_device *adev);
3312 static int gfx_v10_0_rlc_backdoor_autoload_enable(struct amdgpu_device *adev);
3313 static int gfx_v10_0_wait_for_rlc_autoload_complete(struct amdgpu_device *adev);
3314 static void gfx_v10_0_ring_emit_ce_meta(struct amdgpu_ring *ring, bool resume);
3315 static void gfx_v10_0_ring_emit_de_meta(struct amdgpu_ring *ring, bool resume);
3316 static void gfx_v10_0_ring_emit_frame_cntl(struct amdgpu_ring *ring, bool start, bool secure);
3317 static u32 gfx_v10_3_get_disabled_sa(struct amdgpu_device *adev);
3318 static void gfx_v10_3_program_pbb_mode(struct amdgpu_device *adev);
3319
3320 static void gfx10_kiq_set_resources(struct amdgpu_ring *kiq_ring, uint64_t queue_mask)
3321 {
3322         amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_RESOURCES, 6));
3323         amdgpu_ring_write(kiq_ring, PACKET3_SET_RESOURCES_VMID_MASK(0) |
3324                           PACKET3_SET_RESOURCES_QUEUE_TYPE(0)); /* vmid_mask:0 queue_type:0 (KIQ) */
3325         amdgpu_ring_write(kiq_ring, lower_32_bits(queue_mask)); /* queue mask lo */
3326         amdgpu_ring_write(kiq_ring, upper_32_bits(queue_mask)); /* queue mask hi */
3327         amdgpu_ring_write(kiq_ring, 0); /* gws mask lo */
3328         amdgpu_ring_write(kiq_ring, 0); /* gws mask hi */
3329         amdgpu_ring_write(kiq_ring, 0); /* oac mask */
3330         amdgpu_ring_write(kiq_ring, 0); /* gds heap base:0, gds heap size:0 */
3331 }
3332
3333 static void gfx10_kiq_map_queues(struct amdgpu_ring *kiq_ring,
3334                                  struct amdgpu_ring *ring)
3335 {
3336         struct amdgpu_device *adev = kiq_ring->adev;
3337         uint64_t mqd_addr = amdgpu_bo_gpu_offset(ring->mqd_obj);
3338         uint64_t wptr_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
3339         uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0;
3340
3341         amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5));
3342         /* Q_sel:0, vmid:0, vidmem: 1, engine:0, num_Q:1*/
3343         amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */
3344                           PACKET3_MAP_QUEUES_QUEUE_SEL(0) | /* Queue_Sel */
3345                           PACKET3_MAP_QUEUES_VMID(0) | /* VMID */
3346                           PACKET3_MAP_QUEUES_QUEUE(ring->queue) |
3347                           PACKET3_MAP_QUEUES_PIPE(ring->pipe) |
3348                           PACKET3_MAP_QUEUES_ME((ring->me == 1 ? 0 : 1)) |
3349                           PACKET3_MAP_QUEUES_QUEUE_TYPE(0) | /*queue_type: normal compute queue */
3350                           PACKET3_MAP_QUEUES_ALLOC_FORMAT(0) | /* alloc format: all_on_one_pipe */
3351                           PACKET3_MAP_QUEUES_ENGINE_SEL(eng_sel) |
3352                           PACKET3_MAP_QUEUES_NUM_QUEUES(1)); /* num_queues: must be 1 */
3353         amdgpu_ring_write(kiq_ring, PACKET3_MAP_QUEUES_DOORBELL_OFFSET(ring->doorbell_index));
3354         amdgpu_ring_write(kiq_ring, lower_32_bits(mqd_addr));
3355         amdgpu_ring_write(kiq_ring, upper_32_bits(mqd_addr));
3356         amdgpu_ring_write(kiq_ring, lower_32_bits(wptr_addr));
3357         amdgpu_ring_write(kiq_ring, upper_32_bits(wptr_addr));
3358 }
3359
3360 static void gfx10_kiq_unmap_queues(struct amdgpu_ring *kiq_ring,
3361                                    struct amdgpu_ring *ring,
3362                                    enum amdgpu_unmap_queues_action action,
3363                                    u64 gpu_addr, u64 seq)
3364 {
3365         uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0;
3366
3367         amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_UNMAP_QUEUES, 4));
3368         amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */
3369                           PACKET3_UNMAP_QUEUES_ACTION(action) |
3370                           PACKET3_UNMAP_QUEUES_QUEUE_SEL(0) |
3371                           PACKET3_UNMAP_QUEUES_ENGINE_SEL(eng_sel) |
3372                           PACKET3_UNMAP_QUEUES_NUM_QUEUES(1));
3373         amdgpu_ring_write(kiq_ring,
3374                   PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET0(ring->doorbell_index));
3375
3376         if (action == PREEMPT_QUEUES_NO_UNMAP) {
3377                 amdgpu_ring_write(kiq_ring, lower_32_bits(gpu_addr));
3378                 amdgpu_ring_write(kiq_ring, upper_32_bits(gpu_addr));
3379                 amdgpu_ring_write(kiq_ring, seq);
3380         } else {
3381                 amdgpu_ring_write(kiq_ring, 0);
3382                 amdgpu_ring_write(kiq_ring, 0);
3383                 amdgpu_ring_write(kiq_ring, 0);
3384         }
3385 }
3386
3387 static void gfx10_kiq_query_status(struct amdgpu_ring *kiq_ring,
3388                                    struct amdgpu_ring *ring,
3389                                    u64 addr,
3390                                    u64 seq)
3391 {
3392         uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0;
3393
3394         amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_QUERY_STATUS, 5));
3395         amdgpu_ring_write(kiq_ring,
3396                           PACKET3_QUERY_STATUS_CONTEXT_ID(0) |
3397                           PACKET3_QUERY_STATUS_INTERRUPT_SEL(0) |
3398                           PACKET3_QUERY_STATUS_COMMAND(2));
3399         amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */
3400                           PACKET3_QUERY_STATUS_DOORBELL_OFFSET(ring->doorbell_index) |
3401                           PACKET3_QUERY_STATUS_ENG_SEL(eng_sel));
3402         amdgpu_ring_write(kiq_ring, lower_32_bits(addr));
3403         amdgpu_ring_write(kiq_ring, upper_32_bits(addr));
3404         amdgpu_ring_write(kiq_ring, lower_32_bits(seq));
3405         amdgpu_ring_write(kiq_ring, upper_32_bits(seq));
3406 }
3407
3408 static void gfx10_kiq_invalidate_tlbs(struct amdgpu_ring *kiq_ring,
3409                                 uint16_t pasid, uint32_t flush_type,
3410                                 bool all_hub)
3411 {
3412         amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_INVALIDATE_TLBS, 0));
3413         amdgpu_ring_write(kiq_ring,
3414                         PACKET3_INVALIDATE_TLBS_DST_SEL(1) |
3415                         PACKET3_INVALIDATE_TLBS_ALL_HUB(all_hub) |
3416                         PACKET3_INVALIDATE_TLBS_PASID(pasid) |
3417                         PACKET3_INVALIDATE_TLBS_FLUSH_TYPE(flush_type));
3418 }
3419
3420 static const struct kiq_pm4_funcs gfx_v10_0_kiq_pm4_funcs = {
3421         .kiq_set_resources = gfx10_kiq_set_resources,
3422         .kiq_map_queues = gfx10_kiq_map_queues,
3423         .kiq_unmap_queues = gfx10_kiq_unmap_queues,
3424         .kiq_query_status = gfx10_kiq_query_status,
3425         .kiq_invalidate_tlbs = gfx10_kiq_invalidate_tlbs,
3426         .set_resources_size = 8,
3427         .map_queues_size = 7,
3428         .unmap_queues_size = 6,
3429         .query_status_size = 7,
3430         .invalidate_tlbs_size = 2,
3431 };
3432
3433 static void gfx_v10_0_set_kiq_pm4_funcs(struct amdgpu_device *adev)
3434 {
3435         adev->gfx.kiq.pmf = &gfx_v10_0_kiq_pm4_funcs;
3436 }
3437
3438 static void gfx_v10_0_init_spm_golden_registers(struct amdgpu_device *adev)
3439 {
3440         switch (adev->asic_type) {
3441         case CHIP_NAVI10:
3442                 soc15_program_register_sequence(adev,
3443                                                 golden_settings_gc_rlc_spm_10_0_nv10,
3444                                                 (const u32)ARRAY_SIZE(golden_settings_gc_rlc_spm_10_0_nv10));
3445                 break;
3446         case CHIP_NAVI14:
3447                 soc15_program_register_sequence(adev,
3448                                                 golden_settings_gc_rlc_spm_10_1_nv14,
3449                                                 (const u32)ARRAY_SIZE(golden_settings_gc_rlc_spm_10_1_nv14));
3450                 break;
3451         case CHIP_NAVI12:
3452                 soc15_program_register_sequence(adev,
3453                                                 golden_settings_gc_rlc_spm_10_1_2_nv12,
3454                                                 (const u32)ARRAY_SIZE(golden_settings_gc_rlc_spm_10_1_2_nv12));
3455                 break;
3456         default:
3457                 break;
3458         }
3459 }
3460
3461 static void gfx_v10_0_init_golden_registers(struct amdgpu_device *adev)
3462 {
3463         switch (adev->asic_type) {
3464         case CHIP_NAVI10:
3465                 soc15_program_register_sequence(adev,
3466                                                 golden_settings_gc_10_1,
3467                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_1));
3468                 soc15_program_register_sequence(adev,
3469                                                 golden_settings_gc_10_0_nv10,
3470                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_0_nv10));
3471                 break;
3472         case CHIP_NAVI14:
3473                 soc15_program_register_sequence(adev,
3474                                                 golden_settings_gc_10_1_1,
3475                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_1_1));
3476                 soc15_program_register_sequence(adev,
3477                                                 golden_settings_gc_10_1_nv14,
3478                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_1_nv14));
3479                 break;
3480         case CHIP_NAVI12:
3481                 soc15_program_register_sequence(adev,
3482                                                 golden_settings_gc_10_1_2,
3483                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_1_2));
3484                 soc15_program_register_sequence(adev,
3485                                                 golden_settings_gc_10_1_2_nv12,
3486                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_1_2_nv12));
3487                 break;
3488         case CHIP_SIENNA_CICHLID:
3489                 soc15_program_register_sequence(adev,
3490                                                 golden_settings_gc_10_3,
3491                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_3));
3492                 soc15_program_register_sequence(adev,
3493                                                 golden_settings_gc_10_3_sienna_cichlid,
3494                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_sienna_cichlid));
3495                 break;
3496         case CHIP_NAVY_FLOUNDER:
3497                 soc15_program_register_sequence(adev,
3498                                                 golden_settings_gc_10_3_2,
3499                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_2));
3500                 break;
3501         case CHIP_VANGOGH:
3502                 soc15_program_register_sequence(adev,
3503                                                 golden_settings_gc_10_3_vangogh,
3504                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_vangogh));
3505                 break;
3506         case CHIP_DIMGREY_CAVEFISH:
3507                 soc15_program_register_sequence(adev,
3508                                                 golden_settings_gc_10_3_4,
3509                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_4));
3510                 break;
3511         default:
3512                 break;
3513         }
3514         gfx_v10_0_init_spm_golden_registers(adev);
3515 }
3516
3517 static void gfx_v10_0_scratch_init(struct amdgpu_device *adev)
3518 {
3519         adev->gfx.scratch.num_reg = 8;
3520         adev->gfx.scratch.reg_base = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG0);
3521         adev->gfx.scratch.free_mask = (1u << adev->gfx.scratch.num_reg) - 1;
3522 }
3523
3524 static void gfx_v10_0_write_data_to_reg(struct amdgpu_ring *ring, int eng_sel,
3525                                        bool wc, uint32_t reg, uint32_t val)
3526 {
3527         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
3528         amdgpu_ring_write(ring, WRITE_DATA_ENGINE_SEL(eng_sel) |
3529                           WRITE_DATA_DST_SEL(0) | (wc ? WR_CONFIRM : 0));
3530         amdgpu_ring_write(ring, reg);
3531         amdgpu_ring_write(ring, 0);
3532         amdgpu_ring_write(ring, val);
3533 }
3534
3535 static void gfx_v10_0_wait_reg_mem(struct amdgpu_ring *ring, int eng_sel,
3536                                   int mem_space, int opt, uint32_t addr0,
3537                                   uint32_t addr1, uint32_t ref, uint32_t mask,
3538                                   uint32_t inv)
3539 {
3540         amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
3541         amdgpu_ring_write(ring,
3542                           /* memory (1) or register (0) */
3543                           (WAIT_REG_MEM_MEM_SPACE(mem_space) |
3544                            WAIT_REG_MEM_OPERATION(opt) | /* wait */
3545                            WAIT_REG_MEM_FUNCTION(3) |  /* equal */
3546                            WAIT_REG_MEM_ENGINE(eng_sel)));
3547
3548         if (mem_space)
3549                 BUG_ON(addr0 & 0x3); /* Dword align */
3550         amdgpu_ring_write(ring, addr0);
3551         amdgpu_ring_write(ring, addr1);
3552         amdgpu_ring_write(ring, ref);
3553         amdgpu_ring_write(ring, mask);
3554         amdgpu_ring_write(ring, inv); /* poll interval */
3555 }
3556
3557 static int gfx_v10_0_ring_test_ring(struct amdgpu_ring *ring)
3558 {
3559         struct amdgpu_device *adev = ring->adev;
3560         uint32_t scratch;
3561         uint32_t tmp = 0;
3562         unsigned i;
3563         int r;
3564
3565         r = amdgpu_gfx_scratch_get(adev, &scratch);
3566         if (r) {
3567                 DRM_ERROR("amdgpu: cp failed to get scratch reg (%d).\n", r);
3568                 return r;
3569         }
3570
3571         WREG32(scratch, 0xCAFEDEAD);
3572
3573         r = amdgpu_ring_alloc(ring, 3);
3574         if (r) {
3575                 DRM_ERROR("amdgpu: cp failed to lock ring %d (%d).\n",
3576                           ring->idx, r);
3577                 amdgpu_gfx_scratch_free(adev, scratch);
3578                 return r;
3579         }
3580
3581         amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1));
3582         amdgpu_ring_write(ring, (scratch - PACKET3_SET_UCONFIG_REG_START));
3583         amdgpu_ring_write(ring, 0xDEADBEEF);
3584         amdgpu_ring_commit(ring);
3585
3586         for (i = 0; i < adev->usec_timeout; i++) {
3587                 tmp = RREG32(scratch);
3588                 if (tmp == 0xDEADBEEF)
3589                         break;
3590                 if (amdgpu_emu_mode == 1)
3591                         msleep(1);
3592                 else
3593                         udelay(1);
3594         }
3595
3596         if (i >= adev->usec_timeout)
3597                 r = -ETIMEDOUT;
3598
3599         amdgpu_gfx_scratch_free(adev, scratch);
3600
3601         return r;
3602 }
3603
3604 static int gfx_v10_0_ring_test_ib(struct amdgpu_ring *ring, long timeout)
3605 {
3606         struct amdgpu_device *adev = ring->adev;
3607         struct amdgpu_ib ib;
3608         struct dma_fence *f = NULL;
3609         unsigned index;
3610         uint64_t gpu_addr;
3611         uint32_t tmp;
3612         long r;
3613
3614         r = amdgpu_device_wb_get(adev, &index);
3615         if (r)
3616                 return r;
3617
3618         gpu_addr = adev->wb.gpu_addr + (index * 4);
3619         adev->wb.wb[index] = cpu_to_le32(0xCAFEDEAD);
3620         memset(&ib, 0, sizeof(ib));
3621         r = amdgpu_ib_get(adev, NULL, 16,
3622                                         AMDGPU_IB_POOL_DIRECT, &ib);
3623         if (r)
3624                 goto err1;
3625
3626         ib.ptr[0] = PACKET3(PACKET3_WRITE_DATA, 3);
3627         ib.ptr[1] = WRITE_DATA_DST_SEL(5) | WR_CONFIRM;
3628         ib.ptr[2] = lower_32_bits(gpu_addr);
3629         ib.ptr[3] = upper_32_bits(gpu_addr);
3630         ib.ptr[4] = 0xDEADBEEF;
3631         ib.length_dw = 5;
3632
3633         r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
3634         if (r)
3635                 goto err2;
3636
3637         r = dma_fence_wait_timeout(f, false, timeout);
3638         if (r == 0) {
3639                 r = -ETIMEDOUT;
3640                 goto err2;
3641         } else if (r < 0) {
3642                 goto err2;
3643         }
3644
3645         tmp = adev->wb.wb[index];
3646         if (tmp == 0xDEADBEEF)
3647                 r = 0;
3648         else
3649                 r = -EINVAL;
3650 err2:
3651         amdgpu_ib_free(adev, &ib, NULL);
3652         dma_fence_put(f);
3653 err1:
3654         amdgpu_device_wb_free(adev, index);
3655         return r;
3656 }
3657
3658 static void gfx_v10_0_free_microcode(struct amdgpu_device *adev)
3659 {
3660         release_firmware(adev->gfx.pfp_fw);
3661         adev->gfx.pfp_fw = NULL;
3662         release_firmware(adev->gfx.me_fw);
3663         adev->gfx.me_fw = NULL;
3664         release_firmware(adev->gfx.ce_fw);
3665         adev->gfx.ce_fw = NULL;
3666         release_firmware(adev->gfx.rlc_fw);
3667         adev->gfx.rlc_fw = NULL;
3668         release_firmware(adev->gfx.mec_fw);
3669         adev->gfx.mec_fw = NULL;
3670         release_firmware(adev->gfx.mec2_fw);
3671         adev->gfx.mec2_fw = NULL;
3672
3673         kfree(adev->gfx.rlc.register_list_format);
3674 }
3675
3676 static void gfx_v10_0_check_fw_write_wait(struct amdgpu_device *adev)
3677 {
3678         adev->gfx.cp_fw_write_wait = false;
3679
3680         switch (adev->asic_type) {
3681         case CHIP_NAVI10:
3682         case CHIP_NAVI12:
3683         case CHIP_NAVI14:
3684                 if ((adev->gfx.me_fw_version >= 0x00000046) &&
3685                     (adev->gfx.me_feature_version >= 27) &&
3686                     (adev->gfx.pfp_fw_version >= 0x00000068) &&
3687                     (adev->gfx.pfp_feature_version >= 27) &&
3688                     (adev->gfx.mec_fw_version >= 0x0000005b) &&
3689                     (adev->gfx.mec_feature_version >= 27))
3690                         adev->gfx.cp_fw_write_wait = true;
3691                 break;
3692         case CHIP_SIENNA_CICHLID:
3693         case CHIP_NAVY_FLOUNDER:
3694         case CHIP_VANGOGH:
3695         case CHIP_DIMGREY_CAVEFISH:
3696                 adev->gfx.cp_fw_write_wait = true;
3697                 break;
3698         default:
3699                 break;
3700         }
3701
3702         if (!adev->gfx.cp_fw_write_wait)
3703                 DRM_WARN_ONCE("CP firmware version too old, please update!");
3704 }
3705
3706
3707 static void gfx_v10_0_init_rlc_ext_microcode(struct amdgpu_device *adev)
3708 {
3709         const struct rlc_firmware_header_v2_1 *rlc_hdr;
3710
3711         rlc_hdr = (const struct rlc_firmware_header_v2_1 *)adev->gfx.rlc_fw->data;
3712         adev->gfx.rlc_srlc_fw_version = le32_to_cpu(rlc_hdr->save_restore_list_cntl_ucode_ver);
3713         adev->gfx.rlc_srlc_feature_version = le32_to_cpu(rlc_hdr->save_restore_list_cntl_feature_ver);
3714         adev->gfx.rlc.save_restore_list_cntl_size_bytes = le32_to_cpu(rlc_hdr->save_restore_list_cntl_size_bytes);
3715         adev->gfx.rlc.save_restore_list_cntl = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_list_cntl_offset_bytes);
3716         adev->gfx.rlc_srlg_fw_version = le32_to_cpu(rlc_hdr->save_restore_list_gpm_ucode_ver);
3717         adev->gfx.rlc_srlg_feature_version = le32_to_cpu(rlc_hdr->save_restore_list_gpm_feature_ver);
3718         adev->gfx.rlc.save_restore_list_gpm_size_bytes = le32_to_cpu(rlc_hdr->save_restore_list_gpm_size_bytes);
3719         adev->gfx.rlc.save_restore_list_gpm = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_list_gpm_offset_bytes);
3720         adev->gfx.rlc_srls_fw_version = le32_to_cpu(rlc_hdr->save_restore_list_srm_ucode_ver);
3721         adev->gfx.rlc_srls_feature_version = le32_to_cpu(rlc_hdr->save_restore_list_srm_feature_ver);
3722         adev->gfx.rlc.save_restore_list_srm_size_bytes = le32_to_cpu(rlc_hdr->save_restore_list_srm_size_bytes);
3723         adev->gfx.rlc.save_restore_list_srm = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_list_srm_offset_bytes);
3724         adev->gfx.rlc.reg_list_format_direct_reg_list_length =
3725                         le32_to_cpu(rlc_hdr->reg_list_format_direct_reg_list_length);
3726 }
3727
3728 static void gfx_v10_0_init_rlc_iram_dram_microcode(struct amdgpu_device *adev)
3729 {
3730         const struct rlc_firmware_header_v2_2 *rlc_hdr;
3731
3732         rlc_hdr = (const struct rlc_firmware_header_v2_2 *)adev->gfx.rlc_fw->data;
3733         adev->gfx.rlc.rlc_iram_ucode_size_bytes = le32_to_cpu(rlc_hdr->rlc_iram_ucode_size_bytes);
3734         adev->gfx.rlc.rlc_iram_ucode = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->rlc_iram_ucode_offset_bytes);
3735         adev->gfx.rlc.rlc_dram_ucode_size_bytes = le32_to_cpu(rlc_hdr->rlc_dram_ucode_size_bytes);
3736         adev->gfx.rlc.rlc_dram_ucode = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->rlc_dram_ucode_offset_bytes);
3737 }
3738
3739 static bool gfx_v10_0_navi10_gfxoff_should_enable(struct amdgpu_device *adev)
3740 {
3741         bool ret = false;
3742
3743         switch (adev->pdev->revision) {
3744         case 0xc2:
3745         case 0xc3:
3746                 ret = true;
3747                 break;
3748         default:
3749                 ret = false;
3750                 break;
3751         }
3752
3753         return ret ;
3754 }
3755
3756 static void gfx_v10_0_check_gfxoff_flag(struct amdgpu_device *adev)
3757 {
3758         switch (adev->asic_type) {
3759         case CHIP_NAVI10:
3760                 if (!gfx_v10_0_navi10_gfxoff_should_enable(adev))
3761                         adev->pm.pp_feature &= ~PP_GFXOFF_MASK;
3762                 break;
3763         case CHIP_VANGOGH:
3764                 adev->pm.pp_feature &= ~PP_GFXOFF_MASK;
3765                 break;
3766         default:
3767                 break;
3768         }
3769 }
3770
3771 static int gfx_v10_0_init_microcode(struct amdgpu_device *adev)
3772 {
3773         const char *chip_name;
3774         char fw_name[40];
3775         char wks[10];
3776         int err;
3777         struct amdgpu_firmware_info *info = NULL;
3778         const struct common_firmware_header *header = NULL;
3779         const struct gfx_firmware_header_v1_0 *cp_hdr;
3780         const struct rlc_firmware_header_v2_0 *rlc_hdr;
3781         unsigned int *tmp = NULL;
3782         unsigned int i = 0;
3783         uint16_t version_major;
3784         uint16_t version_minor;
3785
3786         DRM_DEBUG("\n");
3787
3788         memset(wks, 0, sizeof(wks));
3789         switch (adev->asic_type) {
3790         case CHIP_NAVI10:
3791                 chip_name = "navi10";
3792                 break;
3793         case CHIP_NAVI14:
3794                 chip_name = "navi14";
3795                 if (!(adev->pdev->device == 0x7340 &&
3796                       adev->pdev->revision != 0x00))
3797                         snprintf(wks, sizeof(wks), "_wks");
3798                 break;
3799         case CHIP_NAVI12:
3800                 chip_name = "navi12";
3801                 break;
3802         case CHIP_SIENNA_CICHLID:
3803                 chip_name = "sienna_cichlid";
3804                 break;
3805         case CHIP_NAVY_FLOUNDER:
3806                 chip_name = "navy_flounder";
3807                 break;
3808         case CHIP_VANGOGH:
3809                 chip_name = "vangogh";
3810                 break;
3811         case CHIP_DIMGREY_CAVEFISH:
3812                 chip_name = "dimgrey_cavefish";
3813                 break;
3814         default:
3815                 BUG();
3816         }
3817
3818         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_pfp%s.bin", chip_name, wks);
3819         err = request_firmware(&adev->gfx.pfp_fw, fw_name, adev->dev);
3820         if (err)
3821                 goto out;
3822         err = amdgpu_ucode_validate(adev->gfx.pfp_fw);
3823         if (err)
3824                 goto out;
3825         cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data;
3826         adev->gfx.pfp_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
3827         adev->gfx.pfp_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
3828
3829         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_me%s.bin", chip_name, wks);
3830         err = request_firmware(&adev->gfx.me_fw, fw_name, adev->dev);
3831         if (err)
3832                 goto out;
3833         err = amdgpu_ucode_validate(adev->gfx.me_fw);
3834         if (err)
3835                 goto out;
3836         cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data;
3837         adev->gfx.me_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
3838         adev->gfx.me_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
3839
3840         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ce%s.bin", chip_name, wks);
3841         err = request_firmware(&adev->gfx.ce_fw, fw_name, adev->dev);
3842         if (err)
3843                 goto out;
3844         err = amdgpu_ucode_validate(adev->gfx.ce_fw);
3845         if (err)
3846                 goto out;
3847         cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data;
3848         adev->gfx.ce_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
3849         adev->gfx.ce_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
3850
3851         if (!amdgpu_sriov_vf(adev)) {
3852                 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_rlc.bin", chip_name);
3853                 err = request_firmware(&adev->gfx.rlc_fw, fw_name, adev->dev);
3854                 if (err)
3855                         goto out;
3856                 err = amdgpu_ucode_validate(adev->gfx.rlc_fw);
3857                 rlc_hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data;
3858                 version_major = le16_to_cpu(rlc_hdr->header.header_version_major);
3859                 version_minor = le16_to_cpu(rlc_hdr->header.header_version_minor);
3860
3861                 adev->gfx.rlc_fw_version = le32_to_cpu(rlc_hdr->header.ucode_version);
3862                 adev->gfx.rlc_feature_version = le32_to_cpu(rlc_hdr->ucode_feature_version);
3863                 adev->gfx.rlc.save_and_restore_offset =
3864                         le32_to_cpu(rlc_hdr->save_and_restore_offset);
3865                 adev->gfx.rlc.clear_state_descriptor_offset =
3866                         le32_to_cpu(rlc_hdr->clear_state_descriptor_offset);
3867                 adev->gfx.rlc.avail_scratch_ram_locations =
3868                         le32_to_cpu(rlc_hdr->avail_scratch_ram_locations);
3869                 adev->gfx.rlc.reg_restore_list_size =
3870                         le32_to_cpu(rlc_hdr->reg_restore_list_size);
3871                 adev->gfx.rlc.reg_list_format_start =
3872                         le32_to_cpu(rlc_hdr->reg_list_format_start);
3873                 adev->gfx.rlc.reg_list_format_separate_start =
3874                         le32_to_cpu(rlc_hdr->reg_list_format_separate_start);
3875                 adev->gfx.rlc.starting_offsets_start =
3876                         le32_to_cpu(rlc_hdr->starting_offsets_start);
3877                 adev->gfx.rlc.reg_list_format_size_bytes =
3878                         le32_to_cpu(rlc_hdr->reg_list_format_size_bytes);
3879                 adev->gfx.rlc.reg_list_size_bytes =
3880                         le32_to_cpu(rlc_hdr->reg_list_size_bytes);
3881                 adev->gfx.rlc.register_list_format =
3882                         kmalloc(adev->gfx.rlc.reg_list_format_size_bytes +
3883                                         adev->gfx.rlc.reg_list_size_bytes, GFP_KERNEL);
3884                 if (!adev->gfx.rlc.register_list_format) {
3885                         err = -ENOMEM;
3886                         goto out;
3887                 }
3888
3889                 tmp = (unsigned int *)((uintptr_t)rlc_hdr +
3890                                                            le32_to_cpu(rlc_hdr->reg_list_format_array_offset_bytes));
3891                 for (i = 0 ; i < (rlc_hdr->reg_list_format_size_bytes >> 2); i++)
3892                         adev->gfx.rlc.register_list_format[i] = le32_to_cpu(tmp[i]);
3893
3894                 adev->gfx.rlc.register_restore = adev->gfx.rlc.register_list_format + i;
3895
3896                 tmp = (unsigned int *)((uintptr_t)rlc_hdr +
3897                                                            le32_to_cpu(rlc_hdr->reg_list_array_offset_bytes));
3898                 for (i = 0 ; i < (rlc_hdr->reg_list_size_bytes >> 2); i++)
3899                         adev->gfx.rlc.register_restore[i] = le32_to_cpu(tmp[i]);
3900
3901                 if (version_major == 2) {
3902                         if (version_minor >= 1)
3903                                 gfx_v10_0_init_rlc_ext_microcode(adev);
3904                         if (version_minor == 2)
3905                                 gfx_v10_0_init_rlc_iram_dram_microcode(adev);
3906                 }
3907         }
3908
3909         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec%s.bin", chip_name, wks);
3910         err = request_firmware(&adev->gfx.mec_fw, fw_name, adev->dev);
3911         if (err)
3912                 goto out;
3913         err = amdgpu_ucode_validate(adev->gfx.mec_fw);
3914         if (err)
3915                 goto out;
3916         cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
3917         adev->gfx.mec_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
3918         adev->gfx.mec_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
3919
3920         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec2%s.bin", chip_name, wks);
3921         err = request_firmware(&adev->gfx.mec2_fw, fw_name, adev->dev);
3922         if (!err) {
3923                 err = amdgpu_ucode_validate(adev->gfx.mec2_fw);
3924                 if (err)
3925                         goto out;
3926                 cp_hdr = (const struct gfx_firmware_header_v1_0 *)
3927                 adev->gfx.mec2_fw->data;
3928                 adev->gfx.mec2_fw_version =
3929                 le32_to_cpu(cp_hdr->header.ucode_version);
3930                 adev->gfx.mec2_feature_version =
3931                 le32_to_cpu(cp_hdr->ucode_feature_version);
3932         } else {
3933                 err = 0;
3934                 adev->gfx.mec2_fw = NULL;
3935         }
3936
3937         if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
3938                 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_PFP];
3939                 info->ucode_id = AMDGPU_UCODE_ID_CP_PFP;
3940                 info->fw = adev->gfx.pfp_fw;
3941                 header = (const struct common_firmware_header *)info->fw->data;
3942                 adev->firmware.fw_size +=
3943                         ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
3944
3945                 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_ME];
3946                 info->ucode_id = AMDGPU_UCODE_ID_CP_ME;
3947                 info->fw = adev->gfx.me_fw;
3948                 header = (const struct common_firmware_header *)info->fw->data;
3949                 adev->firmware.fw_size +=
3950                         ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
3951
3952                 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_CE];
3953                 info->ucode_id = AMDGPU_UCODE_ID_CP_CE;
3954                 info->fw = adev->gfx.ce_fw;
3955                 header = (const struct common_firmware_header *)info->fw->data;
3956                 adev->firmware.fw_size +=
3957                         ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
3958
3959                 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_G];
3960                 info->ucode_id = AMDGPU_UCODE_ID_RLC_G;
3961                 info->fw = adev->gfx.rlc_fw;
3962                 if (info->fw) {
3963                         header = (const struct common_firmware_header *)info->fw->data;
3964                         adev->firmware.fw_size +=
3965                                 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
3966                 }
3967                 if (adev->gfx.rlc.save_restore_list_cntl_size_bytes &&
3968                     adev->gfx.rlc.save_restore_list_gpm_size_bytes &&
3969                     adev->gfx.rlc.save_restore_list_srm_size_bytes) {
3970                         info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL];
3971                         info->ucode_id = AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL;
3972                         info->fw = adev->gfx.rlc_fw;
3973                         adev->firmware.fw_size +=
3974                                 ALIGN(adev->gfx.rlc.save_restore_list_cntl_size_bytes, PAGE_SIZE);
3975
3976                         info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM];
3977                         info->ucode_id = AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM;
3978                         info->fw = adev->gfx.rlc_fw;
3979                         adev->firmware.fw_size +=
3980                                 ALIGN(adev->gfx.rlc.save_restore_list_gpm_size_bytes, PAGE_SIZE);
3981
3982                         info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM];
3983                         info->ucode_id = AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM;
3984                         info->fw = adev->gfx.rlc_fw;
3985                         adev->firmware.fw_size +=
3986                                 ALIGN(adev->gfx.rlc.save_restore_list_srm_size_bytes, PAGE_SIZE);
3987
3988                         if (adev->gfx.rlc.rlc_iram_ucode_size_bytes &&
3989                             adev->gfx.rlc.rlc_dram_ucode_size_bytes) {
3990                                 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_IRAM];
3991                                 info->ucode_id = AMDGPU_UCODE_ID_RLC_IRAM;
3992                                 info->fw = adev->gfx.rlc_fw;
3993                                 adev->firmware.fw_size +=
3994                                         ALIGN(adev->gfx.rlc.rlc_iram_ucode_size_bytes, PAGE_SIZE);
3995
3996                                 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_DRAM];
3997                                 info->ucode_id = AMDGPU_UCODE_ID_RLC_DRAM;
3998                                 info->fw = adev->gfx.rlc_fw;
3999                                 adev->firmware.fw_size +=
4000                                         ALIGN(adev->gfx.rlc.rlc_dram_ucode_size_bytes, PAGE_SIZE);
4001                         }
4002                 }
4003
4004                 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC1];
4005                 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC1;
4006                 info->fw = adev->gfx.mec_fw;
4007                 header = (const struct common_firmware_header *)info->fw->data;
4008                 cp_hdr = (const struct gfx_firmware_header_v1_0 *)info->fw->data;
4009                 adev->firmware.fw_size +=
4010                         ALIGN(le32_to_cpu(header->ucode_size_bytes) -
4011                               le32_to_cpu(cp_hdr->jt_size) * 4, PAGE_SIZE);
4012
4013                 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC1_JT];
4014                 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC1_JT;
4015                 info->fw = adev->gfx.mec_fw;
4016                 adev->firmware.fw_size +=
4017                         ALIGN(le32_to_cpu(cp_hdr->jt_size) * 4, PAGE_SIZE);
4018
4019                 if (adev->gfx.mec2_fw) {
4020                         info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC2];
4021                         info->ucode_id = AMDGPU_UCODE_ID_CP_MEC2;
4022                         info->fw = adev->gfx.mec2_fw;
4023                         header = (const struct common_firmware_header *)info->fw->data;
4024                         cp_hdr = (const struct gfx_firmware_header_v1_0 *)info->fw->data;
4025                         adev->firmware.fw_size +=
4026                                 ALIGN(le32_to_cpu(header->ucode_size_bytes) -
4027                                       le32_to_cpu(cp_hdr->jt_size) * 4,
4028                                       PAGE_SIZE);
4029                         info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC2_JT];
4030                         info->ucode_id = AMDGPU_UCODE_ID_CP_MEC2_JT;
4031                         info->fw = adev->gfx.mec2_fw;
4032                         adev->firmware.fw_size +=
4033                                 ALIGN(le32_to_cpu(cp_hdr->jt_size) * 4,
4034                                       PAGE_SIZE);
4035                 }
4036         }
4037
4038         gfx_v10_0_check_fw_write_wait(adev);
4039 out:
4040         if (err) {
4041                 dev_err(adev->dev,
4042                         "gfx10: Failed to load firmware \"%s\"\n",
4043                         fw_name);
4044                 release_firmware(adev->gfx.pfp_fw);
4045                 adev->gfx.pfp_fw = NULL;
4046                 release_firmware(adev->gfx.me_fw);
4047                 adev->gfx.me_fw = NULL;
4048                 release_firmware(adev->gfx.ce_fw);
4049                 adev->gfx.ce_fw = NULL;
4050                 release_firmware(adev->gfx.rlc_fw);
4051                 adev->gfx.rlc_fw = NULL;
4052                 release_firmware(adev->gfx.mec_fw);
4053                 adev->gfx.mec_fw = NULL;
4054                 release_firmware(adev->gfx.mec2_fw);
4055                 adev->gfx.mec2_fw = NULL;
4056         }
4057
4058         gfx_v10_0_check_gfxoff_flag(adev);
4059
4060         return err;
4061 }
4062
4063 static u32 gfx_v10_0_get_csb_size(struct amdgpu_device *adev)
4064 {
4065         u32 count = 0;
4066         const struct cs_section_def *sect = NULL;
4067         const struct cs_extent_def *ext = NULL;
4068
4069         /* begin clear state */
4070         count += 2;
4071         /* context control state */
4072         count += 3;
4073
4074         for (sect = gfx10_cs_data; sect->section != NULL; ++sect) {
4075                 for (ext = sect->section; ext->extent != NULL; ++ext) {
4076                         if (sect->id == SECT_CONTEXT)
4077                                 count += 2 + ext->reg_count;
4078                         else
4079                                 return 0;
4080                 }
4081         }
4082
4083         /* set PA_SC_TILE_STEERING_OVERRIDE */
4084         count += 3;
4085         /* end clear state */
4086         count += 2;
4087         /* clear state */
4088         count += 2;
4089
4090         return count;
4091 }
4092
4093 static void gfx_v10_0_get_csb_buffer(struct amdgpu_device *adev,
4094                                     volatile u32 *buffer)
4095 {
4096         u32 count = 0, i;
4097         const struct cs_section_def *sect = NULL;
4098         const struct cs_extent_def *ext = NULL;
4099         int ctx_reg_offset;
4100
4101         if (adev->gfx.rlc.cs_data == NULL)
4102                 return;
4103         if (buffer == NULL)
4104                 return;
4105
4106         buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));
4107         buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
4108
4109         buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CONTEXT_CONTROL, 1));
4110         buffer[count++] = cpu_to_le32(0x80000000);
4111         buffer[count++] = cpu_to_le32(0x80000000);
4112
4113         for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) {
4114                 for (ext = sect->section; ext->extent != NULL; ++ext) {
4115                         if (sect->id == SECT_CONTEXT) {
4116                                 buffer[count++] =
4117                                         cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count));
4118                                 buffer[count++] = cpu_to_le32(ext->reg_index -
4119                                                 PACKET3_SET_CONTEXT_REG_START);
4120                                 for (i = 0; i < ext->reg_count; i++)
4121                                         buffer[count++] = cpu_to_le32(ext->extent[i]);
4122                         } else {
4123                                 return;
4124                         }
4125                 }
4126         }
4127
4128         ctx_reg_offset =
4129                 SOC15_REG_OFFSET(GC, 0, mmPA_SC_TILE_STEERING_OVERRIDE) - PACKET3_SET_CONTEXT_REG_START;
4130         buffer[count++] = cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, 1));
4131         buffer[count++] = cpu_to_le32(ctx_reg_offset);
4132         buffer[count++] = cpu_to_le32(adev->gfx.config.pa_sc_tile_steering_override);
4133
4134         buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));
4135         buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_END_CLEAR_STATE);
4136
4137         buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CLEAR_STATE, 0));
4138         buffer[count++] = cpu_to_le32(0);
4139 }
4140
4141 static void gfx_v10_0_rlc_fini(struct amdgpu_device *adev)
4142 {
4143         /* clear state block */
4144         amdgpu_bo_free_kernel(&adev->gfx.rlc.clear_state_obj,
4145                         &adev->gfx.rlc.clear_state_gpu_addr,
4146                         (void **)&adev->gfx.rlc.cs_ptr);
4147
4148         /* jump table block */
4149         amdgpu_bo_free_kernel(&adev->gfx.rlc.cp_table_obj,
4150                         &adev->gfx.rlc.cp_table_gpu_addr,
4151                         (void **)&adev->gfx.rlc.cp_table_ptr);
4152 }
4153
4154 static int gfx_v10_0_rlc_init(struct amdgpu_device *adev)
4155 {
4156         const struct cs_section_def *cs_data;
4157         int r;
4158
4159         adev->gfx.rlc.cs_data = gfx10_cs_data;
4160
4161         cs_data = adev->gfx.rlc.cs_data;
4162
4163         if (cs_data) {
4164                 /* init clear state block */
4165                 r = amdgpu_gfx_rlc_init_csb(adev);
4166                 if (r)
4167                         return r;
4168         }
4169
4170         /* init spm vmid with 0xf */
4171         if (adev->gfx.rlc.funcs->update_spm_vmid)
4172                 adev->gfx.rlc.funcs->update_spm_vmid(adev, 0xf);
4173
4174         return 0;
4175 }
4176
4177 static void gfx_v10_0_mec_fini(struct amdgpu_device *adev)
4178 {
4179         amdgpu_bo_free_kernel(&adev->gfx.mec.hpd_eop_obj, NULL, NULL);
4180         amdgpu_bo_free_kernel(&adev->gfx.mec.mec_fw_obj, NULL, NULL);
4181 }
4182
4183 static int gfx_v10_0_me_init(struct amdgpu_device *adev)
4184 {
4185         int r;
4186
4187         bitmap_zero(adev->gfx.me.queue_bitmap, AMDGPU_MAX_GFX_QUEUES);
4188
4189         amdgpu_gfx_graphics_queue_acquire(adev);
4190
4191         r = gfx_v10_0_init_microcode(adev);
4192         if (r)
4193                 DRM_ERROR("Failed to load gfx firmware!\n");
4194
4195         return r;
4196 }
4197
4198 static int gfx_v10_0_mec_init(struct amdgpu_device *adev)
4199 {
4200         int r;
4201         u32 *hpd;
4202         const __le32 *fw_data = NULL;
4203         unsigned fw_size;
4204         u32 *fw = NULL;
4205         size_t mec_hpd_size;
4206
4207         const struct gfx_firmware_header_v1_0 *mec_hdr = NULL;
4208
4209         bitmap_zero(adev->gfx.mec.queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES);
4210
4211         /* take ownership of the relevant compute queues */
4212         amdgpu_gfx_compute_queue_acquire(adev);
4213         mec_hpd_size = adev->gfx.num_compute_rings * GFX10_MEC_HPD_SIZE;
4214
4215         if (mec_hpd_size) {
4216                 r = amdgpu_bo_create_reserved(adev, mec_hpd_size, PAGE_SIZE,
4217                                               AMDGPU_GEM_DOMAIN_GTT,
4218                                               &adev->gfx.mec.hpd_eop_obj,
4219                                               &adev->gfx.mec.hpd_eop_gpu_addr,
4220                                               (void **)&hpd);
4221                 if (r) {
4222                         dev_warn(adev->dev, "(%d) create HDP EOP bo failed\n", r);
4223                         gfx_v10_0_mec_fini(adev);
4224                         return r;
4225                 }
4226
4227                 memset(hpd, 0, mec_hpd_size);
4228
4229                 amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj);
4230                 amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj);
4231         }
4232
4233         if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
4234                 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
4235
4236                 fw_data = (const __le32 *) (adev->gfx.mec_fw->data +
4237                          le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes));
4238                 fw_size = le32_to_cpu(mec_hdr->header.ucode_size_bytes);
4239
4240                 r = amdgpu_bo_create_reserved(adev, mec_hdr->header.ucode_size_bytes,
4241                                               PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,
4242                                               &adev->gfx.mec.mec_fw_obj,
4243                                               &adev->gfx.mec.mec_fw_gpu_addr,
4244                                               (void **)&fw);
4245                 if (r) {
4246                         dev_err(adev->dev, "(%d) failed to create mec fw bo\n", r);
4247                         gfx_v10_0_mec_fini(adev);
4248                         return r;
4249                 }
4250
4251                 memcpy(fw, fw_data, fw_size);
4252
4253                 amdgpu_bo_kunmap(adev->gfx.mec.mec_fw_obj);
4254                 amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_obj);
4255         }
4256
4257         return 0;
4258 }
4259
4260 static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t wave, uint32_t address)
4261 {
4262         WREG32_SOC15(GC, 0, mmSQ_IND_INDEX,
4263                 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) |
4264                 (address << SQ_IND_INDEX__INDEX__SHIFT));
4265         return RREG32_SOC15(GC, 0, mmSQ_IND_DATA);
4266 }
4267
4268 static void wave_read_regs(struct amdgpu_device *adev, uint32_t wave,
4269                            uint32_t thread, uint32_t regno,
4270                            uint32_t num, uint32_t *out)
4271 {
4272         WREG32_SOC15(GC, 0, mmSQ_IND_INDEX,
4273                 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) |
4274                 (regno << SQ_IND_INDEX__INDEX__SHIFT) |
4275                 (thread << SQ_IND_INDEX__WORKITEM_ID__SHIFT) |
4276                 (SQ_IND_INDEX__AUTO_INCR_MASK));
4277         while (num--)
4278                 *(out++) = RREG32_SOC15(GC, 0, mmSQ_IND_DATA);
4279 }
4280
4281 static void gfx_v10_0_read_wave_data(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t *dst, int *no_fields)
4282 {
4283         /* in gfx10 the SIMD_ID is specified as part of the INSTANCE
4284          * field when performing a select_se_sh so it should be
4285          * zero here */
4286         WARN_ON(simd != 0);
4287
4288         /* type 2 wave data */
4289         dst[(*no_fields)++] = 2;
4290         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_STATUS);
4291         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_PC_LO);
4292         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_PC_HI);
4293         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXEC_LO);
4294         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXEC_HI);
4295         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_HW_ID1);
4296         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_HW_ID2);
4297         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_INST_DW0);
4298         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_GPR_ALLOC);
4299         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_LDS_ALLOC);
4300         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_TRAPSTS);
4301         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_STS);
4302         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_STS2);
4303         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_DBG1);
4304         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_M0);
4305 }
4306
4307 static void gfx_v10_0_read_wave_sgprs(struct amdgpu_device *adev, uint32_t simd,
4308                                      uint32_t wave, uint32_t start,
4309                                      uint32_t size, uint32_t *dst)
4310 {
4311         WARN_ON(simd != 0);
4312
4313         wave_read_regs(
4314                 adev, wave, 0, start + SQIND_WAVE_SGPRS_OFFSET, size,
4315                 dst);
4316 }
4317
4318 static void gfx_v10_0_read_wave_vgprs(struct amdgpu_device *adev, uint32_t simd,
4319                                       uint32_t wave, uint32_t thread,
4320                                       uint32_t start, uint32_t size,
4321                                       uint32_t *dst)
4322 {
4323         wave_read_regs(
4324                 adev, wave, thread,
4325                 start + SQIND_WAVE_VGPRS_OFFSET, size, dst);
4326 }
4327
4328 static void gfx_v10_0_select_me_pipe_q(struct amdgpu_device *adev,
4329                                        u32 me, u32 pipe, u32 q, u32 vm)
4330 {
4331         nv_grbm_select(adev, me, pipe, q, vm);
4332 }
4333
4334 static void gfx_v10_0_update_perfmon_mgcg(struct amdgpu_device *adev,
4335                                           bool enable)
4336 {
4337         uint32_t data, def;
4338
4339         data = def = RREG32_SOC15(GC, 0, mmRLC_PERFMON_CLK_CNTL);
4340
4341         if (enable)
4342                 data |= RLC_PERFMON_CLK_CNTL__PERFMON_CLOCK_STATE_MASK;
4343         else
4344                 data &= ~RLC_PERFMON_CLK_CNTL__PERFMON_CLOCK_STATE_MASK;
4345
4346         if (data != def)
4347                 WREG32_SOC15(GC, 0, mmRLC_PERFMON_CLK_CNTL, data);
4348 }
4349
4350 static const struct amdgpu_gfx_funcs gfx_v10_0_gfx_funcs = {
4351         .get_gpu_clock_counter = &gfx_v10_0_get_gpu_clock_counter,
4352         .select_se_sh = &gfx_v10_0_select_se_sh,
4353         .read_wave_data = &gfx_v10_0_read_wave_data,
4354         .read_wave_sgprs = &gfx_v10_0_read_wave_sgprs,
4355         .read_wave_vgprs = &gfx_v10_0_read_wave_vgprs,
4356         .select_me_pipe_q = &gfx_v10_0_select_me_pipe_q,
4357         .init_spm_golden = &gfx_v10_0_init_spm_golden_registers,
4358         .update_perfmon_mgcg = &gfx_v10_0_update_perfmon_mgcg,
4359 };
4360
4361 static void gfx_v10_0_gpu_early_init(struct amdgpu_device *adev)
4362 {
4363         u32 gb_addr_config;
4364
4365         adev->gfx.funcs = &gfx_v10_0_gfx_funcs;
4366
4367         switch (adev->asic_type) {
4368         case CHIP_NAVI10:
4369         case CHIP_NAVI14:
4370         case CHIP_NAVI12:
4371                 adev->gfx.config.max_hw_contexts = 8;
4372                 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
4373                 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
4374                 adev->gfx.config.sc_hiz_tile_fifo_size = 0;
4375                 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0;
4376                 gb_addr_config = RREG32_SOC15(GC, 0, mmGB_ADDR_CONFIG);
4377                 break;
4378         case CHIP_SIENNA_CICHLID:
4379         case CHIP_NAVY_FLOUNDER:
4380         case CHIP_VANGOGH:
4381         case CHIP_DIMGREY_CAVEFISH:
4382                 adev->gfx.config.max_hw_contexts = 8;
4383                 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
4384                 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
4385                 adev->gfx.config.sc_hiz_tile_fifo_size = 0;
4386                 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0;
4387                 gb_addr_config = RREG32_SOC15(GC, 0, mmGB_ADDR_CONFIG);
4388                 adev->gfx.config.gb_addr_config_fields.num_pkrs =
4389                         1 << REG_GET_FIELD(gb_addr_config, GB_ADDR_CONFIG, NUM_PKRS);
4390                 break;
4391         default:
4392                 BUG();
4393                 break;
4394         }
4395
4396         adev->gfx.config.gb_addr_config = gb_addr_config;
4397
4398         adev->gfx.config.gb_addr_config_fields.num_pipes = 1 <<
4399                         REG_GET_FIELD(adev->gfx.config.gb_addr_config,
4400                                       GB_ADDR_CONFIG, NUM_PIPES);
4401
4402         adev->gfx.config.max_tile_pipes =
4403                 adev->gfx.config.gb_addr_config_fields.num_pipes;
4404
4405         adev->gfx.config.gb_addr_config_fields.max_compress_frags = 1 <<
4406                         REG_GET_FIELD(adev->gfx.config.gb_addr_config,
4407                                       GB_ADDR_CONFIG, MAX_COMPRESSED_FRAGS);
4408         adev->gfx.config.gb_addr_config_fields.num_rb_per_se = 1 <<
4409                         REG_GET_FIELD(adev->gfx.config.gb_addr_config,
4410                                       GB_ADDR_CONFIG, NUM_RB_PER_SE);
4411         adev->gfx.config.gb_addr_config_fields.num_se = 1 <<
4412                         REG_GET_FIELD(adev->gfx.config.gb_addr_config,
4413                                       GB_ADDR_CONFIG, NUM_SHADER_ENGINES);
4414         adev->gfx.config.gb_addr_config_fields.pipe_interleave_size = 1 << (8 +
4415                         REG_GET_FIELD(adev->gfx.config.gb_addr_config,
4416                                       GB_ADDR_CONFIG, PIPE_INTERLEAVE_SIZE));
4417 }
4418
4419 static int gfx_v10_0_gfx_ring_init(struct amdgpu_device *adev, int ring_id,
4420                                    int me, int pipe, int queue)
4421 {
4422         int r;
4423         struct amdgpu_ring *ring;
4424         unsigned int irq_type;
4425
4426         ring = &adev->gfx.gfx_ring[ring_id];
4427
4428         ring->me = me;
4429         ring->pipe = pipe;
4430         ring->queue = queue;
4431
4432         ring->ring_obj = NULL;
4433         ring->use_doorbell = true;
4434
4435         if (!ring_id)
4436                 ring->doorbell_index = adev->doorbell_index.gfx_ring0 << 1;
4437         else
4438                 ring->doorbell_index = adev->doorbell_index.gfx_ring1 << 1;
4439         sprintf(ring->name, "gfx_%d.%d.%d", ring->me, ring->pipe, ring->queue);
4440
4441         irq_type = AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP + ring->pipe;
4442         r = amdgpu_ring_init(adev, ring, 1024,
4443                              &adev->gfx.eop_irq, irq_type,
4444                              AMDGPU_RING_PRIO_DEFAULT);
4445         if (r)
4446                 return r;
4447         return 0;
4448 }
4449
4450 static int gfx_v10_0_compute_ring_init(struct amdgpu_device *adev, int ring_id,
4451                                        int mec, int pipe, int queue)
4452 {
4453         int r;
4454         unsigned irq_type;
4455         struct amdgpu_ring *ring;
4456         unsigned int hw_prio;
4457
4458         ring = &adev->gfx.compute_ring[ring_id];
4459
4460         /* mec0 is me1 */
4461         ring->me = mec + 1;
4462         ring->pipe = pipe;
4463         ring->queue = queue;
4464
4465         ring->ring_obj = NULL;
4466         ring->use_doorbell = true;
4467         ring->doorbell_index = (adev->doorbell_index.mec_ring0 + ring_id) << 1;
4468         ring->eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr
4469                                 + (ring_id * GFX10_MEC_HPD_SIZE);
4470         sprintf(ring->name, "comp_%d.%d.%d", ring->me, ring->pipe, ring->queue);
4471
4472         irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP
4473                 + ((ring->me - 1) * adev->gfx.mec.num_pipe_per_mec)
4474                 + ring->pipe;
4475         hw_prio = amdgpu_gfx_is_high_priority_compute_queue(adev, ring->queue) ?
4476                         AMDGPU_GFX_PIPE_PRIO_HIGH : AMDGPU_GFX_PIPE_PRIO_NORMAL;
4477         /* type-2 packets are deprecated on MEC, use type-3 instead */
4478         r = amdgpu_ring_init(adev, ring, 1024,
4479                              &adev->gfx.eop_irq, irq_type, hw_prio);
4480         if (r)
4481                 return r;
4482
4483         return 0;
4484 }
4485
4486 static int gfx_v10_0_sw_init(void *handle)
4487 {
4488         int i, j, k, r, ring_id = 0;
4489         struct amdgpu_kiq *kiq;
4490         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4491
4492         switch (adev->asic_type) {
4493         case CHIP_NAVI10:
4494         case CHIP_NAVI14:
4495         case CHIP_NAVI12:
4496                 adev->gfx.me.num_me = 1;
4497                 adev->gfx.me.num_pipe_per_me = 1;
4498                 adev->gfx.me.num_queue_per_pipe = 1;
4499                 adev->gfx.mec.num_mec = 2;
4500                 adev->gfx.mec.num_pipe_per_mec = 4;
4501                 adev->gfx.mec.num_queue_per_pipe = 8;
4502                 break;
4503         case CHIP_SIENNA_CICHLID:
4504         case CHIP_NAVY_FLOUNDER:
4505         case CHIP_VANGOGH:
4506         case CHIP_DIMGREY_CAVEFISH:
4507                 adev->gfx.me.num_me = 1;
4508                 adev->gfx.me.num_pipe_per_me = 1;
4509                 adev->gfx.me.num_queue_per_pipe = 1;
4510                 adev->gfx.mec.num_mec = 2;
4511                 adev->gfx.mec.num_pipe_per_mec = 4;
4512                 adev->gfx.mec.num_queue_per_pipe = 4;
4513                 break;
4514         default:
4515                 adev->gfx.me.num_me = 1;
4516                 adev->gfx.me.num_pipe_per_me = 1;
4517                 adev->gfx.me.num_queue_per_pipe = 1;
4518                 adev->gfx.mec.num_mec = 1;
4519                 adev->gfx.mec.num_pipe_per_mec = 4;
4520                 adev->gfx.mec.num_queue_per_pipe = 8;
4521                 break;
4522         }
4523
4524         /* KIQ event */
4525         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP,
4526                               GFX_10_1__SRCID__CP_IB2_INTERRUPT_PKT,
4527                               &adev->gfx.kiq.irq);
4528         if (r)
4529                 return r;
4530
4531         /* EOP Event */
4532         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP,
4533                               GFX_10_1__SRCID__CP_EOP_INTERRUPT,
4534                               &adev->gfx.eop_irq);
4535         if (r)
4536                 return r;
4537
4538         /* Privileged reg */
4539         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_10_1__SRCID__CP_PRIV_REG_FAULT,
4540                               &adev->gfx.priv_reg_irq);
4541         if (r)
4542                 return r;
4543
4544         /* Privileged inst */
4545         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_10_1__SRCID__CP_PRIV_INSTR_FAULT,
4546                               &adev->gfx.priv_inst_irq);
4547         if (r)
4548                 return r;
4549
4550         adev->gfx.gfx_current_status = AMDGPU_GFX_NORMAL_MODE;
4551
4552         gfx_v10_0_scratch_init(adev);
4553
4554         r = gfx_v10_0_me_init(adev);
4555         if (r)
4556                 return r;
4557
4558         r = gfx_v10_0_rlc_init(adev);
4559         if (r) {
4560                 DRM_ERROR("Failed to init rlc BOs!\n");
4561                 return r;
4562         }
4563
4564         r = gfx_v10_0_mec_init(adev);
4565         if (r) {
4566                 DRM_ERROR("Failed to init MEC BOs!\n");
4567                 return r;
4568         }
4569
4570         /* set up the gfx ring */
4571         for (i = 0; i < adev->gfx.me.num_me; i++) {
4572                 for (j = 0; j < adev->gfx.me.num_queue_per_pipe; j++) {
4573                         for (k = 0; k < adev->gfx.me.num_pipe_per_me; k++) {
4574                                 if (!amdgpu_gfx_is_me_queue_enabled(adev, i, k, j))
4575                                         continue;
4576
4577                                 r = gfx_v10_0_gfx_ring_init(adev, ring_id,
4578                                                             i, k, j);
4579                                 if (r)
4580                                         return r;
4581                                 ring_id++;
4582                         }
4583                 }
4584         }
4585
4586         ring_id = 0;
4587         /* set up the compute queues - allocate horizontally across pipes */
4588         for (i = 0; i < adev->gfx.mec.num_mec; ++i) {
4589                 for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) {
4590                         for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) {
4591                                 if (!amdgpu_gfx_is_mec_queue_enabled(adev, i, k,
4592                                                                      j))
4593                                         continue;
4594
4595                                 r = gfx_v10_0_compute_ring_init(adev, ring_id,
4596                                                                 i, k, j);
4597                                 if (r)
4598                                         return r;
4599
4600                                 ring_id++;
4601                         }
4602                 }
4603         }
4604
4605         r = amdgpu_gfx_kiq_init(adev, GFX10_MEC_HPD_SIZE);
4606         if (r) {
4607                 DRM_ERROR("Failed to init KIQ BOs!\n");
4608                 return r;
4609         }
4610
4611         kiq = &adev->gfx.kiq;
4612         r = amdgpu_gfx_kiq_init_ring(adev, &kiq->ring, &kiq->irq);
4613         if (r)
4614                 return r;
4615
4616         r = amdgpu_gfx_mqd_sw_init(adev, sizeof(struct v10_compute_mqd));
4617         if (r)
4618                 return r;
4619
4620         /* allocate visible FB for rlc auto-loading fw */
4621         if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) {
4622                 r = gfx_v10_0_rlc_backdoor_autoload_buffer_init(adev);
4623                 if (r)
4624                         return r;
4625         }
4626
4627         adev->gfx.ce_ram_size = F32_CE_PROGRAM_RAM_SIZE;
4628
4629         gfx_v10_0_gpu_early_init(adev);
4630
4631         return 0;
4632 }
4633
4634 static void gfx_v10_0_pfp_fini(struct amdgpu_device *adev)
4635 {
4636         amdgpu_bo_free_kernel(&adev->gfx.pfp.pfp_fw_obj,
4637                               &adev->gfx.pfp.pfp_fw_gpu_addr,
4638                               (void **)&adev->gfx.pfp.pfp_fw_ptr);
4639 }
4640
4641 static void gfx_v10_0_ce_fini(struct amdgpu_device *adev)
4642 {
4643         amdgpu_bo_free_kernel(&adev->gfx.ce.ce_fw_obj,
4644                               &adev->gfx.ce.ce_fw_gpu_addr,
4645                               (void **)&adev->gfx.ce.ce_fw_ptr);
4646 }
4647
4648 static void gfx_v10_0_me_fini(struct amdgpu_device *adev)
4649 {
4650         amdgpu_bo_free_kernel(&adev->gfx.me.me_fw_obj,
4651                               &adev->gfx.me.me_fw_gpu_addr,
4652                               (void **)&adev->gfx.me.me_fw_ptr);
4653 }
4654
4655 static int gfx_v10_0_sw_fini(void *handle)
4656 {
4657         int i;
4658         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4659
4660         for (i = 0; i < adev->gfx.num_gfx_rings; i++)
4661                 amdgpu_ring_fini(&adev->gfx.gfx_ring[i]);
4662         for (i = 0; i < adev->gfx.num_compute_rings; i++)
4663                 amdgpu_ring_fini(&adev->gfx.compute_ring[i]);
4664
4665         amdgpu_gfx_mqd_sw_fini(adev);
4666         amdgpu_gfx_kiq_free_ring(&adev->gfx.kiq.ring);
4667         amdgpu_gfx_kiq_fini(adev);
4668
4669         gfx_v10_0_pfp_fini(adev);
4670         gfx_v10_0_ce_fini(adev);
4671         gfx_v10_0_me_fini(adev);
4672         gfx_v10_0_rlc_fini(adev);
4673         gfx_v10_0_mec_fini(adev);
4674
4675         if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO)
4676                 gfx_v10_0_rlc_backdoor_autoload_buffer_fini(adev);
4677
4678         gfx_v10_0_free_microcode(adev);
4679
4680         return 0;
4681 }
4682
4683 static void gfx_v10_0_select_se_sh(struct amdgpu_device *adev, u32 se_num,
4684                                    u32 sh_num, u32 instance)
4685 {
4686         u32 data;
4687
4688         if (instance == 0xffffffff)
4689                 data = REG_SET_FIELD(0, GRBM_GFX_INDEX,
4690                                      INSTANCE_BROADCAST_WRITES, 1);
4691         else
4692                 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_INDEX,
4693                                      instance);
4694
4695         if (se_num == 0xffffffff)
4696                 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_BROADCAST_WRITES,
4697                                      1);
4698         else
4699                 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num);
4700
4701         if (sh_num == 0xffffffff)
4702                 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SA_BROADCAST_WRITES,
4703                                      1);
4704         else
4705                 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SA_INDEX, sh_num);
4706
4707         WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, data);
4708 }
4709
4710 static u32 gfx_v10_0_get_rb_active_bitmap(struct amdgpu_device *adev)
4711 {
4712         u32 data, mask;
4713
4714         data = RREG32_SOC15(GC, 0, mmCC_RB_BACKEND_DISABLE);
4715         data |= RREG32_SOC15(GC, 0, mmGC_USER_RB_BACKEND_DISABLE);
4716
4717         data &= CC_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK;
4718         data >>= GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT;
4719
4720         mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_backends_per_se /
4721                                          adev->gfx.config.max_sh_per_se);
4722
4723         return (~data) & mask;
4724 }
4725
4726 static void gfx_v10_0_setup_rb(struct amdgpu_device *adev)
4727 {
4728         int i, j;
4729         u32 data;
4730         u32 active_rbs = 0;
4731         u32 bitmap;
4732         u32 rb_bitmap_width_per_sh = adev->gfx.config.max_backends_per_se /
4733                                         adev->gfx.config.max_sh_per_se;
4734
4735         mutex_lock(&adev->grbm_idx_mutex);
4736         for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
4737                 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
4738                         bitmap = i * adev->gfx.config.max_sh_per_se + j;
4739                         if ((adev->asic_type == CHIP_SIENNA_CICHLID) &&
4740                             ((gfx_v10_3_get_disabled_sa(adev) >> bitmap) & 1))
4741                                 continue;
4742                         gfx_v10_0_select_se_sh(adev, i, j, 0xffffffff);
4743                         data = gfx_v10_0_get_rb_active_bitmap(adev);
4744                         active_rbs |= data << ((i * adev->gfx.config.max_sh_per_se + j) *
4745                                                rb_bitmap_width_per_sh);
4746                 }
4747         }
4748         gfx_v10_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
4749         mutex_unlock(&adev->grbm_idx_mutex);
4750
4751         adev->gfx.config.backend_enable_mask = active_rbs;
4752         adev->gfx.config.num_rbs = hweight32(active_rbs);
4753 }
4754
4755 static u32 gfx_v10_0_init_pa_sc_tile_steering_override(struct amdgpu_device *adev)
4756 {
4757         uint32_t num_sc;
4758         uint32_t enabled_rb_per_sh;
4759         uint32_t active_rb_bitmap;
4760         uint32_t num_rb_per_sc;
4761         uint32_t num_packer_per_sc;
4762         uint32_t pa_sc_tile_steering_override;
4763
4764         /* for ASICs that integrates GFX v10.3
4765          * pa_sc_tile_steering_override should be set to 0 */
4766         if (adev->asic_type >= CHIP_SIENNA_CICHLID)
4767                 return 0;
4768
4769         /* init num_sc */
4770         num_sc = adev->gfx.config.max_shader_engines * adev->gfx.config.max_sh_per_se *
4771                         adev->gfx.config.num_sc_per_sh;
4772         /* init num_rb_per_sc */
4773         active_rb_bitmap = gfx_v10_0_get_rb_active_bitmap(adev);
4774         enabled_rb_per_sh = hweight32(active_rb_bitmap);
4775         num_rb_per_sc = enabled_rb_per_sh / adev->gfx.config.num_sc_per_sh;
4776         /* init num_packer_per_sc */
4777         num_packer_per_sc = adev->gfx.config.num_packer_per_sc;
4778
4779         pa_sc_tile_steering_override = 0;
4780         pa_sc_tile_steering_override |=
4781                 (order_base_2(num_sc) << PA_SC_TILE_STEERING_OVERRIDE__NUM_SC__SHIFT) &
4782                 PA_SC_TILE_STEERING_OVERRIDE__NUM_SC_MASK;
4783         pa_sc_tile_steering_override |=
4784                 (order_base_2(num_rb_per_sc) << PA_SC_TILE_STEERING_OVERRIDE__NUM_RB_PER_SC__SHIFT) &
4785                 PA_SC_TILE_STEERING_OVERRIDE__NUM_RB_PER_SC_MASK;
4786         pa_sc_tile_steering_override |=
4787                 (order_base_2(num_packer_per_sc) << PA_SC_TILE_STEERING_OVERRIDE__NUM_PACKER_PER_SC__SHIFT) &
4788                 PA_SC_TILE_STEERING_OVERRIDE__NUM_PACKER_PER_SC_MASK;
4789
4790         return pa_sc_tile_steering_override;
4791 }
4792
4793 #define DEFAULT_SH_MEM_BASES    (0x6000)
4794
4795 static void gfx_v10_0_init_compute_vmid(struct amdgpu_device *adev)
4796 {
4797         int i;
4798         uint32_t sh_mem_bases;
4799
4800         /*
4801          * Configure apertures:
4802          * LDS:         0x60000000'00000000 - 0x60000001'00000000 (4GB)
4803          * Scratch:     0x60000001'00000000 - 0x60000002'00000000 (4GB)
4804          * GPUVM:       0x60010000'00000000 - 0x60020000'00000000 (1TB)
4805          */
4806         sh_mem_bases = DEFAULT_SH_MEM_BASES | (DEFAULT_SH_MEM_BASES << 16);
4807
4808         mutex_lock(&adev->srbm_mutex);
4809         for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) {
4810                 nv_grbm_select(adev, 0, 0, 0, i);
4811                 /* CP and shaders */
4812                 WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, DEFAULT_SH_MEM_CONFIG);
4813                 WREG32_SOC15(GC, 0, mmSH_MEM_BASES, sh_mem_bases);
4814         }
4815         nv_grbm_select(adev, 0, 0, 0, 0);
4816         mutex_unlock(&adev->srbm_mutex);
4817
4818         /* Initialize all compute VMIDs to have no GDS, GWS, or OA
4819            acccess. These should be enabled by FW for target VMIDs. */
4820         for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) {
4821                 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_BASE, 2 * i, 0);
4822                 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_SIZE, 2 * i, 0);
4823                 WREG32_SOC15_OFFSET(GC, 0, mmGDS_GWS_VMID0, i, 0);
4824                 WREG32_SOC15_OFFSET(GC, 0, mmGDS_OA_VMID0, i, 0);
4825         }
4826 }
4827
4828 static void gfx_v10_0_init_gds_vmid(struct amdgpu_device *adev)
4829 {
4830         int vmid;
4831
4832         /*
4833          * Initialize all compute and user-gfx VMIDs to have no GDS, GWS, or OA
4834          * access. Compute VMIDs should be enabled by FW for target VMIDs,
4835          * the driver can enable them for graphics. VMID0 should maintain
4836          * access so that HWS firmware can save/restore entries.
4837          */
4838         for (vmid = 1; vmid < 16; vmid++) {
4839                 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_BASE, 2 * vmid, 0);
4840                 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_SIZE, 2 * vmid, 0);
4841                 WREG32_SOC15_OFFSET(GC, 0, mmGDS_GWS_VMID0, vmid, 0);
4842                 WREG32_SOC15_OFFSET(GC, 0, mmGDS_OA_VMID0, vmid, 0);
4843         }
4844 }
4845
4846
4847 static void gfx_v10_0_tcp_harvest(struct amdgpu_device *adev)
4848 {
4849         int i, j, k;
4850         int max_wgp_per_sh = adev->gfx.config.max_cu_per_sh >> 1;
4851         u32 tmp, wgp_active_bitmap = 0;
4852         u32 gcrd_targets_disable_tcp = 0;
4853         u32 utcl_invreq_disable = 0;
4854         /*
4855          * GCRD_TARGETS_DISABLE field contains
4856          * for Navi10/Navi12: GL1C=[18:15], SQC=[14:10], TCP=[9:0]
4857          * for Navi14: GL1C=[21:18], SQC=[17:12], TCP=[11:0]
4858          */
4859         u32 gcrd_targets_disable_mask = amdgpu_gfx_create_bitmask(
4860                 2 * max_wgp_per_sh + /* TCP */
4861                 max_wgp_per_sh + /* SQC */
4862                 4); /* GL1C */
4863         /*
4864          * UTCL1_UTCL0_INVREQ_DISABLE field contains
4865          * for Navi10Navi12: SQG=[24], RMI=[23:20], SQC=[19:10], TCP=[9:0]
4866          * for Navi14: SQG=[28], RMI=[27:24], SQC=[23:12], TCP=[11:0]
4867          */
4868         u32 utcl_invreq_disable_mask = amdgpu_gfx_create_bitmask(
4869                 2 * max_wgp_per_sh + /* TCP */
4870                 2 * max_wgp_per_sh + /* SQC */
4871                 4 + /* RMI */
4872                 1); /* SQG */
4873
4874         if (adev->asic_type == CHIP_NAVI10 ||
4875             adev->asic_type == CHIP_NAVI14 ||
4876             adev->asic_type == CHIP_NAVI12) {
4877                 mutex_lock(&adev->grbm_idx_mutex);
4878                 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
4879                         for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
4880                                 gfx_v10_0_select_se_sh(adev, i, j, 0xffffffff);
4881                                 wgp_active_bitmap = gfx_v10_0_get_wgp_active_bitmap_per_sh(adev);
4882                                 /*
4883                                  * Set corresponding TCP bits for the inactive WGPs in
4884                                  * GCRD_SA_TARGETS_DISABLE
4885                                  */
4886                                 gcrd_targets_disable_tcp = 0;
4887                                 /* Set TCP & SQC bits in UTCL1_UTCL0_INVREQ_DISABLE */
4888                                 utcl_invreq_disable = 0;
4889
4890                                 for (k = 0; k < max_wgp_per_sh; k++) {
4891                                         if (!(wgp_active_bitmap & (1 << k))) {
4892                                                 gcrd_targets_disable_tcp |= 3 << (2 * k);
4893                                                 utcl_invreq_disable |= (3 << (2 * k)) |
4894                                                         (3 << (2 * (max_wgp_per_sh + k)));
4895                                         }
4896                                 }
4897
4898                                 tmp = RREG32_SOC15(GC, 0, mmUTCL1_UTCL0_INVREQ_DISABLE);
4899                                 /* only override TCP & SQC bits */
4900                                 tmp &= 0xffffffff << (4 * max_wgp_per_sh);
4901                                 tmp |= (utcl_invreq_disable & utcl_invreq_disable_mask);
4902                                 WREG32_SOC15(GC, 0, mmUTCL1_UTCL0_INVREQ_DISABLE, tmp);
4903
4904                                 tmp = RREG32_SOC15(GC, 0, mmGCRD_SA_TARGETS_DISABLE);
4905                                 /* only override TCP bits */
4906                                 tmp &= 0xffffffff << (2 * max_wgp_per_sh);
4907                                 tmp |= (gcrd_targets_disable_tcp & gcrd_targets_disable_mask);
4908                                 WREG32_SOC15(GC, 0, mmGCRD_SA_TARGETS_DISABLE, tmp);
4909                         }
4910                 }
4911
4912                 gfx_v10_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
4913                 mutex_unlock(&adev->grbm_idx_mutex);
4914         }
4915 }
4916
4917 static void gfx_v10_0_get_tcc_info(struct amdgpu_device *adev)
4918 {
4919         /* TCCs are global (not instanced). */
4920         uint32_t tcc_disable = RREG32_SOC15(GC, 0, mmCGTS_TCC_DISABLE) |
4921                                RREG32_SOC15(GC, 0, mmCGTS_USER_TCC_DISABLE);
4922
4923         adev->gfx.config.tcc_disabled_mask =
4924                 REG_GET_FIELD(tcc_disable, CGTS_TCC_DISABLE, TCC_DISABLE) |
4925                 (REG_GET_FIELD(tcc_disable, CGTS_TCC_DISABLE, HI_TCC_DISABLE) << 16);
4926 }
4927
4928 static void gfx_v10_0_constants_init(struct amdgpu_device *adev)
4929 {
4930         u32 tmp;
4931         int i;
4932
4933         WREG32_FIELD15(GC, 0, GRBM_CNTL, READ_TIMEOUT, 0xff);
4934
4935         gfx_v10_0_setup_rb(adev);
4936         gfx_v10_0_get_cu_info(adev, &adev->gfx.cu_info);
4937         gfx_v10_0_get_tcc_info(adev);
4938         adev->gfx.config.pa_sc_tile_steering_override =
4939                 gfx_v10_0_init_pa_sc_tile_steering_override(adev);
4940
4941         /* XXX SH_MEM regs */
4942         /* where to put LDS, scratch, GPUVM in FSA64 space */
4943         mutex_lock(&adev->srbm_mutex);
4944         for (i = 0; i < adev->vm_manager.id_mgr[AMDGPU_GFXHUB_0].num_ids; i++) {
4945                 nv_grbm_select(adev, 0, 0, 0, i);
4946                 /* CP and shaders */
4947                 WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, DEFAULT_SH_MEM_CONFIG);
4948                 if (i != 0) {
4949                         tmp = REG_SET_FIELD(0, SH_MEM_BASES, PRIVATE_BASE,
4950                                 (adev->gmc.private_aperture_start >> 48));
4951                         tmp = REG_SET_FIELD(tmp, SH_MEM_BASES, SHARED_BASE,
4952                                 (adev->gmc.shared_aperture_start >> 48));
4953                         WREG32_SOC15(GC, 0, mmSH_MEM_BASES, tmp);
4954                 }
4955         }
4956         nv_grbm_select(adev, 0, 0, 0, 0);
4957
4958         mutex_unlock(&adev->srbm_mutex);
4959
4960         gfx_v10_0_init_compute_vmid(adev);
4961         gfx_v10_0_init_gds_vmid(adev);
4962
4963 }
4964
4965 static void gfx_v10_0_enable_gui_idle_interrupt(struct amdgpu_device *adev,
4966                                                bool enable)
4967 {
4968         u32 tmp;
4969
4970         if (amdgpu_sriov_vf(adev))
4971                 return;
4972
4973         tmp = RREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0);
4974
4975         tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE,
4976                             enable ? 1 : 0);
4977         tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE,
4978                             enable ? 1 : 0);
4979         tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE,
4980                             enable ? 1 : 0);
4981         tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, GFX_IDLE_INT_ENABLE,
4982                             enable ? 1 : 0);
4983
4984         WREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0, tmp);
4985 }
4986
4987 static int gfx_v10_0_init_csb(struct amdgpu_device *adev)
4988 {
4989         adev->gfx.rlc.funcs->get_csb_buffer(adev, adev->gfx.rlc.cs_ptr);
4990
4991         /* csib */
4992         if (adev->asic_type == CHIP_NAVI12) {
4993                 WREG32_SOC15_RLC(GC, 0, mmRLC_CSIB_ADDR_HI,
4994                                 adev->gfx.rlc.clear_state_gpu_addr >> 32);
4995                 WREG32_SOC15_RLC(GC, 0, mmRLC_CSIB_ADDR_LO,
4996                                 adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc);
4997                 WREG32_SOC15_RLC(GC, 0, mmRLC_CSIB_LENGTH, adev->gfx.rlc.clear_state_size);
4998         } else {
4999                 WREG32_SOC15(GC, 0, mmRLC_CSIB_ADDR_HI,
5000                                 adev->gfx.rlc.clear_state_gpu_addr >> 32);
5001                 WREG32_SOC15(GC, 0, mmRLC_CSIB_ADDR_LO,
5002                                 adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc);
5003                 WREG32_SOC15(GC, 0, mmRLC_CSIB_LENGTH, adev->gfx.rlc.clear_state_size);
5004         }
5005         return 0;
5006 }
5007
5008 void gfx_v10_0_rlc_stop(struct amdgpu_device *adev)
5009 {
5010         u32 tmp = RREG32_SOC15(GC, 0, mmRLC_CNTL);
5011
5012         tmp = REG_SET_FIELD(tmp, RLC_CNTL, RLC_ENABLE_F32, 0);
5013         WREG32_SOC15(GC, 0, mmRLC_CNTL, tmp);
5014 }
5015
5016 static void gfx_v10_0_rlc_reset(struct amdgpu_device *adev)
5017 {
5018         WREG32_FIELD15(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 1);
5019         udelay(50);
5020         WREG32_FIELD15(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 0);
5021         udelay(50);
5022 }
5023
5024 static void gfx_v10_0_rlc_smu_handshake_cntl(struct amdgpu_device *adev,
5025                                              bool enable)
5026 {
5027         uint32_t rlc_pg_cntl;
5028
5029         rlc_pg_cntl = RREG32_SOC15(GC, 0, mmRLC_PG_CNTL);
5030
5031         if (!enable) {
5032                 /* RLC_PG_CNTL[23] = 0 (default)
5033                  * RLC will wait for handshake acks with SMU
5034                  * GFXOFF will be enabled
5035                  * RLC_PG_CNTL[23] = 1
5036                  * RLC will not issue any message to SMU
5037                  * hence no handshake between SMU & RLC
5038                  * GFXOFF will be disabled
5039                  */
5040                 rlc_pg_cntl |= 0x800000;
5041         } else
5042                 rlc_pg_cntl &= ~0x800000;
5043         WREG32_SOC15(GC, 0, mmRLC_PG_CNTL, rlc_pg_cntl);
5044 }
5045
5046 static void gfx_v10_0_rlc_start(struct amdgpu_device *adev)
5047 {
5048         /* TODO: enable rlc & smu handshake until smu
5049          * and gfxoff feature works as expected */
5050         if (!(amdgpu_pp_feature_mask & PP_GFXOFF_MASK))
5051                 gfx_v10_0_rlc_smu_handshake_cntl(adev, false);
5052
5053         WREG32_FIELD15(GC, 0, RLC_CNTL, RLC_ENABLE_F32, 1);
5054         udelay(50);
5055 }
5056
5057 static void gfx_v10_0_rlc_enable_srm(struct amdgpu_device *adev)
5058 {
5059         uint32_t tmp;
5060
5061         /* enable Save Restore Machine */
5062         tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_CNTL));
5063         tmp |= RLC_SRM_CNTL__AUTO_INCR_ADDR_MASK;
5064         tmp |= RLC_SRM_CNTL__SRM_ENABLE_MASK;
5065         WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_CNTL), tmp);
5066 }
5067
5068 static int gfx_v10_0_rlc_load_microcode(struct amdgpu_device *adev)
5069 {
5070         const struct rlc_firmware_header_v2_0 *hdr;
5071         const __le32 *fw_data;
5072         unsigned i, fw_size;
5073
5074         if (!adev->gfx.rlc_fw)
5075                 return -EINVAL;
5076
5077         hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data;
5078         amdgpu_ucode_print_rlc_hdr(&hdr->header);
5079
5080         fw_data = (const __le32 *)(adev->gfx.rlc_fw->data +
5081                            le32_to_cpu(hdr->header.ucode_array_offset_bytes));
5082         fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
5083
5084         WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_ADDR,
5085                      RLCG_UCODE_LOADING_START_ADDRESS);
5086
5087         for (i = 0; i < fw_size; i++)
5088                 WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_DATA,
5089                              le32_to_cpup(fw_data++));
5090
5091         WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_ADDR, adev->gfx.rlc_fw_version);
5092
5093         return 0;
5094 }
5095
5096 static int gfx_v10_0_rlc_resume(struct amdgpu_device *adev)
5097 {
5098         int r;
5099
5100         if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
5101
5102                 r = gfx_v10_0_wait_for_rlc_autoload_complete(adev);
5103                 if (r)
5104                         return r;
5105
5106                 gfx_v10_0_init_csb(adev);
5107
5108                 if (!amdgpu_sriov_vf(adev)) /* enable RLC SRM */
5109                         gfx_v10_0_rlc_enable_srm(adev);
5110         } else {
5111                 if (amdgpu_sriov_vf(adev)) {
5112                         gfx_v10_0_init_csb(adev);
5113                         return 0;
5114                 }
5115
5116                 adev->gfx.rlc.funcs->stop(adev);
5117
5118                 /* disable CG */
5119                 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, 0);
5120
5121                 /* disable PG */
5122                 WREG32_SOC15(GC, 0, mmRLC_PG_CNTL, 0);
5123
5124                 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
5125                         /* legacy rlc firmware loading */
5126                         r = gfx_v10_0_rlc_load_microcode(adev);
5127                         if (r)
5128                                 return r;
5129                 } else if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) {
5130                         /* rlc backdoor autoload firmware */
5131                         r = gfx_v10_0_rlc_backdoor_autoload_enable(adev);
5132                         if (r)
5133                                 return r;
5134                 }
5135
5136                 gfx_v10_0_init_csb(adev);
5137
5138                 adev->gfx.rlc.funcs->start(adev);
5139
5140                 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) {
5141                         r = gfx_v10_0_wait_for_rlc_autoload_complete(adev);
5142                         if (r)
5143                                 return r;
5144                 }
5145         }
5146         return 0;
5147 }
5148
5149 static struct {
5150         FIRMWARE_ID     id;
5151         unsigned int    offset;
5152         unsigned int    size;
5153 } rlc_autoload_info[FIRMWARE_ID_MAX];
5154
5155 static int gfx_v10_0_parse_rlc_toc(struct amdgpu_device *adev)
5156 {
5157         int ret;
5158         RLC_TABLE_OF_CONTENT *rlc_toc;
5159
5160         ret = amdgpu_bo_create_reserved(adev, adev->psp.toc_bin_size, PAGE_SIZE,
5161                                         AMDGPU_GEM_DOMAIN_GTT,
5162                                         &adev->gfx.rlc.rlc_toc_bo,
5163                                         &adev->gfx.rlc.rlc_toc_gpu_addr,
5164                                         (void **)&adev->gfx.rlc.rlc_toc_buf);
5165         if (ret) {
5166                 dev_err(adev->dev, "(%d) failed to create rlc toc bo\n", ret);
5167                 return ret;
5168         }
5169
5170         /* Copy toc from psp sos fw to rlc toc buffer */
5171         memcpy(adev->gfx.rlc.rlc_toc_buf, adev->psp.toc_start_addr, adev->psp.toc_bin_size);
5172
5173         rlc_toc = (RLC_TABLE_OF_CONTENT *)adev->gfx.rlc.rlc_toc_buf;
5174         while (rlc_toc && (rlc_toc->id > FIRMWARE_ID_INVALID) &&
5175                 (rlc_toc->id < FIRMWARE_ID_MAX)) {
5176                 if ((rlc_toc->id >= FIRMWARE_ID_CP_CE) &&
5177                     (rlc_toc->id <= FIRMWARE_ID_CP_MES)) {
5178                         /* Offset needs 4KB alignment */
5179                         rlc_toc->offset = ALIGN(rlc_toc->offset * 4, PAGE_SIZE);
5180                 }
5181
5182                 rlc_autoload_info[rlc_toc->id].id = rlc_toc->id;
5183                 rlc_autoload_info[rlc_toc->id].offset = rlc_toc->offset * 4;
5184                 rlc_autoload_info[rlc_toc->id].size = rlc_toc->size * 4;
5185
5186                 rlc_toc++;
5187         }
5188
5189         return 0;
5190 }
5191
5192 static uint32_t gfx_v10_0_calc_toc_total_size(struct amdgpu_device *adev)
5193 {
5194         uint32_t total_size = 0;
5195         FIRMWARE_ID id;
5196         int ret;
5197
5198         ret = gfx_v10_0_parse_rlc_toc(adev);
5199         if (ret) {
5200                 dev_err(adev->dev, "failed to parse rlc toc\n");
5201                 return 0;
5202         }
5203
5204         for (id = FIRMWARE_ID_RLC_G_UCODE; id < FIRMWARE_ID_MAX; id++)
5205                 total_size += rlc_autoload_info[id].size;
5206
5207         /* In case the offset in rlc toc ucode is aligned */
5208         if (total_size < rlc_autoload_info[FIRMWARE_ID_MAX-1].offset)
5209                 total_size = rlc_autoload_info[FIRMWARE_ID_MAX-1].offset +
5210                                 rlc_autoload_info[FIRMWARE_ID_MAX-1].size;
5211
5212         return total_size;
5213 }
5214
5215 static int gfx_v10_0_rlc_backdoor_autoload_buffer_init(struct amdgpu_device *adev)
5216 {
5217         int r;
5218         uint32_t total_size;
5219
5220         total_size = gfx_v10_0_calc_toc_total_size(adev);
5221
5222         r = amdgpu_bo_create_reserved(adev, total_size, PAGE_SIZE,
5223                                       AMDGPU_GEM_DOMAIN_GTT,
5224                                       &adev->gfx.rlc.rlc_autoload_bo,
5225                                       &adev->gfx.rlc.rlc_autoload_gpu_addr,
5226                                       (void **)&adev->gfx.rlc.rlc_autoload_ptr);
5227         if (r) {
5228                 dev_err(adev->dev, "(%d) failed to create fw autoload bo\n", r);
5229                 return r;
5230         }
5231
5232         return 0;
5233 }
5234
5235 static void gfx_v10_0_rlc_backdoor_autoload_buffer_fini(struct amdgpu_device *adev)
5236 {
5237         amdgpu_bo_free_kernel(&adev->gfx.rlc.rlc_toc_bo,
5238                               &adev->gfx.rlc.rlc_toc_gpu_addr,
5239                               (void **)&adev->gfx.rlc.rlc_toc_buf);
5240         amdgpu_bo_free_kernel(&adev->gfx.rlc.rlc_autoload_bo,
5241                               &adev->gfx.rlc.rlc_autoload_gpu_addr,
5242                               (void **)&adev->gfx.rlc.rlc_autoload_ptr);
5243 }
5244
5245 static void gfx_v10_0_rlc_backdoor_autoload_copy_ucode(struct amdgpu_device *adev,
5246                                                        FIRMWARE_ID id,
5247                                                        const void *fw_data,
5248                                                        uint32_t fw_size)
5249 {
5250         uint32_t toc_offset;
5251         uint32_t toc_fw_size;
5252         char *ptr = adev->gfx.rlc.rlc_autoload_ptr;
5253
5254         if (id <= FIRMWARE_ID_INVALID || id >= FIRMWARE_ID_MAX)
5255                 return;
5256
5257         toc_offset = rlc_autoload_info[id].offset;
5258         toc_fw_size = rlc_autoload_info[id].size;
5259
5260         if (fw_size == 0)
5261                 fw_size = toc_fw_size;
5262
5263         if (fw_size > toc_fw_size)
5264                 fw_size = toc_fw_size;
5265
5266         memcpy(ptr + toc_offset, fw_data, fw_size);
5267
5268         if (fw_size < toc_fw_size)
5269                 memset(ptr + toc_offset + fw_size, 0, toc_fw_size - fw_size);
5270 }
5271
5272 static void gfx_v10_0_rlc_backdoor_autoload_copy_toc_ucode(struct amdgpu_device *adev)
5273 {
5274         void *data;
5275         uint32_t size;
5276
5277         data = adev->gfx.rlc.rlc_toc_buf;
5278         size = rlc_autoload_info[FIRMWARE_ID_RLC_TOC].size;
5279
5280         gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5281                                                    FIRMWARE_ID_RLC_TOC,
5282                                                    data, size);
5283 }
5284
5285 static void gfx_v10_0_rlc_backdoor_autoload_copy_gfx_ucode(struct amdgpu_device *adev)
5286 {
5287         const __le32 *fw_data;
5288         uint32_t fw_size;
5289         const struct gfx_firmware_header_v1_0 *cp_hdr;
5290         const struct rlc_firmware_header_v2_0 *rlc_hdr;
5291
5292         /* pfp ucode */
5293         cp_hdr = (const struct gfx_firmware_header_v1_0 *)
5294                 adev->gfx.pfp_fw->data;
5295         fw_data = (const __le32 *)(adev->gfx.pfp_fw->data +
5296                 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes));
5297         fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes);
5298         gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5299                                                    FIRMWARE_ID_CP_PFP,
5300                                                    fw_data, fw_size);
5301
5302         /* ce ucode */
5303         cp_hdr = (const struct gfx_firmware_header_v1_0 *)
5304                 adev->gfx.ce_fw->data;
5305         fw_data = (const __le32 *)(adev->gfx.ce_fw->data +
5306                 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes));
5307         fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes);
5308         gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5309                                                    FIRMWARE_ID_CP_CE,
5310                                                    fw_data, fw_size);
5311
5312         /* me ucode */
5313         cp_hdr = (const struct gfx_firmware_header_v1_0 *)
5314                 adev->gfx.me_fw->data;
5315         fw_data = (const __le32 *)(adev->gfx.me_fw->data +
5316                 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes));
5317         fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes);
5318         gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5319                                                    FIRMWARE_ID_CP_ME,
5320                                                    fw_data, fw_size);
5321
5322         /* rlc ucode */
5323         rlc_hdr = (const struct rlc_firmware_header_v2_0 *)
5324                 adev->gfx.rlc_fw->data;
5325         fw_data = (const __le32 *)(adev->gfx.rlc_fw->data +
5326                 le32_to_cpu(rlc_hdr->header.ucode_array_offset_bytes));
5327         fw_size = le32_to_cpu(rlc_hdr->header.ucode_size_bytes);
5328         gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5329                                                    FIRMWARE_ID_RLC_G_UCODE,
5330                                                    fw_data, fw_size);
5331
5332         /* mec1 ucode */
5333         cp_hdr = (const struct gfx_firmware_header_v1_0 *)
5334                 adev->gfx.mec_fw->data;
5335         fw_data = (const __le32 *) (adev->gfx.mec_fw->data +
5336                 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes));
5337         fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes) -
5338                 cp_hdr->jt_size * 4;
5339         gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5340                                                    FIRMWARE_ID_CP_MEC,
5341                                                    fw_data, fw_size);
5342         /* mec2 ucode is not necessary if mec2 ucode is same as mec1 */
5343 }
5344
5345 /* Temporarily put sdma part here */
5346 static void gfx_v10_0_rlc_backdoor_autoload_copy_sdma_ucode(struct amdgpu_device *adev)
5347 {
5348         const __le32 *fw_data;
5349         uint32_t fw_size;
5350         const struct sdma_firmware_header_v1_0 *sdma_hdr;
5351         int i;
5352
5353         for (i = 0; i < adev->sdma.num_instances; i++) {
5354                 sdma_hdr = (const struct sdma_firmware_header_v1_0 *)
5355                         adev->sdma.instance[i].fw->data;
5356                 fw_data = (const __le32 *) (adev->sdma.instance[i].fw->data +
5357                         le32_to_cpu(sdma_hdr->header.ucode_array_offset_bytes));
5358                 fw_size = le32_to_cpu(sdma_hdr->header.ucode_size_bytes);
5359
5360                 if (i == 0) {
5361                         gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5362                                 FIRMWARE_ID_SDMA0_UCODE, fw_data, fw_size);
5363                         gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5364                                 FIRMWARE_ID_SDMA0_JT,
5365                                 (uint32_t *)fw_data +
5366                                 sdma_hdr->jt_offset,
5367                                 sdma_hdr->jt_size * 4);
5368                 } else if (i == 1) {
5369                         gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5370                                 FIRMWARE_ID_SDMA1_UCODE, fw_data, fw_size);
5371                         gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5372                                 FIRMWARE_ID_SDMA1_JT,
5373                                 (uint32_t *)fw_data +
5374                                 sdma_hdr->jt_offset,
5375                                 sdma_hdr->jt_size * 4);
5376                 }
5377         }
5378 }
5379
5380 static int gfx_v10_0_rlc_backdoor_autoload_enable(struct amdgpu_device *adev)
5381 {
5382         uint32_t rlc_g_offset, rlc_g_size, tmp;
5383         uint64_t gpu_addr;
5384
5385         gfx_v10_0_rlc_backdoor_autoload_copy_toc_ucode(adev);
5386         gfx_v10_0_rlc_backdoor_autoload_copy_sdma_ucode(adev);
5387         gfx_v10_0_rlc_backdoor_autoload_copy_gfx_ucode(adev);
5388
5389         rlc_g_offset = rlc_autoload_info[FIRMWARE_ID_RLC_G_UCODE].offset;
5390         rlc_g_size = rlc_autoload_info[FIRMWARE_ID_RLC_G_UCODE].size;
5391         gpu_addr = adev->gfx.rlc.rlc_autoload_gpu_addr + rlc_g_offset;
5392
5393         WREG32_SOC15(GC, 0, mmRLC_HYP_BOOTLOAD_ADDR_HI, upper_32_bits(gpu_addr));
5394         WREG32_SOC15(GC, 0, mmRLC_HYP_BOOTLOAD_ADDR_LO, lower_32_bits(gpu_addr));
5395         WREG32_SOC15(GC, 0, mmRLC_HYP_BOOTLOAD_SIZE, rlc_g_size);
5396
5397         tmp = RREG32_SOC15(GC, 0, mmRLC_HYP_RESET_VECTOR);
5398         if (!(tmp & (RLC_HYP_RESET_VECTOR__COLD_BOOT_EXIT_MASK |
5399                    RLC_HYP_RESET_VECTOR__VDDGFX_EXIT_MASK))) {
5400                 DRM_ERROR("Neither COLD_BOOT_EXIT nor VDDGFX_EXIT is set\n");
5401                 return -EINVAL;
5402         }
5403
5404         tmp = RREG32_SOC15(GC, 0, mmRLC_CNTL);
5405         if (tmp & RLC_CNTL__RLC_ENABLE_F32_MASK) {
5406                 DRM_ERROR("RLC ROM should halt itself\n");
5407                 return -EINVAL;
5408         }
5409
5410         return 0;
5411 }
5412
5413 static int gfx_v10_0_rlc_backdoor_autoload_config_me_cache(struct amdgpu_device *adev)
5414 {
5415         uint32_t usec_timeout = 50000;  /* wait for 50ms */
5416         uint32_t tmp;
5417         int i;
5418         uint64_t addr;
5419
5420         /* Trigger an invalidation of the L1 instruction caches */
5421         tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL);
5422         tmp = REG_SET_FIELD(tmp, CP_ME_IC_OP_CNTL, INVALIDATE_CACHE, 1);
5423         WREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL, tmp);
5424
5425         /* Wait for invalidation complete */
5426         for (i = 0; i < usec_timeout; i++) {
5427                 tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL);
5428                 if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL,
5429                         INVALIDATE_CACHE_COMPLETE))
5430                         break;
5431                 udelay(1);
5432         }
5433
5434         if (i >= usec_timeout) {
5435                 dev_err(adev->dev, "failed to invalidate instruction cache\n");
5436                 return -EINVAL;
5437         }
5438
5439         /* Program me ucode address into intruction cache address register */
5440         addr = adev->gfx.rlc.rlc_autoload_gpu_addr +
5441                 rlc_autoload_info[FIRMWARE_ID_CP_ME].offset;
5442         WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_LO,
5443                         lower_32_bits(addr) & 0xFFFFF000);
5444         WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_HI,
5445                         upper_32_bits(addr));
5446
5447         return 0;
5448 }
5449
5450 static int gfx_v10_0_rlc_backdoor_autoload_config_ce_cache(struct amdgpu_device *adev)
5451 {
5452         uint32_t usec_timeout = 50000;  /* wait for 50ms */
5453         uint32_t tmp;
5454         int i;
5455         uint64_t addr;
5456
5457         /* Trigger an invalidation of the L1 instruction caches */
5458         tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL);
5459         tmp = REG_SET_FIELD(tmp, CP_CE_IC_OP_CNTL, INVALIDATE_CACHE, 1);
5460         WREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL, tmp);
5461
5462         /* Wait for invalidation complete */
5463         for (i = 0; i < usec_timeout; i++) {
5464                 tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL);
5465                 if (1 == REG_GET_FIELD(tmp, CP_CE_IC_OP_CNTL,
5466                         INVALIDATE_CACHE_COMPLETE))
5467                         break;
5468                 udelay(1);
5469         }
5470
5471         if (i >= usec_timeout) {
5472                 dev_err(adev->dev, "failed to invalidate instruction cache\n");
5473                 return -EINVAL;
5474         }
5475
5476         /* Program ce ucode address into intruction cache address register */
5477         addr = adev->gfx.rlc.rlc_autoload_gpu_addr +
5478                 rlc_autoload_info[FIRMWARE_ID_CP_CE].offset;
5479         WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_LO,
5480                         lower_32_bits(addr) & 0xFFFFF000);
5481         WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_HI,
5482                         upper_32_bits(addr));
5483
5484         return 0;
5485 }
5486
5487 static int gfx_v10_0_rlc_backdoor_autoload_config_pfp_cache(struct amdgpu_device *adev)
5488 {
5489         uint32_t usec_timeout = 50000;  /* wait for 50ms */
5490         uint32_t tmp;
5491         int i;
5492         uint64_t addr;
5493
5494         /* Trigger an invalidation of the L1 instruction caches */
5495         tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL);
5496         tmp = REG_SET_FIELD(tmp, CP_PFP_IC_OP_CNTL, INVALIDATE_CACHE, 1);
5497         WREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL, tmp);
5498
5499         /* Wait for invalidation complete */
5500         for (i = 0; i < usec_timeout; i++) {
5501                 tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL);
5502                 if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL,
5503                         INVALIDATE_CACHE_COMPLETE))
5504                         break;
5505                 udelay(1);
5506         }
5507
5508         if (i >= usec_timeout) {
5509                 dev_err(adev->dev, "failed to invalidate instruction cache\n");
5510                 return -EINVAL;
5511         }
5512
5513         /* Program pfp ucode address into intruction cache address register */
5514         addr = adev->gfx.rlc.rlc_autoload_gpu_addr +
5515                 rlc_autoload_info[FIRMWARE_ID_CP_PFP].offset;
5516         WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_LO,
5517                         lower_32_bits(addr) & 0xFFFFF000);
5518         WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_HI,
5519                         upper_32_bits(addr));
5520
5521         return 0;
5522 }
5523
5524 static int gfx_v10_0_rlc_backdoor_autoload_config_mec_cache(struct amdgpu_device *adev)
5525 {
5526         uint32_t usec_timeout = 50000;  /* wait for 50ms */
5527         uint32_t tmp;
5528         int i;
5529         uint64_t addr;
5530
5531         /* Trigger an invalidation of the L1 instruction caches */
5532         tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL);
5533         tmp = REG_SET_FIELD(tmp, CP_CPC_IC_OP_CNTL, INVALIDATE_CACHE, 1);
5534         WREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL, tmp);
5535
5536         /* Wait for invalidation complete */
5537         for (i = 0; i < usec_timeout; i++) {
5538                 tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL);
5539                 if (1 == REG_GET_FIELD(tmp, CP_CPC_IC_OP_CNTL,
5540                         INVALIDATE_CACHE_COMPLETE))
5541                         break;
5542                 udelay(1);
5543         }
5544
5545         if (i >= usec_timeout) {
5546                 dev_err(adev->dev, "failed to invalidate instruction cache\n");
5547                 return -EINVAL;
5548         }
5549
5550         /* Program mec1 ucode address into intruction cache address register */
5551         addr = adev->gfx.rlc.rlc_autoload_gpu_addr +
5552                 rlc_autoload_info[FIRMWARE_ID_CP_MEC].offset;
5553         WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_LO,
5554                         lower_32_bits(addr) & 0xFFFFF000);
5555         WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_HI,
5556                         upper_32_bits(addr));
5557
5558         return 0;
5559 }
5560
5561 static int gfx_v10_0_wait_for_rlc_autoload_complete(struct amdgpu_device *adev)
5562 {
5563         uint32_t cp_status;
5564         uint32_t bootload_status;
5565         int i, r;
5566
5567         for (i = 0; i < adev->usec_timeout; i++) {
5568                 cp_status = RREG32_SOC15(GC, 0, mmCP_STAT);
5569                 bootload_status = RREG32_SOC15(GC, 0, mmRLC_RLCS_BOOTLOAD_STATUS);
5570                 if ((cp_status == 0) &&
5571                     (REG_GET_FIELD(bootload_status,
5572                         RLC_RLCS_BOOTLOAD_STATUS, BOOTLOAD_COMPLETE) == 1)) {
5573                         break;
5574                 }
5575                 udelay(1);
5576         }
5577
5578         if (i >= adev->usec_timeout) {
5579                 dev_err(adev->dev, "rlc autoload: gc ucode autoload timeout\n");
5580                 return -ETIMEDOUT;
5581         }
5582
5583         if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) {
5584                 r = gfx_v10_0_rlc_backdoor_autoload_config_me_cache(adev);
5585                 if (r)
5586                         return r;
5587
5588                 r = gfx_v10_0_rlc_backdoor_autoload_config_ce_cache(adev);
5589                 if (r)
5590                         return r;
5591
5592                 r = gfx_v10_0_rlc_backdoor_autoload_config_pfp_cache(adev);
5593                 if (r)
5594                         return r;
5595
5596                 r = gfx_v10_0_rlc_backdoor_autoload_config_mec_cache(adev);
5597                 if (r)
5598                         return r;
5599         }
5600
5601         return 0;
5602 }
5603
5604 static int gfx_v10_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable)
5605 {
5606         int i;
5607         u32 tmp = RREG32_SOC15(GC, 0, mmCP_ME_CNTL);
5608
5609         tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, enable ? 0 : 1);
5610         tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, enable ? 0 : 1);
5611         tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_HALT, enable ? 0 : 1);
5612
5613         if (adev->asic_type == CHIP_NAVI12) {
5614                 WREG32_SOC15_RLC(GC, 0, mmCP_ME_CNTL, tmp);
5615         } else {
5616                 WREG32_SOC15(GC, 0, mmCP_ME_CNTL, tmp);
5617         }
5618
5619         for (i = 0; i < adev->usec_timeout; i++) {
5620                 if (RREG32_SOC15(GC, 0, mmCP_STAT) == 0)
5621                         break;
5622                 udelay(1);
5623         }
5624
5625         if (i >= adev->usec_timeout)
5626                 DRM_ERROR("failed to %s cp gfx\n", enable ? "unhalt" : "halt");
5627
5628         return 0;
5629 }
5630
5631 static int gfx_v10_0_cp_gfx_load_pfp_microcode(struct amdgpu_device *adev)
5632 {
5633         int r;
5634         const struct gfx_firmware_header_v1_0 *pfp_hdr;
5635         const __le32 *fw_data;
5636         unsigned i, fw_size;
5637         uint32_t tmp;
5638         uint32_t usec_timeout = 50000;  /* wait for 50ms */
5639
5640         pfp_hdr = (const struct gfx_firmware_header_v1_0 *)
5641                 adev->gfx.pfp_fw->data;
5642
5643         amdgpu_ucode_print_gfx_hdr(&pfp_hdr->header);
5644
5645         fw_data = (const __le32 *)(adev->gfx.pfp_fw->data +
5646                 le32_to_cpu(pfp_hdr->header.ucode_array_offset_bytes));
5647         fw_size = le32_to_cpu(pfp_hdr->header.ucode_size_bytes);
5648
5649         r = amdgpu_bo_create_reserved(adev, pfp_hdr->header.ucode_size_bytes,
5650                                       PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,
5651                                       &adev->gfx.pfp.pfp_fw_obj,
5652                                       &adev->gfx.pfp.pfp_fw_gpu_addr,
5653                                       (void **)&adev->gfx.pfp.pfp_fw_ptr);
5654         if (r) {
5655                 dev_err(adev->dev, "(%d) failed to create pfp fw bo\n", r);
5656                 gfx_v10_0_pfp_fini(adev);
5657                 return r;
5658         }
5659
5660         memcpy(adev->gfx.pfp.pfp_fw_ptr, fw_data, fw_size);
5661
5662         amdgpu_bo_kunmap(adev->gfx.pfp.pfp_fw_obj);
5663         amdgpu_bo_unreserve(adev->gfx.pfp.pfp_fw_obj);
5664
5665         /* Trigger an invalidation of the L1 instruction caches */
5666         tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL);
5667         tmp = REG_SET_FIELD(tmp, CP_PFP_IC_OP_CNTL, INVALIDATE_CACHE, 1);
5668         WREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL, tmp);
5669
5670         /* Wait for invalidation complete */
5671         for (i = 0; i < usec_timeout; i++) {
5672                 tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL);
5673                 if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL,
5674                         INVALIDATE_CACHE_COMPLETE))
5675                         break;
5676                 udelay(1);
5677         }
5678
5679         if (i >= usec_timeout) {
5680                 dev_err(adev->dev, "failed to invalidate instruction cache\n");
5681                 return -EINVAL;
5682         }
5683
5684         if (amdgpu_emu_mode == 1)
5685                 adev->nbio.funcs->hdp_flush(adev, NULL);
5686
5687         tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_CNTL);
5688         tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, VMID, 0);
5689         tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, CACHE_POLICY, 0);
5690         tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, EXE_DISABLE, 0);
5691         tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, ADDRESS_CLAMP, 1);
5692         WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_CNTL, tmp);
5693         WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_LO,
5694                 adev->gfx.pfp.pfp_fw_gpu_addr & 0xFFFFF000);
5695         WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_HI,
5696                 upper_32_bits(adev->gfx.pfp.pfp_fw_gpu_addr));
5697
5698         WREG32_SOC15(GC, 0, mmCP_HYP_PFP_UCODE_ADDR, 0);
5699
5700         for (i = 0; i < pfp_hdr->jt_size; i++)
5701                 WREG32_SOC15(GC, 0, mmCP_HYP_PFP_UCODE_DATA,
5702                              le32_to_cpup(fw_data + pfp_hdr->jt_offset + i));
5703
5704         WREG32_SOC15(GC, 0, mmCP_HYP_PFP_UCODE_ADDR, adev->gfx.pfp_fw_version);
5705
5706         return 0;
5707 }
5708
5709 static int gfx_v10_0_cp_gfx_load_ce_microcode(struct amdgpu_device *adev)
5710 {
5711         int r;
5712         const struct gfx_firmware_header_v1_0 *ce_hdr;
5713         const __le32 *fw_data;
5714         unsigned i, fw_size;
5715         uint32_t tmp;
5716         uint32_t usec_timeout = 50000;  /* wait for 50ms */
5717
5718         ce_hdr = (const struct gfx_firmware_header_v1_0 *)
5719                 adev->gfx.ce_fw->data;
5720
5721         amdgpu_ucode_print_gfx_hdr(&ce_hdr->header);
5722
5723         fw_data = (const __le32 *)(adev->gfx.ce_fw->data +
5724                 le32_to_cpu(ce_hdr->header.ucode_array_offset_bytes));
5725         fw_size = le32_to_cpu(ce_hdr->header.ucode_size_bytes);
5726
5727         r = amdgpu_bo_create_reserved(adev, ce_hdr->header.ucode_size_bytes,
5728                                       PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,
5729                                       &adev->gfx.ce.ce_fw_obj,
5730                                       &adev->gfx.ce.ce_fw_gpu_addr,
5731                                       (void **)&adev->gfx.ce.ce_fw_ptr);
5732         if (r) {
5733                 dev_err(adev->dev, "(%d) failed to create ce fw bo\n", r);
5734                 gfx_v10_0_ce_fini(adev);
5735                 return r;
5736         }
5737
5738         memcpy(adev->gfx.ce.ce_fw_ptr, fw_data, fw_size);
5739
5740         amdgpu_bo_kunmap(adev->gfx.ce.ce_fw_obj);
5741         amdgpu_bo_unreserve(adev->gfx.ce.ce_fw_obj);
5742
5743         /* Trigger an invalidation of the L1 instruction caches */
5744         tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL);
5745         tmp = REG_SET_FIELD(tmp, CP_CE_IC_OP_CNTL, INVALIDATE_CACHE, 1);
5746         WREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL, tmp);
5747
5748         /* Wait for invalidation complete */
5749         for (i = 0; i < usec_timeout; i++) {
5750                 tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL);
5751                 if (1 == REG_GET_FIELD(tmp, CP_CE_IC_OP_CNTL,
5752                         INVALIDATE_CACHE_COMPLETE))
5753                         break;
5754                 udelay(1);
5755         }
5756
5757         if (i >= usec_timeout) {
5758                 dev_err(adev->dev, "failed to invalidate instruction cache\n");
5759                 return -EINVAL;
5760         }
5761
5762         if (amdgpu_emu_mode == 1)
5763                 adev->nbio.funcs->hdp_flush(adev, NULL);
5764
5765         tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_CNTL);
5766         tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, VMID, 0);
5767         tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, CACHE_POLICY, 0);
5768         tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, EXE_DISABLE, 0);
5769         tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, ADDRESS_CLAMP, 1);
5770         WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_LO,
5771                 adev->gfx.ce.ce_fw_gpu_addr & 0xFFFFF000);
5772         WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_HI,
5773                 upper_32_bits(adev->gfx.ce.ce_fw_gpu_addr));
5774
5775         WREG32_SOC15(GC, 0, mmCP_HYP_CE_UCODE_ADDR, 0);
5776
5777         for (i = 0; i < ce_hdr->jt_size; i++)
5778                 WREG32_SOC15(GC, 0, mmCP_HYP_CE_UCODE_DATA,
5779                              le32_to_cpup(fw_data + ce_hdr->jt_offset + i));
5780
5781         WREG32_SOC15(GC, 0, mmCP_HYP_CE_UCODE_ADDR, adev->gfx.ce_fw_version);
5782
5783         return 0;
5784 }
5785
5786 static int gfx_v10_0_cp_gfx_load_me_microcode(struct amdgpu_device *adev)
5787 {
5788         int r;
5789         const struct gfx_firmware_header_v1_0 *me_hdr;
5790         const __le32 *fw_data;
5791         unsigned i, fw_size;
5792         uint32_t tmp;
5793         uint32_t usec_timeout = 50000;  /* wait for 50ms */
5794
5795         me_hdr = (const struct gfx_firmware_header_v1_0 *)
5796                 adev->gfx.me_fw->data;
5797
5798         amdgpu_ucode_print_gfx_hdr(&me_hdr->header);
5799
5800         fw_data = (const __le32 *)(adev->gfx.me_fw->data +
5801                 le32_to_cpu(me_hdr->header.ucode_array_offset_bytes));
5802         fw_size = le32_to_cpu(me_hdr->header.ucode_size_bytes);
5803
5804         r = amdgpu_bo_create_reserved(adev, me_hdr->header.ucode_size_bytes,
5805                                       PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,
5806                                       &adev->gfx.me.me_fw_obj,
5807                                       &adev->gfx.me.me_fw_gpu_addr,
5808                                       (void **)&adev->gfx.me.me_fw_ptr);
5809         if (r) {
5810                 dev_err(adev->dev, "(%d) failed to create me fw bo\n", r);
5811                 gfx_v10_0_me_fini(adev);
5812                 return r;
5813         }
5814
5815         memcpy(adev->gfx.me.me_fw_ptr, fw_data, fw_size);
5816
5817         amdgpu_bo_kunmap(adev->gfx.me.me_fw_obj);
5818         amdgpu_bo_unreserve(adev->gfx.me.me_fw_obj);
5819
5820         /* Trigger an invalidation of the L1 instruction caches */
5821         tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL);
5822         tmp = REG_SET_FIELD(tmp, CP_ME_IC_OP_CNTL, INVALIDATE_CACHE, 1);
5823         WREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL, tmp);
5824
5825         /* Wait for invalidation complete */
5826         for (i = 0; i < usec_timeout; i++) {
5827                 tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL);
5828                 if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL,
5829                         INVALIDATE_CACHE_COMPLETE))
5830                         break;
5831                 udelay(1);
5832         }
5833
5834         if (i >= usec_timeout) {
5835                 dev_err(adev->dev, "failed to invalidate instruction cache\n");
5836                 return -EINVAL;
5837         }
5838
5839         if (amdgpu_emu_mode == 1)
5840                 adev->nbio.funcs->hdp_flush(adev, NULL);
5841
5842         tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_CNTL);
5843         tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, VMID, 0);
5844         tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, CACHE_POLICY, 0);
5845         tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, EXE_DISABLE, 0);
5846         tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, ADDRESS_CLAMP, 1);
5847         WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_LO,
5848                 adev->gfx.me.me_fw_gpu_addr & 0xFFFFF000);
5849         WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_HI,
5850                 upper_32_bits(adev->gfx.me.me_fw_gpu_addr));
5851
5852         WREG32_SOC15(GC, 0, mmCP_HYP_ME_UCODE_ADDR, 0);
5853
5854         for (i = 0; i < me_hdr->jt_size; i++)
5855                 WREG32_SOC15(GC, 0, mmCP_HYP_ME_UCODE_DATA,
5856                              le32_to_cpup(fw_data + me_hdr->jt_offset + i));
5857
5858         WREG32_SOC15(GC, 0, mmCP_HYP_ME_UCODE_ADDR, adev->gfx.me_fw_version);
5859
5860         return 0;
5861 }
5862
5863 static int gfx_v10_0_cp_gfx_load_microcode(struct amdgpu_device *adev)
5864 {
5865         int r;
5866
5867         if (!adev->gfx.me_fw || !adev->gfx.pfp_fw || !adev->gfx.ce_fw)
5868                 return -EINVAL;
5869
5870         gfx_v10_0_cp_gfx_enable(adev, false);
5871
5872         r = gfx_v10_0_cp_gfx_load_pfp_microcode(adev);
5873         if (r) {
5874                 dev_err(adev->dev, "(%d) failed to load pfp fw\n", r);
5875                 return r;
5876         }
5877
5878         r = gfx_v10_0_cp_gfx_load_ce_microcode(adev);
5879         if (r) {
5880                 dev_err(adev->dev, "(%d) failed to load ce fw\n", r);
5881                 return r;
5882         }
5883
5884         r = gfx_v10_0_cp_gfx_load_me_microcode(adev);
5885         if (r) {
5886                 dev_err(adev->dev, "(%d) failed to load me fw\n", r);
5887                 return r;
5888         }
5889
5890         return 0;
5891 }
5892
5893 static int gfx_v10_0_cp_gfx_start(struct amdgpu_device *adev)
5894 {
5895         struct amdgpu_ring *ring;
5896         const struct cs_section_def *sect = NULL;
5897         const struct cs_extent_def *ext = NULL;
5898         int r, i;
5899         int ctx_reg_offset;
5900
5901         /* init the CP */
5902         WREG32_SOC15(GC, 0, mmCP_MAX_CONTEXT,
5903                      adev->gfx.config.max_hw_contexts - 1);
5904         WREG32_SOC15(GC, 0, mmCP_DEVICE_ID, 1);
5905
5906         gfx_v10_0_cp_gfx_enable(adev, true);
5907
5908         ring = &adev->gfx.gfx_ring[0];
5909         r = amdgpu_ring_alloc(ring, gfx_v10_0_get_csb_size(adev) + 4);
5910         if (r) {
5911                 DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r);
5912                 return r;
5913         }
5914
5915         amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
5916         amdgpu_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
5917
5918         amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1));
5919         amdgpu_ring_write(ring, 0x80000000);
5920         amdgpu_ring_write(ring, 0x80000000);
5921
5922         for (sect = gfx10_cs_data; sect->section != NULL; ++sect) {
5923                 for (ext = sect->section; ext->extent != NULL; ++ext) {
5924                         if (sect->id == SECT_CONTEXT) {
5925                                 amdgpu_ring_write(ring,
5926                                                   PACKET3(PACKET3_SET_CONTEXT_REG,
5927                                                           ext->reg_count));
5928                                 amdgpu_ring_write(ring, ext->reg_index -
5929                                                   PACKET3_SET_CONTEXT_REG_START);
5930                                 for (i = 0; i < ext->reg_count; i++)
5931                                         amdgpu_ring_write(ring, ext->extent[i]);
5932                         }
5933                 }
5934         }
5935
5936         ctx_reg_offset =
5937                 SOC15_REG_OFFSET(GC, 0, mmPA_SC_TILE_STEERING_OVERRIDE) - PACKET3_SET_CONTEXT_REG_START;
5938         amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
5939         amdgpu_ring_write(ring, ctx_reg_offset);
5940         amdgpu_ring_write(ring, adev->gfx.config.pa_sc_tile_steering_override);
5941
5942         amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
5943         amdgpu_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE);
5944
5945         amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));
5946         amdgpu_ring_write(ring, 0);
5947
5948         amdgpu_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2));
5949         amdgpu_ring_write(ring, PACKET3_BASE_INDEX(CE_PARTITION_BASE));
5950         amdgpu_ring_write(ring, 0x8000);
5951         amdgpu_ring_write(ring, 0x8000);
5952
5953         amdgpu_ring_commit(ring);
5954
5955         /* submit cs packet to copy state 0 to next available state */
5956         if (adev->gfx.num_gfx_rings > 1) {
5957                 /* maximum supported gfx ring is 2 */
5958                 ring = &adev->gfx.gfx_ring[1];
5959                 r = amdgpu_ring_alloc(ring, 2);
5960                 if (r) {
5961                         DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r);
5962                         return r;
5963                 }
5964
5965                 amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));
5966                 amdgpu_ring_write(ring, 0);
5967
5968                 amdgpu_ring_commit(ring);
5969         }
5970         return 0;
5971 }
5972
5973 static void gfx_v10_0_cp_gfx_switch_pipe(struct amdgpu_device *adev,
5974                                          CP_PIPE_ID pipe)
5975 {
5976         u32 tmp;
5977
5978         tmp = RREG32_SOC15(GC, 0, mmGRBM_GFX_CNTL);
5979         tmp = REG_SET_FIELD(tmp, GRBM_GFX_CNTL, PIPEID, pipe);
5980
5981         WREG32_SOC15(GC, 0, mmGRBM_GFX_CNTL, tmp);
5982 }
5983
5984 static void gfx_v10_0_cp_gfx_set_doorbell(struct amdgpu_device *adev,
5985                                           struct amdgpu_ring *ring)
5986 {
5987         u32 tmp;
5988
5989         tmp = RREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL);
5990         if (ring->use_doorbell) {
5991                 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
5992                                     DOORBELL_OFFSET, ring->doorbell_index);
5993                 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
5994                                     DOORBELL_EN, 1);
5995         } else {
5996                 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
5997                                     DOORBELL_EN, 0);
5998         }
5999         WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL, tmp);
6000         switch (adev->asic_type) {
6001         case CHIP_SIENNA_CICHLID:
6002         case CHIP_NAVY_FLOUNDER:
6003         case CHIP_VANGOGH:
6004         case CHIP_DIMGREY_CAVEFISH:
6005                 tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER,
6006                                     DOORBELL_RANGE_LOWER_Sienna_Cichlid, ring->doorbell_index);
6007                 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_LOWER, tmp);
6008
6009                 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_UPPER,
6010                              CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_Sienna_Cichlid_MASK);
6011                 break;
6012         default:
6013                 tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER,
6014                                     DOORBELL_RANGE_LOWER, ring->doorbell_index);
6015                 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_LOWER, tmp);
6016
6017                 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_UPPER,
6018                              CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_MASK);
6019                 break;
6020         }
6021 }
6022
6023 static int gfx_v10_0_cp_gfx_resume(struct amdgpu_device *adev)
6024 {
6025         struct amdgpu_ring *ring;
6026         u32 tmp;
6027         u32 rb_bufsz;
6028         u64 rb_addr, rptr_addr, wptr_gpu_addr;
6029         u32 i;
6030
6031         /* Set the write pointer delay */
6032         WREG32_SOC15(GC, 0, mmCP_RB_WPTR_DELAY, 0);
6033
6034         /* set the RB to use vmid 0 */
6035         WREG32_SOC15(GC, 0, mmCP_RB_VMID, 0);
6036
6037         /* Init gfx ring 0 for pipe 0 */
6038         mutex_lock(&adev->srbm_mutex);
6039         gfx_v10_0_cp_gfx_switch_pipe(adev, PIPE_ID0);
6040
6041         /* Set ring buffer size */
6042         ring = &adev->gfx.gfx_ring[0];
6043         rb_bufsz = order_base_2(ring->ring_size / 8);
6044         tmp = REG_SET_FIELD(0, CP_RB0_CNTL, RB_BUFSZ, rb_bufsz);
6045         tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, RB_BLKSZ, rb_bufsz - 2);
6046 #ifdef __BIG_ENDIAN
6047         tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, BUF_SWAP, 1);
6048 #endif
6049         WREG32_SOC15(GC, 0, mmCP_RB0_CNTL, tmp);
6050
6051         /* Initialize the ring buffer's write pointers */
6052         ring->wptr = 0;
6053         WREG32_SOC15(GC, 0, mmCP_RB0_WPTR, lower_32_bits(ring->wptr));
6054         WREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI, upper_32_bits(ring->wptr));
6055
6056         /* set the wb address wether it's enabled or not */
6057         rptr_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
6058         WREG32_SOC15(GC, 0, mmCP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr));
6059         WREG32_SOC15(GC, 0, mmCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) &
6060                      CP_RB_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK);
6061
6062         wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
6063         WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_LO,
6064                      lower_32_bits(wptr_gpu_addr));
6065         WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI,
6066                      upper_32_bits(wptr_gpu_addr));
6067
6068         mdelay(1);
6069         WREG32_SOC15(GC, 0, mmCP_RB0_CNTL, tmp);
6070
6071         rb_addr = ring->gpu_addr >> 8;
6072         WREG32_SOC15(GC, 0, mmCP_RB0_BASE, rb_addr);
6073         WREG32_SOC15(GC, 0, mmCP_RB0_BASE_HI, upper_32_bits(rb_addr));
6074
6075         WREG32_SOC15(GC, 0, mmCP_RB_ACTIVE, 1);
6076
6077         gfx_v10_0_cp_gfx_set_doorbell(adev, ring);
6078         mutex_unlock(&adev->srbm_mutex);
6079
6080         /* Init gfx ring 1 for pipe 1 */
6081         if (adev->gfx.num_gfx_rings > 1) {
6082                 mutex_lock(&adev->srbm_mutex);
6083                 gfx_v10_0_cp_gfx_switch_pipe(adev, PIPE_ID1);
6084                 /* maximum supported gfx ring is 2 */
6085                 ring = &adev->gfx.gfx_ring[1];
6086                 rb_bufsz = order_base_2(ring->ring_size / 8);
6087                 tmp = REG_SET_FIELD(0, CP_RB1_CNTL, RB_BUFSZ, rb_bufsz);
6088                 tmp = REG_SET_FIELD(tmp, CP_RB1_CNTL, RB_BLKSZ, rb_bufsz - 2);
6089                 WREG32_SOC15(GC, 0, mmCP_RB1_CNTL, tmp);
6090                 /* Initialize the ring buffer's write pointers */
6091                 ring->wptr = 0;
6092                 WREG32_SOC15(GC, 0, mmCP_RB1_WPTR, lower_32_bits(ring->wptr));
6093                 WREG32_SOC15(GC, 0, mmCP_RB1_WPTR_HI, upper_32_bits(ring->wptr));
6094                 /* Set the wb address wether it's enabled or not */
6095                 rptr_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
6096                 WREG32_SOC15(GC, 0, mmCP_RB1_RPTR_ADDR, lower_32_bits(rptr_addr));
6097                 WREG32_SOC15(GC, 0, mmCP_RB1_RPTR_ADDR_HI, upper_32_bits(rptr_addr) &
6098                              CP_RB1_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK);
6099                 wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
6100                 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_LO,
6101                              lower_32_bits(wptr_gpu_addr));
6102                 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI,
6103                              upper_32_bits(wptr_gpu_addr));
6104
6105                 mdelay(1);
6106                 WREG32_SOC15(GC, 0, mmCP_RB1_CNTL, tmp);
6107
6108                 rb_addr = ring->gpu_addr >> 8;
6109                 WREG32_SOC15(GC, 0, mmCP_RB1_BASE, rb_addr);
6110                 WREG32_SOC15(GC, 0, mmCP_RB1_BASE_HI, upper_32_bits(rb_addr));
6111                 WREG32_SOC15(GC, 0, mmCP_RB1_ACTIVE, 1);
6112
6113                 gfx_v10_0_cp_gfx_set_doorbell(adev, ring);
6114                 mutex_unlock(&adev->srbm_mutex);
6115         }
6116         /* Switch to pipe 0 */
6117         mutex_lock(&adev->srbm_mutex);
6118         gfx_v10_0_cp_gfx_switch_pipe(adev, PIPE_ID0);
6119         mutex_unlock(&adev->srbm_mutex);
6120
6121         /* start the ring */
6122         gfx_v10_0_cp_gfx_start(adev);
6123
6124         for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
6125                 ring = &adev->gfx.gfx_ring[i];
6126                 ring->sched.ready = true;
6127         }
6128
6129         return 0;
6130 }
6131
6132 static void gfx_v10_0_cp_compute_enable(struct amdgpu_device *adev, bool enable)
6133 {
6134         if (enable) {
6135                 switch (adev->asic_type) {
6136                 case CHIP_SIENNA_CICHLID:
6137                 case CHIP_NAVY_FLOUNDER:
6138                 case CHIP_VANGOGH:
6139                 case CHIP_DIMGREY_CAVEFISH:
6140                         WREG32_SOC15(GC, 0, mmCP_MEC_CNTL_Sienna_Cichlid, 0);
6141                         break;
6142                 default:
6143                         WREG32_SOC15(GC, 0, mmCP_MEC_CNTL, 0);
6144                         break;
6145                 }
6146         } else {
6147                 switch (adev->asic_type) {
6148                 case CHIP_SIENNA_CICHLID:
6149                 case CHIP_NAVY_FLOUNDER:
6150                 case CHIP_VANGOGH:
6151                 case CHIP_DIMGREY_CAVEFISH:
6152                         WREG32_SOC15(GC, 0, mmCP_MEC_CNTL_Sienna_Cichlid,
6153                                      (CP_MEC_CNTL__MEC_ME1_HALT_MASK |
6154                                       CP_MEC_CNTL__MEC_ME2_HALT_MASK));
6155                         break;
6156                 default:
6157                         WREG32_SOC15(GC, 0, mmCP_MEC_CNTL,
6158                                      (CP_MEC_CNTL__MEC_ME1_HALT_MASK |
6159                                       CP_MEC_CNTL__MEC_ME2_HALT_MASK));
6160                         break;
6161                 }
6162                 adev->gfx.kiq.ring.sched.ready = false;
6163         }
6164         udelay(50);
6165 }
6166
6167 static int gfx_v10_0_cp_compute_load_microcode(struct amdgpu_device *adev)
6168 {
6169         const struct gfx_firmware_header_v1_0 *mec_hdr;
6170         const __le32 *fw_data;
6171         unsigned i;
6172         u32 tmp;
6173         u32 usec_timeout = 50000; /* Wait for 50 ms */
6174
6175         if (!adev->gfx.mec_fw)
6176                 return -EINVAL;
6177
6178         gfx_v10_0_cp_compute_enable(adev, false);
6179
6180         mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
6181         amdgpu_ucode_print_gfx_hdr(&mec_hdr->header);
6182
6183         fw_data = (const __le32 *)
6184                 (adev->gfx.mec_fw->data +
6185                  le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes));
6186
6187         /* Trigger an invalidation of the L1 instruction caches */
6188         tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL);
6189         tmp = REG_SET_FIELD(tmp, CP_CPC_IC_OP_CNTL, INVALIDATE_CACHE, 1);
6190         WREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL, tmp);
6191
6192         /* Wait for invalidation complete */
6193         for (i = 0; i < usec_timeout; i++) {
6194                 tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL);
6195                 if (1 == REG_GET_FIELD(tmp, CP_CPC_IC_OP_CNTL,
6196                                        INVALIDATE_CACHE_COMPLETE))
6197                         break;
6198                 udelay(1);
6199         }
6200
6201         if (i >= usec_timeout) {
6202                 dev_err(adev->dev, "failed to invalidate instruction cache\n");
6203                 return -EINVAL;
6204         }
6205
6206         if (amdgpu_emu_mode == 1)
6207                 adev->nbio.funcs->hdp_flush(adev, NULL);
6208
6209         tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_CNTL);
6210         tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0);
6211         tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, EXE_DISABLE, 0);
6212         tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, ADDRESS_CLAMP, 1);
6213         WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_CNTL, tmp);
6214
6215         WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_LO, adev->gfx.mec.mec_fw_gpu_addr &
6216                      0xFFFFF000);
6217         WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_HI,
6218                      upper_32_bits(adev->gfx.mec.mec_fw_gpu_addr));
6219
6220         /* MEC1 */
6221         WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_ADDR, 0);
6222
6223         for (i = 0; i < mec_hdr->jt_size; i++)
6224                 WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_DATA,
6225                              le32_to_cpup(fw_data + mec_hdr->jt_offset + i));
6226
6227         WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_ADDR, adev->gfx.mec_fw_version);
6228
6229         /*
6230          * TODO: Loading MEC2 firmware is only necessary if MEC2 should run
6231          * different microcode than MEC1.
6232          */
6233
6234         return 0;
6235 }
6236
6237 static void gfx_v10_0_kiq_setting(struct amdgpu_ring *ring)
6238 {
6239         uint32_t tmp;
6240         struct amdgpu_device *adev = ring->adev;
6241
6242         /* tell RLC which is KIQ queue */
6243         switch (adev->asic_type) {
6244         case CHIP_SIENNA_CICHLID:
6245         case CHIP_NAVY_FLOUNDER:
6246         case CHIP_VANGOGH:
6247         case CHIP_DIMGREY_CAVEFISH:
6248                 tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS_Sienna_Cichlid);
6249                 tmp &= 0xffffff00;
6250                 tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue);
6251                 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS_Sienna_Cichlid, tmp);
6252                 tmp |= 0x80;
6253                 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS_Sienna_Cichlid, tmp);
6254                 break;
6255         default:
6256                 tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS);
6257                 tmp &= 0xffffff00;
6258                 tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue);
6259                 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS, tmp);
6260                 tmp |= 0x80;
6261                 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS, tmp);
6262                 break;
6263         }
6264 }
6265
6266 static int gfx_v10_0_gfx_mqd_init(struct amdgpu_ring *ring)
6267 {
6268         struct amdgpu_device *adev = ring->adev;
6269         struct v10_gfx_mqd *mqd = ring->mqd_ptr;
6270         uint64_t hqd_gpu_addr, wb_gpu_addr;
6271         uint32_t tmp;
6272         uint32_t rb_bufsz;
6273
6274         /* set up gfx hqd wptr */
6275         mqd->cp_gfx_hqd_wptr = 0;
6276         mqd->cp_gfx_hqd_wptr_hi = 0;
6277
6278         /* set the pointer to the MQD */
6279         mqd->cp_mqd_base_addr = ring->mqd_gpu_addr & 0xfffffffc;
6280         mqd->cp_mqd_base_addr_hi = upper_32_bits(ring->mqd_gpu_addr);
6281
6282         /* set up mqd control */
6283         tmp = RREG32_SOC15(GC, 0, mmCP_GFX_MQD_CONTROL);
6284         tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, VMID, 0);
6285         tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, PRIV_STATE, 1);
6286         tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, CACHE_POLICY, 0);
6287         mqd->cp_gfx_mqd_control = tmp;
6288
6289         /* set up gfx_hqd_vimd with 0x0 to indicate the ring buffer's vmid */
6290         tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_VMID);
6291         tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_VMID, VMID, 0);
6292         mqd->cp_gfx_hqd_vmid = 0;
6293
6294         /* set up default queue priority level
6295          * 0x0 = low priority, 0x1 = high priority */
6296         tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_QUEUE_PRIORITY);
6297         tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_QUEUE_PRIORITY, PRIORITY_LEVEL, 0);
6298         mqd->cp_gfx_hqd_queue_priority = tmp;
6299
6300         /* set up time quantum */
6301         tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_QUANTUM);
6302         tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_QUANTUM, QUANTUM_EN, 1);
6303         mqd->cp_gfx_hqd_quantum = tmp;
6304
6305         /* set up gfx hqd base. this is similar as CP_RB_BASE */
6306         hqd_gpu_addr = ring->gpu_addr >> 8;
6307         mqd->cp_gfx_hqd_base = hqd_gpu_addr;
6308         mqd->cp_gfx_hqd_base_hi = upper_32_bits(hqd_gpu_addr);
6309
6310         /* set up hqd_rptr_addr/_hi, similar as CP_RB_RPTR */
6311         wb_gpu_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
6312         mqd->cp_gfx_hqd_rptr_addr = wb_gpu_addr & 0xfffffffc;
6313         mqd->cp_gfx_hqd_rptr_addr_hi =
6314                 upper_32_bits(wb_gpu_addr) & 0xffff;
6315
6316         /* set up rb_wptr_poll addr */
6317         wb_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
6318         mqd->cp_rb_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc;
6319         mqd->cp_rb_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff;
6320
6321         /* set up the gfx_hqd_control, similar as CP_RB0_CNTL */
6322         rb_bufsz = order_base_2(ring->ring_size / 4) - 1;
6323         tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_CNTL);
6324         tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_BUFSZ, rb_bufsz);
6325         tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_BLKSZ, rb_bufsz - 2);
6326 #ifdef __BIG_ENDIAN
6327         tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, BUF_SWAP, 1);
6328 #endif
6329         mqd->cp_gfx_hqd_cntl = tmp;
6330
6331         /* set up cp_doorbell_control */
6332         tmp = RREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL);
6333         if (ring->use_doorbell) {
6334                 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
6335                                     DOORBELL_OFFSET, ring->doorbell_index);
6336                 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
6337                                     DOORBELL_EN, 1);
6338         } else
6339                 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
6340                                     DOORBELL_EN, 0);
6341         mqd->cp_rb_doorbell_control = tmp;
6342
6343         /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */
6344         ring->wptr = 0;
6345         mqd->cp_gfx_hqd_rptr = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_RPTR);
6346
6347         /* active the queue */
6348         mqd->cp_gfx_hqd_active = 1;
6349
6350         return 0;
6351 }
6352
6353 #ifdef BRING_UP_DEBUG
6354 static int gfx_v10_0_gfx_queue_init_register(struct amdgpu_ring *ring)
6355 {
6356         struct amdgpu_device *adev = ring->adev;
6357         struct v10_gfx_mqd *mqd = ring->mqd_ptr;
6358
6359         /* set mmCP_GFX_HQD_WPTR/_HI to 0 */
6360         WREG32_SOC15(GC, 0, mmCP_GFX_HQD_WPTR, mqd->cp_gfx_hqd_wptr);
6361         WREG32_SOC15(GC, 0, mmCP_GFX_HQD_WPTR_HI, mqd->cp_gfx_hqd_wptr_hi);
6362
6363         /* set GFX_MQD_BASE */
6364         WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR, mqd->cp_mqd_base_addr);
6365         WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR_HI, mqd->cp_mqd_base_addr_hi);
6366
6367         /* set GFX_MQD_CONTROL */
6368         WREG32_SOC15(GC, 0, mmCP_GFX_MQD_CONTROL, mqd->cp_gfx_mqd_control);
6369
6370         /* set GFX_HQD_VMID to 0 */
6371         WREG32_SOC15(GC, 0, mmCP_GFX_HQD_VMID, mqd->cp_gfx_hqd_vmid);
6372
6373         WREG32_SOC15(GC, 0, mmCP_GFX_HQD_QUEUE_PRIORITY,
6374                         mqd->cp_gfx_hqd_queue_priority);
6375         WREG32_SOC15(GC, 0, mmCP_GFX_HQD_QUANTUM, mqd->cp_gfx_hqd_quantum);
6376
6377         /* set GFX_HQD_BASE, similar as CP_RB_BASE */
6378         WREG32_SOC15(GC, 0, mmCP_GFX_HQD_BASE, mqd->cp_gfx_hqd_base);
6379         WREG32_SOC15(GC, 0, mmCP_GFX_HQD_BASE_HI, mqd->cp_gfx_hqd_base_hi);
6380
6381         /* set GFX_HQD_RPTR_ADDR, similar as CP_RB_RPTR */
6382         WREG32_SOC15(GC, 0, mmCP_GFX_HQD_RPTR_ADDR, mqd->cp_gfx_hqd_rptr_addr);
6383         WREG32_SOC15(GC, 0, mmCP_GFX_HQD_RPTR_ADDR_HI, mqd->cp_gfx_hqd_rptr_addr_hi);
6384
6385         /* set GFX_HQD_CNTL, similar as CP_RB_CNTL */
6386         WREG32_SOC15(GC, 0, mmCP_GFX_HQD_CNTL, mqd->cp_gfx_hqd_cntl);
6387
6388         /* set RB_WPTR_POLL_ADDR */
6389         WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_LO, mqd->cp_rb_wptr_poll_addr_lo);
6390         WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI, mqd->cp_rb_wptr_poll_addr_hi);
6391
6392         /* set RB_DOORBELL_CONTROL */
6393         WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL, mqd->cp_rb_doorbell_control);
6394
6395         /* active the queue */
6396         WREG32_SOC15(GC, 0, mmCP_GFX_HQD_ACTIVE, mqd->cp_gfx_hqd_active);
6397
6398         return 0;
6399 }
6400 #endif
6401
6402 static int gfx_v10_0_gfx_init_queue(struct amdgpu_ring *ring)
6403 {
6404         struct amdgpu_device *adev = ring->adev;
6405         struct v10_gfx_mqd *mqd = ring->mqd_ptr;
6406         int mqd_idx = ring - &adev->gfx.gfx_ring[0];
6407
6408         if (!amdgpu_in_reset(adev) && !adev->in_suspend) {
6409                 memset((void *)mqd, 0, sizeof(*mqd));
6410                 mutex_lock(&adev->srbm_mutex);
6411                 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
6412                 gfx_v10_0_gfx_mqd_init(ring);
6413 #ifdef BRING_UP_DEBUG
6414                 gfx_v10_0_gfx_queue_init_register(ring);
6415 #endif
6416                 nv_grbm_select(adev, 0, 0, 0, 0);
6417                 mutex_unlock(&adev->srbm_mutex);
6418                 if (adev->gfx.me.mqd_backup[mqd_idx])
6419                         memcpy(adev->gfx.me.mqd_backup[mqd_idx], mqd, sizeof(*mqd));
6420         } else if (amdgpu_in_reset(adev)) {
6421                 /* reset mqd with the backup copy */
6422                 if (adev->gfx.me.mqd_backup[mqd_idx])
6423                         memcpy(mqd, adev->gfx.me.mqd_backup[mqd_idx], sizeof(*mqd));
6424                 /* reset the ring */
6425                 ring->wptr = 0;
6426                 adev->wb.wb[ring->wptr_offs] = 0;
6427                 amdgpu_ring_clear_ring(ring);
6428 #ifdef BRING_UP_DEBUG
6429                 mutex_lock(&adev->srbm_mutex);
6430                 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
6431                 gfx_v10_0_gfx_queue_init_register(ring);
6432                 nv_grbm_select(adev, 0, 0, 0, 0);
6433                 mutex_unlock(&adev->srbm_mutex);
6434 #endif
6435         } else {
6436                 amdgpu_ring_clear_ring(ring);
6437         }
6438
6439         return 0;
6440 }
6441
6442 #ifndef BRING_UP_DEBUG
6443 static int gfx_v10_0_kiq_enable_kgq(struct amdgpu_device *adev)
6444 {
6445         struct amdgpu_kiq *kiq = &adev->gfx.kiq;
6446         struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring;
6447         int r, i;
6448
6449         if (!kiq->pmf || !kiq->pmf->kiq_map_queues)
6450                 return -EINVAL;
6451
6452         r = amdgpu_ring_alloc(kiq_ring, kiq->pmf->map_queues_size *
6453                                         adev->gfx.num_gfx_rings);
6454         if (r) {
6455                 DRM_ERROR("Failed to lock KIQ (%d).\n", r);
6456                 return r;
6457         }
6458
6459         for (i = 0; i < adev->gfx.num_gfx_rings; i++)
6460                 kiq->pmf->kiq_map_queues(kiq_ring, &adev->gfx.gfx_ring[i]);
6461
6462         return amdgpu_ring_test_helper(kiq_ring);
6463 }
6464 #endif
6465
6466 static int gfx_v10_0_cp_async_gfx_ring_resume(struct amdgpu_device *adev)
6467 {
6468         int r, i;
6469         struct amdgpu_ring *ring;
6470
6471         for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
6472                 ring = &adev->gfx.gfx_ring[i];
6473
6474                 r = amdgpu_bo_reserve(ring->mqd_obj, false);
6475                 if (unlikely(r != 0))
6476                         goto done;
6477
6478                 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr);
6479                 if (!r) {
6480                         r = gfx_v10_0_gfx_init_queue(ring);
6481                         amdgpu_bo_kunmap(ring->mqd_obj);
6482                         ring->mqd_ptr = NULL;
6483                 }
6484                 amdgpu_bo_unreserve(ring->mqd_obj);
6485                 if (r)
6486                         goto done;
6487         }
6488 #ifndef BRING_UP_DEBUG
6489         r = gfx_v10_0_kiq_enable_kgq(adev);
6490         if (r)
6491                 goto done;
6492 #endif
6493         r = gfx_v10_0_cp_gfx_start(adev);
6494         if (r)
6495                 goto done;
6496
6497         for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
6498                 ring = &adev->gfx.gfx_ring[i];
6499                 ring->sched.ready = true;
6500         }
6501 done:
6502         return r;
6503 }
6504
6505 static void gfx_v10_0_compute_mqd_set_priority(struct amdgpu_ring *ring, struct v10_compute_mqd *mqd)
6506 {
6507         struct amdgpu_device *adev = ring->adev;
6508
6509         if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) {
6510                 if (amdgpu_gfx_is_high_priority_compute_queue(adev, ring->queue)) {
6511                         mqd->cp_hqd_pipe_priority = AMDGPU_GFX_PIPE_PRIO_HIGH;
6512                         mqd->cp_hqd_queue_priority =
6513                                 AMDGPU_GFX_QUEUE_PRIORITY_MAXIMUM;
6514                 }
6515         }
6516 }
6517
6518 static int gfx_v10_0_compute_mqd_init(struct amdgpu_ring *ring)
6519 {
6520         struct amdgpu_device *adev = ring->adev;
6521         struct v10_compute_mqd *mqd = ring->mqd_ptr;
6522         uint64_t hqd_gpu_addr, wb_gpu_addr, eop_base_addr;
6523         uint32_t tmp;
6524
6525         mqd->header = 0xC0310800;
6526         mqd->compute_pipelinestat_enable = 0x00000001;
6527         mqd->compute_static_thread_mgmt_se0 = 0xffffffff;
6528         mqd->compute_static_thread_mgmt_se1 = 0xffffffff;
6529         mqd->compute_static_thread_mgmt_se2 = 0xffffffff;
6530         mqd->compute_static_thread_mgmt_se3 = 0xffffffff;
6531         mqd->compute_misc_reserved = 0x00000003;
6532
6533         eop_base_addr = ring->eop_gpu_addr >> 8;
6534         mqd->cp_hqd_eop_base_addr_lo = eop_base_addr;
6535         mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr);
6536
6537         /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */
6538         tmp = RREG32_SOC15(GC, 0, mmCP_HQD_EOP_CONTROL);
6539         tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE,
6540                         (order_base_2(GFX10_MEC_HPD_SIZE / 4) - 1));
6541
6542         mqd->cp_hqd_eop_control = tmp;
6543
6544         /* enable doorbell? */
6545         tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL);
6546
6547         if (ring->use_doorbell) {
6548                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
6549                                     DOORBELL_OFFSET, ring->doorbell_index);
6550                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
6551                                     DOORBELL_EN, 1);
6552                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
6553                                     DOORBELL_SOURCE, 0);
6554                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
6555                                     DOORBELL_HIT, 0);
6556         } else {
6557                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
6558                                     DOORBELL_EN, 0);
6559         }
6560
6561         mqd->cp_hqd_pq_doorbell_control = tmp;
6562
6563         /* disable the queue if it's active */
6564         ring->wptr = 0;
6565         mqd->cp_hqd_dequeue_request = 0;
6566         mqd->cp_hqd_pq_rptr = 0;
6567         mqd->cp_hqd_pq_wptr_lo = 0;
6568         mqd->cp_hqd_pq_wptr_hi = 0;
6569
6570         /* set the pointer to the MQD */
6571         mqd->cp_mqd_base_addr_lo = ring->mqd_gpu_addr & 0xfffffffc;
6572         mqd->cp_mqd_base_addr_hi = upper_32_bits(ring->mqd_gpu_addr);
6573
6574         /* set MQD vmid to 0 */
6575         tmp = RREG32_SOC15(GC, 0, mmCP_MQD_CONTROL);
6576         tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0);
6577         mqd->cp_mqd_control = tmp;
6578
6579         /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */
6580         hqd_gpu_addr = ring->gpu_addr >> 8;
6581         mqd->cp_hqd_pq_base_lo = hqd_gpu_addr;
6582         mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr);
6583
6584         /* set up the HQD, this is similar to CP_RB0_CNTL */
6585         tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_CONTROL);
6586         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE,
6587                             (order_base_2(ring->ring_size / 4) - 1));
6588         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE,
6589                             ((order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1) << 8));
6590 #ifdef __BIG_ENDIAN
6591         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ENDIAN_SWAP, 1);
6592 #endif
6593         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 0);
6594         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, TUNNEL_DISPATCH, 0);
6595         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1);
6596         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1);
6597         mqd->cp_hqd_pq_control = tmp;
6598
6599         /* set the wb address whether it's enabled or not */
6600         wb_gpu_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
6601         mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc;
6602         mqd->cp_hqd_pq_rptr_report_addr_hi =
6603                 upper_32_bits(wb_gpu_addr) & 0xffff;
6604
6605         /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */
6606         wb_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
6607         mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc;
6608         mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff;
6609
6610         tmp = 0;
6611         /* enable the doorbell if requested */
6612         if (ring->use_doorbell) {
6613                 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL);
6614                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
6615                                 DOORBELL_OFFSET, ring->doorbell_index);
6616
6617                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
6618                                     DOORBELL_EN, 1);
6619                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
6620                                     DOORBELL_SOURCE, 0);
6621                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
6622                                     DOORBELL_HIT, 0);
6623         }
6624
6625         mqd->cp_hqd_pq_doorbell_control = tmp;
6626
6627         /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */
6628         ring->wptr = 0;
6629         mqd->cp_hqd_pq_rptr = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR);
6630
6631         /* set the vmid for the queue */
6632         mqd->cp_hqd_vmid = 0;
6633
6634         tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PERSISTENT_STATE);
6635         tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, PRELOAD_SIZE, 0x53);
6636         mqd->cp_hqd_persistent_state = tmp;
6637
6638         /* set MIN_IB_AVAIL_SIZE */
6639         tmp = RREG32_SOC15(GC, 0, mmCP_HQD_IB_CONTROL);
6640         tmp = REG_SET_FIELD(tmp, CP_HQD_IB_CONTROL, MIN_IB_AVAIL_SIZE, 3);
6641         mqd->cp_hqd_ib_control = tmp;
6642
6643         /* set static priority for a compute queue/ring */
6644         gfx_v10_0_compute_mqd_set_priority(ring, mqd);
6645
6646         /* map_queues packet doesn't need activate the queue,
6647          * so only kiq need set this field.
6648          */
6649         if (ring->funcs->type == AMDGPU_RING_TYPE_KIQ)
6650                 mqd->cp_hqd_active = 1;
6651
6652         return 0;
6653 }
6654
6655 static int gfx_v10_0_kiq_init_register(struct amdgpu_ring *ring)
6656 {
6657         struct amdgpu_device *adev = ring->adev;
6658         struct v10_compute_mqd *mqd = ring->mqd_ptr;
6659         int j;
6660
6661         /* inactivate the queue */
6662         if (amdgpu_sriov_vf(adev))
6663                 WREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE, 0);
6664
6665         /* disable wptr polling */
6666         WREG32_FIELD15(GC, 0, CP_PQ_WPTR_POLL_CNTL, EN, 0);
6667
6668         /* write the EOP addr */
6669         WREG32_SOC15(GC, 0, mmCP_HQD_EOP_BASE_ADDR,
6670                mqd->cp_hqd_eop_base_addr_lo);
6671         WREG32_SOC15(GC, 0, mmCP_HQD_EOP_BASE_ADDR_HI,
6672                mqd->cp_hqd_eop_base_addr_hi);
6673
6674         /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */
6675         WREG32_SOC15(GC, 0, mmCP_HQD_EOP_CONTROL,
6676                mqd->cp_hqd_eop_control);
6677
6678         /* enable doorbell? */
6679         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL,
6680                mqd->cp_hqd_pq_doorbell_control);
6681
6682         /* disable the queue if it's active */
6683         if (RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1) {
6684                 WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST, 1);
6685                 for (j = 0; j < adev->usec_timeout; j++) {
6686                         if (!(RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1))
6687                                 break;
6688                         udelay(1);
6689                 }
6690                 WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST,
6691                        mqd->cp_hqd_dequeue_request);
6692                 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR,
6693                        mqd->cp_hqd_pq_rptr);
6694                 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_LO,
6695                        mqd->cp_hqd_pq_wptr_lo);
6696                 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_HI,
6697                        mqd->cp_hqd_pq_wptr_hi);
6698         }
6699
6700         /* set the pointer to the MQD */
6701         WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR,
6702                mqd->cp_mqd_base_addr_lo);
6703         WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR_HI,
6704                mqd->cp_mqd_base_addr_hi);
6705
6706         /* set MQD vmid to 0 */
6707         WREG32_SOC15(GC, 0, mmCP_MQD_CONTROL,
6708                mqd->cp_mqd_control);
6709
6710         /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */
6711         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_BASE,
6712                mqd->cp_hqd_pq_base_lo);
6713         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_BASE_HI,
6714                mqd->cp_hqd_pq_base_hi);
6715
6716         /* set up the HQD, this is similar to CP_RB0_CNTL */
6717         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_CONTROL,
6718                mqd->cp_hqd_pq_control);
6719
6720         /* set the wb address whether it's enabled or not */
6721         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR_REPORT_ADDR,
6722                 mqd->cp_hqd_pq_rptr_report_addr_lo);
6723         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI,
6724                 mqd->cp_hqd_pq_rptr_report_addr_hi);
6725
6726         /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */
6727         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR,
6728                mqd->cp_hqd_pq_wptr_poll_addr_lo);
6729         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR_HI,
6730                mqd->cp_hqd_pq_wptr_poll_addr_hi);
6731
6732         /* enable the doorbell if requested */
6733         if (ring->use_doorbell) {
6734                 WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_LOWER,
6735                         (adev->doorbell_index.kiq * 2) << 2);
6736                 WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_UPPER,
6737                         (adev->doorbell_index.userqueue_end * 2) << 2);
6738         }
6739
6740         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL,
6741                mqd->cp_hqd_pq_doorbell_control);
6742
6743         /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */
6744         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_LO,
6745                mqd->cp_hqd_pq_wptr_lo);
6746         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_HI,
6747                mqd->cp_hqd_pq_wptr_hi);
6748
6749         /* set the vmid for the queue */
6750         WREG32_SOC15(GC, 0, mmCP_HQD_VMID, mqd->cp_hqd_vmid);
6751
6752         WREG32_SOC15(GC, 0, mmCP_HQD_PERSISTENT_STATE,
6753                mqd->cp_hqd_persistent_state);
6754
6755         /* activate the queue */
6756         WREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE,
6757                mqd->cp_hqd_active);
6758
6759         if (ring->use_doorbell)
6760                 WREG32_FIELD15(GC, 0, CP_PQ_STATUS, DOORBELL_ENABLE, 1);
6761
6762         return 0;
6763 }
6764
6765 static int gfx_v10_0_kiq_init_queue(struct amdgpu_ring *ring)
6766 {
6767         struct amdgpu_device *adev = ring->adev;
6768         struct v10_compute_mqd *mqd = ring->mqd_ptr;
6769         int mqd_idx = AMDGPU_MAX_COMPUTE_RINGS;
6770
6771         gfx_v10_0_kiq_setting(ring);
6772
6773         if (amdgpu_in_reset(adev)) { /* for GPU_RESET case */
6774                 /* reset MQD to a clean status */
6775                 if (adev->gfx.mec.mqd_backup[mqd_idx])
6776                         memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(*mqd));
6777
6778                 /* reset ring buffer */
6779                 ring->wptr = 0;
6780                 amdgpu_ring_clear_ring(ring);
6781
6782                 mutex_lock(&adev->srbm_mutex);
6783                 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
6784                 gfx_v10_0_kiq_init_register(ring);
6785                 nv_grbm_select(adev, 0, 0, 0, 0);
6786                 mutex_unlock(&adev->srbm_mutex);
6787         } else {
6788                 memset((void *)mqd, 0, sizeof(*mqd));
6789                 mutex_lock(&adev->srbm_mutex);
6790                 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
6791                 gfx_v10_0_compute_mqd_init(ring);
6792                 gfx_v10_0_kiq_init_register(ring);
6793                 nv_grbm_select(adev, 0, 0, 0, 0);
6794                 mutex_unlock(&adev->srbm_mutex);
6795
6796                 if (adev->gfx.mec.mqd_backup[mqd_idx])
6797                         memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(*mqd));
6798         }
6799
6800         return 0;
6801 }
6802
6803 static int gfx_v10_0_kcq_init_queue(struct amdgpu_ring *ring)
6804 {
6805         struct amdgpu_device *adev = ring->adev;
6806         struct v10_compute_mqd *mqd = ring->mqd_ptr;
6807         int mqd_idx = ring - &adev->gfx.compute_ring[0];
6808
6809         if (!amdgpu_in_reset(adev) && !adev->in_suspend) {
6810                 memset((void *)mqd, 0, sizeof(*mqd));
6811                 mutex_lock(&adev->srbm_mutex);
6812                 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
6813                 gfx_v10_0_compute_mqd_init(ring);
6814                 nv_grbm_select(adev, 0, 0, 0, 0);
6815                 mutex_unlock(&adev->srbm_mutex);
6816
6817                 if (adev->gfx.mec.mqd_backup[mqd_idx])
6818                         memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(*mqd));
6819         } else if (amdgpu_in_reset(adev)) { /* for GPU_RESET case */
6820                 /* reset MQD to a clean status */
6821                 if (adev->gfx.mec.mqd_backup[mqd_idx])
6822                         memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(*mqd));
6823
6824                 /* reset ring buffer */
6825                 ring->wptr = 0;
6826                 atomic64_set((atomic64_t *)&adev->wb.wb[ring->wptr_offs], 0);
6827                 amdgpu_ring_clear_ring(ring);
6828         } else {
6829                 amdgpu_ring_clear_ring(ring);
6830         }
6831
6832         return 0;
6833 }
6834
6835 static int gfx_v10_0_kiq_resume(struct amdgpu_device *adev)
6836 {
6837         struct amdgpu_ring *ring;
6838         int r;
6839
6840         ring = &adev->gfx.kiq.ring;
6841
6842         r = amdgpu_bo_reserve(ring->mqd_obj, false);
6843         if (unlikely(r != 0))
6844                 return r;
6845
6846         r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr);
6847         if (unlikely(r != 0))
6848                 return r;
6849
6850         gfx_v10_0_kiq_init_queue(ring);
6851         amdgpu_bo_kunmap(ring->mqd_obj);
6852         ring->mqd_ptr = NULL;
6853         amdgpu_bo_unreserve(ring->mqd_obj);
6854         ring->sched.ready = true;
6855         return 0;
6856 }
6857
6858 static int gfx_v10_0_kcq_resume(struct amdgpu_device *adev)
6859 {
6860         struct amdgpu_ring *ring = NULL;
6861         int r = 0, i;
6862
6863         gfx_v10_0_cp_compute_enable(adev, true);
6864
6865         for (i = 0; i < adev->gfx.num_compute_rings; i++) {
6866                 ring = &adev->gfx.compute_ring[i];
6867
6868                 r = amdgpu_bo_reserve(ring->mqd_obj, false);
6869                 if (unlikely(r != 0))
6870                         goto done;
6871                 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr);
6872                 if (!r) {
6873                         r = gfx_v10_0_kcq_init_queue(ring);
6874                         amdgpu_bo_kunmap(ring->mqd_obj);
6875                         ring->mqd_ptr = NULL;
6876                 }
6877                 amdgpu_bo_unreserve(ring->mqd_obj);
6878                 if (r)
6879                         goto done;
6880         }
6881
6882         r = amdgpu_gfx_enable_kcq(adev);
6883 done:
6884         return r;
6885 }
6886
6887 static int gfx_v10_0_cp_resume(struct amdgpu_device *adev)
6888 {
6889         int r, i;
6890         struct amdgpu_ring *ring;
6891
6892         if (!(adev->flags & AMD_IS_APU))
6893                 gfx_v10_0_enable_gui_idle_interrupt(adev, false);
6894
6895         if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
6896                 /* legacy firmware loading */
6897                 r = gfx_v10_0_cp_gfx_load_microcode(adev);
6898                 if (r)
6899                         return r;
6900
6901                 r = gfx_v10_0_cp_compute_load_microcode(adev);
6902                 if (r)
6903                         return r;
6904         }
6905
6906         r = gfx_v10_0_kiq_resume(adev);
6907         if (r)
6908                 return r;
6909
6910         r = gfx_v10_0_kcq_resume(adev);
6911         if (r)
6912                 return r;
6913
6914         if (!amdgpu_async_gfx_ring) {
6915                 r = gfx_v10_0_cp_gfx_resume(adev);
6916                 if (r)
6917                         return r;
6918         } else {
6919                 r = gfx_v10_0_cp_async_gfx_ring_resume(adev);
6920                 if (r)
6921                         return r;
6922         }
6923
6924         for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
6925                 ring = &adev->gfx.gfx_ring[i];
6926                 r = amdgpu_ring_test_helper(ring);
6927                 if (r)
6928                         return r;
6929         }
6930
6931         for (i = 0; i < adev->gfx.num_compute_rings; i++) {
6932                 ring = &adev->gfx.compute_ring[i];
6933                 r = amdgpu_ring_test_helper(ring);
6934                 if (r)
6935                         return r;
6936         }
6937
6938         return 0;
6939 }
6940
6941 static void gfx_v10_0_cp_enable(struct amdgpu_device *adev, bool enable)
6942 {
6943         gfx_v10_0_cp_gfx_enable(adev, enable);
6944         gfx_v10_0_cp_compute_enable(adev, enable);
6945 }
6946
6947 static bool gfx_v10_0_check_grbm_cam_remapping(struct amdgpu_device *adev)
6948 {
6949         uint32_t data, pattern = 0xDEADBEEF;
6950
6951         /* check if mmVGT_ESGS_RING_SIZE_UMD
6952          * has been remapped to mmVGT_ESGS_RING_SIZE */
6953         switch (adev->asic_type) {
6954         case CHIP_SIENNA_CICHLID:
6955         case CHIP_NAVY_FLOUNDER:
6956         case CHIP_DIMGREY_CAVEFISH:
6957                 data = RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid);
6958                 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid, 0);
6959                 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_UMD, pattern);
6960
6961                 if (RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid) == pattern) {
6962                         WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_UMD , data);
6963                         return true;
6964                 } else {
6965                         WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid, data);
6966                         return false;
6967                 }
6968                 break;
6969         case CHIP_VANGOGH:
6970                 return true;
6971         default:
6972                 data = RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE);
6973                 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE, 0);
6974                 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_UMD, pattern);
6975
6976                 if (RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE) == pattern) {
6977                         WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_UMD, data);
6978                         return true;
6979                 } else {
6980                         WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE, data);
6981                         return false;
6982                 }
6983                 break;
6984         }
6985 }
6986
6987 static void gfx_v10_0_setup_grbm_cam_remapping(struct amdgpu_device *adev)
6988 {
6989         uint32_t data;
6990
6991         /* initialize cam_index to 0
6992          * index will auto-inc after each data writting */
6993         WREG32_SOC15(GC, 0, mmGRBM_CAM_INDEX, 0);
6994
6995         switch (adev->asic_type) {
6996         case CHIP_SIENNA_CICHLID:
6997         case CHIP_NAVY_FLOUNDER:
6998         case CHIP_VANGOGH:
6999         case CHIP_DIMGREY_CAVEFISH:
7000                 /* mmVGT_TF_RING_SIZE_UMD -> mmVGT_TF_RING_SIZE */
7001                 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE_UMD) <<
7002                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7003                        (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE_Sienna_Cichlid) <<
7004                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7005                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7006                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7007
7008                 /* mmVGT_TF_MEMORY_BASE_UMD -> mmVGT_TF_MEMORY_BASE */
7009                 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_UMD) <<
7010                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7011                        (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_Sienna_Cichlid) <<
7012                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7013                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7014                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7015
7016                 /* mmVGT_TF_MEMORY_BASE_HI_UMD -> mmVGT_TF_MEMORY_BASE_HI */
7017                 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI_UMD) <<
7018                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7019                        (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI_Sienna_Cichlid) <<
7020                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7021                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7022                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7023
7024                 /* mmVGT_HS_OFFCHIP_PARAM_UMD -> mmVGT_HS_OFFCHIP_PARAM */
7025                 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM_UMD) <<
7026                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7027                        (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM_Sienna_Cichlid) <<
7028                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7029                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7030                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7031
7032                 /* mmVGT_ESGS_RING_SIZE_UMD -> mmVGT_ESGS_RING_SIZE */
7033                 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE_UMD) <<
7034                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7035                        (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid) <<
7036                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7037                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7038                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7039
7040                 /* mmVGT_GSVS_RING_SIZE_UMD -> mmVGT_GSVS_RING_SIZE */
7041                 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE_UMD) <<
7042                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7043                        (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE_Sienna_Cichlid) <<
7044                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7045                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7046                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7047
7048                 /* mmSPI_CONFIG_CNTL_REMAP -> mmSPI_CONFIG_CNTL */
7049                 data = (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL_REMAP) <<
7050                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7051                        (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL_Sienna_Cichlid) <<
7052                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7053                 break;
7054         default:
7055                 /* mmVGT_TF_RING_SIZE_UMD -> mmVGT_TF_RING_SIZE */
7056                 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE_UMD) <<
7057                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7058                        (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE) <<
7059                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7060                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7061                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7062
7063                 /* mmVGT_TF_MEMORY_BASE_UMD -> mmVGT_TF_MEMORY_BASE */
7064                 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_UMD) <<
7065                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7066                        (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE) <<
7067                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7068                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7069                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7070
7071                 /* mmVGT_TF_MEMORY_BASE_HI_UMD -> mmVGT_TF_MEMORY_BASE_HI */
7072                 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI_UMD) <<
7073                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7074                        (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI) <<
7075                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7076                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7077                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7078
7079                 /* mmVGT_HS_OFFCHIP_PARAM_UMD -> mmVGT_HS_OFFCHIP_PARAM */
7080                 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM_UMD) <<
7081                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7082                        (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM) <<
7083                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7084                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7085                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7086
7087                 /* mmVGT_ESGS_RING_SIZE_UMD -> mmVGT_ESGS_RING_SIZE */
7088                 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE_UMD) <<
7089                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7090                        (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE) <<
7091                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7092                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7093                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7094
7095                 /* mmVGT_GSVS_RING_SIZE_UMD -> mmVGT_GSVS_RING_SIZE */
7096                 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE_UMD) <<
7097                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7098                        (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE) <<
7099                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7100                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7101                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7102
7103                 /* mmSPI_CONFIG_CNTL_REMAP -> mmSPI_CONFIG_CNTL */
7104                 data = (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL_REMAP) <<
7105                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7106                        (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL) <<
7107                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7108                 break;
7109         }
7110
7111         WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7112         WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7113 }
7114
7115 static void gfx_v10_0_disable_gpa_mode(struct amdgpu_device *adev)
7116 {
7117         uint32_t data;
7118         data = RREG32_SOC15(GC, 0, mmCPC_PSP_DEBUG);
7119         data |= CPC_PSP_DEBUG__GPA_OVERRIDE_MASK;
7120         WREG32_SOC15(GC, 0, mmCPC_PSP_DEBUG, data);
7121
7122         data = RREG32_SOC15(GC, 0, mmCPG_PSP_DEBUG);
7123         data |= CPG_PSP_DEBUG__GPA_OVERRIDE_MASK;
7124         WREG32_SOC15(GC, 0, mmCPG_PSP_DEBUG, data);
7125 }
7126
7127 static int gfx_v10_0_hw_init(void *handle)
7128 {
7129         int r;
7130         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7131
7132         if (!amdgpu_emu_mode)
7133                 gfx_v10_0_init_golden_registers(adev);
7134
7135         if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
7136                 /**
7137                  * For gfx 10, rlc firmware loading relies on smu firmware is
7138                  * loaded firstly, so in direct type, it has to load smc ucode
7139                  * here before rlc.
7140                  */
7141                 if (adev->smu.ppt_funcs != NULL && !(adev->flags & AMD_IS_APU)) {
7142                         r = smu_load_microcode(&adev->smu);
7143                         if (r)
7144                                 return r;
7145
7146                         r = smu_check_fw_status(&adev->smu);
7147                         if (r) {
7148                                 pr_err("SMC firmware status is not correct\n");
7149                                 return r;
7150                         }
7151                 }
7152                 gfx_v10_0_disable_gpa_mode(adev);
7153         }
7154
7155         /* if GRBM CAM not remapped, set up the remapping */
7156         if (!gfx_v10_0_check_grbm_cam_remapping(adev))
7157                 gfx_v10_0_setup_grbm_cam_remapping(adev);
7158
7159         gfx_v10_0_constants_init(adev);
7160
7161         r = gfx_v10_0_rlc_resume(adev);
7162         if (r)
7163                 return r;
7164
7165         /*
7166          * init golden registers and rlc resume may override some registers,
7167          * reconfig them here
7168          */
7169         gfx_v10_0_tcp_harvest(adev);
7170
7171         r = gfx_v10_0_cp_resume(adev);
7172         if (r)
7173                 return r;
7174
7175         if (adev->asic_type == CHIP_SIENNA_CICHLID)
7176                 gfx_v10_3_program_pbb_mode(adev);
7177
7178         return r;
7179 }
7180
7181 #ifndef BRING_UP_DEBUG
7182 static int gfx_v10_0_kiq_disable_kgq(struct amdgpu_device *adev)
7183 {
7184         struct amdgpu_kiq *kiq = &adev->gfx.kiq;
7185         struct amdgpu_ring *kiq_ring = &kiq->ring;
7186         int i;
7187
7188         if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues)
7189                 return -EINVAL;
7190
7191         if (amdgpu_ring_alloc(kiq_ring, kiq->pmf->unmap_queues_size *
7192                                         adev->gfx.num_gfx_rings))
7193                 return -ENOMEM;
7194
7195         for (i = 0; i < adev->gfx.num_gfx_rings; i++)
7196                 kiq->pmf->kiq_unmap_queues(kiq_ring, &adev->gfx.gfx_ring[i],
7197                                            PREEMPT_QUEUES, 0, 0);
7198
7199         return amdgpu_ring_test_helper(kiq_ring);
7200 }
7201 #endif
7202
7203 static int gfx_v10_0_hw_fini(void *handle)
7204 {
7205         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7206         int r;
7207         uint32_t tmp;
7208
7209         amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0);
7210         amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0);
7211
7212         if (!adev->in_pci_err_recovery) {
7213 #ifndef BRING_UP_DEBUG
7214                 if (amdgpu_async_gfx_ring) {
7215                         r = gfx_v10_0_kiq_disable_kgq(adev);
7216                         if (r)
7217                                 DRM_ERROR("KGQ disable failed\n");
7218                 }
7219 #endif
7220                 if (amdgpu_gfx_disable_kcq(adev))
7221                         DRM_ERROR("KCQ disable failed\n");
7222         }
7223
7224         if (amdgpu_sriov_vf(adev)) {
7225                 gfx_v10_0_cp_gfx_enable(adev, false);
7226                 /* Program KIQ position of RLC_CP_SCHEDULERS during destroy */
7227                 tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS);
7228                 tmp &= 0xffffff00;
7229                 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS, tmp);
7230
7231                 return 0;
7232         }
7233         gfx_v10_0_cp_enable(adev, false);
7234         gfx_v10_0_enable_gui_idle_interrupt(adev, false);
7235
7236         return 0;
7237 }
7238
7239 static int gfx_v10_0_suspend(void *handle)
7240 {
7241         return gfx_v10_0_hw_fini(handle);
7242 }
7243
7244 static int gfx_v10_0_resume(void *handle)
7245 {
7246         return gfx_v10_0_hw_init(handle);
7247 }
7248
7249 static bool gfx_v10_0_is_idle(void *handle)
7250 {
7251         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7252
7253         if (REG_GET_FIELD(RREG32_SOC15(GC, 0, mmGRBM_STATUS),
7254                                 GRBM_STATUS, GUI_ACTIVE))
7255                 return false;
7256         else
7257                 return true;
7258 }
7259
7260 static int gfx_v10_0_wait_for_idle(void *handle)
7261 {
7262         unsigned i;
7263         u32 tmp;
7264         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7265
7266         for (i = 0; i < adev->usec_timeout; i++) {
7267                 /* read MC_STATUS */
7268                 tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS) &
7269                         GRBM_STATUS__GUI_ACTIVE_MASK;
7270
7271                 if (!REG_GET_FIELD(tmp, GRBM_STATUS, GUI_ACTIVE))
7272                         return 0;
7273                 udelay(1);
7274         }
7275         return -ETIMEDOUT;
7276 }
7277
7278 static int gfx_v10_0_soft_reset(void *handle)
7279 {
7280         u32 grbm_soft_reset = 0;
7281         u32 tmp;
7282         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7283
7284         /* GRBM_STATUS */
7285         tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS);
7286         if (tmp & (GRBM_STATUS__PA_BUSY_MASK | GRBM_STATUS__SC_BUSY_MASK |
7287                    GRBM_STATUS__BCI_BUSY_MASK | GRBM_STATUS__SX_BUSY_MASK |
7288                    GRBM_STATUS__TA_BUSY_MASK | GRBM_STATUS__DB_BUSY_MASK |
7289                    GRBM_STATUS__CB_BUSY_MASK | GRBM_STATUS__GDS_BUSY_MASK |
7290                    GRBM_STATUS__SPI_BUSY_MASK | GRBM_STATUS__GE_BUSY_NO_DMA_MASK)) {
7291                 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
7292                                                 GRBM_SOFT_RESET, SOFT_RESET_CP,
7293                                                 1);
7294                 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
7295                                                 GRBM_SOFT_RESET, SOFT_RESET_GFX,
7296                                                 1);
7297         }
7298
7299         if (tmp & (GRBM_STATUS__CP_BUSY_MASK | GRBM_STATUS__CP_COHERENCY_BUSY_MASK)) {
7300                 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
7301                                                 GRBM_SOFT_RESET, SOFT_RESET_CP,
7302                                                 1);
7303         }
7304
7305         /* GRBM_STATUS2 */
7306         tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS2);
7307         switch (adev->asic_type) {
7308         case CHIP_SIENNA_CICHLID:
7309         case CHIP_NAVY_FLOUNDER:
7310         case CHIP_VANGOGH:
7311         case CHIP_DIMGREY_CAVEFISH:
7312                 if (REG_GET_FIELD(tmp, GRBM_STATUS2, RLC_BUSY_Sienna_Cichlid))
7313                         grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
7314                                                         GRBM_SOFT_RESET,
7315                                                         SOFT_RESET_RLC,
7316                                                         1);
7317                 break;
7318         default:
7319                 if (REG_GET_FIELD(tmp, GRBM_STATUS2, RLC_BUSY))
7320                         grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
7321                                                         GRBM_SOFT_RESET,
7322                                                         SOFT_RESET_RLC,
7323                                                         1);
7324                 break;
7325         }
7326
7327         if (grbm_soft_reset) {
7328                 /* stop the rlc */
7329                 gfx_v10_0_rlc_stop(adev);
7330
7331                 /* Disable GFX parsing/prefetching */
7332                 gfx_v10_0_cp_gfx_enable(adev, false);
7333
7334                 /* Disable MEC parsing/prefetching */
7335                 gfx_v10_0_cp_compute_enable(adev, false);
7336
7337                 if (grbm_soft_reset) {
7338                         tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);
7339                         tmp |= grbm_soft_reset;
7340                         dev_info(adev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp);
7341                         WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp);
7342                         tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);
7343
7344                         udelay(50);
7345
7346                         tmp &= ~grbm_soft_reset;
7347                         WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp);
7348                         tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);
7349                 }
7350
7351                 /* Wait a little for things to settle down */
7352                 udelay(50);
7353         }
7354         return 0;
7355 }
7356
7357 static uint64_t gfx_v10_0_get_gpu_clock_counter(struct amdgpu_device *adev)
7358 {
7359         uint64_t clock;
7360
7361         amdgpu_gfx_off_ctrl(adev, false);
7362         mutex_lock(&adev->gfx.gpu_clock_mutex);
7363         clock = (uint64_t)RREG32_SOC15(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER) |
7364                 ((uint64_t)RREG32_SOC15(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER) << 32ULL);
7365         mutex_unlock(&adev->gfx.gpu_clock_mutex);
7366         amdgpu_gfx_off_ctrl(adev, true);
7367         return clock;
7368 }
7369
7370 static void gfx_v10_0_ring_emit_gds_switch(struct amdgpu_ring *ring,
7371                                            uint32_t vmid,
7372                                            uint32_t gds_base, uint32_t gds_size,
7373                                            uint32_t gws_base, uint32_t gws_size,
7374                                            uint32_t oa_base, uint32_t oa_size)
7375 {
7376         struct amdgpu_device *adev = ring->adev;
7377
7378         /* GDS Base */
7379         gfx_v10_0_write_data_to_reg(ring, 0, false,
7380                                     SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_BASE) + 2 * vmid,
7381                                     gds_base);
7382
7383         /* GDS Size */
7384         gfx_v10_0_write_data_to_reg(ring, 0, false,
7385                                     SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_SIZE) + 2 * vmid,
7386                                     gds_size);
7387
7388         /* GWS */
7389         gfx_v10_0_write_data_to_reg(ring, 0, false,
7390                                     SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID0) + vmid,
7391                                     gws_size << GDS_GWS_VMID0__SIZE__SHIFT | gws_base);
7392
7393         /* OA */
7394         gfx_v10_0_write_data_to_reg(ring, 0, false,
7395                                     SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID0) + vmid,
7396                                     (1 << (oa_size + oa_base)) - (1 << oa_base));
7397 }
7398
7399 static int gfx_v10_0_early_init(void *handle)
7400 {
7401         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7402
7403         switch (adev->asic_type) {
7404         case CHIP_NAVI10:
7405         case CHIP_NAVI14:
7406         case CHIP_NAVI12:
7407                 adev->gfx.num_gfx_rings = GFX10_NUM_GFX_RINGS_NV1X;
7408                 break;
7409         case CHIP_SIENNA_CICHLID:
7410         case CHIP_NAVY_FLOUNDER:
7411         case CHIP_VANGOGH:
7412         case CHIP_DIMGREY_CAVEFISH:
7413                 adev->gfx.num_gfx_rings = GFX10_NUM_GFX_RINGS_Sienna_Cichlid;
7414                 break;
7415         default:
7416                 break;
7417         }
7418
7419         adev->gfx.num_compute_rings = min(amdgpu_gfx_get_num_kcq(adev),
7420                                           AMDGPU_MAX_COMPUTE_RINGS);
7421
7422         gfx_v10_0_set_kiq_pm4_funcs(adev);
7423         gfx_v10_0_set_ring_funcs(adev);
7424         gfx_v10_0_set_irq_funcs(adev);
7425         gfx_v10_0_set_gds_init(adev);
7426         gfx_v10_0_set_rlc_funcs(adev);
7427
7428         return 0;
7429 }
7430
7431 static int gfx_v10_0_late_init(void *handle)
7432 {
7433         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7434         int r;
7435
7436         r = amdgpu_irq_get(adev, &adev->gfx.priv_reg_irq, 0);
7437         if (r)
7438                 return r;
7439
7440         r = amdgpu_irq_get(adev, &adev->gfx.priv_inst_irq, 0);
7441         if (r)
7442                 return r;
7443
7444         return 0;
7445 }
7446
7447 static bool gfx_v10_0_is_rlc_enabled(struct amdgpu_device *adev)
7448 {
7449         uint32_t rlc_cntl;
7450
7451         /* if RLC is not enabled, do nothing */
7452         rlc_cntl = RREG32_SOC15(GC, 0, mmRLC_CNTL);
7453         return (REG_GET_FIELD(rlc_cntl, RLC_CNTL, RLC_ENABLE_F32)) ? true : false;
7454 }
7455
7456 static void gfx_v10_0_set_safe_mode(struct amdgpu_device *adev)
7457 {
7458         uint32_t data;
7459         unsigned i;
7460
7461         data = RLC_SAFE_MODE__CMD_MASK;
7462         data |= (1 << RLC_SAFE_MODE__MESSAGE__SHIFT);
7463
7464         switch (adev->asic_type) {
7465         case CHIP_SIENNA_CICHLID:
7466         case CHIP_NAVY_FLOUNDER:
7467         case CHIP_VANGOGH:
7468         case CHIP_DIMGREY_CAVEFISH:
7469                 WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE_Sienna_Cichlid, data);
7470
7471                 /* wait for RLC_SAFE_MODE */
7472                 for (i = 0; i < adev->usec_timeout; i++) {
7473                         if (!REG_GET_FIELD(RREG32_SOC15(GC, 0, mmRLC_SAFE_MODE_Sienna_Cichlid),
7474                                            RLC_SAFE_MODE, CMD))
7475                                 break;
7476                         udelay(1);
7477                 }
7478                 break;
7479         default:
7480                 WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE, data);
7481
7482                 /* wait for RLC_SAFE_MODE */
7483                 for (i = 0; i < adev->usec_timeout; i++) {
7484                         if (!REG_GET_FIELD(RREG32_SOC15(GC, 0, mmRLC_SAFE_MODE),
7485                                            RLC_SAFE_MODE, CMD))
7486                                 break;
7487                         udelay(1);
7488                 }
7489                 break;
7490         }
7491 }
7492
7493 static void gfx_v10_0_unset_safe_mode(struct amdgpu_device *adev)
7494 {
7495         uint32_t data;
7496
7497         data = RLC_SAFE_MODE__CMD_MASK;
7498         switch (adev->asic_type) {
7499         case CHIP_SIENNA_CICHLID:
7500         case CHIP_NAVY_FLOUNDER:
7501         case CHIP_VANGOGH:
7502         case CHIP_DIMGREY_CAVEFISH:
7503                 WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE_Sienna_Cichlid, data);
7504                 break;
7505         default:
7506                 WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE, data);
7507                 break;
7508         }
7509 }
7510
7511 static void gfx_v10_0_update_medium_grain_clock_gating(struct amdgpu_device *adev,
7512                                                       bool enable)
7513 {
7514         uint32_t data, def;
7515
7516         /* It is disabled by HW by default */
7517         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) {
7518                 /* 0 - Disable some blocks' MGCG */
7519                 WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, 0xe0000000);
7520                 WREG32_SOC15(GC, 0, mmCGTT_WD_CLK_CTRL, 0xff000000);
7521                 WREG32_SOC15(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xff000000);
7522                 WREG32_SOC15(GC, 0, mmCGTT_IA_CLK_CTRL, 0xff000000);
7523
7524                 /* 1 - RLC_CGTT_MGCG_OVERRIDE */
7525                 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
7526                 data &= ~(RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK |
7527                           RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK |
7528                           RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK |
7529                           RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK |
7530                           RLC_CGTT_MGCG_OVERRIDE__ENABLE_CGTS_LEGACY_MASK);
7531
7532                 if (def != data)
7533                         WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
7534
7535                 /* MGLS is a global flag to control all MGLS in GFX */
7536                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGLS) {
7537                         /* 2 - RLC memory Light sleep */
7538                         if (adev->cg_flags & AMD_CG_SUPPORT_GFX_RLC_LS) {
7539                                 def = data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL);
7540                                 data |= RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK;
7541                                 if (def != data)
7542                                         WREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL, data);
7543                         }
7544                         /* 3 - CP memory Light sleep */
7545                         if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CP_LS) {
7546                                 def = data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL);
7547                                 data |= CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK;
7548                                 if (def != data)
7549                                         WREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL, data);
7550                         }
7551                 }
7552         } else {
7553                 /* 1 - MGCG_OVERRIDE */
7554                 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
7555                 data |= (RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK |
7556                          RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK |
7557                          RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK |
7558                          RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK);
7559                 if (def != data)
7560                         WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
7561
7562                 /* 2 - disable MGLS in CP */
7563                 data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL);
7564                 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) {
7565                         data &= ~CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK;
7566                         WREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL, data);
7567                 }
7568
7569                 /* 3 - disable MGLS in RLC */
7570                 data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL);
7571                 if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK) {
7572                         data &= ~RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK;
7573                         WREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL, data);
7574                 }
7575
7576         }
7577 }
7578
7579 static void gfx_v10_0_update_3d_clock_gating(struct amdgpu_device *adev,
7580                                            bool enable)
7581 {
7582         uint32_t data, def;
7583
7584         /* Enable 3D CGCG/CGLS */
7585         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG)) {
7586                 /* write cmd to clear cgcg/cgls ov */
7587                 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
7588                 /* unset CGCG override */
7589                 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_GFX3D_CG_OVERRIDE_MASK;
7590                 /* update CGCG and CGLS override bits */
7591                 if (def != data)
7592                         WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
7593                 /* enable 3Dcgcg FSM(0x0000363f) */
7594                 def = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D);
7595                 data = (0x36 << RLC_CGCG_CGLS_CTRL_3D__CGCG_GFX_IDLE_THRESHOLD__SHIFT) |
7596                         RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK;
7597                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS)
7598                         data |= (0x000F << RLC_CGCG_CGLS_CTRL_3D__CGLS_REP_COMPANSAT_DELAY__SHIFT) |
7599                                 RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK;
7600                 if (def != data)
7601                         WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D, data);
7602
7603                 /* set IDLE_POLL_COUNT(0x00900100) */
7604                 def = RREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL);
7605                 data = (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) |
7606                         (0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT);
7607                 if (def != data)
7608                         WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL, data);
7609         } else {
7610                 /* Disable CGCG/CGLS */
7611                 def = data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D);
7612                 /* disable cgcg, cgls should be disabled */
7613                 data &= ~(RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK |
7614                           RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK);
7615                 /* disable cgcg and cgls in FSM */
7616                 if (def != data)
7617                         WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D, data);
7618         }
7619 }
7620
7621 static void gfx_v10_0_update_coarse_grain_clock_gating(struct amdgpu_device *adev,
7622                                                       bool enable)
7623 {
7624         uint32_t def, data;
7625
7626         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)) {
7627                 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
7628                 /* unset CGCG override */
7629                 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGCG_OVERRIDE_MASK;
7630                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS)
7631                         data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK;
7632                 else
7633                         data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK;
7634                 /* update CGCG and CGLS override bits */
7635                 if (def != data)
7636                         WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
7637
7638                 /* enable cgcg FSM(0x0000363F) */
7639                 def = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL);
7640                 data = (0x36 << RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT) |
7641                         RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK;
7642                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS)
7643                         data |= (0x000F << RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY__SHIFT) |
7644                                 RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK;
7645                 if (def != data)
7646                         WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, data);
7647
7648                 /* set IDLE_POLL_COUNT(0x00900100) */
7649                 def = RREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL);
7650                 data = (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) |
7651                         (0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT);
7652                 if (def != data)
7653                         WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL, data);
7654         } else {
7655                 def = data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL);
7656                 /* reset CGCG/CGLS bits */
7657                 data &= ~(RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK | RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK);
7658                 /* disable cgcg and cgls in FSM */
7659                 if (def != data)
7660                         WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, data);
7661         }
7662 }
7663
7664 static void gfx_v10_0_update_fine_grain_clock_gating(struct amdgpu_device *adev,
7665                                                       bool enable)
7666 {
7667         uint32_t def, data;
7668
7669         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_FGCG)) {
7670                 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
7671                 /* unset FGCG override */
7672                 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK;
7673                 /* update FGCG override bits */
7674                 if (def != data)
7675                         WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
7676
7677                 def = data = RREG32_SOC15(GC, 0, mmRLC_CLK_CNTL);
7678                 /* unset RLC SRAM CLK GATER override */
7679                 data &= ~RLC_CLK_CNTL__RLC_SRAM_CLK_GATER_OVERRIDE_MASK;
7680                 /* update RLC SRAM CLK GATER override bits */
7681                 if (def != data)
7682                         WREG32_SOC15(GC, 0, mmRLC_CLK_CNTL, data);
7683         } else {
7684                 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
7685                 /* reset FGCG bits */
7686                 data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK;
7687                 /* disable FGCG*/
7688                 if (def != data)
7689                         WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
7690
7691                 def = data = RREG32_SOC15(GC, 0, mmRLC_CLK_CNTL);
7692                 /* reset RLC SRAM CLK GATER bits */
7693                 data |= RLC_CLK_CNTL__RLC_SRAM_CLK_GATER_OVERRIDE_MASK;
7694                 /* disable RLC SRAM CLK*/
7695                 if (def != data)
7696                         WREG32_SOC15(GC, 0, mmRLC_CLK_CNTL, data);
7697         }
7698 }
7699
7700 static int gfx_v10_0_update_gfx_clock_gating(struct amdgpu_device *adev,
7701                                             bool enable)
7702 {
7703         amdgpu_gfx_rlc_enter_safe_mode(adev);
7704
7705         if (enable) {
7706                 /* enable FGCG firstly*/
7707                 gfx_v10_0_update_fine_grain_clock_gating(adev, enable);
7708                 /* CGCG/CGLS should be enabled after MGCG/MGLS
7709                  * ===  MGCG + MGLS ===
7710                  */
7711                 gfx_v10_0_update_medium_grain_clock_gating(adev, enable);
7712                 /* ===  CGCG /CGLS for GFX 3D Only === */
7713                 gfx_v10_0_update_3d_clock_gating(adev, enable);
7714                 /* ===  CGCG + CGLS === */
7715                 gfx_v10_0_update_coarse_grain_clock_gating(adev, enable);
7716         } else {
7717                 /* CGCG/CGLS should be disabled before MGCG/MGLS
7718                  * ===  CGCG + CGLS ===
7719                  */
7720                 gfx_v10_0_update_coarse_grain_clock_gating(adev, enable);
7721                 /* ===  CGCG /CGLS for GFX 3D Only === */
7722                 gfx_v10_0_update_3d_clock_gating(adev, enable);
7723                 /* ===  MGCG + MGLS === */
7724                 gfx_v10_0_update_medium_grain_clock_gating(adev, enable);
7725                 /* disable fgcg at last*/
7726                 gfx_v10_0_update_fine_grain_clock_gating(adev, enable);
7727         }
7728
7729         if (adev->cg_flags &
7730             (AMD_CG_SUPPORT_GFX_MGCG |
7731              AMD_CG_SUPPORT_GFX_CGLS |
7732              AMD_CG_SUPPORT_GFX_CGCG |
7733              AMD_CG_SUPPORT_GFX_3D_CGCG |
7734              AMD_CG_SUPPORT_GFX_3D_CGLS))
7735                 gfx_v10_0_enable_gui_idle_interrupt(adev, enable);
7736
7737         amdgpu_gfx_rlc_exit_safe_mode(adev);
7738
7739         return 0;
7740 }
7741
7742 static void gfx_v10_0_update_spm_vmid(struct amdgpu_device *adev, unsigned vmid)
7743 {
7744         u32 reg, data;
7745
7746         reg = SOC15_REG_OFFSET(GC, 0, mmRLC_SPM_MC_CNTL);
7747         if (amdgpu_sriov_is_pp_one_vf(adev))
7748                 data = RREG32_NO_KIQ(reg);
7749         else
7750                 data = RREG32(reg);
7751
7752         data &= ~RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK;
7753         data |= (vmid & RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK) << RLC_SPM_MC_CNTL__RLC_SPM_VMID__SHIFT;
7754
7755         if (amdgpu_sriov_is_pp_one_vf(adev))
7756                 WREG32_SOC15_NO_KIQ(GC, 0, mmRLC_SPM_MC_CNTL, data);
7757         else
7758                 WREG32_SOC15(GC, 0, mmRLC_SPM_MC_CNTL, data);
7759 }
7760
7761 static bool gfx_v10_0_check_rlcg_range(struct amdgpu_device *adev,
7762                                         uint32_t offset,
7763                                         struct soc15_reg_rlcg *entries, int arr_size)
7764 {
7765         int i;
7766         uint32_t reg;
7767
7768         if (!entries)
7769                 return false;
7770
7771         for (i = 0; i < arr_size; i++) {
7772                 const struct soc15_reg_rlcg *entry;
7773
7774                 entry = &entries[i];
7775                 reg = adev->reg_offset[entry->hwip][entry->instance][entry->segment] + entry->reg;
7776                 if (offset == reg)
7777                         return true;
7778         }
7779
7780         return false;
7781 }
7782
7783 static bool gfx_v10_0_is_rlcg_access_range(struct amdgpu_device *adev, u32 offset)
7784 {
7785         return gfx_v10_0_check_rlcg_range(adev, offset, NULL, 0);
7786 }
7787
7788 static void gfx_v10_cntl_power_gating(struct amdgpu_device *adev, bool enable)
7789 {
7790         u32 data = RREG32_SOC15(GC, 0, mmRLC_PG_CNTL);
7791
7792         if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG))
7793                 data |= RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK;
7794         else
7795                 data &= ~RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK;
7796
7797         WREG32_SOC15(GC, 0, mmRLC_PG_CNTL, data);
7798 }
7799
7800 static void gfx_v10_cntl_pg(struct amdgpu_device *adev, bool enable)
7801 {
7802         amdgpu_gfx_rlc_enter_safe_mode(adev);
7803
7804         gfx_v10_cntl_power_gating(adev, enable);
7805
7806         amdgpu_gfx_rlc_exit_safe_mode(adev);
7807 }
7808
7809 static const struct amdgpu_rlc_funcs gfx_v10_0_rlc_funcs = {
7810         .is_rlc_enabled = gfx_v10_0_is_rlc_enabled,
7811         .set_safe_mode = gfx_v10_0_set_safe_mode,
7812         .unset_safe_mode = gfx_v10_0_unset_safe_mode,
7813         .init = gfx_v10_0_rlc_init,
7814         .get_csb_size = gfx_v10_0_get_csb_size,
7815         .get_csb_buffer = gfx_v10_0_get_csb_buffer,
7816         .resume = gfx_v10_0_rlc_resume,
7817         .stop = gfx_v10_0_rlc_stop,
7818         .reset = gfx_v10_0_rlc_reset,
7819         .start = gfx_v10_0_rlc_start,
7820         .update_spm_vmid = gfx_v10_0_update_spm_vmid,
7821 };
7822
7823 static const struct amdgpu_rlc_funcs gfx_v10_0_rlc_funcs_sriov = {
7824         .is_rlc_enabled = gfx_v10_0_is_rlc_enabled,
7825         .set_safe_mode = gfx_v10_0_set_safe_mode,
7826         .unset_safe_mode = gfx_v10_0_unset_safe_mode,
7827         .init = gfx_v10_0_rlc_init,
7828         .get_csb_size = gfx_v10_0_get_csb_size,
7829         .get_csb_buffer = gfx_v10_0_get_csb_buffer,
7830         .resume = gfx_v10_0_rlc_resume,
7831         .stop = gfx_v10_0_rlc_stop,
7832         .reset = gfx_v10_0_rlc_reset,
7833         .start = gfx_v10_0_rlc_start,
7834         .update_spm_vmid = gfx_v10_0_update_spm_vmid,
7835         .rlcg_wreg = gfx_v10_rlcg_wreg,
7836         .is_rlcg_access_range = gfx_v10_0_is_rlcg_access_range,
7837 };
7838
7839 static int gfx_v10_0_set_powergating_state(void *handle,
7840                                           enum amd_powergating_state state)
7841 {
7842         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7843         bool enable = (state == AMD_PG_STATE_GATE);
7844
7845         if (amdgpu_sriov_vf(adev))
7846                 return 0;
7847
7848         switch (adev->asic_type) {
7849         case CHIP_NAVI10:
7850         case CHIP_NAVI14:
7851         case CHIP_NAVI12:
7852         case CHIP_SIENNA_CICHLID:
7853         case CHIP_NAVY_FLOUNDER:
7854         case CHIP_DIMGREY_CAVEFISH:
7855                 amdgpu_gfx_off_ctrl(adev, enable);
7856                 break;
7857         case CHIP_VANGOGH:
7858                 gfx_v10_cntl_pg(adev, enable);
7859                 break;
7860         default:
7861                 break;
7862         }
7863         return 0;
7864 }
7865
7866 static int gfx_v10_0_set_clockgating_state(void *handle,
7867                                           enum amd_clockgating_state state)
7868 {
7869         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7870
7871         if (amdgpu_sriov_vf(adev))
7872                 return 0;
7873
7874         switch (adev->asic_type) {
7875         case CHIP_NAVI10:
7876         case CHIP_NAVI14:
7877         case CHIP_NAVI12:
7878         case CHIP_SIENNA_CICHLID:
7879         case CHIP_NAVY_FLOUNDER:
7880         case CHIP_VANGOGH:
7881         case CHIP_DIMGREY_CAVEFISH:
7882                 gfx_v10_0_update_gfx_clock_gating(adev,
7883                                                  state == AMD_CG_STATE_GATE);
7884                 break;
7885         default:
7886                 break;
7887         }
7888         return 0;
7889 }
7890
7891 static void gfx_v10_0_get_clockgating_state(void *handle, u32 *flags)
7892 {
7893         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7894         int data;
7895
7896         /* AMD_CG_SUPPORT_GFX_FGCG */
7897         data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE));
7898         if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK))
7899                 *flags |= AMD_CG_SUPPORT_GFX_FGCG;
7900
7901         /* AMD_CG_SUPPORT_GFX_MGCG */
7902         data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE));
7903         if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK))
7904                 *flags |= AMD_CG_SUPPORT_GFX_MGCG;
7905
7906         /* AMD_CG_SUPPORT_GFX_CGCG */
7907         data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGCG_CGLS_CTRL));
7908         if (data & RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK)
7909                 *flags |= AMD_CG_SUPPORT_GFX_CGCG;
7910
7911         /* AMD_CG_SUPPORT_GFX_CGLS */
7912         if (data & RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK)
7913                 *flags |= AMD_CG_SUPPORT_GFX_CGLS;
7914
7915         /* AMD_CG_SUPPORT_GFX_RLC_LS */
7916         data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_MEM_SLP_CNTL));
7917         if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK)
7918                 *flags |= AMD_CG_SUPPORT_GFX_RLC_LS | AMD_CG_SUPPORT_GFX_MGLS;
7919
7920         /* AMD_CG_SUPPORT_GFX_CP_LS */
7921         data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmCP_MEM_SLP_CNTL));
7922         if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK)
7923                 *flags |= AMD_CG_SUPPORT_GFX_CP_LS | AMD_CG_SUPPORT_GFX_MGLS;
7924
7925         /* AMD_CG_SUPPORT_GFX_3D_CGCG */
7926         data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D));
7927         if (data & RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK)
7928                 *flags |= AMD_CG_SUPPORT_GFX_3D_CGCG;
7929
7930         /* AMD_CG_SUPPORT_GFX_3D_CGLS */
7931         if (data & RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK)
7932                 *flags |= AMD_CG_SUPPORT_GFX_3D_CGLS;
7933 }
7934
7935 static u64 gfx_v10_0_ring_get_rptr_gfx(struct amdgpu_ring *ring)
7936 {
7937         return ring->adev->wb.wb[ring->rptr_offs]; /* gfx10 is 32bit rptr*/
7938 }
7939
7940 static u64 gfx_v10_0_ring_get_wptr_gfx(struct amdgpu_ring *ring)
7941 {
7942         struct amdgpu_device *adev = ring->adev;
7943         u64 wptr;
7944
7945         /* XXX check if swapping is necessary on BE */
7946         if (ring->use_doorbell) {
7947                 wptr = atomic64_read((atomic64_t *)&adev->wb.wb[ring->wptr_offs]);
7948         } else {
7949                 wptr = RREG32_SOC15(GC, 0, mmCP_RB0_WPTR);
7950                 wptr += (u64)RREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI) << 32;
7951         }
7952
7953         return wptr;
7954 }
7955
7956 static void gfx_v10_0_ring_set_wptr_gfx(struct amdgpu_ring *ring)
7957 {
7958         struct amdgpu_device *adev = ring->adev;
7959
7960         if (ring->use_doorbell) {
7961                 /* XXX check if swapping is necessary on BE */
7962                 atomic64_set((atomic64_t *)&adev->wb.wb[ring->wptr_offs], ring->wptr);
7963                 WDOORBELL64(ring->doorbell_index, ring->wptr);
7964         } else {
7965                 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR, lower_32_bits(ring->wptr));
7966                 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI, upper_32_bits(ring->wptr));
7967         }
7968 }
7969
7970 static u64 gfx_v10_0_ring_get_rptr_compute(struct amdgpu_ring *ring)
7971 {
7972         return ring->adev->wb.wb[ring->rptr_offs]; /* gfx10 hardware is 32bit rptr */
7973 }
7974
7975 static u64 gfx_v10_0_ring_get_wptr_compute(struct amdgpu_ring *ring)
7976 {
7977         u64 wptr;
7978
7979         /* XXX check if swapping is necessary on BE */
7980         if (ring->use_doorbell)
7981                 wptr = atomic64_read((atomic64_t *)&ring->adev->wb.wb[ring->wptr_offs]);
7982         else
7983                 BUG();
7984         return wptr;
7985 }
7986
7987 static void gfx_v10_0_ring_set_wptr_compute(struct amdgpu_ring *ring)
7988 {
7989         struct amdgpu_device *adev = ring->adev;
7990
7991         /* XXX check if swapping is necessary on BE */
7992         if (ring->use_doorbell) {
7993                 atomic64_set((atomic64_t *)&adev->wb.wb[ring->wptr_offs], ring->wptr);
7994                 WDOORBELL64(ring->doorbell_index, ring->wptr);
7995         } else {
7996                 BUG(); /* only DOORBELL method supported on gfx10 now */
7997         }
7998 }
7999
8000 static void gfx_v10_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
8001 {
8002         struct amdgpu_device *adev = ring->adev;
8003         u32 ref_and_mask, reg_mem_engine;
8004         const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio.hdp_flush_reg;
8005
8006         if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) {
8007                 switch (ring->me) {
8008                 case 1:
8009                         ref_and_mask = nbio_hf_reg->ref_and_mask_cp2 << ring->pipe;
8010                         break;
8011                 case 2:
8012                         ref_and_mask = nbio_hf_reg->ref_and_mask_cp6 << ring->pipe;
8013                         break;
8014                 default:
8015                         return;
8016                 }
8017                 reg_mem_engine = 0;
8018         } else {
8019                 ref_and_mask = nbio_hf_reg->ref_and_mask_cp0;
8020                 reg_mem_engine = 1; /* pfp */
8021         }
8022
8023         gfx_v10_0_wait_reg_mem(ring, reg_mem_engine, 0, 1,
8024                                adev->nbio.funcs->get_hdp_flush_req_offset(adev),
8025                                adev->nbio.funcs->get_hdp_flush_done_offset(adev),
8026                                ref_and_mask, ref_and_mask, 0x20);
8027 }
8028
8029 static void gfx_v10_0_ring_emit_ib_gfx(struct amdgpu_ring *ring,
8030                                        struct amdgpu_job *job,
8031                                        struct amdgpu_ib *ib,
8032                                        uint32_t flags)
8033 {
8034         unsigned vmid = AMDGPU_JOB_GET_VMID(job);
8035         u32 header, control = 0;
8036
8037         if (ib->flags & AMDGPU_IB_FLAG_CE)
8038                 header = PACKET3(PACKET3_INDIRECT_BUFFER_CNST, 2);
8039         else
8040                 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2);
8041
8042         control |= ib->length_dw | (vmid << 24);
8043
8044         if ((amdgpu_sriov_vf(ring->adev) || amdgpu_mcbp) && (ib->flags & AMDGPU_IB_FLAG_PREEMPT)) {
8045                 control |= INDIRECT_BUFFER_PRE_ENB(1);
8046
8047                 if (flags & AMDGPU_IB_PREEMPTED)
8048                         control |= INDIRECT_BUFFER_PRE_RESUME(1);
8049
8050                 if (!(ib->flags & AMDGPU_IB_FLAG_CE) && vmid)
8051                         gfx_v10_0_ring_emit_de_meta(ring,
8052                                     (!amdgpu_sriov_vf(ring->adev) && flags & AMDGPU_IB_PREEMPTED) ? true : false);
8053         }
8054
8055         amdgpu_ring_write(ring, header);
8056         BUG_ON(ib->gpu_addr & 0x3); /* Dword align */
8057         amdgpu_ring_write(ring,
8058 #ifdef __BIG_ENDIAN
8059                 (2 << 0) |
8060 #endif
8061                 lower_32_bits(ib->gpu_addr));
8062         amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
8063         amdgpu_ring_write(ring, control);
8064 }
8065
8066 static void gfx_v10_0_ring_emit_ib_compute(struct amdgpu_ring *ring,
8067                                            struct amdgpu_job *job,
8068                                            struct amdgpu_ib *ib,
8069                                            uint32_t flags)
8070 {
8071         unsigned vmid = AMDGPU_JOB_GET_VMID(job);
8072         u32 control = INDIRECT_BUFFER_VALID | ib->length_dw | (vmid << 24);
8073
8074         /* Currently, there is a high possibility to get wave ID mismatch
8075          * between ME and GDS, leading to a hw deadlock, because ME generates
8076          * different wave IDs than the GDS expects. This situation happens
8077          * randomly when at least 5 compute pipes use GDS ordered append.
8078          * The wave IDs generated by ME are also wrong after suspend/resume.
8079          * Those are probably bugs somewhere else in the kernel driver.
8080          *
8081          * Writing GDS_COMPUTE_MAX_WAVE_ID resets wave ID counters in ME and
8082          * GDS to 0 for this ring (me/pipe).
8083          */
8084         if (ib->flags & AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID) {
8085                 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
8086                 amdgpu_ring_write(ring, mmGDS_COMPUTE_MAX_WAVE_ID);
8087                 amdgpu_ring_write(ring, ring->adev->gds.gds_compute_max_wave_id);
8088         }
8089
8090         amdgpu_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
8091         BUG_ON(ib->gpu_addr & 0x3); /* Dword align */
8092         amdgpu_ring_write(ring,
8093 #ifdef __BIG_ENDIAN
8094                                 (2 << 0) |
8095 #endif
8096                                 lower_32_bits(ib->gpu_addr));
8097         amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
8098         amdgpu_ring_write(ring, control);
8099 }
8100
8101 static void gfx_v10_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr,
8102                                      u64 seq, unsigned flags)
8103 {
8104         bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
8105         bool int_sel = flags & AMDGPU_FENCE_FLAG_INT;
8106
8107         /* RELEASE_MEM - flush caches, send int */
8108         amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 6));
8109         amdgpu_ring_write(ring, (PACKET3_RELEASE_MEM_GCR_SEQ |
8110                                  PACKET3_RELEASE_MEM_GCR_GL2_WB |
8111                                  PACKET3_RELEASE_MEM_GCR_GLM_INV | /* must be set with GLM_WB */
8112                                  PACKET3_RELEASE_MEM_GCR_GLM_WB |
8113                                  PACKET3_RELEASE_MEM_CACHE_POLICY(3) |
8114                                  PACKET3_RELEASE_MEM_EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) |
8115                                  PACKET3_RELEASE_MEM_EVENT_INDEX(5)));
8116         amdgpu_ring_write(ring, (PACKET3_RELEASE_MEM_DATA_SEL(write64bit ? 2 : 1) |
8117                                  PACKET3_RELEASE_MEM_INT_SEL(int_sel ? 2 : 0)));
8118
8119         /*
8120          * the address should be Qword aligned if 64bit write, Dword
8121          * aligned if only send 32bit data low (discard data high)
8122          */
8123         if (write64bit)
8124                 BUG_ON(addr & 0x7);
8125         else
8126                 BUG_ON(addr & 0x3);
8127         amdgpu_ring_write(ring, lower_32_bits(addr));
8128         amdgpu_ring_write(ring, upper_32_bits(addr));
8129         amdgpu_ring_write(ring, lower_32_bits(seq));
8130         amdgpu_ring_write(ring, upper_32_bits(seq));
8131         amdgpu_ring_write(ring, 0);
8132 }
8133
8134 static void gfx_v10_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
8135 {
8136         int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
8137         uint32_t seq = ring->fence_drv.sync_seq;
8138         uint64_t addr = ring->fence_drv.gpu_addr;
8139
8140         gfx_v10_0_wait_reg_mem(ring, usepfp, 1, 0, lower_32_bits(addr),
8141                                upper_32_bits(addr), seq, 0xffffffff, 4);
8142 }
8143
8144 static void gfx_v10_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
8145                                          unsigned vmid, uint64_t pd_addr)
8146 {
8147         amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
8148
8149         /* compute doesn't have PFP */
8150         if (ring->funcs->type == AMDGPU_RING_TYPE_GFX) {
8151                 /* sync PFP to ME, otherwise we might get invalid PFP reads */
8152                 amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0));
8153                 amdgpu_ring_write(ring, 0x0);
8154         }
8155 }
8156
8157 static void gfx_v10_0_ring_emit_fence_kiq(struct amdgpu_ring *ring, u64 addr,
8158                                           u64 seq, unsigned int flags)
8159 {
8160         struct amdgpu_device *adev = ring->adev;
8161
8162         /* we only allocate 32bit for each seq wb address */
8163         BUG_ON(flags & AMDGPU_FENCE_FLAG_64BIT);
8164
8165         /* write fence seq to the "addr" */
8166         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
8167         amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
8168                                  WRITE_DATA_DST_SEL(5) | WR_CONFIRM));
8169         amdgpu_ring_write(ring, lower_32_bits(addr));
8170         amdgpu_ring_write(ring, upper_32_bits(addr));
8171         amdgpu_ring_write(ring, lower_32_bits(seq));
8172
8173         if (flags & AMDGPU_FENCE_FLAG_INT) {
8174                 /* set register to trigger INT */
8175                 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
8176                 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
8177                                          WRITE_DATA_DST_SEL(0) | WR_CONFIRM));
8178                 amdgpu_ring_write(ring, SOC15_REG_OFFSET(GC, 0, mmCPC_INT_STATUS));
8179                 amdgpu_ring_write(ring, 0);
8180                 amdgpu_ring_write(ring, 0x20000000); /* src_id is 178 */
8181         }
8182 }
8183
8184 static void gfx_v10_0_ring_emit_sb(struct amdgpu_ring *ring)
8185 {
8186         amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
8187         amdgpu_ring_write(ring, 0);
8188 }
8189
8190 static void gfx_v10_0_ring_emit_cntxcntl(struct amdgpu_ring *ring,
8191                                          uint32_t flags)
8192 {
8193         uint32_t dw2 = 0;
8194
8195         if (amdgpu_mcbp || amdgpu_sriov_vf(ring->adev))
8196                 gfx_v10_0_ring_emit_ce_meta(ring,
8197                                     (!amdgpu_sriov_vf(ring->adev) && flags & AMDGPU_IB_PREEMPTED) ? true : false);
8198
8199         dw2 |= 0x80000000; /* set load_enable otherwise this package is just NOPs */
8200         if (flags & AMDGPU_HAVE_CTX_SWITCH) {
8201                 /* set load_global_config & load_global_uconfig */
8202                 dw2 |= 0x8001;
8203                 /* set load_cs_sh_regs */
8204                 dw2 |= 0x01000000;
8205                 /* set load_per_context_state & load_gfx_sh_regs for GFX */
8206                 dw2 |= 0x10002;
8207
8208                 /* set load_ce_ram if preamble presented */
8209                 if (AMDGPU_PREAMBLE_IB_PRESENT & flags)
8210                         dw2 |= 0x10000000;
8211         } else {
8212                 /* still load_ce_ram if this is the first time preamble presented
8213                  * although there is no context switch happens.
8214                  */
8215                 if (AMDGPU_PREAMBLE_IB_PRESENT_FIRST & flags)
8216                         dw2 |= 0x10000000;
8217         }
8218
8219         amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1));
8220         amdgpu_ring_write(ring, dw2);
8221         amdgpu_ring_write(ring, 0);
8222 }
8223
8224 static unsigned gfx_v10_0_ring_emit_init_cond_exec(struct amdgpu_ring *ring)
8225 {
8226         unsigned ret;
8227
8228         amdgpu_ring_write(ring, PACKET3(PACKET3_COND_EXEC, 3));
8229         amdgpu_ring_write(ring, lower_32_bits(ring->cond_exe_gpu_addr));
8230         amdgpu_ring_write(ring, upper_32_bits(ring->cond_exe_gpu_addr));
8231         amdgpu_ring_write(ring, 0); /* discard following DWs if *cond_exec_gpu_addr==0 */
8232         ret = ring->wptr & ring->buf_mask;
8233         amdgpu_ring_write(ring, 0x55aa55aa); /* patch dummy value later */
8234
8235         return ret;
8236 }
8237
8238 static void gfx_v10_0_ring_emit_patch_cond_exec(struct amdgpu_ring *ring, unsigned offset)
8239 {
8240         unsigned cur;
8241         BUG_ON(offset > ring->buf_mask);
8242         BUG_ON(ring->ring[offset] != 0x55aa55aa);
8243
8244         cur = (ring->wptr - 1) & ring->buf_mask;
8245         if (likely(cur > offset))
8246                 ring->ring[offset] = cur - offset;
8247         else
8248                 ring->ring[offset] = (ring->buf_mask + 1) - offset + cur;
8249 }
8250
8251 static int gfx_v10_0_ring_preempt_ib(struct amdgpu_ring *ring)
8252 {
8253         int i, r = 0;
8254         struct amdgpu_device *adev = ring->adev;
8255         struct amdgpu_kiq *kiq = &adev->gfx.kiq;
8256         struct amdgpu_ring *kiq_ring = &kiq->ring;
8257         unsigned long flags;
8258
8259         if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues)
8260                 return -EINVAL;
8261
8262         spin_lock_irqsave(&kiq->ring_lock, flags);
8263
8264         if (amdgpu_ring_alloc(kiq_ring, kiq->pmf->unmap_queues_size)) {
8265                 spin_unlock_irqrestore(&kiq->ring_lock, flags);
8266                 return -ENOMEM;
8267         }
8268
8269         /* assert preemption condition */
8270         amdgpu_ring_set_preempt_cond_exec(ring, false);
8271
8272         /* assert IB preemption, emit the trailing fence */
8273         kiq->pmf->kiq_unmap_queues(kiq_ring, ring, PREEMPT_QUEUES_NO_UNMAP,
8274                                    ring->trail_fence_gpu_addr,
8275                                    ++ring->trail_seq);
8276         amdgpu_ring_commit(kiq_ring);
8277
8278         spin_unlock_irqrestore(&kiq->ring_lock, flags);
8279
8280         /* poll the trailing fence */
8281         for (i = 0; i < adev->usec_timeout; i++) {
8282                 if (ring->trail_seq ==
8283                     le32_to_cpu(*(ring->trail_fence_cpu_addr)))
8284                         break;
8285                 udelay(1);
8286         }
8287
8288         if (i >= adev->usec_timeout) {
8289                 r = -EINVAL;
8290                 DRM_ERROR("ring %d failed to preempt ib\n", ring->idx);
8291         }
8292
8293         /* deassert preemption condition */
8294         amdgpu_ring_set_preempt_cond_exec(ring, true);
8295         return r;
8296 }
8297
8298 static void gfx_v10_0_ring_emit_ce_meta(struct amdgpu_ring *ring, bool resume)
8299 {
8300         struct amdgpu_device *adev = ring->adev;
8301         struct v10_ce_ib_state ce_payload = {0};
8302         uint64_t csa_addr;
8303         int cnt;
8304
8305         cnt = (sizeof(ce_payload) >> 2) + 4 - 2;
8306         csa_addr = amdgpu_csa_vaddr(ring->adev);
8307
8308         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt));
8309         amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(2) |
8310                                  WRITE_DATA_DST_SEL(8) |
8311                                  WR_CONFIRM) |
8312                                  WRITE_DATA_CACHE_POLICY(0));
8313         amdgpu_ring_write(ring, lower_32_bits(csa_addr +
8314                               offsetof(struct v10_gfx_meta_data, ce_payload)));
8315         amdgpu_ring_write(ring, upper_32_bits(csa_addr +
8316                               offsetof(struct v10_gfx_meta_data, ce_payload)));
8317
8318         if (resume)
8319                 amdgpu_ring_write_multiple(ring, adev->virt.csa_cpu_addr +
8320                                            offsetof(struct v10_gfx_meta_data,
8321                                                     ce_payload),
8322                                            sizeof(ce_payload) >> 2);
8323         else
8324                 amdgpu_ring_write_multiple(ring, (void *)&ce_payload,
8325                                            sizeof(ce_payload) >> 2);
8326 }
8327
8328 static void gfx_v10_0_ring_emit_de_meta(struct amdgpu_ring *ring, bool resume)
8329 {
8330         struct amdgpu_device *adev = ring->adev;
8331         struct v10_de_ib_state de_payload = {0};
8332         uint64_t csa_addr, gds_addr;
8333         int cnt;
8334
8335         csa_addr = amdgpu_csa_vaddr(ring->adev);
8336         gds_addr = ALIGN(csa_addr + AMDGPU_CSA_SIZE - adev->gds.gds_size,
8337                          PAGE_SIZE);
8338         de_payload.gds_backup_addrlo = lower_32_bits(gds_addr);
8339         de_payload.gds_backup_addrhi = upper_32_bits(gds_addr);
8340
8341         cnt = (sizeof(de_payload) >> 2) + 4 - 2;
8342         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt));
8343         amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(1) |
8344                                  WRITE_DATA_DST_SEL(8) |
8345                                  WR_CONFIRM) |
8346                                  WRITE_DATA_CACHE_POLICY(0));
8347         amdgpu_ring_write(ring, lower_32_bits(csa_addr +
8348                               offsetof(struct v10_gfx_meta_data, de_payload)));
8349         amdgpu_ring_write(ring, upper_32_bits(csa_addr +
8350                               offsetof(struct v10_gfx_meta_data, de_payload)));
8351
8352         if (resume)
8353                 amdgpu_ring_write_multiple(ring, adev->virt.csa_cpu_addr +
8354                                            offsetof(struct v10_gfx_meta_data,
8355                                                     de_payload),
8356                                            sizeof(de_payload) >> 2);
8357         else
8358                 amdgpu_ring_write_multiple(ring, (void *)&de_payload,
8359                                            sizeof(de_payload) >> 2);
8360 }
8361
8362 static void gfx_v10_0_ring_emit_frame_cntl(struct amdgpu_ring *ring, bool start,
8363                                     bool secure)
8364 {
8365         uint32_t v = secure ? FRAME_TMZ : 0;
8366
8367         amdgpu_ring_write(ring, PACKET3(PACKET3_FRAME_CONTROL, 0));
8368         amdgpu_ring_write(ring, v | FRAME_CMD(start ? 0 : 1));
8369 }
8370
8371 static void gfx_v10_0_ring_emit_rreg(struct amdgpu_ring *ring, uint32_t reg,
8372                                      uint32_t reg_val_offs)
8373 {
8374         struct amdgpu_device *adev = ring->adev;
8375
8376         amdgpu_ring_write(ring, PACKET3(PACKET3_COPY_DATA, 4));
8377         amdgpu_ring_write(ring, 0 |     /* src: register*/
8378                                 (5 << 8) |      /* dst: memory */
8379                                 (1 << 20));     /* write confirm */
8380         amdgpu_ring_write(ring, reg);
8381         amdgpu_ring_write(ring, 0);
8382         amdgpu_ring_write(ring, lower_32_bits(adev->wb.gpu_addr +
8383                                 reg_val_offs * 4));
8384         amdgpu_ring_write(ring, upper_32_bits(adev->wb.gpu_addr +
8385                                 reg_val_offs * 4));
8386 }
8387
8388 static void gfx_v10_0_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg,
8389                                    uint32_t val)
8390 {
8391         uint32_t cmd = 0;
8392
8393         switch (ring->funcs->type) {
8394         case AMDGPU_RING_TYPE_GFX:
8395                 cmd = WRITE_DATA_ENGINE_SEL(1) | WR_CONFIRM;
8396                 break;
8397         case AMDGPU_RING_TYPE_KIQ:
8398                 cmd = (1 << 16); /* no inc addr */
8399                 break;
8400         default:
8401                 cmd = WR_CONFIRM;
8402                 break;
8403         }
8404         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
8405         amdgpu_ring_write(ring, cmd);
8406         amdgpu_ring_write(ring, reg);
8407         amdgpu_ring_write(ring, 0);
8408         amdgpu_ring_write(ring, val);
8409 }
8410
8411 static void gfx_v10_0_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,
8412                                         uint32_t val, uint32_t mask)
8413 {
8414         gfx_v10_0_wait_reg_mem(ring, 0, 0, 0, reg, 0, val, mask, 0x20);
8415 }
8416
8417 static void gfx_v10_0_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring,
8418                                                    uint32_t reg0, uint32_t reg1,
8419                                                    uint32_t ref, uint32_t mask)
8420 {
8421         int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
8422         struct amdgpu_device *adev = ring->adev;
8423         bool fw_version_ok = false;
8424
8425         fw_version_ok = adev->gfx.cp_fw_write_wait;
8426
8427         if (fw_version_ok)
8428                 gfx_v10_0_wait_reg_mem(ring, usepfp, 0, 1, reg0, reg1,
8429                                        ref, mask, 0x20);
8430         else
8431                 amdgpu_ring_emit_reg_write_reg_wait_helper(ring, reg0, reg1,
8432                                                            ref, mask);
8433 }
8434
8435 static void gfx_v10_0_ring_soft_recovery(struct amdgpu_ring *ring,
8436                                          unsigned vmid)
8437 {
8438         struct amdgpu_device *adev = ring->adev;
8439         uint32_t value = 0;
8440
8441         value = REG_SET_FIELD(value, SQ_CMD, CMD, 0x03);
8442         value = REG_SET_FIELD(value, SQ_CMD, MODE, 0x01);
8443         value = REG_SET_FIELD(value, SQ_CMD, CHECK_VMID, 1);
8444         value = REG_SET_FIELD(value, SQ_CMD, VM_ID, vmid);
8445         WREG32_SOC15(GC, 0, mmSQ_CMD, value);
8446 }
8447
8448 static void
8449 gfx_v10_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev,
8450                                       uint32_t me, uint32_t pipe,
8451                                       enum amdgpu_interrupt_state state)
8452 {
8453         uint32_t cp_int_cntl, cp_int_cntl_reg;
8454
8455         if (!me) {
8456                 switch (pipe) {
8457                 case 0:
8458                         cp_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_INT_CNTL_RING0);
8459                         break;
8460                 case 1:
8461                         cp_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_INT_CNTL_RING1);
8462                         break;
8463                 default:
8464                         DRM_DEBUG("invalid pipe %d\n", pipe);
8465                         return;
8466                 }
8467         } else {
8468                 DRM_DEBUG("invalid me %d\n", me);
8469                 return;
8470         }
8471
8472         switch (state) {
8473         case AMDGPU_IRQ_STATE_DISABLE:
8474                 cp_int_cntl = RREG32(cp_int_cntl_reg);
8475                 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
8476                                             TIME_STAMP_INT_ENABLE, 0);
8477                 WREG32(cp_int_cntl_reg, cp_int_cntl);
8478                 break;
8479         case AMDGPU_IRQ_STATE_ENABLE:
8480                 cp_int_cntl = RREG32(cp_int_cntl_reg);
8481                 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
8482                                             TIME_STAMP_INT_ENABLE, 1);
8483                 WREG32(cp_int_cntl_reg, cp_int_cntl);
8484                 break;
8485         default:
8486                 break;
8487         }
8488 }
8489
8490 static void gfx_v10_0_set_compute_eop_interrupt_state(struct amdgpu_device *adev,
8491                                                      int me, int pipe,
8492                                                      enum amdgpu_interrupt_state state)
8493 {
8494         u32 mec_int_cntl, mec_int_cntl_reg;
8495
8496         /*
8497          * amdgpu controls only the first MEC. That's why this function only
8498          * handles the setting of interrupts for this specific MEC. All other
8499          * pipes' interrupts are set by amdkfd.
8500          */
8501
8502         if (me == 1) {
8503                 switch (pipe) {
8504                 case 0:
8505                         mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE0_INT_CNTL);
8506                         break;
8507                 case 1:
8508                         mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE1_INT_CNTL);
8509                         break;
8510                 case 2:
8511                         mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE2_INT_CNTL);
8512                         break;
8513                 case 3:
8514                         mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE3_INT_CNTL);
8515                         break;
8516                 default:
8517                         DRM_DEBUG("invalid pipe %d\n", pipe);
8518                         return;
8519                 }
8520         } else {
8521                 DRM_DEBUG("invalid me %d\n", me);
8522                 return;
8523         }
8524
8525         switch (state) {
8526         case AMDGPU_IRQ_STATE_DISABLE:
8527                 mec_int_cntl = RREG32(mec_int_cntl_reg);
8528                 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,
8529                                              TIME_STAMP_INT_ENABLE, 0);
8530                 WREG32(mec_int_cntl_reg, mec_int_cntl);
8531                 break;
8532         case AMDGPU_IRQ_STATE_ENABLE:
8533                 mec_int_cntl = RREG32(mec_int_cntl_reg);
8534                 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,
8535                                              TIME_STAMP_INT_ENABLE, 1);
8536                 WREG32(mec_int_cntl_reg, mec_int_cntl);
8537                 break;
8538         default:
8539                 break;
8540         }
8541 }
8542
8543 static int gfx_v10_0_set_eop_interrupt_state(struct amdgpu_device *adev,
8544                                             struct amdgpu_irq_src *src,
8545                                             unsigned type,
8546                                             enum amdgpu_interrupt_state state)
8547 {
8548         switch (type) {
8549         case AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP:
8550                 gfx_v10_0_set_gfx_eop_interrupt_state(adev, 0, 0, state);
8551                 break;
8552         case AMDGPU_CP_IRQ_GFX_ME0_PIPE1_EOP:
8553                 gfx_v10_0_set_gfx_eop_interrupt_state(adev, 0, 1, state);
8554                 break;
8555         case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP:
8556                 gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 0, state);
8557                 break;
8558         case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP:
8559                 gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 1, state);
8560                 break;
8561         case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP:
8562                 gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 2, state);
8563                 break;
8564         case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP:
8565                 gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 3, state);
8566                 break;
8567         case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP:
8568                 gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 0, state);
8569                 break;
8570         case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP:
8571                 gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 1, state);
8572                 break;
8573         case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP:
8574                 gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 2, state);
8575                 break;
8576         case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP:
8577                 gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 3, state);
8578                 break;
8579         default:
8580                 break;
8581         }
8582         return 0;
8583 }
8584
8585 static int gfx_v10_0_eop_irq(struct amdgpu_device *adev,
8586                              struct amdgpu_irq_src *source,
8587                              struct amdgpu_iv_entry *entry)
8588 {
8589         int i;
8590         u8 me_id, pipe_id, queue_id;
8591         struct amdgpu_ring *ring;
8592
8593         DRM_DEBUG("IH: CP EOP\n");
8594         me_id = (entry->ring_id & 0x0c) >> 2;
8595         pipe_id = (entry->ring_id & 0x03) >> 0;
8596         queue_id = (entry->ring_id & 0x70) >> 4;
8597
8598         switch (me_id) {
8599         case 0:
8600                 if (pipe_id == 0)
8601                         amdgpu_fence_process(&adev->gfx.gfx_ring[0]);
8602                 else
8603                         amdgpu_fence_process(&adev->gfx.gfx_ring[1]);
8604                 break;
8605         case 1:
8606         case 2:
8607                 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
8608                         ring = &adev->gfx.compute_ring[i];
8609                         /* Per-queue interrupt is supported for MEC starting from VI.
8610                           * The interrupt can only be enabled/disabled per pipe instead of per queue.
8611                           */
8612                         if ((ring->me == me_id) && (ring->pipe == pipe_id) && (ring->queue == queue_id))
8613                                 amdgpu_fence_process(ring);
8614                 }
8615                 break;
8616         }
8617         return 0;
8618 }
8619
8620 static int gfx_v10_0_set_priv_reg_fault_state(struct amdgpu_device *adev,
8621                                               struct amdgpu_irq_src *source,
8622                                               unsigned type,
8623                                               enum amdgpu_interrupt_state state)
8624 {
8625         switch (state) {
8626         case AMDGPU_IRQ_STATE_DISABLE:
8627         case AMDGPU_IRQ_STATE_ENABLE:
8628                 WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0,
8629                                PRIV_REG_INT_ENABLE,
8630                                state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
8631                 break;
8632         default:
8633                 break;
8634         }
8635
8636         return 0;
8637 }
8638
8639 static int gfx_v10_0_set_priv_inst_fault_state(struct amdgpu_device *adev,
8640                                                struct amdgpu_irq_src *source,
8641                                                unsigned type,
8642                                                enum amdgpu_interrupt_state state)
8643 {
8644         switch (state) {
8645         case AMDGPU_IRQ_STATE_DISABLE:
8646         case AMDGPU_IRQ_STATE_ENABLE:
8647                 WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0,
8648                                PRIV_INSTR_INT_ENABLE,
8649                                state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
8650         default:
8651                 break;
8652         }
8653
8654         return 0;
8655 }
8656
8657 static void gfx_v10_0_handle_priv_fault(struct amdgpu_device *adev,
8658                                         struct amdgpu_iv_entry *entry)
8659 {
8660         u8 me_id, pipe_id, queue_id;
8661         struct amdgpu_ring *ring;
8662         int i;
8663
8664         me_id = (entry->ring_id & 0x0c) >> 2;
8665         pipe_id = (entry->ring_id & 0x03) >> 0;
8666         queue_id = (entry->ring_id & 0x70) >> 4;
8667
8668         switch (me_id) {
8669         case 0:
8670                 for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
8671                         ring = &adev->gfx.gfx_ring[i];
8672                         /* we only enabled 1 gfx queue per pipe for now */
8673                         if (ring->me == me_id && ring->pipe == pipe_id)
8674                                 drm_sched_fault(&ring->sched);
8675                 }
8676                 break;
8677         case 1:
8678         case 2:
8679                 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
8680                         ring = &adev->gfx.compute_ring[i];
8681                         if (ring->me == me_id && ring->pipe == pipe_id &&
8682                             ring->queue == queue_id)
8683                                 drm_sched_fault(&ring->sched);
8684                 }
8685                 break;
8686         default:
8687                 BUG();
8688         }
8689 }
8690
8691 static int gfx_v10_0_priv_reg_irq(struct amdgpu_device *adev,
8692                                   struct amdgpu_irq_src *source,
8693                                   struct amdgpu_iv_entry *entry)
8694 {
8695         DRM_ERROR("Illegal register access in command stream\n");
8696         gfx_v10_0_handle_priv_fault(adev, entry);
8697         return 0;
8698 }
8699
8700 static int gfx_v10_0_priv_inst_irq(struct amdgpu_device *adev,
8701                                    struct amdgpu_irq_src *source,
8702                                    struct amdgpu_iv_entry *entry)
8703 {
8704         DRM_ERROR("Illegal instruction in command stream\n");
8705         gfx_v10_0_handle_priv_fault(adev, entry);
8706         return 0;
8707 }
8708
8709 static int gfx_v10_0_kiq_set_interrupt_state(struct amdgpu_device *adev,
8710                                              struct amdgpu_irq_src *src,
8711                                              unsigned int type,
8712                                              enum amdgpu_interrupt_state state)
8713 {
8714         uint32_t tmp, target;
8715         struct amdgpu_ring *ring = &(adev->gfx.kiq.ring);
8716
8717         if (ring->me == 1)
8718                 target = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE0_INT_CNTL);
8719         else
8720                 target = SOC15_REG_OFFSET(GC, 0, mmCP_ME2_PIPE0_INT_CNTL);
8721         target += ring->pipe;
8722
8723         switch (type) {
8724         case AMDGPU_CP_KIQ_IRQ_DRIVER0:
8725                 if (state == AMDGPU_IRQ_STATE_DISABLE) {
8726                         tmp = RREG32_SOC15(GC, 0, mmCPC_INT_CNTL);
8727                         tmp = REG_SET_FIELD(tmp, CPC_INT_CNTL,
8728                                             GENERIC2_INT_ENABLE, 0);
8729                         WREG32_SOC15(GC, 0, mmCPC_INT_CNTL, tmp);
8730
8731                         tmp = RREG32(target);
8732                         tmp = REG_SET_FIELD(tmp, CP_ME2_PIPE0_INT_CNTL,
8733                                             GENERIC2_INT_ENABLE, 0);
8734                         WREG32(target, tmp);
8735                 } else {
8736                         tmp = RREG32_SOC15(GC, 0, mmCPC_INT_CNTL);
8737                         tmp = REG_SET_FIELD(tmp, CPC_INT_CNTL,
8738                                             GENERIC2_INT_ENABLE, 1);
8739                         WREG32_SOC15(GC, 0, mmCPC_INT_CNTL, tmp);
8740
8741                         tmp = RREG32(target);
8742                         tmp = REG_SET_FIELD(tmp, CP_ME2_PIPE0_INT_CNTL,
8743                                             GENERIC2_INT_ENABLE, 1);
8744                         WREG32(target, tmp);
8745                 }
8746                 break;
8747         default:
8748                 BUG(); /* kiq only support GENERIC2_INT now */
8749                 break;
8750         }
8751         return 0;
8752 }
8753
8754 static int gfx_v10_0_kiq_irq(struct amdgpu_device *adev,
8755                              struct amdgpu_irq_src *source,
8756                              struct amdgpu_iv_entry *entry)
8757 {
8758         u8 me_id, pipe_id, queue_id;
8759         struct amdgpu_ring *ring = &(adev->gfx.kiq.ring);
8760
8761         me_id = (entry->ring_id & 0x0c) >> 2;
8762         pipe_id = (entry->ring_id & 0x03) >> 0;
8763         queue_id = (entry->ring_id & 0x70) >> 4;
8764         DRM_DEBUG("IH: CPC GENERIC2_INT, me:%d, pipe:%d, queue:%d\n",
8765                    me_id, pipe_id, queue_id);
8766
8767         amdgpu_fence_process(ring);
8768         return 0;
8769 }
8770
8771 static void gfx_v10_0_emit_mem_sync(struct amdgpu_ring *ring)
8772 {
8773         const unsigned int gcr_cntl =
8774                         PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_INV(1) |
8775                         PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_WB(1) |
8776                         PACKET3_ACQUIRE_MEM_GCR_CNTL_GLM_INV(1) |
8777                         PACKET3_ACQUIRE_MEM_GCR_CNTL_GLM_WB(1) |
8778                         PACKET3_ACQUIRE_MEM_GCR_CNTL_GL1_INV(1) |
8779                         PACKET3_ACQUIRE_MEM_GCR_CNTL_GLV_INV(1) |
8780                         PACKET3_ACQUIRE_MEM_GCR_CNTL_GLK_INV(1) |
8781                         PACKET3_ACQUIRE_MEM_GCR_CNTL_GLI_INV(1);
8782
8783         /* ACQUIRE_MEM - make one or more surfaces valid for use by the subsequent operations */
8784         amdgpu_ring_write(ring, PACKET3(PACKET3_ACQUIRE_MEM, 6));
8785         amdgpu_ring_write(ring, 0); /* CP_COHER_CNTL */
8786         amdgpu_ring_write(ring, 0xffffffff);  /* CP_COHER_SIZE */
8787         amdgpu_ring_write(ring, 0xffffff);  /* CP_COHER_SIZE_HI */
8788         amdgpu_ring_write(ring, 0); /* CP_COHER_BASE */
8789         amdgpu_ring_write(ring, 0);  /* CP_COHER_BASE_HI */
8790         amdgpu_ring_write(ring, 0x0000000A); /* POLL_INTERVAL */
8791         amdgpu_ring_write(ring, gcr_cntl); /* GCR_CNTL */
8792 }
8793
8794 static const struct amd_ip_funcs gfx_v10_0_ip_funcs = {
8795         .name = "gfx_v10_0",
8796         .early_init = gfx_v10_0_early_init,
8797         .late_init = gfx_v10_0_late_init,
8798         .sw_init = gfx_v10_0_sw_init,
8799         .sw_fini = gfx_v10_0_sw_fini,
8800         .hw_init = gfx_v10_0_hw_init,
8801         .hw_fini = gfx_v10_0_hw_fini,
8802         .suspend = gfx_v10_0_suspend,
8803         .resume = gfx_v10_0_resume,
8804         .is_idle = gfx_v10_0_is_idle,
8805         .wait_for_idle = gfx_v10_0_wait_for_idle,
8806         .soft_reset = gfx_v10_0_soft_reset,
8807         .set_clockgating_state = gfx_v10_0_set_clockgating_state,
8808         .set_powergating_state = gfx_v10_0_set_powergating_state,
8809         .get_clockgating_state = gfx_v10_0_get_clockgating_state,
8810 };
8811
8812 static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_gfx = {
8813         .type = AMDGPU_RING_TYPE_GFX,
8814         .align_mask = 0xff,
8815         .nop = PACKET3(PACKET3_NOP, 0x3FFF),
8816         .support_64bit_ptrs = true,
8817         .vmhub = AMDGPU_GFXHUB_0,
8818         .get_rptr = gfx_v10_0_ring_get_rptr_gfx,
8819         .get_wptr = gfx_v10_0_ring_get_wptr_gfx,
8820         .set_wptr = gfx_v10_0_ring_set_wptr_gfx,
8821         .emit_frame_size = /* totally 242 maximum if 16 IBs */
8822                 5 + /* COND_EXEC */
8823                 7 + /* PIPELINE_SYNC */
8824                 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 +
8825                 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 +
8826                 2 + /* VM_FLUSH */
8827                 8 + /* FENCE for VM_FLUSH */
8828                 20 + /* GDS switch */
8829                 4 + /* double SWITCH_BUFFER,
8830                      * the first COND_EXEC jump to the place
8831                      * just prior to this double SWITCH_BUFFER
8832                      */
8833                 5 + /* COND_EXEC */
8834                 7 + /* HDP_flush */
8835                 4 + /* VGT_flush */
8836                 14 + /* CE_META */
8837                 31 + /* DE_META */
8838                 3 + /* CNTX_CTRL */
8839                 5 + /* HDP_INVL */
8840                 8 + 8 + /* FENCE x2 */
8841                 2 + /* SWITCH_BUFFER */
8842                 8, /* gfx_v10_0_emit_mem_sync */
8843         .emit_ib_size = 4, /* gfx_v10_0_ring_emit_ib_gfx */
8844         .emit_ib = gfx_v10_0_ring_emit_ib_gfx,
8845         .emit_fence = gfx_v10_0_ring_emit_fence,
8846         .emit_pipeline_sync = gfx_v10_0_ring_emit_pipeline_sync,
8847         .emit_vm_flush = gfx_v10_0_ring_emit_vm_flush,
8848         .emit_gds_switch = gfx_v10_0_ring_emit_gds_switch,
8849         .emit_hdp_flush = gfx_v10_0_ring_emit_hdp_flush,
8850         .test_ring = gfx_v10_0_ring_test_ring,
8851         .test_ib = gfx_v10_0_ring_test_ib,
8852         .insert_nop = amdgpu_ring_insert_nop,
8853         .pad_ib = amdgpu_ring_generic_pad_ib,
8854         .emit_switch_buffer = gfx_v10_0_ring_emit_sb,
8855         .emit_cntxcntl = gfx_v10_0_ring_emit_cntxcntl,
8856         .init_cond_exec = gfx_v10_0_ring_emit_init_cond_exec,
8857         .patch_cond_exec = gfx_v10_0_ring_emit_patch_cond_exec,
8858         .preempt_ib = gfx_v10_0_ring_preempt_ib,
8859         .emit_frame_cntl = gfx_v10_0_ring_emit_frame_cntl,
8860         .emit_wreg = gfx_v10_0_ring_emit_wreg,
8861         .emit_reg_wait = gfx_v10_0_ring_emit_reg_wait,
8862         .emit_reg_write_reg_wait = gfx_v10_0_ring_emit_reg_write_reg_wait,
8863         .soft_recovery = gfx_v10_0_ring_soft_recovery,
8864         .emit_mem_sync = gfx_v10_0_emit_mem_sync,
8865 };
8866
8867 static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_compute = {
8868         .type = AMDGPU_RING_TYPE_COMPUTE,
8869         .align_mask = 0xff,
8870         .nop = PACKET3(PACKET3_NOP, 0x3FFF),
8871         .support_64bit_ptrs = true,
8872         .vmhub = AMDGPU_GFXHUB_0,
8873         .get_rptr = gfx_v10_0_ring_get_rptr_compute,
8874         .get_wptr = gfx_v10_0_ring_get_wptr_compute,
8875         .set_wptr = gfx_v10_0_ring_set_wptr_compute,
8876         .emit_frame_size =
8877                 20 + /* gfx_v10_0_ring_emit_gds_switch */
8878                 7 + /* gfx_v10_0_ring_emit_hdp_flush */
8879                 5 + /* hdp invalidate */
8880                 7 + /* gfx_v10_0_ring_emit_pipeline_sync */
8881                 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 +
8882                 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 +
8883                 2 + /* gfx_v10_0_ring_emit_vm_flush */
8884                 8 + 8 + 8 + /* gfx_v10_0_ring_emit_fence x3 for user fence, vm fence */
8885                 8, /* gfx_v10_0_emit_mem_sync */
8886         .emit_ib_size = 7, /* gfx_v10_0_ring_emit_ib_compute */
8887         .emit_ib = gfx_v10_0_ring_emit_ib_compute,
8888         .emit_fence = gfx_v10_0_ring_emit_fence,
8889         .emit_pipeline_sync = gfx_v10_0_ring_emit_pipeline_sync,
8890         .emit_vm_flush = gfx_v10_0_ring_emit_vm_flush,
8891         .emit_gds_switch = gfx_v10_0_ring_emit_gds_switch,
8892         .emit_hdp_flush = gfx_v10_0_ring_emit_hdp_flush,
8893         .test_ring = gfx_v10_0_ring_test_ring,
8894         .test_ib = gfx_v10_0_ring_test_ib,
8895         .insert_nop = amdgpu_ring_insert_nop,
8896         .pad_ib = amdgpu_ring_generic_pad_ib,
8897         .emit_wreg = gfx_v10_0_ring_emit_wreg,
8898         .emit_reg_wait = gfx_v10_0_ring_emit_reg_wait,
8899         .emit_reg_write_reg_wait = gfx_v10_0_ring_emit_reg_write_reg_wait,
8900         .emit_mem_sync = gfx_v10_0_emit_mem_sync,
8901 };
8902
8903 static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_kiq = {
8904         .type = AMDGPU_RING_TYPE_KIQ,
8905         .align_mask = 0xff,
8906         .nop = PACKET3(PACKET3_NOP, 0x3FFF),
8907         .support_64bit_ptrs = true,
8908         .vmhub = AMDGPU_GFXHUB_0,
8909         .get_rptr = gfx_v10_0_ring_get_rptr_compute,
8910         .get_wptr = gfx_v10_0_ring_get_wptr_compute,
8911         .set_wptr = gfx_v10_0_ring_set_wptr_compute,
8912         .emit_frame_size =
8913                 20 + /* gfx_v10_0_ring_emit_gds_switch */
8914                 7 + /* gfx_v10_0_ring_emit_hdp_flush */
8915                 5 + /*hdp invalidate */
8916                 7 + /* gfx_v10_0_ring_emit_pipeline_sync */
8917                 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 +
8918                 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 +
8919                 2 + /* gfx_v10_0_ring_emit_vm_flush */
8920                 8 + 8 + 8, /* gfx_v10_0_ring_emit_fence_kiq x3 for user fence, vm fence */
8921         .emit_ib_size = 7, /* gfx_v10_0_ring_emit_ib_compute */
8922         .emit_ib = gfx_v10_0_ring_emit_ib_compute,
8923         .emit_fence = gfx_v10_0_ring_emit_fence_kiq,
8924         .test_ring = gfx_v10_0_ring_test_ring,
8925         .test_ib = gfx_v10_0_ring_test_ib,
8926         .insert_nop = amdgpu_ring_insert_nop,
8927         .pad_ib = amdgpu_ring_generic_pad_ib,
8928         .emit_rreg = gfx_v10_0_ring_emit_rreg,
8929         .emit_wreg = gfx_v10_0_ring_emit_wreg,
8930         .emit_reg_wait = gfx_v10_0_ring_emit_reg_wait,
8931         .emit_reg_write_reg_wait = gfx_v10_0_ring_emit_reg_write_reg_wait,
8932 };
8933
8934 static void gfx_v10_0_set_ring_funcs(struct amdgpu_device *adev)
8935 {
8936         int i;
8937
8938         adev->gfx.kiq.ring.funcs = &gfx_v10_0_ring_funcs_kiq;
8939
8940         for (i = 0; i < adev->gfx.num_gfx_rings; i++)
8941                 adev->gfx.gfx_ring[i].funcs = &gfx_v10_0_ring_funcs_gfx;
8942
8943         for (i = 0; i < adev->gfx.num_compute_rings; i++)
8944                 adev->gfx.compute_ring[i].funcs = &gfx_v10_0_ring_funcs_compute;
8945 }
8946
8947 static const struct amdgpu_irq_src_funcs gfx_v10_0_eop_irq_funcs = {
8948         .set = gfx_v10_0_set_eop_interrupt_state,
8949         .process = gfx_v10_0_eop_irq,
8950 };
8951
8952 static const struct amdgpu_irq_src_funcs gfx_v10_0_priv_reg_irq_funcs = {
8953         .set = gfx_v10_0_set_priv_reg_fault_state,
8954         .process = gfx_v10_0_priv_reg_irq,
8955 };
8956
8957 static const struct amdgpu_irq_src_funcs gfx_v10_0_priv_inst_irq_funcs = {
8958         .set = gfx_v10_0_set_priv_inst_fault_state,
8959         .process = gfx_v10_0_priv_inst_irq,
8960 };
8961
8962 static const struct amdgpu_irq_src_funcs gfx_v10_0_kiq_irq_funcs = {
8963         .set = gfx_v10_0_kiq_set_interrupt_state,
8964         .process = gfx_v10_0_kiq_irq,
8965 };
8966
8967 static void gfx_v10_0_set_irq_funcs(struct amdgpu_device *adev)
8968 {
8969         adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST;
8970         adev->gfx.eop_irq.funcs = &gfx_v10_0_eop_irq_funcs;
8971
8972         adev->gfx.kiq.irq.num_types = AMDGPU_CP_KIQ_IRQ_LAST;
8973         adev->gfx.kiq.irq.funcs = &gfx_v10_0_kiq_irq_funcs;
8974
8975         adev->gfx.priv_reg_irq.num_types = 1;
8976         adev->gfx.priv_reg_irq.funcs = &gfx_v10_0_priv_reg_irq_funcs;
8977
8978         adev->gfx.priv_inst_irq.num_types = 1;
8979         adev->gfx.priv_inst_irq.funcs = &gfx_v10_0_priv_inst_irq_funcs;
8980 }
8981
8982 static void gfx_v10_0_set_rlc_funcs(struct amdgpu_device *adev)
8983 {
8984         switch (adev->asic_type) {
8985         case CHIP_NAVI10:
8986         case CHIP_NAVI14:
8987         case CHIP_SIENNA_CICHLID:
8988         case CHIP_NAVY_FLOUNDER:
8989         case CHIP_VANGOGH:
8990         case CHIP_DIMGREY_CAVEFISH:
8991                 adev->gfx.rlc.funcs = &gfx_v10_0_rlc_funcs;
8992                 break;
8993         case CHIP_NAVI12:
8994                 adev->gfx.rlc.funcs = &gfx_v10_0_rlc_funcs_sriov;
8995                 break;
8996         default:
8997                 break;
8998         }
8999 }
9000
9001 static void gfx_v10_0_set_gds_init(struct amdgpu_device *adev)
9002 {
9003         unsigned total_cu = adev->gfx.config.max_cu_per_sh *
9004                             adev->gfx.config.max_sh_per_se *
9005                             adev->gfx.config.max_shader_engines;
9006
9007         adev->gds.gds_size = 0x10000;
9008         adev->gds.gds_compute_max_wave_id = total_cu * 32 - 1;
9009         adev->gds.gws_size = 64;
9010         adev->gds.oa_size = 16;
9011 }
9012
9013 static void gfx_v10_0_set_user_wgp_inactive_bitmap_per_sh(struct amdgpu_device *adev,
9014                                                           u32 bitmap)
9015 {
9016         u32 data;
9017
9018         if (!bitmap)
9019                 return;
9020
9021         data = bitmap << GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT;
9022         data &= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK;
9023
9024         WREG32_SOC15(GC, 0, mmGC_USER_SHADER_ARRAY_CONFIG, data);
9025 }
9026
9027 static u32 gfx_v10_0_get_wgp_active_bitmap_per_sh(struct amdgpu_device *adev)
9028 {
9029         u32 data, wgp_bitmask;
9030         data = RREG32_SOC15(GC, 0, mmCC_GC_SHADER_ARRAY_CONFIG);
9031         data |= RREG32_SOC15(GC, 0, mmGC_USER_SHADER_ARRAY_CONFIG);
9032
9033         data &= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK;
9034         data >>= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT;
9035
9036         wgp_bitmask =
9037                 amdgpu_gfx_create_bitmask(adev->gfx.config.max_cu_per_sh >> 1);
9038
9039         return (~data) & wgp_bitmask;
9040 }
9041
9042 static u32 gfx_v10_0_get_cu_active_bitmap_per_sh(struct amdgpu_device *adev)
9043 {
9044         u32 wgp_idx, wgp_active_bitmap;
9045         u32 cu_bitmap_per_wgp, cu_active_bitmap;
9046
9047         wgp_active_bitmap = gfx_v10_0_get_wgp_active_bitmap_per_sh(adev);
9048         cu_active_bitmap = 0;
9049
9050         for (wgp_idx = 0; wgp_idx < 16; wgp_idx++) {
9051                 /* if there is one WGP enabled, it means 2 CUs will be enabled */
9052                 cu_bitmap_per_wgp = 3 << (2 * wgp_idx);
9053                 if (wgp_active_bitmap & (1 << wgp_idx))
9054                         cu_active_bitmap |= cu_bitmap_per_wgp;
9055         }
9056
9057         return cu_active_bitmap;
9058 }
9059
9060 static int gfx_v10_0_get_cu_info(struct amdgpu_device *adev,
9061                                  struct amdgpu_cu_info *cu_info)
9062 {
9063         int i, j, k, counter, active_cu_number = 0;
9064         u32 mask, bitmap, ao_bitmap, ao_cu_mask = 0;
9065         unsigned disable_masks[4 * 2];
9066
9067         if (!adev || !cu_info)
9068                 return -EINVAL;
9069
9070         amdgpu_gfx_parse_disable_cu(disable_masks, 4, 2);
9071
9072         mutex_lock(&adev->grbm_idx_mutex);
9073         for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
9074                 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
9075                         bitmap = i * adev->gfx.config.max_sh_per_se + j;
9076                         if ((adev->asic_type == CHIP_SIENNA_CICHLID) &&
9077                             ((gfx_v10_3_get_disabled_sa(adev) >> bitmap) & 1))
9078                                 continue;
9079                         mask = 1;
9080                         ao_bitmap = 0;
9081                         counter = 0;
9082                         gfx_v10_0_select_se_sh(adev, i, j, 0xffffffff);
9083                         if (i < 4 && j < 2)
9084                                 gfx_v10_0_set_user_wgp_inactive_bitmap_per_sh(
9085                                         adev, disable_masks[i * 2 + j]);
9086                         bitmap = gfx_v10_0_get_cu_active_bitmap_per_sh(adev);
9087                         cu_info->bitmap[i][j] = bitmap;
9088
9089                         for (k = 0; k < adev->gfx.config.max_cu_per_sh; k++) {
9090                                 if (bitmap & mask) {
9091                                         if (counter < adev->gfx.config.max_cu_per_sh)
9092                                                 ao_bitmap |= mask;
9093                                         counter++;
9094                                 }
9095                                 mask <<= 1;
9096                         }
9097                         active_cu_number += counter;
9098                         if (i < 2 && j < 2)
9099                                 ao_cu_mask |= (ao_bitmap << (i * 16 + j * 8));
9100                         cu_info->ao_cu_bitmap[i][j] = ao_bitmap;
9101                 }
9102         }
9103         gfx_v10_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
9104         mutex_unlock(&adev->grbm_idx_mutex);
9105
9106         cu_info->number = active_cu_number;
9107         cu_info->ao_cu_mask = ao_cu_mask;
9108         cu_info->simd_per_cu = NUM_SIMD_PER_CU;
9109
9110         return 0;
9111 }
9112
9113 static u32 gfx_v10_3_get_disabled_sa(struct amdgpu_device *adev)
9114 {
9115         uint32_t efuse_setting, vbios_setting, disabled_sa, max_sa_mask;
9116
9117         efuse_setting = RREG32_SOC15(GC, 0, mmCC_GC_SA_UNIT_DISABLE);
9118         efuse_setting &= CC_GC_SA_UNIT_DISABLE__SA_DISABLE_MASK;
9119         efuse_setting >>= CC_GC_SA_UNIT_DISABLE__SA_DISABLE__SHIFT;
9120
9121         vbios_setting = RREG32_SOC15(GC, 0, mmGC_USER_SA_UNIT_DISABLE);
9122         vbios_setting &= GC_USER_SA_UNIT_DISABLE__SA_DISABLE_MASK;
9123         vbios_setting >>= GC_USER_SA_UNIT_DISABLE__SA_DISABLE__SHIFT;
9124
9125         max_sa_mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_sh_per_se *
9126                                                 adev->gfx.config.max_shader_engines);
9127         disabled_sa = efuse_setting | vbios_setting;
9128         disabled_sa &= max_sa_mask;
9129
9130         return disabled_sa;
9131 }
9132
9133 static void gfx_v10_3_program_pbb_mode(struct amdgpu_device *adev)
9134 {
9135         uint32_t max_sa_per_se, max_sa_per_se_mask, max_shader_engines;
9136         uint32_t disabled_sa_mask, se_index, disabled_sa_per_se;
9137
9138         disabled_sa_mask = gfx_v10_3_get_disabled_sa(adev);
9139
9140         max_sa_per_se = adev->gfx.config.max_sh_per_se;
9141         max_sa_per_se_mask = (1 << max_sa_per_se) - 1;
9142         max_shader_engines = adev->gfx.config.max_shader_engines;
9143
9144         for (se_index = 0; max_shader_engines > se_index; se_index++) {
9145                 disabled_sa_per_se = disabled_sa_mask >> (se_index * max_sa_per_se);
9146                 disabled_sa_per_se &= max_sa_per_se_mask;
9147                 if (disabled_sa_per_se == max_sa_per_se_mask) {
9148                         WREG32_FIELD15(GC, 0, PA_SC_ENHANCE_3, FORCE_PBB_WORKLOAD_MODE_TO_ZERO, 1);
9149                         break;
9150                 }
9151         }
9152 }
9153
9154 const struct amdgpu_ip_block_version gfx_v10_0_ip_block =
9155 {
9156         .type = AMD_IP_BLOCK_TYPE_GFX,
9157         .major = 10,
9158         .minor = 0,
9159         .rev = 0,
9160         .funcs = &gfx_v10_0_ip_funcs,
9161 };