drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

   1 /*
   2  * Copyright 2019 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #include <linux/delay.h>
  25 #include <linux/kernel.h>
  26 #include <linux/firmware.h>
  27 #include <linux/module.h>
  28 #include <linux/pci.h>
  29 #include "amdgpu.h"
  30 #include "amdgpu_gfx.h"
  31 #include "amdgpu_psp.h"
  32 #include "nv.h"
  33 #include "nvd.h"
  34
  35 #include "gc/gc_10_1_0_offset.h"
  36 #include "gc/gc_10_1_0_sh_mask.h"
  37 #include "smuio/smuio_11_0_0_offset.h"
  38 #include "smuio/smuio_11_0_0_sh_mask.h"
  39 #include "navi10_enum.h"
  40 #include "ivsrcid/gfx/irqsrcs_gfx_10_1.h"
  41
  42 #include "soc15.h"
  43 #include "soc15d.h"
  44 #include "soc15_common.h"
  45 #include "clearstate_gfx10.h"
  46 #include "v10_structs.h"
  47 #include "gfx_v10_0.h"
  48 #include "nbio_v2_3.h"
  49
  50 /*
  51  * Navi10 has two graphic rings to share each graphic pipe.
  52  * 1. Primary ring
  53  * 2. Async ring
  54  */
  55 #define GFX10_NUM_GFX_RINGS_NV1X        1
  56 #define GFX10_NUM_GFX_RINGS_Sienna_Cichlid      2
  57 #define GFX10_MEC_HPD_SIZE      2048
  58
  59 #define F32_CE_PROGRAM_RAM_SIZE         65536
  60 #define RLCG_UCODE_LOADING_START_ADDRESS        0x00002000L
  61
  62 #define mmCGTT_GS_NGG_CLK_CTRL  0x5087
  63 #define mmCGTT_GS_NGG_CLK_CTRL_BASE_IDX 1
  64 #define mmCGTT_SPI_RA0_CLK_CTRL 0x507a
  65 #define mmCGTT_SPI_RA0_CLK_CTRL_BASE_IDX 1
  66 #define mmCGTT_SPI_RA1_CLK_CTRL 0x507b
  67 #define mmCGTT_SPI_RA1_CLK_CTRL_BASE_IDX 1
  68
  69 #define GB_ADDR_CONFIG__NUM_PKRS__SHIFT                                                                       0x8
  70 #define GB_ADDR_CONFIG__NUM_PKRS_MASK                                                                         0x00000700L
  71
  72 #define mmCGTS_TCC_DISABLE_gc_10_3                 0x5006
  73 #define mmCGTS_TCC_DISABLE_gc_10_3_BASE_IDX        1
  74 #define mmCGTS_USER_TCC_DISABLE_gc_10_3            0x5007
  75 #define mmCGTS_USER_TCC_DISABLE_gc_10_3_BASE_IDX   1
  76
  77 #define mmCP_MEC_CNTL_Sienna_Cichlid                      0x0f55
  78 #define mmCP_MEC_CNTL_Sienna_Cichlid_BASE_IDX             0
  79 #define mmRLC_SAFE_MODE_Sienna_Cichlid                  0x4ca0
  80 #define mmRLC_SAFE_MODE_Sienna_Cichlid_BASE_IDX         1
  81 #define mmRLC_CP_SCHEDULERS_Sienna_Cichlid              0x4ca1
  82 #define mmRLC_CP_SCHEDULERS_Sienna_Cichlid_BASE_IDX     1
  83 #define mmSPI_CONFIG_CNTL_Sienna_Cichlid                        0x11ec
  84 #define mmSPI_CONFIG_CNTL_Sienna_Cichlid_BASE_IDX               0
  85 #define mmVGT_ESGS_RING_SIZE_Sienna_Cichlid             0x0fc1
  86 #define mmVGT_ESGS_RING_SIZE_Sienna_Cichlid_BASE_IDX    0
  87 #define mmVGT_GSVS_RING_SIZE_Sienna_Cichlid             0x0fc2
  88 #define mmVGT_GSVS_RING_SIZE_Sienna_Cichlid_BASE_IDX    0
  89 #define mmVGT_TF_RING_SIZE_Sienna_Cichlid                       0x0fc3
  90 #define mmVGT_TF_RING_SIZE_Sienna_Cichlid_BASE_IDX      0
  91 #define mmVGT_HS_OFFCHIP_PARAM_Sienna_Cichlid           0x0fc4
  92 #define mmVGT_HS_OFFCHIP_PARAM_Sienna_Cichlid_BASE_IDX  0
  93 #define mmVGT_TF_MEMORY_BASE_Sienna_Cichlid             0x0fc5
  94 #define mmVGT_TF_MEMORY_BASE_Sienna_Cichlid_BASE_IDX    0
  95 #define mmVGT_TF_MEMORY_BASE_HI_Sienna_Cichlid          0x0fc6
  96 #define mmVGT_TF_MEMORY_BASE_HI_Sienna_Cichlid_BASE_IDX 0
  97 #define GRBM_STATUS2__RLC_BUSY_Sienna_Cichlid__SHIFT    0x1a
  98 #define GRBM_STATUS2__RLC_BUSY_Sienna_Cichlid_MASK      0x04000000L
  99 #define CP_RB_DOORBELL_RANGE_LOWER__DOORBELL_RANGE_LOWER_Sienna_Cichlid_MASK    0x00000FFCL
 100 #define CP_RB_DOORBELL_RANGE_LOWER__DOORBELL_RANGE_LOWER_Sienna_Cichlid__SHIFT  0x2
 101 #define CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_Sienna_Cichlid_MASK    0x00000FFCL
 102 #define mmGCR_GENERAL_CNTL_Sienna_Cichlid                       0x1580
 103 #define mmGCR_GENERAL_CNTL_Sienna_Cichlid_BASE_IDX      0
 104
 105 #define mmGOLDEN_TSC_COUNT_UPPER_Cyan_Skillfish                0x0105
 106 #define mmGOLDEN_TSC_COUNT_UPPER_Cyan_Skillfish_BASE_IDX       1
 107 #define mmGOLDEN_TSC_COUNT_LOWER_Cyan_Skillfish                0x0106
 108 #define mmGOLDEN_TSC_COUNT_LOWER_Cyan_Skillfish_BASE_IDX       1
 109
 110 #define mmGOLDEN_TSC_COUNT_UPPER_Vangogh                0x0025
 111 #define mmGOLDEN_TSC_COUNT_UPPER_Vangogh_BASE_IDX       1
 112 #define mmGOLDEN_TSC_COUNT_LOWER_Vangogh                0x0026
 113 #define mmGOLDEN_TSC_COUNT_LOWER_Vangogh_BASE_IDX       1
 114
 115 #define mmGOLDEN_TSC_COUNT_UPPER_GC_10_3_6                0x002d
 116 #define mmGOLDEN_TSC_COUNT_UPPER_GC_10_3_6_BASE_IDX       1
 117 #define mmGOLDEN_TSC_COUNT_LOWER_GC_10_3_6                0x002e
 118 #define mmGOLDEN_TSC_COUNT_LOWER_GC_10_3_6_BASE_IDX       1
 119
 120 #define mmSPI_CONFIG_CNTL_1_Vangogh              0x2441
 121 #define mmSPI_CONFIG_CNTL_1_Vangogh_BASE_IDX     1
 122 #define mmVGT_TF_MEMORY_BASE_HI_Vangogh          0x2261
 123 #define mmVGT_TF_MEMORY_BASE_HI_Vangogh_BASE_IDX 1
 124 #define mmVGT_HS_OFFCHIP_PARAM_Vangogh           0x224f
 125 #define mmVGT_HS_OFFCHIP_PARAM_Vangogh_BASE_IDX  1
 126 #define mmVGT_TF_RING_SIZE_Vangogh               0x224e
 127 #define mmVGT_TF_RING_SIZE_Vangogh_BASE_IDX      1
 128 #define mmVGT_GSVS_RING_SIZE_Vangogh             0x2241
 129 #define mmVGT_GSVS_RING_SIZE_Vangogh_BASE_IDX    1
 130 #define mmVGT_TF_MEMORY_BASE_Vangogh             0x2250
 131 #define mmVGT_TF_MEMORY_BASE_Vangogh_BASE_IDX    1
 132 #define mmVGT_ESGS_RING_SIZE_Vangogh             0x2240
 133 #define mmVGT_ESGS_RING_SIZE_Vangogh_BASE_IDX    1
 134 #define mmSPI_CONFIG_CNTL_Vangogh                0x2440
 135 #define mmSPI_CONFIG_CNTL_Vangogh_BASE_IDX       1
 136 #define mmGCR_GENERAL_CNTL_Vangogh               0x1580
 137 #define mmGCR_GENERAL_CNTL_Vangogh_BASE_IDX      0
 138 #define RLC_PG_DELAY_3__CGCG_ACTIVE_BEFORE_CGPG_MASK_Vangogh   0x0000FFFFL
 139
 140 #define mmCP_HYP_PFP_UCODE_ADDR                 0x5814
 141 #define mmCP_HYP_PFP_UCODE_ADDR_BASE_IDX        1
 142 #define mmCP_HYP_PFP_UCODE_DATA                 0x5815
 143 #define mmCP_HYP_PFP_UCODE_DATA_BASE_IDX        1
 144 #define mmCP_HYP_CE_UCODE_ADDR                  0x5818
 145 #define mmCP_HYP_CE_UCODE_ADDR_BASE_IDX         1
 146 #define mmCP_HYP_CE_UCODE_DATA                  0x5819
 147 #define mmCP_HYP_CE_UCODE_DATA_BASE_IDX         1
 148 #define mmCP_HYP_ME_UCODE_ADDR                  0x5816
 149 #define mmCP_HYP_ME_UCODE_ADDR_BASE_IDX         1
 150 #define mmCP_HYP_ME_UCODE_DATA                  0x5817
 151 #define mmCP_HYP_ME_UCODE_DATA_BASE_IDX         1
 152
 153 #define mmCPG_PSP_DEBUG                         0x5c10
 154 #define mmCPG_PSP_DEBUG_BASE_IDX                1
 155 #define mmCPC_PSP_DEBUG                         0x5c11
 156 #define mmCPC_PSP_DEBUG_BASE_IDX                1
 157 #define CPC_PSP_DEBUG__GPA_OVERRIDE_MASK        0x00000008L
 158 #define CPG_PSP_DEBUG__GPA_OVERRIDE_MASK        0x00000008L
 159
 160 //CC_GC_SA_UNIT_DISABLE
 161 #define mmCC_GC_SA_UNIT_DISABLE                 0x0fe9
 162 #define mmCC_GC_SA_UNIT_DISABLE_BASE_IDX        0
 163 #define CC_GC_SA_UNIT_DISABLE__SA_DISABLE__SHIFT        0x8
 164 #define CC_GC_SA_UNIT_DISABLE__SA_DISABLE_MASK          0x0000FF00L
 165 //GC_USER_SA_UNIT_DISABLE
 166 #define mmGC_USER_SA_UNIT_DISABLE               0x0fea
 167 #define mmGC_USER_SA_UNIT_DISABLE_BASE_IDX      0
 168 #define GC_USER_SA_UNIT_DISABLE__SA_DISABLE__SHIFT      0x8
 169 #define GC_USER_SA_UNIT_DISABLE__SA_DISABLE_MASK        0x0000FF00L
 170 //PA_SC_ENHANCE_3
 171 #define mmPA_SC_ENHANCE_3                       0x1085
 172 #define mmPA_SC_ENHANCE_3_BASE_IDX              0
 173 #define PA_SC_ENHANCE_3__FORCE_PBB_WORKLOAD_MODE_TO_ZERO__SHIFT 0x3
 174 #define PA_SC_ENHANCE_3__FORCE_PBB_WORKLOAD_MODE_TO_ZERO_MASK   0x00000008L
 175
 176 #define mmCGTT_SPI_CS_CLK_CTRL                  0x507c
 177 #define mmCGTT_SPI_CS_CLK_CTRL_BASE_IDX         1
 178
 179 #define mmGCUTCL2_CGTT_CLK_CTRL_Sienna_Cichlid          0x16f3
 180 #define mmGCUTCL2_CGTT_CLK_CTRL_Sienna_Cichlid_BASE_IDX 0
 181 #define mmGCVM_L2_CGTT_CLK_CTRL_Sienna_Cichlid          0x15db
 182 #define mmGCVM_L2_CGTT_CLK_CTRL_Sienna_Cichlid_BASE_IDX 0
 183
 184 #define mmGC_THROTTLE_CTRL_Sienna_Cichlid              0x2030
 185 #define mmGC_THROTTLE_CTRL_Sienna_Cichlid_BASE_IDX     0
 186
 187 #define mmRLC_SPARE_INT_0_Sienna_Cichlid               0x4ca5
 188 #define mmRLC_SPARE_INT_0_Sienna_Cichlid_BASE_IDX      1
 189
 190 MODULE_FIRMWARE("amdgpu/navi10_ce.bin");
 191 MODULE_FIRMWARE("amdgpu/navi10_pfp.bin");
 192 MODULE_FIRMWARE("amdgpu/navi10_me.bin");
 193 MODULE_FIRMWARE("amdgpu/navi10_mec.bin");
 194 MODULE_FIRMWARE("amdgpu/navi10_mec2.bin");
 195 MODULE_FIRMWARE("amdgpu/navi10_rlc.bin");
 196
 197 MODULE_FIRMWARE("amdgpu/navi14_ce_wks.bin");
 198 MODULE_FIRMWARE("amdgpu/navi14_pfp_wks.bin");
 199 MODULE_FIRMWARE("amdgpu/navi14_me_wks.bin");
 200 MODULE_FIRMWARE("amdgpu/navi14_mec_wks.bin");
 201 MODULE_FIRMWARE("amdgpu/navi14_mec2_wks.bin");
 202 MODULE_FIRMWARE("amdgpu/navi14_ce.bin");
 203 MODULE_FIRMWARE("amdgpu/navi14_pfp.bin");
 204 MODULE_FIRMWARE("amdgpu/navi14_me.bin");
 205 MODULE_FIRMWARE("amdgpu/navi14_mec.bin");
 206 MODULE_FIRMWARE("amdgpu/navi14_mec2.bin");
 207 MODULE_FIRMWARE("amdgpu/navi14_rlc.bin");
 208
 209 MODULE_FIRMWARE("amdgpu/navi12_ce.bin");
 210 MODULE_FIRMWARE("amdgpu/navi12_pfp.bin");
 211 MODULE_FIRMWARE("amdgpu/navi12_me.bin");
 212 MODULE_FIRMWARE("amdgpu/navi12_mec.bin");
 213 MODULE_FIRMWARE("amdgpu/navi12_mec2.bin");
 214 MODULE_FIRMWARE("amdgpu/navi12_rlc.bin");
 215
 216 MODULE_FIRMWARE("amdgpu/sienna_cichlid_ce.bin");
 217 MODULE_FIRMWARE("amdgpu/sienna_cichlid_pfp.bin");
 218 MODULE_FIRMWARE("amdgpu/sienna_cichlid_me.bin");
 219 MODULE_FIRMWARE("amdgpu/sienna_cichlid_mec.bin");
 220 MODULE_FIRMWARE("amdgpu/sienna_cichlid_mec2.bin");
 221 MODULE_FIRMWARE("amdgpu/sienna_cichlid_rlc.bin");
 222
 223 MODULE_FIRMWARE("amdgpu/navy_flounder_ce.bin");
 224 MODULE_FIRMWARE("amdgpu/navy_flounder_pfp.bin");
 225 MODULE_FIRMWARE("amdgpu/navy_flounder_me.bin");
 226 MODULE_FIRMWARE("amdgpu/navy_flounder_mec.bin");
 227 MODULE_FIRMWARE("amdgpu/navy_flounder_mec2.bin");
 228 MODULE_FIRMWARE("amdgpu/navy_flounder_rlc.bin");
 229
 230 MODULE_FIRMWARE("amdgpu/vangogh_ce.bin");
 231 MODULE_FIRMWARE("amdgpu/vangogh_pfp.bin");
 232 MODULE_FIRMWARE("amdgpu/vangogh_me.bin");
 233 MODULE_FIRMWARE("amdgpu/vangogh_mec.bin");
 234 MODULE_FIRMWARE("amdgpu/vangogh_mec2.bin");
 235 MODULE_FIRMWARE("amdgpu/vangogh_rlc.bin");
 236
 237 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_ce.bin");
 238 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_pfp.bin");
 239 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_me.bin");
 240 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_mec.bin");
 241 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_mec2.bin");
 242 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_rlc.bin");
 243
 244 MODULE_FIRMWARE("amdgpu/beige_goby_ce.bin");
 245 MODULE_FIRMWARE("amdgpu/beige_goby_pfp.bin");
 246 MODULE_FIRMWARE("amdgpu/beige_goby_me.bin");
 247 MODULE_FIRMWARE("amdgpu/beige_goby_mec.bin");
 248 MODULE_FIRMWARE("amdgpu/beige_goby_mec2.bin");
 249 MODULE_FIRMWARE("amdgpu/beige_goby_rlc.bin");
 250
 251 MODULE_FIRMWARE("amdgpu/yellow_carp_ce.bin");
 252 MODULE_FIRMWARE("amdgpu/yellow_carp_pfp.bin");
 253 MODULE_FIRMWARE("amdgpu/yellow_carp_me.bin");
 254 MODULE_FIRMWARE("amdgpu/yellow_carp_mec.bin");
 255 MODULE_FIRMWARE("amdgpu/yellow_carp_mec2.bin");
 256 MODULE_FIRMWARE("amdgpu/yellow_carp_rlc.bin");
 257
 258 MODULE_FIRMWARE("amdgpu/cyan_skillfish2_ce.bin");
 259 MODULE_FIRMWARE("amdgpu/cyan_skillfish2_pfp.bin");
 260 MODULE_FIRMWARE("amdgpu/cyan_skillfish2_me.bin");
 261 MODULE_FIRMWARE("amdgpu/cyan_skillfish2_mec.bin");
 262 MODULE_FIRMWARE("amdgpu/cyan_skillfish2_mec2.bin");
 263 MODULE_FIRMWARE("amdgpu/cyan_skillfish2_rlc.bin");
 264
 265 MODULE_FIRMWARE("amdgpu/gc_10_3_6_ce.bin");
 266 MODULE_FIRMWARE("amdgpu/gc_10_3_6_pfp.bin");
 267 MODULE_FIRMWARE("amdgpu/gc_10_3_6_me.bin");
 268 MODULE_FIRMWARE("amdgpu/gc_10_3_6_mec.bin");
 269 MODULE_FIRMWARE("amdgpu/gc_10_3_6_mec2.bin");
 270 MODULE_FIRMWARE("amdgpu/gc_10_3_6_rlc.bin");
 271
 272 MODULE_FIRMWARE("amdgpu/gc_10_3_7_ce.bin");
 273 MODULE_FIRMWARE("amdgpu/gc_10_3_7_pfp.bin");
 274 MODULE_FIRMWARE("amdgpu/gc_10_3_7_me.bin");
 275 MODULE_FIRMWARE("amdgpu/gc_10_3_7_mec.bin");
 276 MODULE_FIRMWARE("amdgpu/gc_10_3_7_mec2.bin");
 277 MODULE_FIRMWARE("amdgpu/gc_10_3_7_rlc.bin");
 278
 279 static const struct soc15_reg_golden golden_settings_gc_10_1[] = {
 280         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0xffffffff, 0x00400014),
 281         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_CPF_CLK_CTRL, 0xfcff8fff, 0xf8000100),
 282         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xcd000000, 0x0d000100),
 283         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQ_CLK_CTRL, 0x60000ff0, 0x60000100),
 284         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQG_CLK_CTRL, 0x40000000, 0x40000100),
 285         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xffff8fff, 0xffff8100),
 286         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_WD_CLK_CTRL, 0xfeff8fff, 0xfeff8100),
 287         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
 288         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_VC5_ENABLE, 0x00000002, 0x00000000),
 289         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0x000007ff, 0x000005ff),
 290         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG, 0x20000000, 0x20000000),
 291         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xffffffff, 0x00000420),
 292         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0x00000200, 0x00000200),
 293         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0x07900000, 0x04900000),
 294         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DFSM_TILES_IN_FLIGHT, 0x0000ffff, 0x0000003f),
 295         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_LAST_OF_BURST_CONFIG, 0xffffffff, 0x03860204),
 296         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff0ffff, 0x00000500),
 297         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PRIV_CONTROL, 0x000007ff, 0x000001fe),
 298         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
 299         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x10321032),
 300         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x02310231),
 301         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
 302         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
 303         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CGTT_SCLK_CTRL, 0x10000000, 0x10000100),
 304         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL2, 0xffffffff, 0x1402002f),
 305         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xffff9fff, 0x00001188),
 306         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
 307         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x08000009),
 308         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0x00400000, 0x04440000),
 309         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0x00000800, 0x00000820),
 310         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000),
 311         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0xffffffff, 0xffff3101),
 312         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0x001f0000, 0x00070104),
 313         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ALU_CLK_CTRL, 0xffffffff, 0xffffffff),
 314         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x00000100, 0x00000130),
 315         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0xffffffff, 0xffffffff),
 316         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
 317         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CNTL, 0x60000010, 0x479c0010),
 318         SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CGTT_CLK_CTRL, 0xfeff0fff, 0x40000100),
 319         SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0x00c00000, 0x00c00000)
 320 };
 321
 322 static const struct soc15_reg_golden golden_settings_gc_10_0_nv10[] = {
 323         /* Pending on emulation bring up */
 324 };
 325
 326 static const struct soc15_reg_golden golden_settings_gc_rlc_spm_10_0_nv10[] = {
 327         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xe0000000, 0x0),
 328         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 329         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
 330         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 331         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
 332         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 333         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
 334         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 335         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
 336         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 337         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
 338         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 339         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
 340         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 341         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
 342         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 343         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 344         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 345         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8),
 346         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 347         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
 348         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 349         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc),
 350         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 351         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
 352         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 353         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0),
 354         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 355         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
 356         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 357         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4),
 358         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 359         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
 360         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 361         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
 362         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 363         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
 364         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 365         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
 366         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 367         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
 368         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 369         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
 370         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 371         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
 372         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 373         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
 374         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 375         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
 376         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 377         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
 378         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 379         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
 380         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 381         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
 382         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 383         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
 384         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 385         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
 386         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 387         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
 388         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 389         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
 390         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 391         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
 392         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 393         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
 394         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 395         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
 396         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 397         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0),
 398         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 399         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
 400         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 401         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4),
 402         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 403         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
 404         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 405         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8),
 406         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 407         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 408         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 409         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc),
 410         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 411         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
 412         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 413         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0),
 414         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 415         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 416         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 417         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4),
 418         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 419         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 420         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 421         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90),
 422         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 423         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
 424         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 425         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94),
 426         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 427         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
 428         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 429         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98),
 430         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 431         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
 432         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 433         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c),
 434         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 435         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
 436         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 437         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0),
 438         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 439         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
 440         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 441         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4),
 442         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 443         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
 444         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 445         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8),
 446         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 447         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
 448         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 449         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac),
 450         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 451         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
 452         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 453         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
 454         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 455         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
 456         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 457         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
 458         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 459         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
 460         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 461         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
 462         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 463         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
 464         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 465         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
 466         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 467         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
 468         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 469         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
 470         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 471         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
 472         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 473         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
 474         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 475         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 476         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 477         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
 478         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 479         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
 480         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 481         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
 482         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 483         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
 484         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 485         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
 486         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 487         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
 488         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 489         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
 490         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 491         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
 492         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 493         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
 494         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 495         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
 496         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 497         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
 498         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 499         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
 500         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 501         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
 502         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 503         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
 504         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 505         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
 506         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 507         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
 508         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 509         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
 510         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 511         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
 512         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 513         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
 514         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 515         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
 516         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 517         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
 518         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 519         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
 520         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 521         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
 522         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 523         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
 524         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 525         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
 526         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 527         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
 528         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 529         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
 530         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 531         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
 532         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 533         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
 534         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 535         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
 536         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 537         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
 538         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 539         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
 540         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 541         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
 542         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 543         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
 544         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 545         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c),
 546         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 547         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
 548         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 549         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
 550         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 551         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 552         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 553         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
 554         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 555         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
 556         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 557         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
 558         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 559         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
 560         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 561         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
 562         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 563         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
 564         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 565         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
 566         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 567         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
 568         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 569         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
 570         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 571         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 572         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 573         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
 574         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 575         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 576         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 577         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
 578         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 579         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
 580         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 581         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
 582         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 583         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
 584         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 585         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
 586         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 587         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 588         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 589         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
 590         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 591         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 592         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 593         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
 594         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 595         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
 596         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 597         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
 598         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 599         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
 600         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 601         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
 602         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 603         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 604         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 605         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
 606         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 607         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 608         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 609         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
 610         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 611         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
 612         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 613         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
 614         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 615         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
 616         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 617         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
 618         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 619         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
 620         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 621         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
 622         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 623         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
 624         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 625         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
 626         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 627         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 628         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 629         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
 630         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 631         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 632         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 633         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
 634         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 635         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 636         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 637         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
 638         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 639         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 640         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 641         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
 642         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 643         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 644         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 645         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
 646         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 647         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 648         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 649         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
 650         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 651         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 652         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 653         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
 654         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 655         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 656         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 657         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
 658         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 659         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
 660         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 661         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
 662         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 663         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
 664         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 665         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
 666         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 667         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
 668         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 669         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
 670         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 671         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
 672         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 673         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
 674         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 675         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
 676         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 677         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
 678         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 679         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
 680         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 681         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
 682         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 683         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
 684         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 685         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
 686         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 687         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
 688         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 689         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
 690         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 691         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
 692         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 693         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
 694         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 695         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
 696         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 697         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
 698         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 699         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17),
 700         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 701         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
 702         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 703         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17),
 704         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 705         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
 706         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 707         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 708         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 709         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
 710         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 711         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 712         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 713         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
 714         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 715         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
 716         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 717         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
 718         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 719         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
 720         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 721         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
 722         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 723         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
 724         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 725         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
 726         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 727         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
 728         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 729         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
 730         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 731         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 732         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 733         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
 734         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 735         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 736         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 737         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
 738         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 739         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 740         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 741         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
 742         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 743         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 744         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 745         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
 746         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 747         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
 748         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 749         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
 750         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 751         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
 752         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 753         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
 754         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 755         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
 756         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 757         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
 758         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 759         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
 760         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 761         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
 762         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 763         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 764         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 765         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
 766         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 767         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 768         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 769         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
 770         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 771         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 772         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 773         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
 774         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 775         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 776         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 777         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
 778         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 779         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 780         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 781         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
 782         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 783         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 784         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 785         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
 786         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 787         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 788         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 789         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
 790         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 791         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 792         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 793         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
 794         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 795         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 796         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 797         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
 798         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 799         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 800         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 801         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90),
 802         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 803         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
 804         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 805         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90),
 806         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 807         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
 808         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 809         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94),
 810         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 811         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
 812         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 813         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94),
 814         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 815         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
 816         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 817         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0),
 818         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 819         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
 820         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 821         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0),
 822         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 823         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
 824         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 825         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4),
 826         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 827         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
 828         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 829         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4),
 830         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 831         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
 832         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 833         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98),
 834         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 835         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
 836         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 837         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98),
 838         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 839         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
 840         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 841         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c),
 842         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 843         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
 844         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 845         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c),
 846         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 847         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
 848         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 849         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8),
 850         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 851         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 852         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 853         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8),
 854         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 855         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 856         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 857         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac),
 858         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 859         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 860         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 861         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac),
 862         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 863         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 864         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 865         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8),
 866         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 867         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
 868         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 869         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8),
 870         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 871         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
 872         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 873         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc),
 874         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 875         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
 876         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 877         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc),
 878         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 879         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
 880         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 881         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0),
 882         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 883         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 884         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 885         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0),
 886         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 887         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 888         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 889         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4),
 890         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 891         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 892         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 893         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4),
 894         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 895         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 896         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 897         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0),
 898         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 899         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
 900         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 901         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0),
 902         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 903         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
 904         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 905         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4),
 906         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 907         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 908         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 909         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4),
 910         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 911         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 912         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 913         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0),
 914         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 915         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
 916         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 917         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0),
 918         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 919         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
 920         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 921         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4),
 922         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 923         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
 924         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 925         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4),
 926         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 927         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
 928         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 929         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8),
 930         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 931         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
 932         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 933         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8),
 934         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 935         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
 936         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 937         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc),
 938         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 939         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
 940         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 941         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc),
 942         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 943         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
 944         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 945         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8),
 946         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 947         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 948         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 949         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8),
 950         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 951         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 952         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 953         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec),
 954         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 955         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 956         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 957         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec),
 958         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 959         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 960         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 961         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0),
 962         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 963         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
 964         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 965         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0),
 966         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 967         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
 968         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 969         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4),
 970         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 971         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
 972         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 973         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4),
 974         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 975         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
 976         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 977         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8),
 978         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 979         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 980         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 981         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8),
 982         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 983         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 984         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 985         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xfc),
 986         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 987         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 988         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 989         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xfc),
 990         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 991         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 992         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 993         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100),
 994         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 995         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 996         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 997         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100),
 998         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 999         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1000         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1001         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104),
1002         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1003         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1004         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1005         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104),
1006         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1007         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1008         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1009         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0),
1010         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1011         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
1012         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1013         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0),
1014         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1015         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
1016         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1017         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118),
1018         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1019         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
1020         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1021         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118),
1022         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1023         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
1024         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1025         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c),
1026         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1027         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
1028         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1029         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c),
1030         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1031         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
1032         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1033         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120),
1034         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1035         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
1036         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1037         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120),
1038         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1039         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
1040         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1041         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124),
1042         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1043         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
1044         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1045         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124),
1046         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1047         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
1048         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1049         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc),
1050         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1051         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
1052         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1053         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc),
1054         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1055         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
1056         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1057         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110),
1058         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1059         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1060         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1061         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110),
1062         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1063         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1064         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1065         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114),
1066         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1067         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1068         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1069         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114),
1070         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1071         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1072         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1073         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108),
1074         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1075         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1076         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1077         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108),
1078         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1079         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1080         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1081         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c),
1082         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1083         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1084         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1085         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c),
1086         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1087         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1088         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1089         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8),
1090         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1091         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17),
1092         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1093         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8),
1094         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1095         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17),
1096         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1097         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128),
1098         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1099         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
1100         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1101         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128),
1102         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1103         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
1104         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1105         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c),
1106         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1107         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1108         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1109         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c),
1110         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1111         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1112         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1113         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138),
1114         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1115         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1116         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1117         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138),
1118         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1119         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1120         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1121         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c),
1122         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1123         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1124         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1125         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c),
1126         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1127         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1128         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1129         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130),
1130         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1131         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1132         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1133         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130),
1134         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1135         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1136         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1137         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134),
1138         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1139         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1140         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1141         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134),
1142         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1143         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1144         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1145         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140),
1146         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1147         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1148         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1149         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140),
1150         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1151         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1152         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1153         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144),
1154         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1155         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
1156         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1157         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144),
1158         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1159         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
1160         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1161         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150),
1162         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1163         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1164         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1165         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150),
1166         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1167         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1168         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1169         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154),
1170         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1171         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
1172         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1173         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154),
1174         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1175         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
1176         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1177         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148),
1178         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1179         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1180         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1181         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148),
1182         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1183         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1184         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1185         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c),
1186         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1187         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
1188         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1189         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c),
1190         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1191         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
1192         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1193         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158),
1194         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1195         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
1196         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1197         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158),
1198         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1199         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
1200         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1201         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c),
1202         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1203         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1204         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1205         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c),
1206         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1207         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1208         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1209         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168),
1210         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1211         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1),
1212         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1213         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168),
1214         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1215         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1),
1216         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1217         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c),
1218         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1219         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
1220         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1221         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c),
1222         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1223         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
1224         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1225         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160),
1226         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1227         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
1228         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1229         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160),
1230         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1231         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
1232         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1233         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164),
1234         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1235         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1236         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1237         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164),
1238         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1239         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1240         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1241         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170),
1242         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1243         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
1244         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1245         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170),
1246         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1247         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
1248         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1249         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174),
1250         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1251         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
1252         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1253         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174),
1254         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1255         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
1256         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1257         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180),
1258         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1259         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
1260         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1261         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180),
1262         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1263         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
1264         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1265         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184),
1266         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1267         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1268         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1269         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184),
1270         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1271         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1272         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1273         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178),
1274         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1275         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
1276         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1277         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178),
1278         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1279         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
1280         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1281         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c),
1282         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1283         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
1284         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1285         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c),
1286         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1287         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
1288         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1289         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188),
1290         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1291         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1292         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1293         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188),
1294         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1295         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1296         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1297         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c),
1298         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1299         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
1300         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1301         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c),
1302         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1303         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
1304         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1305         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198),
1306         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1307         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
1308         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1309         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198),
1310         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1311         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
1312         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1313         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c),
1314         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1315         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
1316         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1317         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c),
1318         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1319         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
1320         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1321         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190),
1322         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1323         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1324         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1325         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190),
1326         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1327         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1328         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1329         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194),
1330         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1331         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
1332         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1333         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194),
1334         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1335         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
1336         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1337         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
1338         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1339         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
1340         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1341         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
1342         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1343         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1344         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1345         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
1346         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1347         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
1348         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1349         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
1350         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1351         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
1352         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1353         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
1354         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1355         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1f),
1356         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1357         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
1358         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1359         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1f),
1360         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1361         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
1362         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1363         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
1364         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1365         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_SAMPLE_SKEW, 0x000000FF, 0x19),
1366         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1367         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_MUXSEL_SKEW, 0x000000FF, 0x20),
1368         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1369         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0x5),
1370         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1371         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0xa),
1372         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1373         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x14),
1374         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1375         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x19),
1376         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1377         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_DESER_START_SKEW, 0x000000FF, 0x33),
1378         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xFFFFFFFF, 0xe0000000)
1379 };
1380
1381 static const struct soc15_reg_golden golden_settings_gc_10_1_1[] = {
1382         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0xffffffff, 0x003c0014),
1383         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_GS_NGG_CLK_CTRL, 0xffff8fff, 0xffff8100),
1384         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_IA_CLK_CTRL, 0xffff0fff, 0xffff0100),
1385         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xcd000000, 0x0d000100),
1386         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQ_CLK_CTRL, 0xf8ff0fff, 0x60000100),
1387         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQG_CLK_CTRL, 0x40000ff0, 0x40000100),
1388         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xffff8fff, 0xffff8100),
1389         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_WD_CLK_CTRL, 0xffff8fff, 0xffff8100),
1390         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
1391         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_VC5_ENABLE, 0x00000002, 0x00000000),
1392         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0x800007ff, 0x000005ff),
1393         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG, 0xffffffff, 0x20000000),
1394         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xffffffff, 0x00000420),
1395         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0x00000200, 0x00000200),
1396         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x04900000),
1397         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DFSM_TILES_IN_FLIGHT, 0x0000ffff, 0x0000003f),
1398         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_LAST_OF_BURST_CONFIG, 0xffffffff, 0x03860204),
1399         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff0ffff, 0x00000500),
1400         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PRIV_CONTROL, 0x000007ff, 0x000001fe),
1401         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
1402         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffe7),
1403         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffe7),
1404         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CGTT_SCLK_CTRL, 0xffff0fff, 0x10000100),
1405         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL2, 0xffffffff, 0x1402002f),
1406         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xffffbfff, 0x00000188),
1407         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
1408         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x08000009),
1409         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0x00400000, 0x04440000),
1410         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0x00000800, 0x00000820),
1411         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000),
1412         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0xffffffff, 0xffff3101),
1413         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0x001f0000, 0x00070105),
1414         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ALU_CLK_CTRL, 0xffffffff, 0xffffffff),
1415         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x00000133, 0x00000130),
1416         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0xffffffff, 0xffffffff),
1417         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
1418         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CNTL, 0x60000010, 0x479c0010),
1419         SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0x00c00000, 0x00c00000),
1420 };
1421
1422 static const struct soc15_reg_golden golden_settings_gc_10_1_2[] = {
1423         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0x003e001f, 0x003c0014),
1424         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_GS_NGG_CLK_CTRL, 0xffff8fff, 0xffff8100),
1425         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_IA_CLK_CTRL, 0xffff0fff, 0xffff0100),
1426         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xff7f0fff, 0x0d000100),
1427         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQ_CLK_CTRL, 0xffffcfff, 0x60000100),
1428         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQG_CLK_CTRL, 0xffff0fff, 0x40000100),
1429         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xffff8fff, 0xffff8100),
1430         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_WD_CLK_CTRL, 0xffff8fff, 0xffff8100),
1431         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
1432         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_VC5_ENABLE, 0x00000003, 0x00000000),
1433         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0x800007ff, 0x000005ff),
1434         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG, 0xffffffff, 0x20000000),
1435         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xffffffff, 0x00000420),
1436         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000200),
1437         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x04900000),
1438         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DFSM_TILES_IN_FLIGHT, 0x0000ffff, 0x0000003f),
1439         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_LAST_OF_BURST_CONFIG, 0xffffffff, 0x03860204),
1440         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0x0c1800ff, 0x00000044),
1441         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff0ffff, 0x00000500),
1442         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PRIV_CONTROL, 0x00007fff, 0x000001fe),
1443         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
1444         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x10321032),
1445         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x02310231),
1446         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
1447         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
1448         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CGTT_SCLK_CTRL, 0xffff0fff, 0x10000100),
1449         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL2, 0xffffffff, 0x1402002f),
1450         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xffffbfff, 0x00000188),
1451         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_0, 0xffffffff, 0x842a4c02),
1452         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
1453         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x08000009),
1454         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0xffffffff, 0x04440000),
1455         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0x00000820, 0x00000820),
1456         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000),
1457         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0xffffffff, 0xffff3101),
1458         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0x001f0000, 0x00070104),
1459         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ALU_CLK_CTRL, 0xffffffff, 0xffffffff),
1460         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x00000133, 0x00000130),
1461         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0xffffffff, 0xffffffff),
1462         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
1463         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CNTL, 0xffdf80ff, 0x479c0010),
1464         SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffffffff, 0x00c00000)
1465 };
1466
1467 static const struct soc15_reg_golden golden_settings_gc_10_1_nv14[] = {
1468         /* Pending on emulation bring up */
1469 };
1470
1471 static const struct soc15_reg_golden golden_settings_gc_rlc_spm_10_1_nv14[] = {
1472         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xE0000000L, 0x0),
1473         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1474         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
1475         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1476         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1477         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1478         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
1479         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1480         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
1481         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1482         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
1483         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1484         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
1485         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1486         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
1487         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1488         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1489         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1490         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
1491         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1492         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1493         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1494         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
1495         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1496         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1497         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1498         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
1499         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1500         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1501         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1502         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
1503         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1504         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1505         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1506         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
1507         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1508         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1509         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1510         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
1511         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1512         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1513         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1514         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
1515         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1516         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1517         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1518         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
1519         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1520         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1521         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1522         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
1523         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1524         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20),
1525         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1526         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
1527         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1528         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
1529         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1530         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
1531         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1532         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1533         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1534         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
1535         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1536         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1537         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1538         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
1539         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1540         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1541         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1542         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
1543         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1544         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1545         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1546         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
1547         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1548         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1549         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1550         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
1551         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1552         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
1553         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1554         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
1555         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1556         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1557         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1558         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
1559         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1560         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1561         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1562         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
1563         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1564         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1565         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1566         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
1567         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1568         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1569         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1570         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
1571         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1572         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
1573         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1574         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
1575         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1576         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
1577         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1578         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
1579         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1580         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
1581         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1582         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
1583         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1584         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
1585         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1586         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
1587         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1588         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
1589         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1590         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
1591         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1592         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
1593         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1594         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
1595         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1596         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
1597         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1598         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
1599         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1600         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
1601         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1602         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
1603         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1604         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
1605         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1606         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
1607         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1608         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
1609         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1610         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c),
1611         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1612         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1613         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1614         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
1615         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1616         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1617         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1618         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
1619         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1620         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1621         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1622         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
1623         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1624         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1625         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1626         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
1627         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1628         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1629         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1630         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
1631         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1632         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
1633         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1634         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
1635         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1636         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1637         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1638         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
1639         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1640         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1641         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1642         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
1643         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1644         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
1645         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1646         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
1647         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1648         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
1649         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1650         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
1651         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1652         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
1653         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1654         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
1655         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1656         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e),
1657         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1658         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
1659         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1660         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e),
1661         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1662         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
1663         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1664         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e),
1665         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1666         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
1667         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1668         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e),
1669         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1670         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
1671         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1672         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20),
1673         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1674         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
1675         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1676         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
1677         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1678         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
1679         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1680         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
1681         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1682         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
1683         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1684         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e),
1685         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1686         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
1687         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1688         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e),
1689         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1690         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
1691         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1692         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
1693         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1694         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
1695         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1696         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1697         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1698         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
1699         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1700         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1701         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1702         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
1703         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1704         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1705         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1706         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
1707         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1708         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1709         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1710         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
1711         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1712         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1713         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1714         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
1715         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1716         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1717         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1718         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
1719         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1720         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1721         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1722         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
1723         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1724         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1725         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1726         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
1727         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1728         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1729         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1730         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
1731         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1732         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1733         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1734         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
1735         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1736         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1737         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1738         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
1739         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1740         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1741         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1742         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90),
1743         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1744         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1745         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1746         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94),
1747         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1748         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
1749         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1750         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0),
1751         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1752         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1753         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1754         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4),
1755         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1756         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1757         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1758         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98),
1759         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1760         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1761         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1762         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c),
1763         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1764         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
1765         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1766         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8),
1767         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1768         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
1769         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1770         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac),
1771         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1772         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1773         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1774         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8),
1775         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1776         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1777         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1778         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc),
1779         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1780         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1781         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1782         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0),
1783         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1784         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
1785         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1786         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4),
1787         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1788         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1789         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1790         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0),
1791         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1792         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1793         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1794         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4),
1795         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1796         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1797         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1798         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0),
1799         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1800         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1801         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1802         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4),
1803         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1804         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1805         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1806         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8),
1807         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1808         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1809         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1810         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc),
1811         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1812         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1813         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1814         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8),
1815         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1816         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1817         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1818         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc),
1819         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1820         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1821         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1822         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8),
1823         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1824         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1825         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1826         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec),
1827         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1828         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1829         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1830         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0),
1831         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1832         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1833         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1834         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe4),
1835         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1836         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1837         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1838         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100),
1839         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1840         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1841         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1842         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104),
1843         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1844         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1845         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1846         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108),
1847         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1848         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1849         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1850         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c),
1851         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1852         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1853         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1854         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110),
1855         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1856         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1857         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1858         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114),
1859         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1860         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1861         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1862         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118),
1863         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1864         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1865         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1866         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c),
1867         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1868         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1869         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1870         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8),
1871         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1872         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17),
1873         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1874         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130),
1875         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1876         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1877         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1878         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134),
1879         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1880         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1881         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1882         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138),
1883         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1884         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1885         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1886         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c),
1887         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1888         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1889         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1890         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4),
1891         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1892         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20),
1893         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1894         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128),
1895         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1896         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1897         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1898         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c),
1899         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1900         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1901         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1902         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120),
1903         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1904         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1905         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1906         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124),
1907         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1908         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1909         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1910         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0),
1911         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1912         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
1913         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1914         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140),
1915         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1916         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1917         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1918         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144),
1919         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1920         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1921         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1922         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150),
1923         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1924         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1925         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1926         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154),
1927         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1928         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1929         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1930         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148),
1931         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1932         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1933         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1934         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c),
1935         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1936         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1937         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1938         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158),
1939         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1940         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1941         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1942         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c),
1943         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1944         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
1945         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1946         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168),
1947         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1948         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1949         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1950         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c),
1951         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1952         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1953         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1954         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160),
1955         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1956         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1957         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1958         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164),
1959         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1960         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
1961         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1962         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170),
1963         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1964         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
1965         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1966         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174),
1967         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1968         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
1969         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1970         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180),
1971         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1972         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1973         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1974         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184),
1975         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1976         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
1977         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1978         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178),
1979         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1980         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
1981         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1982         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c),
1983         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1984         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
1985         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1986         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188),
1987         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1988         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1989         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1990         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c),
1991         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1992         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1993         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1994         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198),
1995         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1996         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1997         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1998         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c),
1999         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2000         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2001         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2002         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190),
2003         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2004         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
2005         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2006         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194),
2007         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2008         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2009         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2010         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1a0),
2011         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2012         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2013         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2014         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1a4),
2015         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2016         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
2017         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2018         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1b0),
2019         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2020         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2021         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2022         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1b4),
2023         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2024         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2025         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2026         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1a8),
2027         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2028         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2029         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2030         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1ac),
2031         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2032         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
2033         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2034         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1b8),
2035         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2036         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
2037         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2038         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1bc),
2039         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2040         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2041         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2042         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c8),
2043         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2044         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
2045         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2046         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1cc),
2047         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2048         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
2049         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2050         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c0),
2051         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2052         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
2053         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2054         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c4),
2055         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2056         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2057         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2058         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
2059         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2060         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2061         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2062         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
2063         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2064         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2065         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2066         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
2067         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2068         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20),
2069         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2070         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
2071         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2072         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20),
2073         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2074         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
2075         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2076         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
2077         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2078         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_SAMPLE_SKEW, 0x000000FF, 0x26),
2079         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2080         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_MUXSEL_SKEW, 0x000000FF, 0x28),
2081         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2082         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0xf),
2083         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2084         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0x15),
2085         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2086         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x1f),
2087         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2088         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x25),
2089         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2090         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_DESER_START_SKEW, 0x000000FF, 0x3b),
2091         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xFFFFFFFF, 0xe0000000)
2092 };
2093
2094 static const struct soc15_reg_golden golden_settings_gc_10_1_2_nv12[] = {
2095         /* Pending on emulation bring up */
2096 };
2097
2098 static const struct soc15_reg_golden golden_settings_gc_rlc_spm_10_1_2_nv12[] = {
2099         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xe0000000L, 0x0),
2100         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2101         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
2102         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2103         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
2104         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2105         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
2106         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2107         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
2108         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2109         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
2110         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2111         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
2112         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2113         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
2114         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2115         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
2116         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2117         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8),
2118         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2119         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2120         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2121         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc),
2122         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2123         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2124         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2125         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0),
2126         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2127         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2128         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2129         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4),
2130         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2131         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2132         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2133         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
2134         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2135         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2136         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2137         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
2138         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2139         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2140         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2141         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
2142         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2143         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2144         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2145         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
2146         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2147         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2148         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2149         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
2150         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2151         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2152         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2153         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
2154         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2155         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2156         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2157         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
2158         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2159         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2160         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2161         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
2162         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2163         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
2164         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2165         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
2166         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2167         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
2168         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2169         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0),
2170         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2171         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
2172         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2173         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4),
2174         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2175         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
2176         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2177         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8),
2178         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2179         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2180         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2181         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc),
2182         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2183         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2184         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2185         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0),
2186         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2187         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2188         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2189         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4),
2190         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2191         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2192         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2193         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90),
2194         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2195         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
2196         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2197         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94),
2198         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2199         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1),
2200         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2201         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98),
2202         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2203         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
2204         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2205         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c),
2206         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2207         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2208         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2209         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0),
2210         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2211         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1),
2212         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2213         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4),
2214         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2215         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2216         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2217         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8),
2218         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2219         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2220         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2221         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac),
2222         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2223         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2224         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2225         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
2226         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2227         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
2228         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2229         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
2230         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2231         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2232         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2233         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
2234         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2235         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
2236         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2237         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
2238         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2239         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2240         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2241         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
2242         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2243         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2244         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2245         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
2246         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2247         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2248         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2249         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
2250         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2251         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
2252         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2253         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
2254         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2255         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2256         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2257         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
2258         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2259         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2260         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2261         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
2262         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2263         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
2264         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2265         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
2266         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2267         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2268         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2269         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
2270         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2271         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
2272         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2273         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
2274         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2275         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
2276         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2277         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
2278         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2279         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2280         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2281         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
2282         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2283         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2284         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2285         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
2286         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2287         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2288         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2289         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
2290         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2291         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
2292         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2293         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
2294         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2295         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2296         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2297         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
2298         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2299         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2300         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2301         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
2302         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2303         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2304         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2305         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
2306         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2307         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2308         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2309         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
2310         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2311         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2312         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2313         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
2314         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2315         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
2316         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2317         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c),
2318         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2319         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
2320         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2321         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
2322         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2323         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2324         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2325         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
2326         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2327         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
2328         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2329         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
2330         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2331         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
2332         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2333         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
2334         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2335         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2336         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2337         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
2338         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2339         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2340         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2341         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
2342         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2343         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2344         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2345         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
2346         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2347         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2348         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2349         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
2350         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2351         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2352         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2353         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
2354         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2355         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2356         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2357         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
2358         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2359         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
2360         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2361         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
2362         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2363         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
2364         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2365         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
2366         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2367         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2368         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2369         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
2370         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2371         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2372         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2373         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
2374         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2375         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
2376         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2377         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
2378         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2379         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
2380         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2381         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
2382         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2383         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2384         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2385         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
2386         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2387         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2388         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2389         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
2390         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2391         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
2392         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2393         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
2394         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2395         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
2396         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2397         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
2398         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2399         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2400         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2401         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
2402         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2403         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2404         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2405         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
2406         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2407         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2408         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2409         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
2410         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2411         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2412         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2413         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
2414         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2415         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2416         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2417         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
2418         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2419         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2420         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2421         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
2422         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2423         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2424         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2425         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
2426         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2427         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2428         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2429         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
2430         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2431         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2432         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2433         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
2434         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2435         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2436         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2437         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
2438         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2439         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2440         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2441         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
2442         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2443         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2444         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2445         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
2446         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2447         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2448         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2449         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
2450         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2451         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2452         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2453         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
2454         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2455         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2456         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2457         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
2458         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2459         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2460         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2461         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
2462         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2463         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2464         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2465         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
2466         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2467         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2468         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2469         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
2470         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2471         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
2472         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2473         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
2474         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2475         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
2476         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2477         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
2478         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2479         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2480         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2481         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
2482         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2483         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2484         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2485         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
2486         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2487         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
2488         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2489         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
2490         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2491         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
2492         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2493         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
2494         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2495         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
2496         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2497         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
2498         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2499         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
2500         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2501         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
2502         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2503         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2504         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2505         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
2506         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2507         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2508         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2509         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
2510         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2511         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2512         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2513         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
2514         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2515         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2516         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2517         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
2518         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2519         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
2520         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2521         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
2522         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2523         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
2524         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2525         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
2526         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2527         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2528         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2529         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
2530         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2531         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2532         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2533         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
2534         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2535         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2536         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2537         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
2538         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2539         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2540         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2541         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
2542         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2543         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2544         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2545         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
2546         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2547         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2548         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2549         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
2550         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2551         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2552         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2553         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
2554         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2555         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2556         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2557         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
2558         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2559         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2560         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2561         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
2562         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2563         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2564         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2565         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
2566         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2567         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2568         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2569         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
2570         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2571         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2572         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2573         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90),
2574         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2575         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
2576         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2577         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90),
2578         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2579         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
2580         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2581         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94),
2582         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2583         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2584         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2585         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94),
2586         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2587         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2588         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2589         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0),
2590         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2591         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2592         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2593         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0),
2594         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2595         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2596         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2597         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4),
2598         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2599         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2600         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2601         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4),
2602         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2603         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2604         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2605         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98),
2606         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2607         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
2608         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2609         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98),
2610         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2611         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
2612         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2613         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c),
2614         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2615         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2616         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2617         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c),
2618         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2619         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2620         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2621         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8),
2622         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2623         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2624         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2625         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8),
2626         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2627         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2628         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2629         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac),
2630         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2631         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2632         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2633         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac),
2634         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2635         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2636         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2637         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8),
2638         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2639         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2640         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2641         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8),
2642         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2643         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2644         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2645         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc),
2646         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2647         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2648         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2649         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc),
2650         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2651         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2652         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2653         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0),
2654         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2655         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2656         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2657         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0),
2658         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2659         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2660         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2661         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4),
2662         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2663         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2664         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2665         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4),
2666         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2667         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2668         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2669         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0),
2670         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2671         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2672         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2673         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0),
2674         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2675         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2676         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2677         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4),
2678         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2679         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2680         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2681         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4),
2682         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2683         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2684         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2685         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0),
2686         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2687         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2688         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2689         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0),
2690         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2691         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2692         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2693         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4),
2694         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2695         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2696         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2697         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4),
2698         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2699         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2700         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2701         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8),
2702         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2703         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2704         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2705         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8),
2706         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2707         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2708         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2709         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc),
2710         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2711         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2712         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2713         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc),
2714         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2715         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2716         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2717         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8),
2718         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2719         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2720         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2721         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8),
2722         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2723         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2724         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2725         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec),
2726         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2727         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
2728         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2729         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec),
2730         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2731         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
2732         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2733         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0),
2734         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2735         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2736         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2737         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0),
2738         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2739         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2740         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2741         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4),
2742         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2743         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2744         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2745         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4),
2746         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2747         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2748         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2749         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8),
2750         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2751         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2752         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2753         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8),
2754         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2755         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2756         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2757         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xfc),
2758         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2759         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17),
2760         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2761         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xfc),
2762         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2763         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17),
2764         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2765         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100),
2766         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2767         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
2768         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2769         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100),
2770         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2771         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
2772         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2773         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104),
2774         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2775         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2776         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2777         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104),
2778         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2779         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2780         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2781         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0),
2782         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2783         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2784         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2785         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0),
2786         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2787         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2788         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2789         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118),
2790         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2791         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2792         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2793         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118),
2794         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2795         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2796         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2797         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c),
2798         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2799         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2800         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2801         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c),
2802         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2803         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2804         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2805         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120),
2806         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2807         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2808         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2809         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120),
2810         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2811         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2812         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2813         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124),
2814         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2815         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2816         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2817         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124),
2818         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2819         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2820         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2821         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc),
2822         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2823         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2824         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2825         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc),
2826         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2827         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2828         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2829         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110),
2830         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2831         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2832         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2833         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110),
2834         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2835         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2836         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2837         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114),
2838         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2839         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2840         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2841         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114),
2842         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2843         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2844         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2845         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108),
2846         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2847         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2848         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2849         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108),
2850         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2851         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2852         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2853         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c),
2854         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2855         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2856         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2857         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c),
2858         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2859         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2860         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2861         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8),
2862         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2863         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
2864         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2865         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8),
2866         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2867         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
2868         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2869         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128),
2870         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2871         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2872         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2873         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128),
2874         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2875         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2876         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2877         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c),
2878         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2879         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2880         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2881         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c),
2882         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2883         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2884         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2885         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138),
2886         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2887         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2888         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2889         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138),
2890         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2891         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2892         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2893         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c),
2894         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2895         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2896         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2897         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c),
2898         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2899         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2900         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2901         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130),
2902         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2903         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2904         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2905         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130),
2906         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2907         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2908         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2909         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134),
2910         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2911         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
2912         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2913         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134),
2914         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2915         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
2916         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2917         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140),
2918         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2919         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2920         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2921         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140),
2922         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2923         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2924         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2925         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144),
2926         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2927         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2928         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2929         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144),
2930         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2931         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2932         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2933         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150),
2934         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2935         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2936         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2937         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150),
2938         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2939         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2940         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2941         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154),
2942         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2943         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2944         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2945         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154),
2946         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2947         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2948         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2949         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148),
2950         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2951         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2952         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2953         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148),
2954         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2955         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2956         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2957         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c),
2958         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2959         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2960         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2961         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c),
2962         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2963         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2964         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2965         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158),
2966         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2967         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
2968         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2969         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158),
2970         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2971         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
2972         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2973         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c),
2974         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2975         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
2976         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2977         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c),
2978         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2979         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
2980         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2981         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168),
2982         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2983         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
2984         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2985         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168),
2986         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2987         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
2988         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2989         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c),
2990         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2991         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
2992         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2993         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c),
2994         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2995         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
2996         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2997         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160),
2998         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2999         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
3000         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3001         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160),
3002         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3003         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
3004         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3005         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164),
3006         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3007         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
3008         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3009         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164),
3010         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3011         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
3012         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3013         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170),
3014         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3015         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
3016         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3017         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170),
3018         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3019         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
3020         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3021         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174),
3022         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3023         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3024         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3025         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174),
3026         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3027         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3028         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3029         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180),
3030         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3031         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
3032         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3033         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180),
3034         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3035         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
3036         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3037         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184),
3038         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3039         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3040         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3041         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184),
3042         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3043         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3044         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3045         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178),
3046         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3047         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
3048         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3049         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178),
3050         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3051         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
3052         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3053         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c),
3054         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3055         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3056         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3057         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c),
3058         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3059         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3060         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3061         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188),
3062         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3063         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3064         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3065         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188),
3066         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3067         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3068         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3069         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c),
3070         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3071         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
3072         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3073         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c),
3074         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3075         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
3076         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3077         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198),
3078         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3079         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
3080         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3081         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198),
3082         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3083         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
3084         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3085         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c),
3086         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3087         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
3088         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3089         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c),
3090         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3091         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
3092         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3093         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190),
3094         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3095         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3096         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3097         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190),
3098         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3099         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3100         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3101         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194),
3102         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3103         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
3104         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3105         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194),
3106         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3107         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
3108         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3109         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
3110         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3111         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
3112         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3113         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
3114         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3115         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
3116         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3117         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
3118         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3119         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
3120         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3121         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
3122         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3123         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
3124         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3125         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
3126         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3127         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1f),
3128         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3129         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
3130         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3131         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1f),
3132         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3133         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
3134         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3135         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
3136         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3137         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_SAMPLE_SKEW, 0x000000FF, 0x1f),
3138         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3139         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_MUXSEL_SKEW, 0x000000FF, 0x22),
3140         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3141         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0x1),
3142         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3143         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0x6),
3144         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3145         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x10),
3146         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3147         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x15),
3148         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3149         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_DESER_START_SKEW, 0x000000FF, 0x35),
3150         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xFFFFFFFF, 0xe0000000)
3151 };
3152
3153 static const struct soc15_reg_golden golden_settings_gc_10_3[] = {
3154         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0x78000000, 0x78000100),
3155         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_PS_CLK_CTRL, 0xff7f0fff, 0x78000100),
3156         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA0_CLK_CTRL, 0xff7f0fff, 0x30000100),
3157         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA1_CLK_CTRL, 0xff7f0fff, 0x7e000100),
3158         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c000),
3159         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000280),
3160         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000),
3161         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_EXCEPTION_CONTROL, 0x7fff0f1f, 0x00b80000),
3162         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCEA_SDP_TAG_RESERVE0, 0xffffffff, 0x10100100),
3163         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCEA_SDP_TAG_RESERVE1, 0xffffffff, 0x17000088),
3164         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Sienna_Cichlid, 0x1ff1ffff, 0x00000500),
3165         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCUTCL2_CGTT_CLK_CTRL_Sienna_Cichlid, 0xff000000, 0xff008080),
3166         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCVM_L2_CGTT_CLK_CTRL_Sienna_Cichlid, 0xff000000, 0xff008080),
3167         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PC_CNTL, 0x003fffff, 0x00280400),
3168         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
3169         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
3170         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008),
3171         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x10f80988),
3172         SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG,  0x00000020, 0x00000020),
3173         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007),
3174         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
3175         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0xffffffbf, 0x00000820),
3176         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0xffffffff, 0x00070104),
3177         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_CONFIG, 0xe07df47f, 0x00180070),
3178         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER0_SELECT, 0xf0f001ff, 0x00000000),
3179         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER1_SELECT, 0xf0f001ff, 0x00000000),
3180         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER10_SELECT, 0xf0f001ff, 0x00000000),
3181         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER11_SELECT, 0xf0f001ff, 0x00000000),
3182         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER12_SELECT, 0xf0f001ff, 0x00000000),
3183         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER13_SELECT, 0xf0f001ff, 0x00000000),
3184         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER14_SELECT, 0xf0f001ff, 0x00000000),
3185         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER15_SELECT, 0xf0f001ff, 0x00000000),
3186         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER2_SELECT, 0xf0f001ff, 0x00000000),
3187         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER3_SELECT, 0xf0f001ff, 0x00000000),
3188         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER4_SELECT, 0xf0f001ff, 0x00000000),
3189         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER5_SELECT, 0xf0f001ff, 0x00000000),
3190         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER6_SELECT, 0xf0f001ff, 0x00000000),
3191         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER7_SELECT, 0xf0f001ff, 0x00000000),
3192         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER8_SELECT, 0xf0f001ff, 0x00000000),
3193         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER9_SELECT, 0xf0f001ff, 0x00000000),
3194         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSX_DEBUG_1, 0x00010000, 0x00010020),
3195         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
3196         SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffbfffff, 0x00a00000)
3197 };
3198
3199 static const struct soc15_reg_golden golden_settings_gc_10_3_sienna_cichlid[] = {
3200         /* Pending on emulation bring up */
3201 };
3202
3203 static const struct soc15_reg_golden golden_settings_gc_10_3_2[] = {
3204         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0xff7f0fff, 0x78000100),
3205         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_PS_CLK_CTRL, 0xff7f0fff, 0x78000100),
3206         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA0_CLK_CTRL, 0xff7f0fff, 0x30000100),
3207         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA1_CLK_CTRL, 0xff7f0fff, 0x7e000100),
3208         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c000),
3209         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000280),
3210         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000),
3211         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_EXCEPTION_CONTROL, 0x7fff0f1f, 0x00b80000),
3212         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Sienna_Cichlid, 0x1ff1ffff, 0x00000500),
3213         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCUTCL2_CGTT_CLK_CTRL_Sienna_Cichlid, 0xffffffff, 0xff008080),
3214         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCVM_L2_CGTT_CLK_CTRL_Sienna_Cichlid, 0xffff8fff, 0xff008080),
3215         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PC_CNTL, 0x003fffff, 0x00280400),
3216         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
3217         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
3218         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008),
3219         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x00f80988),
3220         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007),
3221         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
3222         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0xffffffbf, 0x00000820),
3223         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0xffffffff, 0x00070104),
3224         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_START_PHASE, 0x000000ff, 0x00000004),
3225         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_CONFIG, 0xe07df47f, 0x00180070),
3226         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER0_SELECT, 0xf0f001ff, 0x00000000),
3227         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER1_SELECT, 0xf0f001ff, 0x00000000),
3228         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER10_SELECT, 0xf0f001ff, 0x00000000),
3229         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER11_SELECT, 0xf0f001ff, 0x00000000),
3230         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER12_SELECT, 0xf0f001ff, 0x00000000),
3231         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER13_SELECT, 0xf0f001ff, 0x00000000),
3232         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER14_SELECT, 0xf0f001ff, 0x00000000),
3233         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER15_SELECT, 0xf0f001ff, 0x00000000),
3234         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER2_SELECT, 0xf0f001ff, 0x00000000),
3235         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER3_SELECT, 0xf0f001ff, 0x00000000),
3236         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER4_SELECT, 0xf0f001ff, 0x00000000),
3237         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER5_SELECT, 0xf0f001ff, 0x00000000),
3238         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER6_SELECT, 0xf0f001ff, 0x00000000),
3239         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER7_SELECT, 0xf0f001ff, 0x00000000),
3240         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER8_SELECT, 0xf0f001ff, 0x00000000),
3241         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER9_SELECT, 0xf0f001ff, 0x00000000),
3242         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
3243         SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffbfffff, 0x00a00000),
3244         SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_GS_MAX_WAVE_ID, 0x00000fff, 0x000003ff),
3245
3246         /* This is not in GDB yet. Don't remove it. It fixes a GPU hang on Navy Flounder. */
3247         SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG,  0x00000020, 0x00000020),
3248 };
3249
3250 static const struct soc15_reg_golden golden_settings_gc_10_3_vangogh[] = {
3251         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA0_CLK_CTRL, 0xff7f0fff, 0x30000100),
3252         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA1_CLK_CTRL, 0xff7f0fff, 0x7e000100),
3253         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0x000000ff, 0x000000e4),
3254         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000200),
3255         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000),
3256         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_EXCEPTION_CONTROL, 0x7fff0f1f, 0x00b80000),
3257         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0x0c1807ff, 0x00000142),
3258         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Vangogh, 0x1ff1ffff, 0x00000500),
3259         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0x000000ff, 0x000000e4),
3260         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x32103210),
3261         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x32103210),
3262         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xfffffff3),
3263         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xfffffff3),
3264         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008),
3265         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x00f80988),
3266         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007),
3267         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
3268         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0xffffffbf, 0x00000020),
3269         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1_Vangogh, 0xffffffff, 0x00070103),
3270         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQG_CONFIG, 0x000017ff, 0x00001000),
3271         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSX_DEBUG_1, 0x00010000, 0x00010020),
3272         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
3273         SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffffffff, 0x00400000),
3274         SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_GS_MAX_WAVE_ID, 0x00000fff, 0x000000ff),
3275
3276         /* This is not in GDB yet. Don't remove it. It fixes a GPU hang on VanGogh. */
3277         SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG,  0x00000020, 0x00000020),
3278 };
3279
3280 static const struct soc15_reg_golden golden_settings_gc_10_3_3[] = {
3281         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0xff7f0fff, 0x78000100),
3282         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0x000000ff, 0x000000e4),
3283         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c200),
3284         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000280),
3285         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000),
3286         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0x0c1807ff, 0x00000242),
3287         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Vangogh, 0x1ff1ffff, 0x00000500),
3288         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0x000000ff, 0x000000e4),
3289         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x32103210),
3290         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x32103210),
3291         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xfffffff3),
3292         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xfffffff3),
3293         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008),
3294         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x00f80988),
3295         SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG, 0x000001ff, 0x00000020),
3296         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007),
3297         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
3298         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0xffffffbf, 0x00000820),
3299         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
3300         SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffffffff, 0x00100000)
3301 };
3302
3303 static const struct soc15_reg_golden golden_settings_gc_10_3_4[] = {
3304         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0x78000000, 0x78000100),
3305         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA0_CLK_CTRL, 0x30000000, 0x30000100),
3306         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA1_CLK_CTRL, 0x7e000000, 0x7e000100),
3307         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c000),
3308         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0x00000280, 0x00000280),
3309         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0x07800000, 0x00800000),
3310         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Sienna_Cichlid, 0x00001d00, 0x00000500),
3311         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PC_CNTL, 0x003c0000, 0x00280400),
3312         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
3313         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
3314         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0x40000000, 0x580f1008),
3315         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0x00040000, 0x00f80988),
3316         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0x01000000, 0x01200007),
3317         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
3318         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0x00000800, 0x00000820),
3319         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_CONFIG, 0x0000001f, 0x00180070),
3320         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER0_SELECT, 0xf0f001ff, 0x00000000),
3321         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER1_SELECT, 0xf0f001ff, 0x00000000),
3322         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER10_SELECT, 0xf0f001ff, 0x00000000),
3323         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER11_SELECT, 0xf0f001ff, 0x00000000),
3324         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER12_SELECT, 0xf0f001ff, 0x00000000),
3325         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER13_SELECT, 0xf0f001ff, 0x00000000),
3326         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER14_SELECT, 0xf0f001ff, 0x00000000),
3327         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER15_SELECT, 0xf0f001ff, 0x00000000),
3328         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER2_SELECT, 0xf0f001ff, 0x00000000),
3329         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER3_SELECT, 0xf0f001ff, 0x00000000),
3330         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER4_SELECT, 0xf0f001ff, 0x00000000),
3331         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER5_SELECT, 0xf0f001ff, 0x00000000),
3332         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER6_SELECT, 0xf0f001ff, 0x00000000),
3333         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER7_SELECT, 0xf0f001ff, 0x00000000),
3334         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER8_SELECT, 0xf0f001ff, 0x00000000),
3335         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER9_SELECT, 0xf0f001ff, 0x00000000),
3336         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSX_DEBUG_1, 0x00010000, 0x00010020),
3337         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0x01030000, 0x01030000),
3338         SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0x03a00000, 0x00a00000),
3339         SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG,  0x00000020, 0x00000020)
3340 };
3341
3342 static const struct soc15_reg_golden golden_settings_gc_10_3_5[] = {
3343         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0x78000000, 0x78000100),
3344         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA0_CLK_CTRL, 0xb0000ff0, 0x30000100),
3345         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA1_CLK_CTRL, 0xff000000, 0x7e000100),
3346         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c000),
3347         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000280),
3348         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000),
3349         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Sienna_Cichlid, 0x1ff1ffff, 0x00000500),
3350         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
3351         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
3352         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008),
3353         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x00f80988),
3354         SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG, 0x000001ff, 0x00000020),
3355         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007),
3356         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_CONFIG, 0xe07df47f, 0x00180070),
3357         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER0_SELECT, 0xf0f001ff, 0x00000000),
3358         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER1_SELECT, 0xf0f001ff, 0x00000000),
3359         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER10_SELECT, 0xf0f001ff, 0x00000000),
3360         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER11_SELECT, 0xf0f001ff, 0x00000000),
3361         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER12_SELECT, 0xf0f001ff, 0x00000000),
3362         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER13_SELECT, 0xf0f001ff, 0x00000000),
3363         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER14_SELECT, 0xf0f001ff, 0x00000000),
3364         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER15_SELECT, 0xf0f001ff, 0x00000000),
3365         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER2_SELECT, 0xf0f001ff, 0x00000000),
3366         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER3_SELECT, 0xf0f001ff, 0x00000000),
3367         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER4_SELECT, 0xf0f001ff, 0x00000000),
3368         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER5_SELECT, 0xf0f001ff, 0x00000000),
3369         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER6_SELECT, 0xf0f001ff, 0x00000000),
3370         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER7_SELECT, 0xf0f001ff, 0x00000000),
3371         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER8_SELECT, 0xf0f001ff, 0x00000000),
3372         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER9_SELECT, 0xf0f001ff, 0x00000000),
3373         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
3374         SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffbfffff, 0x00a00000)
3375 };
3376
3377 static const struct soc15_reg_golden golden_settings_gc_10_0_cyan_skillfish[] = {
3378         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000),
3379         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_FAST_CLKS, 0x3fffffff, 0x0000493e),
3380         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_CPF_CLK_CTRL, 0xfcff8fff, 0xf8000100),
3381         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xff7f0fff, 0x3c000100),
3382         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_3, 0xa0000000, 0xa0000000),
3383         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0x00008000, 0x003c8014),
3384         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_DRAM_BURST_CTRL, 0x00000010, 0x00000017),
3385         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0xffffffff, 0xd8d8d8d8),
3386         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_VC5_ENABLE, 0x00000003, 0x00000003),
3387         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0x800007ff, 0x000005ff),
3388         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG, 0xffffffff, 0x20000000),
3389         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000200),
3390         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x04800000),
3391         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_LAST_OF_BURST_CONFIG, 0xffffffff, 0x03860210),
3392         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0x0c1800ff, 0x00000044),
3393         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x00009d00, 0x00008500),
3394         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCMC_VM_CACHEABLE_DRAM_ADDRESS_END, 0xffffffff, 0x000fffff),
3395         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_DRAM_BURST_CTRL, 0x00000010, 0x00000017),
3396         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0xfcfcfcfc, 0xd8d8d8d8),
3397         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77707770, 0x21302130),
3398         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77707770, 0x21302130),
3399         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
3400         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
3401         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CGTT_SCLK_CTRL, 0x10000000, 0x10000100),
3402         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL2, 0xfc02002f, 0x9402002f),
3403         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0x00002188, 0x00000188),
3404         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x08000009, 0x08000009),
3405         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_0, 0xcc3fcc03, 0x842a4c02),
3406         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000000f, 0x00000000),
3407         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0xffff3109, 0xffff3101),
3408         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x00000100, 0x00000130),
3409         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0xffffffff, 0xffffffff),
3410         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0x00030008, 0x01030000),
3411         SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0x00800000, 0x00800000)
3412 };
3413
3414 static const struct soc15_reg_golden golden_settings_gc_10_3_6[] = {
3415         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0xff7f0fff, 0x78000100),
3416         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0x000000ff, 0x00000044),
3417         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c200),
3418         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000280),
3419         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000),
3420         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0x0c1807ff, 0x00000042),
3421         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Vangogh, 0x1ff1ffff, 0x00000500),
3422         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0x000000ff, 0x00000044),
3423         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x32103210),
3424         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x32103210),
3425         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xfffffff3),
3426         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xfffffff3),
3427         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008),
3428         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x00f80988),
3429         SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG, 0x000001ff, 0x00000020),
3430         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007),
3431         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
3432         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0xffffffbf, 0x00000820),
3433         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQG_CONFIG, 0x000017ff, 0x00001000),
3434         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSX_DEBUG_1, 0xffffff7f, 0x00010020),
3435         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
3436         SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffffffff, 0x00100000)
3437 };
3438
3439 static const struct soc15_reg_golden golden_settings_gc_10_3_7[] = {
3440         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0xff7f0fff, 0x78000100),
3441         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0x000000ff, 0x000000e4),
3442         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c200),
3443         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000280),
3444         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000),
3445         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0x0c1807ff, 0x00000041),
3446         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Vangogh, 0x1ff1ffff, 0x00000500),
3447         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0x000000ff, 0x000000e4),
3448         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x32103210),
3449         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x32103210),
3450         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffff),
3451         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffff),
3452         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008),
3453         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x00f80988),
3454         SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG, 0x000001ff, 0x00000020),
3455         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf000003f, 0x01200007),
3456         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
3457         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0xffffffbf, 0x00000820),
3458         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQG_CONFIG, 0x000017ff, 0x00001000),
3459         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSX_DEBUG_1, 0xffffff7f, 0x00010020),
3460         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
3461         SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffffffff, 0x00100000)
3462 };
3463
3464 #define DEFAULT_SH_MEM_CONFIG \
3465         ((SH_MEM_ADDRESS_MODE_64 << SH_MEM_CONFIG__ADDRESS_MODE__SHIFT) | \
3466          (SH_MEM_ALIGNMENT_MODE_UNALIGNED << SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT) | \
3467          (SH_MEM_RETRY_MODE_ALL << SH_MEM_CONFIG__RETRY_MODE__SHIFT) | \
3468          (3 << SH_MEM_CONFIG__INITIAL_INST_PREFETCH__SHIFT))
3469
3470 /* TODO: pending on golden setting value of gb address config */
3471 #define CYAN_SKILLFISH_GB_ADDR_CONFIG_GOLDEN 0x00100044
3472
3473 static void gfx_v10_0_set_ring_funcs(struct amdgpu_device *adev);
3474 static void gfx_v10_0_set_irq_funcs(struct amdgpu_device *adev);
3475 static void gfx_v10_0_set_gds_init(struct amdgpu_device *adev);
3476 static void gfx_v10_0_set_rlc_funcs(struct amdgpu_device *adev);
3477 static void gfx_v10_0_set_mqd_funcs(struct amdgpu_device *adev);
3478 static int gfx_v10_0_get_cu_info(struct amdgpu_device *adev,
3479                                  struct amdgpu_cu_info *cu_info);
3480 static uint64_t gfx_v10_0_get_gpu_clock_counter(struct amdgpu_device *adev);
3481 static void gfx_v10_0_select_se_sh(struct amdgpu_device *adev, u32 se_num,
3482                                    u32 sh_num, u32 instance, int xcc_id);
3483 static u32 gfx_v10_0_get_wgp_active_bitmap_per_sh(struct amdgpu_device *adev);
3484
3485 static int gfx_v10_0_rlc_backdoor_autoload_buffer_init(struct amdgpu_device *adev);
3486 static void gfx_v10_0_rlc_backdoor_autoload_buffer_fini(struct amdgpu_device *adev);
3487 static int gfx_v10_0_rlc_backdoor_autoload_enable(struct amdgpu_device *adev);
3488 static int gfx_v10_0_wait_for_rlc_autoload_complete(struct amdgpu_device *adev);
3489 static void gfx_v10_0_ring_emit_ce_meta(struct amdgpu_ring *ring, bool resume);
3490 static void gfx_v10_0_ring_emit_de_meta(struct amdgpu_ring *ring, bool resume);
3491 static void gfx_v10_0_ring_emit_frame_cntl(struct amdgpu_ring *ring, bool start, bool secure);
3492 static u32 gfx_v10_3_get_disabled_sa(struct amdgpu_device *adev);
3493 static void gfx_v10_3_program_pbb_mode(struct amdgpu_device *adev);
3494 static void gfx_v10_3_set_power_brake_sequence(struct amdgpu_device *adev);
3495 static void gfx_v10_0_ring_invalidate_tlbs(struct amdgpu_ring *ring,
3496                                            uint16_t pasid, uint32_t flush_type,
3497                                            bool all_hub, uint8_t dst_sel);
3498 static void gfx_v10_0_update_spm_vmid_internal(struct amdgpu_device *adev,
3499                                                unsigned int vmid);
3500
3501 static int gfx_v10_0_set_powergating_state(void *handle,
3502                                           enum amd_powergating_state state);
3503 static void gfx10_kiq_set_resources(struct amdgpu_ring *kiq_ring, uint64_t queue_mask)
3504 {
3505         amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_RESOURCES, 6));
3506         amdgpu_ring_write(kiq_ring, PACKET3_SET_RESOURCES_VMID_MASK(0) |
3507                           PACKET3_SET_RESOURCES_QUEUE_TYPE(0)); /* vmid_mask:0 queue_type:0 (KIQ) */
3508         amdgpu_ring_write(kiq_ring, lower_32_bits(queue_mask)); /* queue mask lo */
3509         amdgpu_ring_write(kiq_ring, upper_32_bits(queue_mask)); /* queue mask hi */
3510         amdgpu_ring_write(kiq_ring, 0); /* gws mask lo */
3511         amdgpu_ring_write(kiq_ring, 0); /* gws mask hi */
3512         amdgpu_ring_write(kiq_ring, 0); /* oac mask */
3513         amdgpu_ring_write(kiq_ring, 0); /* gds heap base:0, gds heap size:0 */
3514 }
3515
3516 static void gfx10_kiq_map_queues(struct amdgpu_ring *kiq_ring,
3517                                  struct amdgpu_ring *ring)
3518 {
3519         uint64_t mqd_addr = amdgpu_bo_gpu_offset(ring->mqd_obj);
3520         uint64_t wptr_addr = ring->wptr_gpu_addr;
3521         uint32_t eng_sel = 0;
3522
3523         switch (ring->funcs->type) {
3524         case AMDGPU_RING_TYPE_COMPUTE:
3525                 eng_sel = 0;
3526                 break;
3527         case AMDGPU_RING_TYPE_GFX:
3528                 eng_sel = 4;
3529                 break;
3530         case AMDGPU_RING_TYPE_MES:
3531                 eng_sel = 5;
3532                 break;
3533         default:
3534                 WARN_ON(1);
3535         }
3536
3537         amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5));
3538         /* Q_sel:0, vmid:0, vidmem: 1, engine:0, num_Q:1*/
3539         amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */
3540                           PACKET3_MAP_QUEUES_QUEUE_SEL(0) | /* Queue_Sel */
3541                           PACKET3_MAP_QUEUES_VMID(0) | /* VMID */
3542                           PACKET3_MAP_QUEUES_QUEUE(ring->queue) |
3543                           PACKET3_MAP_QUEUES_PIPE(ring->pipe) |
3544                           PACKET3_MAP_QUEUES_ME((ring->me == 1 ? 0 : 1)) |
3545                           PACKET3_MAP_QUEUES_QUEUE_TYPE(0) | /*queue_type: normal compute queue */
3546                           PACKET3_MAP_QUEUES_ALLOC_FORMAT(0) | /* alloc format: all_on_one_pipe */
3547                           PACKET3_MAP_QUEUES_ENGINE_SEL(eng_sel) |
3548                           PACKET3_MAP_QUEUES_NUM_QUEUES(1)); /* num_queues: must be 1 */
3549         amdgpu_ring_write(kiq_ring, PACKET3_MAP_QUEUES_DOORBELL_OFFSET(ring->doorbell_index));
3550         amdgpu_ring_write(kiq_ring, lower_32_bits(mqd_addr));
3551         amdgpu_ring_write(kiq_ring, upper_32_bits(mqd_addr));
3552         amdgpu_ring_write(kiq_ring, lower_32_bits(wptr_addr));
3553         amdgpu_ring_write(kiq_ring, upper_32_bits(wptr_addr));
3554 }
3555
3556 static void gfx10_kiq_unmap_queues(struct amdgpu_ring *kiq_ring,
3557                                    struct amdgpu_ring *ring,
3558                                    enum amdgpu_unmap_queues_action action,
3559                                    u64 gpu_addr, u64 seq)
3560 {
3561         struct amdgpu_device *adev = kiq_ring->adev;
3562         uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0;
3563
3564         if (adev->enable_mes && !adev->gfx.kiq[0].ring.sched.ready) {
3565                 amdgpu_mes_unmap_legacy_queue(adev, ring, action, gpu_addr, seq);
3566                 return;
3567         }
3568
3569         amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_UNMAP_QUEUES, 4));
3570         amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */
3571                           PACKET3_UNMAP_QUEUES_ACTION(action) |
3572                           PACKET3_UNMAP_QUEUES_QUEUE_SEL(0) |
3573                           PACKET3_UNMAP_QUEUES_ENGINE_SEL(eng_sel) |
3574                           PACKET3_UNMAP_QUEUES_NUM_QUEUES(1));
3575         amdgpu_ring_write(kiq_ring,
3576                   PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET0(ring->doorbell_index));
3577
3578         if (action == PREEMPT_QUEUES_NO_UNMAP) {
3579                 amdgpu_ring_write(kiq_ring, lower_32_bits(gpu_addr));
3580                 amdgpu_ring_write(kiq_ring, upper_32_bits(gpu_addr));
3581                 amdgpu_ring_write(kiq_ring, seq);
3582         } else {
3583                 amdgpu_ring_write(kiq_ring, 0);
3584                 amdgpu_ring_write(kiq_ring, 0);
3585                 amdgpu_ring_write(kiq_ring, 0);
3586         }
3587 }
3588
3589 static void gfx10_kiq_query_status(struct amdgpu_ring *kiq_ring,
3590                                    struct amdgpu_ring *ring,
3591                                    u64 addr,
3592                                    u64 seq)
3593 {
3594         uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0;
3595
3596         amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_QUERY_STATUS, 5));
3597         amdgpu_ring_write(kiq_ring,
3598                           PACKET3_QUERY_STATUS_CONTEXT_ID(0) |
3599                           PACKET3_QUERY_STATUS_INTERRUPT_SEL(0) |
3600                           PACKET3_QUERY_STATUS_COMMAND(2));
3601         amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */
3602                           PACKET3_QUERY_STATUS_DOORBELL_OFFSET(ring->doorbell_index) |
3603                           PACKET3_QUERY_STATUS_ENG_SEL(eng_sel));
3604         amdgpu_ring_write(kiq_ring, lower_32_bits(addr));
3605         amdgpu_ring_write(kiq_ring, upper_32_bits(addr));
3606         amdgpu_ring_write(kiq_ring, lower_32_bits(seq));
3607         amdgpu_ring_write(kiq_ring, upper_32_bits(seq));
3608 }
3609
3610 static void gfx10_kiq_invalidate_tlbs(struct amdgpu_ring *kiq_ring,
3611                                 uint16_t pasid, uint32_t flush_type,
3612                                 bool all_hub)
3613 {
3614         gfx_v10_0_ring_invalidate_tlbs(kiq_ring, pasid, flush_type, all_hub, 1);
3615 }
3616
3617 static const struct kiq_pm4_funcs gfx_v10_0_kiq_pm4_funcs = {
3618         .kiq_set_resources = gfx10_kiq_set_resources,
3619         .kiq_map_queues = gfx10_kiq_map_queues,
3620         .kiq_unmap_queues = gfx10_kiq_unmap_queues,
3621         .kiq_query_status = gfx10_kiq_query_status,
3622         .kiq_invalidate_tlbs = gfx10_kiq_invalidate_tlbs,
3623         .set_resources_size = 8,
3624         .map_queues_size = 7,
3625         .unmap_queues_size = 6,
3626         .query_status_size = 7,
3627         .invalidate_tlbs_size = 2,
3628 };
3629
3630 static void gfx_v10_0_set_kiq_pm4_funcs(struct amdgpu_device *adev)
3631 {
3632         adev->gfx.kiq[0].pmf = &gfx_v10_0_kiq_pm4_funcs;
3633 }
3634
3635 static void gfx_v10_0_init_spm_golden_registers(struct amdgpu_device *adev)
3636 {
3637         switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
3638         case IP_VERSION(10, 1, 10):
3639                 soc15_program_register_sequence(adev,
3640                                                 golden_settings_gc_rlc_spm_10_0_nv10,
3641                                                 (const u32)ARRAY_SIZE(golden_settings_gc_rlc_spm_10_0_nv10));
3642                 break;
3643         case IP_VERSION(10, 1, 1):
3644                 soc15_program_register_sequence(adev,
3645                                                 golden_settings_gc_rlc_spm_10_1_nv14,
3646                                                 (const u32)ARRAY_SIZE(golden_settings_gc_rlc_spm_10_1_nv14));
3647                 break;
3648         case IP_VERSION(10, 1, 2):
3649                 soc15_program_register_sequence(adev,
3650                                                 golden_settings_gc_rlc_spm_10_1_2_nv12,
3651                                                 (const u32)ARRAY_SIZE(golden_settings_gc_rlc_spm_10_1_2_nv12));
3652                 break;
3653         default:
3654                 break;
3655         }
3656 }
3657
3658 static void gfx_v10_0_init_golden_registers(struct amdgpu_device *adev)
3659 {
3660         switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
3661         case IP_VERSION(10, 1, 10):
3662                 soc15_program_register_sequence(adev,
3663                                                 golden_settings_gc_10_1,
3664                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_1));
3665                 soc15_program_register_sequence(adev,
3666                                                 golden_settings_gc_10_0_nv10,
3667                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_0_nv10));
3668                 break;
3669         case IP_VERSION(10, 1, 1):
3670                 soc15_program_register_sequence(adev,
3671                                                 golden_settings_gc_10_1_1,
3672                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_1_1));
3673                 soc15_program_register_sequence(adev,
3674                                                 golden_settings_gc_10_1_nv14,
3675                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_1_nv14));
3676                 break;
3677         case IP_VERSION(10, 1, 2):
3678                 soc15_program_register_sequence(adev,
3679                                                 golden_settings_gc_10_1_2,
3680                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_1_2));
3681                 soc15_program_register_sequence(adev,
3682                                                 golden_settings_gc_10_1_2_nv12,
3683                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_1_2_nv12));
3684                 break;
3685         case IP_VERSION(10, 3, 0):
3686                 soc15_program_register_sequence(adev,
3687                                                 golden_settings_gc_10_3,
3688                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_3));
3689                 soc15_program_register_sequence(adev,
3690                                                 golden_settings_gc_10_3_sienna_cichlid,
3691                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_sienna_cichlid));
3692                 break;
3693         case IP_VERSION(10, 3, 2):
3694                 soc15_program_register_sequence(adev,
3695                                                 golden_settings_gc_10_3_2,
3696                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_2));
3697                 break;
3698         case IP_VERSION(10, 3, 1):
3699                 soc15_program_register_sequence(adev,
3700                                                 golden_settings_gc_10_3_vangogh,
3701                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_vangogh));
3702                 break;
3703         case IP_VERSION(10, 3, 3):
3704                 soc15_program_register_sequence(adev,
3705                                                 golden_settings_gc_10_3_3,
3706                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_3));
3707                 break;
3708         case IP_VERSION(10, 3, 4):
3709                 soc15_program_register_sequence(adev,
3710                                                 golden_settings_gc_10_3_4,
3711                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_4));
3712                 break;
3713         case IP_VERSION(10, 3, 5):
3714                 soc15_program_register_sequence(adev,
3715                                                 golden_settings_gc_10_3_5,
3716                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_5));
3717                 break;
3718         case IP_VERSION(10, 1, 3):
3719         case IP_VERSION(10, 1, 4):
3720                 soc15_program_register_sequence(adev,
3721                                                 golden_settings_gc_10_0_cyan_skillfish,
3722                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_0_cyan_skillfish));
3723                 break;
3724         case IP_VERSION(10, 3, 6):
3725                 soc15_program_register_sequence(adev,
3726                                                 golden_settings_gc_10_3_6,
3727                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_6));
3728                 break;
3729         case IP_VERSION(10, 3, 7):
3730                 soc15_program_register_sequence(adev,
3731                                                 golden_settings_gc_10_3_7,
3732                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_7));
3733                 break;
3734         default:
3735                 break;
3736         }
3737         gfx_v10_0_init_spm_golden_registers(adev);
3738 }
3739
3740 static void gfx_v10_0_write_data_to_reg(struct amdgpu_ring *ring, int eng_sel,
3741                                        bool wc, uint32_t reg, uint32_t val)
3742 {
3743         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
3744         amdgpu_ring_write(ring, WRITE_DATA_ENGINE_SEL(eng_sel) |
3745                           WRITE_DATA_DST_SEL(0) | (wc ? WR_CONFIRM : 0));
3746         amdgpu_ring_write(ring, reg);
3747         amdgpu_ring_write(ring, 0);
3748         amdgpu_ring_write(ring, val);
3749 }
3750
3751 static void gfx_v10_0_wait_reg_mem(struct amdgpu_ring *ring, int eng_sel,
3752                                   int mem_space, int opt, uint32_t addr0,
3753                                   uint32_t addr1, uint32_t ref, uint32_t mask,
3754                                   uint32_t inv)
3755 {
3756         amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
3757         amdgpu_ring_write(ring,
3758                           /* memory (1) or register (0) */
3759                           (WAIT_REG_MEM_MEM_SPACE(mem_space) |
3760                            WAIT_REG_MEM_OPERATION(opt) | /* wait */
3761                            WAIT_REG_MEM_FUNCTION(3) |  /* equal */
3762                            WAIT_REG_MEM_ENGINE(eng_sel)));
3763
3764         if (mem_space)
3765                 BUG_ON(addr0 & 0x3); /* Dword align */
3766         amdgpu_ring_write(ring, addr0);
3767         amdgpu_ring_write(ring, addr1);
3768         amdgpu_ring_write(ring, ref);
3769         amdgpu_ring_write(ring, mask);
3770         amdgpu_ring_write(ring, inv); /* poll interval */
3771 }
3772
3773 static int gfx_v10_0_ring_test_ring(struct amdgpu_ring *ring)
3774 {
3775         struct amdgpu_device *adev = ring->adev;
3776         uint32_t scratch = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG0);
3777         uint32_t tmp = 0;
3778         unsigned int i;
3779         int r;
3780
3781         WREG32(scratch, 0xCAFEDEAD);
3782         r = amdgpu_ring_alloc(ring, 3);
3783         if (r) {
3784                 DRM_ERROR("amdgpu: cp failed to lock ring %d (%d).\n",
3785                           ring->idx, r);
3786                 return r;
3787         }
3788
3789         amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1));
3790         amdgpu_ring_write(ring, scratch -
3791                           PACKET3_SET_UCONFIG_REG_START);
3792         amdgpu_ring_write(ring, 0xDEADBEEF);
3793         amdgpu_ring_commit(ring);
3794
3795         for (i = 0; i < adev->usec_timeout; i++) {
3796                 tmp = RREG32(scratch);
3797                 if (tmp == 0xDEADBEEF)
3798                         break;
3799                 if (amdgpu_emu_mode == 1)
3800                         msleep(1);
3801                 else
3802                         udelay(1);
3803         }
3804
3805         if (i >= adev->usec_timeout)
3806                 r = -ETIMEDOUT;
3807
3808         return r;
3809 }
3810
3811 static int gfx_v10_0_ring_test_ib(struct amdgpu_ring *ring, long timeout)
3812 {
3813         struct amdgpu_device *adev = ring->adev;
3814         struct amdgpu_ib ib;
3815         struct dma_fence *f = NULL;
3816         unsigned int index;
3817         uint64_t gpu_addr;
3818         volatile uint32_t *cpu_ptr;
3819         long r;
3820
3821         memset(&ib, 0, sizeof(ib));
3822
3823         if (ring->is_mes_queue) {
3824                 uint32_t padding, offset;
3825
3826                 offset = amdgpu_mes_ctx_get_offs(ring, AMDGPU_MES_CTX_IB_OFFS);
3827                 padding = amdgpu_mes_ctx_get_offs(ring,
3828                                                   AMDGPU_MES_CTX_PADDING_OFFS);
3829
3830                 ib.gpu_addr = amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset);
3831                 ib.ptr = amdgpu_mes_ctx_get_offs_cpu_addr(ring, offset);
3832
3833                 gpu_addr = amdgpu_mes_ctx_get_offs_gpu_addr(ring, padding);
3834                 cpu_ptr = amdgpu_mes_ctx_get_offs_cpu_addr(ring, padding);
3835                 *cpu_ptr = cpu_to_le32(0xCAFEDEAD);
3836         } else {
3837                 r = amdgpu_device_wb_get(adev, &index);
3838                 if (r)
3839                         return r;
3840
3841                 gpu_addr = adev->wb.gpu_addr + (index * 4);
3842                 adev->wb.wb[index] = cpu_to_le32(0xCAFEDEAD);
3843                 cpu_ptr = &adev->wb.wb[index];
3844
3845                 r = amdgpu_ib_get(adev, NULL, 20, AMDGPU_IB_POOL_DIRECT, &ib);
3846                 if (r) {
3847                         DRM_ERROR("amdgpu: failed to get ib (%ld).\n", r);
3848                         goto err1;
3849                 }
3850         }
3851
3852         ib.ptr[0] = PACKET3(PACKET3_WRITE_DATA, 3);
3853         ib.ptr[1] = WRITE_DATA_DST_SEL(5) | WR_CONFIRM;
3854         ib.ptr[2] = lower_32_bits(gpu_addr);
3855         ib.ptr[3] = upper_32_bits(gpu_addr);
3856         ib.ptr[4] = 0xDEADBEEF;
3857         ib.length_dw = 5;
3858
3859         r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
3860         if (r)
3861                 goto err2;
3862
3863         r = dma_fence_wait_timeout(f, false, timeout);
3864         if (r == 0) {
3865                 r = -ETIMEDOUT;
3866                 goto err2;
3867         } else if (r < 0) {
3868                 goto err2;
3869         }
3870
3871         if (le32_to_cpu(*cpu_ptr) == 0xDEADBEEF)
3872                 r = 0;
3873         else
3874                 r = -EINVAL;
3875 err2:
3876         if (!ring->is_mes_queue)
3877                 amdgpu_ib_free(adev, &ib, NULL);
3878         dma_fence_put(f);
3879 err1:
3880         if (!ring->is_mes_queue)
3881                 amdgpu_device_wb_free(adev, index);
3882         return r;
3883 }
3884
3885 static void gfx_v10_0_free_microcode(struct amdgpu_device *adev)
3886 {
3887         amdgpu_ucode_release(&adev->gfx.pfp_fw);
3888         amdgpu_ucode_release(&adev->gfx.me_fw);
3889         amdgpu_ucode_release(&adev->gfx.ce_fw);
3890         amdgpu_ucode_release(&adev->gfx.rlc_fw);
3891         amdgpu_ucode_release(&adev->gfx.mec_fw);
3892         amdgpu_ucode_release(&adev->gfx.mec2_fw);
3893
3894         kfree(adev->gfx.rlc.register_list_format);
3895 }
3896
3897 static void gfx_v10_0_check_fw_write_wait(struct amdgpu_device *adev)
3898 {
3899         adev->gfx.cp_fw_write_wait = false;
3900
3901         switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
3902         case IP_VERSION(10, 1, 10):
3903         case IP_VERSION(10, 1, 2):
3904         case IP_VERSION(10, 1, 1):
3905         case IP_VERSION(10, 1, 3):
3906         case IP_VERSION(10, 1, 4):
3907                 if ((adev->gfx.me_fw_version >= 0x00000046) &&
3908                     (adev->gfx.me_feature_version >= 27) &&
3909                     (adev->gfx.pfp_fw_version >= 0x00000068) &&
3910                     (adev->gfx.pfp_feature_version >= 27) &&
3911                     (adev->gfx.mec_fw_version >= 0x0000005b) &&
3912                     (adev->gfx.mec_feature_version >= 27))
3913                         adev->gfx.cp_fw_write_wait = true;
3914                 break;
3915         case IP_VERSION(10, 3, 0):
3916         case IP_VERSION(10, 3, 2):
3917         case IP_VERSION(10, 3, 1):
3918         case IP_VERSION(10, 3, 4):
3919         case IP_VERSION(10, 3, 5):
3920         case IP_VERSION(10, 3, 6):
3921         case IP_VERSION(10, 3, 3):
3922         case IP_VERSION(10, 3, 7):
3923                 adev->gfx.cp_fw_write_wait = true;
3924                 break;
3925         default:
3926                 break;
3927         }
3928
3929         if (!adev->gfx.cp_fw_write_wait)
3930                 DRM_WARN_ONCE("CP firmware version too old, please update!");
3931 }
3932
3933 static bool gfx_v10_0_navi10_gfxoff_should_enable(struct amdgpu_device *adev)
3934 {
3935         bool ret = false;
3936
3937         switch (adev->pdev->revision) {
3938         case 0xc2:
3939         case 0xc3:
3940                 ret = true;
3941                 break;
3942         default:
3943                 ret = false;
3944                 break;
3945         }
3946
3947         return ret;
3948 }
3949
3950 static void gfx_v10_0_check_gfxoff_flag(struct amdgpu_device *adev)
3951 {
3952         switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
3953         case IP_VERSION(10, 1, 10):
3954                 if (!gfx_v10_0_navi10_gfxoff_should_enable(adev))
3955                         adev->pm.pp_feature &= ~PP_GFXOFF_MASK;
3956                 break;
3957         default:
3958                 break;
3959         }
3960 }
3961
3962 static int gfx_v10_0_init_microcode(struct amdgpu_device *adev)
3963 {
3964         char fw_name[40];
3965         char ucode_prefix[30];
3966         const char *wks = "";
3967         int err;
3968         const struct rlc_firmware_header_v2_0 *rlc_hdr;
3969         uint16_t version_major;
3970         uint16_t version_minor;
3971
3972         DRM_DEBUG("\n");
3973
3974         if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(10, 1, 1) &&
3975             (!(adev->pdev->device == 0x7340 && adev->pdev->revision != 0x00)))
3976                 wks = "_wks";
3977         amdgpu_ucode_ip_version_decode(adev, GC_HWIP, ucode_prefix, sizeof(ucode_prefix));
3978
3979         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_pfp%s.bin", ucode_prefix, wks);
3980         err = amdgpu_ucode_request(adev, &adev->gfx.pfp_fw, fw_name);
3981         if (err)
3982                 goto out;
3983         amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_PFP);
3984
3985         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_me%s.bin", ucode_prefix, wks);
3986         err = amdgpu_ucode_request(adev, &adev->gfx.me_fw, fw_name);
3987         if (err)
3988                 goto out;
3989         amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_ME);
3990
3991         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ce%s.bin", ucode_prefix, wks);
3992         err = amdgpu_ucode_request(adev, &adev->gfx.ce_fw, fw_name);
3993         if (err)
3994                 goto out;
3995         amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_CE);
3996
3997         if (!amdgpu_sriov_vf(adev)) {
3998                 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_rlc.bin", ucode_prefix);
3999                 err = amdgpu_ucode_request(adev, &adev->gfx.rlc_fw, fw_name);
4000                 /* don't check this.  There are apparently firmwares in the wild with
4001                  * incorrect size in the header
4002                  */
4003                 if (err == -ENODEV)
4004                         goto out;
4005                 if (err)
4006                         dev_dbg(adev->dev,
4007                                 "gfx10: amdgpu_ucode_request() failed \"%s\"\n",
4008                                 fw_name);
4009                 rlc_hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data;
4010                 version_major = le16_to_cpu(rlc_hdr->header.header_version_major);
4011                 version_minor = le16_to_cpu(rlc_hdr->header.header_version_minor);
4012                 err = amdgpu_gfx_rlc_init_microcode(adev, version_major, version_minor);
4013                 if (err)
4014                         goto out;
4015         }
4016
4017         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec%s.bin", ucode_prefix, wks);
4018         err = amdgpu_ucode_request(adev, &adev->gfx.mec_fw, fw_name);
4019         if (err)
4020                 goto out;
4021         amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC1);
4022         amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC1_JT);
4023
4024         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec2%s.bin", ucode_prefix, wks);
4025         err = amdgpu_ucode_request(adev, &adev->gfx.mec2_fw, fw_name);
4026         if (!err) {
4027                 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC2);
4028                 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC2_JT);
4029         } else {
4030                 err = 0;
4031                 adev->gfx.mec2_fw = NULL;
4032         }
4033         amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC2);
4034         amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC2_JT);
4035
4036         gfx_v10_0_check_fw_write_wait(adev);
4037 out:
4038         if (err) {
4039                 amdgpu_ucode_release(&adev->gfx.pfp_fw);
4040                 amdgpu_ucode_release(&adev->gfx.me_fw);
4041                 amdgpu_ucode_release(&adev->gfx.ce_fw);
4042                 amdgpu_ucode_release(&adev->gfx.rlc_fw);
4043                 amdgpu_ucode_release(&adev->gfx.mec_fw);
4044                 amdgpu_ucode_release(&adev->gfx.mec2_fw);
4045         }
4046
4047         gfx_v10_0_check_gfxoff_flag(adev);
4048
4049         return err;
4050 }
4051
4052 static u32 gfx_v10_0_get_csb_size(struct amdgpu_device *adev)
4053 {
4054         u32 count = 0;
4055         const struct cs_section_def *sect = NULL;
4056         const struct cs_extent_def *ext = NULL;
4057
4058         /* begin clear state */
4059         count += 2;
4060         /* context control state */
4061         count += 3;
4062
4063         for (sect = gfx10_cs_data; sect->section != NULL; ++sect) {
4064                 for (ext = sect->section; ext->extent != NULL; ++ext) {
4065                         if (sect->id == SECT_CONTEXT)
4066                                 count += 2 + ext->reg_count;
4067                         else
4068                                 return 0;
4069                 }
4070         }
4071
4072         /* set PA_SC_TILE_STEERING_OVERRIDE */
4073         count += 3;
4074         /* end clear state */
4075         count += 2;
4076         /* clear state */
4077         count += 2;
4078
4079         return count;
4080 }
4081
4082 static void gfx_v10_0_get_csb_buffer(struct amdgpu_device *adev,
4083                                     volatile u32 *buffer)
4084 {
4085         u32 count = 0, i;
4086         const struct cs_section_def *sect = NULL;
4087         const struct cs_extent_def *ext = NULL;
4088         int ctx_reg_offset;
4089
4090         if (adev->gfx.rlc.cs_data == NULL)
4091                 return;
4092         if (buffer == NULL)
4093                 return;
4094
4095         buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));
4096         buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
4097
4098         buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CONTEXT_CONTROL, 1));
4099         buffer[count++] = cpu_to_le32(0x80000000);
4100         buffer[count++] = cpu_to_le32(0x80000000);
4101
4102         for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) {
4103                 for (ext = sect->section; ext->extent != NULL; ++ext) {
4104                         if (sect->id == SECT_CONTEXT) {
4105                                 buffer[count++] =
4106                                         cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count));
4107                                 buffer[count++] = cpu_to_le32(ext->reg_index -
4108                                                 PACKET3_SET_CONTEXT_REG_START);
4109                                 for (i = 0; i < ext->reg_count; i++)
4110                                         buffer[count++] = cpu_to_le32(ext->extent[i]);
4111                         } else {
4112                                 return;
4113                         }
4114                 }
4115         }
4116
4117         ctx_reg_offset =
4118                 SOC15_REG_OFFSET(GC, 0, mmPA_SC_TILE_STEERING_OVERRIDE) - PACKET3_SET_CONTEXT_REG_START;
4119         buffer[count++] = cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, 1));
4120         buffer[count++] = cpu_to_le32(ctx_reg_offset);
4121         buffer[count++] = cpu_to_le32(adev->gfx.config.pa_sc_tile_steering_override);
4122
4123         buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));
4124         buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_END_CLEAR_STATE);
4125
4126         buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CLEAR_STATE, 0));
4127         buffer[count++] = cpu_to_le32(0);
4128 }
4129
4130 static void gfx_v10_0_rlc_fini(struct amdgpu_device *adev)
4131 {
4132         /* clear state block */
4133         amdgpu_bo_free_kernel(&adev->gfx.rlc.clear_state_obj,
4134                         &adev->gfx.rlc.clear_state_gpu_addr,
4135                         (void **)&adev->gfx.rlc.cs_ptr);
4136
4137         /* jump table block */
4138         amdgpu_bo_free_kernel(&adev->gfx.rlc.cp_table_obj,
4139                         &adev->gfx.rlc.cp_table_gpu_addr,
4140                         (void **)&adev->gfx.rlc.cp_table_ptr);
4141 }
4142
4143 static void gfx_v10_0_init_rlcg_reg_access_ctrl(struct amdgpu_device *adev)
4144 {
4145         struct amdgpu_rlcg_reg_access_ctrl *reg_access_ctrl;
4146
4147         reg_access_ctrl = &adev->gfx.rlc.reg_access_ctrl[0];
4148         reg_access_ctrl->scratch_reg0 = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG0);
4149         reg_access_ctrl->scratch_reg1 = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG1);
4150         reg_access_ctrl->scratch_reg2 = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG2);
4151         reg_access_ctrl->scratch_reg3 = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG3);
4152         reg_access_ctrl->grbm_cntl = SOC15_REG_OFFSET(GC, 0, mmGRBM_GFX_CNTL);
4153         reg_access_ctrl->grbm_idx = SOC15_REG_OFFSET(GC, 0, mmGRBM_GFX_INDEX);
4154         switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
4155         case IP_VERSION(10, 3, 0):
4156                 reg_access_ctrl->spare_int =
4157                         SOC15_REG_OFFSET(GC, 0, mmRLC_SPARE_INT_0_Sienna_Cichlid);
4158                 break;
4159         default:
4160                 reg_access_ctrl->spare_int =
4161                         SOC15_REG_OFFSET(GC, 0, mmRLC_SPARE_INT);
4162                 break;
4163         }
4164         adev->gfx.rlc.rlcg_reg_access_supported = true;
4165 }
4166
4167 static int gfx_v10_0_rlc_init(struct amdgpu_device *adev)
4168 {
4169         const struct cs_section_def *cs_data;
4170         int r;
4171
4172         adev->gfx.rlc.cs_data = gfx10_cs_data;
4173
4174         cs_data = adev->gfx.rlc.cs_data;
4175
4176         if (cs_data) {
4177                 /* init clear state block */
4178                 r = amdgpu_gfx_rlc_init_csb(adev);
4179                 if (r)
4180                         return r;
4181         }
4182
4183         return 0;
4184 }
4185
4186 static void gfx_v10_0_mec_fini(struct amdgpu_device *adev)
4187 {
4188         amdgpu_bo_free_kernel(&adev->gfx.mec.hpd_eop_obj, NULL, NULL);
4189         amdgpu_bo_free_kernel(&adev->gfx.mec.mec_fw_obj, NULL, NULL);
4190 }
4191
4192 static void gfx_v10_0_me_init(struct amdgpu_device *adev)
4193 {
4194         bitmap_zero(adev->gfx.me.queue_bitmap, AMDGPU_MAX_GFX_QUEUES);
4195
4196         amdgpu_gfx_graphics_queue_acquire(adev);
4197 }
4198
4199 static int gfx_v10_0_mec_init(struct amdgpu_device *adev)
4200 {
4201         int r;
4202         u32 *hpd;
4203         const __le32 *fw_data = NULL;
4204         unsigned int fw_size;
4205         u32 *fw = NULL;
4206         size_t mec_hpd_size;
4207
4208         const struct gfx_firmware_header_v1_0 *mec_hdr = NULL;
4209
4210         bitmap_zero(adev->gfx.mec_bitmap[0].queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES);
4211
4212         /* take ownership of the relevant compute queues */
4213         amdgpu_gfx_compute_queue_acquire(adev);
4214         mec_hpd_size = adev->gfx.num_compute_rings * GFX10_MEC_HPD_SIZE;
4215
4216         if (mec_hpd_size) {
4217                 r = amdgpu_bo_create_reserved(adev, mec_hpd_size, PAGE_SIZE,
4218                                               AMDGPU_GEM_DOMAIN_GTT,
4219                                               &adev->gfx.mec.hpd_eop_obj,
4220                                               &adev->gfx.mec.hpd_eop_gpu_addr,
4221                                               (void **)&hpd);
4222                 if (r) {
4223                         dev_warn(adev->dev, "(%d) create HDP EOP bo failed\n", r);
4224                         gfx_v10_0_mec_fini(adev);
4225                         return r;
4226                 }
4227
4228                 memset(hpd, 0, mec_hpd_size);
4229
4230                 amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj);
4231                 amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj);
4232         }
4233
4234         if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
4235                 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
4236
4237                 fw_data = (const __le32 *) (adev->gfx.mec_fw->data +
4238                          le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes));
4239                 fw_size = le32_to_cpu(mec_hdr->header.ucode_size_bytes);
4240
4241                 r = amdgpu_bo_create_reserved(adev, mec_hdr->header.ucode_size_bytes,
4242                                               PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,
4243                                               &adev->gfx.mec.mec_fw_obj,
4244                                               &adev->gfx.mec.mec_fw_gpu_addr,
4245                                               (void **)&fw);
4246                 if (r) {
4247                         dev_err(adev->dev, "(%d) failed to create mec fw bo\n", r);
4248                         gfx_v10_0_mec_fini(adev);
4249                         return r;
4250                 }
4251
4252                 memcpy(fw, fw_data, fw_size);
4253
4254                 amdgpu_bo_kunmap(adev->gfx.mec.mec_fw_obj);
4255                 amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_obj);
4256         }
4257
4258         return 0;
4259 }
4260
4261 static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t wave, uint32_t address)
4262 {
4263         WREG32_SOC15(GC, 0, mmSQ_IND_INDEX,
4264                 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) |
4265                 (address << SQ_IND_INDEX__INDEX__SHIFT));
4266         return RREG32_SOC15(GC, 0, mmSQ_IND_DATA);
4267 }
4268
4269 static void wave_read_regs(struct amdgpu_device *adev, uint32_t wave,
4270                            uint32_t thread, uint32_t regno,
4271                            uint32_t num, uint32_t *out)
4272 {
4273         WREG32_SOC15(GC, 0, mmSQ_IND_INDEX,
4274                 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) |
4275                 (regno << SQ_IND_INDEX__INDEX__SHIFT) |
4276                 (thread << SQ_IND_INDEX__WORKITEM_ID__SHIFT) |
4277                 (SQ_IND_INDEX__AUTO_INCR_MASK));
4278         while (num--)
4279                 *(out++) = RREG32_SOC15(GC, 0, mmSQ_IND_DATA);
4280 }
4281
4282 static void gfx_v10_0_read_wave_data(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, uint32_t wave, uint32_t *dst, int *no_fields)
4283 {
4284         /* in gfx10 the SIMD_ID is specified as part of the INSTANCE
4285          * field when performing a select_se_sh so it should be
4286          * zero here
4287          */
4288         WARN_ON(simd != 0);
4289
4290         /* type 2 wave data */
4291         dst[(*no_fields)++] = 2;
4292         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_STATUS);
4293         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_PC_LO);
4294         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_PC_HI);
4295         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXEC_LO);
4296         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXEC_HI);
4297         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_HW_ID1);
4298         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_HW_ID2);
4299         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_INST_DW0);
4300         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_GPR_ALLOC);
4301         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_LDS_ALLOC);
4302         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_TRAPSTS);
4303         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_STS);
4304         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_STS2);
4305         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_DBG1);
4306         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_M0);
4307         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_MODE);
4308 }
4309
4310 static void gfx_v10_0_read_wave_sgprs(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd,
4311                                      uint32_t wave, uint32_t start,
4312                                      uint32_t size, uint32_t *dst)
4313 {
4314         WARN_ON(simd != 0);
4315
4316         wave_read_regs(
4317                 adev, wave, 0, start + SQIND_WAVE_SGPRS_OFFSET, size,
4318                 dst);
4319 }
4320
4321 static void gfx_v10_0_read_wave_vgprs(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd,
4322                                       uint32_t wave, uint32_t thread,
4323                                       uint32_t start, uint32_t size,
4324                                       uint32_t *dst)
4325 {
4326         wave_read_regs(
4327                 adev, wave, thread,
4328                 start + SQIND_WAVE_VGPRS_OFFSET, size, dst);
4329 }
4330
4331 static void gfx_v10_0_select_me_pipe_q(struct amdgpu_device *adev,
4332                                        u32 me, u32 pipe, u32 q, u32 vm, u32 xcc_id)
4333 {
4334         nv_grbm_select(adev, me, pipe, q, vm);
4335 }
4336
4337 static void gfx_v10_0_update_perfmon_mgcg(struct amdgpu_device *adev,
4338                                           bool enable)
4339 {
4340         uint32_t data, def;
4341
4342         data = def = RREG32_SOC15(GC, 0, mmRLC_PERFMON_CLK_CNTL);
4343
4344         if (enable)
4345                 data |= RLC_PERFMON_CLK_CNTL__PERFMON_CLOCK_STATE_MASK;
4346         else
4347                 data &= ~RLC_PERFMON_CLK_CNTL__PERFMON_CLOCK_STATE_MASK;
4348
4349         if (data != def)
4350                 WREG32_SOC15(GC, 0, mmRLC_PERFMON_CLK_CNTL, data);
4351 }
4352
4353 static const struct amdgpu_gfx_funcs gfx_v10_0_gfx_funcs = {
4354         .get_gpu_clock_counter = &gfx_v10_0_get_gpu_clock_counter,
4355         .select_se_sh = &gfx_v10_0_select_se_sh,
4356         .read_wave_data = &gfx_v10_0_read_wave_data,
4357         .read_wave_sgprs = &gfx_v10_0_read_wave_sgprs,
4358         .read_wave_vgprs = &gfx_v10_0_read_wave_vgprs,
4359         .select_me_pipe_q = &gfx_v10_0_select_me_pipe_q,
4360         .init_spm_golden = &gfx_v10_0_init_spm_golden_registers,
4361         .update_perfmon_mgcg = &gfx_v10_0_update_perfmon_mgcg,
4362 };
4363
4364 static void gfx_v10_0_gpu_early_init(struct amdgpu_device *adev)
4365 {
4366         u32 gb_addr_config;
4367
4368         switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
4369         case IP_VERSION(10, 1, 10):
4370         case IP_VERSION(10, 1, 1):
4371         case IP_VERSION(10, 1, 2):
4372                 adev->gfx.config.max_hw_contexts = 8;
4373                 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
4374                 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
4375                 adev->gfx.config.sc_hiz_tile_fifo_size = 0;
4376                 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0;
4377                 gb_addr_config = RREG32_SOC15(GC, 0, mmGB_ADDR_CONFIG);
4378                 break;
4379         case IP_VERSION(10, 3, 0):
4380         case IP_VERSION(10, 3, 2):
4381         case IP_VERSION(10, 3, 1):
4382         case IP_VERSION(10, 3, 4):
4383         case IP_VERSION(10, 3, 5):
4384         case IP_VERSION(10, 3, 6):
4385         case IP_VERSION(10, 3, 3):
4386         case IP_VERSION(10, 3, 7):
4387                 adev->gfx.config.max_hw_contexts = 8;
4388                 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
4389                 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
4390                 adev->gfx.config.sc_hiz_tile_fifo_size = 0;
4391                 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0;
4392                 gb_addr_config = RREG32_SOC15(GC, 0, mmGB_ADDR_CONFIG);
4393                 adev->gfx.config.gb_addr_config_fields.num_pkrs =
4394                         1 << REG_GET_FIELD(gb_addr_config, GB_ADDR_CONFIG, NUM_PKRS);
4395                 break;
4396         case IP_VERSION(10, 1, 3):
4397         case IP_VERSION(10, 1, 4):
4398                 adev->gfx.config.max_hw_contexts = 8;
4399                 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
4400                 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
4401                 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
4402                 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0;
4403                 gb_addr_config = CYAN_SKILLFISH_GB_ADDR_CONFIG_GOLDEN;
4404                 break;
4405         default:
4406                 BUG();
4407                 break;
4408         }
4409
4410         adev->gfx.config.gb_addr_config = gb_addr_config;
4411
4412         adev->gfx.config.gb_addr_config_fields.num_pipes = 1 <<
4413                         REG_GET_FIELD(adev->gfx.config.gb_addr_config,
4414                                       GB_ADDR_CONFIG, NUM_PIPES);
4415
4416         adev->gfx.config.max_tile_pipes =
4417                 adev->gfx.config.gb_addr_config_fields.num_pipes;
4418
4419         adev->gfx.config.gb_addr_config_fields.max_compress_frags = 1 <<
4420                         REG_GET_FIELD(adev->gfx.config.gb_addr_config,
4421                                       GB_ADDR_CONFIG, MAX_COMPRESSED_FRAGS);
4422         adev->gfx.config.gb_addr_config_fields.num_rb_per_se = 1 <<
4423                         REG_GET_FIELD(adev->gfx.config.gb_addr_config,
4424                                       GB_ADDR_CONFIG, NUM_RB_PER_SE);
4425         adev->gfx.config.gb_addr_config_fields.num_se = 1 <<
4426                         REG_GET_FIELD(adev->gfx.config.gb_addr_config,
4427                                       GB_ADDR_CONFIG, NUM_SHADER_ENGINES);
4428         adev->gfx.config.gb_addr_config_fields.pipe_interleave_size = 1 << (8 +
4429                         REG_GET_FIELD(adev->gfx.config.gb_addr_config,
4430                                       GB_ADDR_CONFIG, PIPE_INTERLEAVE_SIZE));
4431 }
4432
4433 static int gfx_v10_0_gfx_ring_init(struct amdgpu_device *adev, int ring_id,
4434                                    int me, int pipe, int queue)
4435 {
4436         struct amdgpu_ring *ring;
4437         unsigned int irq_type;
4438         unsigned int hw_prio;
4439
4440         ring = &adev->gfx.gfx_ring[ring_id];
4441
4442         ring->me = me;
4443         ring->pipe = pipe;
4444         ring->queue = queue;
4445
4446         ring->ring_obj = NULL;
4447         ring->use_doorbell = true;
4448
4449         if (!ring_id)
4450                 ring->doorbell_index = adev->doorbell_index.gfx_ring0 << 1;
4451         else
4452                 ring->doorbell_index = adev->doorbell_index.gfx_ring1 << 1;
4453         ring->vm_hub = AMDGPU_GFXHUB(0);
4454         sprintf(ring->name, "gfx_%d.%d.%d", ring->me, ring->pipe, ring->queue);
4455
4456         irq_type = AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP + ring->pipe;
4457         hw_prio = amdgpu_gfx_is_high_priority_graphics_queue(adev, ring) ?
4458                         AMDGPU_GFX_PIPE_PRIO_HIGH : AMDGPU_GFX_PIPE_PRIO_NORMAL;
4459         return amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, irq_type,
4460                                 hw_prio, NULL);
4461 }
4462
4463 static int gfx_v10_0_compute_ring_init(struct amdgpu_device *adev, int ring_id,
4464                                        int mec, int pipe, int queue)
4465 {
4466         unsigned int irq_type;
4467         struct amdgpu_ring *ring;
4468         unsigned int hw_prio;
4469
4470         ring = &adev->gfx.compute_ring[ring_id];
4471
4472         /* mec0 is me1 */
4473         ring->me = mec + 1;
4474         ring->pipe = pipe;
4475         ring->queue = queue;
4476
4477         ring->ring_obj = NULL;
4478         ring->use_doorbell = true;
4479         ring->doorbell_index = (adev->doorbell_index.mec_ring0 + ring_id) << 1;
4480         ring->eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr
4481                                 + (ring_id * GFX10_MEC_HPD_SIZE);
4482         ring->vm_hub = AMDGPU_GFXHUB(0);
4483         sprintf(ring->name, "comp_%d.%d.%d", ring->me, ring->pipe, ring->queue);
4484
4485         irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP
4486                 + ((ring->me - 1) * adev->gfx.mec.num_pipe_per_mec)
4487                 + ring->pipe;
4488         hw_prio = amdgpu_gfx_is_high_priority_compute_queue(adev, ring) ?
4489                         AMDGPU_RING_PRIO_2 : AMDGPU_RING_PRIO_DEFAULT;
4490         /* type-2 packets are deprecated on MEC, use type-3 instead */
4491         return amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, irq_type,
4492                              hw_prio, NULL);
4493 }
4494
4495 static int gfx_v10_0_sw_init(void *handle)
4496 {
4497         int i, j, k, r, ring_id = 0;
4498         struct amdgpu_kiq *kiq;
4499         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4500
4501         switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
4502         case IP_VERSION(10, 1, 10):
4503         case IP_VERSION(10, 1, 1):
4504         case IP_VERSION(10, 1, 2):
4505         case IP_VERSION(10, 1, 3):
4506         case IP_VERSION(10, 1, 4):
4507                 adev->gfx.me.num_me = 1;
4508                 adev->gfx.me.num_pipe_per_me = 1;
4509                 adev->gfx.me.num_queue_per_pipe = 1;
4510                 adev->gfx.mec.num_mec = 2;
4511                 adev->gfx.mec.num_pipe_per_mec = 4;
4512                 adev->gfx.mec.num_queue_per_pipe = 8;
4513                 break;
4514         case IP_VERSION(10, 3, 0):
4515         case IP_VERSION(10, 3, 2):
4516         case IP_VERSION(10, 3, 1):
4517         case IP_VERSION(10, 3, 4):
4518         case IP_VERSION(10, 3, 5):
4519         case IP_VERSION(10, 3, 6):
4520         case IP_VERSION(10, 3, 3):
4521         case IP_VERSION(10, 3, 7):
4522                 adev->gfx.me.num_me = 1;
4523                 adev->gfx.me.num_pipe_per_me = 1;
4524                 adev->gfx.me.num_queue_per_pipe = 1;
4525                 adev->gfx.mec.num_mec = 2;
4526                 adev->gfx.mec.num_pipe_per_mec = 4;
4527                 adev->gfx.mec.num_queue_per_pipe = 4;
4528                 break;
4529         default:
4530                 adev->gfx.me.num_me = 1;
4531                 adev->gfx.me.num_pipe_per_me = 1;
4532                 adev->gfx.me.num_queue_per_pipe = 1;
4533                 adev->gfx.mec.num_mec = 1;
4534                 adev->gfx.mec.num_pipe_per_mec = 4;
4535                 adev->gfx.mec.num_queue_per_pipe = 8;
4536                 break;
4537         }
4538
4539         /* KIQ event */
4540         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP,
4541                               GFX_10_1__SRCID__CP_IB2_INTERRUPT_PKT,
4542                               &adev->gfx.kiq[0].irq);
4543         if (r)
4544                 return r;
4545
4546         /* EOP Event */
4547         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP,
4548                               GFX_10_1__SRCID__CP_EOP_INTERRUPT,
4549                               &adev->gfx.eop_irq);
4550         if (r)
4551                 return r;
4552
4553         /* Privileged reg */
4554         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_10_1__SRCID__CP_PRIV_REG_FAULT,
4555                               &adev->gfx.priv_reg_irq);
4556         if (r)
4557                 return r;
4558
4559         /* Privileged inst */
4560         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_10_1__SRCID__CP_PRIV_INSTR_FAULT,
4561                               &adev->gfx.priv_inst_irq);
4562         if (r)
4563                 return r;
4564
4565         adev->gfx.gfx_current_status = AMDGPU_GFX_NORMAL_MODE;
4566
4567         gfx_v10_0_me_init(adev);
4568
4569         if (adev->gfx.rlc.funcs) {
4570                 if (adev->gfx.rlc.funcs->init) {
4571                         r = adev->gfx.rlc.funcs->init(adev);
4572                         if (r) {
4573                                 dev_err(adev->dev, "Failed to init rlc BOs!\n");
4574                                 return r;
4575                         }
4576                 }
4577         }
4578
4579         r = gfx_v10_0_mec_init(adev);
4580         if (r) {
4581                 DRM_ERROR("Failed to init MEC BOs!\n");
4582                 return r;
4583         }
4584
4585         /* set up the gfx ring */
4586         for (i = 0; i < adev->gfx.me.num_me; i++) {
4587                 for (j = 0; j < adev->gfx.me.num_queue_per_pipe; j++) {
4588                         for (k = 0; k < adev->gfx.me.num_pipe_per_me; k++) {
4589                                 if (!amdgpu_gfx_is_me_queue_enabled(adev, i, k, j))
4590                                         continue;
4591
4592                                 r = gfx_v10_0_gfx_ring_init(adev, ring_id,
4593                                                             i, k, j);
4594                                 if (r)
4595                                         return r;
4596                                 ring_id++;
4597                         }
4598                 }
4599         }
4600
4601         ring_id = 0;
4602         /* set up the compute queues - allocate horizontally across pipes */
4603         for (i = 0; i < adev->gfx.mec.num_mec; ++i) {
4604                 for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) {
4605                         for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) {
4606                                 if (!amdgpu_gfx_is_mec_queue_enabled(adev, 0, i,
4607                                                                      k, j))
4608                                         continue;
4609
4610                                 r = gfx_v10_0_compute_ring_init(adev, ring_id,
4611                                                                 i, k, j);
4612                                 if (r)
4613                                         return r;
4614
4615                                 ring_id++;
4616                         }
4617                 }
4618         }
4619
4620         if (!adev->enable_mes_kiq) {
4621                 r = amdgpu_gfx_kiq_init(adev, GFX10_MEC_HPD_SIZE, 0);
4622                 if (r) {
4623                         DRM_ERROR("Failed to init KIQ BOs!\n");
4624                         return r;
4625                 }
4626
4627                 kiq = &adev->gfx.kiq[0];
4628                 r = amdgpu_gfx_kiq_init_ring(adev, &kiq->ring, &kiq->irq, 0);
4629                 if (r)
4630                         return r;
4631         }
4632
4633         r = amdgpu_gfx_mqd_sw_init(adev, sizeof(struct v10_compute_mqd), 0);
4634         if (r)
4635                 return r;
4636
4637         /* allocate visible FB for rlc auto-loading fw */
4638         if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) {
4639                 r = gfx_v10_0_rlc_backdoor_autoload_buffer_init(adev);
4640                 if (r)
4641                         return r;
4642         }
4643
4644         adev->gfx.ce_ram_size = F32_CE_PROGRAM_RAM_SIZE;
4645
4646         gfx_v10_0_gpu_early_init(adev);
4647
4648         return 0;
4649 }
4650
4651 static void gfx_v10_0_pfp_fini(struct amdgpu_device *adev)
4652 {
4653         amdgpu_bo_free_kernel(&adev->gfx.pfp.pfp_fw_obj,
4654                               &adev->gfx.pfp.pfp_fw_gpu_addr,
4655                               (void **)&adev->gfx.pfp.pfp_fw_ptr);
4656 }
4657
4658 static void gfx_v10_0_ce_fini(struct amdgpu_device *adev)
4659 {
4660         amdgpu_bo_free_kernel(&adev->gfx.ce.ce_fw_obj,
4661                               &adev->gfx.ce.ce_fw_gpu_addr,
4662                               (void **)&adev->gfx.ce.ce_fw_ptr);
4663 }
4664
4665 static void gfx_v10_0_me_fini(struct amdgpu_device *adev)
4666 {
4667         amdgpu_bo_free_kernel(&adev->gfx.me.me_fw_obj,
4668                               &adev->gfx.me.me_fw_gpu_addr,
4669                               (void **)&adev->gfx.me.me_fw_ptr);
4670 }
4671
4672 static int gfx_v10_0_sw_fini(void *handle)
4673 {
4674         int i;
4675         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4676
4677         for (i = 0; i < adev->gfx.num_gfx_rings; i++)
4678                 amdgpu_ring_fini(&adev->gfx.gfx_ring[i]);
4679         for (i = 0; i < adev->gfx.num_compute_rings; i++)
4680                 amdgpu_ring_fini(&adev->gfx.compute_ring[i]);
4681
4682         amdgpu_gfx_mqd_sw_fini(adev, 0);
4683
4684         if (!adev->enable_mes_kiq) {
4685                 amdgpu_gfx_kiq_free_ring(&adev->gfx.kiq[0].ring);
4686                 amdgpu_gfx_kiq_fini(adev, 0);
4687         }
4688
4689         gfx_v10_0_pfp_fini(adev);
4690         gfx_v10_0_ce_fini(adev);
4691         gfx_v10_0_me_fini(adev);
4692         gfx_v10_0_rlc_fini(adev);
4693         gfx_v10_0_mec_fini(adev);
4694
4695         if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO)
4696                 gfx_v10_0_rlc_backdoor_autoload_buffer_fini(adev);
4697
4698         gfx_v10_0_free_microcode(adev);
4699
4700         return 0;
4701 }
4702
4703 static void gfx_v10_0_select_se_sh(struct amdgpu_device *adev, u32 se_num,
4704                                    u32 sh_num, u32 instance, int xcc_id)
4705 {
4706         u32 data;
4707
4708         if (instance == 0xffffffff)
4709                 data = REG_SET_FIELD(0, GRBM_GFX_INDEX,
4710                                      INSTANCE_BROADCAST_WRITES, 1);
4711         else
4712                 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_INDEX,
4713                                      instance);
4714
4715         if (se_num == 0xffffffff)
4716                 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_BROADCAST_WRITES,
4717                                      1);
4718         else
4719                 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num);
4720
4721         if (sh_num == 0xffffffff)
4722                 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SA_BROADCAST_WRITES,
4723                                      1);
4724         else
4725                 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SA_INDEX, sh_num);
4726
4727         WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, data);
4728 }
4729
4730 static u32 gfx_v10_0_get_rb_active_bitmap(struct amdgpu_device *adev)
4731 {
4732         u32 data, mask;
4733
4734         data = RREG32_SOC15(GC, 0, mmCC_RB_BACKEND_DISABLE);
4735         data |= RREG32_SOC15(GC, 0, mmGC_USER_RB_BACKEND_DISABLE);
4736
4737         data &= CC_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK;
4738         data >>= GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT;
4739
4740         mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_backends_per_se /
4741                                          adev->gfx.config.max_sh_per_se);
4742
4743         return (~data) & mask;
4744 }
4745
4746 static void gfx_v10_0_setup_rb(struct amdgpu_device *adev)
4747 {
4748         int i, j;
4749         u32 data;
4750         u32 active_rbs = 0;
4751         u32 bitmap;
4752         u32 rb_bitmap_width_per_sh = adev->gfx.config.max_backends_per_se /
4753                                         adev->gfx.config.max_sh_per_se;
4754
4755         mutex_lock(&adev->grbm_idx_mutex);
4756         for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
4757                 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
4758                         bitmap = i * adev->gfx.config.max_sh_per_se + j;
4759                         if (((amdgpu_ip_version(adev, GC_HWIP, 0) ==
4760                               IP_VERSION(10, 3, 0)) ||
4761                              (amdgpu_ip_version(adev, GC_HWIP, 0) ==
4762                               IP_VERSION(10, 3, 3)) ||
4763                              (amdgpu_ip_version(adev, GC_HWIP, 0) ==
4764                               IP_VERSION(10, 3, 6))) &&
4765                             ((gfx_v10_3_get_disabled_sa(adev) >> bitmap) & 1))
4766                                 continue;
4767                         gfx_v10_0_select_se_sh(adev, i, j, 0xffffffff, 0);
4768                         data = gfx_v10_0_get_rb_active_bitmap(adev);
4769                         active_rbs |= data << ((i * adev->gfx.config.max_sh_per_se + j) *
4770                                                rb_bitmap_width_per_sh);
4771                 }
4772         }
4773         gfx_v10_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0);
4774         mutex_unlock(&adev->grbm_idx_mutex);
4775
4776         adev->gfx.config.backend_enable_mask = active_rbs;
4777         adev->gfx.config.num_rbs = hweight32(active_rbs);
4778 }
4779
4780 static u32 gfx_v10_0_init_pa_sc_tile_steering_override(struct amdgpu_device *adev)
4781 {
4782         uint32_t num_sc;
4783         uint32_t enabled_rb_per_sh;
4784         uint32_t active_rb_bitmap;
4785         uint32_t num_rb_per_sc;
4786         uint32_t num_packer_per_sc;
4787         uint32_t pa_sc_tile_steering_override;
4788
4789         /* for ASICs that integrates GFX v10.3
4790          * pa_sc_tile_steering_override should be set to 0
4791          */
4792         if (amdgpu_ip_version(adev, GC_HWIP, 0) >= IP_VERSION(10, 3, 0))
4793                 return 0;
4794
4795         /* init num_sc */
4796         num_sc = adev->gfx.config.max_shader_engines * adev->gfx.config.max_sh_per_se *
4797                         adev->gfx.config.num_sc_per_sh;
4798         /* init num_rb_per_sc */
4799         active_rb_bitmap = gfx_v10_0_get_rb_active_bitmap(adev);
4800         enabled_rb_per_sh = hweight32(active_rb_bitmap);
4801         num_rb_per_sc = enabled_rb_per_sh / adev->gfx.config.num_sc_per_sh;
4802         /* init num_packer_per_sc */
4803         num_packer_per_sc = adev->gfx.config.num_packer_per_sc;
4804
4805         pa_sc_tile_steering_override = 0;
4806         pa_sc_tile_steering_override |=
4807                 (order_base_2(num_sc) << PA_SC_TILE_STEERING_OVERRIDE__NUM_SC__SHIFT) &
4808                 PA_SC_TILE_STEERING_OVERRIDE__NUM_SC_MASK;
4809         pa_sc_tile_steering_override |=
4810                 (order_base_2(num_rb_per_sc) << PA_SC_TILE_STEERING_OVERRIDE__NUM_RB_PER_SC__SHIFT) &
4811                 PA_SC_TILE_STEERING_OVERRIDE__NUM_RB_PER_SC_MASK;
4812         pa_sc_tile_steering_override |=
4813                 (order_base_2(num_packer_per_sc) << PA_SC_TILE_STEERING_OVERRIDE__NUM_PACKER_PER_SC__SHIFT) &
4814                 PA_SC_TILE_STEERING_OVERRIDE__NUM_PACKER_PER_SC_MASK;
4815
4816         return pa_sc_tile_steering_override;
4817 }
4818
4819 #define DEFAULT_SH_MEM_BASES    (0x6000)
4820
4821 static void gfx_v10_0_debug_trap_config_init(struct amdgpu_device *adev,
4822                                 uint32_t first_vmid,
4823                                 uint32_t last_vmid)
4824 {
4825         uint32_t data;
4826         uint32_t trap_config_vmid_mask = 0;
4827         int i;
4828
4829         /* Calculate trap config vmid mask */
4830         for (i = first_vmid; i < last_vmid; i++)
4831                 trap_config_vmid_mask |= (1 << i);
4832
4833         data = REG_SET_FIELD(0, SPI_GDBG_TRAP_CONFIG,
4834                         VMID_SEL, trap_config_vmid_mask);
4835         data = REG_SET_FIELD(data, SPI_GDBG_TRAP_CONFIG,
4836                         TRAP_EN, 1);
4837         WREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_GDBG_TRAP_CONFIG), data);
4838         WREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_GDBG_TRAP_MASK), 0);
4839
4840         WREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_GDBG_TRAP_DATA0), 0);
4841         WREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_GDBG_TRAP_DATA1), 0);
4842 }
4843
4844 static void gfx_v10_0_init_compute_vmid(struct amdgpu_device *adev)
4845 {
4846         int i;
4847         uint32_t sh_mem_bases;
4848
4849         /*
4850          * Configure apertures:
4851          * LDS:         0x60000000'00000000 - 0x60000001'00000000 (4GB)
4852          * Scratch:     0x60000001'00000000 - 0x60000002'00000000 (4GB)
4853          * GPUVM:       0x60010000'00000000 - 0x60020000'00000000 (1TB)
4854          */
4855         sh_mem_bases = DEFAULT_SH_MEM_BASES | (DEFAULT_SH_MEM_BASES << 16);
4856
4857         mutex_lock(&adev->srbm_mutex);
4858         for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) {
4859                 nv_grbm_select(adev, 0, 0, 0, i);
4860                 /* CP and shaders */
4861                 WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, DEFAULT_SH_MEM_CONFIG);
4862                 WREG32_SOC15(GC, 0, mmSH_MEM_BASES, sh_mem_bases);
4863         }
4864         nv_grbm_select(adev, 0, 0, 0, 0);
4865         mutex_unlock(&adev->srbm_mutex);
4866
4867         /*
4868          * Initialize all compute VMIDs to have no GDS, GWS, or OA
4869          * access. These should be enabled by FW for target VMIDs.
4870          */
4871         for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) {
4872                 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_BASE, 2 * i, 0);
4873                 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_SIZE, 2 * i, 0);
4874                 WREG32_SOC15_OFFSET(GC, 0, mmGDS_GWS_VMID0, i, 0);
4875                 WREG32_SOC15_OFFSET(GC, 0, mmGDS_OA_VMID0, i, 0);
4876         }
4877
4878         gfx_v10_0_debug_trap_config_init(adev, adev->vm_manager.first_kfd_vmid,
4879                                         AMDGPU_NUM_VMID);
4880 }
4881
4882 static void gfx_v10_0_init_gds_vmid(struct amdgpu_device *adev)
4883 {
4884         int vmid;
4885
4886         /*
4887          * Initialize all compute and user-gfx VMIDs to have no GDS, GWS, or OA
4888          * access. Compute VMIDs should be enabled by FW for target VMIDs,
4889          * the driver can enable them for graphics. VMID0 should maintain
4890          * access so that HWS firmware can save/restore entries.
4891          */
4892         for (vmid = 1; vmid < AMDGPU_NUM_VMID; vmid++) {
4893                 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_BASE, 2 * vmid, 0);
4894                 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_SIZE, 2 * vmid, 0);
4895                 WREG32_SOC15_OFFSET(GC, 0, mmGDS_GWS_VMID0, vmid, 0);
4896                 WREG32_SOC15_OFFSET(GC, 0, mmGDS_OA_VMID0, vmid, 0);
4897         }
4898 }
4899
4900
4901 static void gfx_v10_0_tcp_harvest(struct amdgpu_device *adev)
4902 {
4903         int i, j, k;
4904         int max_wgp_per_sh = adev->gfx.config.max_cu_per_sh >> 1;
4905         u32 tmp, wgp_active_bitmap = 0;
4906         u32 gcrd_targets_disable_tcp = 0;
4907         u32 utcl_invreq_disable = 0;
4908         /*
4909          * GCRD_TARGETS_DISABLE field contains
4910          * for Navi10/Navi12: GL1C=[18:15], SQC=[14:10], TCP=[9:0]
4911          * for Navi14: GL1C=[21:18], SQC=[17:12], TCP=[11:0]
4912          */
4913         u32 gcrd_targets_disable_mask = amdgpu_gfx_create_bitmask(
4914                 2 * max_wgp_per_sh + /* TCP */
4915                 max_wgp_per_sh + /* SQC */
4916                 4); /* GL1C */
4917         /*
4918          * UTCL1_UTCL0_INVREQ_DISABLE field contains
4919          * for Navi10Navi12: SQG=[24], RMI=[23:20], SQC=[19:10], TCP=[9:0]
4920          * for Navi14: SQG=[28], RMI=[27:24], SQC=[23:12], TCP=[11:0]
4921          */
4922         u32 utcl_invreq_disable_mask = amdgpu_gfx_create_bitmask(
4923                 2 * max_wgp_per_sh + /* TCP */
4924                 2 * max_wgp_per_sh + /* SQC */
4925                 4 + /* RMI */
4926                 1); /* SQG */
4927
4928         mutex_lock(&adev->grbm_idx_mutex);
4929         for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
4930                 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
4931                         gfx_v10_0_select_se_sh(adev, i, j, 0xffffffff, 0);
4932                         wgp_active_bitmap = gfx_v10_0_get_wgp_active_bitmap_per_sh(adev);
4933                         /*
4934                          * Set corresponding TCP bits for the inactive WGPs in
4935                          * GCRD_SA_TARGETS_DISABLE
4936                          */
4937                         gcrd_targets_disable_tcp = 0;
4938                         /* Set TCP & SQC bits in UTCL1_UTCL0_INVREQ_DISABLE */
4939                         utcl_invreq_disable = 0;
4940
4941                         for (k = 0; k < max_wgp_per_sh; k++) {
4942                                 if (!(wgp_active_bitmap & (1 << k))) {
4943                                         gcrd_targets_disable_tcp |= 3 << (2 * k);
4944                                         gcrd_targets_disable_tcp |= 1 << (k + (max_wgp_per_sh * 2));
4945                                         utcl_invreq_disable |= (3 << (2 * k)) |
4946                                                 (3 << (2 * (max_wgp_per_sh + k)));
4947                                 }
4948                         }
4949
4950                         tmp = RREG32_SOC15(GC, 0, mmUTCL1_UTCL0_INVREQ_DISABLE);
4951                         /* only override TCP & SQC bits */
4952                         tmp &= (0xffffffffU << (4 * max_wgp_per_sh));
4953                         tmp |= (utcl_invreq_disable & utcl_invreq_disable_mask);
4954                         WREG32_SOC15(GC, 0, mmUTCL1_UTCL0_INVREQ_DISABLE, tmp);
4955
4956                         tmp = RREG32_SOC15(GC, 0, mmGCRD_SA_TARGETS_DISABLE);
4957                         /* only override TCP & SQC bits */
4958                         tmp &= (0xffffffffU << (3 * max_wgp_per_sh));
4959                         tmp |= (gcrd_targets_disable_tcp & gcrd_targets_disable_mask);
4960                         WREG32_SOC15(GC, 0, mmGCRD_SA_TARGETS_DISABLE, tmp);
4961                 }
4962         }
4963
4964         gfx_v10_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0);
4965         mutex_unlock(&adev->grbm_idx_mutex);
4966 }
4967
4968 static void gfx_v10_0_get_tcc_info(struct amdgpu_device *adev)
4969 {
4970         /* TCCs are global (not instanced). */
4971         uint32_t tcc_disable;
4972
4973         if (amdgpu_ip_version(adev, GC_HWIP, 0) >= IP_VERSION(10, 3, 0)) {
4974                 tcc_disable = RREG32_SOC15(GC, 0, mmCGTS_TCC_DISABLE_gc_10_3) |
4975                               RREG32_SOC15(GC, 0, mmCGTS_USER_TCC_DISABLE_gc_10_3);
4976         } else {
4977                 tcc_disable = RREG32_SOC15(GC, 0, mmCGTS_TCC_DISABLE) |
4978                               RREG32_SOC15(GC, 0, mmCGTS_USER_TCC_DISABLE);
4979         }
4980
4981         adev->gfx.config.tcc_disabled_mask =
4982                 REG_GET_FIELD(tcc_disable, CGTS_TCC_DISABLE, TCC_DISABLE) |
4983                 (REG_GET_FIELD(tcc_disable, CGTS_TCC_DISABLE, HI_TCC_DISABLE) << 16);
4984 }
4985
4986 static void gfx_v10_0_constants_init(struct amdgpu_device *adev)
4987 {
4988         u32 tmp;
4989         int i;
4990
4991         WREG32_FIELD15(GC, 0, GRBM_CNTL, READ_TIMEOUT, 0xff);
4992
4993         gfx_v10_0_setup_rb(adev);
4994         gfx_v10_0_get_cu_info(adev, &adev->gfx.cu_info);
4995         gfx_v10_0_get_tcc_info(adev);
4996         adev->gfx.config.pa_sc_tile_steering_override =
4997                 gfx_v10_0_init_pa_sc_tile_steering_override(adev);
4998
4999         /* XXX SH_MEM regs */
5000         /* where to put LDS, scratch, GPUVM in FSA64 space */
5001         mutex_lock(&adev->srbm_mutex);
5002         for (i = 0; i < adev->vm_manager.id_mgr[AMDGPU_GFXHUB(0)].num_ids; i++) {
5003                 nv_grbm_select(adev, 0, 0, 0, i);
5004                 /* CP and shaders */
5005                 WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, DEFAULT_SH_MEM_CONFIG);
5006                 if (i != 0) {
5007                         tmp = REG_SET_FIELD(0, SH_MEM_BASES, PRIVATE_BASE,
5008                                 (adev->gmc.private_aperture_start >> 48));
5009                         tmp = REG_SET_FIELD(tmp, SH_MEM_BASES, SHARED_BASE,
5010                                 (adev->gmc.shared_aperture_start >> 48));
5011                         WREG32_SOC15(GC, 0, mmSH_MEM_BASES, tmp);
5012                 }
5013         }
5014         nv_grbm_select(adev, 0, 0, 0, 0);
5015
5016         mutex_unlock(&adev->srbm_mutex);
5017
5018         gfx_v10_0_init_compute_vmid(adev);
5019         gfx_v10_0_init_gds_vmid(adev);
5020
5021 }
5022
5023 static void gfx_v10_0_enable_gui_idle_interrupt(struct amdgpu_device *adev,
5024                                                bool enable)
5025 {
5026         u32 tmp;
5027
5028         if (amdgpu_sriov_vf(adev))
5029                 return;
5030
5031         tmp = RREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0);
5032
5033         tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE,
5034                             enable ? 1 : 0);
5035         tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE,
5036                             enable ? 1 : 0);
5037         tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE,
5038                             enable ? 1 : 0);
5039         tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, GFX_IDLE_INT_ENABLE,
5040                             enable ? 1 : 0);
5041
5042         WREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0, tmp);
5043 }
5044
5045 static int gfx_v10_0_init_csb(struct amdgpu_device *adev)
5046 {
5047         adev->gfx.rlc.funcs->get_csb_buffer(adev, adev->gfx.rlc.cs_ptr);
5048
5049         /* csib */
5050         if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(10, 1, 2)) {
5051                 WREG32_SOC15_RLC(GC, 0, mmRLC_CSIB_ADDR_HI,
5052                                 adev->gfx.rlc.clear_state_gpu_addr >> 32);
5053                 WREG32_SOC15_RLC(GC, 0, mmRLC_CSIB_ADDR_LO,
5054                                 adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc);
5055                 WREG32_SOC15_RLC(GC, 0, mmRLC_CSIB_LENGTH, adev->gfx.rlc.clear_state_size);
5056         } else {
5057                 WREG32_SOC15(GC, 0, mmRLC_CSIB_ADDR_HI,
5058                                 adev->gfx.rlc.clear_state_gpu_addr >> 32);
5059                 WREG32_SOC15(GC, 0, mmRLC_CSIB_ADDR_LO,
5060                                 adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc);
5061                 WREG32_SOC15(GC, 0, mmRLC_CSIB_LENGTH, adev->gfx.rlc.clear_state_size);
5062         }
5063         return 0;
5064 }
5065
5066 static void gfx_v10_0_rlc_stop(struct amdgpu_device *adev)
5067 {
5068         u32 tmp = RREG32_SOC15(GC, 0, mmRLC_CNTL);
5069
5070         tmp = REG_SET_FIELD(tmp, RLC_CNTL, RLC_ENABLE_F32, 0);
5071         WREG32_SOC15(GC, 0, mmRLC_CNTL, tmp);
5072 }
5073
5074 static void gfx_v10_0_rlc_reset(struct amdgpu_device *adev)
5075 {
5076         WREG32_FIELD15(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 1);
5077         udelay(50);
5078         WREG32_FIELD15(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 0);
5079         udelay(50);
5080 }
5081
5082 static void gfx_v10_0_rlc_smu_handshake_cntl(struct amdgpu_device *adev,
5083                                              bool enable)
5084 {
5085         uint32_t rlc_pg_cntl;
5086
5087         rlc_pg_cntl = RREG32_SOC15(GC, 0, mmRLC_PG_CNTL);
5088
5089         if (!enable) {
5090                 /* RLC_PG_CNTL[23] = 0 (default)
5091                  * RLC will wait for handshake acks with SMU
5092                  * GFXOFF will be enabled
5093                  * RLC_PG_CNTL[23] = 1
5094                  * RLC will not issue any message to SMU
5095                  * hence no handshake between SMU & RLC
5096                  * GFXOFF will be disabled
5097                  */
5098                 rlc_pg_cntl |= 0x800000;
5099         } else
5100                 rlc_pg_cntl &= ~0x800000;
5101         WREG32_SOC15(GC, 0, mmRLC_PG_CNTL, rlc_pg_cntl);
5102 }
5103
5104 static void gfx_v10_0_rlc_start(struct amdgpu_device *adev)
5105 {
5106         /*
5107          * TODO: enable rlc & smu handshake until smu
5108          * and gfxoff feature works as expected
5109          */
5110         if (!(amdgpu_pp_feature_mask & PP_GFXOFF_MASK))
5111                 gfx_v10_0_rlc_smu_handshake_cntl(adev, false);
5112
5113         WREG32_FIELD15(GC, 0, RLC_CNTL, RLC_ENABLE_F32, 1);
5114         udelay(50);
5115 }
5116
5117 static void gfx_v10_0_rlc_enable_srm(struct amdgpu_device *adev)
5118 {
5119         uint32_t tmp;
5120
5121         /* enable Save Restore Machine */
5122         tmp = RREG32_SOC15(GC, 0, mmRLC_SRM_CNTL);
5123         tmp |= RLC_SRM_CNTL__AUTO_INCR_ADDR_MASK;
5124         tmp |= RLC_SRM_CNTL__SRM_ENABLE_MASK;
5125         WREG32_SOC15(GC, 0, mmRLC_SRM_CNTL, tmp);
5126 }
5127
5128 static int gfx_v10_0_rlc_load_microcode(struct amdgpu_device *adev)
5129 {
5130         const struct rlc_firmware_header_v2_0 *hdr;
5131         const __le32 *fw_data;
5132         unsigned int i, fw_size;
5133
5134         if (!adev->gfx.rlc_fw)
5135                 return -EINVAL;
5136
5137         hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data;
5138         amdgpu_ucode_print_rlc_hdr(&hdr->header);
5139
5140         fw_data = (const __le32 *)(adev->gfx.rlc_fw->data +
5141                            le32_to_cpu(hdr->header.ucode_array_offset_bytes));
5142         fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
5143
5144         WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_ADDR,
5145                      RLCG_UCODE_LOADING_START_ADDRESS);
5146
5147         for (i = 0; i < fw_size; i++)
5148                 WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_DATA,
5149                              le32_to_cpup(fw_data++));
5150
5151         WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_ADDR, adev->gfx.rlc_fw_version);
5152
5153         return 0;
5154 }
5155
5156 static int gfx_v10_0_rlc_resume(struct amdgpu_device *adev)
5157 {
5158         int r;
5159
5160         if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP &&
5161                 adev->psp.autoload_supported) {
5162
5163                 r = gfx_v10_0_wait_for_rlc_autoload_complete(adev);
5164                 if (r)
5165                         return r;
5166
5167                 gfx_v10_0_init_csb(adev);
5168
5169                 gfx_v10_0_update_spm_vmid_internal(adev, 0xf);
5170
5171                 if (!amdgpu_sriov_vf(adev)) /* enable RLC SRM */
5172                         gfx_v10_0_rlc_enable_srm(adev);
5173         } else {
5174                 if (amdgpu_sriov_vf(adev)) {
5175                         gfx_v10_0_init_csb(adev);
5176                         return 0;
5177                 }
5178
5179                 adev->gfx.rlc.funcs->stop(adev);
5180
5181                 /* disable CG */
5182                 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, 0);
5183
5184                 /* disable PG */
5185                 WREG32_SOC15(GC, 0, mmRLC_PG_CNTL, 0);
5186
5187                 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
5188                         /* legacy rlc firmware loading */
5189                         r = gfx_v10_0_rlc_load_microcode(adev);
5190                         if (r)
5191                                 return r;
5192                 } else if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) {
5193                         /* rlc backdoor autoload firmware */
5194                         r = gfx_v10_0_rlc_backdoor_autoload_enable(adev);
5195                         if (r)
5196                                 return r;
5197                 }
5198
5199                 gfx_v10_0_init_csb(adev);
5200
5201                 gfx_v10_0_update_spm_vmid_internal(adev, 0xf);
5202
5203                 adev->gfx.rlc.funcs->start(adev);
5204
5205                 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) {
5206                         r = gfx_v10_0_wait_for_rlc_autoload_complete(adev);
5207                         if (r)
5208                                 return r;
5209                 }
5210         }
5211
5212         return 0;
5213 }
5214
5215 static struct {
5216         FIRMWARE_ID     id;
5217         unsigned int    offset;
5218         unsigned int    size;
5219 } rlc_autoload_info[FIRMWARE_ID_MAX];
5220
5221 static int gfx_v10_0_parse_rlc_toc(struct amdgpu_device *adev)
5222 {
5223         int ret;
5224         RLC_TABLE_OF_CONTENT *rlc_toc;
5225
5226         ret = amdgpu_bo_create_reserved(adev, adev->psp.toc.size_bytes, PAGE_SIZE,
5227                                         AMDGPU_GEM_DOMAIN_GTT,
5228                                         &adev->gfx.rlc.rlc_toc_bo,
5229                                         &adev->gfx.rlc.rlc_toc_gpu_addr,
5230                                         (void **)&adev->gfx.rlc.rlc_toc_buf);
5231         if (ret) {
5232                 dev_err(adev->dev, "(%d) failed to create rlc toc bo\n", ret);
5233                 return ret;
5234         }
5235
5236         /* Copy toc from psp sos fw to rlc toc buffer */
5237         memcpy(adev->gfx.rlc.rlc_toc_buf, adev->psp.toc.start_addr, adev->psp.toc.size_bytes);
5238
5239         rlc_toc = (RLC_TABLE_OF_CONTENT *)adev->gfx.rlc.rlc_toc_buf;
5240         while (rlc_toc && (rlc_toc->id > FIRMWARE_ID_INVALID) &&
5241                 (rlc_toc->id < FIRMWARE_ID_MAX)) {
5242                 if ((rlc_toc->id >= FIRMWARE_ID_CP_CE) &&
5243                     (rlc_toc->id <= FIRMWARE_ID_CP_MES)) {
5244                         /* Offset needs 4KB alignment */
5245                         rlc_toc->offset = ALIGN(rlc_toc->offset * 4, PAGE_SIZE);
5246                 }
5247
5248                 rlc_autoload_info[rlc_toc->id].id = rlc_toc->id;
5249                 rlc_autoload_info[rlc_toc->id].offset = rlc_toc->offset * 4;
5250                 rlc_autoload_info[rlc_toc->id].size = rlc_toc->size * 4;
5251
5252                 rlc_toc++;
5253         }
5254
5255         return 0;
5256 }
5257
5258 static uint32_t gfx_v10_0_calc_toc_total_size(struct amdgpu_device *adev)
5259 {
5260         uint32_t total_size = 0;
5261         FIRMWARE_ID id;
5262         int ret;
5263
5264         ret = gfx_v10_0_parse_rlc_toc(adev);
5265         if (ret) {
5266                 dev_err(adev->dev, "failed to parse rlc toc\n");
5267                 return 0;
5268         }
5269
5270         for (id = FIRMWARE_ID_RLC_G_UCODE; id < FIRMWARE_ID_MAX; id++)
5271                 total_size += rlc_autoload_info[id].size;
5272
5273         /* In case the offset in rlc toc ucode is aligned */
5274         if (total_size < rlc_autoload_info[FIRMWARE_ID_MAX-1].offset)
5275                 total_size = rlc_autoload_info[FIRMWARE_ID_MAX-1].offset +
5276                                 rlc_autoload_info[FIRMWARE_ID_MAX-1].size;
5277
5278         return total_size;
5279 }
5280
5281 static int gfx_v10_0_rlc_backdoor_autoload_buffer_init(struct amdgpu_device *adev)
5282 {
5283         int r;
5284         uint32_t total_size;
5285
5286         total_size = gfx_v10_0_calc_toc_total_size(adev);
5287
5288         r = amdgpu_bo_create_reserved(adev, total_size, PAGE_SIZE,
5289                                       AMDGPU_GEM_DOMAIN_GTT,
5290                                       &adev->gfx.rlc.rlc_autoload_bo,
5291                                       &adev->gfx.rlc.rlc_autoload_gpu_addr,
5292                                       (void **)&adev->gfx.rlc.rlc_autoload_ptr);
5293         if (r) {
5294                 dev_err(adev->dev, "(%d) failed to create fw autoload bo\n", r);
5295                 return r;
5296         }
5297
5298         return 0;
5299 }
5300
5301 static void gfx_v10_0_rlc_backdoor_autoload_buffer_fini(struct amdgpu_device *adev)
5302 {
5303         amdgpu_bo_free_kernel(&adev->gfx.rlc.rlc_toc_bo,
5304                               &adev->gfx.rlc.rlc_toc_gpu_addr,
5305                               (void **)&adev->gfx.rlc.rlc_toc_buf);
5306         amdgpu_bo_free_kernel(&adev->gfx.rlc.rlc_autoload_bo,
5307                               &adev->gfx.rlc.rlc_autoload_gpu_addr,
5308                               (void **)&adev->gfx.rlc.rlc_autoload_ptr);
5309 }
5310
5311 static void gfx_v10_0_rlc_backdoor_autoload_copy_ucode(struct amdgpu_device *adev,
5312                                                        FIRMWARE_ID id,
5313                                                        const void *fw_data,
5314                                                        uint32_t fw_size)
5315 {
5316         uint32_t toc_offset;
5317         uint32_t toc_fw_size;
5318         char *ptr = adev->gfx.rlc.rlc_autoload_ptr;
5319
5320         if (id <= FIRMWARE_ID_INVALID || id >= FIRMWARE_ID_MAX)
5321                 return;
5322
5323         toc_offset = rlc_autoload_info[id].offset;
5324         toc_fw_size = rlc_autoload_info[id].size;
5325
5326         if (fw_size == 0)
5327                 fw_size = toc_fw_size;
5328
5329         if (fw_size > toc_fw_size)
5330                 fw_size = toc_fw_size;
5331
5332         memcpy(ptr + toc_offset, fw_data, fw_size);
5333
5334         if (fw_size < toc_fw_size)
5335                 memset(ptr + toc_offset + fw_size, 0, toc_fw_size - fw_size);
5336 }
5337
5338 static void gfx_v10_0_rlc_backdoor_autoload_copy_toc_ucode(struct amdgpu_device *adev)
5339 {
5340         void *data;
5341         uint32_t size;
5342
5343         data = adev->gfx.rlc.rlc_toc_buf;
5344         size = rlc_autoload_info[FIRMWARE_ID_RLC_TOC].size;
5345
5346         gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5347                                                    FIRMWARE_ID_RLC_TOC,
5348                                                    data, size);
5349 }
5350
5351 static void gfx_v10_0_rlc_backdoor_autoload_copy_gfx_ucode(struct amdgpu_device *adev)
5352 {
5353         const __le32 *fw_data;
5354         uint32_t fw_size;
5355         const struct gfx_firmware_header_v1_0 *cp_hdr;
5356         const struct rlc_firmware_header_v2_0 *rlc_hdr;
5357
5358         /* pfp ucode */
5359         cp_hdr = (const struct gfx_firmware_header_v1_0 *)
5360                 adev->gfx.pfp_fw->data;
5361         fw_data = (const __le32 *)(adev->gfx.pfp_fw->data +
5362                 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes));
5363         fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes);
5364         gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5365                                                    FIRMWARE_ID_CP_PFP,
5366                                                    fw_data, fw_size);
5367
5368         /* ce ucode */
5369         cp_hdr = (const struct gfx_firmware_header_v1_0 *)
5370                 adev->gfx.ce_fw->data;
5371         fw_data = (const __le32 *)(adev->gfx.ce_fw->data +
5372                 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes));
5373         fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes);
5374         gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5375                                                    FIRMWARE_ID_CP_CE,
5376                                                    fw_data, fw_size);
5377
5378         /* me ucode */
5379         cp_hdr = (const struct gfx_firmware_header_v1_0 *)
5380                 adev->gfx.me_fw->data;
5381         fw_data = (const __le32 *)(adev->gfx.me_fw->data +
5382                 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes));
5383         fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes);
5384         gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5385                                                    FIRMWARE_ID_CP_ME,
5386                                                    fw_data, fw_size);
5387
5388         /* rlc ucode */
5389         rlc_hdr = (const struct rlc_firmware_header_v2_0 *)
5390                 adev->gfx.rlc_fw->data;
5391         fw_data = (const __le32 *)(adev->gfx.rlc_fw->data +
5392                 le32_to_cpu(rlc_hdr->header.ucode_array_offset_bytes));
5393         fw_size = le32_to_cpu(rlc_hdr->header.ucode_size_bytes);
5394         gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5395                                                    FIRMWARE_ID_RLC_G_UCODE,
5396                                                    fw_data, fw_size);
5397
5398         /* mec1 ucode */
5399         cp_hdr = (const struct gfx_firmware_header_v1_0 *)
5400                 adev->gfx.mec_fw->data;
5401         fw_data = (const __le32 *) (adev->gfx.mec_fw->data +
5402                 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes));
5403         fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes) -
5404                 cp_hdr->jt_size * 4;
5405         gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5406                                                    FIRMWARE_ID_CP_MEC,
5407                                                    fw_data, fw_size);
5408         /* mec2 ucode is not necessary if mec2 ucode is same as mec1 */
5409 }
5410
5411 /* Temporarily put sdma part here */
5412 static void gfx_v10_0_rlc_backdoor_autoload_copy_sdma_ucode(struct amdgpu_device *adev)
5413 {
5414         const __le32 *fw_data;
5415         uint32_t fw_size;
5416         const struct sdma_firmware_header_v1_0 *sdma_hdr;
5417         int i;
5418
5419         for (i = 0; i < adev->sdma.num_instances; i++) {
5420                 sdma_hdr = (const struct sdma_firmware_header_v1_0 *)
5421                         adev->sdma.instance[i].fw->data;
5422                 fw_data = (const __le32 *) (adev->sdma.instance[i].fw->data +
5423                         le32_to_cpu(sdma_hdr->header.ucode_array_offset_bytes));
5424                 fw_size = le32_to_cpu(sdma_hdr->header.ucode_size_bytes);
5425
5426                 if (i == 0) {
5427                         gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5428                                 FIRMWARE_ID_SDMA0_UCODE, fw_data, fw_size);
5429                         gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5430                                 FIRMWARE_ID_SDMA0_JT,
5431                                 (uint32_t *)fw_data +
5432                                 sdma_hdr->jt_offset,
5433                                 sdma_hdr->jt_size * 4);
5434                 } else if (i == 1) {
5435                         gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5436                                 FIRMWARE_ID_SDMA1_UCODE, fw_data, fw_size);
5437                         gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5438                                 FIRMWARE_ID_SDMA1_JT,
5439                                 (uint32_t *)fw_data +
5440                                 sdma_hdr->jt_offset,
5441                                 sdma_hdr->jt_size * 4);
5442                 }
5443         }
5444 }
5445
5446 static int gfx_v10_0_rlc_backdoor_autoload_enable(struct amdgpu_device *adev)
5447 {
5448         uint32_t rlc_g_offset, rlc_g_size, tmp;
5449         uint64_t gpu_addr;
5450
5451         gfx_v10_0_rlc_backdoor_autoload_copy_toc_ucode(adev);
5452         gfx_v10_0_rlc_backdoor_autoload_copy_sdma_ucode(adev);
5453         gfx_v10_0_rlc_backdoor_autoload_copy_gfx_ucode(adev);
5454
5455         rlc_g_offset = rlc_autoload_info[FIRMWARE_ID_RLC_G_UCODE].offset;
5456         rlc_g_size = rlc_autoload_info[FIRMWARE_ID_RLC_G_UCODE].size;
5457         gpu_addr = adev->gfx.rlc.rlc_autoload_gpu_addr + rlc_g_offset;
5458
5459         WREG32_SOC15(GC, 0, mmRLC_HYP_BOOTLOAD_ADDR_HI, upper_32_bits(gpu_addr));
5460         WREG32_SOC15(GC, 0, mmRLC_HYP_BOOTLOAD_ADDR_LO, lower_32_bits(gpu_addr));
5461         WREG32_SOC15(GC, 0, mmRLC_HYP_BOOTLOAD_SIZE, rlc_g_size);
5462
5463         tmp = RREG32_SOC15(GC, 0, mmRLC_HYP_RESET_VECTOR);
5464         if (!(tmp & (RLC_HYP_RESET_VECTOR__COLD_BOOT_EXIT_MASK |
5465                    RLC_HYP_RESET_VECTOR__VDDGFX_EXIT_MASK))) {
5466                 DRM_ERROR("Neither COLD_BOOT_EXIT nor VDDGFX_EXIT is set\n");
5467                 return -EINVAL;
5468         }
5469
5470         tmp = RREG32_SOC15(GC, 0, mmRLC_CNTL);
5471         if (tmp & RLC_CNTL__RLC_ENABLE_F32_MASK) {
5472                 DRM_ERROR("RLC ROM should halt itself\n");
5473                 return -EINVAL;
5474         }
5475
5476         return 0;
5477 }
5478
5479 static int gfx_v10_0_rlc_backdoor_autoload_config_me_cache(struct amdgpu_device *adev)
5480 {
5481         uint32_t usec_timeout = 50000;  /* wait for 50ms */
5482         uint32_t tmp;
5483         int i;
5484         uint64_t addr;
5485
5486         /* Trigger an invalidation of the L1 instruction caches */
5487         tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL);
5488         tmp = REG_SET_FIELD(tmp, CP_ME_IC_OP_CNTL, INVALIDATE_CACHE, 1);
5489         WREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL, tmp);
5490
5491         /* Wait for invalidation complete */
5492         for (i = 0; i < usec_timeout; i++) {
5493                 tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL);
5494                 if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL,
5495                         INVALIDATE_CACHE_COMPLETE))
5496                         break;
5497                 udelay(1);
5498         }
5499
5500         if (i >= usec_timeout) {
5501                 dev_err(adev->dev, "failed to invalidate instruction cache\n");
5502                 return -EINVAL;
5503         }
5504
5505         /* Program me ucode address into intruction cache address register */
5506         addr = adev->gfx.rlc.rlc_autoload_gpu_addr +
5507                 rlc_autoload_info[FIRMWARE_ID_CP_ME].offset;
5508         WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_LO,
5509                         lower_32_bits(addr) & 0xFFFFF000);
5510         WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_HI,
5511                         upper_32_bits(addr));
5512
5513         return 0;
5514 }
5515
5516 static int gfx_v10_0_rlc_backdoor_autoload_config_ce_cache(struct amdgpu_device *adev)
5517 {
5518         uint32_t usec_timeout = 50000;  /* wait for 50ms */
5519         uint32_t tmp;
5520         int i;
5521         uint64_t addr;
5522
5523         /* Trigger an invalidation of the L1 instruction caches */
5524         tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL);
5525         tmp = REG_SET_FIELD(tmp, CP_CE_IC_OP_CNTL, INVALIDATE_CACHE, 1);
5526         WREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL, tmp);
5527
5528         /* Wait for invalidation complete */
5529         for (i = 0; i < usec_timeout; i++) {
5530                 tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL);
5531                 if (1 == REG_GET_FIELD(tmp, CP_CE_IC_OP_CNTL,
5532                         INVALIDATE_CACHE_COMPLETE))
5533                         break;
5534                 udelay(1);
5535         }
5536
5537         if (i >= usec_timeout) {
5538                 dev_err(adev->dev, "failed to invalidate instruction cache\n");
5539                 return -EINVAL;
5540         }
5541
5542         /* Program ce ucode address into intruction cache address register */
5543         addr = adev->gfx.rlc.rlc_autoload_gpu_addr +
5544                 rlc_autoload_info[FIRMWARE_ID_CP_CE].offset;
5545         WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_LO,
5546                         lower_32_bits(addr) & 0xFFFFF000);
5547         WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_HI,
5548                         upper_32_bits(addr));
5549
5550         return 0;
5551 }
5552
5553 static int gfx_v10_0_rlc_backdoor_autoload_config_pfp_cache(struct amdgpu_device *adev)
5554 {
5555         uint32_t usec_timeout = 50000;  /* wait for 50ms */
5556         uint32_t tmp;
5557         int i;
5558         uint64_t addr;
5559
5560         /* Trigger an invalidation of the L1 instruction caches */
5561         tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL);
5562         tmp = REG_SET_FIELD(tmp, CP_PFP_IC_OP_CNTL, INVALIDATE_CACHE, 1);
5563         WREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL, tmp);
5564
5565         /* Wait for invalidation complete */
5566         for (i = 0; i < usec_timeout; i++) {
5567                 tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL);
5568                 if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL,
5569                         INVALIDATE_CACHE_COMPLETE))
5570                         break;
5571                 udelay(1);
5572         }
5573
5574         if (i >= usec_timeout) {
5575                 dev_err(adev->dev, "failed to invalidate instruction cache\n");
5576                 return -EINVAL;
5577         }
5578
5579         /* Program pfp ucode address into intruction cache address register */
5580         addr = adev->gfx.rlc.rlc_autoload_gpu_addr +
5581                 rlc_autoload_info[FIRMWARE_ID_CP_PFP].offset;
5582         WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_LO,
5583                         lower_32_bits(addr) & 0xFFFFF000);
5584         WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_HI,
5585                         upper_32_bits(addr));
5586
5587         return 0;
5588 }
5589
5590 static int gfx_v10_0_rlc_backdoor_autoload_config_mec_cache(struct amdgpu_device *adev)
5591 {
5592         uint32_t usec_timeout = 50000;  /* wait for 50ms */
5593         uint32_t tmp;
5594         int i;
5595         uint64_t addr;
5596
5597         /* Trigger an invalidation of the L1 instruction caches */
5598         tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL);
5599         tmp = REG_SET_FIELD(tmp, CP_CPC_IC_OP_CNTL, INVALIDATE_CACHE, 1);
5600         WREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL, tmp);
5601
5602         /* Wait for invalidation complete */
5603         for (i = 0; i < usec_timeout; i++) {
5604                 tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL);
5605                 if (1 == REG_GET_FIELD(tmp, CP_CPC_IC_OP_CNTL,
5606                         INVALIDATE_CACHE_COMPLETE))
5607                         break;
5608                 udelay(1);
5609         }
5610
5611         if (i >= usec_timeout) {
5612                 dev_err(adev->dev, "failed to invalidate instruction cache\n");
5613                 return -EINVAL;
5614         }
5615
5616         /* Program mec1 ucode address into intruction cache address register */
5617         addr = adev->gfx.rlc.rlc_autoload_gpu_addr +
5618                 rlc_autoload_info[FIRMWARE_ID_CP_MEC].offset;
5619         WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_LO,
5620                         lower_32_bits(addr) & 0xFFFFF000);
5621         WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_HI,
5622                         upper_32_bits(addr));
5623
5624         return 0;
5625 }
5626
5627 static int gfx_v10_0_wait_for_rlc_autoload_complete(struct amdgpu_device *adev)
5628 {
5629         uint32_t cp_status;
5630         uint32_t bootload_status;
5631         int i, r;
5632
5633         for (i = 0; i < adev->usec_timeout; i++) {
5634                 cp_status = RREG32_SOC15(GC, 0, mmCP_STAT);
5635                 bootload_status = RREG32_SOC15(GC, 0, mmRLC_RLCS_BOOTLOAD_STATUS);
5636                 if ((cp_status == 0) &&
5637                     (REG_GET_FIELD(bootload_status,
5638                         RLC_RLCS_BOOTLOAD_STATUS, BOOTLOAD_COMPLETE) == 1)) {
5639                         break;
5640                 }
5641                 udelay(1);
5642         }
5643
5644         if (i >= adev->usec_timeout) {
5645                 dev_err(adev->dev, "rlc autoload: gc ucode autoload timeout\n");
5646                 return -ETIMEDOUT;
5647         }
5648
5649         if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) {
5650                 r = gfx_v10_0_rlc_backdoor_autoload_config_me_cache(adev);
5651                 if (r)
5652                         return r;
5653
5654                 r = gfx_v10_0_rlc_backdoor_autoload_config_ce_cache(adev);
5655                 if (r)
5656                         return r;
5657
5658                 r = gfx_v10_0_rlc_backdoor_autoload_config_pfp_cache(adev);
5659                 if (r)
5660                         return r;
5661
5662                 r = gfx_v10_0_rlc_backdoor_autoload_config_mec_cache(adev);
5663                 if (r)
5664                         return r;
5665         }
5666
5667         return 0;
5668 }
5669
5670 static int gfx_v10_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable)
5671 {
5672         int i;
5673         u32 tmp = RREG32_SOC15(GC, 0, mmCP_ME_CNTL);
5674
5675         tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, enable ? 0 : 1);
5676         tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, enable ? 0 : 1);
5677         tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_HALT, enable ? 0 : 1);
5678
5679         if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(10, 1, 2))
5680                 WREG32_SOC15_RLC(GC, 0, mmCP_ME_CNTL, tmp);
5681         else
5682                 WREG32_SOC15(GC, 0, mmCP_ME_CNTL, tmp);
5683
5684         if (adev->job_hang && !enable)
5685                 return 0;
5686
5687         for (i = 0; i < adev->usec_timeout; i++) {
5688                 if (RREG32_SOC15(GC, 0, mmCP_STAT) == 0)
5689                         break;
5690                 udelay(1);
5691         }
5692
5693         if (i >= adev->usec_timeout)
5694                 DRM_ERROR("failed to %s cp gfx\n", enable ? "unhalt" : "halt");
5695
5696         return 0;
5697 }
5698
5699 static int gfx_v10_0_cp_gfx_load_pfp_microcode(struct amdgpu_device *adev)
5700 {
5701         int r;
5702         const struct gfx_firmware_header_v1_0 *pfp_hdr;
5703         const __le32 *fw_data;
5704         unsigned int i, fw_size;
5705         uint32_t tmp;
5706         uint32_t usec_timeout = 50000;  /* wait for 50ms */
5707
5708         pfp_hdr = (const struct gfx_firmware_header_v1_0 *)
5709                 adev->gfx.pfp_fw->data;
5710
5711         amdgpu_ucode_print_gfx_hdr(&pfp_hdr->header);
5712
5713         fw_data = (const __le32 *)(adev->gfx.pfp_fw->data +
5714                 le32_to_cpu(pfp_hdr->header.ucode_array_offset_bytes));
5715         fw_size = le32_to_cpu(pfp_hdr->header.ucode_size_bytes);
5716
5717         r = amdgpu_bo_create_reserved(adev, pfp_hdr->header.ucode_size_bytes,
5718                                       PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,
5719                                       &adev->gfx.pfp.pfp_fw_obj,
5720                                       &adev->gfx.pfp.pfp_fw_gpu_addr,
5721                                       (void **)&adev->gfx.pfp.pfp_fw_ptr);
5722         if (r) {
5723                 dev_err(adev->dev, "(%d) failed to create pfp fw bo\n", r);
5724                 gfx_v10_0_pfp_fini(adev);
5725                 return r;
5726         }
5727
5728         memcpy(adev->gfx.pfp.pfp_fw_ptr, fw_data, fw_size);
5729
5730         amdgpu_bo_kunmap(adev->gfx.pfp.pfp_fw_obj);
5731         amdgpu_bo_unreserve(adev->gfx.pfp.pfp_fw_obj);
5732
5733         /* Trigger an invalidation of the L1 instruction caches */
5734         tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL);
5735         tmp = REG_SET_FIELD(tmp, CP_PFP_IC_OP_CNTL, INVALIDATE_CACHE, 1);
5736         WREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL, tmp);
5737
5738         /* Wait for invalidation complete */
5739         for (i = 0; i < usec_timeout; i++) {
5740                 tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL);
5741                 if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL,
5742                         INVALIDATE_CACHE_COMPLETE))
5743                         break;
5744                 udelay(1);
5745         }
5746
5747         if (i >= usec_timeout) {
5748                 dev_err(adev->dev, "failed to invalidate instruction cache\n");
5749                 return -EINVAL;
5750         }
5751
5752         if (amdgpu_emu_mode == 1)
5753                 adev->hdp.funcs->flush_hdp(adev, NULL);
5754
5755         tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_CNTL);
5756         tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, VMID, 0);
5757         tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, CACHE_POLICY, 0);
5758         tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, EXE_DISABLE, 0);
5759         tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, ADDRESS_CLAMP, 1);
5760         WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_CNTL, tmp);
5761         WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_LO,
5762                 adev->gfx.pfp.pfp_fw_gpu_addr & 0xFFFFF000);
5763         WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_HI,
5764                 upper_32_bits(adev->gfx.pfp.pfp_fw_gpu_addr));
5765
5766         WREG32_SOC15(GC, 0, mmCP_HYP_PFP_UCODE_ADDR, 0);
5767
5768         for (i = 0; i < pfp_hdr->jt_size; i++)
5769                 WREG32_SOC15(GC, 0, mmCP_HYP_PFP_UCODE_DATA,
5770                              le32_to_cpup(fw_data + pfp_hdr->jt_offset + i));
5771
5772         WREG32_SOC15(GC, 0, mmCP_HYP_PFP_UCODE_ADDR, adev->gfx.pfp_fw_version);
5773
5774         return 0;
5775 }
5776
5777 static int gfx_v10_0_cp_gfx_load_ce_microcode(struct amdgpu_device *adev)
5778 {
5779         int r;
5780         const struct gfx_firmware_header_v1_0 *ce_hdr;
5781         const __le32 *fw_data;
5782         unsigned int i, fw_size;
5783         uint32_t tmp;
5784         uint32_t usec_timeout = 50000;  /* wait for 50ms */
5785
5786         ce_hdr = (const struct gfx_firmware_header_v1_0 *)
5787                 adev->gfx.ce_fw->data;
5788
5789         amdgpu_ucode_print_gfx_hdr(&ce_hdr->header);
5790
5791         fw_data = (const __le32 *)(adev->gfx.ce_fw->data +
5792                 le32_to_cpu(ce_hdr->header.ucode_array_offset_bytes));
5793         fw_size = le32_to_cpu(ce_hdr->header.ucode_size_bytes);
5794
5795         r = amdgpu_bo_create_reserved(adev, ce_hdr->header.ucode_size_bytes,
5796                                       PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,
5797                                       &adev->gfx.ce.ce_fw_obj,
5798                                       &adev->gfx.ce.ce_fw_gpu_addr,
5799                                       (void **)&adev->gfx.ce.ce_fw_ptr);
5800         if (r) {
5801                 dev_err(adev->dev, "(%d) failed to create ce fw bo\n", r);
5802                 gfx_v10_0_ce_fini(adev);
5803                 return r;
5804         }
5805
5806         memcpy(adev->gfx.ce.ce_fw_ptr, fw_data, fw_size);
5807
5808         amdgpu_bo_kunmap(adev->gfx.ce.ce_fw_obj);
5809         amdgpu_bo_unreserve(adev->gfx.ce.ce_fw_obj);
5810
5811         /* Trigger an invalidation of the L1 instruction caches */
5812         tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL);
5813         tmp = REG_SET_FIELD(tmp, CP_CE_IC_OP_CNTL, INVALIDATE_CACHE, 1);
5814         WREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL, tmp);
5815
5816         /* Wait for invalidation complete */
5817         for (i = 0; i < usec_timeout; i++) {
5818                 tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL);
5819                 if (1 == REG_GET_FIELD(tmp, CP_CE_IC_OP_CNTL,
5820                         INVALIDATE_CACHE_COMPLETE))
5821                         break;
5822                 udelay(1);
5823         }
5824
5825         if (i >= usec_timeout) {
5826                 dev_err(adev->dev, "failed to invalidate instruction cache\n");
5827                 return -EINVAL;
5828         }
5829
5830         if (amdgpu_emu_mode == 1)
5831                 adev->hdp.funcs->flush_hdp(adev, NULL);
5832
5833         tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_CNTL);
5834         tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, VMID, 0);
5835         tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, CACHE_POLICY, 0);
5836         tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, EXE_DISABLE, 0);
5837         tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, ADDRESS_CLAMP, 1);
5838         WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_LO,
5839                 adev->gfx.ce.ce_fw_gpu_addr & 0xFFFFF000);
5840         WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_HI,
5841                 upper_32_bits(adev->gfx.ce.ce_fw_gpu_addr));
5842
5843         WREG32_SOC15(GC, 0, mmCP_HYP_CE_UCODE_ADDR, 0);
5844
5845         for (i = 0; i < ce_hdr->jt_size; i++)
5846                 WREG32_SOC15(GC, 0, mmCP_HYP_CE_UCODE_DATA,
5847                              le32_to_cpup(fw_data + ce_hdr->jt_offset + i));
5848
5849         WREG32_SOC15(GC, 0, mmCP_HYP_CE_UCODE_ADDR, adev->gfx.ce_fw_version);
5850
5851         return 0;
5852 }
5853
5854 static int gfx_v10_0_cp_gfx_load_me_microcode(struct amdgpu_device *adev)
5855 {
5856         int r;
5857         const struct gfx_firmware_header_v1_0 *me_hdr;
5858         const __le32 *fw_data;
5859         unsigned int i, fw_size;
5860         uint32_t tmp;
5861         uint32_t usec_timeout = 50000;  /* wait for 50ms */
5862
5863         me_hdr = (const struct gfx_firmware_header_v1_0 *)
5864                 adev->gfx.me_fw->data;
5865
5866         amdgpu_ucode_print_gfx_hdr(&me_hdr->header);
5867
5868         fw_data = (const __le32 *)(adev->gfx.me_fw->data +
5869                 le32_to_cpu(me_hdr->header.ucode_array_offset_bytes));
5870         fw_size = le32_to_cpu(me_hdr->header.ucode_size_bytes);
5871
5872         r = amdgpu_bo_create_reserved(adev, me_hdr->header.ucode_size_bytes,
5873                                       PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,
5874                                       &adev->gfx.me.me_fw_obj,
5875                                       &adev->gfx.me.me_fw_gpu_addr,
5876                                       (void **)&adev->gfx.me.me_fw_ptr);
5877         if (r) {
5878                 dev_err(adev->dev, "(%d) failed to create me fw bo\n", r);
5879                 gfx_v10_0_me_fini(adev);
5880                 return r;
5881         }
5882
5883         memcpy(adev->gfx.me.me_fw_ptr, fw_data, fw_size);
5884
5885         amdgpu_bo_kunmap(adev->gfx.me.me_fw_obj);
5886         amdgpu_bo_unreserve(adev->gfx.me.me_fw_obj);
5887
5888         /* Trigger an invalidation of the L1 instruction caches */
5889         tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL);
5890         tmp = REG_SET_FIELD(tmp, CP_ME_IC_OP_CNTL, INVALIDATE_CACHE, 1);
5891         WREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL, tmp);
5892
5893         /* Wait for invalidation complete */
5894         for (i = 0; i < usec_timeout; i++) {
5895                 tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL);
5896                 if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL,
5897                         INVALIDATE_CACHE_COMPLETE))
5898                         break;
5899                 udelay(1);
5900         }
5901
5902         if (i >= usec_timeout) {
5903                 dev_err(adev->dev, "failed to invalidate instruction cache\n");
5904                 return -EINVAL;
5905         }
5906
5907         if (amdgpu_emu_mode == 1)
5908                 adev->hdp.funcs->flush_hdp(adev, NULL);
5909
5910         tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_CNTL);
5911         tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, VMID, 0);
5912         tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, CACHE_POLICY, 0);
5913         tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, EXE_DISABLE, 0);
5914         tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, ADDRESS_CLAMP, 1);
5915         WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_LO,
5916                 adev->gfx.me.me_fw_gpu_addr & 0xFFFFF000);
5917         WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_HI,
5918                 upper_32_bits(adev->gfx.me.me_fw_gpu_addr));
5919
5920         WREG32_SOC15(GC, 0, mmCP_HYP_ME_UCODE_ADDR, 0);
5921
5922         for (i = 0; i < me_hdr->jt_size; i++)
5923                 WREG32_SOC15(GC, 0, mmCP_HYP_ME_UCODE_DATA,
5924                              le32_to_cpup(fw_data + me_hdr->jt_offset + i));
5925
5926         WREG32_SOC15(GC, 0, mmCP_HYP_ME_UCODE_ADDR, adev->gfx.me_fw_version);
5927
5928         return 0;
5929 }
5930
5931 static int gfx_v10_0_cp_gfx_load_microcode(struct amdgpu_device *adev)
5932 {
5933         int r;
5934
5935         if (!adev->gfx.me_fw || !adev->gfx.pfp_fw || !adev->gfx.ce_fw)
5936                 return -EINVAL;
5937
5938         gfx_v10_0_cp_gfx_enable(adev, false);
5939
5940         r = gfx_v10_0_cp_gfx_load_pfp_microcode(adev);
5941         if (r) {
5942                 dev_err(adev->dev, "(%d) failed to load pfp fw\n", r);
5943                 return r;
5944         }
5945
5946         r = gfx_v10_0_cp_gfx_load_ce_microcode(adev);
5947         if (r) {
5948                 dev_err(adev->dev, "(%d) failed to load ce fw\n", r);
5949                 return r;
5950         }
5951
5952         r = gfx_v10_0_cp_gfx_load_me_microcode(adev);
5953         if (r) {
5954                 dev_err(adev->dev, "(%d) failed to load me fw\n", r);
5955                 return r;
5956         }
5957
5958         return 0;
5959 }
5960
5961 static int gfx_v10_0_cp_gfx_start(struct amdgpu_device *adev)
5962 {
5963         struct amdgpu_ring *ring;
5964         const struct cs_section_def *sect = NULL;
5965         const struct cs_extent_def *ext = NULL;
5966         int r, i;
5967         int ctx_reg_offset;
5968
5969         /* init the CP */
5970         WREG32_SOC15(GC, 0, mmCP_MAX_CONTEXT,
5971                      adev->gfx.config.max_hw_contexts - 1);
5972         WREG32_SOC15(GC, 0, mmCP_DEVICE_ID, 1);
5973
5974         gfx_v10_0_cp_gfx_enable(adev, true);
5975
5976         ring = &adev->gfx.gfx_ring[0];
5977         r = amdgpu_ring_alloc(ring, gfx_v10_0_get_csb_size(adev) + 4);
5978         if (r) {
5979                 DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r);
5980                 return r;
5981         }
5982
5983         amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
5984         amdgpu_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
5985
5986         amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1));
5987         amdgpu_ring_write(ring, 0x80000000);
5988         amdgpu_ring_write(ring, 0x80000000);
5989
5990         for (sect = gfx10_cs_data; sect->section != NULL; ++sect) {
5991                 for (ext = sect->section; ext->extent != NULL; ++ext) {
5992                         if (sect->id == SECT_CONTEXT) {
5993                                 amdgpu_ring_write(ring,
5994                                                   PACKET3(PACKET3_SET_CONTEXT_REG,
5995                                                           ext->reg_count));
5996                                 amdgpu_ring_write(ring, ext->reg_index -
5997                                                   PACKET3_SET_CONTEXT_REG_START);
5998                                 for (i = 0; i < ext->reg_count; i++)
5999                                         amdgpu_ring_write(ring, ext->extent[i]);
6000                         }
6001                 }
6002         }
6003
6004         ctx_reg_offset =
6005                 SOC15_REG_OFFSET(GC, 0, mmPA_SC_TILE_STEERING_OVERRIDE) - PACKET3_SET_CONTEXT_REG_START;
6006         amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
6007         amdgpu_ring_write(ring, ctx_reg_offset);
6008         amdgpu_ring_write(ring, adev->gfx.config.pa_sc_tile_steering_override);
6009
6010         amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
6011         amdgpu_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE);
6012
6013         amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));
6014         amdgpu_ring_write(ring, 0);
6015
6016         amdgpu_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2));
6017         amdgpu_ring_write(ring, PACKET3_BASE_INDEX(CE_PARTITION_BASE));
6018         amdgpu_ring_write(ring, 0x8000);
6019         amdgpu_ring_write(ring, 0x8000);
6020
6021         amdgpu_ring_commit(ring);
6022
6023         /* submit cs packet to copy state 0 to next available state */
6024         if (adev->gfx.num_gfx_rings > 1) {
6025                 /* maximum supported gfx ring is 2 */
6026                 ring = &adev->gfx.gfx_ring[1];
6027                 r = amdgpu_ring_alloc(ring, 2);
6028                 if (r) {
6029                         DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r);
6030                         return r;
6031                 }
6032
6033                 amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));
6034                 amdgpu_ring_write(ring, 0);
6035
6036                 amdgpu_ring_commit(ring);
6037         }
6038         return 0;
6039 }
6040
6041 static void gfx_v10_0_cp_gfx_switch_pipe(struct amdgpu_device *adev,
6042                                          CP_PIPE_ID pipe)
6043 {
6044         u32 tmp;
6045
6046         tmp = RREG32_SOC15(GC, 0, mmGRBM_GFX_CNTL);
6047         tmp = REG_SET_FIELD(tmp, GRBM_GFX_CNTL, PIPEID, pipe);
6048
6049         WREG32_SOC15(GC, 0, mmGRBM_GFX_CNTL, tmp);
6050 }
6051
6052 static void gfx_v10_0_cp_gfx_set_doorbell(struct amdgpu_device *adev,
6053                                           struct amdgpu_ring *ring)
6054 {
6055         u32 tmp;
6056
6057         if (!amdgpu_async_gfx_ring) {
6058                 tmp = RREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL);
6059                 if (ring->use_doorbell) {
6060                         tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
6061                                                 DOORBELL_OFFSET, ring->doorbell_index);
6062                         tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
6063                                                 DOORBELL_EN, 1);
6064                 } else {
6065                         tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
6066                                                 DOORBELL_EN, 0);
6067                 }
6068                 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL, tmp);
6069         }
6070         switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
6071         case IP_VERSION(10, 3, 0):
6072         case IP_VERSION(10, 3, 2):
6073         case IP_VERSION(10, 3, 1):
6074         case IP_VERSION(10, 3, 4):
6075         case IP_VERSION(10, 3, 5):
6076         case IP_VERSION(10, 3, 6):
6077         case IP_VERSION(10, 3, 3):
6078         case IP_VERSION(10, 3, 7):
6079                 tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER,
6080                                     DOORBELL_RANGE_LOWER_Sienna_Cichlid, ring->doorbell_index);
6081                 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_LOWER, tmp);
6082
6083                 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_UPPER,
6084                              CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_Sienna_Cichlid_MASK);
6085                 break;
6086         default:
6087                 tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER,
6088                                     DOORBELL_RANGE_LOWER, ring->doorbell_index);
6089                 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_LOWER, tmp);
6090
6091                 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_UPPER,
6092                              CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_MASK);
6093                 break;
6094         }
6095 }
6096
6097 static int gfx_v10_0_cp_gfx_resume(struct amdgpu_device *adev)
6098 {
6099         struct amdgpu_ring *ring;
6100         u32 tmp;
6101         u32 rb_bufsz;
6102         u64 rb_addr, rptr_addr, wptr_gpu_addr;
6103
6104         /* Set the write pointer delay */
6105         WREG32_SOC15(GC, 0, mmCP_RB_WPTR_DELAY, 0);
6106
6107         /* set the RB to use vmid 0 */
6108         WREG32_SOC15(GC, 0, mmCP_RB_VMID, 0);
6109
6110         /* Init gfx ring 0 for pipe 0 */
6111         mutex_lock(&adev->srbm_mutex);
6112         gfx_v10_0_cp_gfx_switch_pipe(adev, PIPE_ID0);
6113
6114         /* Set ring buffer size */
6115         ring = &adev->gfx.gfx_ring[0];
6116         rb_bufsz = order_base_2(ring->ring_size / 8);
6117         tmp = REG_SET_FIELD(0, CP_RB0_CNTL, RB_BUFSZ, rb_bufsz);
6118         tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, RB_BLKSZ, rb_bufsz - 2);
6119 #ifdef __BIG_ENDIAN
6120         tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, BUF_SWAP, 1);
6121 #endif
6122         WREG32_SOC15(GC, 0, mmCP_RB0_CNTL, tmp);
6123
6124         /* Initialize the ring buffer's write pointers */
6125         ring->wptr = 0;
6126         WREG32_SOC15(GC, 0, mmCP_RB0_WPTR, lower_32_bits(ring->wptr));
6127         WREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI, upper_32_bits(ring->wptr));
6128
6129         /* set the wb address wether it's enabled or not */
6130         rptr_addr = ring->rptr_gpu_addr;
6131         WREG32_SOC15(GC, 0, mmCP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr));
6132         WREG32_SOC15(GC, 0, mmCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) &
6133                      CP_RB_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK);
6134
6135         wptr_gpu_addr = ring->wptr_gpu_addr;
6136         WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_LO,
6137                      lower_32_bits(wptr_gpu_addr));
6138         WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI,
6139                      upper_32_bits(wptr_gpu_addr));
6140
6141         mdelay(1);
6142         WREG32_SOC15(GC, 0, mmCP_RB0_CNTL, tmp);
6143
6144         rb_addr = ring->gpu_addr >> 8;
6145         WREG32_SOC15(GC, 0, mmCP_RB0_BASE, rb_addr);
6146         WREG32_SOC15(GC, 0, mmCP_RB0_BASE_HI, upper_32_bits(rb_addr));
6147
6148         WREG32_SOC15(GC, 0, mmCP_RB_ACTIVE, 1);
6149
6150         gfx_v10_0_cp_gfx_set_doorbell(adev, ring);
6151         mutex_unlock(&adev->srbm_mutex);
6152
6153         /* Init gfx ring 1 for pipe 1 */
6154         if (adev->gfx.num_gfx_rings > 1) {
6155                 mutex_lock(&adev->srbm_mutex);
6156                 gfx_v10_0_cp_gfx_switch_pipe(adev, PIPE_ID1);
6157                 /* maximum supported gfx ring is 2 */
6158                 ring = &adev->gfx.gfx_ring[1];
6159                 rb_bufsz = order_base_2(ring->ring_size / 8);
6160                 tmp = REG_SET_FIELD(0, CP_RB1_CNTL, RB_BUFSZ, rb_bufsz);
6161                 tmp = REG_SET_FIELD(tmp, CP_RB1_CNTL, RB_BLKSZ, rb_bufsz - 2);
6162                 WREG32_SOC15(GC, 0, mmCP_RB1_CNTL, tmp);
6163                 /* Initialize the ring buffer's write pointers */
6164                 ring->wptr = 0;
6165                 WREG32_SOC15(GC, 0, mmCP_RB1_WPTR, lower_32_bits(ring->wptr));
6166                 WREG32_SOC15(GC, 0, mmCP_RB1_WPTR_HI, upper_32_bits(ring->wptr));
6167                 /* Set the wb address wether it's enabled or not */
6168                 rptr_addr = ring->rptr_gpu_addr;
6169                 WREG32_SOC15(GC, 0, mmCP_RB1_RPTR_ADDR, lower_32_bits(rptr_addr));
6170                 WREG32_SOC15(GC, 0, mmCP_RB1_RPTR_ADDR_HI, upper_32_bits(rptr_addr) &
6171                              CP_RB1_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK);
6172                 wptr_gpu_addr = ring->wptr_gpu_addr;
6173                 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_LO,
6174                              lower_32_bits(wptr_gpu_addr));
6175                 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI,
6176                              upper_32_bits(wptr_gpu_addr));
6177
6178                 mdelay(1);
6179                 WREG32_SOC15(GC, 0, mmCP_RB1_CNTL, tmp);
6180
6181                 rb_addr = ring->gpu_addr >> 8;
6182                 WREG32_SOC15(GC, 0, mmCP_RB1_BASE, rb_addr);
6183                 WREG32_SOC15(GC, 0, mmCP_RB1_BASE_HI, upper_32_bits(rb_addr));
6184                 WREG32_SOC15(GC, 0, mmCP_RB1_ACTIVE, 1);
6185
6186                 gfx_v10_0_cp_gfx_set_doorbell(adev, ring);
6187                 mutex_unlock(&adev->srbm_mutex);
6188         }
6189         /* Switch to pipe 0 */
6190         mutex_lock(&adev->srbm_mutex);
6191         gfx_v10_0_cp_gfx_switch_pipe(adev, PIPE_ID0);
6192         mutex_unlock(&adev->srbm_mutex);
6193
6194         /* start the ring */
6195         gfx_v10_0_cp_gfx_start(adev);
6196
6197         return 0;
6198 }
6199
6200 static void gfx_v10_0_cp_compute_enable(struct amdgpu_device *adev, bool enable)
6201 {
6202         if (enable) {
6203                 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
6204                 case IP_VERSION(10, 3, 0):
6205                 case IP_VERSION(10, 3, 2):
6206                 case IP_VERSION(10, 3, 1):
6207                 case IP_VERSION(10, 3, 4):
6208                 case IP_VERSION(10, 3, 5):
6209                 case IP_VERSION(10, 3, 6):
6210                 case IP_VERSION(10, 3, 3):
6211                 case IP_VERSION(10, 3, 7):
6212                         WREG32_SOC15(GC, 0, mmCP_MEC_CNTL_Sienna_Cichlid, 0);
6213                         break;
6214                 default:
6215                         WREG32_SOC15(GC, 0, mmCP_MEC_CNTL, 0);
6216                         break;
6217                 }
6218         } else {
6219                 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
6220                 case IP_VERSION(10, 3, 0):
6221                 case IP_VERSION(10, 3, 2):
6222                 case IP_VERSION(10, 3, 1):
6223                 case IP_VERSION(10, 3, 4):
6224                 case IP_VERSION(10, 3, 5):
6225                 case IP_VERSION(10, 3, 6):
6226                 case IP_VERSION(10, 3, 3):
6227                 case IP_VERSION(10, 3, 7):
6228                         WREG32_SOC15(GC, 0, mmCP_MEC_CNTL_Sienna_Cichlid,
6229                                      (CP_MEC_CNTL__MEC_ME1_HALT_MASK |
6230                                       CP_MEC_CNTL__MEC_ME2_HALT_MASK));
6231                         break;
6232                 default:
6233                         WREG32_SOC15(GC, 0, mmCP_MEC_CNTL,
6234                                      (CP_MEC_CNTL__MEC_ME1_HALT_MASK |
6235                                       CP_MEC_CNTL__MEC_ME2_HALT_MASK));
6236                         break;
6237                 }
6238                 adev->gfx.kiq[0].ring.sched.ready = false;
6239         }
6240         udelay(50);
6241 }
6242
6243 static int gfx_v10_0_cp_compute_load_microcode(struct amdgpu_device *adev)
6244 {
6245         const struct gfx_firmware_header_v1_0 *mec_hdr;
6246         const __le32 *fw_data;
6247         unsigned int i;
6248         u32 tmp;
6249         u32 usec_timeout = 50000; /* Wait for 50 ms */
6250
6251         if (!adev->gfx.mec_fw)
6252                 return -EINVAL;
6253
6254         gfx_v10_0_cp_compute_enable(adev, false);
6255
6256         mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
6257         amdgpu_ucode_print_gfx_hdr(&mec_hdr->header);
6258
6259         fw_data = (const __le32 *)
6260                 (adev->gfx.mec_fw->data +
6261                  le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes));
6262
6263         /* Trigger an invalidation of the L1 instruction caches */
6264         tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL);
6265         tmp = REG_SET_FIELD(tmp, CP_CPC_IC_OP_CNTL, INVALIDATE_CACHE, 1);
6266         WREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL, tmp);
6267
6268         /* Wait for invalidation complete */
6269         for (i = 0; i < usec_timeout; i++) {
6270                 tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL);
6271                 if (1 == REG_GET_FIELD(tmp, CP_CPC_IC_OP_CNTL,
6272                                        INVALIDATE_CACHE_COMPLETE))
6273                         break;
6274                 udelay(1);
6275         }
6276
6277         if (i >= usec_timeout) {
6278                 dev_err(adev->dev, "failed to invalidate instruction cache\n");
6279                 return -EINVAL;
6280         }
6281
6282         if (amdgpu_emu_mode == 1)
6283                 adev->hdp.funcs->flush_hdp(adev, NULL);
6284
6285         tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_CNTL);
6286         tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0);
6287         tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, EXE_DISABLE, 0);
6288         tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, ADDRESS_CLAMP, 1);
6289         WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_CNTL, tmp);
6290
6291         WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_LO, adev->gfx.mec.mec_fw_gpu_addr &
6292                      0xFFFFF000);
6293         WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_HI,
6294                      upper_32_bits(adev->gfx.mec.mec_fw_gpu_addr));
6295
6296         /* MEC1 */
6297         WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_ADDR, 0);
6298
6299         for (i = 0; i < mec_hdr->jt_size; i++)
6300                 WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_DATA,
6301                              le32_to_cpup(fw_data + mec_hdr->jt_offset + i));
6302
6303         WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_ADDR, adev->gfx.mec_fw_version);
6304
6305         /*
6306          * TODO: Loading MEC2 firmware is only necessary if MEC2 should run
6307          * different microcode than MEC1.
6308          */
6309
6310         return 0;
6311 }
6312
6313 static void gfx_v10_0_kiq_setting(struct amdgpu_ring *ring)
6314 {
6315         uint32_t tmp;
6316         struct amdgpu_device *adev = ring->adev;
6317
6318         /* tell RLC which is KIQ queue */
6319         switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
6320         case IP_VERSION(10, 3, 0):
6321         case IP_VERSION(10, 3, 2):
6322         case IP_VERSION(10, 3, 1):
6323         case IP_VERSION(10, 3, 4):
6324         case IP_VERSION(10, 3, 5):
6325         case IP_VERSION(10, 3, 6):
6326         case IP_VERSION(10, 3, 3):
6327         case IP_VERSION(10, 3, 7):
6328                 tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS_Sienna_Cichlid);
6329                 tmp &= 0xffffff00;
6330                 tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue);
6331                 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS_Sienna_Cichlid, tmp);
6332                 tmp |= 0x80;
6333                 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS_Sienna_Cichlid, tmp);
6334                 break;
6335         default:
6336                 tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS);
6337                 tmp &= 0xffffff00;
6338                 tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue);
6339                 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS, tmp);
6340                 tmp |= 0x80;
6341                 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS, tmp);
6342                 break;
6343         }
6344 }
6345
6346 static void gfx_v10_0_gfx_mqd_set_priority(struct amdgpu_device *adev,
6347                                            struct v10_gfx_mqd *mqd,
6348                                            struct amdgpu_mqd_prop *prop)
6349 {
6350         bool priority = 0;
6351         u32 tmp;
6352
6353         /* set up default queue priority level
6354          * 0x0 = low priority, 0x1 = high priority
6355          */
6356         if (prop->hqd_pipe_priority == AMDGPU_GFX_PIPE_PRIO_HIGH)
6357                 priority = 1;
6358
6359         tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_QUEUE_PRIORITY);
6360         tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_QUEUE_PRIORITY, PRIORITY_LEVEL, priority);
6361         mqd->cp_gfx_hqd_queue_priority = tmp;
6362 }
6363
6364 static int gfx_v10_0_gfx_mqd_init(struct amdgpu_device *adev, void *m,
6365                                   struct amdgpu_mqd_prop *prop)
6366 {
6367         struct v10_gfx_mqd *mqd = m;
6368         uint64_t hqd_gpu_addr, wb_gpu_addr;
6369         uint32_t tmp;
6370         uint32_t rb_bufsz;
6371
6372         /* set up gfx hqd wptr */
6373         mqd->cp_gfx_hqd_wptr = 0;
6374         mqd->cp_gfx_hqd_wptr_hi = 0;
6375
6376         /* set the pointer to the MQD */
6377         mqd->cp_mqd_base_addr = prop->mqd_gpu_addr & 0xfffffffc;
6378         mqd->cp_mqd_base_addr_hi = upper_32_bits(prop->mqd_gpu_addr);
6379
6380         /* set up mqd control */
6381         tmp = RREG32_SOC15(GC, 0, mmCP_GFX_MQD_CONTROL);
6382         tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, VMID, 0);
6383         tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, PRIV_STATE, 1);
6384         tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, CACHE_POLICY, 0);
6385         mqd->cp_gfx_mqd_control = tmp;
6386
6387         /* set up gfx_hqd_vimd with 0x0 to indicate the ring buffer's vmid */
6388         tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_VMID);
6389         tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_VMID, VMID, 0);
6390         mqd->cp_gfx_hqd_vmid = 0;
6391
6392         /* set up gfx queue priority */
6393         gfx_v10_0_gfx_mqd_set_priority(adev, mqd, prop);
6394
6395         /* set up time quantum */
6396         tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_QUANTUM);
6397         tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_QUANTUM, QUANTUM_EN, 1);
6398         mqd->cp_gfx_hqd_quantum = tmp;
6399
6400         /* set up gfx hqd base. this is similar as CP_RB_BASE */
6401         hqd_gpu_addr = prop->hqd_base_gpu_addr >> 8;
6402         mqd->cp_gfx_hqd_base = hqd_gpu_addr;
6403         mqd->cp_gfx_hqd_base_hi = upper_32_bits(hqd_gpu_addr);
6404
6405         /* set up hqd_rptr_addr/_hi, similar as CP_RB_RPTR */
6406         wb_gpu_addr = prop->rptr_gpu_addr;
6407         mqd->cp_gfx_hqd_rptr_addr = wb_gpu_addr & 0xfffffffc;
6408         mqd->cp_gfx_hqd_rptr_addr_hi =
6409                 upper_32_bits(wb_gpu_addr) & 0xffff;
6410
6411         /* set up rb_wptr_poll addr */
6412         wb_gpu_addr = prop->wptr_gpu_addr;
6413         mqd->cp_rb_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc;
6414         mqd->cp_rb_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff;
6415
6416         /* set up the gfx_hqd_control, similar as CP_RB0_CNTL */
6417         rb_bufsz = order_base_2(prop->queue_size / 4) - 1;
6418         tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_CNTL);
6419         tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_BUFSZ, rb_bufsz);
6420         tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_BLKSZ, rb_bufsz - 2);
6421 #ifdef __BIG_ENDIAN
6422         tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, BUF_SWAP, 1);
6423 #endif
6424         mqd->cp_gfx_hqd_cntl = tmp;
6425
6426         /* set up cp_doorbell_control */
6427         tmp = RREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL);
6428         if (prop->use_doorbell) {
6429                 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
6430                                     DOORBELL_OFFSET, prop->doorbell_index);
6431                 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
6432                                     DOORBELL_EN, 1);
6433         } else
6434                 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
6435                                     DOORBELL_EN, 0);
6436         mqd->cp_rb_doorbell_control = tmp;
6437
6438         /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */
6439         mqd->cp_gfx_hqd_rptr = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_RPTR);
6440
6441         /* active the queue */
6442         mqd->cp_gfx_hqd_active = 1;
6443
6444         return 0;
6445 }
6446
6447 static int gfx_v10_0_gfx_init_queue(struct amdgpu_ring *ring)
6448 {
6449         struct amdgpu_device *adev = ring->adev;
6450         struct v10_gfx_mqd *mqd = ring->mqd_ptr;
6451         int mqd_idx = ring - &adev->gfx.gfx_ring[0];
6452
6453         if (!amdgpu_in_reset(adev) && !adev->in_suspend) {
6454                 memset((void *)mqd, 0, sizeof(*mqd));
6455                 mutex_lock(&adev->srbm_mutex);
6456                 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
6457                 amdgpu_ring_init_mqd(ring);
6458
6459                 /*
6460                  * if there are 2 gfx rings, set the lower doorbell
6461                  * range of the first ring, otherwise the range of
6462                  * the second ring will override the first ring
6463                  */
6464                 if (ring->doorbell_index == adev->doorbell_index.gfx_ring0 << 1)
6465                         gfx_v10_0_cp_gfx_set_doorbell(adev, ring);
6466
6467                 nv_grbm_select(adev, 0, 0, 0, 0);
6468                 mutex_unlock(&adev->srbm_mutex);
6469                 if (adev->gfx.me.mqd_backup[mqd_idx])
6470                         memcpy_fromio(adev->gfx.me.mqd_backup[mqd_idx], mqd, sizeof(*mqd));
6471         } else {
6472                 mutex_lock(&adev->srbm_mutex);
6473                 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
6474                 if (ring->doorbell_index == adev->doorbell_index.gfx_ring0 << 1)
6475                         gfx_v10_0_cp_gfx_set_doorbell(adev, ring);
6476
6477                 nv_grbm_select(adev, 0, 0, 0, 0);
6478                 mutex_unlock(&adev->srbm_mutex);
6479                 /* restore mqd with the backup copy */
6480                 if (adev->gfx.me.mqd_backup[mqd_idx])
6481                         memcpy_toio(mqd, adev->gfx.me.mqd_backup[mqd_idx], sizeof(*mqd));
6482                 /* reset the ring */
6483                 ring->wptr = 0;
6484                 *ring->wptr_cpu_addr = 0;
6485                 amdgpu_ring_clear_ring(ring);
6486         }
6487
6488         return 0;
6489 }
6490
6491 static int gfx_v10_0_cp_async_gfx_ring_resume(struct amdgpu_device *adev)
6492 {
6493         int r, i;
6494         struct amdgpu_ring *ring;
6495
6496         for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
6497                 ring = &adev->gfx.gfx_ring[i];
6498
6499                 r = amdgpu_bo_reserve(ring->mqd_obj, false);
6500                 if (unlikely(r != 0))
6501                         return r;
6502
6503                 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr);
6504                 if (!r) {
6505                         r = gfx_v10_0_gfx_init_queue(ring);
6506                         amdgpu_bo_kunmap(ring->mqd_obj);
6507                         ring->mqd_ptr = NULL;
6508                 }
6509                 amdgpu_bo_unreserve(ring->mqd_obj);
6510                 if (r)
6511                         return r;
6512         }
6513
6514         r = amdgpu_gfx_enable_kgq(adev, 0);
6515         if (r)
6516                 return r;
6517
6518         return gfx_v10_0_cp_gfx_start(adev);
6519 }
6520
6521 static int gfx_v10_0_compute_mqd_init(struct amdgpu_device *adev, void *m,
6522                                       struct amdgpu_mqd_prop *prop)
6523 {
6524         struct v10_compute_mqd *mqd = m;
6525         uint64_t hqd_gpu_addr, wb_gpu_addr, eop_base_addr;
6526         uint32_t tmp;
6527
6528         mqd->header = 0xC0310800;
6529         mqd->compute_pipelinestat_enable = 0x00000001;
6530         mqd->compute_static_thread_mgmt_se0 = 0xffffffff;
6531         mqd->compute_static_thread_mgmt_se1 = 0xffffffff;
6532         mqd->compute_static_thread_mgmt_se2 = 0xffffffff;
6533         mqd->compute_static_thread_mgmt_se3 = 0xffffffff;
6534         mqd->compute_misc_reserved = 0x00000003;
6535
6536         eop_base_addr = prop->eop_gpu_addr >> 8;
6537         mqd->cp_hqd_eop_base_addr_lo = eop_base_addr;
6538         mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr);
6539
6540         /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */
6541         tmp = RREG32_SOC15(GC, 0, mmCP_HQD_EOP_CONTROL);
6542         tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE,
6543                         (order_base_2(GFX10_MEC_HPD_SIZE / 4) - 1));
6544
6545         mqd->cp_hqd_eop_control = tmp;
6546
6547         /* enable doorbell? */
6548         tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL);
6549
6550         if (prop->use_doorbell) {
6551                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
6552                                     DOORBELL_OFFSET, prop->doorbell_index);
6553                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
6554                                     DOORBELL_EN, 1);
6555                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
6556                                     DOORBELL_SOURCE, 0);
6557                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
6558                                     DOORBELL_HIT, 0);
6559         } else {
6560                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
6561                                     DOORBELL_EN, 0);
6562         }
6563
6564         mqd->cp_hqd_pq_doorbell_control = tmp;
6565
6566         /* disable the queue if it's active */
6567         mqd->cp_hqd_dequeue_request = 0;
6568         mqd->cp_hqd_pq_rptr = 0;
6569         mqd->cp_hqd_pq_wptr_lo = 0;
6570         mqd->cp_hqd_pq_wptr_hi = 0;
6571
6572         /* set the pointer to the MQD */
6573         mqd->cp_mqd_base_addr_lo = prop->mqd_gpu_addr & 0xfffffffc;
6574         mqd->cp_mqd_base_addr_hi = upper_32_bits(prop->mqd_gpu_addr);
6575
6576         /* set MQD vmid to 0 */
6577         tmp = RREG32_SOC15(GC, 0, mmCP_MQD_CONTROL);
6578         tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0);
6579         mqd->cp_mqd_control = tmp;
6580
6581         /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */
6582         hqd_gpu_addr = prop->hqd_base_gpu_addr >> 8;
6583         mqd->cp_hqd_pq_base_lo = hqd_gpu_addr;
6584         mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr);
6585
6586         /* set up the HQD, this is similar to CP_RB0_CNTL */
6587         tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_CONTROL);
6588         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE,
6589                             (order_base_2(prop->queue_size / 4) - 1));
6590         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE,
6591                             (order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1));
6592 #ifdef __BIG_ENDIAN
6593         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ENDIAN_SWAP, 1);
6594 #endif
6595         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 0);
6596         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, TUNNEL_DISPATCH,
6597                             prop->allow_tunneling);
6598         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1);
6599         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1);
6600         mqd->cp_hqd_pq_control = tmp;
6601
6602         /* set the wb address whether it's enabled or not */
6603         wb_gpu_addr = prop->rptr_gpu_addr;
6604         mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc;
6605         mqd->cp_hqd_pq_rptr_report_addr_hi =
6606                 upper_32_bits(wb_gpu_addr) & 0xffff;
6607
6608         /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */
6609         wb_gpu_addr = prop->wptr_gpu_addr;
6610         mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc;
6611         mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff;
6612
6613         /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */
6614         mqd->cp_hqd_pq_rptr = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR);
6615
6616         /* set the vmid for the queue */
6617         mqd->cp_hqd_vmid = 0;
6618
6619         tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PERSISTENT_STATE);
6620         tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, PRELOAD_SIZE, 0x53);
6621         mqd->cp_hqd_persistent_state = tmp;
6622
6623         /* set MIN_IB_AVAIL_SIZE */
6624         tmp = RREG32_SOC15(GC, 0, mmCP_HQD_IB_CONTROL);
6625         tmp = REG_SET_FIELD(tmp, CP_HQD_IB_CONTROL, MIN_IB_AVAIL_SIZE, 3);
6626         mqd->cp_hqd_ib_control = tmp;
6627
6628         /* set static priority for a compute queue/ring */
6629         mqd->cp_hqd_pipe_priority = prop->hqd_pipe_priority;
6630         mqd->cp_hqd_queue_priority = prop->hqd_queue_priority;
6631
6632         mqd->cp_hqd_active = prop->hqd_active;
6633
6634         return 0;
6635 }
6636
6637 static int gfx_v10_0_kiq_init_register(struct amdgpu_ring *ring)
6638 {
6639         struct amdgpu_device *adev = ring->adev;
6640         struct v10_compute_mqd *mqd = ring->mqd_ptr;
6641         int j;
6642
6643         /* inactivate the queue */
6644         if (amdgpu_sriov_vf(adev))
6645                 WREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE, 0);
6646
6647         /* disable wptr polling */
6648         WREG32_FIELD15(GC, 0, CP_PQ_WPTR_POLL_CNTL, EN, 0);
6649
6650         /* disable the queue if it's active */
6651         if (RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1) {
6652                 WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST, 1);
6653                 for (j = 0; j < adev->usec_timeout; j++) {
6654                         if (!(RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1))
6655                                 break;
6656                         udelay(1);
6657                 }
6658                 WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST,
6659                        mqd->cp_hqd_dequeue_request);
6660                 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR,
6661                        mqd->cp_hqd_pq_rptr);
6662                 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_LO,
6663                        mqd->cp_hqd_pq_wptr_lo);
6664                 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_HI,
6665                        mqd->cp_hqd_pq_wptr_hi);
6666         }
6667
6668         /* disable doorbells */
6669         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL, 0);
6670
6671         /* write the EOP addr */
6672         WREG32_SOC15(GC, 0, mmCP_HQD_EOP_BASE_ADDR,
6673                mqd->cp_hqd_eop_base_addr_lo);
6674         WREG32_SOC15(GC, 0, mmCP_HQD_EOP_BASE_ADDR_HI,
6675                mqd->cp_hqd_eop_base_addr_hi);
6676
6677         /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */
6678         WREG32_SOC15(GC, 0, mmCP_HQD_EOP_CONTROL,
6679                mqd->cp_hqd_eop_control);
6680
6681         /* set the pointer to the MQD */
6682         WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR,
6683                mqd->cp_mqd_base_addr_lo);
6684         WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR_HI,
6685                mqd->cp_mqd_base_addr_hi);
6686
6687         /* set MQD vmid to 0 */
6688         WREG32_SOC15(GC, 0, mmCP_MQD_CONTROL,
6689                mqd->cp_mqd_control);
6690
6691         /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */
6692         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_BASE,
6693                mqd->cp_hqd_pq_base_lo);
6694         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_BASE_HI,
6695                mqd->cp_hqd_pq_base_hi);
6696
6697         /* set up the HQD, this is similar to CP_RB0_CNTL */
6698         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_CONTROL,
6699                mqd->cp_hqd_pq_control);
6700
6701         /* set the wb address whether it's enabled or not */
6702         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR_REPORT_ADDR,
6703                 mqd->cp_hqd_pq_rptr_report_addr_lo);
6704         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI,
6705                 mqd->cp_hqd_pq_rptr_report_addr_hi);
6706
6707         /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */
6708         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR,
6709                mqd->cp_hqd_pq_wptr_poll_addr_lo);
6710         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR_HI,
6711                mqd->cp_hqd_pq_wptr_poll_addr_hi);
6712
6713         /* enable the doorbell if requested */
6714         if (ring->use_doorbell) {
6715                 WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_LOWER,
6716                         (adev->doorbell_index.kiq * 2) << 2);
6717                 WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_UPPER,
6718                         (adev->doorbell_index.userqueue_end * 2) << 2);
6719         }
6720
6721         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL,
6722                mqd->cp_hqd_pq_doorbell_control);
6723
6724         /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */
6725         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_LO,
6726                mqd->cp_hqd_pq_wptr_lo);
6727         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_HI,
6728                mqd->cp_hqd_pq_wptr_hi);
6729
6730         /* set the vmid for the queue */
6731         WREG32_SOC15(GC, 0, mmCP_HQD_VMID, mqd->cp_hqd_vmid);
6732
6733         WREG32_SOC15(GC, 0, mmCP_HQD_PERSISTENT_STATE,
6734                mqd->cp_hqd_persistent_state);
6735
6736         /* activate the queue */
6737         WREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE,
6738                mqd->cp_hqd_active);
6739
6740         if (ring->use_doorbell)
6741                 WREG32_FIELD15(GC, 0, CP_PQ_STATUS, DOORBELL_ENABLE, 1);
6742
6743         return 0;
6744 }
6745
6746 static int gfx_v10_0_kiq_init_queue(struct amdgpu_ring *ring)
6747 {
6748         struct amdgpu_device *adev = ring->adev;
6749         struct v10_compute_mqd *mqd = ring->mqd_ptr;
6750
6751         gfx_v10_0_kiq_setting(ring);
6752
6753         if (amdgpu_in_reset(adev)) { /* for GPU_RESET case */
6754                 /* reset MQD to a clean status */
6755                 if (adev->gfx.kiq[0].mqd_backup)
6756                         memcpy_toio(mqd, adev->gfx.kiq[0].mqd_backup, sizeof(*mqd));
6757
6758                 /* reset ring buffer */
6759                 ring->wptr = 0;
6760                 amdgpu_ring_clear_ring(ring);
6761
6762                 mutex_lock(&adev->srbm_mutex);
6763                 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
6764                 gfx_v10_0_kiq_init_register(ring);
6765                 nv_grbm_select(adev, 0, 0, 0, 0);
6766                 mutex_unlock(&adev->srbm_mutex);
6767         } else {
6768                 memset((void *)mqd, 0, sizeof(*mqd));
6769                 if (amdgpu_sriov_vf(adev) && adev->in_suspend)
6770                         amdgpu_ring_clear_ring(ring);
6771                 mutex_lock(&adev->srbm_mutex);
6772                 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
6773                 amdgpu_ring_init_mqd(ring);
6774                 gfx_v10_0_kiq_init_register(ring);
6775                 nv_grbm_select(adev, 0, 0, 0, 0);
6776                 mutex_unlock(&adev->srbm_mutex);
6777
6778                 if (adev->gfx.kiq[0].mqd_backup)
6779                         memcpy_fromio(adev->gfx.kiq[0].mqd_backup, mqd, sizeof(*mqd));
6780         }
6781
6782         return 0;
6783 }
6784
6785 static int gfx_v10_0_kcq_init_queue(struct amdgpu_ring *ring)
6786 {
6787         struct amdgpu_device *adev = ring->adev;
6788         struct v10_compute_mqd *mqd = ring->mqd_ptr;
6789         int mqd_idx = ring - &adev->gfx.compute_ring[0];
6790
6791         if (!amdgpu_in_reset(adev) && !adev->in_suspend) {
6792                 memset((void *)mqd, 0, sizeof(*mqd));
6793                 mutex_lock(&adev->srbm_mutex);
6794                 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
6795                 amdgpu_ring_init_mqd(ring);
6796                 nv_grbm_select(adev, 0, 0, 0, 0);
6797                 mutex_unlock(&adev->srbm_mutex);
6798
6799                 if (adev->gfx.mec.mqd_backup[mqd_idx])
6800                         memcpy_fromio(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(*mqd));
6801         } else {
6802                 /* restore MQD to a clean status */
6803                 if (adev->gfx.mec.mqd_backup[mqd_idx])
6804                         memcpy_toio(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(*mqd));
6805                 /* reset ring buffer */
6806                 ring->wptr = 0;
6807                 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, 0);
6808                 amdgpu_ring_clear_ring(ring);
6809         }
6810
6811         return 0;
6812 }
6813
6814 static int gfx_v10_0_kiq_resume(struct amdgpu_device *adev)
6815 {
6816         struct amdgpu_ring *ring;
6817         int r;
6818
6819         ring = &adev->gfx.kiq[0].ring;
6820
6821         r = amdgpu_bo_reserve(ring->mqd_obj, false);
6822         if (unlikely(r != 0))
6823                 return r;
6824
6825         r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr);
6826         if (unlikely(r != 0)) {
6827                 amdgpu_bo_unreserve(ring->mqd_obj);
6828                 return r;
6829         }
6830
6831         gfx_v10_0_kiq_init_queue(ring);
6832         amdgpu_bo_kunmap(ring->mqd_obj);
6833         ring->mqd_ptr = NULL;
6834         amdgpu_bo_unreserve(ring->mqd_obj);
6835         return 0;
6836 }
6837
6838 static int gfx_v10_0_kcq_resume(struct amdgpu_device *adev)
6839 {
6840         struct amdgpu_ring *ring = NULL;
6841         int r = 0, i;
6842
6843         gfx_v10_0_cp_compute_enable(adev, true);
6844
6845         for (i = 0; i < adev->gfx.num_compute_rings; i++) {
6846                 ring = &adev->gfx.compute_ring[i];
6847
6848                 r = amdgpu_bo_reserve(ring->mqd_obj, false);
6849                 if (unlikely(r != 0))
6850                         goto done;
6851                 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr);
6852                 if (!r) {
6853                         r = gfx_v10_0_kcq_init_queue(ring);
6854                         amdgpu_bo_kunmap(ring->mqd_obj);
6855                         ring->mqd_ptr = NULL;
6856                 }
6857                 amdgpu_bo_unreserve(ring->mqd_obj);
6858                 if (r)
6859                         goto done;
6860         }
6861
6862         r = amdgpu_gfx_enable_kcq(adev, 0);
6863 done:
6864         return r;
6865 }
6866
6867 static int gfx_v10_0_cp_resume(struct amdgpu_device *adev)
6868 {
6869         int r, i;
6870         struct amdgpu_ring *ring;
6871
6872         if (!(adev->flags & AMD_IS_APU))
6873                 gfx_v10_0_enable_gui_idle_interrupt(adev, false);
6874
6875         if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
6876                 /* legacy firmware loading */
6877                 r = gfx_v10_0_cp_gfx_load_microcode(adev);
6878                 if (r)
6879                         return r;
6880
6881                 r = gfx_v10_0_cp_compute_load_microcode(adev);
6882                 if (r)
6883                         return r;
6884         }
6885
6886         if (adev->enable_mes_kiq && adev->mes.kiq_hw_init)
6887                 r = amdgpu_mes_kiq_hw_init(adev);
6888         else
6889                 r = gfx_v10_0_kiq_resume(adev);
6890         if (r)
6891                 return r;
6892
6893         r = gfx_v10_0_kcq_resume(adev);
6894         if (r)
6895                 return r;
6896
6897         if (!amdgpu_async_gfx_ring) {
6898                 r = gfx_v10_0_cp_gfx_resume(adev);
6899                 if (r)
6900                         return r;
6901         } else {
6902                 r = gfx_v10_0_cp_async_gfx_ring_resume(adev);
6903                 if (r)
6904                         return r;
6905         }
6906
6907         for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
6908                 ring = &adev->gfx.gfx_ring[i];
6909                 r = amdgpu_ring_test_helper(ring);
6910                 if (r)
6911                         return r;
6912         }
6913
6914         for (i = 0; i < adev->gfx.num_compute_rings; i++) {
6915                 ring = &adev->gfx.compute_ring[i];
6916                 r = amdgpu_ring_test_helper(ring);
6917                 if (r)
6918                         return r;
6919         }
6920
6921         return 0;
6922 }
6923
6924 static void gfx_v10_0_cp_enable(struct amdgpu_device *adev, bool enable)
6925 {
6926         gfx_v10_0_cp_gfx_enable(adev, enable);
6927         gfx_v10_0_cp_compute_enable(adev, enable);
6928 }
6929
6930 static bool gfx_v10_0_check_grbm_cam_remapping(struct amdgpu_device *adev)
6931 {
6932         uint32_t data, pattern = 0xDEADBEEF;
6933
6934         /*
6935          * check if mmVGT_ESGS_RING_SIZE_UMD
6936          * has been remapped to mmVGT_ESGS_RING_SIZE
6937          */
6938         switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
6939         case IP_VERSION(10, 3, 0):
6940         case IP_VERSION(10, 3, 2):
6941         case IP_VERSION(10, 3, 4):
6942         case IP_VERSION(10, 3, 5):
6943                 data = RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid);
6944                 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid, 0);
6945                 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_UMD, pattern);
6946
6947                 if (RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid) == pattern) {
6948                         WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_UMD, data);
6949                         return true;
6950                 }
6951                 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid, data);
6952                 break;
6953         case IP_VERSION(10, 3, 1):
6954         case IP_VERSION(10, 3, 3):
6955         case IP_VERSION(10, 3, 6):
6956         case IP_VERSION(10, 3, 7):
6957                 return true;
6958         default:
6959                 data = RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE);
6960                 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE, 0);
6961                 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_UMD, pattern);
6962
6963                 if (RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE) == pattern) {
6964                         WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_UMD, data);
6965                         return true;
6966                 }
6967                 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE, data);
6968                 break;
6969         }
6970
6971         return false;
6972 }
6973
6974 static void gfx_v10_0_setup_grbm_cam_remapping(struct amdgpu_device *adev)
6975 {
6976         uint32_t data;
6977
6978         if (amdgpu_sriov_vf(adev))
6979                 return;
6980
6981         /*
6982          * Initialize cam_index to 0
6983          * index will auto-inc after each data writing
6984          */
6985         WREG32_SOC15(GC, 0, mmGRBM_CAM_INDEX, 0);
6986
6987         switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
6988         case IP_VERSION(10, 3, 0):
6989         case IP_VERSION(10, 3, 2):
6990         case IP_VERSION(10, 3, 1):
6991         case IP_VERSION(10, 3, 4):
6992         case IP_VERSION(10, 3, 5):
6993         case IP_VERSION(10, 3, 6):
6994         case IP_VERSION(10, 3, 3):
6995         case IP_VERSION(10, 3, 7):
6996                 /* mmVGT_TF_RING_SIZE_UMD -> mmVGT_TF_RING_SIZE */
6997                 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE_UMD) <<
6998                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
6999                        (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE_Sienna_Cichlid) <<
7000                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7001                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7002                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7003
7004                 /* mmVGT_TF_MEMORY_BASE_UMD -> mmVGT_TF_MEMORY_BASE */
7005                 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_UMD) <<
7006                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7007                        (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_Sienna_Cichlid) <<
7008                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7009                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7010                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7011
7012                 /* mmVGT_TF_MEMORY_BASE_HI_UMD -> mmVGT_TF_MEMORY_BASE_HI */
7013                 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI_UMD) <<
7014                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7015                        (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI_Sienna_Cichlid) <<
7016                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7017                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7018                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7019
7020                 /* mmVGT_HS_OFFCHIP_PARAM_UMD -> mmVGT_HS_OFFCHIP_PARAM */
7021                 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM_UMD) <<
7022                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7023                        (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM_Sienna_Cichlid) <<
7024                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7025                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7026                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7027
7028                 /* mmVGT_ESGS_RING_SIZE_UMD -> mmVGT_ESGS_RING_SIZE */
7029                 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE_UMD) <<
7030                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7031                        (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid) <<
7032                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7033                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7034                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7035
7036                 /* mmVGT_GSVS_RING_SIZE_UMD -> mmVGT_GSVS_RING_SIZE */
7037                 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE_UMD) <<
7038                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7039                        (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE_Sienna_Cichlid) <<
7040                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7041                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7042                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7043
7044                 /* mmSPI_CONFIG_CNTL_REMAP -> mmSPI_CONFIG_CNTL */
7045                 data = (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL_REMAP) <<
7046                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7047                        (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL_Sienna_Cichlid) <<
7048                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7049                 break;
7050         default:
7051                 /* mmVGT_TF_RING_SIZE_UMD -> mmVGT_TF_RING_SIZE */
7052                 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE_UMD) <<
7053                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7054                        (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE) <<
7055                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7056                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7057                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7058
7059                 /* mmVGT_TF_MEMORY_BASE_UMD -> mmVGT_TF_MEMORY_BASE */
7060                 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_UMD) <<
7061                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7062                        (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE) <<
7063                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7064                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7065                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7066
7067                 /* mmVGT_TF_MEMORY_BASE_HI_UMD -> mmVGT_TF_MEMORY_BASE_HI */
7068                 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI_UMD) <<
7069                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7070                        (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI) <<
7071                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7072                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7073                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7074
7075                 /* mmVGT_HS_OFFCHIP_PARAM_UMD -> mmVGT_HS_OFFCHIP_PARAM */
7076                 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM_UMD) <<
7077                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7078                        (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM) <<
7079                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7080                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7081                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7082
7083                 /* mmVGT_ESGS_RING_SIZE_UMD -> mmVGT_ESGS_RING_SIZE */
7084                 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE_UMD) <<
7085                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7086                        (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE) <<
7087                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7088                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7089                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7090
7091                 /* mmVGT_GSVS_RING_SIZE_UMD -> mmVGT_GSVS_RING_SIZE */
7092                 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE_UMD) <<
7093                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7094                        (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE) <<
7095                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7096                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7097                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7098
7099                 /* mmSPI_CONFIG_CNTL_REMAP -> mmSPI_CONFIG_CNTL */
7100                 data = (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL_REMAP) <<
7101                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7102                        (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL) <<
7103                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7104                 break;
7105         }
7106
7107         WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7108         WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7109 }
7110
7111 static void gfx_v10_0_disable_gpa_mode(struct amdgpu_device *adev)
7112 {
7113         uint32_t data;
7114
7115         data = RREG32_SOC15(GC, 0, mmCPC_PSP_DEBUG);
7116         data |= CPC_PSP_DEBUG__GPA_OVERRIDE_MASK;
7117         WREG32_SOC15(GC, 0, mmCPC_PSP_DEBUG, data);
7118
7119         data = RREG32_SOC15(GC, 0, mmCPG_PSP_DEBUG);
7120         data |= CPG_PSP_DEBUG__GPA_OVERRIDE_MASK;
7121         WREG32_SOC15(GC, 0, mmCPG_PSP_DEBUG, data);
7122 }
7123
7124 static int gfx_v10_0_hw_init(void *handle)
7125 {
7126         int r;
7127         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7128
7129         if (!amdgpu_emu_mode)
7130                 gfx_v10_0_init_golden_registers(adev);
7131
7132         if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
7133                 /**
7134                  * For gfx 10, rlc firmware loading relies on smu firmware is
7135                  * loaded firstly, so in direct type, it has to load smc ucode
7136                  * here before rlc.
7137                  */
7138                 if (!(adev->flags & AMD_IS_APU)) {
7139                         r = amdgpu_pm_load_smu_firmware(adev, NULL);
7140                         if (r)
7141                                 return r;
7142                 }
7143                 gfx_v10_0_disable_gpa_mode(adev);
7144         }
7145
7146         /* if GRBM CAM not remapped, set up the remapping */
7147         if (!gfx_v10_0_check_grbm_cam_remapping(adev))
7148                 gfx_v10_0_setup_grbm_cam_remapping(adev);
7149
7150         gfx_v10_0_constants_init(adev);
7151
7152         r = gfx_v10_0_rlc_resume(adev);
7153         if (r)
7154                 return r;
7155
7156         /*
7157          * init golden registers and rlc resume may override some registers,
7158          * reconfig them here
7159          */
7160         if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(10, 1, 10) ||
7161             amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(10, 1, 1) ||
7162             amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(10, 1, 2))
7163                 gfx_v10_0_tcp_harvest(adev);
7164
7165         r = gfx_v10_0_cp_resume(adev);
7166         if (r)
7167                 return r;
7168
7169         if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(10, 3, 0))
7170                 gfx_v10_3_program_pbb_mode(adev);
7171
7172         if (amdgpu_ip_version(adev, GC_HWIP, 0) >= IP_VERSION(10, 3, 0))
7173                 gfx_v10_3_set_power_brake_sequence(adev);
7174
7175         return r;
7176 }
7177
7178 static int gfx_v10_0_hw_fini(void *handle)
7179 {
7180         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7181
7182         amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0);
7183         amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0);
7184
7185         /* WA added for Vangogh asic fixing the SMU suspend failure
7186          * It needs to set power gating again during gfxoff control
7187          * otherwise the gfxoff disallowing will be failed to set.
7188          */
7189         if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(10, 3, 1))
7190                 gfx_v10_0_set_powergating_state(handle, AMD_PG_STATE_UNGATE);
7191
7192         if (!adev->no_hw_access) {
7193                 if (amdgpu_async_gfx_ring) {
7194                         if (amdgpu_gfx_disable_kgq(adev, 0))
7195                                 DRM_ERROR("KGQ disable failed\n");
7196                 }
7197
7198                 if (amdgpu_gfx_disable_kcq(adev, 0))
7199                         DRM_ERROR("KCQ disable failed\n");
7200         }
7201
7202         if (amdgpu_sriov_vf(adev)) {
7203                 gfx_v10_0_cp_gfx_enable(adev, false);
7204                 /* Remove the steps of clearing KIQ position.
7205                  * It causes GFX hang when another Win guest is rendering.
7206                  */
7207                 return 0;
7208         }
7209         gfx_v10_0_cp_enable(adev, false);
7210         gfx_v10_0_enable_gui_idle_interrupt(adev, false);
7211
7212         return 0;
7213 }
7214
7215 static int gfx_v10_0_suspend(void *handle)
7216 {
7217         return gfx_v10_0_hw_fini(handle);
7218 }
7219
7220 static int gfx_v10_0_resume(void *handle)
7221 {
7222         return gfx_v10_0_hw_init(handle);
7223 }
7224
7225 static bool gfx_v10_0_is_idle(void *handle)
7226 {
7227         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7228
7229         if (REG_GET_FIELD(RREG32_SOC15(GC, 0, mmGRBM_STATUS),
7230                                 GRBM_STATUS, GUI_ACTIVE))
7231                 return false;
7232         else
7233                 return true;
7234 }
7235
7236 static int gfx_v10_0_wait_for_idle(void *handle)
7237 {
7238         unsigned int i;
7239         u32 tmp;
7240         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7241
7242         for (i = 0; i < adev->usec_timeout; i++) {
7243                 /* read MC_STATUS */
7244                 tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS) &
7245                         GRBM_STATUS__GUI_ACTIVE_MASK;
7246
7247                 if (!REG_GET_FIELD(tmp, GRBM_STATUS, GUI_ACTIVE))
7248                         return 0;
7249                 udelay(1);
7250         }
7251         return -ETIMEDOUT;
7252 }
7253
7254 static int gfx_v10_0_soft_reset(void *handle)
7255 {
7256         u32 grbm_soft_reset = 0;
7257         u32 tmp;
7258         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7259
7260         /* GRBM_STATUS */
7261         tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS);
7262         if (tmp & (GRBM_STATUS__PA_BUSY_MASK | GRBM_STATUS__SC_BUSY_MASK |
7263                    GRBM_STATUS__BCI_BUSY_MASK | GRBM_STATUS__SX_BUSY_MASK |
7264                    GRBM_STATUS__TA_BUSY_MASK | GRBM_STATUS__DB_BUSY_MASK |
7265                    GRBM_STATUS__CB_BUSY_MASK | GRBM_STATUS__GDS_BUSY_MASK |
7266                    GRBM_STATUS__SPI_BUSY_MASK | GRBM_STATUS__GE_BUSY_NO_DMA_MASK)) {
7267                 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
7268                                                 GRBM_SOFT_RESET, SOFT_RESET_CP,
7269                                                 1);
7270                 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
7271                                                 GRBM_SOFT_RESET, SOFT_RESET_GFX,
7272                                                 1);
7273         }
7274
7275         if (tmp & (GRBM_STATUS__CP_BUSY_MASK | GRBM_STATUS__CP_COHERENCY_BUSY_MASK)) {
7276                 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
7277                                                 GRBM_SOFT_RESET, SOFT_RESET_CP,
7278                                                 1);
7279         }
7280
7281         /* GRBM_STATUS2 */
7282         tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS2);
7283         switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
7284         case IP_VERSION(10, 3, 0):
7285         case IP_VERSION(10, 3, 2):
7286         case IP_VERSION(10, 3, 1):
7287         case IP_VERSION(10, 3, 4):
7288         case IP_VERSION(10, 3, 5):
7289         case IP_VERSION(10, 3, 6):
7290         case IP_VERSION(10, 3, 3):
7291                 if (REG_GET_FIELD(tmp, GRBM_STATUS2, RLC_BUSY_Sienna_Cichlid))
7292                         grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
7293                                                         GRBM_SOFT_RESET,
7294                                                         SOFT_RESET_RLC,
7295                                                         1);
7296                 break;
7297         default:
7298                 if (REG_GET_FIELD(tmp, GRBM_STATUS2, RLC_BUSY))
7299                         grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
7300                                                         GRBM_SOFT_RESET,
7301                                                         SOFT_RESET_RLC,
7302                                                         1);
7303                 break;
7304         }
7305
7306         if (grbm_soft_reset) {
7307                 /* stop the rlc */
7308                 gfx_v10_0_rlc_stop(adev);
7309
7310                 /* Disable GFX parsing/prefetching */
7311                 gfx_v10_0_cp_gfx_enable(adev, false);
7312
7313                 /* Disable MEC parsing/prefetching */
7314                 gfx_v10_0_cp_compute_enable(adev, false);
7315
7316                 if (grbm_soft_reset) {
7317                         tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);
7318                         tmp |= grbm_soft_reset;
7319                         dev_info(adev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp);
7320                         WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp);
7321                         tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);
7322
7323                         udelay(50);
7324
7325                         tmp &= ~grbm_soft_reset;
7326                         WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp);
7327                         tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);
7328                 }
7329
7330                 /* Wait a little for things to settle down */
7331                 udelay(50);
7332         }
7333         return 0;
7334 }
7335
7336 static uint64_t gfx_v10_0_get_gpu_clock_counter(struct amdgpu_device *adev)
7337 {
7338         uint64_t clock, clock_lo, clock_hi, hi_check;
7339
7340         switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
7341         case IP_VERSION(10, 1, 3):
7342         case IP_VERSION(10, 1, 4):
7343                 preempt_disable();
7344                 clock_hi = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER_Cyan_Skillfish);
7345                 clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER_Cyan_Skillfish);
7346                 hi_check = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER_Cyan_Skillfish);
7347                 /* The SMUIO TSC clock frequency is 100MHz, which sets 32-bit carry over
7348                  * roughly every 42 seconds.
7349                  */
7350                 if (hi_check != clock_hi) {
7351                         clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER_Cyan_Skillfish);
7352                         clock_hi = hi_check;
7353                 }
7354                 preempt_enable();
7355                 clock = clock_lo | (clock_hi << 32ULL);
7356                 break;
7357         case IP_VERSION(10, 3, 1):
7358         case IP_VERSION(10, 3, 3):
7359         case IP_VERSION(10, 3, 7):
7360                 preempt_disable();
7361                 clock_hi = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER_Vangogh);
7362                 clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER_Vangogh);
7363                 hi_check = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER_Vangogh);
7364                 /* The SMUIO TSC clock frequency is 100MHz, which sets 32-bit carry over
7365                  * roughly every 42 seconds.
7366                  */
7367                 if (hi_check != clock_hi) {
7368                         clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER_Vangogh);
7369                         clock_hi = hi_check;
7370                 }
7371                 preempt_enable();
7372                 clock = clock_lo | (clock_hi << 32ULL);
7373                 break;
7374         case IP_VERSION(10, 3, 6):
7375                 preempt_disable();
7376                 clock_hi = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER_GC_10_3_6);
7377                 clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER_GC_10_3_6);
7378                 hi_check = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER_GC_10_3_6);
7379                 /* The SMUIO TSC clock frequency is 100MHz, which sets 32-bit carry over
7380                  * roughly every 42 seconds.
7381                  */
7382                 if (hi_check != clock_hi) {
7383                         clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER_GC_10_3_6);
7384                         clock_hi = hi_check;
7385                 }
7386                 preempt_enable();
7387                 clock = clock_lo | (clock_hi << 32ULL);
7388                 break;
7389         default:
7390                 preempt_disable();
7391                 clock_hi = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER);
7392                 clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER);
7393                 hi_check = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER);
7394                 /* The SMUIO TSC clock frequency is 100MHz, which sets 32-bit carry over
7395                  * roughly every 42 seconds.
7396                  */
7397                 if (hi_check != clock_hi) {
7398                         clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER);
7399                         clock_hi = hi_check;
7400                 }
7401                 preempt_enable();
7402                 clock = clock_lo | (clock_hi << 32ULL);
7403                 break;
7404         }
7405         return clock;
7406 }
7407
7408 static void gfx_v10_0_ring_emit_gds_switch(struct amdgpu_ring *ring,
7409                                            uint32_t vmid,
7410                                            uint32_t gds_base, uint32_t gds_size,
7411                                            uint32_t gws_base, uint32_t gws_size,
7412                                            uint32_t oa_base, uint32_t oa_size)
7413 {
7414         struct amdgpu_device *adev = ring->adev;
7415
7416         /* GDS Base */
7417         gfx_v10_0_write_data_to_reg(ring, 0, false,
7418                                     SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_BASE) + 2 * vmid,
7419                                     gds_base);
7420
7421         /* GDS Size */
7422         gfx_v10_0_write_data_to_reg(ring, 0, false,
7423                                     SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_SIZE) + 2 * vmid,
7424                                     gds_size);
7425
7426         /* GWS */
7427         gfx_v10_0_write_data_to_reg(ring, 0, false,
7428                                     SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID0) + vmid,
7429                                     gws_size << GDS_GWS_VMID0__SIZE__SHIFT | gws_base);
7430
7431         /* OA */
7432         gfx_v10_0_write_data_to_reg(ring, 0, false,
7433                                     SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID0) + vmid,
7434                                     (1 << (oa_size + oa_base)) - (1 << oa_base));
7435 }
7436
7437 static int gfx_v10_0_early_init(void *handle)
7438 {
7439         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7440
7441         adev->gfx.funcs = &gfx_v10_0_gfx_funcs;
7442
7443         switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
7444         case IP_VERSION(10, 1, 10):
7445         case IP_VERSION(10, 1, 1):
7446         case IP_VERSION(10, 1, 2):
7447         case IP_VERSION(10, 1, 3):
7448         case IP_VERSION(10, 1, 4):
7449                 adev->gfx.num_gfx_rings = GFX10_NUM_GFX_RINGS_NV1X;
7450                 break;
7451         case IP_VERSION(10, 3, 0):
7452         case IP_VERSION(10, 3, 2):
7453         case IP_VERSION(10, 3, 1):
7454         case IP_VERSION(10, 3, 4):
7455         case IP_VERSION(10, 3, 5):
7456         case IP_VERSION(10, 3, 6):
7457         case IP_VERSION(10, 3, 3):
7458         case IP_VERSION(10, 3, 7):
7459                 adev->gfx.num_gfx_rings = GFX10_NUM_GFX_RINGS_Sienna_Cichlid;
7460                 break;
7461         default:
7462                 break;
7463         }
7464
7465         adev->gfx.num_compute_rings = min(amdgpu_gfx_get_num_kcq(adev),
7466                                           AMDGPU_MAX_COMPUTE_RINGS);
7467
7468         gfx_v10_0_set_kiq_pm4_funcs(adev);
7469         gfx_v10_0_set_ring_funcs(adev);
7470         gfx_v10_0_set_irq_funcs(adev);
7471         gfx_v10_0_set_gds_init(adev);
7472         gfx_v10_0_set_rlc_funcs(adev);
7473         gfx_v10_0_set_mqd_funcs(adev);
7474
7475         /* init rlcg reg access ctrl */
7476         gfx_v10_0_init_rlcg_reg_access_ctrl(adev);
7477
7478         return gfx_v10_0_init_microcode(adev);
7479 }
7480
7481 static int gfx_v10_0_late_init(void *handle)
7482 {
7483         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7484         int r;
7485
7486         r = amdgpu_irq_get(adev, &adev->gfx.priv_reg_irq, 0);
7487         if (r)
7488                 return r;
7489
7490         r = amdgpu_irq_get(adev, &adev->gfx.priv_inst_irq, 0);
7491         if (r)
7492                 return r;
7493
7494         return 0;
7495 }
7496
7497 static bool gfx_v10_0_is_rlc_enabled(struct amdgpu_device *adev)
7498 {
7499         uint32_t rlc_cntl;
7500
7501         /* if RLC is not enabled, do nothing */
7502         rlc_cntl = RREG32_SOC15(GC, 0, mmRLC_CNTL);
7503         return (REG_GET_FIELD(rlc_cntl, RLC_CNTL, RLC_ENABLE_F32)) ? true : false;
7504 }
7505
7506 static void gfx_v10_0_set_safe_mode(struct amdgpu_device *adev, int xcc_id)
7507 {
7508         uint32_t data;
7509         unsigned int i;
7510
7511         data = RLC_SAFE_MODE__CMD_MASK;
7512         data |= (1 << RLC_SAFE_MODE__MESSAGE__SHIFT);
7513
7514         switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
7515         case IP_VERSION(10, 3, 0):
7516         case IP_VERSION(10, 3, 2):
7517         case IP_VERSION(10, 3, 1):
7518         case IP_VERSION(10, 3, 4):
7519         case IP_VERSION(10, 3, 5):
7520         case IP_VERSION(10, 3, 6):
7521         case IP_VERSION(10, 3, 3):
7522         case IP_VERSION(10, 3, 7):
7523                 WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE_Sienna_Cichlid, data);
7524
7525                 /* wait for RLC_SAFE_MODE */
7526                 for (i = 0; i < adev->usec_timeout; i++) {
7527                         if (!REG_GET_FIELD(RREG32_SOC15(GC, 0, mmRLC_SAFE_MODE_Sienna_Cichlid),
7528                                            RLC_SAFE_MODE, CMD))
7529                                 break;
7530                         udelay(1);
7531                 }
7532                 break;
7533         default:
7534                 WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE, data);
7535
7536                 /* wait for RLC_SAFE_MODE */
7537                 for (i = 0; i < adev->usec_timeout; i++) {
7538                         if (!REG_GET_FIELD(RREG32_SOC15(GC, 0, mmRLC_SAFE_MODE),
7539                                            RLC_SAFE_MODE, CMD))
7540                                 break;
7541                         udelay(1);
7542                 }
7543                 break;
7544         }
7545 }
7546
7547 static void gfx_v10_0_unset_safe_mode(struct amdgpu_device *adev, int xcc_id)
7548 {
7549         uint32_t data;
7550
7551         data = RLC_SAFE_MODE__CMD_MASK;
7552         switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
7553         case IP_VERSION(10, 3, 0):
7554         case IP_VERSION(10, 3, 2):
7555         case IP_VERSION(10, 3, 1):
7556         case IP_VERSION(10, 3, 4):
7557         case IP_VERSION(10, 3, 5):
7558         case IP_VERSION(10, 3, 6):
7559         case IP_VERSION(10, 3, 3):
7560         case IP_VERSION(10, 3, 7):
7561                 WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE_Sienna_Cichlid, data);
7562                 break;
7563         default:
7564                 WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE, data);
7565                 break;
7566         }
7567 }
7568
7569 static void gfx_v10_0_update_medium_grain_clock_gating(struct amdgpu_device *adev,
7570                                                       bool enable)
7571 {
7572         uint32_t data, def;
7573
7574         if (!(adev->cg_flags & (AMD_CG_SUPPORT_GFX_MGCG | AMD_CG_SUPPORT_GFX_MGLS)))
7575                 return;
7576
7577         /* It is disabled by HW by default */
7578         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) {
7579                 /* 0 - Disable some blocks' MGCG */
7580                 WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, 0xe0000000);
7581                 WREG32_SOC15(GC, 0, mmCGTT_WD_CLK_CTRL, 0xff000000);
7582                 WREG32_SOC15(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xff000000);
7583                 WREG32_SOC15(GC, 0, mmCGTT_IA_CLK_CTRL, 0xff000000);
7584
7585                 /* 1 - RLC_CGTT_MGCG_OVERRIDE */
7586                 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
7587                 data &= ~(RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK |
7588                           RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK |
7589                           RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK |
7590                           RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK |
7591                           RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK |
7592                           RLC_CGTT_MGCG_OVERRIDE__ENABLE_CGTS_LEGACY_MASK);
7593
7594                 if (def != data)
7595                         WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
7596
7597                 /* MGLS is a global flag to control all MGLS in GFX */
7598                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGLS) {
7599                         /* 2 - RLC memory Light sleep */
7600                         if (adev->cg_flags & AMD_CG_SUPPORT_GFX_RLC_LS) {
7601                                 def = data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL);
7602                                 data |= RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK;
7603                                 if (def != data)
7604                                         WREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL, data);
7605                         }
7606                         /* 3 - CP memory Light sleep */
7607                         if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CP_LS) {
7608                                 def = data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL);
7609                                 data |= CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK;
7610                                 if (def != data)
7611                                         WREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL, data);
7612                         }
7613                 }
7614         } else if (!enable || !(adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) {
7615                 /* 1 - MGCG_OVERRIDE */
7616                 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
7617                 data |= (RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK |
7618                          RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK |
7619                          RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK |
7620                          RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK |
7621                          RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK |
7622                          RLC_CGTT_MGCG_OVERRIDE__ENABLE_CGTS_LEGACY_MASK);
7623                 if (def != data)
7624                         WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
7625
7626                 /* 2 - disable MGLS in CP */
7627                 data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL);
7628                 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) {
7629                         data &= ~CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK;
7630                         WREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL, data);
7631                 }
7632
7633                 /* 3 - disable MGLS in RLC */
7634                 data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL);
7635                 if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK) {
7636                         data &= ~RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK;
7637                         WREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL, data);
7638                 }
7639
7640         }
7641 }
7642
7643 static void gfx_v10_0_update_3d_clock_gating(struct amdgpu_device *adev,
7644                                            bool enable)
7645 {
7646         uint32_t data, def;
7647
7648         if (!(adev->cg_flags & (AMD_CG_SUPPORT_GFX_3D_CGCG | AMD_CG_SUPPORT_GFX_3D_CGLS)))
7649                 return;
7650
7651         /* Enable 3D CGCG/CGLS */
7652         if (enable) {
7653                 /* write cmd to clear cgcg/cgls ov */
7654                 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
7655
7656                 /* unset CGCG override */
7657                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG)
7658                         data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_GFX3D_CG_OVERRIDE_MASK;
7659
7660                 /* update CGCG and CGLS override bits */
7661                 if (def != data)
7662                         WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
7663
7664                 /* enable 3Dcgcg FSM(0x0000363f) */
7665                 def = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D);
7666                 data = 0;
7667
7668                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG)
7669                         data = (0x36 << RLC_CGCG_CGLS_CTRL_3D__CGCG_GFX_IDLE_THRESHOLD__SHIFT) |
7670                                 RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK;
7671
7672                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS)
7673                         data |= (0x000F << RLC_CGCG_CGLS_CTRL_3D__CGLS_REP_COMPANSAT_DELAY__SHIFT) |
7674                                 RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK;
7675
7676                 if (def != data)
7677                         WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D, data);
7678
7679                 /* set IDLE_POLL_COUNT(0x00900100) */
7680                 def = RREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL);
7681                 data = (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) |
7682                         (0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT);
7683                 if (def != data)
7684                         WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL, data);
7685         } else {
7686                 /* Disable CGCG/CGLS */
7687                 def = data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D);
7688
7689                 /* disable cgcg, cgls should be disabled */
7690                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG)
7691                         data &= ~RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK;
7692
7693                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS)
7694                         data &= ~RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK;
7695
7696                 /* disable cgcg and cgls in FSM */
7697                 if (def != data)
7698                         WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D, data);
7699         }
7700 }
7701
7702 static void gfx_v10_0_update_coarse_grain_clock_gating(struct amdgpu_device *adev,
7703                                                       bool enable)
7704 {
7705         uint32_t def, data;
7706
7707         if (!(adev->cg_flags & (AMD_CG_SUPPORT_GFX_CGCG | AMD_CG_SUPPORT_GFX_CGLS)))
7708                 return;
7709
7710         if (enable) {
7711                 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
7712
7713                 /* unset CGCG override */
7714                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)
7715                         data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGCG_OVERRIDE_MASK;
7716
7717                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS)
7718                         data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK;
7719
7720                 /* update CGCG and CGLS override bits */
7721                 if (def != data)
7722                         WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
7723
7724                 /* enable cgcg FSM(0x0000363F) */
7725                 def = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL);
7726                 data = 0;
7727
7728                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)
7729                         data = (0x36 << RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT) |
7730                                 RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK;
7731
7732                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS)
7733                         data |= (0x000F << RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY__SHIFT) |
7734                                 RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK;
7735
7736                 if (def != data)
7737                         WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, data);
7738
7739                 /* set IDLE_POLL_COUNT(0x00900100) */
7740                 def = RREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL);
7741                 data = (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) |
7742                         (0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT);
7743                 if (def != data)
7744                         WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL, data);
7745         } else {
7746                 def = data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL);
7747
7748                 /* reset CGCG/CGLS bits */
7749                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)
7750                         data &= ~RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK;
7751
7752                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS)
7753                         data &= ~RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK;
7754
7755                 /* disable cgcg and cgls in FSM */
7756                 if (def != data)
7757                         WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, data);
7758         }
7759 }
7760
7761 static void gfx_v10_0_update_fine_grain_clock_gating(struct amdgpu_device *adev,
7762                                                       bool enable)
7763 {
7764         uint32_t def, data;
7765
7766         if (!(adev->cg_flags & AMD_CG_SUPPORT_GFX_FGCG))
7767                 return;
7768
7769         if (enable) {
7770                 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
7771                 /* unset FGCG override */
7772                 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK;
7773                 /* update FGCG override bits */
7774                 if (def != data)
7775                         WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
7776
7777                 def = data = RREG32_SOC15(GC, 0, mmRLC_CLK_CNTL);
7778                 /* unset RLC SRAM CLK GATER override */
7779                 data &= ~RLC_CLK_CNTL__RLC_SRAM_CLK_GATER_OVERRIDE_MASK;
7780                 /* update RLC SRAM CLK GATER override bits */
7781                 if (def != data)
7782                         WREG32_SOC15(GC, 0, mmRLC_CLK_CNTL, data);
7783         } else {
7784                 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
7785                 /* reset FGCG bits */
7786                 data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK;
7787                 /* disable FGCG*/
7788                 if (def != data)
7789                         WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
7790
7791                 def = data = RREG32_SOC15(GC, 0, mmRLC_CLK_CNTL);
7792                 /* reset RLC SRAM CLK GATER bits */
7793                 data |= RLC_CLK_CNTL__RLC_SRAM_CLK_GATER_OVERRIDE_MASK;
7794                 /* disable RLC SRAM CLK*/
7795                 if (def != data)
7796                         WREG32_SOC15(GC, 0, mmRLC_CLK_CNTL, data);
7797         }
7798 }
7799
7800 static void gfx_v10_0_apply_medium_grain_clock_gating_workaround(struct amdgpu_device *adev)
7801 {
7802         uint32_t reg_data = 0;
7803         uint32_t reg_idx = 0;
7804         uint32_t i;
7805
7806         const uint32_t tcp_ctrl_regs[] = {
7807                 mmCGTS_SA0_WGP00_CU0_TCP_CTRL_REG,
7808                 mmCGTS_SA0_WGP00_CU1_TCP_CTRL_REG,
7809                 mmCGTS_SA0_WGP01_CU0_TCP_CTRL_REG,
7810                 mmCGTS_SA0_WGP01_CU1_TCP_CTRL_REG,
7811                 mmCGTS_SA0_WGP02_CU0_TCP_CTRL_REG,
7812                 mmCGTS_SA0_WGP02_CU1_TCP_CTRL_REG,
7813                 mmCGTS_SA0_WGP10_CU0_TCP_CTRL_REG,
7814                 mmCGTS_SA0_WGP10_CU1_TCP_CTRL_REG,
7815                 mmCGTS_SA0_WGP11_CU0_TCP_CTRL_REG,
7816                 mmCGTS_SA0_WGP11_CU1_TCP_CTRL_REG,
7817                 mmCGTS_SA0_WGP12_CU0_TCP_CTRL_REG,
7818                 mmCGTS_SA0_WGP12_CU1_TCP_CTRL_REG,
7819                 mmCGTS_SA1_WGP00_CU0_TCP_CTRL_REG,
7820                 mmCGTS_SA1_WGP00_CU1_TCP_CTRL_REG,
7821                 mmCGTS_SA1_WGP01_CU0_TCP_CTRL_REG,
7822                 mmCGTS_SA1_WGP01_CU1_TCP_CTRL_REG,
7823                 mmCGTS_SA1_WGP02_CU0_TCP_CTRL_REG,
7824                 mmCGTS_SA1_WGP02_CU1_TCP_CTRL_REG,
7825                 mmCGTS_SA1_WGP10_CU0_TCP_CTRL_REG,
7826                 mmCGTS_SA1_WGP10_CU1_TCP_CTRL_REG,
7827                 mmCGTS_SA1_WGP11_CU0_TCP_CTRL_REG,
7828                 mmCGTS_SA1_WGP11_CU1_TCP_CTRL_REG,
7829                 mmCGTS_SA1_WGP12_CU0_TCP_CTRL_REG,
7830                 mmCGTS_SA1_WGP12_CU1_TCP_CTRL_REG
7831         };
7832
7833         const uint32_t tcp_ctrl_regs_nv12[] = {
7834                 mmCGTS_SA0_WGP00_CU0_TCP_CTRL_REG,
7835                 mmCGTS_SA0_WGP00_CU1_TCP_CTRL_REG,
7836                 mmCGTS_SA0_WGP01_CU0_TCP_CTRL_REG,
7837                 mmCGTS_SA0_WGP01_CU1_TCP_CTRL_REG,
7838                 mmCGTS_SA0_WGP02_CU0_TCP_CTRL_REG,
7839                 mmCGTS_SA0_WGP02_CU1_TCP_CTRL_REG,
7840                 mmCGTS_SA0_WGP10_CU0_TCP_CTRL_REG,
7841                 mmCGTS_SA0_WGP10_CU1_TCP_CTRL_REG,
7842                 mmCGTS_SA0_WGP11_CU0_TCP_CTRL_REG,
7843                 mmCGTS_SA0_WGP11_CU1_TCP_CTRL_REG,
7844                 mmCGTS_SA1_WGP00_CU0_TCP_CTRL_REG,
7845                 mmCGTS_SA1_WGP00_CU1_TCP_CTRL_REG,
7846                 mmCGTS_SA1_WGP01_CU0_TCP_CTRL_REG,
7847                 mmCGTS_SA1_WGP01_CU1_TCP_CTRL_REG,
7848                 mmCGTS_SA1_WGP02_CU0_TCP_CTRL_REG,
7849                 mmCGTS_SA1_WGP02_CU1_TCP_CTRL_REG,
7850                 mmCGTS_SA1_WGP10_CU0_TCP_CTRL_REG,
7851                 mmCGTS_SA1_WGP10_CU1_TCP_CTRL_REG,
7852                 mmCGTS_SA1_WGP11_CU0_TCP_CTRL_REG,
7853                 mmCGTS_SA1_WGP11_CU1_TCP_CTRL_REG,
7854         };
7855
7856         const uint32_t sm_ctlr_regs[] = {
7857                 mmCGTS_SA0_QUAD0_SM_CTRL_REG,
7858                 mmCGTS_SA0_QUAD1_SM_CTRL_REG,
7859                 mmCGTS_SA1_QUAD0_SM_CTRL_REG,
7860                 mmCGTS_SA1_QUAD1_SM_CTRL_REG
7861         };
7862
7863         if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(10, 1, 2)) {
7864                 for (i = 0; i < ARRAY_SIZE(tcp_ctrl_regs_nv12); i++) {
7865                         reg_idx = adev->reg_offset[GC_HWIP][0][mmCGTS_SA0_WGP00_CU0_TCP_CTRL_REG_BASE_IDX] +
7866                                   tcp_ctrl_regs_nv12[i];
7867                         reg_data = RREG32(reg_idx);
7868                         reg_data |= CGTS_SA0_WGP00_CU0_TCP_CTRL_REG__TCPI_LS_OVERRIDE_MASK;
7869                         WREG32(reg_idx, reg_data);
7870                 }
7871         } else {
7872                 for (i = 0; i < ARRAY_SIZE(tcp_ctrl_regs); i++) {
7873                         reg_idx = adev->reg_offset[GC_HWIP][0][mmCGTS_SA0_WGP00_CU0_TCP_CTRL_REG_BASE_IDX] +
7874                                   tcp_ctrl_regs[i];
7875                         reg_data = RREG32(reg_idx);
7876                         reg_data |= CGTS_SA0_WGP00_CU0_TCP_CTRL_REG__TCPI_LS_OVERRIDE_MASK;
7877                         WREG32(reg_idx, reg_data);
7878                 }
7879         }
7880
7881         for (i = 0; i < ARRAY_SIZE(sm_ctlr_regs); i++) {
7882                 reg_idx = adev->reg_offset[GC_HWIP][0][mmCGTS_SA0_QUAD0_SM_CTRL_REG_BASE_IDX] +
7883                           sm_ctlr_regs[i];
7884                 reg_data = RREG32(reg_idx);
7885                 reg_data &= ~CGTS_SA0_QUAD0_SM_CTRL_REG__SM_MODE_MASK;
7886                 reg_data |= 2 << CGTS_SA0_QUAD0_SM_CTRL_REG__SM_MODE__SHIFT;
7887                 WREG32(reg_idx, reg_data);
7888         }
7889 }
7890
7891 static int gfx_v10_0_update_gfx_clock_gating(struct amdgpu_device *adev,
7892                                             bool enable)
7893 {
7894         amdgpu_gfx_rlc_enter_safe_mode(adev, 0);
7895
7896         if (enable) {
7897                 /* enable FGCG firstly*/
7898                 gfx_v10_0_update_fine_grain_clock_gating(adev, enable);
7899                 /* CGCG/CGLS should be enabled after MGCG/MGLS
7900                  * ===  MGCG + MGLS ===
7901                  */
7902                 gfx_v10_0_update_medium_grain_clock_gating(adev, enable);
7903                 /* ===  CGCG /CGLS for GFX 3D Only === */
7904                 gfx_v10_0_update_3d_clock_gating(adev, enable);
7905                 /* ===  CGCG + CGLS === */
7906                 gfx_v10_0_update_coarse_grain_clock_gating(adev, enable);
7907
7908                 if ((amdgpu_ip_version(adev, GC_HWIP, 0) ==
7909                      IP_VERSION(10, 1, 10)) ||
7910                     (amdgpu_ip_version(adev, GC_HWIP, 0) ==
7911                      IP_VERSION(10, 1, 1)) ||
7912                     (amdgpu_ip_version(adev, GC_HWIP, 0) ==
7913                      IP_VERSION(10, 1, 2)))
7914                         gfx_v10_0_apply_medium_grain_clock_gating_workaround(adev);
7915         } else {
7916                 /* CGCG/CGLS should be disabled before MGCG/MGLS
7917                  * ===  CGCG + CGLS ===
7918                  */
7919                 gfx_v10_0_update_coarse_grain_clock_gating(adev, enable);
7920                 /* ===  CGCG /CGLS for GFX 3D Only === */
7921                 gfx_v10_0_update_3d_clock_gating(adev, enable);
7922                 /* ===  MGCG + MGLS === */
7923                 gfx_v10_0_update_medium_grain_clock_gating(adev, enable);
7924                 /* disable fgcg at last*/
7925                 gfx_v10_0_update_fine_grain_clock_gating(adev, enable);
7926         }
7927
7928         if (adev->cg_flags &
7929             (AMD_CG_SUPPORT_GFX_MGCG |
7930              AMD_CG_SUPPORT_GFX_CGLS |
7931              AMD_CG_SUPPORT_GFX_CGCG |
7932              AMD_CG_SUPPORT_GFX_3D_CGCG |
7933              AMD_CG_SUPPORT_GFX_3D_CGLS))
7934                 gfx_v10_0_enable_gui_idle_interrupt(adev, enable);
7935
7936         amdgpu_gfx_rlc_exit_safe_mode(adev, 0);
7937
7938         return 0;
7939 }
7940
7941 static void gfx_v10_0_update_spm_vmid_internal(struct amdgpu_device *adev,
7942                                                unsigned int vmid)
7943 {
7944         u32 data;
7945
7946         /* not for *_SOC15 */
7947         data = RREG32_SOC15_NO_KIQ(GC, 0, mmRLC_SPM_MC_CNTL);
7948
7949         data &= ~RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK;
7950         data |= (vmid & RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK) << RLC_SPM_MC_CNTL__RLC_SPM_VMID__SHIFT;
7951
7952         WREG32_SOC15_NO_KIQ(GC, 0, mmRLC_SPM_MC_CNTL, data);
7953 }
7954
7955 static void gfx_v10_0_update_spm_vmid(struct amdgpu_device *adev, unsigned int vmid)
7956 {
7957         amdgpu_gfx_off_ctrl(adev, false);
7958
7959         gfx_v10_0_update_spm_vmid_internal(adev, vmid);
7960
7961         amdgpu_gfx_off_ctrl(adev, true);
7962 }
7963
7964 static bool gfx_v10_0_check_rlcg_range(struct amdgpu_device *adev,
7965                                         uint32_t offset,
7966                                         struct soc15_reg_rlcg *entries, int arr_size)
7967 {
7968         int i;
7969         uint32_t reg;
7970
7971         if (!entries)
7972                 return false;
7973
7974         for (i = 0; i < arr_size; i++) {
7975                 const struct soc15_reg_rlcg *entry;
7976
7977                 entry = &entries[i];
7978                 reg = adev->reg_offset[entry->hwip][entry->instance][entry->segment] + entry->reg;
7979                 if (offset == reg)
7980                         return true;
7981         }
7982
7983         return false;
7984 }
7985
7986 static bool gfx_v10_0_is_rlcg_access_range(struct amdgpu_device *adev, u32 offset)
7987 {
7988         return gfx_v10_0_check_rlcg_range(adev, offset, NULL, 0);
7989 }
7990
7991 static void gfx_v10_cntl_power_gating(struct amdgpu_device *adev, bool enable)
7992 {
7993         u32 data = RREG32_SOC15(GC, 0, mmRLC_PG_CNTL);
7994
7995         if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG))
7996                 data |= RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK;
7997         else
7998                 data &= ~RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK;
7999
8000         WREG32_SOC15(GC, 0, mmRLC_PG_CNTL, data);
8001
8002         /*
8003          * CGPG enablement required and the register to program the hysteresis value
8004          * RLC_PG_DELAY_3.CGCG_ACTIVE_BEFORE_CGPG to the desired CGPG hysteresis value
8005          * in refclk count. Note that RLC FW is modified to take 16 bits from
8006          * RLC_PG_DELAY_3[15:0] as the hysteresis instead of just 8 bits.
8007          *
8008          * The recommendation from RLC team is setting RLC_PG_DELAY_3 to 200us as part)
8009          * of CGPG enablement starting point.
8010          * Power/performance team will optimize it and might give a new value later.
8011          */
8012         if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG)) {
8013                 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
8014                 case IP_VERSION(10, 3, 1):
8015                 case IP_VERSION(10, 3, 3):
8016                 case IP_VERSION(10, 3, 6):
8017                 case IP_VERSION(10, 3, 7):
8018                         data = 0x4E20 & RLC_PG_DELAY_3__CGCG_ACTIVE_BEFORE_CGPG_MASK_Vangogh;
8019                         WREG32_SOC15(GC, 0, mmRLC_PG_DELAY_3, data);
8020                         break;
8021                 default:
8022                         break;
8023                 }
8024         }
8025 }
8026
8027 static void gfx_v10_cntl_pg(struct amdgpu_device *adev, bool enable)
8028 {
8029         amdgpu_gfx_rlc_enter_safe_mode(adev, 0);
8030
8031         gfx_v10_cntl_power_gating(adev, enable);
8032
8033         amdgpu_gfx_rlc_exit_safe_mode(adev, 0);
8034 }
8035
8036 static const struct amdgpu_rlc_funcs gfx_v10_0_rlc_funcs = {
8037         .is_rlc_enabled = gfx_v10_0_is_rlc_enabled,
8038         .set_safe_mode = gfx_v10_0_set_safe_mode,
8039         .unset_safe_mode = gfx_v10_0_unset_safe_mode,
8040         .init = gfx_v10_0_rlc_init,
8041         .get_csb_size = gfx_v10_0_get_csb_size,
8042         .get_csb_buffer = gfx_v10_0_get_csb_buffer,
8043         .resume = gfx_v10_0_rlc_resume,
8044         .stop = gfx_v10_0_rlc_stop,
8045         .reset = gfx_v10_0_rlc_reset,
8046         .start = gfx_v10_0_rlc_start,
8047         .update_spm_vmid = gfx_v10_0_update_spm_vmid,
8048 };
8049
8050 static const struct amdgpu_rlc_funcs gfx_v10_0_rlc_funcs_sriov = {
8051         .is_rlc_enabled = gfx_v10_0_is_rlc_enabled,
8052         .set_safe_mode = gfx_v10_0_set_safe_mode,
8053         .unset_safe_mode = gfx_v10_0_unset_safe_mode,
8054         .init = gfx_v10_0_rlc_init,
8055         .get_csb_size = gfx_v10_0_get_csb_size,
8056         .get_csb_buffer = gfx_v10_0_get_csb_buffer,
8057         .resume = gfx_v10_0_rlc_resume,
8058         .stop = gfx_v10_0_rlc_stop,
8059         .reset = gfx_v10_0_rlc_reset,
8060         .start = gfx_v10_0_rlc_start,
8061         .update_spm_vmid = gfx_v10_0_update_spm_vmid,
8062         .is_rlcg_access_range = gfx_v10_0_is_rlcg_access_range,
8063 };
8064
8065 static int gfx_v10_0_set_powergating_state(void *handle,
8066                                           enum amd_powergating_state state)
8067 {
8068         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
8069         bool enable = (state == AMD_PG_STATE_GATE);
8070
8071         if (amdgpu_sriov_vf(adev))
8072                 return 0;
8073
8074         switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
8075         case IP_VERSION(10, 1, 10):
8076         case IP_VERSION(10, 1, 1):
8077         case IP_VERSION(10, 1, 2):
8078         case IP_VERSION(10, 3, 0):
8079         case IP_VERSION(10, 3, 2):
8080         case IP_VERSION(10, 3, 4):
8081         case IP_VERSION(10, 3, 5):
8082                 amdgpu_gfx_off_ctrl(adev, enable);
8083                 break;
8084         case IP_VERSION(10, 3, 1):
8085         case IP_VERSION(10, 3, 3):
8086         case IP_VERSION(10, 3, 6):
8087         case IP_VERSION(10, 3, 7):
8088                 if (!enable)
8089                         amdgpu_gfx_off_ctrl(adev, false);
8090
8091                 gfx_v10_cntl_pg(adev, enable);
8092
8093                 if (enable)
8094                         amdgpu_gfx_off_ctrl(adev, true);
8095
8096                 break;
8097         default:
8098                 break;
8099         }
8100         return 0;
8101 }
8102
8103 static int gfx_v10_0_set_clockgating_state(void *handle,
8104                                           enum amd_clockgating_state state)
8105 {
8106         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
8107
8108         if (amdgpu_sriov_vf(adev))
8109                 return 0;
8110
8111         switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
8112         case IP_VERSION(10, 1, 10):
8113         case IP_VERSION(10, 1, 1):
8114         case IP_VERSION(10, 1, 2):
8115         case IP_VERSION(10, 3, 0):
8116         case IP_VERSION(10, 3, 2):
8117         case IP_VERSION(10, 3, 1):
8118         case IP_VERSION(10, 3, 4):
8119         case IP_VERSION(10, 3, 5):
8120         case IP_VERSION(10, 3, 6):
8121         case IP_VERSION(10, 3, 3):
8122         case IP_VERSION(10, 3, 7):
8123                 gfx_v10_0_update_gfx_clock_gating(adev,
8124                                                  state == AMD_CG_STATE_GATE);
8125                 break;
8126         default:
8127                 break;
8128         }
8129         return 0;
8130 }
8131
8132 static void gfx_v10_0_get_clockgating_state(void *handle, u64 *flags)
8133 {
8134         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
8135         int data;
8136
8137         /* AMD_CG_SUPPORT_GFX_FGCG */
8138         data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE));
8139         if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK))
8140                 *flags |= AMD_CG_SUPPORT_GFX_FGCG;
8141
8142         /* AMD_CG_SUPPORT_GFX_MGCG */
8143         data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE));
8144         if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK))
8145                 *flags |= AMD_CG_SUPPORT_GFX_MGCG;
8146
8147         /* AMD_CG_SUPPORT_GFX_CGCG */
8148         data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGCG_CGLS_CTRL));
8149         if (data & RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK)
8150                 *flags |= AMD_CG_SUPPORT_GFX_CGCG;
8151
8152         /* AMD_CG_SUPPORT_GFX_CGLS */
8153         if (data & RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK)
8154                 *flags |= AMD_CG_SUPPORT_GFX_CGLS;
8155
8156         /* AMD_CG_SUPPORT_GFX_RLC_LS */
8157         data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_MEM_SLP_CNTL));
8158         if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK)
8159                 *flags |= AMD_CG_SUPPORT_GFX_RLC_LS | AMD_CG_SUPPORT_GFX_MGLS;
8160
8161         /* AMD_CG_SUPPORT_GFX_CP_LS */
8162         data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmCP_MEM_SLP_CNTL));
8163         if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK)
8164                 *flags |= AMD_CG_SUPPORT_GFX_CP_LS | AMD_CG_SUPPORT_GFX_MGLS;
8165
8166         /* AMD_CG_SUPPORT_GFX_3D_CGCG */
8167         data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D));
8168         if (data & RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK)
8169                 *flags |= AMD_CG_SUPPORT_GFX_3D_CGCG;
8170
8171         /* AMD_CG_SUPPORT_GFX_3D_CGLS */
8172         if (data & RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK)
8173                 *flags |= AMD_CG_SUPPORT_GFX_3D_CGLS;
8174 }
8175
8176 static u64 gfx_v10_0_ring_get_rptr_gfx(struct amdgpu_ring *ring)
8177 {
8178         /* gfx10 is 32bit rptr*/
8179         return *(uint32_t *)ring->rptr_cpu_addr;
8180 }
8181
8182 static u64 gfx_v10_0_ring_get_wptr_gfx(struct amdgpu_ring *ring)
8183 {
8184         struct amdgpu_device *adev = ring->adev;
8185         u64 wptr;
8186
8187         /* XXX check if swapping is necessary on BE */
8188         if (ring->use_doorbell) {
8189                 wptr = atomic64_read((atomic64_t *)ring->wptr_cpu_addr);
8190         } else {
8191                 wptr = RREG32_SOC15(GC, 0, mmCP_RB0_WPTR);
8192                 wptr += (u64)RREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI) << 32;
8193         }
8194
8195         return wptr;
8196 }
8197
8198 static void gfx_v10_0_ring_set_wptr_gfx(struct amdgpu_ring *ring)
8199 {
8200         struct amdgpu_device *adev = ring->adev;
8201         uint32_t *wptr_saved;
8202         uint32_t *is_queue_unmap;
8203         uint64_t aggregated_db_index;
8204         uint32_t mqd_size = adev->mqds[AMDGPU_HW_IP_GFX].mqd_size;
8205         uint64_t wptr_tmp;
8206
8207         if (ring->is_mes_queue) {
8208                 wptr_saved = (uint32_t *)(ring->mqd_ptr + mqd_size);
8209                 is_queue_unmap = (uint32_t *)(ring->mqd_ptr + mqd_size +
8210                                               sizeof(uint32_t));
8211                 aggregated_db_index =
8212                         amdgpu_mes_get_aggregated_doorbell_index(adev,
8213                         AMDGPU_MES_PRIORITY_LEVEL_NORMAL);
8214
8215                 wptr_tmp = ring->wptr & ring->buf_mask;
8216                 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, wptr_tmp);
8217                 *wptr_saved = wptr_tmp;
8218                 /* assume doorbell always being used by mes mapped queue */
8219                 if (*is_queue_unmap) {
8220                         WDOORBELL64(aggregated_db_index, wptr_tmp);
8221                         WDOORBELL64(ring->doorbell_index, wptr_tmp);
8222                 } else {
8223                         WDOORBELL64(ring->doorbell_index, wptr_tmp);
8224
8225                         if (*is_queue_unmap)
8226                                 WDOORBELL64(aggregated_db_index, wptr_tmp);
8227                 }
8228         } else {
8229                 if (ring->use_doorbell) {
8230                         /* XXX check if swapping is necessary on BE */
8231                         atomic64_set((atomic64_t *)ring->wptr_cpu_addr,
8232                                      ring->wptr);
8233                         WDOORBELL64(ring->doorbell_index, ring->wptr);
8234                 } else {
8235                         WREG32_SOC15(GC, 0, mmCP_RB0_WPTR,
8236                                      lower_32_bits(ring->wptr));
8237                         WREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI,
8238                                      upper_32_bits(ring->wptr));
8239                 }
8240         }
8241 }
8242
8243 static u64 gfx_v10_0_ring_get_rptr_compute(struct amdgpu_ring *ring)
8244 {
8245         /* gfx10 hardware is 32bit rptr */
8246         return *(uint32_t *)ring->rptr_cpu_addr;
8247 }
8248
8249 static u64 gfx_v10_0_ring_get_wptr_compute(struct amdgpu_ring *ring)
8250 {
8251         u64 wptr;
8252
8253         /* XXX check if swapping is necessary on BE */
8254         if (ring->use_doorbell)
8255                 wptr = atomic64_read((atomic64_t *)ring->wptr_cpu_addr);
8256         else
8257                 BUG();
8258         return wptr;
8259 }
8260
8261 static void gfx_v10_0_ring_set_wptr_compute(struct amdgpu_ring *ring)
8262 {
8263         struct amdgpu_device *adev = ring->adev;
8264         uint32_t *wptr_saved;
8265         uint32_t *is_queue_unmap;
8266         uint64_t aggregated_db_index;
8267         uint32_t mqd_size = adev->mqds[AMDGPU_HW_IP_COMPUTE].mqd_size;
8268         uint64_t wptr_tmp;
8269
8270         if (ring->is_mes_queue) {
8271                 wptr_saved = (uint32_t *)(ring->mqd_ptr + mqd_size);
8272                 is_queue_unmap = (uint32_t *)(ring->mqd_ptr + mqd_size +
8273                                               sizeof(uint32_t));
8274                 aggregated_db_index =
8275                         amdgpu_mes_get_aggregated_doorbell_index(adev,
8276                         AMDGPU_MES_PRIORITY_LEVEL_NORMAL);
8277
8278                 wptr_tmp = ring->wptr & ring->buf_mask;
8279                 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, wptr_tmp);
8280                 *wptr_saved = wptr_tmp;
8281                 /* assume doorbell always used by mes mapped queue */
8282                 if (*is_queue_unmap) {
8283                         WDOORBELL64(aggregated_db_index, wptr_tmp);
8284                         WDOORBELL64(ring->doorbell_index, wptr_tmp);
8285                 } else {
8286                         WDOORBELL64(ring->doorbell_index, wptr_tmp);
8287
8288                         if (*is_queue_unmap)
8289                                 WDOORBELL64(aggregated_db_index, wptr_tmp);
8290                 }
8291         } else {
8292                 /* XXX check if swapping is necessary on BE */
8293                 if (ring->use_doorbell) {
8294                         atomic64_set((atomic64_t *)ring->wptr_cpu_addr,
8295                                      ring->wptr);
8296                         WDOORBELL64(ring->doorbell_index, ring->wptr);
8297                 } else {
8298                         BUG(); /* only DOORBELL method supported on gfx10 now */
8299                 }
8300         }
8301 }
8302
8303 static void gfx_v10_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
8304 {
8305         struct amdgpu_device *adev = ring->adev;
8306         u32 ref_and_mask, reg_mem_engine;
8307         const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio.hdp_flush_reg;
8308
8309         if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) {
8310                 switch (ring->me) {
8311                 case 1:
8312                         ref_and_mask = nbio_hf_reg->ref_and_mask_cp2 << ring->pipe;
8313                         break;
8314                 case 2:
8315                         ref_and_mask = nbio_hf_reg->ref_and_mask_cp6 << ring->pipe;
8316                         break;
8317                 default:
8318                         return;
8319                 }
8320                 reg_mem_engine = 0;
8321         } else {
8322                 ref_and_mask = nbio_hf_reg->ref_and_mask_cp0;
8323                 reg_mem_engine = 1; /* pfp */
8324         }
8325
8326         gfx_v10_0_wait_reg_mem(ring, reg_mem_engine, 0, 1,
8327                                adev->nbio.funcs->get_hdp_flush_req_offset(adev),
8328                                adev->nbio.funcs->get_hdp_flush_done_offset(adev),
8329                                ref_and_mask, ref_and_mask, 0x20);
8330 }
8331
8332 static void gfx_v10_0_ring_emit_ib_gfx(struct amdgpu_ring *ring,
8333                                        struct amdgpu_job *job,
8334                                        struct amdgpu_ib *ib,
8335                                        uint32_t flags)
8336 {
8337         unsigned int vmid = AMDGPU_JOB_GET_VMID(job);
8338         u32 header, control = 0;
8339
8340         if (ib->flags & AMDGPU_IB_FLAG_CE)
8341                 header = PACKET3(PACKET3_INDIRECT_BUFFER_CNST, 2);
8342         else
8343                 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2);
8344
8345         control |= ib->length_dw | (vmid << 24);
8346
8347         if (ring->adev->gfx.mcbp && (ib->flags & AMDGPU_IB_FLAG_PREEMPT)) {
8348                 control |= INDIRECT_BUFFER_PRE_ENB(1);
8349
8350                 if (flags & AMDGPU_IB_PREEMPTED)
8351                         control |= INDIRECT_BUFFER_PRE_RESUME(1);
8352
8353                 if (!(ib->flags & AMDGPU_IB_FLAG_CE) && vmid)
8354                         gfx_v10_0_ring_emit_de_meta(ring,
8355                                     (!amdgpu_sriov_vf(ring->adev) && flags & AMDGPU_IB_PREEMPTED) ? true : false);
8356         }
8357
8358         if (ring->is_mes_queue)
8359                 /* inherit vmid from mqd */
8360                 control |= 0x400000;
8361
8362         amdgpu_ring_write(ring, header);
8363         BUG_ON(ib->gpu_addr & 0x3); /* Dword align */
8364         amdgpu_ring_write(ring,
8365 #ifdef __BIG_ENDIAN
8366                 (2 << 0) |
8367 #endif
8368                 lower_32_bits(ib->gpu_addr));
8369         amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
8370         amdgpu_ring_write(ring, control);
8371 }
8372
8373 static void gfx_v10_0_ring_emit_ib_compute(struct amdgpu_ring *ring,
8374                                            struct amdgpu_job *job,
8375                                            struct amdgpu_ib *ib,
8376                                            uint32_t flags)
8377 {
8378         unsigned int vmid = AMDGPU_JOB_GET_VMID(job);
8379         u32 control = INDIRECT_BUFFER_VALID | ib->length_dw | (vmid << 24);
8380
8381         if (ring->is_mes_queue)
8382                 /* inherit vmid from mqd */
8383                 control |= 0x40000000;
8384
8385         /* Currently, there is a high possibility to get wave ID mismatch
8386          * between ME and GDS, leading to a hw deadlock, because ME generates
8387          * different wave IDs than the GDS expects. This situation happens
8388          * randomly when at least 5 compute pipes use GDS ordered append.
8389          * The wave IDs generated by ME are also wrong after suspend/resume.
8390          * Those are probably bugs somewhere else in the kernel driver.
8391          *
8392          * Writing GDS_COMPUTE_MAX_WAVE_ID resets wave ID counters in ME and
8393          * GDS to 0 for this ring (me/pipe).
8394          */
8395         if (ib->flags & AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID) {
8396                 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
8397                 amdgpu_ring_write(ring, mmGDS_COMPUTE_MAX_WAVE_ID);
8398                 amdgpu_ring_write(ring, ring->adev->gds.gds_compute_max_wave_id);
8399         }
8400
8401         amdgpu_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
8402         BUG_ON(ib->gpu_addr & 0x3); /* Dword align */
8403         amdgpu_ring_write(ring,
8404 #ifdef __BIG_ENDIAN
8405                                 (2 << 0) |
8406 #endif
8407                                 lower_32_bits(ib->gpu_addr));
8408         amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
8409         amdgpu_ring_write(ring, control);
8410 }
8411
8412 static void gfx_v10_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr,
8413                                      u64 seq, unsigned int flags)
8414 {
8415         bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
8416         bool int_sel = flags & AMDGPU_FENCE_FLAG_INT;
8417
8418         /* RELEASE_MEM - flush caches, send int */
8419         amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 6));
8420         amdgpu_ring_write(ring, (PACKET3_RELEASE_MEM_GCR_SEQ |
8421                                  PACKET3_RELEASE_MEM_GCR_GL2_WB |
8422                                  PACKET3_RELEASE_MEM_GCR_GLM_INV | /* must be set with GLM_WB */
8423                                  PACKET3_RELEASE_MEM_GCR_GLM_WB |
8424                                  PACKET3_RELEASE_MEM_CACHE_POLICY(3) |
8425                                  PACKET3_RELEASE_MEM_EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) |
8426                                  PACKET3_RELEASE_MEM_EVENT_INDEX(5)));
8427         amdgpu_ring_write(ring, (PACKET3_RELEASE_MEM_DATA_SEL(write64bit ? 2 : 1) |
8428                                  PACKET3_RELEASE_MEM_INT_SEL(int_sel ? 2 : 0)));
8429
8430         /*
8431          * the address should be Qword aligned if 64bit write, Dword
8432          * aligned if only send 32bit data low (discard data high)
8433          */
8434         if (write64bit)
8435                 BUG_ON(addr & 0x7);
8436         else
8437                 BUG_ON(addr & 0x3);
8438         amdgpu_ring_write(ring, lower_32_bits(addr));
8439         amdgpu_ring_write(ring, upper_32_bits(addr));
8440         amdgpu_ring_write(ring, lower_32_bits(seq));
8441         amdgpu_ring_write(ring, upper_32_bits(seq));
8442         amdgpu_ring_write(ring, ring->is_mes_queue ?
8443                          (ring->hw_queue_id | AMDGPU_FENCE_MES_QUEUE_FLAG) : 0);
8444 }
8445
8446 static void gfx_v10_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
8447 {
8448         int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
8449         uint32_t seq = ring->fence_drv.sync_seq;
8450         uint64_t addr = ring->fence_drv.gpu_addr;
8451
8452         gfx_v10_0_wait_reg_mem(ring, usepfp, 1, 0, lower_32_bits(addr),
8453                                upper_32_bits(addr), seq, 0xffffffff, 4);
8454 }
8455
8456 static void gfx_v10_0_ring_invalidate_tlbs(struct amdgpu_ring *ring,
8457                                    uint16_t pasid, uint32_t flush_type,
8458                                    bool all_hub, uint8_t dst_sel)
8459 {
8460         amdgpu_ring_write(ring, PACKET3(PACKET3_INVALIDATE_TLBS, 0));
8461         amdgpu_ring_write(ring,
8462                           PACKET3_INVALIDATE_TLBS_DST_SEL(dst_sel) |
8463                           PACKET3_INVALIDATE_TLBS_ALL_HUB(all_hub) |
8464                           PACKET3_INVALIDATE_TLBS_PASID(pasid) |
8465                           PACKET3_INVALIDATE_TLBS_FLUSH_TYPE(flush_type));
8466 }
8467
8468 static void gfx_v10_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
8469                                          unsigned int vmid, uint64_t pd_addr)
8470 {
8471         if (ring->is_mes_queue)
8472                 gfx_v10_0_ring_invalidate_tlbs(ring, 0, 0, false, 0);
8473         else
8474                 amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
8475
8476         /* compute doesn't have PFP */
8477         if (ring->funcs->type == AMDGPU_RING_TYPE_GFX) {
8478                 /* sync PFP to ME, otherwise we might get invalid PFP reads */
8479                 amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0));
8480                 amdgpu_ring_write(ring, 0x0);
8481         }
8482 }
8483
8484 static void gfx_v10_0_ring_emit_fence_kiq(struct amdgpu_ring *ring, u64 addr,
8485                                           u64 seq, unsigned int flags)
8486 {
8487         struct amdgpu_device *adev = ring->adev;
8488
8489         /* we only allocate 32bit for each seq wb address */
8490         BUG_ON(flags & AMDGPU_FENCE_FLAG_64BIT);
8491
8492         /* write fence seq to the "addr" */
8493         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
8494         amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
8495                                  WRITE_DATA_DST_SEL(5) | WR_CONFIRM));
8496         amdgpu_ring_write(ring, lower_32_bits(addr));
8497         amdgpu_ring_write(ring, upper_32_bits(addr));
8498         amdgpu_ring_write(ring, lower_32_bits(seq));
8499
8500         if (flags & AMDGPU_FENCE_FLAG_INT) {
8501                 /* set register to trigger INT */
8502                 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
8503                 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
8504                                          WRITE_DATA_DST_SEL(0) | WR_CONFIRM));
8505                 amdgpu_ring_write(ring, SOC15_REG_OFFSET(GC, 0, mmCPC_INT_STATUS));
8506                 amdgpu_ring_write(ring, 0);
8507                 amdgpu_ring_write(ring, 0x20000000); /* src_id is 178 */
8508         }
8509 }
8510
8511 static void gfx_v10_0_ring_emit_sb(struct amdgpu_ring *ring)
8512 {
8513         amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
8514         amdgpu_ring_write(ring, 0);
8515 }
8516
8517 static void gfx_v10_0_ring_emit_cntxcntl(struct amdgpu_ring *ring,
8518                                          uint32_t flags)
8519 {
8520         uint32_t dw2 = 0;
8521
8522         if (ring->adev->gfx.mcbp)
8523                 gfx_v10_0_ring_emit_ce_meta(ring,
8524                                     (!amdgpu_sriov_vf(ring->adev) && flags & AMDGPU_IB_PREEMPTED) ? true : false);
8525
8526         dw2 |= 0x80000000; /* set load_enable otherwise this package is just NOPs */
8527         if (flags & AMDGPU_HAVE_CTX_SWITCH) {
8528                 /* set load_global_config & load_global_uconfig */
8529                 dw2 |= 0x8001;
8530                 /* set load_cs_sh_regs */
8531                 dw2 |= 0x01000000;
8532                 /* set load_per_context_state & load_gfx_sh_regs for GFX */
8533                 dw2 |= 0x10002;
8534
8535                 /* set load_ce_ram if preamble presented */
8536                 if (AMDGPU_PREAMBLE_IB_PRESENT & flags)
8537                         dw2 |= 0x10000000;
8538         } else {
8539                 /* still load_ce_ram if this is the first time preamble presented
8540                  * although there is no context switch happens.
8541                  */
8542                 if (AMDGPU_PREAMBLE_IB_PRESENT_FIRST & flags)
8543                         dw2 |= 0x10000000;
8544         }
8545
8546         amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1));
8547         amdgpu_ring_write(ring, dw2);
8548         amdgpu_ring_write(ring, 0);
8549 }
8550
8551 static unsigned int gfx_v10_0_ring_emit_init_cond_exec(struct amdgpu_ring *ring)
8552 {
8553         unsigned int ret;
8554
8555         amdgpu_ring_write(ring, PACKET3(PACKET3_COND_EXEC, 3));
8556         amdgpu_ring_write(ring, lower_32_bits(ring->cond_exe_gpu_addr));
8557         amdgpu_ring_write(ring, upper_32_bits(ring->cond_exe_gpu_addr));
8558         amdgpu_ring_write(ring, 0); /* discard following DWs if *cond_exec_gpu_addr==0 */
8559         ret = ring->wptr & ring->buf_mask;
8560         amdgpu_ring_write(ring, 0x55aa55aa); /* patch dummy value later */
8561
8562         return ret;
8563 }
8564
8565 static void gfx_v10_0_ring_emit_patch_cond_exec(struct amdgpu_ring *ring, unsigned int offset)
8566 {
8567         unsigned int cur;
8568
8569         BUG_ON(offset > ring->buf_mask);
8570         BUG_ON(ring->ring[offset] != 0x55aa55aa);
8571
8572         cur = (ring->wptr - 1) & ring->buf_mask;
8573         if (likely(cur > offset))
8574                 ring->ring[offset] = cur - offset;
8575         else
8576                 ring->ring[offset] = (ring->buf_mask + 1) - offset + cur;
8577 }
8578
8579 static int gfx_v10_0_ring_preempt_ib(struct amdgpu_ring *ring)
8580 {
8581         int i, r = 0;
8582         struct amdgpu_device *adev = ring->adev;
8583         struct amdgpu_kiq *kiq = &adev->gfx.kiq[0];
8584         struct amdgpu_ring *kiq_ring = &kiq->ring;
8585         unsigned long flags;
8586
8587         if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues)
8588                 return -EINVAL;
8589
8590         spin_lock_irqsave(&kiq->ring_lock, flags);
8591
8592         if (amdgpu_ring_alloc(kiq_ring, kiq->pmf->unmap_queues_size)) {
8593                 spin_unlock_irqrestore(&kiq->ring_lock, flags);
8594                 return -ENOMEM;
8595         }
8596
8597         /* assert preemption condition */
8598         amdgpu_ring_set_preempt_cond_exec(ring, false);
8599
8600         /* assert IB preemption, emit the trailing fence */
8601         kiq->pmf->kiq_unmap_queues(kiq_ring, ring, PREEMPT_QUEUES_NO_UNMAP,
8602                                    ring->trail_fence_gpu_addr,
8603                                    ++ring->trail_seq);
8604         amdgpu_ring_commit(kiq_ring);
8605
8606         spin_unlock_irqrestore(&kiq->ring_lock, flags);
8607
8608         /* poll the trailing fence */
8609         for (i = 0; i < adev->usec_timeout; i++) {
8610                 if (ring->trail_seq ==
8611                     le32_to_cpu(*(ring->trail_fence_cpu_addr)))
8612                         break;
8613                 udelay(1);
8614         }
8615
8616         if (i >= adev->usec_timeout) {
8617                 r = -EINVAL;
8618                 DRM_ERROR("ring %d failed to preempt ib\n", ring->idx);
8619         }
8620
8621         /* deassert preemption condition */
8622         amdgpu_ring_set_preempt_cond_exec(ring, true);
8623         return r;
8624 }
8625
8626 static void gfx_v10_0_ring_emit_ce_meta(struct amdgpu_ring *ring, bool resume)
8627 {
8628         struct amdgpu_device *adev = ring->adev;
8629         struct v10_ce_ib_state ce_payload = {0};
8630         uint64_t offset, ce_payload_gpu_addr;
8631         void *ce_payload_cpu_addr;
8632         int cnt;
8633
8634         cnt = (sizeof(ce_payload) >> 2) + 4 - 2;
8635
8636         if (ring->is_mes_queue) {
8637                 offset = offsetof(struct amdgpu_mes_ctx_meta_data,
8638                                   gfx[0].gfx_meta_data) +
8639                         offsetof(struct v10_gfx_meta_data, ce_payload);
8640                 ce_payload_gpu_addr =
8641                         amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset);
8642                 ce_payload_cpu_addr =
8643                         amdgpu_mes_ctx_get_offs_cpu_addr(ring, offset);
8644         } else {
8645                 offset = offsetof(struct v10_gfx_meta_data, ce_payload);
8646                 ce_payload_gpu_addr = amdgpu_csa_vaddr(ring->adev) + offset;
8647                 ce_payload_cpu_addr = adev->virt.csa_cpu_addr + offset;
8648         }
8649
8650         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt));
8651         amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(2) |
8652                                  WRITE_DATA_DST_SEL(8) |
8653                                  WR_CONFIRM) |
8654                                  WRITE_DATA_CACHE_POLICY(0));
8655         amdgpu_ring_write(ring, lower_32_bits(ce_payload_gpu_addr));
8656         amdgpu_ring_write(ring, upper_32_bits(ce_payload_gpu_addr));
8657
8658         if (resume)
8659                 amdgpu_ring_write_multiple(ring, ce_payload_cpu_addr,
8660                                            sizeof(ce_payload) >> 2);
8661         else
8662                 amdgpu_ring_write_multiple(ring, (void *)&ce_payload,
8663                                            sizeof(ce_payload) >> 2);
8664 }
8665
8666 static void gfx_v10_0_ring_emit_de_meta(struct amdgpu_ring *ring, bool resume)
8667 {
8668         struct amdgpu_device *adev = ring->adev;
8669         struct v10_de_ib_state de_payload = {0};
8670         uint64_t offset, gds_addr, de_payload_gpu_addr;
8671         void *de_payload_cpu_addr;
8672         int cnt;
8673
8674         if (ring->is_mes_queue) {
8675                 offset = offsetof(struct amdgpu_mes_ctx_meta_data,
8676                                   gfx[0].gfx_meta_data) +
8677                         offsetof(struct v10_gfx_meta_data, de_payload);
8678                 de_payload_gpu_addr =
8679                         amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset);
8680                 de_payload_cpu_addr =
8681                         amdgpu_mes_ctx_get_offs_cpu_addr(ring, offset);
8682
8683                 offset = offsetof(struct amdgpu_mes_ctx_meta_data,
8684                                   gfx[0].gds_backup) +
8685                         offsetof(struct v10_gfx_meta_data, de_payload);
8686                 gds_addr = amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset);
8687         } else {
8688                 offset = offsetof(struct v10_gfx_meta_data, de_payload);
8689                 de_payload_gpu_addr = amdgpu_csa_vaddr(ring->adev) + offset;
8690                 de_payload_cpu_addr = adev->virt.csa_cpu_addr + offset;
8691
8692                 gds_addr = ALIGN(amdgpu_csa_vaddr(ring->adev) +
8693                                  AMDGPU_CSA_SIZE - adev->gds.gds_size,
8694                                  PAGE_SIZE);
8695         }
8696
8697         de_payload.gds_backup_addrlo = lower_32_bits(gds_addr);
8698         de_payload.gds_backup_addrhi = upper_32_bits(gds_addr);
8699
8700         cnt = (sizeof(de_payload) >> 2) + 4 - 2;
8701         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt));
8702         amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(1) |
8703                                  WRITE_DATA_DST_SEL(8) |
8704                                  WR_CONFIRM) |
8705                                  WRITE_DATA_CACHE_POLICY(0));
8706         amdgpu_ring_write(ring, lower_32_bits(de_payload_gpu_addr));
8707         amdgpu_ring_write(ring, upper_32_bits(de_payload_gpu_addr));
8708
8709         if (resume)
8710                 amdgpu_ring_write_multiple(ring, de_payload_cpu_addr,
8711                                            sizeof(de_payload) >> 2);
8712         else
8713                 amdgpu_ring_write_multiple(ring, (void *)&de_payload,
8714                                            sizeof(de_payload) >> 2);
8715 }
8716
8717 static void gfx_v10_0_ring_emit_frame_cntl(struct amdgpu_ring *ring, bool start,
8718                                     bool secure)
8719 {
8720         uint32_t v = secure ? FRAME_TMZ : 0;
8721
8722         amdgpu_ring_write(ring, PACKET3(PACKET3_FRAME_CONTROL, 0));
8723         amdgpu_ring_write(ring, v | FRAME_CMD(start ? 0 : 1));
8724 }
8725
8726 static void gfx_v10_0_ring_emit_rreg(struct amdgpu_ring *ring, uint32_t reg,
8727                                      uint32_t reg_val_offs)
8728 {
8729         struct amdgpu_device *adev = ring->adev;
8730
8731         amdgpu_ring_write(ring, PACKET3(PACKET3_COPY_DATA, 4));
8732         amdgpu_ring_write(ring, 0 |     /* src: register*/
8733                                 (5 << 8) |      /* dst: memory */
8734                                 (1 << 20));     /* write confirm */
8735         amdgpu_ring_write(ring, reg);
8736         amdgpu_ring_write(ring, 0);
8737         amdgpu_ring_write(ring, lower_32_bits(adev->wb.gpu_addr +
8738                                 reg_val_offs * 4));
8739         amdgpu_ring_write(ring, upper_32_bits(adev->wb.gpu_addr +
8740                                 reg_val_offs * 4));
8741 }
8742
8743 static void gfx_v10_0_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg,
8744                                    uint32_t val)
8745 {
8746         uint32_t cmd = 0;
8747
8748         switch (ring->funcs->type) {
8749         case AMDGPU_RING_TYPE_GFX:
8750                 cmd = WRITE_DATA_ENGINE_SEL(1) | WR_CONFIRM;
8751                 break;
8752         case AMDGPU_RING_TYPE_KIQ:
8753                 cmd = (1 << 16); /* no inc addr */
8754                 break;
8755         default:
8756                 cmd = WR_CONFIRM;
8757                 break;
8758         }
8759         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
8760         amdgpu_ring_write(ring, cmd);
8761         amdgpu_ring_write(ring, reg);
8762         amdgpu_ring_write(ring, 0);
8763         amdgpu_ring_write(ring, val);
8764 }
8765
8766 static void gfx_v10_0_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,
8767                                         uint32_t val, uint32_t mask)
8768 {
8769         gfx_v10_0_wait_reg_mem(ring, 0, 0, 0, reg, 0, val, mask, 0x20);
8770 }
8771
8772 static void gfx_v10_0_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring,
8773                                                    uint32_t reg0, uint32_t reg1,
8774                                                    uint32_t ref, uint32_t mask)
8775 {
8776         int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
8777         struct amdgpu_device *adev = ring->adev;
8778         bool fw_version_ok = false;
8779
8780         fw_version_ok = adev->gfx.cp_fw_write_wait;
8781
8782         if (fw_version_ok)
8783                 gfx_v10_0_wait_reg_mem(ring, usepfp, 0, 1, reg0, reg1,
8784                                        ref, mask, 0x20);
8785         else
8786                 amdgpu_ring_emit_reg_write_reg_wait_helper(ring, reg0, reg1,
8787                                                            ref, mask);
8788 }
8789
8790 static void gfx_v10_0_ring_soft_recovery(struct amdgpu_ring *ring,
8791                                          unsigned int vmid)
8792 {
8793         struct amdgpu_device *adev = ring->adev;
8794         uint32_t value = 0;
8795
8796         value = REG_SET_FIELD(value, SQ_CMD, CMD, 0x03);
8797         value = REG_SET_FIELD(value, SQ_CMD, MODE, 0x01);
8798         value = REG_SET_FIELD(value, SQ_CMD, CHECK_VMID, 1);
8799         value = REG_SET_FIELD(value, SQ_CMD, VM_ID, vmid);
8800         WREG32_SOC15(GC, 0, mmSQ_CMD, value);
8801 }
8802
8803 static void
8804 gfx_v10_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev,
8805                                       uint32_t me, uint32_t pipe,
8806                                       enum amdgpu_interrupt_state state)
8807 {
8808         uint32_t cp_int_cntl, cp_int_cntl_reg;
8809
8810         if (!me) {
8811                 switch (pipe) {
8812                 case 0:
8813                         cp_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_INT_CNTL_RING0);
8814                         break;
8815                 case 1:
8816                         cp_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_INT_CNTL_RING1);
8817                         break;
8818                 default:
8819                         DRM_DEBUG("invalid pipe %d\n", pipe);
8820                         return;
8821                 }
8822         } else {
8823                 DRM_DEBUG("invalid me %d\n", me);
8824                 return;
8825         }
8826
8827         switch (state) {
8828         case AMDGPU_IRQ_STATE_DISABLE:
8829                 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg);
8830                 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
8831                                             TIME_STAMP_INT_ENABLE, 0);
8832                 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl);
8833                 break;
8834         case AMDGPU_IRQ_STATE_ENABLE:
8835                 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg);
8836                 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
8837                                             TIME_STAMP_INT_ENABLE, 1);
8838                 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl);
8839                 break;
8840         default:
8841                 break;
8842         }
8843 }
8844
8845 static void gfx_v10_0_set_compute_eop_interrupt_state(struct amdgpu_device *adev,
8846                                                      int me, int pipe,
8847                                                      enum amdgpu_interrupt_state state)
8848 {
8849         u32 mec_int_cntl, mec_int_cntl_reg;
8850
8851         /*
8852          * amdgpu controls only the first MEC. That's why this function only
8853          * handles the setting of interrupts for this specific MEC. All other
8854          * pipes' interrupts are set by amdkfd.
8855          */
8856
8857         if (me == 1) {
8858                 switch (pipe) {
8859                 case 0:
8860                         mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE0_INT_CNTL);
8861                         break;
8862                 case 1:
8863                         mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE1_INT_CNTL);
8864                         break;
8865                 case 2:
8866                         mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE2_INT_CNTL);
8867                         break;
8868                 case 3:
8869                         mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE3_INT_CNTL);
8870                         break;
8871                 default:
8872                         DRM_DEBUG("invalid pipe %d\n", pipe);
8873                         return;
8874                 }
8875         } else {
8876                 DRM_DEBUG("invalid me %d\n", me);
8877                 return;
8878         }
8879
8880         switch (state) {
8881         case AMDGPU_IRQ_STATE_DISABLE:
8882                 mec_int_cntl = RREG32_SOC15_IP(GC, mec_int_cntl_reg);
8883                 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,
8884                                              TIME_STAMP_INT_ENABLE, 0);
8885                 WREG32_SOC15_IP(GC, mec_int_cntl_reg, mec_int_cntl);
8886                 break;
8887         case AMDGPU_IRQ_STATE_ENABLE:
8888                 mec_int_cntl = RREG32_SOC15_IP(GC, mec_int_cntl_reg);
8889                 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,
8890                                              TIME_STAMP_INT_ENABLE, 1);
8891                 WREG32_SOC15_IP(GC, mec_int_cntl_reg, mec_int_cntl);
8892                 break;
8893         default:
8894                 break;
8895         }
8896 }
8897
8898 static int gfx_v10_0_set_eop_interrupt_state(struct amdgpu_device *adev,
8899                                             struct amdgpu_irq_src *src,
8900                                             unsigned int type,
8901                                             enum amdgpu_interrupt_state state)
8902 {
8903         switch (type) {
8904         case AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP:
8905                 gfx_v10_0_set_gfx_eop_interrupt_state(adev, 0, 0, state);
8906                 break;
8907         case AMDGPU_CP_IRQ_GFX_ME0_PIPE1_EOP:
8908                 gfx_v10_0_set_gfx_eop_interrupt_state(adev, 0, 1, state);
8909                 break;
8910         case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP:
8911                 gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 0, state);
8912                 break;
8913         case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP:
8914                 gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 1, state);
8915                 break;
8916         case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP:
8917                 gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 2, state);
8918                 break;
8919         case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP:
8920                 gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 3, state);
8921                 break;
8922         case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP:
8923                 gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 0, state);
8924                 break;
8925         case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP:
8926                 gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 1, state);
8927                 break;
8928         case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP:
8929                 gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 2, state);
8930                 break;
8931         case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP:
8932                 gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 3, state);
8933                 break;
8934         default:
8935                 break;
8936         }
8937         return 0;
8938 }
8939
8940 static int gfx_v10_0_eop_irq(struct amdgpu_device *adev,
8941                              struct amdgpu_irq_src *source,
8942                              struct amdgpu_iv_entry *entry)
8943 {
8944         int i;
8945         u8 me_id, pipe_id, queue_id;
8946         struct amdgpu_ring *ring;
8947         uint32_t mes_queue_id = entry->src_data[0];
8948
8949         DRM_DEBUG("IH: CP EOP\n");
8950
8951         if (adev->enable_mes && (mes_queue_id & AMDGPU_FENCE_MES_QUEUE_FLAG)) {
8952                 struct amdgpu_mes_queue *queue;
8953
8954                 mes_queue_id &= AMDGPU_FENCE_MES_QUEUE_ID_MASK;
8955
8956                 spin_lock(&adev->mes.queue_id_lock);
8957                 queue = idr_find(&adev->mes.queue_id_idr, mes_queue_id);
8958                 if (queue) {
8959                         DRM_DEBUG("process mes queue id = %d\n", mes_queue_id);
8960                         amdgpu_fence_process(queue->ring);
8961                 }
8962                 spin_unlock(&adev->mes.queue_id_lock);
8963         } else {
8964                 me_id = (entry->ring_id & 0x0c) >> 2;
8965                 pipe_id = (entry->ring_id & 0x03) >> 0;
8966                 queue_id = (entry->ring_id & 0x70) >> 4;
8967
8968                 switch (me_id) {
8969                 case 0:
8970                         if (pipe_id == 0)
8971                                 amdgpu_fence_process(&adev->gfx.gfx_ring[0]);
8972                         else
8973                                 amdgpu_fence_process(&adev->gfx.gfx_ring[1]);
8974                         break;
8975                 case 1:
8976                 case 2:
8977                         for (i = 0; i < adev->gfx.num_compute_rings; i++) {
8978                                 ring = &adev->gfx.compute_ring[i];
8979                                 /* Per-queue interrupt is supported for MEC starting from VI.
8980                                  * The interrupt can only be enabled/disabled per pipe instead
8981                                  * of per queue.
8982                                  */
8983                                 if ((ring->me == me_id) &&
8984                                     (ring->pipe == pipe_id) &&
8985                                     (ring->queue == queue_id))
8986                                         amdgpu_fence_process(ring);
8987                         }
8988                         break;
8989                 }
8990         }
8991
8992         return 0;
8993 }
8994
8995 static int gfx_v10_0_set_priv_reg_fault_state(struct amdgpu_device *adev,
8996                                               struct amdgpu_irq_src *source,
8997                                               unsigned int type,
8998                                               enum amdgpu_interrupt_state state)
8999 {
9000         switch (state) {
9001         case AMDGPU_IRQ_STATE_DISABLE:
9002         case AMDGPU_IRQ_STATE_ENABLE:
9003                 WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0,
9004                                PRIV_REG_INT_ENABLE,
9005                                state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
9006                 break;
9007         default:
9008                 break;
9009         }
9010
9011         return 0;
9012 }
9013
9014 static int gfx_v10_0_set_priv_inst_fault_state(struct amdgpu_device *adev,
9015                                                struct amdgpu_irq_src *source,
9016                                                unsigned int type,
9017                                                enum amdgpu_interrupt_state state)
9018 {
9019         switch (state) {
9020         case AMDGPU_IRQ_STATE_DISABLE:
9021         case AMDGPU_IRQ_STATE_ENABLE:
9022                 WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0,
9023                                PRIV_INSTR_INT_ENABLE,
9024                                state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
9025                 break;
9026         default:
9027                 break;
9028         }
9029
9030         return 0;
9031 }
9032
9033 static void gfx_v10_0_handle_priv_fault(struct amdgpu_device *adev,
9034                                         struct amdgpu_iv_entry *entry)
9035 {
9036         u8 me_id, pipe_id, queue_id;
9037         struct amdgpu_ring *ring;
9038         int i;
9039
9040         me_id = (entry->ring_id & 0x0c) >> 2;
9041         pipe_id = (entry->ring_id & 0x03) >> 0;
9042         queue_id = (entry->ring_id & 0x70) >> 4;
9043
9044         switch (me_id) {
9045         case 0:
9046                 for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
9047                         ring = &adev->gfx.gfx_ring[i];
9048                         /* we only enabled 1 gfx queue per pipe for now */
9049                         if (ring->me == me_id && ring->pipe == pipe_id)
9050                                 drm_sched_fault(&ring->sched);
9051                 }
9052                 break;
9053         case 1:
9054         case 2:
9055                 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
9056                         ring = &adev->gfx.compute_ring[i];
9057                         if (ring->me == me_id && ring->pipe == pipe_id &&
9058                             ring->queue == queue_id)
9059                                 drm_sched_fault(&ring->sched);
9060                 }
9061                 break;
9062         default:
9063                 BUG();
9064         }
9065 }
9066
9067 static int gfx_v10_0_priv_reg_irq(struct amdgpu_device *adev,
9068                                   struct amdgpu_irq_src *source,
9069                                   struct amdgpu_iv_entry *entry)
9070 {
9071         DRM_ERROR("Illegal register access in command stream\n");
9072         gfx_v10_0_handle_priv_fault(adev, entry);
9073         return 0;
9074 }
9075
9076 static int gfx_v10_0_priv_inst_irq(struct amdgpu_device *adev,
9077                                    struct amdgpu_irq_src *source,
9078                                    struct amdgpu_iv_entry *entry)
9079 {
9080         DRM_ERROR("Illegal instruction in command stream\n");
9081         gfx_v10_0_handle_priv_fault(adev, entry);
9082         return 0;
9083 }
9084
9085 static int gfx_v10_0_kiq_set_interrupt_state(struct amdgpu_device *adev,
9086                                              struct amdgpu_irq_src *src,
9087                                              unsigned int type,
9088                                              enum amdgpu_interrupt_state state)
9089 {
9090         uint32_t tmp, target;
9091         struct amdgpu_ring *ring = &(adev->gfx.kiq[0].ring);
9092
9093         if (ring->me == 1)
9094                 target = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE0_INT_CNTL);
9095         else
9096                 target = SOC15_REG_OFFSET(GC, 0, mmCP_ME2_PIPE0_INT_CNTL);
9097         target += ring->pipe;
9098
9099         switch (type) {
9100         case AMDGPU_CP_KIQ_IRQ_DRIVER0:
9101                 if (state == AMDGPU_IRQ_STATE_DISABLE) {
9102                         tmp = RREG32_SOC15(GC, 0, mmCPC_INT_CNTL);
9103                         tmp = REG_SET_FIELD(tmp, CPC_INT_CNTL,
9104                                             GENERIC2_INT_ENABLE, 0);
9105                         WREG32_SOC15(GC, 0, mmCPC_INT_CNTL, tmp);
9106
9107                         tmp = RREG32_SOC15_IP(GC, target);
9108                         tmp = REG_SET_FIELD(tmp, CP_ME2_PIPE0_INT_CNTL,
9109                                             GENERIC2_INT_ENABLE, 0);
9110                         WREG32_SOC15_IP(GC, target, tmp);
9111                 } else {
9112                         tmp = RREG32_SOC15(GC, 0, mmCPC_INT_CNTL);
9113                         tmp = REG_SET_FIELD(tmp, CPC_INT_CNTL,
9114                                             GENERIC2_INT_ENABLE, 1);
9115                         WREG32_SOC15(GC, 0, mmCPC_INT_CNTL, tmp);
9116
9117                         tmp = RREG32_SOC15_IP(GC, target);
9118                         tmp = REG_SET_FIELD(tmp, CP_ME2_PIPE0_INT_CNTL,
9119                                             GENERIC2_INT_ENABLE, 1);
9120                         WREG32_SOC15_IP(GC, target, tmp);
9121                 }
9122                 break;
9123         default:
9124                 BUG(); /* kiq only support GENERIC2_INT now */
9125                 break;
9126         }
9127         return 0;
9128 }
9129
9130 static int gfx_v10_0_kiq_irq(struct amdgpu_device *adev,
9131                              struct amdgpu_irq_src *source,
9132                              struct amdgpu_iv_entry *entry)
9133 {
9134         u8 me_id, pipe_id, queue_id;
9135         struct amdgpu_ring *ring = &(adev->gfx.kiq[0].ring);
9136
9137         me_id = (entry->ring_id & 0x0c) >> 2;
9138         pipe_id = (entry->ring_id & 0x03) >> 0;
9139         queue_id = (entry->ring_id & 0x70) >> 4;
9140         DRM_DEBUG("IH: CPC GENERIC2_INT, me:%d, pipe:%d, queue:%d\n",
9141                    me_id, pipe_id, queue_id);
9142
9143         amdgpu_fence_process(ring);
9144         return 0;
9145 }
9146
9147 static void gfx_v10_0_emit_mem_sync(struct amdgpu_ring *ring)
9148 {
9149         const unsigned int gcr_cntl =
9150                         PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_INV(1) |
9151                         PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_WB(1) |
9152                         PACKET3_ACQUIRE_MEM_GCR_CNTL_GLM_INV(1) |
9153                         PACKET3_ACQUIRE_MEM_GCR_CNTL_GLM_WB(1) |
9154                         PACKET3_ACQUIRE_MEM_GCR_CNTL_GL1_INV(1) |
9155                         PACKET3_ACQUIRE_MEM_GCR_CNTL_GLV_INV(1) |
9156                         PACKET3_ACQUIRE_MEM_GCR_CNTL_GLK_INV(1) |
9157                         PACKET3_ACQUIRE_MEM_GCR_CNTL_GLI_INV(1);
9158
9159         /* ACQUIRE_MEM - make one or more surfaces valid for use by the subsequent operations */
9160         amdgpu_ring_write(ring, PACKET3(PACKET3_ACQUIRE_MEM, 6));
9161         amdgpu_ring_write(ring, 0); /* CP_COHER_CNTL */
9162         amdgpu_ring_write(ring, 0xffffffff);  /* CP_COHER_SIZE */
9163         amdgpu_ring_write(ring, 0xffffff);  /* CP_COHER_SIZE_HI */
9164         amdgpu_ring_write(ring, 0); /* CP_COHER_BASE */
9165         amdgpu_ring_write(ring, 0);  /* CP_COHER_BASE_HI */
9166         amdgpu_ring_write(ring, 0x0000000A); /* POLL_INTERVAL */
9167         amdgpu_ring_write(ring, gcr_cntl); /* GCR_CNTL */
9168 }
9169
9170 static const struct amd_ip_funcs gfx_v10_0_ip_funcs = {
9171         .name = "gfx_v10_0",
9172         .early_init = gfx_v10_0_early_init,
9173         .late_init = gfx_v10_0_late_init,
9174         .sw_init = gfx_v10_0_sw_init,
9175         .sw_fini = gfx_v10_0_sw_fini,
9176         .hw_init = gfx_v10_0_hw_init,
9177         .hw_fini = gfx_v10_0_hw_fini,
9178         .suspend = gfx_v10_0_suspend,
9179         .resume = gfx_v10_0_resume,
9180         .is_idle = gfx_v10_0_is_idle,
9181         .wait_for_idle = gfx_v10_0_wait_for_idle,
9182         .soft_reset = gfx_v10_0_soft_reset,
9183         .set_clockgating_state = gfx_v10_0_set_clockgating_state,
9184         .set_powergating_state = gfx_v10_0_set_powergating_state,
9185         .get_clockgating_state = gfx_v10_0_get_clockgating_state,
9186 };
9187
9188 static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_gfx = {
9189         .type = AMDGPU_RING_TYPE_GFX,
9190         .align_mask = 0xff,
9191         .nop = PACKET3(PACKET3_NOP, 0x3FFF),
9192         .support_64bit_ptrs = true,
9193         .secure_submission_supported = true,
9194         .get_rptr = gfx_v10_0_ring_get_rptr_gfx,
9195         .get_wptr = gfx_v10_0_ring_get_wptr_gfx,
9196         .set_wptr = gfx_v10_0_ring_set_wptr_gfx,
9197         .emit_frame_size = /* totally 242 maximum if 16 IBs */
9198                 5 + /* COND_EXEC */
9199                 7 + /* PIPELINE_SYNC */
9200                 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 +
9201                 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 +
9202                 2 + /* VM_FLUSH */
9203                 8 + /* FENCE for VM_FLUSH */
9204                 20 + /* GDS switch */
9205                 4 + /* double SWITCH_BUFFER,
9206                      * the first COND_EXEC jump to the place
9207                      * just prior to this double SWITCH_BUFFER
9208                      */
9209                 5 + /* COND_EXEC */
9210                 7 + /* HDP_flush */
9211                 4 + /* VGT_flush */
9212                 14 + /* CE_META */
9213                 31 + /* DE_META */
9214                 3 + /* CNTX_CTRL */
9215                 5 + /* HDP_INVL */
9216                 8 + 8 + /* FENCE x2 */
9217                 2 + /* SWITCH_BUFFER */
9218                 8, /* gfx_v10_0_emit_mem_sync */
9219         .emit_ib_size = 4, /* gfx_v10_0_ring_emit_ib_gfx */
9220         .emit_ib = gfx_v10_0_ring_emit_ib_gfx,
9221         .emit_fence = gfx_v10_0_ring_emit_fence,
9222         .emit_pipeline_sync = gfx_v10_0_ring_emit_pipeline_sync,
9223         .emit_vm_flush = gfx_v10_0_ring_emit_vm_flush,
9224         .emit_gds_switch = gfx_v10_0_ring_emit_gds_switch,
9225         .emit_hdp_flush = gfx_v10_0_ring_emit_hdp_flush,
9226         .test_ring = gfx_v10_0_ring_test_ring,
9227         .test_ib = gfx_v10_0_ring_test_ib,
9228         .insert_nop = amdgpu_ring_insert_nop,
9229         .pad_ib = amdgpu_ring_generic_pad_ib,
9230         .emit_switch_buffer = gfx_v10_0_ring_emit_sb,
9231         .emit_cntxcntl = gfx_v10_0_ring_emit_cntxcntl,
9232         .init_cond_exec = gfx_v10_0_ring_emit_init_cond_exec,
9233         .patch_cond_exec = gfx_v10_0_ring_emit_patch_cond_exec,
9234         .preempt_ib = gfx_v10_0_ring_preempt_ib,
9235         .emit_frame_cntl = gfx_v10_0_ring_emit_frame_cntl,
9236         .emit_wreg = gfx_v10_0_ring_emit_wreg,
9237         .emit_reg_wait = gfx_v10_0_ring_emit_reg_wait,
9238         .emit_reg_write_reg_wait = gfx_v10_0_ring_emit_reg_write_reg_wait,
9239         .soft_recovery = gfx_v10_0_ring_soft_recovery,
9240         .emit_mem_sync = gfx_v10_0_emit_mem_sync,
9241 };
9242
9243 static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_compute = {
9244         .type = AMDGPU_RING_TYPE_COMPUTE,
9245         .align_mask = 0xff,
9246         .nop = PACKET3(PACKET3_NOP, 0x3FFF),
9247         .support_64bit_ptrs = true,
9248         .get_rptr = gfx_v10_0_ring_get_rptr_compute,
9249         .get_wptr = gfx_v10_0_ring_get_wptr_compute,
9250         .set_wptr = gfx_v10_0_ring_set_wptr_compute,
9251         .emit_frame_size =
9252                 20 + /* gfx_v10_0_ring_emit_gds_switch */
9253                 7 + /* gfx_v10_0_ring_emit_hdp_flush */
9254                 5 + /* hdp invalidate */
9255                 7 + /* gfx_v10_0_ring_emit_pipeline_sync */
9256                 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 +
9257                 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 +
9258                 2 + /* gfx_v10_0_ring_emit_vm_flush */
9259                 8 + 8 + 8 + /* gfx_v10_0_ring_emit_fence x3 for user fence, vm fence */
9260                 8, /* gfx_v10_0_emit_mem_sync */
9261         .emit_ib_size = 7, /* gfx_v10_0_ring_emit_ib_compute */
9262         .emit_ib = gfx_v10_0_ring_emit_ib_compute,
9263         .emit_fence = gfx_v10_0_ring_emit_fence,
9264         .emit_pipeline_sync = gfx_v10_0_ring_emit_pipeline_sync,
9265         .emit_vm_flush = gfx_v10_0_ring_emit_vm_flush,
9266         .emit_gds_switch = gfx_v10_0_ring_emit_gds_switch,
9267         .emit_hdp_flush = gfx_v10_0_ring_emit_hdp_flush,
9268         .test_ring = gfx_v10_0_ring_test_ring,
9269         .test_ib = gfx_v10_0_ring_test_ib,
9270         .insert_nop = amdgpu_ring_insert_nop,
9271         .pad_ib = amdgpu_ring_generic_pad_ib,
9272         .emit_wreg = gfx_v10_0_ring_emit_wreg,
9273         .emit_reg_wait = gfx_v10_0_ring_emit_reg_wait,
9274         .emit_reg_write_reg_wait = gfx_v10_0_ring_emit_reg_write_reg_wait,
9275         .emit_mem_sync = gfx_v10_0_emit_mem_sync,
9276 };
9277
9278 static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_kiq = {
9279         .type = AMDGPU_RING_TYPE_KIQ,
9280         .align_mask = 0xff,
9281         .nop = PACKET3(PACKET3_NOP, 0x3FFF),
9282         .support_64bit_ptrs = true,
9283         .get_rptr = gfx_v10_0_ring_get_rptr_compute,
9284         .get_wptr = gfx_v10_0_ring_get_wptr_compute,
9285         .set_wptr = gfx_v10_0_ring_set_wptr_compute,
9286         .emit_frame_size =
9287                 20 + /* gfx_v10_0_ring_emit_gds_switch */
9288                 7 + /* gfx_v10_0_ring_emit_hdp_flush */
9289                 5 + /*hdp invalidate */
9290                 7 + /* gfx_v10_0_ring_emit_pipeline_sync */
9291                 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 +
9292                 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 +
9293                 2 + /* gfx_v10_0_ring_emit_vm_flush */
9294                 8 + 8 + 8, /* gfx_v10_0_ring_emit_fence_kiq x3 for user fence, vm fence */
9295         .emit_ib_size = 7, /* gfx_v10_0_ring_emit_ib_compute */
9296         .emit_ib = gfx_v10_0_ring_emit_ib_compute,
9297         .emit_fence = gfx_v10_0_ring_emit_fence_kiq,
9298         .test_ring = gfx_v10_0_ring_test_ring,
9299         .test_ib = gfx_v10_0_ring_test_ib,
9300         .insert_nop = amdgpu_ring_insert_nop,
9301         .pad_ib = amdgpu_ring_generic_pad_ib,
9302         .emit_rreg = gfx_v10_0_ring_emit_rreg,
9303         .emit_wreg = gfx_v10_0_ring_emit_wreg,
9304         .emit_reg_wait = gfx_v10_0_ring_emit_reg_wait,
9305         .emit_reg_write_reg_wait = gfx_v10_0_ring_emit_reg_write_reg_wait,
9306 };
9307
9308 static void gfx_v10_0_set_ring_funcs(struct amdgpu_device *adev)
9309 {
9310         int i;
9311
9312         adev->gfx.kiq[0].ring.funcs = &gfx_v10_0_ring_funcs_kiq;
9313
9314         for (i = 0; i < adev->gfx.num_gfx_rings; i++)
9315                 adev->gfx.gfx_ring[i].funcs = &gfx_v10_0_ring_funcs_gfx;
9316
9317         for (i = 0; i < adev->gfx.num_compute_rings; i++)
9318                 adev->gfx.compute_ring[i].funcs = &gfx_v10_0_ring_funcs_compute;
9319 }
9320
9321 static const struct amdgpu_irq_src_funcs gfx_v10_0_eop_irq_funcs = {
9322         .set = gfx_v10_0_set_eop_interrupt_state,
9323         .process = gfx_v10_0_eop_irq,
9324 };
9325
9326 static const struct amdgpu_irq_src_funcs gfx_v10_0_priv_reg_irq_funcs = {
9327         .set = gfx_v10_0_set_priv_reg_fault_state,
9328         .process = gfx_v10_0_priv_reg_irq,
9329 };
9330
9331 static const struct amdgpu_irq_src_funcs gfx_v10_0_priv_inst_irq_funcs = {
9332         .set = gfx_v10_0_set_priv_inst_fault_state,
9333         .process = gfx_v10_0_priv_inst_irq,
9334 };
9335
9336 static const struct amdgpu_irq_src_funcs gfx_v10_0_kiq_irq_funcs = {
9337         .set = gfx_v10_0_kiq_set_interrupt_state,
9338         .process = gfx_v10_0_kiq_irq,
9339 };
9340
9341 static void gfx_v10_0_set_irq_funcs(struct amdgpu_device *adev)
9342 {
9343         adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST;
9344         adev->gfx.eop_irq.funcs = &gfx_v10_0_eop_irq_funcs;
9345
9346         adev->gfx.kiq[0].irq.num_types = AMDGPU_CP_KIQ_IRQ_LAST;
9347         adev->gfx.kiq[0].irq.funcs = &gfx_v10_0_kiq_irq_funcs;
9348
9349         adev->gfx.priv_reg_irq.num_types = 1;
9350         adev->gfx.priv_reg_irq.funcs = &gfx_v10_0_priv_reg_irq_funcs;
9351
9352         adev->gfx.priv_inst_irq.num_types = 1;
9353         adev->gfx.priv_inst_irq.funcs = &gfx_v10_0_priv_inst_irq_funcs;
9354 }
9355
9356 static void gfx_v10_0_set_rlc_funcs(struct amdgpu_device *adev)
9357 {
9358         switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
9359         case IP_VERSION(10, 1, 10):
9360         case IP_VERSION(10, 1, 1):
9361         case IP_VERSION(10, 1, 3):
9362         case IP_VERSION(10, 1, 4):
9363         case IP_VERSION(10, 3, 2):
9364         case IP_VERSION(10, 3, 1):
9365         case IP_VERSION(10, 3, 4):
9366         case IP_VERSION(10, 3, 5):
9367         case IP_VERSION(10, 3, 6):
9368         case IP_VERSION(10, 3, 3):
9369         case IP_VERSION(10, 3, 7):
9370                 adev->gfx.rlc.funcs = &gfx_v10_0_rlc_funcs;
9371                 break;
9372         case IP_VERSION(10, 1, 2):
9373         case IP_VERSION(10, 3, 0):
9374                 adev->gfx.rlc.funcs = &gfx_v10_0_rlc_funcs_sriov;
9375                 break;
9376         default:
9377                 break;
9378         }
9379 }
9380
9381 static void gfx_v10_0_set_gds_init(struct amdgpu_device *adev)
9382 {
9383         unsigned int total_cu = adev->gfx.config.max_cu_per_sh *
9384                             adev->gfx.config.max_sh_per_se *
9385                             adev->gfx.config.max_shader_engines;
9386
9387         adev->gds.gds_size = 0x10000;
9388         adev->gds.gds_compute_max_wave_id = total_cu * 32 - 1;
9389         adev->gds.gws_size = 64;
9390         adev->gds.oa_size = 16;
9391 }
9392
9393 static void gfx_v10_0_set_mqd_funcs(struct amdgpu_device *adev)
9394 {
9395         /* set gfx eng mqd */
9396         adev->mqds[AMDGPU_HW_IP_GFX].mqd_size =
9397                 sizeof(struct v10_gfx_mqd);
9398         adev->mqds[AMDGPU_HW_IP_GFX].init_mqd =
9399                 gfx_v10_0_gfx_mqd_init;
9400         /* set compute eng mqd */
9401         adev->mqds[AMDGPU_HW_IP_COMPUTE].mqd_size =
9402                 sizeof(struct v10_compute_mqd);
9403         adev->mqds[AMDGPU_HW_IP_COMPUTE].init_mqd =
9404                 gfx_v10_0_compute_mqd_init;
9405 }
9406
9407 static void gfx_v10_0_set_user_wgp_inactive_bitmap_per_sh(struct amdgpu_device *adev,
9408                                                           u32 bitmap)
9409 {
9410         u32 data;
9411
9412         if (!bitmap)
9413                 return;
9414
9415         data = bitmap << GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT;
9416         data &= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK;
9417
9418         WREG32_SOC15(GC, 0, mmGC_USER_SHADER_ARRAY_CONFIG, data);
9419 }
9420
9421 static u32 gfx_v10_0_get_wgp_active_bitmap_per_sh(struct amdgpu_device *adev)
9422 {
9423         u32 disabled_mask =
9424                 ~amdgpu_gfx_create_bitmask(adev->gfx.config.max_cu_per_sh >> 1);
9425         u32 efuse_setting = 0;
9426         u32 vbios_setting = 0;
9427
9428         efuse_setting = RREG32_SOC15(GC, 0, mmCC_GC_SHADER_ARRAY_CONFIG);
9429         efuse_setting &= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK;
9430         efuse_setting >>= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT;
9431
9432         vbios_setting = RREG32_SOC15(GC, 0, mmGC_USER_SHADER_ARRAY_CONFIG);
9433         vbios_setting &= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK;
9434         vbios_setting >>= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT;
9435
9436         disabled_mask |= efuse_setting | vbios_setting;
9437
9438         return (~disabled_mask);
9439 }
9440
9441 static u32 gfx_v10_0_get_cu_active_bitmap_per_sh(struct amdgpu_device *adev)
9442 {
9443         u32 wgp_idx, wgp_active_bitmap;
9444         u32 cu_bitmap_per_wgp, cu_active_bitmap;
9445
9446         wgp_active_bitmap = gfx_v10_0_get_wgp_active_bitmap_per_sh(adev);
9447         cu_active_bitmap = 0;
9448
9449         for (wgp_idx = 0; wgp_idx < 16; wgp_idx++) {
9450                 /* if there is one WGP enabled, it means 2 CUs will be enabled */
9451                 cu_bitmap_per_wgp = 3 << (2 * wgp_idx);
9452                 if (wgp_active_bitmap & (1 << wgp_idx))
9453                         cu_active_bitmap |= cu_bitmap_per_wgp;
9454         }
9455
9456         return cu_active_bitmap;
9457 }
9458
9459 static int gfx_v10_0_get_cu_info(struct amdgpu_device *adev,
9460                                  struct amdgpu_cu_info *cu_info)
9461 {
9462         int i, j, k, counter, active_cu_number = 0;
9463         u32 mask, bitmap, ao_bitmap, ao_cu_mask = 0;
9464         unsigned int disable_masks[4 * 2];
9465
9466         if (!adev || !cu_info)
9467                 return -EINVAL;
9468
9469         amdgpu_gfx_parse_disable_cu(disable_masks, 4, 2);
9470
9471         mutex_lock(&adev->grbm_idx_mutex);
9472         for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
9473                 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
9474                         bitmap = i * adev->gfx.config.max_sh_per_se + j;
9475                         if (((amdgpu_ip_version(adev, GC_HWIP, 0) ==
9476                               IP_VERSION(10, 3, 0)) ||
9477                              (amdgpu_ip_version(adev, GC_HWIP, 0) ==
9478                               IP_VERSION(10, 3, 3)) ||
9479                              (amdgpu_ip_version(adev, GC_HWIP, 0) ==
9480                               IP_VERSION(10, 3, 6)) ||
9481                              (amdgpu_ip_version(adev, GC_HWIP, 0) ==
9482                               IP_VERSION(10, 3, 7))) &&
9483                             ((gfx_v10_3_get_disabled_sa(adev) >> bitmap) & 1))
9484                                 continue;
9485                         mask = 1;
9486                         ao_bitmap = 0;
9487                         counter = 0;
9488                         gfx_v10_0_select_se_sh(adev, i, j, 0xffffffff, 0);
9489                         if (i < 4 && j < 2)
9490                                 gfx_v10_0_set_user_wgp_inactive_bitmap_per_sh(
9491                                         adev, disable_masks[i * 2 + j]);
9492                         bitmap = gfx_v10_0_get_cu_active_bitmap_per_sh(adev);
9493                         cu_info->bitmap[0][i][j] = bitmap;
9494
9495                         for (k = 0; k < adev->gfx.config.max_cu_per_sh; k++) {
9496                                 if (bitmap & mask) {
9497                                         if (counter < adev->gfx.config.max_cu_per_sh)
9498                                                 ao_bitmap |= mask;
9499                                         counter++;
9500                                 }
9501                                 mask <<= 1;
9502                         }
9503                         active_cu_number += counter;
9504                         if (i < 2 && j < 2)
9505                                 ao_cu_mask |= (ao_bitmap << (i * 16 + j * 8));
9506                         cu_info->ao_cu_bitmap[i][j] = ao_bitmap;
9507                 }
9508         }
9509         gfx_v10_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0);
9510         mutex_unlock(&adev->grbm_idx_mutex);
9511
9512         cu_info->number = active_cu_number;
9513         cu_info->ao_cu_mask = ao_cu_mask;
9514         cu_info->simd_per_cu = NUM_SIMD_PER_CU;
9515
9516         return 0;
9517 }
9518
9519 static u32 gfx_v10_3_get_disabled_sa(struct amdgpu_device *adev)
9520 {
9521         uint32_t efuse_setting, vbios_setting, disabled_sa, max_sa_mask;
9522
9523         efuse_setting = RREG32_SOC15(GC, 0, mmCC_GC_SA_UNIT_DISABLE);
9524         efuse_setting &= CC_GC_SA_UNIT_DISABLE__SA_DISABLE_MASK;
9525         efuse_setting >>= CC_GC_SA_UNIT_DISABLE__SA_DISABLE__SHIFT;
9526
9527         vbios_setting = RREG32_SOC15(GC, 0, mmGC_USER_SA_UNIT_DISABLE);
9528         vbios_setting &= GC_USER_SA_UNIT_DISABLE__SA_DISABLE_MASK;
9529         vbios_setting >>= GC_USER_SA_UNIT_DISABLE__SA_DISABLE__SHIFT;
9530
9531         max_sa_mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_sh_per_se *
9532                                                 adev->gfx.config.max_shader_engines);
9533         disabled_sa = efuse_setting | vbios_setting;
9534         disabled_sa &= max_sa_mask;
9535
9536         return disabled_sa;
9537 }
9538
9539 static void gfx_v10_3_program_pbb_mode(struct amdgpu_device *adev)
9540 {
9541         uint32_t max_sa_per_se, max_sa_per_se_mask, max_shader_engines;
9542         uint32_t disabled_sa_mask, se_index, disabled_sa_per_se;
9543
9544         disabled_sa_mask = gfx_v10_3_get_disabled_sa(adev);
9545
9546         max_sa_per_se = adev->gfx.config.max_sh_per_se;
9547         max_sa_per_se_mask = (1 << max_sa_per_se) - 1;
9548         max_shader_engines = adev->gfx.config.max_shader_engines;
9549
9550         for (se_index = 0; max_shader_engines > se_index; se_index++) {
9551                 disabled_sa_per_se = disabled_sa_mask >> (se_index * max_sa_per_se);
9552                 disabled_sa_per_se &= max_sa_per_se_mask;
9553                 if (disabled_sa_per_se == max_sa_per_se_mask) {
9554                         WREG32_FIELD15(GC, 0, PA_SC_ENHANCE_3, FORCE_PBB_WORKLOAD_MODE_TO_ZERO, 1);
9555                         break;
9556                 }
9557         }
9558 }
9559
9560 static void gfx_v10_3_set_power_brake_sequence(struct amdgpu_device *adev)
9561 {
9562         WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX,
9563                      (0x1 << GRBM_GFX_INDEX__SA_BROADCAST_WRITES__SHIFT) |
9564                      (0x1 << GRBM_GFX_INDEX__INSTANCE_BROADCAST_WRITES__SHIFT) |
9565                      (0x1 << GRBM_GFX_INDEX__SE_BROADCAST_WRITES__SHIFT));
9566
9567         WREG32_SOC15(GC, 0, mmGC_CAC_IND_INDEX, ixPWRBRK_STALL_PATTERN_CTRL);
9568         WREG32_SOC15(GC, 0, mmGC_CAC_IND_DATA,
9569                      (0x1 << PWRBRK_STALL_PATTERN_CTRL__PWRBRK_STEP_INTERVAL__SHIFT) |
9570                      (0x12 << PWRBRK_STALL_PATTERN_CTRL__PWRBRK_BEGIN_STEP__SHIFT) |
9571                      (0x13 << PWRBRK_STALL_PATTERN_CTRL__PWRBRK_END_STEP__SHIFT) |
9572                      (0xf << PWRBRK_STALL_PATTERN_CTRL__PWRBRK_THROTTLE_PATTERN_BIT_NUMS__SHIFT));
9573
9574         WREG32_SOC15(GC, 0, mmGC_THROTTLE_CTRL_Sienna_Cichlid,
9575                      (0x1 << GC_THROTTLE_CTRL__PWRBRK_STALL_EN__SHIFT) |
9576                      (0x1 << GC_THROTTLE_CTRL__PATTERN_MODE__SHIFT) |
9577                      (0x5 << GC_THROTTLE_CTRL__RELEASE_STEP_INTERVAL__SHIFT));
9578
9579         WREG32_SOC15(GC, 0, mmDIDT_IND_INDEX, ixDIDT_SQ_THROTTLE_CTRL);
9580
9581         WREG32_SOC15(GC, 0, mmDIDT_IND_DATA,
9582                      (0x1 << DIDT_SQ_THROTTLE_CTRL__PWRBRK_STALL_EN__SHIFT));
9583 }
9584
9585 const struct amdgpu_ip_block_version gfx_v10_0_ip_block = {
9586         .type = AMD_IP_BLOCK_TYPE_GFX,
9587         .major = 10,
9588         .minor = 0,
9589         .rev = 0,
9590         .funcs = &gfx_v10_0_ip_funcs,
9591 };