drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

   1 /*
   2  * Copyright 2019 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #include <linux/delay.h>
  25 #include <linux/kernel.h>
  26 #include <linux/firmware.h>
  27 #include <linux/module.h>
  28 #include <linux/pci.h>
  29 #include "amdgpu.h"
  30 #include "amdgpu_gfx.h"
  31 #include "amdgpu_psp.h"
  32 #include "amdgpu_smu.h"
  33 #include "nv.h"
  34 #include "nvd.h"
  35
  36 #include "gc/gc_10_1_0_offset.h"
  37 #include "gc/gc_10_1_0_sh_mask.h"
  38 #include "navi10_enum.h"
  39 #include "hdp/hdp_5_0_0_offset.h"
  40 #include "ivsrcid/gfx/irqsrcs_gfx_10_1.h"
  41
  42 #include "soc15.h"
  43 #include "soc15d.h"
  44 #include "soc15_common.h"
  45 #include "clearstate_gfx10.h"
  46 #include "v10_structs.h"
  47 #include "gfx_v10_0.h"
  48 #include "nbio_v2_3.h"
  49
  50 /**
  51  * Navi10 has two graphic rings to share each graphic pipe.
  52  * 1. Primary ring
  53  * 2. Async ring
  54  */
  55 #define GFX10_NUM_GFX_RINGS     2
  56 #define GFX10_MEC_HPD_SIZE      2048
  57
  58 #define F32_CE_PROGRAM_RAM_SIZE         65536
  59 #define RLCG_UCODE_LOADING_START_ADDRESS        0x00002000L
  60
  61 #define mmCGTT_GS_NGG_CLK_CTRL  0x5087
  62 #define mmCGTT_GS_NGG_CLK_CTRL_BASE_IDX 1
  63
  64 MODULE_FIRMWARE("amdgpu/navi10_ce.bin");
  65 MODULE_FIRMWARE("amdgpu/navi10_pfp.bin");
  66 MODULE_FIRMWARE("amdgpu/navi10_me.bin");
  67 MODULE_FIRMWARE("amdgpu/navi10_mec.bin");
  68 MODULE_FIRMWARE("amdgpu/navi10_mec2.bin");
  69 MODULE_FIRMWARE("amdgpu/navi10_rlc.bin");
  70
  71 MODULE_FIRMWARE("amdgpu/navi14_ce_wks.bin");
  72 MODULE_FIRMWARE("amdgpu/navi14_pfp_wks.bin");
  73 MODULE_FIRMWARE("amdgpu/navi14_me_wks.bin");
  74 MODULE_FIRMWARE("amdgpu/navi14_mec_wks.bin");
  75 MODULE_FIRMWARE("amdgpu/navi14_mec2_wks.bin");
  76 MODULE_FIRMWARE("amdgpu/navi14_ce.bin");
  77 MODULE_FIRMWARE("amdgpu/navi14_pfp.bin");
  78 MODULE_FIRMWARE("amdgpu/navi14_me.bin");
  79 MODULE_FIRMWARE("amdgpu/navi14_mec.bin");
  80 MODULE_FIRMWARE("amdgpu/navi14_mec2.bin");
  81 MODULE_FIRMWARE("amdgpu/navi14_rlc.bin");
  82
  83 MODULE_FIRMWARE("amdgpu/navi12_ce.bin");
  84 MODULE_FIRMWARE("amdgpu/navi12_pfp.bin");
  85 MODULE_FIRMWARE("amdgpu/navi12_me.bin");
  86 MODULE_FIRMWARE("amdgpu/navi12_mec.bin");
  87 MODULE_FIRMWARE("amdgpu/navi12_mec2.bin");
  88 MODULE_FIRMWARE("amdgpu/navi12_rlc.bin");
  89
  90 static const struct soc15_reg_golden golden_settings_gc_10_1[] =
  91 {
  92         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0xffffffff, 0x00400014),
  93         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_CPF_CLK_CTRL, 0xfcff8fff, 0xf8000100),
  94         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xcd000000, 0x0d000100),
  95         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQ_CLK_CTRL, 0x60000ff0, 0x60000100),
  96         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQG_CLK_CTRL, 0x40000000, 0x40000100),
  97         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xffff8fff, 0xffff8100),
  98         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_WD_CLK_CTRL, 0xfeff8fff, 0xfeff8100),
  99         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
 100         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_VC5_ENABLE, 0x00000002, 0x00000000),
 101         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0x000007ff, 0x000005ff),
 102         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG, 0x20000000, 0x20000000),
 103         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xffffffff, 0x00000420),
 104         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0x00000200, 0x00000200),
 105         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0x07900000, 0x04900000),
 106         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DFSM_TILES_IN_FLIGHT, 0x0000ffff, 0x0000003f),
 107         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_LAST_OF_BURST_CONFIG, 0xffffffff, 0x03860204),
 108         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff0ffff, 0x00000500),
 109         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PRIV_CONTROL, 0x000007ff, 0x000001fe),
 110         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
 111         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x10321032),
 112         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x02310231),
 113         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
 114         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
 115         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CGTT_SCLK_CTRL, 0x10000000, 0x10000100),
 116         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL2, 0xffffffff, 0x1402002f),
 117         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xffff9fff, 0x00001188),
 118         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
 119         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x08000009),
 120         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0x00400000, 0x04440000),
 121         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0x00000800, 0x00000820),
 122         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000),
 123         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0xffffffff, 0xffff3101),
 124         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0x001f0000, 0x00070104),
 125         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ALU_CLK_CTRL, 0xffffffff, 0xffffffff),
 126         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x00000100, 0x00000130),
 127         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0xffffffff, 0xffffffff),
 128         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
 129         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CNTL, 0x60000010, 0x479c0010),
 130         SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CGTT_CLK_CTRL, 0xfeff0fff, 0x40000100),
 131         SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0x00c00000, 0x00c00000)
 132 };
 133
 134 static const struct soc15_reg_golden golden_settings_gc_10_0_nv10[] =
 135 {
 136         /* Pending on emulation bring up */
 137 };
 138
 139 static const struct soc15_reg_golden golden_settings_gc_10_1_1[] =
 140 {
 141         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0xffffffff, 0x003c0014),
 142         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_GS_NGG_CLK_CTRL, 0xffff8fff, 0xffff8100),
 143         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_IA_CLK_CTRL, 0xffff0fff, 0xffff0100),
 144         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xcd000000, 0x0d000100),
 145         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQ_CLK_CTRL, 0xf8ff0fff, 0x60000100),
 146         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQG_CLK_CTRL, 0x40000ff0, 0x40000100),
 147         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xffff8fff, 0xffff8100),
 148         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_WD_CLK_CTRL, 0xffff8fff, 0xffff8100),
 149         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
 150         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_VC5_ENABLE, 0x00000002, 0x00000000),
 151         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0x800007ff, 0x000005ff),
 152         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG, 0xffffffff, 0x20000000),
 153         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xffffffff, 0x00000420),
 154         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0x00000200, 0x00000200),
 155         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x04900000),
 156         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DFSM_TILES_IN_FLIGHT, 0x0000ffff, 0x0000003f),
 157         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_LAST_OF_BURST_CONFIG, 0xffffffff, 0x03860204),
 158         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff0ffff, 0x00000500),
 159         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PRIV_CONTROL, 0x000007ff, 0x000001fe),
 160         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
 161         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffe7),
 162         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffe7),
 163         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CGTT_SCLK_CTRL, 0xffff0fff, 0x10000100),
 164         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL2, 0xffffffff, 0x1402002f),
 165         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xffffbfff, 0x00000188),
 166         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
 167         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x08000009),
 168         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0x00400000, 0x04440000),
 169         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0x00000800, 0x00000820),
 170         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000),
 171         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0xffffffff, 0xffff3101),
 172         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0x001f0000, 0x00070105),
 173         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ALU_CLK_CTRL, 0xffffffff, 0xffffffff),
 174         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x00000133, 0x00000130),
 175         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0xffffffff, 0xffffffff),
 176         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
 177         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CNTL, 0x60000010, 0x479c0010),
 178         SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0x00c00000, 0x00c00000),
 179 };
 180
 181 static const struct soc15_reg_golden golden_settings_gc_10_1_2[] =
 182 {
 183         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0x003e001f, 0x003c0014),
 184         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_GS_NGG_CLK_CTRL, 0xffff8fff, 0xffff8100),
 185         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_IA_CLK_CTRL, 0xffff0fff, 0xffff0100),
 186         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xff7f0fff, 0x0d000100),
 187         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQ_CLK_CTRL, 0xffffcfff, 0x60000100),
 188         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQG_CLK_CTRL, 0xffff0fff, 0x40000100),
 189         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xffff8fff, 0xffff8100),
 190         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_WD_CLK_CTRL, 0xffff8fff, 0xffff8100),
 191         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
 192         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_VC5_ENABLE, 0x00000003, 0x00000000),
 193         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0x800007ff, 0x000005ff),
 194         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG, 0xffffffff, 0x20000000),
 195         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xffffffff, 0x00000420),
 196         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000200),
 197         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x04800000),
 198         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DFSM_TILES_IN_FLIGHT, 0x0000ffff, 0x0000003f),
 199         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_LAST_OF_BURST_CONFIG, 0xffffffff, 0x03860204),
 200         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff0ffff, 0x00000500),
 201         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PRIV_CONTROL, 0x00007fff, 0x000001fe),
 202         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
 203         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x10321032),
 204         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x02310231),
 205         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
 206         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
 207         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CGTT_SCLK_CTRL, 0xffff0fff, 0x10000100),
 208         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL2, 0xffffffff, 0x1402002f),
 209         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xffffbfff, 0x00000188),
 210         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_0, 0xffffffff, 0x842a4c02),
 211         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
 212         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x08000009),
 213         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0xffffffff, 0x04440000),
 214         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0x00000820, 0x00000820),
 215         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000),
 216         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0xffffffff, 0xffff3101),
 217         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ALU_CLK_CTRL, 0xffffffff, 0xffffffff),
 218         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x00000133, 0x00000130),
 219         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0xffffffff, 0xffffffff),
 220         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
 221         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CNTL, 0xffdf80ff, 0x479c0010),
 222         SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffffffff, 0x00800000)
 223 };
 224
 225 static const struct soc15_reg_golden golden_settings_gc_10_1_nv14[] =
 226 {
 227         /* Pending on emulation bring up */
 228 };
 229
 230 static const struct soc15_reg_golden golden_settings_gc_10_1_2_nv12[] =
 231 {
 232         /* Pending on emulation bring up */
 233 };
 234
 235 #define DEFAULT_SH_MEM_CONFIG \
 236         ((SH_MEM_ADDRESS_MODE_64 << SH_MEM_CONFIG__ADDRESS_MODE__SHIFT) | \
 237          (SH_MEM_ALIGNMENT_MODE_UNALIGNED << SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT) | \
 238          (SH_MEM_RETRY_MODE_ALL << SH_MEM_CONFIG__RETRY_MODE__SHIFT) | \
 239          (3 << SH_MEM_CONFIG__INITIAL_INST_PREFETCH__SHIFT))
 240
 241
 242 static void gfx_v10_0_set_ring_funcs(struct amdgpu_device *adev);
 243 static void gfx_v10_0_set_irq_funcs(struct amdgpu_device *adev);
 244 static void gfx_v10_0_set_gds_init(struct amdgpu_device *adev);
 245 static void gfx_v10_0_set_rlc_funcs(struct amdgpu_device *adev);
 246 static int gfx_v10_0_get_cu_info(struct amdgpu_device *adev,
 247                                  struct amdgpu_cu_info *cu_info);
 248 static uint64_t gfx_v10_0_get_gpu_clock_counter(struct amdgpu_device *adev);
 249 static void gfx_v10_0_select_se_sh(struct amdgpu_device *adev, u32 se_num,
 250                                    u32 sh_num, u32 instance);
 251 static u32 gfx_v10_0_get_wgp_active_bitmap_per_sh(struct amdgpu_device *adev);
 252
 253 static int gfx_v10_0_rlc_backdoor_autoload_buffer_init(struct amdgpu_device *adev);
 254 static void gfx_v10_0_rlc_backdoor_autoload_buffer_fini(struct amdgpu_device *adev);
 255 static int gfx_v10_0_rlc_backdoor_autoload_enable(struct amdgpu_device *adev);
 256 static int gfx_v10_0_wait_for_rlc_autoload_complete(struct amdgpu_device *adev);
 257 static void gfx_v10_0_ring_emit_ce_meta(struct amdgpu_ring *ring, bool resume);
 258 static void gfx_v10_0_ring_emit_de_meta(struct amdgpu_ring *ring, bool resume);
 259 static void gfx_v10_0_ring_emit_tmz(struct amdgpu_ring *ring, bool start);
 260
 261 static void gfx10_kiq_set_resources(struct amdgpu_ring *kiq_ring, uint64_t queue_mask)
 262 {
 263         amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_RESOURCES, 6));
 264         amdgpu_ring_write(kiq_ring, PACKET3_SET_RESOURCES_VMID_MASK(0) |
 265                           PACKET3_SET_RESOURCES_QUEUE_TYPE(0)); /* vmid_mask:0 queue_type:0 (KIQ) */
 266         amdgpu_ring_write(kiq_ring, lower_32_bits(queue_mask)); /* queue mask lo */
 267         amdgpu_ring_write(kiq_ring, upper_32_bits(queue_mask)); /* queue mask hi */
 268         amdgpu_ring_write(kiq_ring, 0); /* gws mask lo */
 269         amdgpu_ring_write(kiq_ring, 0); /* gws mask hi */
 270         amdgpu_ring_write(kiq_ring, 0); /* oac mask */
 271         amdgpu_ring_write(kiq_ring, 0); /* gds heap base:0, gds heap size:0 */
 272 }
 273
 274 static void gfx10_kiq_map_queues(struct amdgpu_ring *kiq_ring,
 275                                  struct amdgpu_ring *ring)
 276 {
 277         struct amdgpu_device *adev = kiq_ring->adev;
 278         uint64_t mqd_addr = amdgpu_bo_gpu_offset(ring->mqd_obj);
 279         uint64_t wptr_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
 280         uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0;
 281
 282         amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5));
 283         /* Q_sel:0, vmid:0, vidmem: 1, engine:0, num_Q:1*/
 284         amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */
 285                           PACKET3_MAP_QUEUES_QUEUE_SEL(0) | /* Queue_Sel */
 286                           PACKET3_MAP_QUEUES_VMID(0) | /* VMID */
 287                           PACKET3_MAP_QUEUES_QUEUE(ring->queue) |
 288                           PACKET3_MAP_QUEUES_PIPE(ring->pipe) |
 289                           PACKET3_MAP_QUEUES_ME((ring->me == 1 ? 0 : 1)) |
 290                           PACKET3_MAP_QUEUES_QUEUE_TYPE(0) | /*queue_type: normal compute queue */
 291                           PACKET3_MAP_QUEUES_ALLOC_FORMAT(0) | /* alloc format: all_on_one_pipe */
 292                           PACKET3_MAP_QUEUES_ENGINE_SEL(eng_sel) |
 293                           PACKET3_MAP_QUEUES_NUM_QUEUES(1)); /* num_queues: must be 1 */
 294         amdgpu_ring_write(kiq_ring, PACKET3_MAP_QUEUES_DOORBELL_OFFSET(ring->doorbell_index));
 295         amdgpu_ring_write(kiq_ring, lower_32_bits(mqd_addr));
 296         amdgpu_ring_write(kiq_ring, upper_32_bits(mqd_addr));
 297         amdgpu_ring_write(kiq_ring, lower_32_bits(wptr_addr));
 298         amdgpu_ring_write(kiq_ring, upper_32_bits(wptr_addr));
 299 }
 300
 301 static void gfx10_kiq_unmap_queues(struct amdgpu_ring *kiq_ring,
 302                                    struct amdgpu_ring *ring,
 303                                    enum amdgpu_unmap_queues_action action,
 304                                    u64 gpu_addr, u64 seq)
 305 {
 306         uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0;
 307
 308         amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_UNMAP_QUEUES, 4));
 309         amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */
 310                           PACKET3_UNMAP_QUEUES_ACTION(action) |
 311                           PACKET3_UNMAP_QUEUES_QUEUE_SEL(0) |
 312                           PACKET3_UNMAP_QUEUES_ENGINE_SEL(eng_sel) |
 313                           PACKET3_UNMAP_QUEUES_NUM_QUEUES(1));
 314         amdgpu_ring_write(kiq_ring,
 315                   PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET0(ring->doorbell_index));
 316
 317         if (action == PREEMPT_QUEUES_NO_UNMAP) {
 318                 amdgpu_ring_write(kiq_ring, lower_32_bits(gpu_addr));
 319                 amdgpu_ring_write(kiq_ring, upper_32_bits(gpu_addr));
 320                 amdgpu_ring_write(kiq_ring, seq);
 321         } else {
 322                 amdgpu_ring_write(kiq_ring, 0);
 323                 amdgpu_ring_write(kiq_ring, 0);
 324                 amdgpu_ring_write(kiq_ring, 0);
 325         }
 326 }
 327
 328 static void gfx10_kiq_query_status(struct amdgpu_ring *kiq_ring,
 329                                    struct amdgpu_ring *ring,
 330                                    u64 addr,
 331                                    u64 seq)
 332 {
 333         uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0;
 334
 335         amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_QUERY_STATUS, 5));
 336         amdgpu_ring_write(kiq_ring,
 337                           PACKET3_QUERY_STATUS_CONTEXT_ID(0) |
 338                           PACKET3_QUERY_STATUS_INTERRUPT_SEL(0) |
 339                           PACKET3_QUERY_STATUS_COMMAND(2));
 340         amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */
 341                           PACKET3_QUERY_STATUS_DOORBELL_OFFSET(ring->doorbell_index) |
 342                           PACKET3_QUERY_STATUS_ENG_SEL(eng_sel));
 343         amdgpu_ring_write(kiq_ring, lower_32_bits(addr));
 344         amdgpu_ring_write(kiq_ring, upper_32_bits(addr));
 345         amdgpu_ring_write(kiq_ring, lower_32_bits(seq));
 346         amdgpu_ring_write(kiq_ring, upper_32_bits(seq));
 347 }
 348
 349 static void gfx10_kiq_invalidate_tlbs(struct amdgpu_ring *kiq_ring,
 350                                 uint16_t pasid, uint32_t flush_type,
 351                                 bool all_hub)
 352 {
 353         amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_INVALIDATE_TLBS, 0));
 354         amdgpu_ring_write(kiq_ring,
 355                         PACKET3_INVALIDATE_TLBS_DST_SEL(1) |
 356                         PACKET3_INVALIDATE_TLBS_ALL_HUB(all_hub) |
 357                         PACKET3_INVALIDATE_TLBS_PASID(pasid) |
 358                         PACKET3_INVALIDATE_TLBS_FLUSH_TYPE(flush_type));
 359 }
 360
 361 static const struct kiq_pm4_funcs gfx_v10_0_kiq_pm4_funcs = {
 362         .kiq_set_resources = gfx10_kiq_set_resources,
 363         .kiq_map_queues = gfx10_kiq_map_queues,
 364         .kiq_unmap_queues = gfx10_kiq_unmap_queues,
 365         .kiq_query_status = gfx10_kiq_query_status,
 366         .kiq_invalidate_tlbs = gfx10_kiq_invalidate_tlbs,
 367         .set_resources_size = 8,
 368         .map_queues_size = 7,
 369         .unmap_queues_size = 6,
 370         .query_status_size = 7,
 371         .invalidate_tlbs_size = 2,
 372 };
 373
 374 static void gfx_v10_0_set_kiq_pm4_funcs(struct amdgpu_device *adev)
 375 {
 376         adev->gfx.kiq.pmf = &gfx_v10_0_kiq_pm4_funcs;
 377 }
 378
 379 static void gfx_v10_0_init_golden_registers(struct amdgpu_device *adev)
 380 {
 381         switch (adev->asic_type) {
 382         case CHIP_NAVI10:
 383                 soc15_program_register_sequence(adev,
 384                                                 golden_settings_gc_10_1,
 385                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_1));
 386                 soc15_program_register_sequence(adev,
 387                                                 golden_settings_gc_10_0_nv10,
 388                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_0_nv10));
 389                 break;
 390         case CHIP_NAVI14:
 391                 soc15_program_register_sequence(adev,
 392                                                 golden_settings_gc_10_1_1,
 393                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_1_1));
 394                 soc15_program_register_sequence(adev,
 395                                                 golden_settings_gc_10_1_nv14,
 396                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_1_nv14));
 397                 break;
 398         case CHIP_NAVI12:
 399                 soc15_program_register_sequence(adev,
 400                                                 golden_settings_gc_10_1_2,
 401                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_1_2));
 402                 soc15_program_register_sequence(adev,
 403                                                 golden_settings_gc_10_1_2_nv12,
 404                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_1_2_nv12));
 405                 break;
 406         default:
 407                 break;
 408         }
 409 }
 410
 411 static void gfx_v10_0_scratch_init(struct amdgpu_device *adev)
 412 {
 413         adev->gfx.scratch.num_reg = 8;
 414         adev->gfx.scratch.reg_base = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG0);
 415         adev->gfx.scratch.free_mask = (1u << adev->gfx.scratch.num_reg) - 1;
 416 }
 417
 418 static void gfx_v10_0_write_data_to_reg(struct amdgpu_ring *ring, int eng_sel,
 419                                        bool wc, uint32_t reg, uint32_t val)
 420 {
 421         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
 422         amdgpu_ring_write(ring, WRITE_DATA_ENGINE_SEL(eng_sel) |
 423                           WRITE_DATA_DST_SEL(0) | (wc ? WR_CONFIRM : 0));
 424         amdgpu_ring_write(ring, reg);
 425         amdgpu_ring_write(ring, 0);
 426         amdgpu_ring_write(ring, val);
 427 }
 428
 429 static void gfx_v10_0_wait_reg_mem(struct amdgpu_ring *ring, int eng_sel,
 430                                   int mem_space, int opt, uint32_t addr0,
 431                                   uint32_t addr1, uint32_t ref, uint32_t mask,
 432                                   uint32_t inv)
 433 {
 434         amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
 435         amdgpu_ring_write(ring,
 436                           /* memory (1) or register (0) */
 437                           (WAIT_REG_MEM_MEM_SPACE(mem_space) |
 438                            WAIT_REG_MEM_OPERATION(opt) | /* wait */
 439                            WAIT_REG_MEM_FUNCTION(3) |  /* equal */
 440                            WAIT_REG_MEM_ENGINE(eng_sel)));
 441
 442         if (mem_space)
 443                 BUG_ON(addr0 & 0x3); /* Dword align */
 444         amdgpu_ring_write(ring, addr0);
 445         amdgpu_ring_write(ring, addr1);
 446         amdgpu_ring_write(ring, ref);
 447         amdgpu_ring_write(ring, mask);
 448         amdgpu_ring_write(ring, inv); /* poll interval */
 449 }
 450
 451 static int gfx_v10_0_ring_test_ring(struct amdgpu_ring *ring)
 452 {
 453         struct amdgpu_device *adev = ring->adev;
 454         uint32_t scratch;
 455         uint32_t tmp = 0;
 456         unsigned i;
 457         int r;
 458
 459         r = amdgpu_gfx_scratch_get(adev, &scratch);
 460         if (r) {
 461                 DRM_ERROR("amdgpu: cp failed to get scratch reg (%d).\n", r);
 462                 return r;
 463         }
 464
 465         WREG32(scratch, 0xCAFEDEAD);
 466
 467         r = amdgpu_ring_alloc(ring, 3);
 468         if (r) {
 469                 DRM_ERROR("amdgpu: cp failed to lock ring %d (%d).\n",
 470                           ring->idx, r);
 471                 amdgpu_gfx_scratch_free(adev, scratch);
 472                 return r;
 473         }
 474
 475         amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1));
 476         amdgpu_ring_write(ring, (scratch - PACKET3_SET_UCONFIG_REG_START));
 477         amdgpu_ring_write(ring, 0xDEADBEEF);
 478         amdgpu_ring_commit(ring);
 479
 480         for (i = 0; i < adev->usec_timeout; i++) {
 481                 tmp = RREG32(scratch);
 482                 if (tmp == 0xDEADBEEF)
 483                         break;
 484                 if (amdgpu_emu_mode == 1)
 485                         msleep(1);
 486                 else
 487                         udelay(1);
 488         }
 489
 490         if (i >= adev->usec_timeout)
 491                 r = -ETIMEDOUT;
 492
 493         amdgpu_gfx_scratch_free(adev, scratch);
 494
 495         return r;
 496 }
 497
 498 static int gfx_v10_0_ring_test_ib(struct amdgpu_ring *ring, long timeout)
 499 {
 500         struct amdgpu_device *adev = ring->adev;
 501         struct amdgpu_ib ib;
 502         struct dma_fence *f = NULL;
 503         uint32_t scratch;
 504         uint32_t tmp = 0;
 505         long r;
 506
 507         r = amdgpu_gfx_scratch_get(adev, &scratch);
 508         if (r) {
 509                 DRM_ERROR("amdgpu: failed to get scratch reg (%ld).\n", r);
 510                 return r;
 511         }
 512
 513         WREG32(scratch, 0xCAFEDEAD);
 514
 515         memset(&ib, 0, sizeof(ib));
 516         r = amdgpu_ib_get(adev, NULL, 256, &ib);
 517         if (r) {
 518                 DRM_ERROR("amdgpu: failed to get ib (%ld).\n", r);
 519                 goto err1;
 520         }
 521
 522         ib.ptr[0] = PACKET3(PACKET3_SET_UCONFIG_REG, 1);
 523         ib.ptr[1] = ((scratch - PACKET3_SET_UCONFIG_REG_START));
 524         ib.ptr[2] = 0xDEADBEEF;
 525         ib.length_dw = 3;
 526
 527         r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
 528         if (r)
 529                 goto err2;
 530
 531         r = dma_fence_wait_timeout(f, false, timeout);
 532         if (r == 0) {
 533                 DRM_ERROR("amdgpu: IB test timed out.\n");
 534                 r = -ETIMEDOUT;
 535                 goto err2;
 536         } else if (r < 0) {
 537                 DRM_ERROR("amdgpu: fence wait failed (%ld).\n", r);
 538                 goto err2;
 539         }
 540
 541         tmp = RREG32(scratch);
 542         if (tmp == 0xDEADBEEF)
 543                 r = 0;
 544         else
 545                 r = -EINVAL;
 546 err2:
 547         amdgpu_ib_free(adev, &ib, NULL);
 548         dma_fence_put(f);
 549 err1:
 550         amdgpu_gfx_scratch_free(adev, scratch);
 551
 552         return r;
 553 }
 554
 555 static void gfx_v10_0_free_microcode(struct amdgpu_device *adev)
 556 {
 557         release_firmware(adev->gfx.pfp_fw);
 558         adev->gfx.pfp_fw = NULL;
 559         release_firmware(adev->gfx.me_fw);
 560         adev->gfx.me_fw = NULL;
 561         release_firmware(adev->gfx.ce_fw);
 562         adev->gfx.ce_fw = NULL;
 563         release_firmware(adev->gfx.rlc_fw);
 564         adev->gfx.rlc_fw = NULL;
 565         release_firmware(adev->gfx.mec_fw);
 566         adev->gfx.mec_fw = NULL;
 567         release_firmware(adev->gfx.mec2_fw);
 568         adev->gfx.mec2_fw = NULL;
 569
 570         kfree(adev->gfx.rlc.register_list_format);
 571 }
 572
 573 static void gfx_v10_0_check_fw_write_wait(struct amdgpu_device *adev)
 574 {
 575         adev->gfx.cp_fw_write_wait = false;
 576
 577         switch (adev->asic_type) {
 578         case CHIP_NAVI10:
 579         case CHIP_NAVI12:
 580         case CHIP_NAVI14:
 581                 if ((adev->gfx.me_fw_version >= 0x00000046) &&
 582                     (adev->gfx.me_feature_version >= 27) &&
 583                     (adev->gfx.pfp_fw_version >= 0x00000068) &&
 584                     (adev->gfx.pfp_feature_version >= 27) &&
 585                     (adev->gfx.mec_fw_version >= 0x0000005b) &&
 586                     (adev->gfx.mec_feature_version >= 27))
 587                         adev->gfx.cp_fw_write_wait = true;
 588                 break;
 589         default:
 590                 break;
 591         }
 592
 593         if (adev->gfx.cp_fw_write_wait == false)
 594                 DRM_WARN_ONCE("CP firmware version too old, please update!");
 595 }
 596
 597
 598 static void gfx_v10_0_init_rlc_ext_microcode(struct amdgpu_device *adev)
 599 {
 600         const struct rlc_firmware_header_v2_1 *rlc_hdr;
 601
 602         rlc_hdr = (const struct rlc_firmware_header_v2_1 *)adev->gfx.rlc_fw->data;
 603         adev->gfx.rlc_srlc_fw_version = le32_to_cpu(rlc_hdr->save_restore_list_cntl_ucode_ver);
 604         adev->gfx.rlc_srlc_feature_version = le32_to_cpu(rlc_hdr->save_restore_list_cntl_feature_ver);
 605         adev->gfx.rlc.save_restore_list_cntl_size_bytes = le32_to_cpu(rlc_hdr->save_restore_list_cntl_size_bytes);
 606         adev->gfx.rlc.save_restore_list_cntl = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_list_cntl_offset_bytes);
 607         adev->gfx.rlc_srlg_fw_version = le32_to_cpu(rlc_hdr->save_restore_list_gpm_ucode_ver);
 608         adev->gfx.rlc_srlg_feature_version = le32_to_cpu(rlc_hdr->save_restore_list_gpm_feature_ver);
 609         adev->gfx.rlc.save_restore_list_gpm_size_bytes = le32_to_cpu(rlc_hdr->save_restore_list_gpm_size_bytes);
 610         adev->gfx.rlc.save_restore_list_gpm = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_list_gpm_offset_bytes);
 611         adev->gfx.rlc_srls_fw_version = le32_to_cpu(rlc_hdr->save_restore_list_srm_ucode_ver);
 612         adev->gfx.rlc_srls_feature_version = le32_to_cpu(rlc_hdr->save_restore_list_srm_feature_ver);
 613         adev->gfx.rlc.save_restore_list_srm_size_bytes = le32_to_cpu(rlc_hdr->save_restore_list_srm_size_bytes);
 614         adev->gfx.rlc.save_restore_list_srm = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_list_srm_offset_bytes);
 615         adev->gfx.rlc.reg_list_format_direct_reg_list_length =
 616                         le32_to_cpu(rlc_hdr->reg_list_format_direct_reg_list_length);
 617 }
 618
 619 static bool gfx_v10_0_navi10_gfxoff_should_enable(struct amdgpu_device *adev)
 620 {
 621         bool ret = false;
 622
 623         switch (adev->pdev->revision) {
 624         case 0xc2:
 625         case 0xc3:
 626                 ret = true;
 627                 break;
 628         default:
 629                 ret = false;
 630                 break;
 631         }
 632
 633         return ret ;
 634 }
 635
 636 static void gfx_v10_0_check_gfxoff_flag(struct amdgpu_device *adev)
 637 {
 638         switch (adev->asic_type) {
 639         case CHIP_NAVI10:
 640                 if (!gfx_v10_0_navi10_gfxoff_should_enable(adev))
 641                         adev->pm.pp_feature &= ~PP_GFXOFF_MASK;
 642                 break;
 643         default:
 644                 break;
 645         }
 646 }
 647
 648 static int gfx_v10_0_init_microcode(struct amdgpu_device *adev)
 649 {
 650         const char *chip_name;
 651         char fw_name[40];
 652         char wks[10];
 653         int err;
 654         struct amdgpu_firmware_info *info = NULL;
 655         const struct common_firmware_header *header = NULL;
 656         const struct gfx_firmware_header_v1_0 *cp_hdr;
 657         const struct rlc_firmware_header_v2_0 *rlc_hdr;
 658         unsigned int *tmp = NULL;
 659         unsigned int i = 0;
 660         uint16_t version_major;
 661         uint16_t version_minor;
 662
 663         DRM_DEBUG("\n");
 664
 665         memset(wks, 0, sizeof(wks));
 666         switch (adev->asic_type) {
 667         case CHIP_NAVI10:
 668                 chip_name = "navi10";
 669                 break;
 670         case CHIP_NAVI14:
 671                 chip_name = "navi14";
 672                 if (!(adev->pdev->device == 0x7340 &&
 673                       adev->pdev->revision != 0x00))
 674                         snprintf(wks, sizeof(wks), "_wks");
 675                 break;
 676         case CHIP_NAVI12:
 677                 chip_name = "navi12";
 678                 break;
 679         default:
 680                 BUG();
 681         }
 682
 683         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_pfp%s.bin", chip_name, wks);
 684         err = request_firmware(&adev->gfx.pfp_fw, fw_name, adev->dev);
 685         if (err)
 686                 goto out;
 687         err = amdgpu_ucode_validate(adev->gfx.pfp_fw);
 688         if (err)
 689                 goto out;
 690         cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data;
 691         adev->gfx.pfp_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
 692         adev->gfx.pfp_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
 693
 694         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_me%s.bin", chip_name, wks);
 695         err = request_firmware(&adev->gfx.me_fw, fw_name, adev->dev);
 696         if (err)
 697                 goto out;
 698         err = amdgpu_ucode_validate(adev->gfx.me_fw);
 699         if (err)
 700                 goto out;
 701         cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data;
 702         adev->gfx.me_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
 703         adev->gfx.me_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
 704
 705         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ce%s.bin", chip_name, wks);
 706         err = request_firmware(&adev->gfx.ce_fw, fw_name, adev->dev);
 707         if (err)
 708                 goto out;
 709         err = amdgpu_ucode_validate(adev->gfx.ce_fw);
 710         if (err)
 711                 goto out;
 712         cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data;
 713         adev->gfx.ce_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
 714         adev->gfx.ce_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
 715
 716         if (!amdgpu_sriov_vf(adev)) {
 717                 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_rlc.bin", chip_name);
 718                 err = request_firmware(&adev->gfx.rlc_fw, fw_name, adev->dev);
 719                 if (err)
 720                         goto out;
 721                 err = amdgpu_ucode_validate(adev->gfx.rlc_fw);
 722                 rlc_hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data;
 723                 version_major = le16_to_cpu(rlc_hdr->header.header_version_major);
 724                 version_minor = le16_to_cpu(rlc_hdr->header.header_version_minor);
 725                 if (version_major == 2 && version_minor == 1)
 726                         adev->gfx.rlc.is_rlc_v2_1 = true;
 727
 728                 adev->gfx.rlc_fw_version = le32_to_cpu(rlc_hdr->header.ucode_version);
 729                 adev->gfx.rlc_feature_version = le32_to_cpu(rlc_hdr->ucode_feature_version);
 730                 adev->gfx.rlc.save_and_restore_offset =
 731                         le32_to_cpu(rlc_hdr->save_and_restore_offset);
 732                 adev->gfx.rlc.clear_state_descriptor_offset =
 733                         le32_to_cpu(rlc_hdr->clear_state_descriptor_offset);
 734                 adev->gfx.rlc.avail_scratch_ram_locations =
 735                         le32_to_cpu(rlc_hdr->avail_scratch_ram_locations);
 736                 adev->gfx.rlc.reg_restore_list_size =
 737                         le32_to_cpu(rlc_hdr->reg_restore_list_size);
 738                 adev->gfx.rlc.reg_list_format_start =
 739                         le32_to_cpu(rlc_hdr->reg_list_format_start);
 740                 adev->gfx.rlc.reg_list_format_separate_start =
 741                         le32_to_cpu(rlc_hdr->reg_list_format_separate_start);
 742                 adev->gfx.rlc.starting_offsets_start =
 743                         le32_to_cpu(rlc_hdr->starting_offsets_start);
 744                 adev->gfx.rlc.reg_list_format_size_bytes =
 745                         le32_to_cpu(rlc_hdr->reg_list_format_size_bytes);
 746                 adev->gfx.rlc.reg_list_size_bytes =
 747                         le32_to_cpu(rlc_hdr->reg_list_size_bytes);
 748                 adev->gfx.rlc.register_list_format =
 749                         kmalloc(adev->gfx.rlc.reg_list_format_size_bytes +
 750                                         adev->gfx.rlc.reg_list_size_bytes, GFP_KERNEL);
 751                 if (!adev->gfx.rlc.register_list_format) {
 752                         err = -ENOMEM;
 753                         goto out;
 754                 }
 755
 756                 tmp = (unsigned int *)((uintptr_t)rlc_hdr +
 757                                                            le32_to_cpu(rlc_hdr->reg_list_format_array_offset_bytes));
 758                 for (i = 0 ; i < (rlc_hdr->reg_list_format_size_bytes >> 2); i++)
 759                         adev->gfx.rlc.register_list_format[i] = le32_to_cpu(tmp[i]);
 760
 761                 adev->gfx.rlc.register_restore = adev->gfx.rlc.register_list_format + i;
 762
 763                 tmp = (unsigned int *)((uintptr_t)rlc_hdr +
 764                                                            le32_to_cpu(rlc_hdr->reg_list_array_offset_bytes));
 765                 for (i = 0 ; i < (rlc_hdr->reg_list_size_bytes >> 2); i++)
 766                         adev->gfx.rlc.register_restore[i] = le32_to_cpu(tmp[i]);
 767
 768                 if (adev->gfx.rlc.is_rlc_v2_1)
 769                         gfx_v10_0_init_rlc_ext_microcode(adev);
 770         }
 771
 772         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec%s.bin", chip_name, wks);
 773         err = request_firmware(&adev->gfx.mec_fw, fw_name, adev->dev);
 774         if (err)
 775                 goto out;
 776         err = amdgpu_ucode_validate(adev->gfx.mec_fw);
 777         if (err)
 778                 goto out;
 779         cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
 780         adev->gfx.mec_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
 781         adev->gfx.mec_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
 782
 783         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec2%s.bin", chip_name, wks);
 784         err = request_firmware(&adev->gfx.mec2_fw, fw_name, adev->dev);
 785         if (!err) {
 786                 err = amdgpu_ucode_validate(adev->gfx.mec2_fw);
 787                 if (err)
 788                         goto out;
 789                 cp_hdr = (const struct gfx_firmware_header_v1_0 *)
 790                 adev->gfx.mec2_fw->data;
 791                 adev->gfx.mec2_fw_version =
 792                 le32_to_cpu(cp_hdr->header.ucode_version);
 793                 adev->gfx.mec2_feature_version =
 794                 le32_to_cpu(cp_hdr->ucode_feature_version);
 795         } else {
 796                 err = 0;
 797                 adev->gfx.mec2_fw = NULL;
 798         }
 799
 800         if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
 801                 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_PFP];
 802                 info->ucode_id = AMDGPU_UCODE_ID_CP_PFP;
 803                 info->fw = adev->gfx.pfp_fw;
 804                 header = (const struct common_firmware_header *)info->fw->data;
 805                 adev->firmware.fw_size +=
 806                         ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
 807
 808                 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_ME];
 809                 info->ucode_id = AMDGPU_UCODE_ID_CP_ME;
 810                 info->fw = adev->gfx.me_fw;
 811                 header = (const struct common_firmware_header *)info->fw->data;
 812                 adev->firmware.fw_size +=
 813                         ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
 814
 815                 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_CE];
 816                 info->ucode_id = AMDGPU_UCODE_ID_CP_CE;
 817                 info->fw = adev->gfx.ce_fw;
 818                 header = (const struct common_firmware_header *)info->fw->data;
 819                 adev->firmware.fw_size +=
 820                         ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
 821
 822                 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_G];
 823                 info->ucode_id = AMDGPU_UCODE_ID_RLC_G;
 824                 info->fw = adev->gfx.rlc_fw;
 825                 if (info->fw) {
 826                         header = (const struct common_firmware_header *)info->fw->data;
 827                         adev->firmware.fw_size +=
 828                                 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
 829                 }
 830                 if (adev->gfx.rlc.is_rlc_v2_1 &&
 831                     adev->gfx.rlc.save_restore_list_cntl_size_bytes &&
 832                     adev->gfx.rlc.save_restore_list_gpm_size_bytes &&
 833                     adev->gfx.rlc.save_restore_list_srm_size_bytes) {
 834                         info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL];
 835                         info->ucode_id = AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL;
 836                         info->fw = adev->gfx.rlc_fw;
 837                         adev->firmware.fw_size +=
 838                                 ALIGN(adev->gfx.rlc.save_restore_list_cntl_size_bytes, PAGE_SIZE);
 839
 840                         info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM];
 841                         info->ucode_id = AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM;
 842                         info->fw = adev->gfx.rlc_fw;
 843                         adev->firmware.fw_size +=
 844                                 ALIGN(adev->gfx.rlc.save_restore_list_gpm_size_bytes, PAGE_SIZE);
 845
 846                         info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM];
 847                         info->ucode_id = AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM;
 848                         info->fw = adev->gfx.rlc_fw;
 849                         adev->firmware.fw_size +=
 850                                 ALIGN(adev->gfx.rlc.save_restore_list_srm_size_bytes, PAGE_SIZE);
 851                 }
 852
 853                 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC1];
 854                 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC1;
 855                 info->fw = adev->gfx.mec_fw;
 856                 header = (const struct common_firmware_header *)info->fw->data;
 857                 cp_hdr = (const struct gfx_firmware_header_v1_0 *)info->fw->data;
 858                 adev->firmware.fw_size +=
 859                         ALIGN(le32_to_cpu(header->ucode_size_bytes) -
 860                               le32_to_cpu(cp_hdr->jt_size) * 4, PAGE_SIZE);
 861
 862                 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC1_JT];
 863                 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC1_JT;
 864                 info->fw = adev->gfx.mec_fw;
 865                 adev->firmware.fw_size +=
 866                         ALIGN(le32_to_cpu(cp_hdr->jt_size) * 4, PAGE_SIZE);
 867
 868                 if (adev->gfx.mec2_fw) {
 869                         info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC2];
 870                         info->ucode_id = AMDGPU_UCODE_ID_CP_MEC2;
 871                         info->fw = adev->gfx.mec2_fw;
 872                         header = (const struct common_firmware_header *)info->fw->data;
 873                         cp_hdr = (const struct gfx_firmware_header_v1_0 *)info->fw->data;
 874                         adev->firmware.fw_size +=
 875                                 ALIGN(le32_to_cpu(header->ucode_size_bytes) -
 876                                       le32_to_cpu(cp_hdr->jt_size) * 4,
 877                                       PAGE_SIZE);
 878                         info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC2_JT];
 879                         info->ucode_id = AMDGPU_UCODE_ID_CP_MEC2_JT;
 880                         info->fw = adev->gfx.mec2_fw;
 881                         adev->firmware.fw_size +=
 882                                 ALIGN(le32_to_cpu(cp_hdr->jt_size) * 4,
 883                                       PAGE_SIZE);
 884                 }
 885         }
 886
 887         gfx_v10_0_check_fw_write_wait(adev);
 888 out:
 889         if (err) {
 890                 dev_err(adev->dev,
 891                         "gfx10: Failed to load firmware \"%s\"\n",
 892                         fw_name);
 893                 release_firmware(adev->gfx.pfp_fw);
 894                 adev->gfx.pfp_fw = NULL;
 895                 release_firmware(adev->gfx.me_fw);
 896                 adev->gfx.me_fw = NULL;
 897                 release_firmware(adev->gfx.ce_fw);
 898                 adev->gfx.ce_fw = NULL;
 899                 release_firmware(adev->gfx.rlc_fw);
 900                 adev->gfx.rlc_fw = NULL;
 901                 release_firmware(adev->gfx.mec_fw);
 902                 adev->gfx.mec_fw = NULL;
 903                 release_firmware(adev->gfx.mec2_fw);
 904                 adev->gfx.mec2_fw = NULL;
 905         }
 906
 907         gfx_v10_0_check_gfxoff_flag(adev);
 908
 909         return err;
 910 }
 911
 912 static u32 gfx_v10_0_get_csb_size(struct amdgpu_device *adev)
 913 {
 914         u32 count = 0;
 915         const struct cs_section_def *sect = NULL;
 916         const struct cs_extent_def *ext = NULL;
 917
 918         /* begin clear state */
 919         count += 2;
 920         /* context control state */
 921         count += 3;
 922
 923         for (sect = gfx10_cs_data; sect->section != NULL; ++sect) {
 924                 for (ext = sect->section; ext->extent != NULL; ++ext) {
 925                         if (sect->id == SECT_CONTEXT)
 926                                 count += 2 + ext->reg_count;
 927                         else
 928                                 return 0;
 929                 }
 930         }
 931
 932         /* set PA_SC_TILE_STEERING_OVERRIDE */
 933         count += 3;
 934         /* end clear state */
 935         count += 2;
 936         /* clear state */
 937         count += 2;
 938
 939         return count;
 940 }
 941
 942 static void gfx_v10_0_get_csb_buffer(struct amdgpu_device *adev,
 943                                     volatile u32 *buffer)
 944 {
 945         u32 count = 0, i;
 946         const struct cs_section_def *sect = NULL;
 947         const struct cs_extent_def *ext = NULL;
 948         int ctx_reg_offset;
 949
 950         if (adev->gfx.rlc.cs_data == NULL)
 951                 return;
 952         if (buffer == NULL)
 953                 return;
 954
 955         buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));
 956         buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
 957
 958         buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CONTEXT_CONTROL, 1));
 959         buffer[count++] = cpu_to_le32(0x80000000);
 960         buffer[count++] = cpu_to_le32(0x80000000);
 961
 962         for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) {
 963                 for (ext = sect->section; ext->extent != NULL; ++ext) {
 964                         if (sect->id == SECT_CONTEXT) {
 965                                 buffer[count++] =
 966                                         cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count));
 967                                 buffer[count++] = cpu_to_le32(ext->reg_index -
 968                                                 PACKET3_SET_CONTEXT_REG_START);
 969                                 for (i = 0; i < ext->reg_count; i++)
 970                                         buffer[count++] = cpu_to_le32(ext->extent[i]);
 971                         } else {
 972                                 return;
 973                         }
 974                 }
 975         }
 976
 977         ctx_reg_offset =
 978                 SOC15_REG_OFFSET(GC, 0, mmPA_SC_TILE_STEERING_OVERRIDE) - PACKET3_SET_CONTEXT_REG_START;
 979         buffer[count++] = cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, 1));
 980         buffer[count++] = cpu_to_le32(ctx_reg_offset);
 981         buffer[count++] = cpu_to_le32(adev->gfx.config.pa_sc_tile_steering_override);
 982
 983         buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));
 984         buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_END_CLEAR_STATE);
 985
 986         buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CLEAR_STATE, 0));
 987         buffer[count++] = cpu_to_le32(0);
 988 }
 989
 990 static void gfx_v10_0_rlc_fini(struct amdgpu_device *adev)
 991 {
 992         /* clear state block */
 993         amdgpu_bo_free_kernel(&adev->gfx.rlc.clear_state_obj,
 994                         &adev->gfx.rlc.clear_state_gpu_addr,
 995                         (void **)&adev->gfx.rlc.cs_ptr);
 996
 997         /* jump table block */
 998         amdgpu_bo_free_kernel(&adev->gfx.rlc.cp_table_obj,
 999                         &adev->gfx.rlc.cp_table_gpu_addr,
1000                         (void **)&adev->gfx.rlc.cp_table_ptr);
1001 }
1002
1003 static int gfx_v10_0_rlc_init(struct amdgpu_device *adev)
1004 {
1005         const struct cs_section_def *cs_data;
1006         int r;
1007
1008         adev->gfx.rlc.cs_data = gfx10_cs_data;
1009
1010         cs_data = adev->gfx.rlc.cs_data;
1011
1012         if (cs_data) {
1013                 /* init clear state block */
1014                 r = amdgpu_gfx_rlc_init_csb(adev);
1015                 if (r)
1016                         return r;
1017         }
1018
1019         /* init spm vmid with 0xf */
1020         if (adev->gfx.rlc.funcs->update_spm_vmid)
1021                 adev->gfx.rlc.funcs->update_spm_vmid(adev, 0xf);
1022
1023         return 0;
1024 }
1025
1026 static void gfx_v10_0_mec_fini(struct amdgpu_device *adev)
1027 {
1028         amdgpu_bo_free_kernel(&adev->gfx.mec.hpd_eop_obj, NULL, NULL);
1029         amdgpu_bo_free_kernel(&adev->gfx.mec.mec_fw_obj, NULL, NULL);
1030 }
1031
1032 static int gfx_v10_0_me_init(struct amdgpu_device *adev)
1033 {
1034         int r;
1035
1036         bitmap_zero(adev->gfx.me.queue_bitmap, AMDGPU_MAX_GFX_QUEUES);
1037
1038         amdgpu_gfx_graphics_queue_acquire(adev);
1039
1040         r = gfx_v10_0_init_microcode(adev);
1041         if (r)
1042                 DRM_ERROR("Failed to load gfx firmware!\n");
1043
1044         return r;
1045 }
1046
1047 static int gfx_v10_0_mec_init(struct amdgpu_device *adev)
1048 {
1049         int r;
1050         u32 *hpd;
1051         const __le32 *fw_data = NULL;
1052         unsigned fw_size;
1053         u32 *fw = NULL;
1054         size_t mec_hpd_size;
1055
1056         const struct gfx_firmware_header_v1_0 *mec_hdr = NULL;
1057
1058         bitmap_zero(adev->gfx.mec.queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES);
1059
1060         /* take ownership of the relevant compute queues */
1061         amdgpu_gfx_compute_queue_acquire(adev);
1062         mec_hpd_size = adev->gfx.num_compute_rings * GFX10_MEC_HPD_SIZE;
1063
1064         r = amdgpu_bo_create_reserved(adev, mec_hpd_size, PAGE_SIZE,
1065                                       AMDGPU_GEM_DOMAIN_GTT,
1066                                       &adev->gfx.mec.hpd_eop_obj,
1067                                       &adev->gfx.mec.hpd_eop_gpu_addr,
1068                                       (void **)&hpd);
1069         if (r) {
1070                 dev_warn(adev->dev, "(%d) create HDP EOP bo failed\n", r);
1071                 gfx_v10_0_mec_fini(adev);
1072                 return r;
1073         }
1074
1075         memset(hpd, 0, adev->gfx.mec.hpd_eop_obj->tbo.mem.size);
1076
1077         amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj);
1078         amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj);
1079
1080         if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
1081                 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
1082
1083                 fw_data = (const __le32 *) (adev->gfx.mec_fw->data +
1084                          le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes));
1085                 fw_size = le32_to_cpu(mec_hdr->header.ucode_size_bytes);
1086
1087                 r = amdgpu_bo_create_reserved(adev, mec_hdr->header.ucode_size_bytes,
1088                                               PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,
1089                                               &adev->gfx.mec.mec_fw_obj,
1090                                               &adev->gfx.mec.mec_fw_gpu_addr,
1091                                               (void **)&fw);
1092                 if (r) {
1093                         dev_err(adev->dev, "(%d) failed to create mec fw bo\n", r);
1094                         gfx_v10_0_mec_fini(adev);
1095                         return r;
1096                 }
1097
1098                 memcpy(fw, fw_data, fw_size);
1099
1100                 amdgpu_bo_kunmap(adev->gfx.mec.mec_fw_obj);
1101                 amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_obj);
1102         }
1103
1104         return 0;
1105 }
1106
1107 static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t wave, uint32_t address)
1108 {
1109         WREG32_SOC15(GC, 0, mmSQ_IND_INDEX,
1110                 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) |
1111                 (address << SQ_IND_INDEX__INDEX__SHIFT));
1112         return RREG32_SOC15(GC, 0, mmSQ_IND_DATA);
1113 }
1114
1115 static void wave_read_regs(struct amdgpu_device *adev, uint32_t wave,
1116                            uint32_t thread, uint32_t regno,
1117                            uint32_t num, uint32_t *out)
1118 {
1119         WREG32_SOC15(GC, 0, mmSQ_IND_INDEX,
1120                 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) |
1121                 (regno << SQ_IND_INDEX__INDEX__SHIFT) |
1122                 (thread << SQ_IND_INDEX__WORKITEM_ID__SHIFT) |
1123                 (SQ_IND_INDEX__AUTO_INCR_MASK));
1124         while (num--)
1125                 *(out++) = RREG32_SOC15(GC, 0, mmSQ_IND_DATA);
1126 }
1127
1128 static void gfx_v10_0_read_wave_data(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t *dst, int *no_fields)
1129 {
1130         /* in gfx10 the SIMD_ID is specified as part of the INSTANCE
1131          * field when performing a select_se_sh so it should be
1132          * zero here */
1133         WARN_ON(simd != 0);
1134
1135         /* type 2 wave data */
1136         dst[(*no_fields)++] = 2;
1137         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_STATUS);
1138         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_PC_LO);
1139         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_PC_HI);
1140         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXEC_LO);
1141         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXEC_HI);
1142         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_HW_ID1);
1143         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_HW_ID2);
1144         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_INST_DW0);
1145         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_GPR_ALLOC);
1146         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_LDS_ALLOC);
1147         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_TRAPSTS);
1148         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_STS);
1149         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_STS2);
1150         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_DBG1);
1151         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_M0);
1152 }
1153
1154 static void gfx_v10_0_read_wave_sgprs(struct amdgpu_device *adev, uint32_t simd,
1155                                      uint32_t wave, uint32_t start,
1156                                      uint32_t size, uint32_t *dst)
1157 {
1158         WARN_ON(simd != 0);
1159
1160         wave_read_regs(
1161                 adev, wave, 0, start + SQIND_WAVE_SGPRS_OFFSET, size,
1162                 dst);
1163 }
1164
1165 static void gfx_v10_0_read_wave_vgprs(struct amdgpu_device *adev, uint32_t simd,
1166                                       uint32_t wave, uint32_t thread,
1167                                       uint32_t start, uint32_t size,
1168                                       uint32_t *dst)
1169 {
1170         wave_read_regs(
1171                 adev, wave, thread,
1172                 start + SQIND_WAVE_VGPRS_OFFSET, size, dst);
1173 }
1174
1175 static void gfx_v10_0_select_me_pipe_q(struct amdgpu_device *adev,
1176                                                                           u32 me, u32 pipe, u32 q, u32 vm)
1177  {
1178        nv_grbm_select(adev, me, pipe, q, vm);
1179  }
1180
1181
1182 static const struct amdgpu_gfx_funcs gfx_v10_0_gfx_funcs = {
1183         .get_gpu_clock_counter = &gfx_v10_0_get_gpu_clock_counter,
1184         .select_se_sh = &gfx_v10_0_select_se_sh,
1185         .read_wave_data = &gfx_v10_0_read_wave_data,
1186         .read_wave_sgprs = &gfx_v10_0_read_wave_sgprs,
1187         .read_wave_vgprs = &gfx_v10_0_read_wave_vgprs,
1188         .select_me_pipe_q = &gfx_v10_0_select_me_pipe_q,
1189 };
1190
1191 static void gfx_v10_0_gpu_early_init(struct amdgpu_device *adev)
1192 {
1193         u32 gb_addr_config;
1194
1195         adev->gfx.funcs = &gfx_v10_0_gfx_funcs;
1196
1197         switch (adev->asic_type) {
1198         case CHIP_NAVI10:
1199         case CHIP_NAVI14:
1200         case CHIP_NAVI12:
1201                 adev->gfx.config.max_hw_contexts = 8;
1202                 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
1203                 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
1204                 adev->gfx.config.sc_hiz_tile_fifo_size = 0;
1205                 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0;
1206                 gb_addr_config = RREG32_SOC15(GC, 0, mmGB_ADDR_CONFIG);
1207                 break;
1208         default:
1209                 BUG();
1210                 break;
1211         }
1212
1213         adev->gfx.config.gb_addr_config = gb_addr_config;
1214
1215         adev->gfx.config.gb_addr_config_fields.num_pipes = 1 <<
1216                         REG_GET_FIELD(adev->gfx.config.gb_addr_config,
1217                                       GB_ADDR_CONFIG, NUM_PIPES);
1218
1219         adev->gfx.config.max_tile_pipes =
1220                 adev->gfx.config.gb_addr_config_fields.num_pipes;
1221
1222         adev->gfx.config.gb_addr_config_fields.max_compress_frags = 1 <<
1223                         REG_GET_FIELD(adev->gfx.config.gb_addr_config,
1224                                       GB_ADDR_CONFIG, MAX_COMPRESSED_FRAGS);
1225         adev->gfx.config.gb_addr_config_fields.num_rb_per_se = 1 <<
1226                         REG_GET_FIELD(adev->gfx.config.gb_addr_config,
1227                                       GB_ADDR_CONFIG, NUM_RB_PER_SE);
1228         adev->gfx.config.gb_addr_config_fields.num_se = 1 <<
1229                         REG_GET_FIELD(adev->gfx.config.gb_addr_config,
1230                                       GB_ADDR_CONFIG, NUM_SHADER_ENGINES);
1231         adev->gfx.config.gb_addr_config_fields.pipe_interleave_size = 1 << (8 +
1232                         REG_GET_FIELD(adev->gfx.config.gb_addr_config,
1233                                       GB_ADDR_CONFIG, PIPE_INTERLEAVE_SIZE));
1234 }
1235
1236 static int gfx_v10_0_gfx_ring_init(struct amdgpu_device *adev, int ring_id,
1237                                    int me, int pipe, int queue)
1238 {
1239         int r;
1240         struct amdgpu_ring *ring;
1241         unsigned int irq_type;
1242
1243         ring = &adev->gfx.gfx_ring[ring_id];
1244
1245         ring->me = me;
1246         ring->pipe = pipe;
1247         ring->queue = queue;
1248
1249         ring->ring_obj = NULL;
1250         ring->use_doorbell = true;
1251
1252         if (!ring_id)
1253                 ring->doorbell_index = adev->doorbell_index.gfx_ring0 << 1;
1254         else
1255                 ring->doorbell_index = adev->doorbell_index.gfx_ring1 << 1;
1256         sprintf(ring->name, "gfx_%d.%d.%d", ring->me, ring->pipe, ring->queue);
1257
1258         irq_type = AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP + ring->pipe;
1259         r = amdgpu_ring_init(adev, ring, 1024,
1260                              &adev->gfx.eop_irq, irq_type);
1261         if (r)
1262                 return r;
1263         return 0;
1264 }
1265
1266 static int gfx_v10_0_compute_ring_init(struct amdgpu_device *adev, int ring_id,
1267                                        int mec, int pipe, int queue)
1268 {
1269         int r;
1270         unsigned irq_type;
1271         struct amdgpu_ring *ring = &adev->gfx.compute_ring[ring_id];
1272
1273         ring = &adev->gfx.compute_ring[ring_id];
1274
1275         /* mec0 is me1 */
1276         ring->me = mec + 1;
1277         ring->pipe = pipe;
1278         ring->queue = queue;
1279
1280         ring->ring_obj = NULL;
1281         ring->use_doorbell = true;
1282         ring->doorbell_index = (adev->doorbell_index.mec_ring0 + ring_id) << 1;
1283         ring->eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr
1284                                 + (ring_id * GFX10_MEC_HPD_SIZE);
1285         sprintf(ring->name, "comp_%d.%d.%d", ring->me, ring->pipe, ring->queue);
1286
1287         irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP
1288                 + ((ring->me - 1) * adev->gfx.mec.num_pipe_per_mec)
1289                 + ring->pipe;
1290
1291         /* type-2 packets are deprecated on MEC, use type-3 instead */
1292         r = amdgpu_ring_init(adev, ring, 1024,
1293                              &adev->gfx.eop_irq, irq_type);
1294         if (r)
1295                 return r;
1296
1297         return 0;
1298 }
1299
1300 static int gfx_v10_0_sw_init(void *handle)
1301 {
1302         int i, j, k, r, ring_id = 0;
1303         struct amdgpu_kiq *kiq;
1304         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1305
1306         switch (adev->asic_type) {
1307         case CHIP_NAVI10:
1308         case CHIP_NAVI14:
1309         case CHIP_NAVI12:
1310                 adev->gfx.me.num_me = 1;
1311                 adev->gfx.me.num_pipe_per_me = 2;
1312                 adev->gfx.me.num_queue_per_pipe = 1;
1313                 adev->gfx.mec.num_mec = 2;
1314                 adev->gfx.mec.num_pipe_per_mec = 4;
1315                 adev->gfx.mec.num_queue_per_pipe = 8;
1316                 break;
1317         default:
1318                 adev->gfx.me.num_me = 1;
1319                 adev->gfx.me.num_pipe_per_me = 1;
1320                 adev->gfx.me.num_queue_per_pipe = 1;
1321                 adev->gfx.mec.num_mec = 1;
1322                 adev->gfx.mec.num_pipe_per_mec = 4;
1323                 adev->gfx.mec.num_queue_per_pipe = 8;
1324                 break;
1325         }
1326
1327         /* KIQ event */
1328         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP,
1329                               GFX_10_1__SRCID__CP_IB2_INTERRUPT_PKT,
1330                               &adev->gfx.kiq.irq);
1331         if (r)
1332                 return r;
1333
1334         /* EOP Event */
1335         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP,
1336                               GFX_10_1__SRCID__CP_EOP_INTERRUPT,
1337                               &adev->gfx.eop_irq);
1338         if (r)
1339                 return r;
1340
1341         /* Privileged reg */
1342         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_10_1__SRCID__CP_PRIV_REG_FAULT,
1343                               &adev->gfx.priv_reg_irq);
1344         if (r)
1345                 return r;
1346
1347         /* Privileged inst */
1348         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_10_1__SRCID__CP_PRIV_INSTR_FAULT,
1349                               &adev->gfx.priv_inst_irq);
1350         if (r)
1351                 return r;
1352
1353         adev->gfx.gfx_current_status = AMDGPU_GFX_NORMAL_MODE;
1354
1355         gfx_v10_0_scratch_init(adev);
1356
1357         r = gfx_v10_0_me_init(adev);
1358         if (r)
1359                 return r;
1360
1361         r = gfx_v10_0_rlc_init(adev);
1362         if (r) {
1363                 DRM_ERROR("Failed to init rlc BOs!\n");
1364                 return r;
1365         }
1366
1367         r = gfx_v10_0_mec_init(adev);
1368         if (r) {
1369                 DRM_ERROR("Failed to init MEC BOs!\n");
1370                 return r;
1371         }
1372
1373         /* set up the gfx ring */
1374         for (i = 0; i < adev->gfx.me.num_me; i++) {
1375                 for (j = 0; j < adev->gfx.me.num_queue_per_pipe; j++) {
1376                         for (k = 0; k < adev->gfx.me.num_pipe_per_me; k++) {
1377                                 if (!amdgpu_gfx_is_me_queue_enabled(adev, i, k, j))
1378                                         continue;
1379
1380                                 r = gfx_v10_0_gfx_ring_init(adev, ring_id,
1381                                                             i, k, j);
1382                                 if (r)
1383                                         return r;
1384                                 ring_id++;
1385                         }
1386                 }
1387         }
1388
1389         ring_id = 0;
1390         /* set up the compute queues - allocate horizontally across pipes */
1391         for (i = 0; i < adev->gfx.mec.num_mec; ++i) {
1392                 for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) {
1393                         for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) {
1394                                 if (!amdgpu_gfx_is_mec_queue_enabled(adev, i, k,
1395                                                                      j))
1396                                         continue;
1397
1398                                 r = gfx_v10_0_compute_ring_init(adev, ring_id,
1399                                                                 i, k, j);
1400                                 if (r)
1401                                         return r;
1402
1403                                 ring_id++;
1404                         }
1405                 }
1406         }
1407
1408         r = amdgpu_gfx_kiq_init(adev, GFX10_MEC_HPD_SIZE);
1409         if (r) {
1410                 DRM_ERROR("Failed to init KIQ BOs!\n");
1411                 return r;
1412         }
1413
1414         kiq = &adev->gfx.kiq;
1415         r = amdgpu_gfx_kiq_init_ring(adev, &kiq->ring, &kiq->irq);
1416         if (r)
1417                 return r;
1418
1419         r = amdgpu_gfx_mqd_sw_init(adev, sizeof(struct v10_compute_mqd));
1420         if (r)
1421                 return r;
1422
1423         /* allocate visible FB for rlc auto-loading fw */
1424         if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) {
1425                 r = gfx_v10_0_rlc_backdoor_autoload_buffer_init(adev);
1426                 if (r)
1427                         return r;
1428         }
1429
1430         adev->gfx.ce_ram_size = F32_CE_PROGRAM_RAM_SIZE;
1431
1432         gfx_v10_0_gpu_early_init(adev);
1433
1434         return 0;
1435 }
1436
1437 static void gfx_v10_0_pfp_fini(struct amdgpu_device *adev)
1438 {
1439         amdgpu_bo_free_kernel(&adev->gfx.pfp.pfp_fw_obj,
1440                               &adev->gfx.pfp.pfp_fw_gpu_addr,
1441                               (void **)&adev->gfx.pfp.pfp_fw_ptr);
1442 }
1443
1444 static void gfx_v10_0_ce_fini(struct amdgpu_device *adev)
1445 {
1446         amdgpu_bo_free_kernel(&adev->gfx.ce.ce_fw_obj,
1447                               &adev->gfx.ce.ce_fw_gpu_addr,
1448                               (void **)&adev->gfx.ce.ce_fw_ptr);
1449 }
1450
1451 static void gfx_v10_0_me_fini(struct amdgpu_device *adev)
1452 {
1453         amdgpu_bo_free_kernel(&adev->gfx.me.me_fw_obj,
1454                               &adev->gfx.me.me_fw_gpu_addr,
1455                               (void **)&adev->gfx.me.me_fw_ptr);
1456 }
1457
1458 static int gfx_v10_0_sw_fini(void *handle)
1459 {
1460         int i;
1461         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1462
1463         for (i = 0; i < adev->gfx.num_gfx_rings; i++)
1464                 amdgpu_ring_fini(&adev->gfx.gfx_ring[i]);
1465         for (i = 0; i < adev->gfx.num_compute_rings; i++)
1466                 amdgpu_ring_fini(&adev->gfx.compute_ring[i]);
1467
1468         amdgpu_gfx_mqd_sw_fini(adev);
1469         amdgpu_gfx_kiq_free_ring(&adev->gfx.kiq.ring);
1470         amdgpu_gfx_kiq_fini(adev);
1471
1472         gfx_v10_0_pfp_fini(adev);
1473         gfx_v10_0_ce_fini(adev);
1474         gfx_v10_0_me_fini(adev);
1475         gfx_v10_0_rlc_fini(adev);
1476         gfx_v10_0_mec_fini(adev);
1477
1478         if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO)
1479                 gfx_v10_0_rlc_backdoor_autoload_buffer_fini(adev);
1480
1481         gfx_v10_0_free_microcode(adev);
1482
1483         return 0;
1484 }
1485
1486
1487 static void gfx_v10_0_tiling_mode_table_init(struct amdgpu_device *adev)
1488 {
1489         /* TODO */
1490 }
1491
1492 static void gfx_v10_0_select_se_sh(struct amdgpu_device *adev, u32 se_num,
1493                                    u32 sh_num, u32 instance)
1494 {
1495         u32 data;
1496
1497         if (instance == 0xffffffff)
1498                 data = REG_SET_FIELD(0, GRBM_GFX_INDEX,
1499                                      INSTANCE_BROADCAST_WRITES, 1);
1500         else
1501                 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_INDEX,
1502                                      instance);
1503
1504         if (se_num == 0xffffffff)
1505                 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_BROADCAST_WRITES,
1506                                      1);
1507         else
1508                 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num);
1509
1510         if (sh_num == 0xffffffff)
1511                 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SA_BROADCAST_WRITES,
1512                                      1);
1513         else
1514                 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SA_INDEX, sh_num);
1515
1516         WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, data);
1517 }
1518
1519 static u32 gfx_v10_0_get_rb_active_bitmap(struct amdgpu_device *adev)
1520 {
1521         u32 data, mask;
1522
1523         data = RREG32_SOC15(GC, 0, mmCC_RB_BACKEND_DISABLE);
1524         data |= RREG32_SOC15(GC, 0, mmGC_USER_RB_BACKEND_DISABLE);
1525
1526         data &= CC_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK;
1527         data >>= GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT;
1528
1529         mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_backends_per_se /
1530                                          adev->gfx.config.max_sh_per_se);
1531
1532         return (~data) & mask;
1533 }
1534
1535 static void gfx_v10_0_setup_rb(struct amdgpu_device *adev)
1536 {
1537         int i, j;
1538         u32 data;
1539         u32 active_rbs = 0;
1540         u32 rb_bitmap_width_per_sh = adev->gfx.config.max_backends_per_se /
1541                                         adev->gfx.config.max_sh_per_se;
1542
1543         mutex_lock(&adev->grbm_idx_mutex);
1544         for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
1545                 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
1546                         gfx_v10_0_select_se_sh(adev, i, j, 0xffffffff);
1547                         data = gfx_v10_0_get_rb_active_bitmap(adev);
1548                         active_rbs |= data << ((i * adev->gfx.config.max_sh_per_se + j) *
1549                                                rb_bitmap_width_per_sh);
1550                 }
1551         }
1552         gfx_v10_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
1553         mutex_unlock(&adev->grbm_idx_mutex);
1554
1555         adev->gfx.config.backend_enable_mask = active_rbs;
1556         adev->gfx.config.num_rbs = hweight32(active_rbs);
1557 }
1558
1559 static u32 gfx_v10_0_init_pa_sc_tile_steering_override(struct amdgpu_device *adev)
1560 {
1561         uint32_t num_sc;
1562         uint32_t enabled_rb_per_sh;
1563         uint32_t active_rb_bitmap;
1564         uint32_t num_rb_per_sc;
1565         uint32_t num_packer_per_sc;
1566         uint32_t pa_sc_tile_steering_override;
1567
1568         /* init num_sc */
1569         num_sc = adev->gfx.config.max_shader_engines * adev->gfx.config.max_sh_per_se *
1570                         adev->gfx.config.num_sc_per_sh;
1571         /* init num_rb_per_sc */
1572         active_rb_bitmap = gfx_v10_0_get_rb_active_bitmap(adev);
1573         enabled_rb_per_sh = hweight32(active_rb_bitmap);
1574         num_rb_per_sc = enabled_rb_per_sh / adev->gfx.config.num_sc_per_sh;
1575         /* init num_packer_per_sc */
1576         num_packer_per_sc = adev->gfx.config.num_packer_per_sc;
1577
1578         pa_sc_tile_steering_override = 0;
1579         pa_sc_tile_steering_override |=
1580                 (order_base_2(num_sc) << PA_SC_TILE_STEERING_OVERRIDE__NUM_SC__SHIFT) &
1581                 PA_SC_TILE_STEERING_OVERRIDE__NUM_SC_MASK;
1582         pa_sc_tile_steering_override |=
1583                 (order_base_2(num_rb_per_sc) << PA_SC_TILE_STEERING_OVERRIDE__NUM_RB_PER_SC__SHIFT) &
1584                 PA_SC_TILE_STEERING_OVERRIDE__NUM_RB_PER_SC_MASK;
1585         pa_sc_tile_steering_override |=
1586                 (order_base_2(num_packer_per_sc) << PA_SC_TILE_STEERING_OVERRIDE__NUM_PACKER_PER_SC__SHIFT) &
1587                 PA_SC_TILE_STEERING_OVERRIDE__NUM_PACKER_PER_SC_MASK;
1588
1589         return pa_sc_tile_steering_override;
1590 }
1591
1592 #define DEFAULT_SH_MEM_BASES    (0x6000)
1593 #define FIRST_COMPUTE_VMID      (8)
1594 #define LAST_COMPUTE_VMID       (16)
1595
1596 static void gfx_v10_0_init_compute_vmid(struct amdgpu_device *adev)
1597 {
1598         int i;
1599         uint32_t sh_mem_bases;
1600
1601         /*
1602          * Configure apertures:
1603          * LDS:         0x60000000'00000000 - 0x60000001'00000000 (4GB)
1604          * Scratch:     0x60000001'00000000 - 0x60000002'00000000 (4GB)
1605          * GPUVM:       0x60010000'00000000 - 0x60020000'00000000 (1TB)
1606          */
1607         sh_mem_bases = DEFAULT_SH_MEM_BASES | (DEFAULT_SH_MEM_BASES << 16);
1608
1609         mutex_lock(&adev->srbm_mutex);
1610         for (i = FIRST_COMPUTE_VMID; i < LAST_COMPUTE_VMID; i++) {
1611                 nv_grbm_select(adev, 0, 0, 0, i);
1612                 /* CP and shaders */
1613                 WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, DEFAULT_SH_MEM_CONFIG);
1614                 WREG32_SOC15(GC, 0, mmSH_MEM_BASES, sh_mem_bases);
1615         }
1616         nv_grbm_select(adev, 0, 0, 0, 0);
1617         mutex_unlock(&adev->srbm_mutex);
1618
1619         /* Initialize all compute VMIDs to have no GDS, GWS, or OA
1620            acccess. These should be enabled by FW for target VMIDs. */
1621         for (i = FIRST_COMPUTE_VMID; i < LAST_COMPUTE_VMID; i++) {
1622                 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_BASE, 2 * i, 0);
1623                 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_SIZE, 2 * i, 0);
1624                 WREG32_SOC15_OFFSET(GC, 0, mmGDS_GWS_VMID0, i, 0);
1625                 WREG32_SOC15_OFFSET(GC, 0, mmGDS_OA_VMID0, i, 0);
1626         }
1627 }
1628
1629 static void gfx_v10_0_init_gds_vmid(struct amdgpu_device *adev)
1630 {
1631         int vmid;
1632
1633         /*
1634          * Initialize all compute and user-gfx VMIDs to have no GDS, GWS, or OA
1635          * access. Compute VMIDs should be enabled by FW for target VMIDs,
1636          * the driver can enable them for graphics. VMID0 should maintain
1637          * access so that HWS firmware can save/restore entries.
1638          */
1639         for (vmid = 1; vmid < 16; vmid++) {
1640                 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_BASE, 2 * vmid, 0);
1641                 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_SIZE, 2 * vmid, 0);
1642                 WREG32_SOC15_OFFSET(GC, 0, mmGDS_GWS_VMID0, vmid, 0);
1643                 WREG32_SOC15_OFFSET(GC, 0, mmGDS_OA_VMID0, vmid, 0);
1644         }
1645 }
1646
1647
1648 static void gfx_v10_0_tcp_harvest(struct amdgpu_device *adev)
1649 {
1650         int i, j, k;
1651         int max_wgp_per_sh = adev->gfx.config.max_cu_per_sh >> 1;
1652         u32 tmp, wgp_active_bitmap = 0;
1653         u32 gcrd_targets_disable_tcp = 0;
1654         u32 utcl_invreq_disable = 0;
1655         /*
1656          * GCRD_TARGETS_DISABLE field contains
1657          * for Navi10/Navi12: GL1C=[18:15], SQC=[14:10], TCP=[9:0]
1658          * for Navi14: GL1C=[21:18], SQC=[17:12], TCP=[11:0]
1659          */
1660         u32 gcrd_targets_disable_mask = amdgpu_gfx_create_bitmask(
1661                 2 * max_wgp_per_sh + /* TCP */
1662                 max_wgp_per_sh + /* SQC */
1663                 4); /* GL1C */
1664         /*
1665          * UTCL1_UTCL0_INVREQ_DISABLE field contains
1666          * for Navi10Navi12: SQG=[24], RMI=[23:20], SQC=[19:10], TCP=[9:0]
1667          * for Navi14: SQG=[28], RMI=[27:24], SQC=[23:12], TCP=[11:0]
1668          */
1669         u32 utcl_invreq_disable_mask = amdgpu_gfx_create_bitmask(
1670                 2 * max_wgp_per_sh + /* TCP */
1671                 2 * max_wgp_per_sh + /* SQC */
1672                 4 + /* RMI */
1673                 1); /* SQG */
1674
1675         if (adev->asic_type == CHIP_NAVI10 ||
1676             adev->asic_type == CHIP_NAVI14 ||
1677             adev->asic_type == CHIP_NAVI12) {
1678                 mutex_lock(&adev->grbm_idx_mutex);
1679                 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
1680                         for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
1681                                 gfx_v10_0_select_se_sh(adev, i, j, 0xffffffff);
1682                                 wgp_active_bitmap = gfx_v10_0_get_wgp_active_bitmap_per_sh(adev);
1683                                 /*
1684                                  * Set corresponding TCP bits for the inactive WGPs in
1685                                  * GCRD_SA_TARGETS_DISABLE
1686                                  */
1687                                 gcrd_targets_disable_tcp = 0;
1688                                 /* Set TCP & SQC bits in UTCL1_UTCL0_INVREQ_DISABLE */
1689                                 utcl_invreq_disable = 0;
1690
1691                                 for (k = 0; k < max_wgp_per_sh; k++) {
1692                                         if (!(wgp_active_bitmap & (1 << k))) {
1693                                                 gcrd_targets_disable_tcp |= 3 << (2 * k);
1694                                                 utcl_invreq_disable |= (3 << (2 * k)) |
1695                                                         (3 << (2 * (max_wgp_per_sh + k)));
1696                                         }
1697                                 }
1698
1699                                 tmp = RREG32_SOC15(GC, 0, mmUTCL1_UTCL0_INVREQ_DISABLE);
1700                                 /* only override TCP & SQC bits */
1701                                 tmp &= 0xffffffff << (4 * max_wgp_per_sh);
1702                                 tmp |= (utcl_invreq_disable & utcl_invreq_disable_mask);
1703                                 WREG32_SOC15(GC, 0, mmUTCL1_UTCL0_INVREQ_DISABLE, tmp);
1704
1705                                 tmp = RREG32_SOC15(GC, 0, mmGCRD_SA_TARGETS_DISABLE);
1706                                 /* only override TCP bits */
1707                                 tmp &= 0xffffffff << (2 * max_wgp_per_sh);
1708                                 tmp |= (gcrd_targets_disable_tcp & gcrd_targets_disable_mask);
1709                                 WREG32_SOC15(GC, 0, mmGCRD_SA_TARGETS_DISABLE, tmp);
1710                         }
1711                 }
1712
1713                 gfx_v10_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
1714                 mutex_unlock(&adev->grbm_idx_mutex);
1715         }
1716 }
1717
1718 static void gfx_v10_0_get_tcc_info(struct amdgpu_device *adev)
1719 {
1720         /* TCCs are global (not instanced). */
1721         uint32_t tcc_disable = RREG32_SOC15(GC, 0, mmCGTS_TCC_DISABLE) |
1722                                RREG32_SOC15(GC, 0, mmCGTS_USER_TCC_DISABLE);
1723
1724         adev->gfx.config.tcc_disabled_mask =
1725                 REG_GET_FIELD(tcc_disable, CGTS_TCC_DISABLE, TCC_DISABLE) |
1726                 (REG_GET_FIELD(tcc_disable, CGTS_TCC_DISABLE, HI_TCC_DISABLE) << 16);
1727 }
1728
1729 static void gfx_v10_0_constants_init(struct amdgpu_device *adev)
1730 {
1731         u32 tmp;
1732         int i;
1733
1734         WREG32_FIELD15(GC, 0, GRBM_CNTL, READ_TIMEOUT, 0xff);
1735
1736         gfx_v10_0_tiling_mode_table_init(adev);
1737
1738         gfx_v10_0_setup_rb(adev);
1739         gfx_v10_0_get_cu_info(adev, &adev->gfx.cu_info);
1740         gfx_v10_0_get_tcc_info(adev);
1741         adev->gfx.config.pa_sc_tile_steering_override =
1742                 gfx_v10_0_init_pa_sc_tile_steering_override(adev);
1743
1744         /* XXX SH_MEM regs */
1745         /* where to put LDS, scratch, GPUVM in FSA64 space */
1746         mutex_lock(&adev->srbm_mutex);
1747         for (i = 0; i < adev->vm_manager.id_mgr[AMDGPU_GFXHUB_0].num_ids; i++) {
1748                 nv_grbm_select(adev, 0, 0, 0, i);
1749                 /* CP and shaders */
1750                 WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, DEFAULT_SH_MEM_CONFIG);
1751                 if (i != 0) {
1752                         tmp = REG_SET_FIELD(0, SH_MEM_BASES, PRIVATE_BASE,
1753                                 (adev->gmc.private_aperture_start >> 48));
1754                         tmp = REG_SET_FIELD(tmp, SH_MEM_BASES, SHARED_BASE,
1755                                 (adev->gmc.shared_aperture_start >> 48));
1756                         WREG32_SOC15(GC, 0, mmSH_MEM_BASES, tmp);
1757                 }
1758         }
1759         nv_grbm_select(adev, 0, 0, 0, 0);
1760
1761         mutex_unlock(&adev->srbm_mutex);
1762
1763         gfx_v10_0_init_compute_vmid(adev);
1764         gfx_v10_0_init_gds_vmid(adev);
1765
1766 }
1767
1768 static void gfx_v10_0_enable_gui_idle_interrupt(struct amdgpu_device *adev,
1769                                                bool enable)
1770 {
1771         u32 tmp = RREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0);
1772
1773         tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE,
1774                             enable ? 1 : 0);
1775         tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE,
1776                             enable ? 1 : 0);
1777         tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE,
1778                             enable ? 1 : 0);
1779         tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, GFX_IDLE_INT_ENABLE,
1780                             enable ? 1 : 0);
1781
1782         WREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0, tmp);
1783 }
1784
1785 static int gfx_v10_0_init_csb(struct amdgpu_device *adev)
1786 {
1787         adev->gfx.rlc.funcs->get_csb_buffer(adev, adev->gfx.rlc.cs_ptr);
1788
1789         /* csib */
1790         WREG32_SOC15(GC, 0, mmRLC_CSIB_ADDR_HI,
1791                      adev->gfx.rlc.clear_state_gpu_addr >> 32);
1792         WREG32_SOC15(GC, 0, mmRLC_CSIB_ADDR_LO,
1793                      adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc);
1794         WREG32_SOC15(GC, 0, mmRLC_CSIB_LENGTH, adev->gfx.rlc.clear_state_size);
1795
1796         return 0;
1797 }
1798
1799 void gfx_v10_0_rlc_stop(struct amdgpu_device *adev)
1800 {
1801         u32 tmp = RREG32_SOC15(GC, 0, mmRLC_CNTL);
1802
1803         tmp = REG_SET_FIELD(tmp, RLC_CNTL, RLC_ENABLE_F32, 0);
1804         WREG32_SOC15(GC, 0, mmRLC_CNTL, tmp);
1805 }
1806
1807 static void gfx_v10_0_rlc_reset(struct amdgpu_device *adev)
1808 {
1809         WREG32_FIELD15(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 1);
1810         udelay(50);
1811         WREG32_FIELD15(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 0);
1812         udelay(50);
1813 }
1814
1815 static void gfx_v10_0_rlc_smu_handshake_cntl(struct amdgpu_device *adev,
1816                                              bool enable)
1817 {
1818         uint32_t rlc_pg_cntl;
1819
1820         rlc_pg_cntl = RREG32_SOC15(GC, 0, mmRLC_PG_CNTL);
1821
1822         if (!enable) {
1823                 /* RLC_PG_CNTL[23] = 0 (default)
1824                  * RLC will wait for handshake acks with SMU
1825                  * GFXOFF will be enabled
1826                  * RLC_PG_CNTL[23] = 1
1827                  * RLC will not issue any message to SMU
1828                  * hence no handshake between SMU & RLC
1829                  * GFXOFF will be disabled
1830                  */
1831                 rlc_pg_cntl |= 0x800000;
1832         } else
1833                 rlc_pg_cntl &= ~0x800000;
1834         WREG32_SOC15(GC, 0, mmRLC_PG_CNTL, rlc_pg_cntl);
1835 }
1836
1837 static void gfx_v10_0_rlc_start(struct amdgpu_device *adev)
1838 {
1839         /* TODO: enable rlc & smu handshake until smu
1840          * and gfxoff feature works as expected */
1841         if (!(amdgpu_pp_feature_mask & PP_GFXOFF_MASK))
1842                 gfx_v10_0_rlc_smu_handshake_cntl(adev, false);
1843
1844         WREG32_FIELD15(GC, 0, RLC_CNTL, RLC_ENABLE_F32, 1);
1845         udelay(50);
1846 }
1847
1848 static void gfx_v10_0_rlc_enable_srm(struct amdgpu_device *adev)
1849 {
1850         uint32_t tmp;
1851
1852         /* enable Save Restore Machine */
1853         tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_CNTL));
1854         tmp |= RLC_SRM_CNTL__AUTO_INCR_ADDR_MASK;
1855         tmp |= RLC_SRM_CNTL__SRM_ENABLE_MASK;
1856         WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_CNTL), tmp);
1857 }
1858
1859 static int gfx_v10_0_rlc_load_microcode(struct amdgpu_device *adev)
1860 {
1861         const struct rlc_firmware_header_v2_0 *hdr;
1862         const __le32 *fw_data;
1863         unsigned i, fw_size;
1864
1865         if (!adev->gfx.rlc_fw)
1866                 return -EINVAL;
1867
1868         hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data;
1869         amdgpu_ucode_print_rlc_hdr(&hdr->header);
1870
1871         fw_data = (const __le32 *)(adev->gfx.rlc_fw->data +
1872                            le32_to_cpu(hdr->header.ucode_array_offset_bytes));
1873         fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
1874
1875         WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_ADDR,
1876                      RLCG_UCODE_LOADING_START_ADDRESS);
1877
1878         for (i = 0; i < fw_size; i++)
1879                 WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_DATA,
1880                              le32_to_cpup(fw_data++));
1881
1882         WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_ADDR, adev->gfx.rlc_fw_version);
1883
1884         return 0;
1885 }
1886
1887 static int gfx_v10_0_rlc_resume(struct amdgpu_device *adev)
1888 {
1889         int r;
1890
1891         if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
1892
1893                 r = gfx_v10_0_wait_for_rlc_autoload_complete(adev);
1894                 if (r)
1895                         return r;
1896
1897                 gfx_v10_0_init_csb(adev);
1898
1899                 if (!amdgpu_sriov_vf(adev)) /* enable RLC SRM */
1900                         gfx_v10_0_rlc_enable_srm(adev);
1901         } else {
1902                 adev->gfx.rlc.funcs->stop(adev);
1903
1904                 /* disable CG */
1905                 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, 0);
1906
1907                 /* disable PG */
1908                 WREG32_SOC15(GC, 0, mmRLC_PG_CNTL, 0);
1909
1910                 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
1911                         /* legacy rlc firmware loading */
1912                         r = gfx_v10_0_rlc_load_microcode(adev);
1913                         if (r)
1914                                 return r;
1915                 } else if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) {
1916                         /* rlc backdoor autoload firmware */
1917                         r = gfx_v10_0_rlc_backdoor_autoload_enable(adev);
1918                         if (r)
1919                                 return r;
1920                 }
1921
1922                 gfx_v10_0_init_csb(adev);
1923
1924                 adev->gfx.rlc.funcs->start(adev);
1925
1926                 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) {
1927                         r = gfx_v10_0_wait_for_rlc_autoload_complete(adev);
1928                         if (r)
1929                                 return r;
1930                 }
1931         }
1932         return 0;
1933 }
1934
1935 static struct {
1936         FIRMWARE_ID     id;
1937         unsigned int    offset;
1938         unsigned int    size;
1939 } rlc_autoload_info[FIRMWARE_ID_MAX];
1940
1941 static int gfx_v10_0_parse_rlc_toc(struct amdgpu_device *adev)
1942 {
1943         int ret;
1944         RLC_TABLE_OF_CONTENT *rlc_toc;
1945
1946         ret = amdgpu_bo_create_reserved(adev, adev->psp.toc_bin_size, PAGE_SIZE,
1947                                         AMDGPU_GEM_DOMAIN_GTT,
1948                                         &adev->gfx.rlc.rlc_toc_bo,
1949                                         &adev->gfx.rlc.rlc_toc_gpu_addr,
1950                                         (void **)&adev->gfx.rlc.rlc_toc_buf);
1951         if (ret) {
1952                 dev_err(adev->dev, "(%d) failed to create rlc toc bo\n", ret);
1953                 return ret;
1954         }
1955
1956         /* Copy toc from psp sos fw to rlc toc buffer */
1957         memcpy(adev->gfx.rlc.rlc_toc_buf, adev->psp.toc_start_addr, adev->psp.toc_bin_size);
1958
1959         rlc_toc = (RLC_TABLE_OF_CONTENT *)adev->gfx.rlc.rlc_toc_buf;
1960         while (rlc_toc && (rlc_toc->id > FIRMWARE_ID_INVALID) &&
1961                 (rlc_toc->id < FIRMWARE_ID_MAX)) {
1962                 if ((rlc_toc->id >= FIRMWARE_ID_CP_CE) &&
1963                     (rlc_toc->id <= FIRMWARE_ID_CP_MES)) {
1964                         /* Offset needs 4KB alignment */
1965                         rlc_toc->offset = ALIGN(rlc_toc->offset * 4, PAGE_SIZE);
1966                 }
1967
1968                 rlc_autoload_info[rlc_toc->id].id = rlc_toc->id;
1969                 rlc_autoload_info[rlc_toc->id].offset = rlc_toc->offset * 4;
1970                 rlc_autoload_info[rlc_toc->id].size = rlc_toc->size * 4;
1971
1972                 rlc_toc++;
1973         }
1974
1975         return 0;
1976 }
1977
1978 static uint32_t gfx_v10_0_calc_toc_total_size(struct amdgpu_device *adev)
1979 {
1980         uint32_t total_size = 0;
1981         FIRMWARE_ID id;
1982         int ret;
1983
1984         ret = gfx_v10_0_parse_rlc_toc(adev);
1985         if (ret) {
1986                 dev_err(adev->dev, "failed to parse rlc toc\n");
1987                 return 0;
1988         }
1989
1990         for (id = FIRMWARE_ID_RLC_G_UCODE; id < FIRMWARE_ID_MAX; id++)
1991                 total_size += rlc_autoload_info[id].size;
1992
1993         /* In case the offset in rlc toc ucode is aligned */
1994         if (total_size < rlc_autoload_info[FIRMWARE_ID_MAX-1].offset)
1995                 total_size = rlc_autoload_info[FIRMWARE_ID_MAX-1].offset +
1996                                 rlc_autoload_info[FIRMWARE_ID_MAX-1].size;
1997
1998         return total_size;
1999 }
2000
2001 static int gfx_v10_0_rlc_backdoor_autoload_buffer_init(struct amdgpu_device *adev)
2002 {
2003         int r;
2004         uint32_t total_size;
2005
2006         total_size = gfx_v10_0_calc_toc_total_size(adev);
2007
2008         r = amdgpu_bo_create_reserved(adev, total_size, PAGE_SIZE,
2009                                       AMDGPU_GEM_DOMAIN_GTT,
2010                                       &adev->gfx.rlc.rlc_autoload_bo,
2011                                       &adev->gfx.rlc.rlc_autoload_gpu_addr,
2012                                       (void **)&adev->gfx.rlc.rlc_autoload_ptr);
2013         if (r) {
2014                 dev_err(adev->dev, "(%d) failed to create fw autoload bo\n", r);
2015                 return r;
2016         }
2017
2018         return 0;
2019 }
2020
2021 static void gfx_v10_0_rlc_backdoor_autoload_buffer_fini(struct amdgpu_device *adev)
2022 {
2023         amdgpu_bo_free_kernel(&adev->gfx.rlc.rlc_toc_bo,
2024                               &adev->gfx.rlc.rlc_toc_gpu_addr,
2025                               (void **)&adev->gfx.rlc.rlc_toc_buf);
2026         amdgpu_bo_free_kernel(&adev->gfx.rlc.rlc_autoload_bo,
2027                               &adev->gfx.rlc.rlc_autoload_gpu_addr,
2028                               (void **)&adev->gfx.rlc.rlc_autoload_ptr);
2029 }
2030
2031 static void gfx_v10_0_rlc_backdoor_autoload_copy_ucode(struct amdgpu_device *adev,
2032                                                        FIRMWARE_ID id,
2033                                                        const void *fw_data,
2034                                                        uint32_t fw_size)
2035 {
2036         uint32_t toc_offset;
2037         uint32_t toc_fw_size;
2038         char *ptr = adev->gfx.rlc.rlc_autoload_ptr;
2039
2040         if (id <= FIRMWARE_ID_INVALID || id >= FIRMWARE_ID_MAX)
2041                 return;
2042
2043         toc_offset = rlc_autoload_info[id].offset;
2044         toc_fw_size = rlc_autoload_info[id].size;
2045
2046         if (fw_size == 0)
2047                 fw_size = toc_fw_size;
2048
2049         if (fw_size > toc_fw_size)
2050                 fw_size = toc_fw_size;
2051
2052         memcpy(ptr + toc_offset, fw_data, fw_size);
2053
2054         if (fw_size < toc_fw_size)
2055                 memset(ptr + toc_offset + fw_size, 0, toc_fw_size - fw_size);
2056 }
2057
2058 static void gfx_v10_0_rlc_backdoor_autoload_copy_toc_ucode(struct amdgpu_device *adev)
2059 {
2060         void *data;
2061         uint32_t size;
2062
2063         data = adev->gfx.rlc.rlc_toc_buf;
2064         size = rlc_autoload_info[FIRMWARE_ID_RLC_TOC].size;
2065
2066         gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
2067                                                    FIRMWARE_ID_RLC_TOC,
2068                                                    data, size);
2069 }
2070
2071 static void gfx_v10_0_rlc_backdoor_autoload_copy_gfx_ucode(struct amdgpu_device *adev)
2072 {
2073         const __le32 *fw_data;
2074         uint32_t fw_size;
2075         const struct gfx_firmware_header_v1_0 *cp_hdr;
2076         const struct rlc_firmware_header_v2_0 *rlc_hdr;
2077
2078         /* pfp ucode */
2079         cp_hdr = (const struct gfx_firmware_header_v1_0 *)
2080                 adev->gfx.pfp_fw->data;
2081         fw_data = (const __le32 *)(adev->gfx.pfp_fw->data +
2082                 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes));
2083         fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes);
2084         gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
2085                                                    FIRMWARE_ID_CP_PFP,
2086                                                    fw_data, fw_size);
2087
2088         /* ce ucode */
2089         cp_hdr = (const struct gfx_firmware_header_v1_0 *)
2090                 adev->gfx.ce_fw->data;
2091         fw_data = (const __le32 *)(adev->gfx.ce_fw->data +
2092                 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes));
2093         fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes);
2094         gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
2095                                                    FIRMWARE_ID_CP_CE,
2096                                                    fw_data, fw_size);
2097
2098         /* me ucode */
2099         cp_hdr = (const struct gfx_firmware_header_v1_0 *)
2100                 adev->gfx.me_fw->data;
2101         fw_data = (const __le32 *)(adev->gfx.me_fw->data +
2102                 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes));
2103         fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes);
2104         gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
2105                                                    FIRMWARE_ID_CP_ME,
2106                                                    fw_data, fw_size);
2107
2108         /* rlc ucode */
2109         rlc_hdr = (const struct rlc_firmware_header_v2_0 *)
2110                 adev->gfx.rlc_fw->data;
2111         fw_data = (const __le32 *)(adev->gfx.rlc_fw->data +
2112                 le32_to_cpu(rlc_hdr->header.ucode_array_offset_bytes));
2113         fw_size = le32_to_cpu(rlc_hdr->header.ucode_size_bytes);
2114         gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
2115                                                    FIRMWARE_ID_RLC_G_UCODE,
2116                                                    fw_data, fw_size);
2117
2118         /* mec1 ucode */
2119         cp_hdr = (const struct gfx_firmware_header_v1_0 *)
2120                 adev->gfx.mec_fw->data;
2121         fw_data = (const __le32 *) (adev->gfx.mec_fw->data +
2122                 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes));
2123         fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes) -
2124                 cp_hdr->jt_size * 4;
2125         gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
2126                                                    FIRMWARE_ID_CP_MEC,
2127                                                    fw_data, fw_size);
2128         /* mec2 ucode is not necessary if mec2 ucode is same as mec1 */
2129 }
2130
2131 /* Temporarily put sdma part here */
2132 static void gfx_v10_0_rlc_backdoor_autoload_copy_sdma_ucode(struct amdgpu_device *adev)
2133 {
2134         const __le32 *fw_data;
2135         uint32_t fw_size;
2136         const struct sdma_firmware_header_v1_0 *sdma_hdr;
2137         int i;
2138
2139         for (i = 0; i < adev->sdma.num_instances; i++) {
2140                 sdma_hdr = (const struct sdma_firmware_header_v1_0 *)
2141                         adev->sdma.instance[i].fw->data;
2142                 fw_data = (const __le32 *) (adev->sdma.instance[i].fw->data +
2143                         le32_to_cpu(sdma_hdr->header.ucode_array_offset_bytes));
2144                 fw_size = le32_to_cpu(sdma_hdr->header.ucode_size_bytes);
2145
2146                 if (i == 0) {
2147                         gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
2148                                 FIRMWARE_ID_SDMA0_UCODE, fw_data, fw_size);
2149                         gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
2150                                 FIRMWARE_ID_SDMA0_JT,
2151                                 (uint32_t *)fw_data +
2152                                 sdma_hdr->jt_offset,
2153                                 sdma_hdr->jt_size * 4);
2154                 } else if (i == 1) {
2155                         gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
2156                                 FIRMWARE_ID_SDMA1_UCODE, fw_data, fw_size);
2157                         gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
2158                                 FIRMWARE_ID_SDMA1_JT,
2159                                 (uint32_t *)fw_data +
2160                                 sdma_hdr->jt_offset,
2161                                 sdma_hdr->jt_size * 4);
2162                 }
2163         }
2164 }
2165
2166 static int gfx_v10_0_rlc_backdoor_autoload_enable(struct amdgpu_device *adev)
2167 {
2168         uint32_t rlc_g_offset, rlc_g_size, tmp;
2169         uint64_t gpu_addr;
2170
2171         gfx_v10_0_rlc_backdoor_autoload_copy_toc_ucode(adev);
2172         gfx_v10_0_rlc_backdoor_autoload_copy_sdma_ucode(adev);
2173         gfx_v10_0_rlc_backdoor_autoload_copy_gfx_ucode(adev);
2174
2175         rlc_g_offset = rlc_autoload_info[FIRMWARE_ID_RLC_G_UCODE].offset;
2176         rlc_g_size = rlc_autoload_info[FIRMWARE_ID_RLC_G_UCODE].size;
2177         gpu_addr = adev->gfx.rlc.rlc_autoload_gpu_addr + rlc_g_offset;
2178
2179         WREG32_SOC15(GC, 0, mmRLC_HYP_BOOTLOAD_ADDR_HI, upper_32_bits(gpu_addr));
2180         WREG32_SOC15(GC, 0, mmRLC_HYP_BOOTLOAD_ADDR_LO, lower_32_bits(gpu_addr));
2181         WREG32_SOC15(GC, 0, mmRLC_HYP_BOOTLOAD_SIZE, rlc_g_size);
2182
2183         tmp = RREG32_SOC15(GC, 0, mmRLC_HYP_RESET_VECTOR);
2184         if (!(tmp & (RLC_HYP_RESET_VECTOR__COLD_BOOT_EXIT_MASK |
2185                    RLC_HYP_RESET_VECTOR__VDDGFX_EXIT_MASK))) {
2186                 DRM_ERROR("Neither COLD_BOOT_EXIT nor VDDGFX_EXIT is set\n");
2187                 return -EINVAL;
2188         }
2189
2190         tmp = RREG32_SOC15(GC, 0, mmRLC_CNTL);
2191         if (tmp & RLC_CNTL__RLC_ENABLE_F32_MASK) {
2192                 DRM_ERROR("RLC ROM should halt itself\n");
2193                 return -EINVAL;
2194         }
2195
2196         return 0;
2197 }
2198
2199 static int gfx_v10_0_rlc_backdoor_autoload_config_me_cache(struct amdgpu_device *adev)
2200 {
2201         uint32_t usec_timeout = 50000;  /* wait for 50ms */
2202         uint32_t tmp;
2203         int i;
2204         uint64_t addr;
2205
2206         /* Trigger an invalidation of the L1 instruction caches */
2207         tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL);
2208         tmp = REG_SET_FIELD(tmp, CP_ME_IC_OP_CNTL, INVALIDATE_CACHE, 1);
2209         WREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL, tmp);
2210
2211         /* Wait for invalidation complete */
2212         for (i = 0; i < usec_timeout; i++) {
2213                 tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL);
2214                 if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL,
2215                         INVALIDATE_CACHE_COMPLETE))
2216                         break;
2217                 udelay(1);
2218         }
2219
2220         if (i >= usec_timeout) {
2221                 dev_err(adev->dev, "failed to invalidate instruction cache\n");
2222                 return -EINVAL;
2223         }
2224
2225         /* Program me ucode address into intruction cache address register */
2226         addr = adev->gfx.rlc.rlc_autoload_gpu_addr +
2227                 rlc_autoload_info[FIRMWARE_ID_CP_ME].offset;
2228         WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_LO,
2229                         lower_32_bits(addr) & 0xFFFFF000);
2230         WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_HI,
2231                         upper_32_bits(addr));
2232
2233         return 0;
2234 }
2235
2236 static int gfx_v10_0_rlc_backdoor_autoload_config_ce_cache(struct amdgpu_device *adev)
2237 {
2238         uint32_t usec_timeout = 50000;  /* wait for 50ms */
2239         uint32_t tmp;
2240         int i;
2241         uint64_t addr;
2242
2243         /* Trigger an invalidation of the L1 instruction caches */
2244         tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL);
2245         tmp = REG_SET_FIELD(tmp, CP_CE_IC_OP_CNTL, INVALIDATE_CACHE, 1);
2246         WREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL, tmp);
2247
2248         /* Wait for invalidation complete */
2249         for (i = 0; i < usec_timeout; i++) {
2250                 tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL);
2251                 if (1 == REG_GET_FIELD(tmp, CP_CE_IC_OP_CNTL,
2252                         INVALIDATE_CACHE_COMPLETE))
2253                         break;
2254                 udelay(1);
2255         }
2256
2257         if (i >= usec_timeout) {
2258                 dev_err(adev->dev, "failed to invalidate instruction cache\n");
2259                 return -EINVAL;
2260         }
2261
2262         /* Program ce ucode address into intruction cache address register */
2263         addr = adev->gfx.rlc.rlc_autoload_gpu_addr +
2264                 rlc_autoload_info[FIRMWARE_ID_CP_CE].offset;
2265         WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_LO,
2266                         lower_32_bits(addr) & 0xFFFFF000);
2267         WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_HI,
2268                         upper_32_bits(addr));
2269
2270         return 0;
2271 }
2272
2273 static int gfx_v10_0_rlc_backdoor_autoload_config_pfp_cache(struct amdgpu_device *adev)
2274 {
2275         uint32_t usec_timeout = 50000;  /* wait for 50ms */
2276         uint32_t tmp;
2277         int i;
2278         uint64_t addr;
2279
2280         /* Trigger an invalidation of the L1 instruction caches */
2281         tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL);
2282         tmp = REG_SET_FIELD(tmp, CP_PFP_IC_OP_CNTL, INVALIDATE_CACHE, 1);
2283         WREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL, tmp);
2284
2285         /* Wait for invalidation complete */
2286         for (i = 0; i < usec_timeout; i++) {
2287                 tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL);
2288                 if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL,
2289                         INVALIDATE_CACHE_COMPLETE))
2290                         break;
2291                 udelay(1);
2292         }
2293
2294         if (i >= usec_timeout) {
2295                 dev_err(adev->dev, "failed to invalidate instruction cache\n");
2296                 return -EINVAL;
2297         }
2298
2299         /* Program pfp ucode address into intruction cache address register */
2300         addr = adev->gfx.rlc.rlc_autoload_gpu_addr +
2301                 rlc_autoload_info[FIRMWARE_ID_CP_PFP].offset;
2302         WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_LO,
2303                         lower_32_bits(addr) & 0xFFFFF000);
2304         WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_HI,
2305                         upper_32_bits(addr));
2306
2307         return 0;
2308 }
2309
2310 static int gfx_v10_0_rlc_backdoor_autoload_config_mec_cache(struct amdgpu_device *adev)
2311 {
2312         uint32_t usec_timeout = 50000;  /* wait for 50ms */
2313         uint32_t tmp;
2314         int i;
2315         uint64_t addr;
2316
2317         /* Trigger an invalidation of the L1 instruction caches */
2318         tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL);
2319         tmp = REG_SET_FIELD(tmp, CP_CPC_IC_OP_CNTL, INVALIDATE_CACHE, 1);
2320         WREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL, tmp);
2321
2322         /* Wait for invalidation complete */
2323         for (i = 0; i < usec_timeout; i++) {
2324                 tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL);
2325                 if (1 == REG_GET_FIELD(tmp, CP_CPC_IC_OP_CNTL,
2326                         INVALIDATE_CACHE_COMPLETE))
2327                         break;
2328                 udelay(1);
2329         }
2330
2331         if (i >= usec_timeout) {
2332                 dev_err(adev->dev, "failed to invalidate instruction cache\n");
2333                 return -EINVAL;
2334         }
2335
2336         /* Program mec1 ucode address into intruction cache address register */
2337         addr = adev->gfx.rlc.rlc_autoload_gpu_addr +
2338                 rlc_autoload_info[FIRMWARE_ID_CP_MEC].offset;
2339         WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_LO,
2340                         lower_32_bits(addr) & 0xFFFFF000);
2341         WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_HI,
2342                         upper_32_bits(addr));
2343
2344         return 0;
2345 }
2346
2347 static int gfx_v10_0_wait_for_rlc_autoload_complete(struct amdgpu_device *adev)
2348 {
2349         uint32_t cp_status;
2350         uint32_t bootload_status;
2351         int i, r;
2352
2353         for (i = 0; i < adev->usec_timeout; i++) {
2354                 cp_status = RREG32_SOC15(GC, 0, mmCP_STAT);
2355                 bootload_status = RREG32_SOC15(GC, 0, mmRLC_RLCS_BOOTLOAD_STATUS);
2356                 if ((cp_status == 0) &&
2357                     (REG_GET_FIELD(bootload_status,
2358                         RLC_RLCS_BOOTLOAD_STATUS, BOOTLOAD_COMPLETE) == 1)) {
2359                         break;
2360                 }
2361                 udelay(1);
2362         }
2363
2364         if (i >= adev->usec_timeout) {
2365                 dev_err(adev->dev, "rlc autoload: gc ucode autoload timeout\n");
2366                 return -ETIMEDOUT;
2367         }
2368
2369         if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) {
2370                 r = gfx_v10_0_rlc_backdoor_autoload_config_me_cache(adev);
2371                 if (r)
2372                         return r;
2373
2374                 r = gfx_v10_0_rlc_backdoor_autoload_config_ce_cache(adev);
2375                 if (r)
2376                         return r;
2377
2378                 r = gfx_v10_0_rlc_backdoor_autoload_config_pfp_cache(adev);
2379                 if (r)
2380                         return r;
2381
2382                 r = gfx_v10_0_rlc_backdoor_autoload_config_mec_cache(adev);
2383                 if (r)
2384                         return r;
2385         }
2386
2387         return 0;
2388 }
2389
2390 static int gfx_v10_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable)
2391 {
2392         int i;
2393         u32 tmp = RREG32_SOC15(GC, 0, mmCP_ME_CNTL);
2394
2395         tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, enable ? 0 : 1);
2396         tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, enable ? 0 : 1);
2397         tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_HALT, enable ? 0 : 1);
2398         if (!enable) {
2399                 for (i = 0; i < adev->gfx.num_gfx_rings; i++)
2400                         adev->gfx.gfx_ring[i].sched.ready = false;
2401         }
2402         WREG32_SOC15(GC, 0, mmCP_ME_CNTL, tmp);
2403
2404         for (i = 0; i < adev->usec_timeout; i++) {
2405                 if (RREG32_SOC15(GC, 0, mmCP_STAT) == 0)
2406                         break;
2407                 udelay(1);
2408         }
2409
2410         if (i >= adev->usec_timeout)
2411                 DRM_ERROR("failed to %s cp gfx\n", enable ? "unhalt" : "halt");
2412
2413         return 0;
2414 }
2415
2416 static int gfx_v10_0_cp_gfx_load_pfp_microcode(struct amdgpu_device *adev)
2417 {
2418         int r;
2419         const struct gfx_firmware_header_v1_0 *pfp_hdr;
2420         const __le32 *fw_data;
2421         unsigned i, fw_size;
2422         uint32_t tmp;
2423         uint32_t usec_timeout = 50000;  /* wait for 50ms */
2424
2425         pfp_hdr = (const struct gfx_firmware_header_v1_0 *)
2426                 adev->gfx.pfp_fw->data;
2427
2428         amdgpu_ucode_print_gfx_hdr(&pfp_hdr->header);
2429
2430         fw_data = (const __le32 *)(adev->gfx.pfp_fw->data +
2431                 le32_to_cpu(pfp_hdr->header.ucode_array_offset_bytes));
2432         fw_size = le32_to_cpu(pfp_hdr->header.ucode_size_bytes);
2433
2434         r = amdgpu_bo_create_reserved(adev, pfp_hdr->header.ucode_size_bytes,
2435                                       PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,
2436                                       &adev->gfx.pfp.pfp_fw_obj,
2437                                       &adev->gfx.pfp.pfp_fw_gpu_addr,
2438                                       (void **)&adev->gfx.pfp.pfp_fw_ptr);
2439         if (r) {
2440                 dev_err(adev->dev, "(%d) failed to create pfp fw bo\n", r);
2441                 gfx_v10_0_pfp_fini(adev);
2442                 return r;
2443         }
2444
2445         memcpy(adev->gfx.pfp.pfp_fw_ptr, fw_data, fw_size);
2446
2447         amdgpu_bo_kunmap(adev->gfx.pfp.pfp_fw_obj);
2448         amdgpu_bo_unreserve(adev->gfx.pfp.pfp_fw_obj);
2449
2450         /* Trigger an invalidation of the L1 instruction caches */
2451         tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL);
2452         tmp = REG_SET_FIELD(tmp, CP_PFP_IC_OP_CNTL, INVALIDATE_CACHE, 1);
2453         WREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL, tmp);
2454
2455         /* Wait for invalidation complete */
2456         for (i = 0; i < usec_timeout; i++) {
2457                 tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL);
2458                 if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL,
2459                         INVALIDATE_CACHE_COMPLETE))
2460                         break;
2461                 udelay(1);
2462         }
2463
2464         if (i >= usec_timeout) {
2465                 dev_err(adev->dev, "failed to invalidate instruction cache\n");
2466                 return -EINVAL;
2467         }
2468
2469         if (amdgpu_emu_mode == 1)
2470                 adev->nbio.funcs->hdp_flush(adev, NULL);
2471
2472         tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_CNTL);
2473         tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, VMID, 0);
2474         tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, CACHE_POLICY, 0);
2475         tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, EXE_DISABLE, 0);
2476         tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, ADDRESS_CLAMP, 1);
2477         WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_CNTL, tmp);
2478         WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_LO,
2479                 adev->gfx.pfp.pfp_fw_gpu_addr & 0xFFFFF000);
2480         WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_HI,
2481                 upper_32_bits(adev->gfx.pfp.pfp_fw_gpu_addr));
2482
2483         return 0;
2484 }
2485
2486 static int gfx_v10_0_cp_gfx_load_ce_microcode(struct amdgpu_device *adev)
2487 {
2488         int r;
2489         const struct gfx_firmware_header_v1_0 *ce_hdr;
2490         const __le32 *fw_data;
2491         unsigned i, fw_size;
2492         uint32_t tmp;
2493         uint32_t usec_timeout = 50000;  /* wait for 50ms */
2494
2495         ce_hdr = (const struct gfx_firmware_header_v1_0 *)
2496                 adev->gfx.ce_fw->data;
2497
2498         amdgpu_ucode_print_gfx_hdr(&ce_hdr->header);
2499
2500         fw_data = (const __le32 *)(adev->gfx.ce_fw->data +
2501                 le32_to_cpu(ce_hdr->header.ucode_array_offset_bytes));
2502         fw_size = le32_to_cpu(ce_hdr->header.ucode_size_bytes);
2503
2504         r = amdgpu_bo_create_reserved(adev, ce_hdr->header.ucode_size_bytes,
2505                                       PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,
2506                                       &adev->gfx.ce.ce_fw_obj,
2507                                       &adev->gfx.ce.ce_fw_gpu_addr,
2508                                       (void **)&adev->gfx.ce.ce_fw_ptr);
2509         if (r) {
2510                 dev_err(adev->dev, "(%d) failed to create ce fw bo\n", r);
2511                 gfx_v10_0_ce_fini(adev);
2512                 return r;
2513         }
2514
2515         memcpy(adev->gfx.ce.ce_fw_ptr, fw_data, fw_size);
2516
2517         amdgpu_bo_kunmap(adev->gfx.ce.ce_fw_obj);
2518         amdgpu_bo_unreserve(adev->gfx.ce.ce_fw_obj);
2519
2520         /* Trigger an invalidation of the L1 instruction caches */
2521         tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL);
2522         tmp = REG_SET_FIELD(tmp, CP_CE_IC_OP_CNTL, INVALIDATE_CACHE, 1);
2523         WREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL, tmp);
2524
2525         /* Wait for invalidation complete */
2526         for (i = 0; i < usec_timeout; i++) {
2527                 tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL);
2528                 if (1 == REG_GET_FIELD(tmp, CP_CE_IC_OP_CNTL,
2529                         INVALIDATE_CACHE_COMPLETE))
2530                         break;
2531                 udelay(1);
2532         }
2533
2534         if (i >= usec_timeout) {
2535                 dev_err(adev->dev, "failed to invalidate instruction cache\n");
2536                 return -EINVAL;
2537         }
2538
2539         if (amdgpu_emu_mode == 1)
2540                 adev->nbio.funcs->hdp_flush(adev, NULL);
2541
2542         tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_CNTL);
2543         tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, VMID, 0);
2544         tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, CACHE_POLICY, 0);
2545         tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, EXE_DISABLE, 0);
2546         tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, ADDRESS_CLAMP, 1);
2547         WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_LO,
2548                 adev->gfx.ce.ce_fw_gpu_addr & 0xFFFFF000);
2549         WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_HI,
2550                 upper_32_bits(adev->gfx.ce.ce_fw_gpu_addr));
2551
2552         return 0;
2553 }
2554
2555 static int gfx_v10_0_cp_gfx_load_me_microcode(struct amdgpu_device *adev)
2556 {
2557         int r;
2558         const struct gfx_firmware_header_v1_0 *me_hdr;
2559         const __le32 *fw_data;
2560         unsigned i, fw_size;
2561         uint32_t tmp;
2562         uint32_t usec_timeout = 50000;  /* wait for 50ms */
2563
2564         me_hdr = (const struct gfx_firmware_header_v1_0 *)
2565                 adev->gfx.me_fw->data;
2566
2567         amdgpu_ucode_print_gfx_hdr(&me_hdr->header);
2568
2569         fw_data = (const __le32 *)(adev->gfx.me_fw->data +
2570                 le32_to_cpu(me_hdr->header.ucode_array_offset_bytes));
2571         fw_size = le32_to_cpu(me_hdr->header.ucode_size_bytes);
2572
2573         r = amdgpu_bo_create_reserved(adev, me_hdr->header.ucode_size_bytes,
2574                                       PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,
2575                                       &adev->gfx.me.me_fw_obj,
2576                                       &adev->gfx.me.me_fw_gpu_addr,
2577                                       (void **)&adev->gfx.me.me_fw_ptr);
2578         if (r) {
2579                 dev_err(adev->dev, "(%d) failed to create me fw bo\n", r);
2580                 gfx_v10_0_me_fini(adev);
2581                 return r;
2582         }
2583
2584         memcpy(adev->gfx.me.me_fw_ptr, fw_data, fw_size);
2585
2586         amdgpu_bo_kunmap(adev->gfx.me.me_fw_obj);
2587         amdgpu_bo_unreserve(adev->gfx.me.me_fw_obj);
2588
2589         /* Trigger an invalidation of the L1 instruction caches */
2590         tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL);
2591         tmp = REG_SET_FIELD(tmp, CP_ME_IC_OP_CNTL, INVALIDATE_CACHE, 1);
2592         WREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL, tmp);
2593
2594         /* Wait for invalidation complete */
2595         for (i = 0; i < usec_timeout; i++) {
2596                 tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL);
2597                 if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL,
2598                         INVALIDATE_CACHE_COMPLETE))
2599                         break;
2600                 udelay(1);
2601         }
2602
2603         if (i >= usec_timeout) {
2604                 dev_err(adev->dev, "failed to invalidate instruction cache\n");
2605                 return -EINVAL;
2606         }
2607
2608         if (amdgpu_emu_mode == 1)
2609                 adev->nbio.funcs->hdp_flush(adev, NULL);
2610
2611         tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_CNTL);
2612         tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, VMID, 0);
2613         tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, CACHE_POLICY, 0);
2614         tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, EXE_DISABLE, 0);
2615         tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, ADDRESS_CLAMP, 1);
2616         WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_LO,
2617                 adev->gfx.me.me_fw_gpu_addr & 0xFFFFF000);
2618         WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_HI,
2619                 upper_32_bits(adev->gfx.me.me_fw_gpu_addr));
2620
2621         return 0;
2622 }
2623
2624 static int gfx_v10_0_cp_gfx_load_microcode(struct amdgpu_device *adev)
2625 {
2626         int r;
2627
2628         if (!adev->gfx.me_fw || !adev->gfx.pfp_fw || !adev->gfx.ce_fw)
2629                 return -EINVAL;
2630
2631         gfx_v10_0_cp_gfx_enable(adev, false);
2632
2633         r = gfx_v10_0_cp_gfx_load_pfp_microcode(adev);
2634         if (r) {
2635                 dev_err(adev->dev, "(%d) failed to load pfp fw\n", r);
2636                 return r;
2637         }
2638
2639         r = gfx_v10_0_cp_gfx_load_ce_microcode(adev);
2640         if (r) {
2641                 dev_err(adev->dev, "(%d) failed to load ce fw\n", r);
2642                 return r;
2643         }
2644
2645         r = gfx_v10_0_cp_gfx_load_me_microcode(adev);
2646         if (r) {
2647                 dev_err(adev->dev, "(%d) failed to load me fw\n", r);
2648                 return r;
2649         }
2650
2651         return 0;
2652 }
2653
2654 static int gfx_v10_0_cp_gfx_start(struct amdgpu_device *adev)
2655 {
2656         struct amdgpu_ring *ring;
2657         const struct cs_section_def *sect = NULL;
2658         const struct cs_extent_def *ext = NULL;
2659         int r, i;
2660         int ctx_reg_offset;
2661
2662         /* init the CP */
2663         WREG32_SOC15(GC, 0, mmCP_MAX_CONTEXT,
2664                      adev->gfx.config.max_hw_contexts - 1);
2665         WREG32_SOC15(GC, 0, mmCP_DEVICE_ID, 1);
2666
2667         gfx_v10_0_cp_gfx_enable(adev, true);
2668
2669         ring = &adev->gfx.gfx_ring[0];
2670         r = amdgpu_ring_alloc(ring, gfx_v10_0_get_csb_size(adev) + 4);
2671         if (r) {
2672                 DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r);
2673                 return r;
2674         }
2675
2676         amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
2677         amdgpu_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
2678
2679         amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1));
2680         amdgpu_ring_write(ring, 0x80000000);
2681         amdgpu_ring_write(ring, 0x80000000);
2682
2683         for (sect = gfx10_cs_data; sect->section != NULL; ++sect) {
2684                 for (ext = sect->section; ext->extent != NULL; ++ext) {
2685                         if (sect->id == SECT_CONTEXT) {
2686                                 amdgpu_ring_write(ring,
2687                                                   PACKET3(PACKET3_SET_CONTEXT_REG,
2688                                                           ext->reg_count));
2689                                 amdgpu_ring_write(ring, ext->reg_index -
2690                                                   PACKET3_SET_CONTEXT_REG_START);
2691                                 for (i = 0; i < ext->reg_count; i++)
2692                                         amdgpu_ring_write(ring, ext->extent[i]);
2693                         }
2694                 }
2695         }
2696
2697         ctx_reg_offset =
2698                 SOC15_REG_OFFSET(GC, 0, mmPA_SC_TILE_STEERING_OVERRIDE) - PACKET3_SET_CONTEXT_REG_START;
2699         amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
2700         amdgpu_ring_write(ring, ctx_reg_offset);
2701         amdgpu_ring_write(ring, adev->gfx.config.pa_sc_tile_steering_override);
2702
2703         amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
2704         amdgpu_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE);
2705
2706         amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));
2707         amdgpu_ring_write(ring, 0);
2708
2709         amdgpu_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2));
2710         amdgpu_ring_write(ring, PACKET3_BASE_INDEX(CE_PARTITION_BASE));
2711         amdgpu_ring_write(ring, 0x8000);
2712         amdgpu_ring_write(ring, 0x8000);
2713
2714         amdgpu_ring_commit(ring);
2715
2716         /* submit cs packet to copy state 0 to next available state */
2717         ring = &adev->gfx.gfx_ring[1];
2718         r = amdgpu_ring_alloc(ring, 2);
2719         if (r) {
2720                 DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r);
2721                 return r;
2722         }
2723
2724         amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));
2725         amdgpu_ring_write(ring, 0);
2726
2727         amdgpu_ring_commit(ring);
2728
2729         return 0;
2730 }
2731
2732 static void gfx_v10_0_cp_gfx_switch_pipe(struct amdgpu_device *adev,
2733                                          CP_PIPE_ID pipe)
2734 {
2735         u32 tmp;
2736
2737         tmp = RREG32_SOC15(GC, 0, mmGRBM_GFX_CNTL);
2738         tmp = REG_SET_FIELD(tmp, GRBM_GFX_CNTL, PIPEID, pipe);
2739
2740         WREG32_SOC15(GC, 0, mmGRBM_GFX_CNTL, tmp);
2741 }
2742
2743 static void gfx_v10_0_cp_gfx_set_doorbell(struct amdgpu_device *adev,
2744                                           struct amdgpu_ring *ring)
2745 {
2746         u32 tmp;
2747
2748         tmp = RREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL);
2749         if (ring->use_doorbell) {
2750                 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
2751                                     DOORBELL_OFFSET, ring->doorbell_index);
2752                 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
2753                                     DOORBELL_EN, 1);
2754         } else {
2755                 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
2756                                     DOORBELL_EN, 0);
2757         }
2758         WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL, tmp);
2759         tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER,
2760                             DOORBELL_RANGE_LOWER, ring->doorbell_index);
2761         WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_LOWER, tmp);
2762
2763         WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_UPPER,
2764                      CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_MASK);
2765 }
2766
2767 static int gfx_v10_0_cp_gfx_resume(struct amdgpu_device *adev)
2768 {
2769         struct amdgpu_ring *ring;
2770         u32 tmp;
2771         u32 rb_bufsz;
2772         u64 rb_addr, rptr_addr, wptr_gpu_addr;
2773         u32 i;
2774
2775         /* Set the write pointer delay */
2776         WREG32_SOC15(GC, 0, mmCP_RB_WPTR_DELAY, 0);
2777
2778         /* set the RB to use vmid 0 */
2779         WREG32_SOC15(GC, 0, mmCP_RB_VMID, 0);
2780
2781         /* Init gfx ring 0 for pipe 0 */
2782         mutex_lock(&adev->srbm_mutex);
2783         gfx_v10_0_cp_gfx_switch_pipe(adev, PIPE_ID0);
2784
2785         /* Set ring buffer size */
2786         ring = &adev->gfx.gfx_ring[0];
2787         rb_bufsz = order_base_2(ring->ring_size / 8);
2788         tmp = REG_SET_FIELD(0, CP_RB0_CNTL, RB_BUFSZ, rb_bufsz);
2789         tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, RB_BLKSZ, rb_bufsz - 2);
2790 #ifdef __BIG_ENDIAN
2791         tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, BUF_SWAP, 1);
2792 #endif
2793         WREG32_SOC15(GC, 0, mmCP_RB0_CNTL, tmp);
2794
2795         /* Initialize the ring buffer's write pointers */
2796         ring->wptr = 0;
2797         WREG32_SOC15(GC, 0, mmCP_RB0_WPTR, lower_32_bits(ring->wptr));
2798         WREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI, upper_32_bits(ring->wptr));
2799
2800         /* set the wb address wether it's enabled or not */
2801         rptr_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
2802         WREG32_SOC15(GC, 0, mmCP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr));
2803         WREG32_SOC15(GC, 0, mmCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) &
2804                      CP_RB_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK);
2805
2806         wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
2807         WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_LO,
2808                      lower_32_bits(wptr_gpu_addr));
2809         WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI,
2810                      upper_32_bits(wptr_gpu_addr));
2811
2812         mdelay(1);
2813         WREG32_SOC15(GC, 0, mmCP_RB0_CNTL, tmp);
2814
2815         rb_addr = ring->gpu_addr >> 8;
2816         WREG32_SOC15(GC, 0, mmCP_RB0_BASE, rb_addr);
2817         WREG32_SOC15(GC, 0, mmCP_RB0_BASE_HI, upper_32_bits(rb_addr));
2818
2819         WREG32_SOC15(GC, 0, mmCP_RB_ACTIVE, 1);
2820
2821         gfx_v10_0_cp_gfx_set_doorbell(adev, ring);
2822         mutex_unlock(&adev->srbm_mutex);
2823
2824         /* Init gfx ring 1 for pipe 1 */
2825         mutex_lock(&adev->srbm_mutex);
2826         gfx_v10_0_cp_gfx_switch_pipe(adev, PIPE_ID1);
2827         ring = &adev->gfx.gfx_ring[1];
2828         rb_bufsz = order_base_2(ring->ring_size / 8);
2829         tmp = REG_SET_FIELD(0, CP_RB1_CNTL, RB_BUFSZ, rb_bufsz);
2830         tmp = REG_SET_FIELD(tmp, CP_RB1_CNTL, RB_BLKSZ, rb_bufsz - 2);
2831         WREG32_SOC15(GC, 0, mmCP_RB1_CNTL, tmp);
2832         /* Initialize the ring buffer's write pointers */
2833         ring->wptr = 0;
2834         WREG32_SOC15(GC, 0, mmCP_RB1_WPTR, lower_32_bits(ring->wptr));
2835         WREG32_SOC15(GC, 0, mmCP_RB1_WPTR_HI, upper_32_bits(ring->wptr));
2836         /* Set the wb address wether it's enabled or not */
2837         rptr_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
2838         WREG32_SOC15(GC, 0, mmCP_RB1_RPTR_ADDR, lower_32_bits(rptr_addr));
2839         WREG32_SOC15(GC, 0, mmCP_RB1_RPTR_ADDR_HI, upper_32_bits(rptr_addr) &
2840                 CP_RB1_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK);
2841         wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
2842         WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_LO,
2843                 lower_32_bits(wptr_gpu_addr));
2844         WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI,
2845                 upper_32_bits(wptr_gpu_addr));
2846
2847         mdelay(1);
2848         WREG32_SOC15(GC, 0, mmCP_RB1_CNTL, tmp);
2849
2850         rb_addr = ring->gpu_addr >> 8;
2851         WREG32_SOC15(GC, 0, mmCP_RB1_BASE, rb_addr);
2852         WREG32_SOC15(GC, 0, mmCP_RB1_BASE_HI, upper_32_bits(rb_addr));
2853         WREG32_SOC15(GC, 0, mmCP_RB1_ACTIVE, 1);
2854
2855         gfx_v10_0_cp_gfx_set_doorbell(adev, ring);
2856         mutex_unlock(&adev->srbm_mutex);
2857
2858         /* Switch to pipe 0 */
2859         mutex_lock(&adev->srbm_mutex);
2860         gfx_v10_0_cp_gfx_switch_pipe(adev, PIPE_ID0);
2861         mutex_unlock(&adev->srbm_mutex);
2862
2863         /* start the ring */
2864         gfx_v10_0_cp_gfx_start(adev);
2865
2866         for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
2867                 ring = &adev->gfx.gfx_ring[i];
2868                 ring->sched.ready = true;
2869         }
2870
2871         return 0;
2872 }
2873
2874 static void gfx_v10_0_cp_compute_enable(struct amdgpu_device *adev, bool enable)
2875 {
2876         int i;
2877
2878         if (enable) {
2879                 WREG32_SOC15(GC, 0, mmCP_MEC_CNTL, 0);
2880         } else {
2881                 WREG32_SOC15(GC, 0, mmCP_MEC_CNTL,
2882                              (CP_MEC_CNTL__MEC_ME1_HALT_MASK |
2883                               CP_MEC_CNTL__MEC_ME2_HALT_MASK));
2884                 for (i = 0; i < adev->gfx.num_compute_rings; i++)
2885                         adev->gfx.compute_ring[i].sched.ready = false;
2886                 adev->gfx.kiq.ring.sched.ready = false;
2887         }
2888         udelay(50);
2889 }
2890
2891 static int gfx_v10_0_cp_compute_load_microcode(struct amdgpu_device *adev)
2892 {
2893         const struct gfx_firmware_header_v1_0 *mec_hdr;
2894         const __le32 *fw_data;
2895         unsigned i;
2896         u32 tmp;
2897         u32 usec_timeout = 50000; /* Wait for 50 ms */
2898
2899         if (!adev->gfx.mec_fw)
2900                 return -EINVAL;
2901
2902         gfx_v10_0_cp_compute_enable(adev, false);
2903
2904         mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
2905         amdgpu_ucode_print_gfx_hdr(&mec_hdr->header);
2906
2907         fw_data = (const __le32 *)
2908                 (adev->gfx.mec_fw->data +
2909                  le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes));
2910
2911         /* Trigger an invalidation of the L1 instruction caches */
2912         tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL);
2913         tmp = REG_SET_FIELD(tmp, CP_CPC_IC_OP_CNTL, INVALIDATE_CACHE, 1);
2914         WREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL, tmp);
2915
2916         /* Wait for invalidation complete */
2917         for (i = 0; i < usec_timeout; i++) {
2918                 tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL);
2919                 if (1 == REG_GET_FIELD(tmp, CP_CPC_IC_OP_CNTL,
2920                                        INVALIDATE_CACHE_COMPLETE))
2921                         break;
2922                 udelay(1);
2923         }
2924
2925         if (i >= usec_timeout) {
2926                 dev_err(adev->dev, "failed to invalidate instruction cache\n");
2927                 return -EINVAL;
2928         }
2929
2930         if (amdgpu_emu_mode == 1)
2931                 adev->nbio.funcs->hdp_flush(adev, NULL);
2932
2933         tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_CNTL);
2934         tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0);
2935         tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, EXE_DISABLE, 0);
2936         tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, ADDRESS_CLAMP, 1);
2937         WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_CNTL, tmp);
2938
2939         WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_LO, adev->gfx.mec.mec_fw_gpu_addr &
2940                      0xFFFFF000);
2941         WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_HI,
2942                      upper_32_bits(adev->gfx.mec.mec_fw_gpu_addr));
2943
2944         /* MEC1 */
2945         WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_ADDR, 0);
2946
2947         for (i = 0; i < mec_hdr->jt_size; i++)
2948                 WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_DATA,
2949                              le32_to_cpup(fw_data + mec_hdr->jt_offset + i));
2950
2951         WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_ADDR, adev->gfx.mec_fw_version);
2952
2953         /*
2954          * TODO: Loading MEC2 firmware is only necessary if MEC2 should run
2955          * different microcode than MEC1.
2956          */
2957
2958         return 0;
2959 }
2960
2961 static void gfx_v10_0_kiq_setting(struct amdgpu_ring *ring)
2962 {
2963         uint32_t tmp;
2964         struct amdgpu_device *adev = ring->adev;
2965
2966         /* tell RLC which is KIQ queue */
2967         tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS);
2968         tmp &= 0xffffff00;
2969         tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue);
2970         WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS, tmp);
2971         tmp |= 0x80;
2972         WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS, tmp);
2973 }
2974
2975 static int gfx_v10_0_gfx_mqd_init(struct amdgpu_ring *ring)
2976 {
2977         struct amdgpu_device *adev = ring->adev;
2978         struct v10_gfx_mqd *mqd = ring->mqd_ptr;
2979         uint64_t hqd_gpu_addr, wb_gpu_addr;
2980         uint32_t tmp;
2981         uint32_t rb_bufsz;
2982
2983         /* set up gfx hqd wptr */
2984         mqd->cp_gfx_hqd_wptr = 0;
2985         mqd->cp_gfx_hqd_wptr_hi = 0;
2986
2987         /* set the pointer to the MQD */
2988         mqd->cp_mqd_base_addr = ring->mqd_gpu_addr & 0xfffffffc;
2989         mqd->cp_mqd_base_addr_hi = upper_32_bits(ring->mqd_gpu_addr);
2990
2991         /* set up mqd control */
2992         tmp = RREG32_SOC15(GC, 0, mmCP_GFX_MQD_CONTROL);
2993         tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, VMID, 0);
2994         tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, PRIV_STATE, 1);
2995         tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, CACHE_POLICY, 0);
2996         mqd->cp_gfx_mqd_control = tmp;
2997
2998         /* set up gfx_hqd_vimd with 0x0 to indicate the ring buffer's vmid */
2999         tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_VMID);
3000         tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_VMID, VMID, 0);
3001         mqd->cp_gfx_hqd_vmid = 0;
3002
3003         /* set up default queue priority level
3004          * 0x0 = low priority, 0x1 = high priority */
3005         tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_QUEUE_PRIORITY);
3006         tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_QUEUE_PRIORITY, PRIORITY_LEVEL, 0);
3007         mqd->cp_gfx_hqd_queue_priority = tmp;
3008
3009         /* set up time quantum */
3010         tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_QUANTUM);
3011         tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_QUANTUM, QUANTUM_EN, 1);
3012         mqd->cp_gfx_hqd_quantum = tmp;
3013
3014         /* set up gfx hqd base. this is similar as CP_RB_BASE */
3015         hqd_gpu_addr = ring->gpu_addr >> 8;
3016         mqd->cp_gfx_hqd_base = hqd_gpu_addr;
3017         mqd->cp_gfx_hqd_base_hi = upper_32_bits(hqd_gpu_addr);
3018
3019         /* set up hqd_rptr_addr/_hi, similar as CP_RB_RPTR */
3020         wb_gpu_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
3021         mqd->cp_gfx_hqd_rptr_addr = wb_gpu_addr & 0xfffffffc;
3022         mqd->cp_gfx_hqd_rptr_addr_hi =
3023                 upper_32_bits(wb_gpu_addr) & 0xffff;
3024
3025         /* set up rb_wptr_poll addr */
3026         wb_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
3027         mqd->cp_rb_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc;
3028         mqd->cp_rb_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff;
3029
3030         /* set up the gfx_hqd_control, similar as CP_RB0_CNTL */
3031         rb_bufsz = order_base_2(ring->ring_size / 4) - 1;
3032         tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_CNTL);
3033         tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_BUFSZ, rb_bufsz);
3034         tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_BLKSZ, rb_bufsz - 2);
3035 #ifdef __BIG_ENDIAN
3036         tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, BUF_SWAP, 1);
3037 #endif
3038         mqd->cp_gfx_hqd_cntl = tmp;
3039
3040         /* set up cp_doorbell_control */
3041         tmp = RREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL);
3042         if (ring->use_doorbell) {
3043                 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
3044                                     DOORBELL_OFFSET, ring->doorbell_index);
3045                 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
3046                                     DOORBELL_EN, 1);
3047         } else
3048                 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
3049                                     DOORBELL_EN, 0);
3050         mqd->cp_rb_doorbell_control = tmp;
3051
3052         /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */
3053         ring->wptr = 0;
3054         mqd->cp_gfx_hqd_rptr = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_RPTR);
3055
3056         /* active the queue */
3057         mqd->cp_gfx_hqd_active = 1;
3058
3059         return 0;
3060 }
3061
3062 #ifdef BRING_UP_DEBUG
3063 static int gfx_v10_0_gfx_queue_init_register(struct amdgpu_ring *ring)
3064 {
3065         struct amdgpu_device *adev = ring->adev;
3066         struct v10_gfx_mqd *mqd = ring->mqd_ptr;
3067
3068         /* set mmCP_GFX_HQD_WPTR/_HI to 0 */
3069         WREG32_SOC15(GC, 0, mmCP_GFX_HQD_WPTR, mqd->cp_gfx_hqd_wptr);
3070         WREG32_SOC15(GC, 0, mmCP_GFX_HQD_WPTR_HI, mqd->cp_gfx_hqd_wptr_hi);
3071
3072         /* set GFX_MQD_BASE */
3073         WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR, mqd->cp_mqd_base_addr);
3074         WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR_HI, mqd->cp_mqd_base_addr_hi);
3075
3076         /* set GFX_MQD_CONTROL */
3077         WREG32_SOC15(GC, 0, mmCP_GFX_MQD_CONTROL, mqd->cp_gfx_mqd_control);
3078
3079         /* set GFX_HQD_VMID to 0 */
3080         WREG32_SOC15(GC, 0, mmCP_GFX_HQD_VMID, mqd->cp_gfx_hqd_vmid);
3081
3082         WREG32_SOC15(GC, 0, mmCP_GFX_HQD_QUEUE_PRIORITY,
3083                         mqd->cp_gfx_hqd_queue_priority);
3084         WREG32_SOC15(GC, 0, mmCP_GFX_HQD_QUANTUM, mqd->cp_gfx_hqd_quantum);
3085
3086         /* set GFX_HQD_BASE, similar as CP_RB_BASE */
3087         WREG32_SOC15(GC, 0, mmCP_GFX_HQD_BASE, mqd->cp_gfx_hqd_base);
3088         WREG32_SOC15(GC, 0, mmCP_GFX_HQD_BASE_HI, mqd->cp_gfx_hqd_base_hi);
3089
3090         /* set GFX_HQD_RPTR_ADDR, similar as CP_RB_RPTR */
3091         WREG32_SOC15(GC, 0, mmCP_GFX_HQD_RPTR_ADDR, mqd->cp_gfx_hqd_rptr_addr);
3092         WREG32_SOC15(GC, 0, mmCP_GFX_HQD_RPTR_ADDR_HI, mqd->cp_gfx_hqd_rptr_addr_hi);
3093
3094         /* set GFX_HQD_CNTL, similar as CP_RB_CNTL */
3095         WREG32_SOC15(GC, 0, mmCP_GFX_HQD_CNTL, mqd->cp_gfx_hqd_cntl);
3096
3097         /* set RB_WPTR_POLL_ADDR */
3098         WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_LO, mqd->cp_rb_wptr_poll_addr_lo);
3099         WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI, mqd->cp_rb_wptr_poll_addr_hi);
3100
3101         /* set RB_DOORBELL_CONTROL */
3102         WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL, mqd->cp_rb_doorbell_control);
3103
3104         /* active the queue */
3105         WREG32_SOC15(GC, 0, mmCP_GFX_HQD_ACTIVE, mqd->cp_gfx_hqd_active);
3106
3107         return 0;
3108 }
3109 #endif
3110
3111 static int gfx_v10_0_gfx_init_queue(struct amdgpu_ring *ring)
3112 {
3113         struct amdgpu_device *adev = ring->adev;
3114         struct v10_gfx_mqd *mqd = ring->mqd_ptr;
3115         int mqd_idx = ring - &adev->gfx.gfx_ring[0];
3116
3117         if (!adev->in_gpu_reset && !adev->in_suspend) {
3118                 memset((void *)mqd, 0, sizeof(*mqd));
3119                 mutex_lock(&adev->srbm_mutex);
3120                 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
3121                 gfx_v10_0_gfx_mqd_init(ring);
3122 #ifdef BRING_UP_DEBUG
3123                 gfx_v10_0_gfx_queue_init_register(ring);
3124 #endif
3125                 nv_grbm_select(adev, 0, 0, 0, 0);
3126                 mutex_unlock(&adev->srbm_mutex);
3127                 if (adev->gfx.me.mqd_backup[mqd_idx])
3128                         memcpy(adev->gfx.me.mqd_backup[mqd_idx], mqd, sizeof(*mqd));
3129         } else if (adev->in_gpu_reset) {
3130                 /* reset mqd with the backup copy */
3131                 if (adev->gfx.me.mqd_backup[mqd_idx])
3132                         memcpy(mqd, adev->gfx.me.mqd_backup[mqd_idx], sizeof(*mqd));
3133                 /* reset the ring */
3134                 ring->wptr = 0;
3135                 adev->wb.wb[ring->wptr_offs] = 0;
3136                 amdgpu_ring_clear_ring(ring);
3137 #ifdef BRING_UP_DEBUG
3138                 mutex_lock(&adev->srbm_mutex);
3139                 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
3140                 gfx_v10_0_gfx_queue_init_register(ring);
3141                 nv_grbm_select(adev, 0, 0, 0, 0);
3142                 mutex_unlock(&adev->srbm_mutex);
3143 #endif
3144         } else {
3145                 amdgpu_ring_clear_ring(ring);
3146         }
3147
3148         return 0;
3149 }
3150
3151 #ifndef BRING_UP_DEBUG
3152 static int gfx_v10_0_kiq_enable_kgq(struct amdgpu_device *adev)
3153 {
3154         struct amdgpu_kiq *kiq = &adev->gfx.kiq;
3155         struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring;
3156         int r, i;
3157
3158         if (!kiq->pmf || !kiq->pmf->kiq_map_queues)
3159                 return -EINVAL;
3160
3161         r = amdgpu_ring_alloc(kiq_ring, kiq->pmf->map_queues_size *
3162                                         adev->gfx.num_gfx_rings);
3163         if (r) {
3164                 DRM_ERROR("Failed to lock KIQ (%d).\n", r);
3165                 return r;
3166         }
3167
3168         for (i = 0; i < adev->gfx.num_gfx_rings; i++)
3169                 kiq->pmf->kiq_map_queues(kiq_ring, &adev->gfx.gfx_ring[i]);
3170
3171         return amdgpu_ring_test_helper(kiq_ring);
3172 }
3173 #endif
3174
3175 static int gfx_v10_0_cp_async_gfx_ring_resume(struct amdgpu_device *adev)
3176 {
3177         int r, i;
3178         struct amdgpu_ring *ring;
3179
3180         for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
3181                 ring = &adev->gfx.gfx_ring[i];
3182
3183                 r = amdgpu_bo_reserve(ring->mqd_obj, false);
3184                 if (unlikely(r != 0))
3185                         goto done;
3186
3187                 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr);
3188                 if (!r) {
3189                         r = gfx_v10_0_gfx_init_queue(ring);
3190                         amdgpu_bo_kunmap(ring->mqd_obj);
3191                         ring->mqd_ptr = NULL;
3192                 }
3193                 amdgpu_bo_unreserve(ring->mqd_obj);
3194                 if (r)
3195                         goto done;
3196         }
3197 #ifndef BRING_UP_DEBUG
3198         r = gfx_v10_0_kiq_enable_kgq(adev);
3199         if (r)
3200                 goto done;
3201 #endif
3202         r = gfx_v10_0_cp_gfx_start(adev);
3203         if (r)
3204                 goto done;
3205
3206         for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
3207                 ring = &adev->gfx.gfx_ring[i];
3208                 ring->sched.ready = true;
3209         }
3210 done:
3211         return r;
3212 }
3213
3214 static int gfx_v10_0_compute_mqd_init(struct amdgpu_ring *ring)
3215 {
3216         struct amdgpu_device *adev = ring->adev;
3217         struct v10_compute_mqd *mqd = ring->mqd_ptr;
3218         uint64_t hqd_gpu_addr, wb_gpu_addr, eop_base_addr;
3219         uint32_t tmp;
3220
3221         mqd->header = 0xC0310800;
3222         mqd->compute_pipelinestat_enable = 0x00000001;
3223         mqd->compute_static_thread_mgmt_se0 = 0xffffffff;
3224         mqd->compute_static_thread_mgmt_se1 = 0xffffffff;
3225         mqd->compute_static_thread_mgmt_se2 = 0xffffffff;
3226         mqd->compute_static_thread_mgmt_se3 = 0xffffffff;
3227         mqd->compute_misc_reserved = 0x00000003;
3228
3229         eop_base_addr = ring->eop_gpu_addr >> 8;
3230         mqd->cp_hqd_eop_base_addr_lo = eop_base_addr;
3231         mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr);
3232
3233         /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */
3234         tmp = RREG32_SOC15(GC, 0, mmCP_HQD_EOP_CONTROL);
3235         tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE,
3236                         (order_base_2(GFX10_MEC_HPD_SIZE / 4) - 1));
3237
3238         mqd->cp_hqd_eop_control = tmp;
3239
3240         /* enable doorbell? */
3241         tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL);
3242
3243         if (ring->use_doorbell) {
3244                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
3245                                     DOORBELL_OFFSET, ring->doorbell_index);
3246                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
3247                                     DOORBELL_EN, 1);
3248                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
3249                                     DOORBELL_SOURCE, 0);
3250                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
3251                                     DOORBELL_HIT, 0);
3252         } else {
3253                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
3254                                     DOORBELL_EN, 0);
3255         }
3256
3257         mqd->cp_hqd_pq_doorbell_control = tmp;
3258
3259         /* disable the queue if it's active */
3260         ring->wptr = 0;
3261         mqd->cp_hqd_dequeue_request = 0;
3262         mqd->cp_hqd_pq_rptr = 0;
3263         mqd->cp_hqd_pq_wptr_lo = 0;
3264         mqd->cp_hqd_pq_wptr_hi = 0;
3265
3266         /* set the pointer to the MQD */
3267         mqd->cp_mqd_base_addr_lo = ring->mqd_gpu_addr & 0xfffffffc;
3268         mqd->cp_mqd_base_addr_hi = upper_32_bits(ring->mqd_gpu_addr);
3269
3270         /* set MQD vmid to 0 */
3271         tmp = RREG32_SOC15(GC, 0, mmCP_MQD_CONTROL);
3272         tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0);
3273         mqd->cp_mqd_control = tmp;
3274
3275         /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */
3276         hqd_gpu_addr = ring->gpu_addr >> 8;
3277         mqd->cp_hqd_pq_base_lo = hqd_gpu_addr;
3278         mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr);
3279
3280         /* set up the HQD, this is similar to CP_RB0_CNTL */
3281         tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_CONTROL);
3282         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE,
3283                             (order_base_2(ring->ring_size / 4) - 1));
3284         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE,
3285                             ((order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1) << 8));
3286 #ifdef __BIG_ENDIAN
3287         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ENDIAN_SWAP, 1);
3288 #endif
3289         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 0);
3290         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, TUNNEL_DISPATCH, 0);
3291         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1);
3292         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1);
3293         mqd->cp_hqd_pq_control = tmp;
3294
3295         /* set the wb address whether it's enabled or not */
3296         wb_gpu_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
3297         mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc;
3298         mqd->cp_hqd_pq_rptr_report_addr_hi =
3299                 upper_32_bits(wb_gpu_addr) & 0xffff;
3300
3301         /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */
3302         wb_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
3303         mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc;
3304         mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff;
3305
3306         tmp = 0;
3307         /* enable the doorbell if requested */
3308         if (ring->use_doorbell) {
3309                 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL);
3310                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
3311                                 DOORBELL_OFFSET, ring->doorbell_index);
3312
3313                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
3314                                     DOORBELL_EN, 1);
3315                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
3316                                     DOORBELL_SOURCE, 0);
3317                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
3318                                     DOORBELL_HIT, 0);
3319         }
3320
3321         mqd->cp_hqd_pq_doorbell_control = tmp;
3322
3323         /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */
3324         ring->wptr = 0;
3325         mqd->cp_hqd_pq_rptr = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR);
3326
3327         /* set the vmid for the queue */
3328         mqd->cp_hqd_vmid = 0;
3329
3330         tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PERSISTENT_STATE);
3331         tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, PRELOAD_SIZE, 0x53);
3332         mqd->cp_hqd_persistent_state = tmp;
3333
3334         /* set MIN_IB_AVAIL_SIZE */
3335         tmp = RREG32_SOC15(GC, 0, mmCP_HQD_IB_CONTROL);
3336         tmp = REG_SET_FIELD(tmp, CP_HQD_IB_CONTROL, MIN_IB_AVAIL_SIZE, 3);
3337         mqd->cp_hqd_ib_control = tmp;
3338
3339         /* map_queues packet doesn't need activate the queue,
3340          * so only kiq need set this field.
3341          */
3342         if (ring->funcs->type == AMDGPU_RING_TYPE_KIQ)
3343                 mqd->cp_hqd_active = 1;
3344
3345         return 0;
3346 }
3347
3348 static int gfx_v10_0_kiq_init_register(struct amdgpu_ring *ring)
3349 {
3350         struct amdgpu_device *adev = ring->adev;
3351         struct v10_compute_mqd *mqd = ring->mqd_ptr;
3352         int j;
3353
3354         /* disable wptr polling */
3355         WREG32_FIELD15(GC, 0, CP_PQ_WPTR_POLL_CNTL, EN, 0);
3356
3357         /* write the EOP addr */
3358         WREG32_SOC15(GC, 0, mmCP_HQD_EOP_BASE_ADDR,
3359                mqd->cp_hqd_eop_base_addr_lo);
3360         WREG32_SOC15(GC, 0, mmCP_HQD_EOP_BASE_ADDR_HI,
3361                mqd->cp_hqd_eop_base_addr_hi);
3362
3363         /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */
3364         WREG32_SOC15(GC, 0, mmCP_HQD_EOP_CONTROL,
3365                mqd->cp_hqd_eop_control);
3366
3367         /* enable doorbell? */
3368         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL,
3369                mqd->cp_hqd_pq_doorbell_control);
3370
3371         /* disable the queue if it's active */
3372         if (RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1) {
3373                 WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST, 1);
3374                 for (j = 0; j < adev->usec_timeout; j++) {
3375                         if (!(RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1))
3376                                 break;
3377                         udelay(1);
3378                 }
3379                 WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST,
3380                        mqd->cp_hqd_dequeue_request);
3381                 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR,
3382                        mqd->cp_hqd_pq_rptr);
3383                 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_LO,
3384                        mqd->cp_hqd_pq_wptr_lo);
3385                 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_HI,
3386                        mqd->cp_hqd_pq_wptr_hi);
3387         }
3388
3389         /* set the pointer to the MQD */
3390         WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR,
3391                mqd->cp_mqd_base_addr_lo);
3392         WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR_HI,
3393                mqd->cp_mqd_base_addr_hi);
3394
3395         /* set MQD vmid to 0 */
3396         WREG32_SOC15(GC, 0, mmCP_MQD_CONTROL,
3397                mqd->cp_mqd_control);
3398
3399         /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */
3400         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_BASE,
3401                mqd->cp_hqd_pq_base_lo);
3402         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_BASE_HI,
3403                mqd->cp_hqd_pq_base_hi);
3404
3405         /* set up the HQD, this is similar to CP_RB0_CNTL */
3406         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_CONTROL,
3407                mqd->cp_hqd_pq_control);
3408
3409         /* set the wb address whether it's enabled or not */
3410         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR_REPORT_ADDR,
3411                 mqd->cp_hqd_pq_rptr_report_addr_lo);
3412         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI,
3413                 mqd->cp_hqd_pq_rptr_report_addr_hi);
3414
3415         /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */
3416         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR,
3417                mqd->cp_hqd_pq_wptr_poll_addr_lo);
3418         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR_HI,
3419                mqd->cp_hqd_pq_wptr_poll_addr_hi);
3420
3421         /* enable the doorbell if requested */
3422         if (ring->use_doorbell) {
3423                 WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_LOWER,
3424                         (adev->doorbell_index.kiq * 2) << 2);
3425                 WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_UPPER,
3426                         (adev->doorbell_index.userqueue_end * 2) << 2);
3427         }
3428
3429         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL,
3430                mqd->cp_hqd_pq_doorbell_control);
3431
3432         /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */
3433         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_LO,
3434                mqd->cp_hqd_pq_wptr_lo);
3435         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_HI,
3436                mqd->cp_hqd_pq_wptr_hi);
3437
3438         /* set the vmid for the queue */
3439         WREG32_SOC15(GC, 0, mmCP_HQD_VMID, mqd->cp_hqd_vmid);
3440
3441         WREG32_SOC15(GC, 0, mmCP_HQD_PERSISTENT_STATE,
3442                mqd->cp_hqd_persistent_state);
3443
3444         /* activate the queue */
3445         WREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE,
3446                mqd->cp_hqd_active);
3447
3448         if (ring->use_doorbell)
3449                 WREG32_FIELD15(GC, 0, CP_PQ_STATUS, DOORBELL_ENABLE, 1);
3450
3451         return 0;
3452 }
3453
3454 static int gfx_v10_0_kiq_init_queue(struct amdgpu_ring *ring)
3455 {
3456         struct amdgpu_device *adev = ring->adev;
3457         struct v10_compute_mqd *mqd = ring->mqd_ptr;
3458         int mqd_idx = AMDGPU_MAX_COMPUTE_RINGS;
3459
3460         gfx_v10_0_kiq_setting(ring);
3461
3462         if (adev->in_gpu_reset) { /* for GPU_RESET case */
3463                 /* reset MQD to a clean status */
3464                 if (adev->gfx.mec.mqd_backup[mqd_idx])
3465                         memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(*mqd));
3466
3467                 /* reset ring buffer */
3468                 ring->wptr = 0;
3469                 amdgpu_ring_clear_ring(ring);
3470
3471                 mutex_lock(&adev->srbm_mutex);
3472                 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
3473                 gfx_v10_0_kiq_init_register(ring);
3474                 nv_grbm_select(adev, 0, 0, 0, 0);
3475                 mutex_unlock(&adev->srbm_mutex);
3476         } else {
3477                 memset((void *)mqd, 0, sizeof(*mqd));
3478                 mutex_lock(&adev->srbm_mutex);
3479                 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
3480                 gfx_v10_0_compute_mqd_init(ring);
3481                 gfx_v10_0_kiq_init_register(ring);
3482                 nv_grbm_select(adev, 0, 0, 0, 0);
3483                 mutex_unlock(&adev->srbm_mutex);
3484
3485                 if (adev->gfx.mec.mqd_backup[mqd_idx])
3486                         memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(*mqd));
3487         }
3488
3489         return 0;
3490 }
3491
3492 static int gfx_v10_0_kcq_init_queue(struct amdgpu_ring *ring)
3493 {
3494         struct amdgpu_device *adev = ring->adev;
3495         struct v10_compute_mqd *mqd = ring->mqd_ptr;
3496         int mqd_idx = ring - &adev->gfx.compute_ring[0];
3497
3498         if (!adev->in_gpu_reset && !adev->in_suspend) {
3499                 memset((void *)mqd, 0, sizeof(*mqd));
3500                 mutex_lock(&adev->srbm_mutex);
3501                 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
3502                 gfx_v10_0_compute_mqd_init(ring);
3503                 nv_grbm_select(adev, 0, 0, 0, 0);
3504                 mutex_unlock(&adev->srbm_mutex);
3505
3506                 if (adev->gfx.mec.mqd_backup[mqd_idx])
3507                         memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(*mqd));
3508         } else if (adev->in_gpu_reset) { /* for GPU_RESET case */
3509                 /* reset MQD to a clean status */
3510                 if (adev->gfx.mec.mqd_backup[mqd_idx])
3511                         memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(*mqd));
3512
3513                 /* reset ring buffer */
3514                 ring->wptr = 0;
3515                 atomic64_set((atomic64_t *)&adev->wb.wb[ring->wptr_offs], 0);
3516                 amdgpu_ring_clear_ring(ring);
3517         } else {
3518                 amdgpu_ring_clear_ring(ring);
3519         }
3520
3521         return 0;
3522 }
3523
3524 static int gfx_v10_0_kiq_resume(struct amdgpu_device *adev)
3525 {
3526         struct amdgpu_ring *ring;
3527         int r;
3528
3529         ring = &adev->gfx.kiq.ring;
3530
3531         r = amdgpu_bo_reserve(ring->mqd_obj, false);
3532         if (unlikely(r != 0))
3533                 return r;
3534
3535         r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr);
3536         if (unlikely(r != 0))
3537                 return r;
3538
3539         gfx_v10_0_kiq_init_queue(ring);
3540         amdgpu_bo_kunmap(ring->mqd_obj);
3541         ring->mqd_ptr = NULL;
3542         amdgpu_bo_unreserve(ring->mqd_obj);
3543         ring->sched.ready = true;
3544         return 0;
3545 }
3546
3547 static int gfx_v10_0_kcq_resume(struct amdgpu_device *adev)
3548 {
3549         struct amdgpu_ring *ring = NULL;
3550         int r = 0, i;
3551
3552         gfx_v10_0_cp_compute_enable(adev, true);
3553
3554         for (i = 0; i < adev->gfx.num_compute_rings; i++) {
3555                 ring = &adev->gfx.compute_ring[i];
3556
3557                 r = amdgpu_bo_reserve(ring->mqd_obj, false);
3558                 if (unlikely(r != 0))
3559                         goto done;
3560                 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr);
3561                 if (!r) {
3562                         r = gfx_v10_0_kcq_init_queue(ring);
3563                         amdgpu_bo_kunmap(ring->mqd_obj);
3564                         ring->mqd_ptr = NULL;
3565                 }
3566                 amdgpu_bo_unreserve(ring->mqd_obj);
3567                 if (r)
3568                         goto done;
3569         }
3570
3571         r = amdgpu_gfx_enable_kcq(adev);
3572 done:
3573         return r;
3574 }
3575
3576 static int gfx_v10_0_cp_resume(struct amdgpu_device *adev)
3577 {
3578         int r, i;
3579         struct amdgpu_ring *ring;
3580
3581         if (!(adev->flags & AMD_IS_APU))
3582                 gfx_v10_0_enable_gui_idle_interrupt(adev, false);
3583
3584         if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
3585                 /* legacy firmware loading */
3586                 r = gfx_v10_0_cp_gfx_load_microcode(adev);
3587                 if (r)
3588                         return r;
3589
3590                 r = gfx_v10_0_cp_compute_load_microcode(adev);
3591                 if (r)
3592                         return r;
3593         }
3594
3595         r = gfx_v10_0_kiq_resume(adev);
3596         if (r)
3597                 return r;
3598
3599         r = gfx_v10_0_kcq_resume(adev);
3600         if (r)
3601                 return r;
3602
3603         if (!amdgpu_async_gfx_ring) {
3604                 r = gfx_v10_0_cp_gfx_resume(adev);
3605                 if (r)
3606                         return r;
3607         } else {
3608                 r = gfx_v10_0_cp_async_gfx_ring_resume(adev);
3609                 if (r)
3610                         return r;
3611         }
3612
3613         for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
3614                 ring = &adev->gfx.gfx_ring[i];
3615                 r = amdgpu_ring_test_helper(ring);
3616                 if (r)
3617                         return r;
3618         }
3619
3620         for (i = 0; i < adev->gfx.num_compute_rings; i++) {
3621                 ring = &adev->gfx.compute_ring[i];
3622                 r = amdgpu_ring_test_helper(ring);
3623                 if (r)
3624                         return r;
3625         }
3626
3627         return 0;
3628 }
3629
3630 static void gfx_v10_0_cp_enable(struct amdgpu_device *adev, bool enable)
3631 {
3632         gfx_v10_0_cp_gfx_enable(adev, enable);
3633         gfx_v10_0_cp_compute_enable(adev, enable);
3634 }
3635
3636 static bool gfx_v10_0_check_grbm_cam_remapping(struct amdgpu_device *adev)
3637 {
3638         uint32_t data, pattern = 0xDEADBEEF;
3639
3640         /* check if mmVGT_ESGS_RING_SIZE_UMD
3641          * has been remapped to mmVGT_ESGS_RING_SIZE */
3642         data = RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE);
3643
3644         WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE, 0);
3645
3646         WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_UMD, pattern);
3647
3648         if (RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE) == pattern) {
3649                 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_UMD, data);
3650                 return true;
3651         } else {
3652                 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE, data);
3653                 return false;
3654         }
3655 }
3656
3657 static void gfx_v10_0_setup_grbm_cam_remapping(struct amdgpu_device *adev)
3658 {
3659         uint32_t data;
3660
3661         /* initialize cam_index to 0
3662          * index will auto-inc after each data writting */
3663         WREG32_SOC15(GC, 0, mmGRBM_CAM_INDEX, 0);
3664
3665         /* mmVGT_TF_RING_SIZE_UMD -> mmVGT_TF_RING_SIZE */
3666         data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE_UMD) <<
3667                 GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
3668                (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE) <<
3669                 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
3670         WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
3671         WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
3672
3673         /* mmVGT_TF_MEMORY_BASE_UMD -> mmVGT_TF_MEMORY_BASE */
3674         data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_UMD) <<
3675                 GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
3676                (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE) <<
3677                 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
3678         WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
3679         WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
3680
3681         /* mmVGT_TF_MEMORY_BASE_HI_UMD -> mmVGT_TF_MEMORY_BASE_HI */
3682         data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI_UMD) <<
3683                 GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
3684                (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI) <<
3685                 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
3686         WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
3687         WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
3688
3689         /* mmVGT_HS_OFFCHIP_PARAM_UMD -> mmVGT_HS_OFFCHIP_PARAM */
3690         data = (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM_UMD) <<
3691                 GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
3692                (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM) <<
3693                 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
3694         WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
3695         WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
3696
3697         /* mmVGT_ESGS_RING_SIZE_UMD -> mmVGT_ESGS_RING_SIZE */
3698         data = (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE_UMD) <<
3699                 GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
3700                (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE) <<
3701                 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
3702         WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
3703         WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
3704
3705         /* mmVGT_GSVS_RING_SIZE_UMD -> mmVGT_GSVS_RING_SIZE */
3706         data = (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE_UMD) <<
3707                 GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
3708                (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE) <<
3709                 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
3710         WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
3711         WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
3712
3713         /* mmSPI_CONFIG_CNTL_REMAP -> mmSPI_CONFIG_CNTL */
3714         data = (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL_REMAP) <<
3715                 GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
3716                (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL) <<
3717                 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
3718         WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
3719         WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
3720 }
3721
3722 static int gfx_v10_0_hw_init(void *handle)
3723 {
3724         int r;
3725         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3726
3727         if (!amdgpu_emu_mode)
3728                 gfx_v10_0_init_golden_registers(adev);
3729
3730         if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
3731                 /**
3732                  * For gfx 10, rlc firmware loading relies on smu firmware is
3733                  * loaded firstly, so in direct type, it has to load smc ucode
3734                  * here before rlc.
3735                  */
3736                 r = smu_load_microcode(&adev->smu);
3737                 if (r)
3738                         return r;
3739
3740                 r = smu_check_fw_status(&adev->smu);
3741                 if (r) {
3742                         pr_err("SMC firmware status is not correct\n");
3743                         return r;
3744                 }
3745         }
3746
3747         /* if GRBM CAM not remapped, set up the remapping */
3748         if (!gfx_v10_0_check_grbm_cam_remapping(adev))
3749                 gfx_v10_0_setup_grbm_cam_remapping(adev);
3750
3751         gfx_v10_0_constants_init(adev);
3752
3753         r = gfx_v10_0_rlc_resume(adev);
3754         if (r)
3755                 return r;
3756
3757         /*
3758          * init golden registers and rlc resume may override some registers,
3759          * reconfig them here
3760          */
3761         gfx_v10_0_tcp_harvest(adev);
3762
3763         r = gfx_v10_0_cp_resume(adev);
3764         if (r)
3765                 return r;
3766
3767         return r;
3768 }
3769
3770 #ifndef BRING_UP_DEBUG
3771 static int gfx_v10_0_kiq_disable_kgq(struct amdgpu_device *adev)
3772 {
3773         struct amdgpu_kiq *kiq = &adev->gfx.kiq;
3774         struct amdgpu_ring *kiq_ring = &kiq->ring;
3775         int i;
3776
3777         if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues)
3778                 return -EINVAL;
3779
3780         if (amdgpu_ring_alloc(kiq_ring, kiq->pmf->unmap_queues_size *
3781                                         adev->gfx.num_gfx_rings))
3782                 return -ENOMEM;
3783
3784         for (i = 0; i < adev->gfx.num_gfx_rings; i++)
3785                 kiq->pmf->kiq_unmap_queues(kiq_ring, &adev->gfx.gfx_ring[i],
3786                                            PREEMPT_QUEUES, 0, 0);
3787
3788         return amdgpu_ring_test_helper(kiq_ring);
3789 }
3790 #endif
3791
3792 static int gfx_v10_0_hw_fini(void *handle)
3793 {
3794         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3795         int r;
3796
3797         amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0);
3798         amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0);
3799 #ifndef BRING_UP_DEBUG
3800         if (amdgpu_async_gfx_ring) {
3801                 r = gfx_v10_0_kiq_disable_kgq(adev);
3802                 if (r)
3803                         DRM_ERROR("KGQ disable failed\n");
3804         }
3805 #endif
3806         if (amdgpu_gfx_disable_kcq(adev))
3807                 DRM_ERROR("KCQ disable failed\n");
3808         if (amdgpu_sriov_vf(adev)) {
3809                 gfx_v10_0_cp_gfx_enable(adev, false);
3810                 return 0;
3811         }
3812         gfx_v10_0_cp_enable(adev, false);
3813         gfx_v10_0_enable_gui_idle_interrupt(adev, false);
3814
3815         return 0;
3816 }
3817
3818 static int gfx_v10_0_suspend(void *handle)
3819 {
3820         return gfx_v10_0_hw_fini(handle);
3821 }
3822
3823 static int gfx_v10_0_resume(void *handle)
3824 {
3825         return gfx_v10_0_hw_init(handle);
3826 }
3827
3828 static bool gfx_v10_0_is_idle(void *handle)
3829 {
3830         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3831
3832         if (REG_GET_FIELD(RREG32_SOC15(GC, 0, mmGRBM_STATUS),
3833                                 GRBM_STATUS, GUI_ACTIVE))
3834                 return false;
3835         else
3836                 return true;
3837 }
3838
3839 static int gfx_v10_0_wait_for_idle(void *handle)
3840 {
3841         unsigned i;
3842         u32 tmp;
3843         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3844
3845         for (i = 0; i < adev->usec_timeout; i++) {
3846                 /* read MC_STATUS */
3847                 tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS) &
3848                         GRBM_STATUS__GUI_ACTIVE_MASK;
3849
3850                 if (!REG_GET_FIELD(tmp, GRBM_STATUS, GUI_ACTIVE))
3851                         return 0;
3852                 udelay(1);
3853         }
3854         return -ETIMEDOUT;
3855 }
3856
3857 static int gfx_v10_0_soft_reset(void *handle)
3858 {
3859         u32 grbm_soft_reset = 0;
3860         u32 tmp;
3861         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3862
3863         /* GRBM_STATUS */
3864         tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS);
3865         if (tmp & (GRBM_STATUS__PA_BUSY_MASK | GRBM_STATUS__SC_BUSY_MASK |
3866                    GRBM_STATUS__BCI_BUSY_MASK | GRBM_STATUS__SX_BUSY_MASK |
3867                    GRBM_STATUS__TA_BUSY_MASK | GRBM_STATUS__DB_BUSY_MASK |
3868                    GRBM_STATUS__CB_BUSY_MASK | GRBM_STATUS__GDS_BUSY_MASK |
3869                    GRBM_STATUS__SPI_BUSY_MASK | GRBM_STATUS__GE_BUSY_NO_DMA_MASK
3870                    | GRBM_STATUS__BCI_BUSY_MASK)) {
3871                 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
3872                                                 GRBM_SOFT_RESET, SOFT_RESET_CP,
3873                                                 1);
3874                 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
3875                                                 GRBM_SOFT_RESET, SOFT_RESET_GFX,
3876                                                 1);
3877         }
3878
3879         if (tmp & (GRBM_STATUS__CP_BUSY_MASK | GRBM_STATUS__CP_COHERENCY_BUSY_MASK)) {
3880                 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
3881                                                 GRBM_SOFT_RESET, SOFT_RESET_CP,
3882                                                 1);
3883         }
3884
3885         /* GRBM_STATUS2 */
3886         tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS2);
3887         if (REG_GET_FIELD(tmp, GRBM_STATUS2, RLC_BUSY))
3888                 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
3889                                                 GRBM_SOFT_RESET, SOFT_RESET_RLC,
3890                                                 1);
3891
3892         if (grbm_soft_reset) {
3893                 /* stop the rlc */
3894                 gfx_v10_0_rlc_stop(adev);
3895
3896                 /* Disable GFX parsing/prefetching */
3897                 gfx_v10_0_cp_gfx_enable(adev, false);
3898
3899                 /* Disable MEC parsing/prefetching */
3900                 gfx_v10_0_cp_compute_enable(adev, false);
3901
3902                 if (grbm_soft_reset) {
3903                         tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);
3904                         tmp |= grbm_soft_reset;
3905                         dev_info(adev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp);
3906                         WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp);
3907                         tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);
3908
3909                         udelay(50);
3910
3911                         tmp &= ~grbm_soft_reset;
3912                         WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp);
3913                         tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);
3914                 }
3915
3916                 /* Wait a little for things to settle down */
3917                 udelay(50);
3918         }
3919         return 0;
3920 }
3921
3922 static uint64_t gfx_v10_0_get_gpu_clock_counter(struct amdgpu_device *adev)
3923 {
3924         uint64_t clock;
3925
3926         amdgpu_gfx_off_ctrl(adev, false);
3927         mutex_lock(&adev->gfx.gpu_clock_mutex);
3928         WREG32_SOC15(GC, 0, mmRLC_CAPTURE_GPU_CLOCK_COUNT, 1);
3929         clock = (uint64_t)RREG32_SOC15(GC, 0, mmRLC_GPU_CLOCK_COUNT_LSB) |
3930                 ((uint64_t)RREG32_SOC15(GC, 0, mmRLC_GPU_CLOCK_COUNT_MSB) << 32ULL);
3931         mutex_unlock(&adev->gfx.gpu_clock_mutex);
3932         amdgpu_gfx_off_ctrl(adev, true);
3933         return clock;
3934 }
3935
3936 static void gfx_v10_0_ring_emit_gds_switch(struct amdgpu_ring *ring,
3937                                            uint32_t vmid,
3938                                            uint32_t gds_base, uint32_t gds_size,
3939                                            uint32_t gws_base, uint32_t gws_size,
3940                                            uint32_t oa_base, uint32_t oa_size)
3941 {
3942         struct amdgpu_device *adev = ring->adev;
3943
3944         /* GDS Base */
3945         gfx_v10_0_write_data_to_reg(ring, 0, false,
3946                                     SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_BASE) + 2 * vmid,
3947                                     gds_base);
3948
3949         /* GDS Size */
3950         gfx_v10_0_write_data_to_reg(ring, 0, false,
3951                                     SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_SIZE) + 2 * vmid,
3952                                     gds_size);
3953
3954         /* GWS */
3955         gfx_v10_0_write_data_to_reg(ring, 0, false,
3956                                     SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID0) + vmid,
3957                                     gws_size << GDS_GWS_VMID0__SIZE__SHIFT | gws_base);
3958
3959         /* OA */
3960         gfx_v10_0_write_data_to_reg(ring, 0, false,
3961                                     SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID0) + vmid,
3962                                     (1 << (oa_size + oa_base)) - (1 << oa_base));
3963 }
3964
3965 static int gfx_v10_0_early_init(void *handle)
3966 {
3967         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3968
3969         adev->gfx.num_gfx_rings = GFX10_NUM_GFX_RINGS;
3970         adev->gfx.num_compute_rings = AMDGPU_MAX_COMPUTE_RINGS;
3971
3972         gfx_v10_0_set_kiq_pm4_funcs(adev);
3973         gfx_v10_0_set_ring_funcs(adev);
3974         gfx_v10_0_set_irq_funcs(adev);
3975         gfx_v10_0_set_gds_init(adev);
3976         gfx_v10_0_set_rlc_funcs(adev);
3977
3978         return 0;
3979 }
3980
3981 static int gfx_v10_0_late_init(void *handle)
3982 {
3983         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3984         int r;
3985
3986         r = amdgpu_irq_get(adev, &adev->gfx.priv_reg_irq, 0);
3987         if (r)
3988                 return r;
3989
3990         r = amdgpu_irq_get(adev, &adev->gfx.priv_inst_irq, 0);
3991         if (r)
3992                 return r;
3993
3994         return 0;
3995 }
3996
3997 static bool gfx_v10_0_is_rlc_enabled(struct amdgpu_device *adev)
3998 {
3999         uint32_t rlc_cntl;
4000
4001         /* if RLC is not enabled, do nothing */
4002         rlc_cntl = RREG32_SOC15(GC, 0, mmRLC_CNTL);
4003         return (REG_GET_FIELD(rlc_cntl, RLC_CNTL, RLC_ENABLE_F32)) ? true : false;
4004 }
4005
4006 static void gfx_v10_0_set_safe_mode(struct amdgpu_device *adev)
4007 {
4008         uint32_t data;
4009         unsigned i;
4010
4011         data = RLC_SAFE_MODE__CMD_MASK;
4012         data |= (1 << RLC_SAFE_MODE__MESSAGE__SHIFT);
4013         WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE, data);
4014
4015         /* wait for RLC_SAFE_MODE */
4016         for (i = 0; i < adev->usec_timeout; i++) {
4017                 if (!REG_GET_FIELD(RREG32_SOC15(GC, 0, mmRLC_SAFE_MODE), RLC_SAFE_MODE, CMD))
4018                         break;
4019                 udelay(1);
4020         }
4021 }
4022
4023 static void gfx_v10_0_unset_safe_mode(struct amdgpu_device *adev)
4024 {
4025         uint32_t data;
4026
4027         data = RLC_SAFE_MODE__CMD_MASK;
4028         WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE, data);
4029 }
4030
4031 static void gfx_v10_0_update_medium_grain_clock_gating(struct amdgpu_device *adev,
4032                                                       bool enable)
4033 {
4034         uint32_t data, def;
4035
4036         /* It is disabled by HW by default */
4037         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) {
4038                 /* 1 - RLC_CGTT_MGCG_OVERRIDE */
4039                 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
4040                 data &= ~(RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK |
4041                           RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK |
4042                           RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK);
4043
4044                 /* only for Vega10 & Raven1 */
4045                 data |= RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK;
4046
4047                 if (def != data)
4048                         WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
4049
4050                 /* MGLS is a global flag to control all MGLS in GFX */
4051                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGLS) {
4052                         /* 2 - RLC memory Light sleep */
4053                         if (adev->cg_flags & AMD_CG_SUPPORT_GFX_RLC_LS) {
4054                                 def = data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL);
4055                                 data |= RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK;
4056                                 if (def != data)
4057                                         WREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL, data);
4058                         }
4059                         /* 3 - CP memory Light sleep */
4060                         if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CP_LS) {
4061                                 def = data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL);
4062                                 data |= CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK;
4063                                 if (def != data)
4064                                         WREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL, data);
4065                         }
4066                 }
4067         } else {
4068                 /* 1 - MGCG_OVERRIDE */
4069                 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
4070                 data |= (RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK |
4071                          RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK |
4072                          RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK |
4073                          RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK);
4074                 if (def != data)
4075                         WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
4076
4077                 /* 2 - disable MGLS in RLC */
4078                 data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL);
4079                 if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK) {
4080                         data &= ~RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK;
4081                         WREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL, data);
4082                 }
4083
4084                 /* 3 - disable MGLS in CP */
4085                 data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL);
4086                 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) {
4087                         data &= ~CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK;
4088                         WREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL, data);
4089                 }
4090         }
4091 }
4092
4093 static void gfx_v10_0_update_3d_clock_gating(struct amdgpu_device *adev,
4094                                            bool enable)
4095 {
4096         uint32_t data, def;
4097
4098         /* Enable 3D CGCG/CGLS */
4099         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG)) {
4100                 /* write cmd to clear cgcg/cgls ov */
4101                 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
4102                 /* unset CGCG override */
4103                 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_GFX3D_CG_OVERRIDE_MASK;
4104                 /* update CGCG and CGLS override bits */
4105                 if (def != data)
4106                         WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
4107                 /* enable 3Dcgcg FSM(0x0000363f) */
4108                 def = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D);
4109                 data = (0x36 << RLC_CGCG_CGLS_CTRL_3D__CGCG_GFX_IDLE_THRESHOLD__SHIFT) |
4110                         RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK;
4111                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS)
4112                         data |= (0x000F << RLC_CGCG_CGLS_CTRL_3D__CGLS_REP_COMPANSAT_DELAY__SHIFT) |
4113                                 RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK;
4114                 if (def != data)
4115                         WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D, data);
4116
4117                 /* set IDLE_POLL_COUNT(0x00900100) */
4118                 def = RREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL);
4119                 data = (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) |
4120                         (0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT);
4121                 if (def != data)
4122                         WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL, data);
4123         } else {
4124                 /* Disable CGCG/CGLS */
4125                 def = data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D);
4126                 /* disable cgcg, cgls should be disabled */
4127                 data &= ~(RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK |
4128                           RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK);
4129                 /* disable cgcg and cgls in FSM */
4130                 if (def != data)
4131                         WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D, data);
4132         }
4133 }
4134
4135 static void gfx_v10_0_update_coarse_grain_clock_gating(struct amdgpu_device *adev,
4136                                                       bool enable)
4137 {
4138         uint32_t def, data;
4139
4140         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)) {
4141                 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
4142                 /* unset CGCG override */
4143                 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGCG_OVERRIDE_MASK;
4144                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS)
4145                         data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK;
4146                 else
4147                         data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK;
4148                 /* update CGCG and CGLS override bits */
4149                 if (def != data)
4150                         WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
4151
4152                 /* enable cgcg FSM(0x0000363F) */
4153                 def = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL);
4154                 data = (0x36 << RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT) |
4155                         RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK;
4156                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS)
4157                         data |= (0x000F << RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY__SHIFT) |
4158                                 RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK;
4159                 if (def != data)
4160                         WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, data);
4161
4162                 /* set IDLE_POLL_COUNT(0x00900100) */
4163                 def = RREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL);
4164                 data = (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) |
4165                         (0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT);
4166                 if (def != data)
4167                         WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL, data);
4168         } else {
4169                 def = data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL);
4170                 /* reset CGCG/CGLS bits */
4171                 data &= ~(RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK | RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK);
4172                 /* disable cgcg and cgls in FSM */
4173                 if (def != data)
4174                         WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, data);
4175         }
4176 }
4177
4178 static int gfx_v10_0_update_gfx_clock_gating(struct amdgpu_device *adev,
4179                                             bool enable)
4180 {
4181         amdgpu_gfx_rlc_enter_safe_mode(adev);
4182
4183         if (enable) {
4184                 /* CGCG/CGLS should be enabled after MGCG/MGLS
4185                  * ===  MGCG + MGLS ===
4186                  */
4187                 gfx_v10_0_update_medium_grain_clock_gating(adev, enable);
4188                 /* ===  CGCG /CGLS for GFX 3D Only === */
4189                 gfx_v10_0_update_3d_clock_gating(adev, enable);
4190                 /* ===  CGCG + CGLS === */
4191                 gfx_v10_0_update_coarse_grain_clock_gating(adev, enable);
4192         } else {
4193                 /* CGCG/CGLS should be disabled before MGCG/MGLS
4194                  * ===  CGCG + CGLS ===
4195                  */
4196                 gfx_v10_0_update_coarse_grain_clock_gating(adev, enable);
4197                 /* ===  CGCG /CGLS for GFX 3D Only === */
4198                 gfx_v10_0_update_3d_clock_gating(adev, enable);
4199                 /* ===  MGCG + MGLS === */
4200                 gfx_v10_0_update_medium_grain_clock_gating(adev, enable);
4201         }
4202
4203         if (adev->cg_flags &
4204             (AMD_CG_SUPPORT_GFX_MGCG |
4205              AMD_CG_SUPPORT_GFX_CGLS |
4206              AMD_CG_SUPPORT_GFX_CGCG |
4207              AMD_CG_SUPPORT_GFX_CGLS |
4208              AMD_CG_SUPPORT_GFX_3D_CGCG |
4209              AMD_CG_SUPPORT_GFX_3D_CGLS))
4210                 gfx_v10_0_enable_gui_idle_interrupt(adev, enable);
4211
4212         amdgpu_gfx_rlc_exit_safe_mode(adev);
4213
4214         return 0;
4215 }
4216
4217 static void gfx_v10_0_update_spm_vmid(struct amdgpu_device *adev, unsigned vmid)
4218 {
4219         u32 data;
4220
4221         data = RREG32_SOC15(GC, 0, mmRLC_SPM_MC_CNTL);
4222
4223         data &= ~RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK;
4224         data |= (vmid & RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK) << RLC_SPM_MC_CNTL__RLC_SPM_VMID__SHIFT;
4225
4226         WREG32_SOC15(GC, 0, mmRLC_SPM_MC_CNTL, data);
4227 }
4228
4229 static const struct amdgpu_rlc_funcs gfx_v10_0_rlc_funcs = {
4230         .is_rlc_enabled = gfx_v10_0_is_rlc_enabled,
4231         .set_safe_mode = gfx_v10_0_set_safe_mode,
4232         .unset_safe_mode = gfx_v10_0_unset_safe_mode,
4233         .init = gfx_v10_0_rlc_init,
4234         .get_csb_size = gfx_v10_0_get_csb_size,
4235         .get_csb_buffer = gfx_v10_0_get_csb_buffer,
4236         .resume = gfx_v10_0_rlc_resume,
4237         .stop = gfx_v10_0_rlc_stop,
4238         .reset = gfx_v10_0_rlc_reset,
4239         .start = gfx_v10_0_rlc_start,
4240         .update_spm_vmid = gfx_v10_0_update_spm_vmid
4241 };
4242
4243 static int gfx_v10_0_set_powergating_state(void *handle,
4244                                           enum amd_powergating_state state)
4245 {
4246         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4247         bool enable = (state == AMD_PG_STATE_GATE);
4248         switch (adev->asic_type) {
4249         case CHIP_NAVI10:
4250         case CHIP_NAVI14:
4251                 if (!enable) {
4252                         amdgpu_gfx_off_ctrl(adev, false);
4253                         cancel_delayed_work_sync(&adev->gfx.gfx_off_delay_work);
4254                 } else
4255                         amdgpu_gfx_off_ctrl(adev, true);
4256                 break;
4257         default:
4258                 break;
4259         }
4260         return 0;
4261 }
4262
4263 static int gfx_v10_0_set_clockgating_state(void *handle,
4264                                           enum amd_clockgating_state state)
4265 {
4266         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4267
4268         switch (adev->asic_type) {
4269         case CHIP_NAVI10:
4270         case CHIP_NAVI14:
4271         case CHIP_NAVI12:
4272                 gfx_v10_0_update_gfx_clock_gating(adev,
4273                                                  state == AMD_CG_STATE_GATE);
4274                 break;
4275         default:
4276                 break;
4277         }
4278         return 0;
4279 }
4280
4281 static void gfx_v10_0_get_clockgating_state(void *handle, u32 *flags)
4282 {
4283         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4284         int data;
4285
4286         /* AMD_CG_SUPPORT_GFX_MGCG */
4287         data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
4288         if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK))
4289                 *flags |= AMD_CG_SUPPORT_GFX_MGCG;
4290
4291         /* AMD_CG_SUPPORT_GFX_CGCG */
4292         data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL);
4293         if (data & RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK)
4294                 *flags |= AMD_CG_SUPPORT_GFX_CGCG;
4295
4296         /* AMD_CG_SUPPORT_GFX_CGLS */
4297         if (data & RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK)
4298                 *flags |= AMD_CG_SUPPORT_GFX_CGLS;
4299
4300         /* AMD_CG_SUPPORT_GFX_RLC_LS */
4301         data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL);
4302         if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK)
4303                 *flags |= AMD_CG_SUPPORT_GFX_RLC_LS | AMD_CG_SUPPORT_GFX_MGLS;
4304
4305         /* AMD_CG_SUPPORT_GFX_CP_LS */
4306         data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL);
4307         if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK)
4308                 *flags |= AMD_CG_SUPPORT_GFX_CP_LS | AMD_CG_SUPPORT_GFX_MGLS;
4309
4310         /* AMD_CG_SUPPORT_GFX_3D_CGCG */
4311         data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D);
4312         if (data & RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK)
4313                 *flags |= AMD_CG_SUPPORT_GFX_3D_CGCG;
4314
4315         /* AMD_CG_SUPPORT_GFX_3D_CGLS */
4316         if (data & RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK)
4317                 *flags |= AMD_CG_SUPPORT_GFX_3D_CGLS;
4318 }
4319
4320 static u64 gfx_v10_0_ring_get_rptr_gfx(struct amdgpu_ring *ring)
4321 {
4322         return ring->adev->wb.wb[ring->rptr_offs]; /* gfx10 is 32bit rptr*/
4323 }
4324
4325 static u64 gfx_v10_0_ring_get_wptr_gfx(struct amdgpu_ring *ring)
4326 {
4327         struct amdgpu_device *adev = ring->adev;
4328         u64 wptr;
4329
4330         /* XXX check if swapping is necessary on BE */
4331         if (ring->use_doorbell) {
4332                 wptr = atomic64_read((atomic64_t *)&adev->wb.wb[ring->wptr_offs]);
4333         } else {
4334                 wptr = RREG32_SOC15(GC, 0, mmCP_RB0_WPTR);
4335                 wptr += (u64)RREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI) << 32;
4336         }
4337
4338         return wptr;
4339 }
4340
4341 static void gfx_v10_0_ring_set_wptr_gfx(struct amdgpu_ring *ring)
4342 {
4343         struct amdgpu_device *adev = ring->adev;
4344
4345         if (ring->use_doorbell) {
4346                 /* XXX check if swapping is necessary on BE */
4347                 atomic64_set((atomic64_t *)&adev->wb.wb[ring->wptr_offs], ring->wptr);
4348                 WDOORBELL64(ring->doorbell_index, ring->wptr);
4349         } else {
4350                 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR, lower_32_bits(ring->wptr));
4351                 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI, upper_32_bits(ring->wptr));
4352         }
4353 }
4354
4355 static u64 gfx_v10_0_ring_get_rptr_compute(struct amdgpu_ring *ring)
4356 {
4357         return ring->adev->wb.wb[ring->rptr_offs]; /* gfx10 hardware is 32bit rptr */
4358 }
4359
4360 static u64 gfx_v10_0_ring_get_wptr_compute(struct amdgpu_ring *ring)
4361 {
4362         u64 wptr;
4363
4364         /* XXX check if swapping is necessary on BE */
4365         if (ring->use_doorbell)
4366                 wptr = atomic64_read((atomic64_t *)&ring->adev->wb.wb[ring->wptr_offs]);
4367         else
4368                 BUG();
4369         return wptr;
4370 }
4371
4372 static void gfx_v10_0_ring_set_wptr_compute(struct amdgpu_ring *ring)
4373 {
4374         struct amdgpu_device *adev = ring->adev;
4375
4376         /* XXX check if swapping is necessary on BE */
4377         if (ring->use_doorbell) {
4378                 atomic64_set((atomic64_t *)&adev->wb.wb[ring->wptr_offs], ring->wptr);
4379                 WDOORBELL64(ring->doorbell_index, ring->wptr);
4380         } else {
4381                 BUG(); /* only DOORBELL method supported on gfx10 now */
4382         }
4383 }
4384
4385 static void gfx_v10_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
4386 {
4387         struct amdgpu_device *adev = ring->adev;
4388         u32 ref_and_mask, reg_mem_engine;
4389         const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio.hdp_flush_reg;
4390
4391         if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) {
4392                 switch (ring->me) {
4393                 case 1:
4394                         ref_and_mask = nbio_hf_reg->ref_and_mask_cp2 << ring->pipe;
4395                         break;
4396                 case 2:
4397                         ref_and_mask = nbio_hf_reg->ref_and_mask_cp6 << ring->pipe;
4398                         break;
4399                 default:
4400                         return;
4401                 }
4402                 reg_mem_engine = 0;
4403         } else {
4404                 ref_and_mask = nbio_hf_reg->ref_and_mask_cp0;
4405                 reg_mem_engine = 1; /* pfp */
4406         }
4407
4408         gfx_v10_0_wait_reg_mem(ring, reg_mem_engine, 0, 1,
4409                                adev->nbio.funcs->get_hdp_flush_req_offset(adev),
4410                                adev->nbio.funcs->get_hdp_flush_done_offset(adev),
4411                                ref_and_mask, ref_and_mask, 0x20);
4412 }
4413
4414 static void gfx_v10_0_ring_emit_ib_gfx(struct amdgpu_ring *ring,
4415                                        struct amdgpu_job *job,
4416                                        struct amdgpu_ib *ib,
4417                                        uint32_t flags)
4418 {
4419         unsigned vmid = AMDGPU_JOB_GET_VMID(job);
4420         u32 header, control = 0;
4421
4422         if (ib->flags & AMDGPU_IB_FLAG_CE)
4423                 header = PACKET3(PACKET3_INDIRECT_BUFFER_CNST, 2);
4424         else
4425                 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2);
4426
4427         control |= ib->length_dw | (vmid << 24);
4428
4429         if ((amdgpu_sriov_vf(ring->adev) || amdgpu_mcbp) && (ib->flags & AMDGPU_IB_FLAG_PREEMPT)) {
4430                 control |= INDIRECT_BUFFER_PRE_ENB(1);
4431
4432                 if (flags & AMDGPU_IB_PREEMPTED)
4433                         control |= INDIRECT_BUFFER_PRE_RESUME(1);
4434
4435                 if (!(ib->flags & AMDGPU_IB_FLAG_CE))
4436                         gfx_v10_0_ring_emit_de_meta(ring,
4437                                     (!amdgpu_sriov_vf(ring->adev) && flags & AMDGPU_IB_PREEMPTED) ? true : false);
4438         }
4439
4440         amdgpu_ring_write(ring, header);
4441         BUG_ON(ib->gpu_addr & 0x3); /* Dword align */
4442         amdgpu_ring_write(ring,
4443 #ifdef __BIG_ENDIAN
4444                 (2 << 0) |
4445 #endif
4446                 lower_32_bits(ib->gpu_addr));
4447         amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
4448         amdgpu_ring_write(ring, control);
4449 }
4450
4451 static void gfx_v10_0_ring_emit_ib_compute(struct amdgpu_ring *ring,
4452                                            struct amdgpu_job *job,
4453                                            struct amdgpu_ib *ib,
4454                                            uint32_t flags)
4455 {
4456         unsigned vmid = AMDGPU_JOB_GET_VMID(job);
4457         u32 control = INDIRECT_BUFFER_VALID | ib->length_dw | (vmid << 24);
4458
4459         /* Currently, there is a high possibility to get wave ID mismatch
4460          * between ME and GDS, leading to a hw deadlock, because ME generates
4461          * different wave IDs than the GDS expects. This situation happens
4462          * randomly when at least 5 compute pipes use GDS ordered append.
4463          * The wave IDs generated by ME are also wrong after suspend/resume.
4464          * Those are probably bugs somewhere else in the kernel driver.
4465          *
4466          * Writing GDS_COMPUTE_MAX_WAVE_ID resets wave ID counters in ME and
4467          * GDS to 0 for this ring (me/pipe).
4468          */
4469         if (ib->flags & AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID) {
4470                 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
4471                 amdgpu_ring_write(ring, mmGDS_COMPUTE_MAX_WAVE_ID);
4472                 amdgpu_ring_write(ring, ring->adev->gds.gds_compute_max_wave_id);
4473         }
4474
4475         amdgpu_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
4476         BUG_ON(ib->gpu_addr & 0x3); /* Dword align */
4477         amdgpu_ring_write(ring,
4478 #ifdef __BIG_ENDIAN
4479                                 (2 << 0) |
4480 #endif
4481                                 lower_32_bits(ib->gpu_addr));
4482         amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
4483         amdgpu_ring_write(ring, control);
4484 }
4485
4486 static void gfx_v10_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr,
4487                                      u64 seq, unsigned flags)
4488 {
4489         struct amdgpu_device *adev = ring->adev;
4490         bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
4491         bool int_sel = flags & AMDGPU_FENCE_FLAG_INT;
4492
4493         /* Interrupt not work fine on GFX10.1 model yet. Use fallback instead */
4494         if (adev->pdev->device == 0x50)
4495                 int_sel = false;
4496
4497         /* RELEASE_MEM - flush caches, send int */
4498         amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 6));
4499         amdgpu_ring_write(ring, (PACKET3_RELEASE_MEM_GCR_SEQ |
4500                                  PACKET3_RELEASE_MEM_GCR_GL2_WB |
4501                                  PACKET3_RELEASE_MEM_GCR_GLM_INV | /* must be set with GLM_WB */
4502                                  PACKET3_RELEASE_MEM_GCR_GLM_WB |
4503                                  PACKET3_RELEASE_MEM_CACHE_POLICY(3) |
4504                                  PACKET3_RELEASE_MEM_EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) |
4505                                  PACKET3_RELEASE_MEM_EVENT_INDEX(5)));
4506         amdgpu_ring_write(ring, (PACKET3_RELEASE_MEM_DATA_SEL(write64bit ? 2 : 1) |
4507                                  PACKET3_RELEASE_MEM_INT_SEL(int_sel ? 2 : 0)));
4508
4509         /*
4510          * the address should be Qword aligned if 64bit write, Dword
4511          * aligned if only send 32bit data low (discard data high)
4512          */
4513         if (write64bit)
4514                 BUG_ON(addr & 0x7);
4515         else
4516                 BUG_ON(addr & 0x3);
4517         amdgpu_ring_write(ring, lower_32_bits(addr));
4518         amdgpu_ring_write(ring, upper_32_bits(addr));
4519         amdgpu_ring_write(ring, lower_32_bits(seq));
4520         amdgpu_ring_write(ring, upper_32_bits(seq));
4521         amdgpu_ring_write(ring, 0);
4522 }
4523
4524 static void gfx_v10_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
4525 {
4526         int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
4527         uint32_t seq = ring->fence_drv.sync_seq;
4528         uint64_t addr = ring->fence_drv.gpu_addr;
4529
4530         gfx_v10_0_wait_reg_mem(ring, usepfp, 1, 0, lower_32_bits(addr),
4531                                upper_32_bits(addr), seq, 0xffffffff, 4);
4532 }
4533
4534 static void gfx_v10_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
4535                                          unsigned vmid, uint64_t pd_addr)
4536 {
4537         amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
4538
4539         /* compute doesn't have PFP */
4540         if (ring->funcs->type == AMDGPU_RING_TYPE_GFX) {
4541                 /* sync PFP to ME, otherwise we might get invalid PFP reads */
4542                 amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0));
4543                 amdgpu_ring_write(ring, 0x0);
4544         }
4545 }
4546
4547 static void gfx_v10_0_ring_emit_fence_kiq(struct amdgpu_ring *ring, u64 addr,
4548                                           u64 seq, unsigned int flags)
4549 {
4550         struct amdgpu_device *adev = ring->adev;
4551
4552         /* we only allocate 32bit for each seq wb address */
4553         BUG_ON(flags & AMDGPU_FENCE_FLAG_64BIT);
4554
4555         /* write fence seq to the "addr" */
4556         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
4557         amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
4558                                  WRITE_DATA_DST_SEL(5) | WR_CONFIRM));
4559         amdgpu_ring_write(ring, lower_32_bits(addr));
4560         amdgpu_ring_write(ring, upper_32_bits(addr));
4561         amdgpu_ring_write(ring, lower_32_bits(seq));
4562
4563         if (flags & AMDGPU_FENCE_FLAG_INT) {
4564                 /* set register to trigger INT */
4565                 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
4566                 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
4567                                          WRITE_DATA_DST_SEL(0) | WR_CONFIRM));
4568                 amdgpu_ring_write(ring, SOC15_REG_OFFSET(GC, 0, mmCPC_INT_STATUS));
4569                 amdgpu_ring_write(ring, 0);
4570                 amdgpu_ring_write(ring, 0x20000000); /* src_id is 178 */
4571         }
4572 }
4573
4574 static void gfx_v10_0_ring_emit_sb(struct amdgpu_ring *ring)
4575 {
4576         amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
4577         amdgpu_ring_write(ring, 0);
4578 }
4579
4580 static void gfx_v10_0_ring_emit_cntxcntl(struct amdgpu_ring *ring, uint32_t flags)
4581 {
4582         uint32_t dw2 = 0;
4583
4584         if (amdgpu_mcbp || amdgpu_sriov_vf(ring->adev))
4585                 gfx_v10_0_ring_emit_ce_meta(ring,
4586                                     (!amdgpu_sriov_vf(ring->adev) && flags & AMDGPU_IB_PREEMPTED) ? true : false);
4587
4588         gfx_v10_0_ring_emit_tmz(ring, true);
4589
4590         dw2 |= 0x80000000; /* set load_enable otherwise this package is just NOPs */
4591         if (flags & AMDGPU_HAVE_CTX_SWITCH) {
4592                 /* set load_global_config & load_global_uconfig */
4593                 dw2 |= 0x8001;
4594                 /* set load_cs_sh_regs */
4595                 dw2 |= 0x01000000;
4596                 /* set load_per_context_state & load_gfx_sh_regs for GFX */
4597                 dw2 |= 0x10002;
4598
4599                 /* set load_ce_ram if preamble presented */
4600                 if (AMDGPU_PREAMBLE_IB_PRESENT & flags)
4601                         dw2 |= 0x10000000;
4602         } else {
4603                 /* still load_ce_ram if this is the first time preamble presented
4604                  * although there is no context switch happens.
4605                  */
4606                 if (AMDGPU_PREAMBLE_IB_PRESENT_FIRST & flags)
4607                         dw2 |= 0x10000000;
4608         }
4609
4610         amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1));
4611         amdgpu_ring_write(ring, dw2);
4612         amdgpu_ring_write(ring, 0);
4613 }
4614
4615 static unsigned gfx_v10_0_ring_emit_init_cond_exec(struct amdgpu_ring *ring)
4616 {
4617         unsigned ret;
4618
4619         amdgpu_ring_write(ring, PACKET3(PACKET3_COND_EXEC, 3));
4620         amdgpu_ring_write(ring, lower_32_bits(ring->cond_exe_gpu_addr));
4621         amdgpu_ring_write(ring, upper_32_bits(ring->cond_exe_gpu_addr));
4622         amdgpu_ring_write(ring, 0); /* discard following DWs if *cond_exec_gpu_addr==0 */
4623         ret = ring->wptr & ring->buf_mask;
4624         amdgpu_ring_write(ring, 0x55aa55aa); /* patch dummy value later */
4625
4626         return ret;
4627 }
4628
4629 static void gfx_v10_0_ring_emit_patch_cond_exec(struct amdgpu_ring *ring, unsigned offset)
4630 {
4631         unsigned cur;
4632         BUG_ON(offset > ring->buf_mask);
4633         BUG_ON(ring->ring[offset] != 0x55aa55aa);
4634
4635         cur = (ring->wptr - 1) & ring->buf_mask;
4636         if (likely(cur > offset))
4637                 ring->ring[offset] = cur - offset;
4638         else
4639                 ring->ring[offset] = (ring->buf_mask + 1) - offset + cur;
4640 }
4641
4642 static int gfx_v10_0_ring_preempt_ib(struct amdgpu_ring *ring)
4643 {
4644         int i, r = 0;
4645         struct amdgpu_device *adev = ring->adev;
4646         struct amdgpu_kiq *kiq = &adev->gfx.kiq;
4647         struct amdgpu_ring *kiq_ring = &kiq->ring;
4648
4649         if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues)
4650                 return -EINVAL;
4651
4652         if (amdgpu_ring_alloc(kiq_ring, kiq->pmf->unmap_queues_size))
4653                 return -ENOMEM;
4654
4655         /* assert preemption condition */
4656         amdgpu_ring_set_preempt_cond_exec(ring, false);
4657
4658         /* assert IB preemption, emit the trailing fence */
4659         kiq->pmf->kiq_unmap_queues(kiq_ring, ring, PREEMPT_QUEUES_NO_UNMAP,
4660                                    ring->trail_fence_gpu_addr,
4661                                    ++ring->trail_seq);
4662         amdgpu_ring_commit(kiq_ring);
4663
4664         /* poll the trailing fence */
4665         for (i = 0; i < adev->usec_timeout; i++) {
4666                 if (ring->trail_seq ==
4667                     le32_to_cpu(*(ring->trail_fence_cpu_addr)))
4668                         break;
4669                 udelay(1);
4670         }
4671
4672         if (i >= adev->usec_timeout) {
4673                 r = -EINVAL;
4674                 DRM_ERROR("ring %d failed to preempt ib\n", ring->idx);
4675         }
4676
4677         /* deassert preemption condition */
4678         amdgpu_ring_set_preempt_cond_exec(ring, true);
4679         return r;
4680 }
4681
4682 static void gfx_v10_0_ring_emit_ce_meta(struct amdgpu_ring *ring, bool resume)
4683 {
4684         struct amdgpu_device *adev = ring->adev;
4685         struct v10_ce_ib_state ce_payload = {0};
4686         uint64_t csa_addr;
4687         int cnt;
4688
4689         cnt = (sizeof(ce_payload) >> 2) + 4 - 2;
4690         csa_addr = amdgpu_csa_vaddr(ring->adev);
4691
4692         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt));
4693         amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(2) |
4694                                  WRITE_DATA_DST_SEL(8) |
4695                                  WR_CONFIRM) |
4696                                  WRITE_DATA_CACHE_POLICY(0));
4697         amdgpu_ring_write(ring, lower_32_bits(csa_addr +
4698                               offsetof(struct v10_gfx_meta_data, ce_payload)));
4699         amdgpu_ring_write(ring, upper_32_bits(csa_addr +
4700                               offsetof(struct v10_gfx_meta_data, ce_payload)));
4701
4702         if (resume)
4703                 amdgpu_ring_write_multiple(ring, adev->virt.csa_cpu_addr +
4704                                            offsetof(struct v10_gfx_meta_data,
4705                                                     ce_payload),
4706                                            sizeof(ce_payload) >> 2);
4707         else
4708                 amdgpu_ring_write_multiple(ring, (void *)&ce_payload,
4709                                            sizeof(ce_payload) >> 2);
4710 }
4711
4712 static void gfx_v10_0_ring_emit_de_meta(struct amdgpu_ring *ring, bool resume)
4713 {
4714         struct amdgpu_device *adev = ring->adev;
4715         struct v10_de_ib_state de_payload = {0};
4716         uint64_t csa_addr, gds_addr;
4717         int cnt;
4718
4719         csa_addr = amdgpu_csa_vaddr(ring->adev);
4720         gds_addr = ALIGN(csa_addr + AMDGPU_CSA_SIZE - adev->gds.gds_size,
4721                          PAGE_SIZE);
4722         de_payload.gds_backup_addrlo = lower_32_bits(gds_addr);
4723         de_payload.gds_backup_addrhi = upper_32_bits(gds_addr);
4724
4725         cnt = (sizeof(de_payload) >> 2) + 4 - 2;
4726         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt));
4727         amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(1) |
4728                                  WRITE_DATA_DST_SEL(8) |
4729                                  WR_CONFIRM) |
4730                                  WRITE_DATA_CACHE_POLICY(0));
4731         amdgpu_ring_write(ring, lower_32_bits(csa_addr +
4732                               offsetof(struct v10_gfx_meta_data, de_payload)));
4733         amdgpu_ring_write(ring, upper_32_bits(csa_addr +
4734                               offsetof(struct v10_gfx_meta_data, de_payload)));
4735
4736         if (resume)
4737                 amdgpu_ring_write_multiple(ring, adev->virt.csa_cpu_addr +
4738                                            offsetof(struct v10_gfx_meta_data,
4739                                                     de_payload),
4740                                            sizeof(de_payload) >> 2);
4741         else
4742                 amdgpu_ring_write_multiple(ring, (void *)&de_payload,
4743                                            sizeof(de_payload) >> 2);
4744 }
4745
4746 static void gfx_v10_0_ring_emit_tmz(struct amdgpu_ring *ring, bool start)
4747 {
4748         amdgpu_ring_write(ring, PACKET3(PACKET3_FRAME_CONTROL, 0));
4749         amdgpu_ring_write(ring, FRAME_CMD(start ? 0 : 1)); /* frame_end */
4750 }
4751
4752 static void gfx_v10_0_ring_emit_rreg(struct amdgpu_ring *ring, uint32_t reg)
4753 {
4754         struct amdgpu_device *adev = ring->adev;
4755         struct amdgpu_kiq *kiq = &adev->gfx.kiq;
4756
4757         amdgpu_ring_write(ring, PACKET3(PACKET3_COPY_DATA, 4));
4758         amdgpu_ring_write(ring, 0 |     /* src: register*/
4759                                 (5 << 8) |      /* dst: memory */
4760                                 (1 << 20));     /* write confirm */
4761         amdgpu_ring_write(ring, reg);
4762         amdgpu_ring_write(ring, 0);
4763         amdgpu_ring_write(ring, lower_32_bits(adev->wb.gpu_addr +
4764                                 kiq->reg_val_offs * 4));
4765         amdgpu_ring_write(ring, upper_32_bits(adev->wb.gpu_addr +
4766                                 kiq->reg_val_offs * 4));
4767 }
4768
4769 static void gfx_v10_0_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg,
4770                                    uint32_t val)
4771 {
4772         uint32_t cmd = 0;
4773
4774         switch (ring->funcs->type) {
4775         case AMDGPU_RING_TYPE_GFX:
4776                 cmd = WRITE_DATA_ENGINE_SEL(1) | WR_CONFIRM;
4777                 break;
4778         case AMDGPU_RING_TYPE_KIQ:
4779                 cmd = (1 << 16); /* no inc addr */
4780                 break;
4781         default:
4782                 cmd = WR_CONFIRM;
4783                 break;
4784         }
4785         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
4786         amdgpu_ring_write(ring, cmd);
4787         amdgpu_ring_write(ring, reg);
4788         amdgpu_ring_write(ring, 0);
4789         amdgpu_ring_write(ring, val);
4790 }
4791
4792 static void gfx_v10_0_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,
4793                                         uint32_t val, uint32_t mask)
4794 {
4795         gfx_v10_0_wait_reg_mem(ring, 0, 0, 0, reg, 0, val, mask, 0x20);
4796 }
4797
4798 static void gfx_v10_0_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring,
4799                                                    uint32_t reg0, uint32_t reg1,
4800                                                    uint32_t ref, uint32_t mask)
4801 {
4802         int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
4803         struct amdgpu_device *adev = ring->adev;
4804         bool fw_version_ok = false;
4805
4806         fw_version_ok = adev->gfx.cp_fw_write_wait;
4807
4808         if (fw_version_ok)
4809                 gfx_v10_0_wait_reg_mem(ring, usepfp, 0, 1, reg0, reg1,
4810                                        ref, mask, 0x20);
4811         else
4812                 amdgpu_ring_emit_reg_write_reg_wait_helper(ring, reg0, reg1,
4813                                                            ref, mask);
4814 }
4815
4816 static void
4817 gfx_v10_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev,
4818                                       uint32_t me, uint32_t pipe,
4819                                       enum amdgpu_interrupt_state state)
4820 {
4821         uint32_t cp_int_cntl, cp_int_cntl_reg;
4822
4823         if (!me) {
4824                 switch (pipe) {
4825                 case 0:
4826                         cp_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_INT_CNTL_RING0);
4827                         break;
4828                 case 1:
4829                         cp_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_INT_CNTL_RING1);
4830                         break;
4831                 default:
4832                         DRM_DEBUG("invalid pipe %d\n", pipe);
4833                         return;
4834                 }
4835         } else {
4836                 DRM_DEBUG("invalid me %d\n", me);
4837                 return;
4838         }
4839
4840         switch (state) {
4841         case AMDGPU_IRQ_STATE_DISABLE:
4842                 cp_int_cntl = RREG32(cp_int_cntl_reg);
4843                 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
4844                                             TIME_STAMP_INT_ENABLE, 0);
4845                 WREG32(cp_int_cntl_reg, cp_int_cntl);
4846                 break;
4847         case AMDGPU_IRQ_STATE_ENABLE:
4848                 cp_int_cntl = RREG32(cp_int_cntl_reg);
4849                 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
4850                                             TIME_STAMP_INT_ENABLE, 1);
4851                 WREG32(cp_int_cntl_reg, cp_int_cntl);
4852                 break;
4853         default:
4854                 break;
4855         }
4856 }
4857
4858 static void gfx_v10_0_set_compute_eop_interrupt_state(struct amdgpu_device *adev,
4859                                                      int me, int pipe,
4860                                                      enum amdgpu_interrupt_state state)
4861 {
4862         u32 mec_int_cntl, mec_int_cntl_reg;
4863
4864         /*
4865          * amdgpu controls only the first MEC. That's why this function only
4866          * handles the setting of interrupts for this specific MEC. All other
4867          * pipes' interrupts are set by amdkfd.
4868          */
4869
4870         if (me == 1) {
4871                 switch (pipe) {
4872                 case 0:
4873                         mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE0_INT_CNTL);
4874                         break;
4875                 case 1:
4876                         mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE1_INT_CNTL);
4877                         break;
4878                 case 2:
4879                         mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE2_INT_CNTL);
4880                         break;
4881                 case 3:
4882                         mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE3_INT_CNTL);
4883                         break;
4884                 default:
4885                         DRM_DEBUG("invalid pipe %d\n", pipe);
4886                         return;
4887                 }
4888         } else {
4889                 DRM_DEBUG("invalid me %d\n", me);
4890                 return;
4891         }
4892
4893         switch (state) {
4894         case AMDGPU_IRQ_STATE_DISABLE:
4895                 mec_int_cntl = RREG32(mec_int_cntl_reg);
4896                 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,
4897                                              TIME_STAMP_INT_ENABLE, 0);
4898                 WREG32(mec_int_cntl_reg, mec_int_cntl);
4899                 break;
4900         case AMDGPU_IRQ_STATE_ENABLE:
4901                 mec_int_cntl = RREG32(mec_int_cntl_reg);
4902                 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,
4903                                              TIME_STAMP_INT_ENABLE, 1);
4904                 WREG32(mec_int_cntl_reg, mec_int_cntl);
4905                 break;
4906         default:
4907                 break;
4908         }
4909 }
4910
4911 static int gfx_v10_0_set_eop_interrupt_state(struct amdgpu_device *adev,
4912                                             struct amdgpu_irq_src *src,
4913                                             unsigned type,
4914                                             enum amdgpu_interrupt_state state)
4915 {
4916         switch (type) {
4917         case AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP:
4918                 gfx_v10_0_set_gfx_eop_interrupt_state(adev, 0, 0, state);
4919                 break;
4920         case AMDGPU_CP_IRQ_GFX_ME0_PIPE1_EOP:
4921                 gfx_v10_0_set_gfx_eop_interrupt_state(adev, 0, 1, state);
4922                 break;
4923         case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP:
4924                 gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 0, state);
4925                 break;
4926         case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP:
4927                 gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 1, state);
4928                 break;
4929         case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP:
4930                 gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 2, state);
4931                 break;
4932         case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP:
4933                 gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 3, state);
4934                 break;
4935         case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP:
4936                 gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 0, state);
4937                 break;
4938         case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP:
4939                 gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 1, state);
4940                 break;
4941         case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP:
4942                 gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 2, state);
4943                 break;
4944         case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP:
4945                 gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 3, state);
4946                 break;
4947         default:
4948                 break;
4949         }
4950         return 0;
4951 }
4952
4953 static int gfx_v10_0_eop_irq(struct amdgpu_device *adev,
4954                              struct amdgpu_irq_src *source,
4955                              struct amdgpu_iv_entry *entry)
4956 {
4957         int i;
4958         u8 me_id, pipe_id, queue_id;
4959         struct amdgpu_ring *ring;
4960
4961         DRM_DEBUG("IH: CP EOP\n");
4962         me_id = (entry->ring_id & 0x0c) >> 2;
4963         pipe_id = (entry->ring_id & 0x03) >> 0;
4964         queue_id = (entry->ring_id & 0x70) >> 4;
4965
4966         switch (me_id) {
4967         case 0:
4968                 if (pipe_id == 0)
4969                         amdgpu_fence_process(&adev->gfx.gfx_ring[0]);
4970                 else
4971                         amdgpu_fence_process(&adev->gfx.gfx_ring[1]);
4972                 break;
4973         case 1:
4974         case 2:
4975                 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
4976                         ring = &adev->gfx.compute_ring[i];
4977                         /* Per-queue interrupt is supported for MEC starting from VI.
4978                           * The interrupt can only be enabled/disabled per pipe instead of per queue.
4979                           */
4980                         if ((ring->me == me_id) && (ring->pipe == pipe_id) && (ring->queue == queue_id))
4981                                 amdgpu_fence_process(ring);
4982                 }
4983                 break;
4984         }
4985         return 0;
4986 }
4987
4988 static int gfx_v10_0_set_priv_reg_fault_state(struct amdgpu_device *adev,
4989                                               struct amdgpu_irq_src *source,
4990                                               unsigned type,
4991                                               enum amdgpu_interrupt_state state)
4992 {
4993         switch (state) {
4994         case AMDGPU_IRQ_STATE_DISABLE:
4995         case AMDGPU_IRQ_STATE_ENABLE:
4996                 WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0,
4997                                PRIV_REG_INT_ENABLE,
4998                                state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
4999                 break;
5000         default:
5001                 break;
5002         }
5003
5004         return 0;
5005 }
5006
5007 static int gfx_v10_0_set_priv_inst_fault_state(struct amdgpu_device *adev,
5008                                                struct amdgpu_irq_src *source,
5009                                                unsigned type,
5010                                                enum amdgpu_interrupt_state state)
5011 {
5012         switch (state) {
5013         case AMDGPU_IRQ_STATE_DISABLE:
5014         case AMDGPU_IRQ_STATE_ENABLE:
5015                 WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0,
5016                                PRIV_INSTR_INT_ENABLE,
5017                                state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
5018         default:
5019                 break;
5020         }
5021
5022         return 0;
5023 }
5024
5025 static void gfx_v10_0_handle_priv_fault(struct amdgpu_device *adev,
5026                                         struct amdgpu_iv_entry *entry)
5027 {
5028         u8 me_id, pipe_id, queue_id;
5029         struct amdgpu_ring *ring;
5030         int i;
5031
5032         me_id = (entry->ring_id & 0x0c) >> 2;
5033         pipe_id = (entry->ring_id & 0x03) >> 0;
5034         queue_id = (entry->ring_id & 0x70) >> 4;
5035
5036         switch (me_id) {
5037         case 0:
5038                 for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
5039                         ring = &adev->gfx.gfx_ring[i];
5040                         /* we only enabled 1 gfx queue per pipe for now */
5041                         if (ring->me == me_id && ring->pipe == pipe_id)
5042                                 drm_sched_fault(&ring->sched);
5043                 }
5044                 break;
5045         case 1:
5046         case 2:
5047                 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
5048                         ring = &adev->gfx.compute_ring[i];
5049                         if (ring->me == me_id && ring->pipe == pipe_id &&
5050                             ring->queue == queue_id)
5051                                 drm_sched_fault(&ring->sched);
5052                 }
5053                 break;
5054         default:
5055                 BUG();
5056         }
5057 }
5058
5059 static int gfx_v10_0_priv_reg_irq(struct amdgpu_device *adev,
5060                                   struct amdgpu_irq_src *source,
5061                                   struct amdgpu_iv_entry *entry)
5062 {
5063         DRM_ERROR("Illegal register access in command stream\n");
5064         gfx_v10_0_handle_priv_fault(adev, entry);
5065         return 0;
5066 }
5067
5068 static int gfx_v10_0_priv_inst_irq(struct amdgpu_device *adev,
5069                                    struct amdgpu_irq_src *source,
5070                                    struct amdgpu_iv_entry *entry)
5071 {
5072         DRM_ERROR("Illegal instruction in command stream\n");
5073         gfx_v10_0_handle_priv_fault(adev, entry);
5074         return 0;
5075 }
5076
5077 static int gfx_v10_0_kiq_set_interrupt_state(struct amdgpu_device *adev,
5078                                              struct amdgpu_irq_src *src,
5079                                              unsigned int type,
5080                                              enum amdgpu_interrupt_state state)
5081 {
5082         uint32_t tmp, target;
5083         struct amdgpu_ring *ring = &(adev->gfx.kiq.ring);
5084
5085         if (ring->me == 1)
5086                 target = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE0_INT_CNTL);
5087         else
5088                 target = SOC15_REG_OFFSET(GC, 0, mmCP_ME2_PIPE0_INT_CNTL);
5089         target += ring->pipe;
5090
5091         switch (type) {
5092         case AMDGPU_CP_KIQ_IRQ_DRIVER0:
5093                 if (state == AMDGPU_IRQ_STATE_DISABLE) {
5094                         tmp = RREG32_SOC15(GC, 0, mmCPC_INT_CNTL);
5095                         tmp = REG_SET_FIELD(tmp, CPC_INT_CNTL,
5096                                             GENERIC2_INT_ENABLE, 0);
5097                         WREG32_SOC15(GC, 0, mmCPC_INT_CNTL, tmp);
5098
5099                         tmp = RREG32(target);
5100                         tmp = REG_SET_FIELD(tmp, CP_ME2_PIPE0_INT_CNTL,
5101                                             GENERIC2_INT_ENABLE, 0);
5102                         WREG32(target, tmp);
5103                 } else {
5104                         tmp = RREG32_SOC15(GC, 0, mmCPC_INT_CNTL);
5105                         tmp = REG_SET_FIELD(tmp, CPC_INT_CNTL,
5106                                             GENERIC2_INT_ENABLE, 1);
5107                         WREG32_SOC15(GC, 0, mmCPC_INT_CNTL, tmp);
5108
5109                         tmp = RREG32(target);
5110                         tmp = REG_SET_FIELD(tmp, CP_ME2_PIPE0_INT_CNTL,
5111                                             GENERIC2_INT_ENABLE, 1);
5112                         WREG32(target, tmp);
5113                 }
5114                 break;
5115         default:
5116                 BUG(); /* kiq only support GENERIC2_INT now */
5117                 break;
5118         }
5119         return 0;
5120 }
5121
5122 static int gfx_v10_0_kiq_irq(struct amdgpu_device *adev,
5123                              struct amdgpu_irq_src *source,
5124                              struct amdgpu_iv_entry *entry)
5125 {
5126         u8 me_id, pipe_id, queue_id;
5127         struct amdgpu_ring *ring = &(adev->gfx.kiq.ring);
5128
5129         me_id = (entry->ring_id & 0x0c) >> 2;
5130         pipe_id = (entry->ring_id & 0x03) >> 0;
5131         queue_id = (entry->ring_id & 0x70) >> 4;
5132         DRM_DEBUG("IH: CPC GENERIC2_INT, me:%d, pipe:%d, queue:%d\n",
5133                    me_id, pipe_id, queue_id);
5134
5135         amdgpu_fence_process(ring);
5136         return 0;
5137 }
5138
5139 static const struct amd_ip_funcs gfx_v10_0_ip_funcs = {
5140         .name = "gfx_v10_0",
5141         .early_init = gfx_v10_0_early_init,
5142         .late_init = gfx_v10_0_late_init,
5143         .sw_init = gfx_v10_0_sw_init,
5144         .sw_fini = gfx_v10_0_sw_fini,
5145         .hw_init = gfx_v10_0_hw_init,
5146         .hw_fini = gfx_v10_0_hw_fini,
5147         .suspend = gfx_v10_0_suspend,
5148         .resume = gfx_v10_0_resume,
5149         .is_idle = gfx_v10_0_is_idle,
5150         .wait_for_idle = gfx_v10_0_wait_for_idle,
5151         .soft_reset = gfx_v10_0_soft_reset,
5152         .set_clockgating_state = gfx_v10_0_set_clockgating_state,
5153         .set_powergating_state = gfx_v10_0_set_powergating_state,
5154         .get_clockgating_state = gfx_v10_0_get_clockgating_state,
5155 };
5156
5157 static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_gfx = {
5158         .type = AMDGPU_RING_TYPE_GFX,
5159         .align_mask = 0xff,
5160         .nop = PACKET3(PACKET3_NOP, 0x3FFF),
5161         .support_64bit_ptrs = true,
5162         .vmhub = AMDGPU_GFXHUB_0,
5163         .get_rptr = gfx_v10_0_ring_get_rptr_gfx,
5164         .get_wptr = gfx_v10_0_ring_get_wptr_gfx,
5165         .set_wptr = gfx_v10_0_ring_set_wptr_gfx,
5166         .emit_frame_size = /* totally 242 maximum if 16 IBs */
5167                 5 + /* COND_EXEC */
5168                 7 + /* PIPELINE_SYNC */
5169                 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 +
5170                 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 +
5171                 2 + /* VM_FLUSH */
5172                 8 + /* FENCE for VM_FLUSH */
5173                 20 + /* GDS switch */
5174                 4 + /* double SWITCH_BUFFER,
5175                      * the first COND_EXEC jump to the place
5176                      * just prior to this double SWITCH_BUFFER
5177                      */
5178                 5 + /* COND_EXEC */
5179                 7 + /* HDP_flush */
5180                 4 + /* VGT_flush */
5181                 14 + /* CE_META */
5182                 31 + /* DE_META */
5183                 3 + /* CNTX_CTRL */
5184                 5 + /* HDP_INVL */
5185                 8 + 8 + /* FENCE x2 */
5186                 2, /* SWITCH_BUFFER */
5187         .emit_ib_size = 4, /* gfx_v10_0_ring_emit_ib_gfx */
5188         .emit_ib = gfx_v10_0_ring_emit_ib_gfx,
5189         .emit_fence = gfx_v10_0_ring_emit_fence,
5190         .emit_pipeline_sync = gfx_v10_0_ring_emit_pipeline_sync,
5191         .emit_vm_flush = gfx_v10_0_ring_emit_vm_flush,
5192         .emit_gds_switch = gfx_v10_0_ring_emit_gds_switch,
5193         .emit_hdp_flush = gfx_v10_0_ring_emit_hdp_flush,
5194         .test_ring = gfx_v10_0_ring_test_ring,
5195         .test_ib = gfx_v10_0_ring_test_ib,
5196         .insert_nop = amdgpu_ring_insert_nop,
5197         .pad_ib = amdgpu_ring_generic_pad_ib,
5198         .emit_switch_buffer = gfx_v10_0_ring_emit_sb,
5199         .emit_cntxcntl = gfx_v10_0_ring_emit_cntxcntl,
5200         .init_cond_exec = gfx_v10_0_ring_emit_init_cond_exec,
5201         .patch_cond_exec = gfx_v10_0_ring_emit_patch_cond_exec,
5202         .preempt_ib = gfx_v10_0_ring_preempt_ib,
5203         .emit_tmz = gfx_v10_0_ring_emit_tmz,
5204         .emit_wreg = gfx_v10_0_ring_emit_wreg,
5205         .emit_reg_wait = gfx_v10_0_ring_emit_reg_wait,
5206         .emit_reg_write_reg_wait = gfx_v10_0_ring_emit_reg_write_reg_wait,
5207 };
5208
5209 static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_compute = {
5210         .type = AMDGPU_RING_TYPE_COMPUTE,
5211         .align_mask = 0xff,
5212         .nop = PACKET3(PACKET3_NOP, 0x3FFF),
5213         .support_64bit_ptrs = true,
5214         .vmhub = AMDGPU_GFXHUB_0,
5215         .get_rptr = gfx_v10_0_ring_get_rptr_compute,
5216         .get_wptr = gfx_v10_0_ring_get_wptr_compute,
5217         .set_wptr = gfx_v10_0_ring_set_wptr_compute,
5218         .emit_frame_size =
5219                 20 + /* gfx_v10_0_ring_emit_gds_switch */
5220                 7 + /* gfx_v10_0_ring_emit_hdp_flush */
5221                 5 + /* hdp invalidate */
5222                 7 + /* gfx_v10_0_ring_emit_pipeline_sync */
5223                 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 +
5224                 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 +
5225                 2 + /* gfx_v10_0_ring_emit_vm_flush */
5226                 8 + 8 + 8, /* gfx_v10_0_ring_emit_fence x3 for user fence, vm fence */
5227         .emit_ib_size = 7, /* gfx_v10_0_ring_emit_ib_compute */
5228         .emit_ib = gfx_v10_0_ring_emit_ib_compute,
5229         .emit_fence = gfx_v10_0_ring_emit_fence,
5230         .emit_pipeline_sync = gfx_v10_0_ring_emit_pipeline_sync,
5231         .emit_vm_flush = gfx_v10_0_ring_emit_vm_flush,
5232         .emit_gds_switch = gfx_v10_0_ring_emit_gds_switch,
5233         .emit_hdp_flush = gfx_v10_0_ring_emit_hdp_flush,
5234         .test_ring = gfx_v10_0_ring_test_ring,
5235         .test_ib = gfx_v10_0_ring_test_ib,
5236         .insert_nop = amdgpu_ring_insert_nop,
5237         .pad_ib = amdgpu_ring_generic_pad_ib,
5238         .emit_wreg = gfx_v10_0_ring_emit_wreg,
5239         .emit_reg_wait = gfx_v10_0_ring_emit_reg_wait,
5240         .emit_reg_write_reg_wait = gfx_v10_0_ring_emit_reg_write_reg_wait,
5241 };
5242
5243 static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_kiq = {
5244         .type = AMDGPU_RING_TYPE_KIQ,
5245         .align_mask = 0xff,
5246         .nop = PACKET3(PACKET3_NOP, 0x3FFF),
5247         .support_64bit_ptrs = true,
5248         .vmhub = AMDGPU_GFXHUB_0,
5249         .get_rptr = gfx_v10_0_ring_get_rptr_compute,
5250         .get_wptr = gfx_v10_0_ring_get_wptr_compute,
5251         .set_wptr = gfx_v10_0_ring_set_wptr_compute,
5252         .emit_frame_size =
5253                 20 + /* gfx_v10_0_ring_emit_gds_switch */
5254                 7 + /* gfx_v10_0_ring_emit_hdp_flush */
5255                 5 + /*hdp invalidate */
5256                 7 + /* gfx_v10_0_ring_emit_pipeline_sync */
5257                 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 +
5258                 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 +
5259                 2 + /* gfx_v10_0_ring_emit_vm_flush */
5260                 8 + 8 + 8, /* gfx_v10_0_ring_emit_fence_kiq x3 for user fence, vm fence */
5261         .emit_ib_size = 7, /* gfx_v10_0_ring_emit_ib_compute */
5262         .emit_ib = gfx_v10_0_ring_emit_ib_compute,
5263         .emit_fence = gfx_v10_0_ring_emit_fence_kiq,
5264         .test_ring = gfx_v10_0_ring_test_ring,
5265         .test_ib = gfx_v10_0_ring_test_ib,
5266         .insert_nop = amdgpu_ring_insert_nop,
5267         .pad_ib = amdgpu_ring_generic_pad_ib,
5268         .emit_rreg = gfx_v10_0_ring_emit_rreg,
5269         .emit_wreg = gfx_v10_0_ring_emit_wreg,
5270         .emit_reg_wait = gfx_v10_0_ring_emit_reg_wait,
5271         .emit_reg_write_reg_wait = gfx_v10_0_ring_emit_reg_write_reg_wait,
5272 };
5273
5274 static void gfx_v10_0_set_ring_funcs(struct amdgpu_device *adev)
5275 {
5276         int i;
5277
5278         adev->gfx.kiq.ring.funcs = &gfx_v10_0_ring_funcs_kiq;
5279
5280         for (i = 0; i < adev->gfx.num_gfx_rings; i++)
5281                 adev->gfx.gfx_ring[i].funcs = &gfx_v10_0_ring_funcs_gfx;
5282
5283         for (i = 0; i < adev->gfx.num_compute_rings; i++)
5284                 adev->gfx.compute_ring[i].funcs = &gfx_v10_0_ring_funcs_compute;
5285 }
5286
5287 static const struct amdgpu_irq_src_funcs gfx_v10_0_eop_irq_funcs = {
5288         .set = gfx_v10_0_set_eop_interrupt_state,
5289         .process = gfx_v10_0_eop_irq,
5290 };
5291
5292 static const struct amdgpu_irq_src_funcs gfx_v10_0_priv_reg_irq_funcs = {
5293         .set = gfx_v10_0_set_priv_reg_fault_state,
5294         .process = gfx_v10_0_priv_reg_irq,
5295 };
5296
5297 static const struct amdgpu_irq_src_funcs gfx_v10_0_priv_inst_irq_funcs = {
5298         .set = gfx_v10_0_set_priv_inst_fault_state,
5299         .process = gfx_v10_0_priv_inst_irq,
5300 };
5301
5302 static const struct amdgpu_irq_src_funcs gfx_v10_0_kiq_irq_funcs = {
5303         .set = gfx_v10_0_kiq_set_interrupt_state,
5304         .process = gfx_v10_0_kiq_irq,
5305 };
5306
5307 static void gfx_v10_0_set_irq_funcs(struct amdgpu_device *adev)
5308 {
5309         adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST;
5310         adev->gfx.eop_irq.funcs = &gfx_v10_0_eop_irq_funcs;
5311
5312         adev->gfx.kiq.irq.num_types = AMDGPU_CP_KIQ_IRQ_LAST;
5313         adev->gfx.kiq.irq.funcs = &gfx_v10_0_kiq_irq_funcs;
5314
5315         adev->gfx.priv_reg_irq.num_types = 1;
5316         adev->gfx.priv_reg_irq.funcs = &gfx_v10_0_priv_reg_irq_funcs;
5317
5318         adev->gfx.priv_inst_irq.num_types = 1;
5319         adev->gfx.priv_inst_irq.funcs = &gfx_v10_0_priv_inst_irq_funcs;
5320 }
5321
5322 static void gfx_v10_0_set_rlc_funcs(struct amdgpu_device *adev)
5323 {
5324         switch (adev->asic_type) {
5325         case CHIP_NAVI10:
5326         case CHIP_NAVI14:
5327         case CHIP_NAVI12:
5328                 adev->gfx.rlc.funcs = &gfx_v10_0_rlc_funcs;
5329                 break;
5330         default:
5331                 break;
5332         }
5333 }
5334
5335 static void gfx_v10_0_set_gds_init(struct amdgpu_device *adev)
5336 {
5337         unsigned total_cu = adev->gfx.config.max_cu_per_sh *
5338                             adev->gfx.config.max_sh_per_se *
5339                             adev->gfx.config.max_shader_engines;
5340
5341         adev->gds.gds_size = 0x10000;
5342         adev->gds.gds_compute_max_wave_id = total_cu * 32 - 1;
5343         adev->gds.gws_size = 64;
5344         adev->gds.oa_size = 16;
5345 }
5346
5347 static void gfx_v10_0_set_user_wgp_inactive_bitmap_per_sh(struct amdgpu_device *adev,
5348                                                           u32 bitmap)
5349 {
5350         u32 data;
5351
5352         if (!bitmap)
5353                 return;
5354
5355         data = bitmap << GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT;
5356         data &= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK;
5357
5358         WREG32_SOC15(GC, 0, mmGC_USER_SHADER_ARRAY_CONFIG, data);
5359 }
5360
5361 static u32 gfx_v10_0_get_wgp_active_bitmap_per_sh(struct amdgpu_device *adev)
5362 {
5363         u32 data, wgp_bitmask;
5364         data = RREG32_SOC15(GC, 0, mmCC_GC_SHADER_ARRAY_CONFIG);
5365         data |= RREG32_SOC15(GC, 0, mmGC_USER_SHADER_ARRAY_CONFIG);
5366
5367         data &= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK;
5368         data >>= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT;
5369
5370         wgp_bitmask =
5371                 amdgpu_gfx_create_bitmask(adev->gfx.config.max_cu_per_sh >> 1);
5372
5373         return (~data) & wgp_bitmask;
5374 }
5375
5376 static u32 gfx_v10_0_get_cu_active_bitmap_per_sh(struct amdgpu_device *adev)
5377 {
5378         u32 wgp_idx, wgp_active_bitmap;
5379         u32 cu_bitmap_per_wgp, cu_active_bitmap;
5380
5381         wgp_active_bitmap = gfx_v10_0_get_wgp_active_bitmap_per_sh(adev);
5382         cu_active_bitmap = 0;
5383
5384         for (wgp_idx = 0; wgp_idx < 16; wgp_idx++) {
5385                 /* if there is one WGP enabled, it means 2 CUs will be enabled */
5386                 cu_bitmap_per_wgp = 3 << (2 * wgp_idx);
5387                 if (wgp_active_bitmap & (1 << wgp_idx))
5388                         cu_active_bitmap |= cu_bitmap_per_wgp;
5389         }
5390
5391         return cu_active_bitmap;
5392 }
5393
5394 static int gfx_v10_0_get_cu_info(struct amdgpu_device *adev,
5395                                  struct amdgpu_cu_info *cu_info)
5396 {
5397         int i, j, k, counter, active_cu_number = 0;
5398         u32 mask, bitmap, ao_bitmap, ao_cu_mask = 0;
5399         unsigned disable_masks[4 * 2];
5400
5401         if (!adev || !cu_info)
5402                 return -EINVAL;
5403
5404         amdgpu_gfx_parse_disable_cu(disable_masks, 4, 2);
5405
5406         mutex_lock(&adev->grbm_idx_mutex);
5407         for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
5408                 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
5409                         mask = 1;
5410                         ao_bitmap = 0;
5411                         counter = 0;
5412                         gfx_v10_0_select_se_sh(adev, i, j, 0xffffffff);
5413                         if (i < 4 && j < 2)
5414                                 gfx_v10_0_set_user_wgp_inactive_bitmap_per_sh(
5415                                         adev, disable_masks[i * 2 + j]);
5416                         bitmap = gfx_v10_0_get_cu_active_bitmap_per_sh(adev);
5417                         cu_info->bitmap[i][j] = bitmap;
5418
5419                         for (k = 0; k < adev->gfx.config.max_cu_per_sh; k++) {
5420                                 if (bitmap & mask) {
5421                                         if (counter < adev->gfx.config.max_cu_per_sh)
5422                                                 ao_bitmap |= mask;
5423                                         counter++;
5424                                 }
5425                                 mask <<= 1;
5426                         }
5427                         active_cu_number += counter;
5428                         if (i < 2 && j < 2)
5429                                 ao_cu_mask |= (ao_bitmap << (i * 16 + j * 8));
5430                         cu_info->ao_cu_bitmap[i][j] = ao_bitmap;
5431                 }
5432         }
5433         gfx_v10_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
5434         mutex_unlock(&adev->grbm_idx_mutex);
5435
5436         cu_info->number = active_cu_number;
5437         cu_info->ao_cu_mask = ao_cu_mask;
5438         cu_info->simd_per_cu = NUM_SIMD_PER_CU;
5439
5440         return 0;
5441 }
5442
5443 const struct amdgpu_ip_block_version gfx_v10_0_ip_block =
5444 {
5445         .type = AMD_IP_BLOCK_TYPE_GFX,
5446         .major = 10,
5447         .minor = 0,
5448         .rev = 0,
5449         .funcs = &gfx_v10_0_ip_funcs,
5450 };